more testbench code
This commit is contained in:
Markus Fröschle
@@ -47,47 +47,47 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity DDR_CTRL_V1 is
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port(
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CLK_MAIN : in std_logic;
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DDR_SYNC_66M : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CS1n : in std_logic;
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FB_OEn : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_ALE : in std_logic;
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FB_WRn : in std_logic;
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FIFO_CLR : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ADR : in std_logic_vector(31 downto 0);
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BLITTER_SIG : in std_logic;
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BLITTER_WR : in std_logic;
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DDRCLK0 : in std_logic;
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CLK_33M : in std_logic;
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FIFO_MW : in std_logic_vector(8 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VWEn : out std_logic;
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VRASn : out std_logic;
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VCSn : out std_logic;
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VCKE : out std_logic;
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VCASn : out std_logic;
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FB_LE : out std_logic_vector(3 downto 0);
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FB_VDOE : out std_logic_vector(3 downto 0);
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SR_FIFO_WRE : out std_logic;
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SR_DDR_FB : out std_logic;
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SR_DDR_WR : out std_logic;
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SR_DDRWR_D_SEL : out std_logic;
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SR_VDMP : out std_logic_vector(7 downto 0);
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VIDEO_DDR_TA : out std_logic;
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SR_BLITTER_DACK : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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DDRWR_D_SEL1 : out std_logic;
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VDM_SEL : out std_logic_vector(3 downto 0);
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DATA_IN : in std_logic_vector(31 downto 0);
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DATA_OUT : out std_logic_vector(31 downto 16);
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DATA_EN_H : out std_logic;
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DATA_EN_L : out std_logic
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);
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port(
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CLK_MAIN : in std_logic;
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DDR_SYNC_66M : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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FB_CS1n : in std_logic;
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FB_OEn : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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FB_ALE : in std_logic;
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FB_WRn : in std_logic;
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FIFO_CLR : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ADR : in std_logic_vector(31 downto 0);
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BLITTER_SIG : in std_logic;
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BLITTER_WR : in std_logic;
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DDRCLK0 : in std_logic;
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CLK_33M : in std_logic;
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FIFO_MW : in std_logic_vector(8 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VWEn : out std_logic;
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VRASn : out std_logic;
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VCSn : out std_logic;
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VCKE : out std_logic;
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VCASn : out std_logic;
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FB_LE : out std_logic_vector(3 downto 0);
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FB_VDOE : out std_logic_vector(3 downto 0);
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SR_FIFO_WRE : out std_logic;
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SR_DDR_FB : out std_logic;
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SR_DDR_WR : out std_logic;
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SR_DDRWR_D_SEL : out std_logic;
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SR_VDMP : out std_logic_vector(7 downto 0);
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VIDEO_DDR_TA : out std_logic;
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SR_BLITTER_DACK : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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DDRWR_D_SEL1 : out std_logic;
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VDM_SEL : out std_logic_vector(3 downto 0);
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DATA_IN : in std_logic_vector(31 downto 0);
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DATA_OUT : out std_logic_vector(31 downto 16);
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DATA_EN_H : out std_logic;
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DATA_EN_L : out std_logic
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);
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end entity DDR_CTRL_V1;
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architecture BEHAVIOUR of DDR_CTRL_V1 is
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@@ -96,16 +96,16 @@ architecture BEHAVIOUR of DDR_CTRL_V1 is
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constant FIFO_MWM : std_logic_vector(8 downto 0) := "011001000"; -- 200.
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constant FIFO_HWM : std_logic_vector(8 downto 0) := "111110100"; -- 500.
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type ACCESS_WIDTH_TYPE is(LONG, WORD, BYTE);
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type DDR_ACCESS_TYPE is(CPU, FIFO, BLITTER, NONE);
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type FB_REGDDR_TYPE is(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
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type DDR_SM_TYPE is(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- Start (normal 8 cycles total = 60ns).
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DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- Configuration.
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DS_T4R, DS_T5R, -- Read CPU or BLITTER.
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DS_T4W, DS_T5W, DS_T6W, DS_T7W, DS_T8W, DS_T9W, -- Write CPU or BLITTER.
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DS_T4F, DS_T5F, DS_T6F, DS_T7F, DS_T8F, DS_T9F, DS_T10F, -- Read FIFO.
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DS_CB6, DS_CB8, -- Close FIFO bank.
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DS_R2, DS_R3, DS_R4, DS_R5, DS_R6); -- Refresh: 10 x 7.5ns = 75ns.
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type ACCESS_WIDTH_TYPE is (LONG, WORD, BYTE);
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type DDR_ACCESS_TYPE is (CPU, FIFO, BLITTER, NONE);
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type FB_REGDDR_TYPE is (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3);
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type DDR_SM_TYPE is (DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- Start (normal 8 cycles total = 60ns).
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DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- Configuration.
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DS_T4R, DS_T5R, -- Read CPU or BLITTER.
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DS_T4W, DS_T5W, DS_T6W, DS_T7W, DS_T8W, DS_T9W, -- Write CPU or BLITTER.
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DS_T4F, DS_T5F, DS_T6F, DS_T7F, DS_T8F, DS_T9F, DS_T10F, -- Read FIFO.
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DS_CB6, DS_CB8, -- Close FIFO bank.
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DS_R2, DS_R3, DS_R4, DS_R5, DS_R6); -- Refresh: 10 x 7.5ns = 75ns.
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signal ACCESS_WIDTH : ACCESS_WIDTH_TYPE;
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signal FB_REGDDR : FB_REGDDR_TYPE;
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@@ -178,33 +178,33 @@ begin
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WORD when "00",
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BYTE when others;
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-- Byte selectors:
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BYTE_SEL(0) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when FB_ADR(1 downto 0) = "00" else '0'; -- Byte 0.
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-- Byte selectors:
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BYTE_SEL(0) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when FB_ADR(1 downto 0) = "00" else '0'; -- Byte 0.
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BYTE_SEL(1) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '0' else -- High word.
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'1' when FB_ADR(1 downto 0) = "01" else '0'; -- Byte 1.
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BYTE_SEL(1) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '0' else -- High word.
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'1' when FB_ADR(1 downto 0) = "01" else '0'; -- Byte 1.
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BYTE_SEL(2) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when FB_ADR(1 downto 0) = "10" else '0'; -- Byte 2.
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BYTE_SEL(2) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when FB_ADR(1 downto 0) = "10" else '0'; -- Byte 2.
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BYTE_SEL(3) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '1' else -- Low word.
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'1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3.
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BYTE_SEL(3) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else
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'1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '1' else -- Low word.
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'1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) ---------------------------------------------------------------------
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FBCTRL_REG: process
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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FB_REGDDR <= FB_REGDDR_NEXT;
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end process FBCTRL_REG;
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) ---------------------------------------------------------------------
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FBCTRL_REG: process
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begin
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wait until CLK_MAIN = '1' and CLK_MAIN' event;
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FB_REGDDR <= FB_REGDDR_NEXT;
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end process FBCTRL_REG;
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FBCTRL_DEC: process(FB_REGDDR, BUS_CYC, DDR_SEL, ACCESS_WIDTH, FB_WRn, DDR_CS)
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begin
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case FB_REGDDR is
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when FR_WAIT =>
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FBCTRL_DEC: process(FB_REGDDR, BUS_CYC, DDR_SEL, ACCESS_WIDTH, FB_WRn, DDR_CS)
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begin
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case FB_REGDDR is
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when FR_WAIT =>
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if BUS_CYC = '1' then
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FB_REGDDR_NEXT <= FR_S0;
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elsif DDR_SEL = '1' and ACCESS_WIDTH = LONG and FB_WRn = '0' then
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