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test using ACR0 & ACR2 to provide supervisor stack access

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Markus Fröschle
2014-01-15 16:03:54 +00:00
parent 64127d5d2f
commit 90a4b60289
1 changed files with 31 additions and 1 deletions
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30
BaS_gcc/sys/mmu.c
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@@ -196,7 +196,35 @@ void mmu_init(void)
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
/*
* need to set data ACRs in a way that supervisor access to all memory regions
* becomes possible. Otherways it might be that the supervisor stack ends up in an unmapped
* region when further MMU TLB entries force a page steal. This would lead to a double
* fault since the CPU wouldn't be able to push its exception stack frame during an access
* exception
*/
/* set data access attributes in ACR0 and ACR1 */ /* set data access attributes in ACR0 and ACR1 */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(0) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHEABLE_WT) | /* cacheable, write through */
ACR_AMM(1) | /* region 13 MByte */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */
ACR_E(1) | /* enable ACR */
ACR_ADMSK(0x0c) | /* cover 13 MByte from 0x0 */
ACR_BA(0)); /* start from 0x0 */
set_acr1(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(0) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHEABLE_WT) | /* cacheable, write through */
ACR_AMM(0) | /* region > 16 MByte */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* memory only visible from supervisor mode */
ACR_E(1) | /* enable ACR */
ACR_ADMSK(0x1f) | /* cover 495 MByte from 0x0f00000 */
ACR_BA(0x0f)); /* start from 0xf000000 */
#ifdef _NOT_USED_
set_acr0(ACR_W(0) | /* read and write accesses permitted */ set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(0) | /* supervisor and user mode access permitted */ ACR_SP(0) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
@@ -226,6 +254,8 @@ void mmu_init(void)
ACR_ADMSK(0x1f) | ACR_ADMSK(0x1f) |
ACR_BA(0x60000000)); ACR_BA(0x60000000));
#endif /* _NOT_USED_ */
/* set instruction access attributes in ACR2 and ACR3 */ /* set instruction access attributes in ACR2 and ACR3 */
//set_acr2(0xe007c400); //set_acr2(0xe007c400);