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finished ELF toolchain integration

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This commit is contained in:
Markus Fröschle
2012-10-30 20:26:43 +00:00
parent a21322541d
commit 8f26c2a99a
2 changed files with 13 additions and 9 deletions
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7
BaS_GNU/BaS_GNU/sources/startcf.S
View File

@@ -1,15 +1,16 @@
.equ MCF_MMU_MMUCR, __MMUBAR + 0 .equ MCF_MMU_MMUCR, __MMUBAR + 0
.global _startup
_startup:
.extern _initialize_hardware .extern _initialize_hardware
.extern _rt_mbar .extern _rt_mbar
_startup:
bra.s warmstart bra.s warmstart
jmp ___BOOT_FLASH + 8 /* that's also our reset vector */ jmp ___BOOT_FLASH + 8 /* that's also our reset vector */
/* disable interrupts */ /* disable interrupts */
warmstart: warmstart:
move.w #0x2700,sr move.w #0x2700,SR
/* Initialize MBAR */ /* Initialize MBAR */
@@ -25,7 +26,7 @@ warmstart:
move.l d0,MCF_MMU_MMUCR move.l d0,MCF_MMU_MMUCR
/* Initialize RAMBARs: locate SRAM and validate it */ /* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */ move.l #__RAMBAR0 + 0x7,%d0 /* supervisor only */
movec d0,RAMBAR0 movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0 move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1 movec d0,RAMBAR1

13
BaS_GNU/BaS_GNU/sources/sysinit.c
View File

@@ -77,7 +77,7 @@ void init_slt(void)
{ {
xprintf("slice timer initialization: "); xprintf("slice timer initialization: ");
MCF_SLT0_STCNT = 0xffffffff; MCF_SLT0_STCNT = 0xffffffff;
MCF_SLT0_SCR = 0x05000000; MCF_SLT0_SCR = MCF_SLT_SCR_TEN | MCF_SLT_SCR_IEN | MCF_SLT_SCR_RUN; /* enable and run continuously */
xprintf("finished\r\n"); xprintf("finished\r\n");
} }
@@ -283,7 +283,7 @@ void init_ddram(void)
} }
/* /*
* init FB_CSx * initialize FlexBus chip select registers
*/ */
void init_fbcs() void init_fbcs()
{ {
@@ -291,8 +291,11 @@ void init_fbcs()
/* Flash */ /* Flash */
MCF_FBCS0_CSAR = 0xE0000000; /* flash base address */ MCF_FBCS0_CSAR = 0xE0000000; /* flash base address */
MCF_FBCS0_CSCR = 0x00001180; /* 16 bit 4ws aa */ MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 |
MCF_FBCS0_CSMR = 0x007F0001; /* 8MB on */ MCF_FBCS_CSCR_WS(4)|
MCF_FBCS_CSCR_AA;
MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM_8M |
MCF_FBCS_CSMR_V; /* 8 MByte on */
MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */ MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
@@ -317,7 +320,7 @@ void init_fbcs()
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_4M // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V; | MCF_FBCS_CSMR_V;
xprintf("finished\r\n"); xprintf("finished\r\n");