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added to the DDR RAM model

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reformatted (converted tabs to spaces)
This commit is contained in:
Markus Fröschle
2014-12-25 15:20:14 +00:00
parent a7eb46e158
commit 8706322f96
2 changed files with 136 additions and 71 deletions
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136
vhdl/rtl/vhdl/WF5380/wf5380_soc_top.vhd
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@@ -43,64 +43,64 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity WF5380_TOP_SOC is entity WF5380_TOP_SOC is
port ( port (
-- System controls: -- System controls:
CLK : in std_logic; -- Use a 16MHz Clock. CLK : in std_logic; -- Use a 16MHz Clock.
RESETn : in std_logic; RESETn : in std_logic;
-- Address and data: -- Address and data:
ADR : in std_logic_vector(2 downto 0); ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0); DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0); DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic; DATA_EN : out std_logic;
-- Bus and DMA controls: -- Bus and DMA controls:
CSn : in std_logic; CSn : in std_logic;
RDn : in std_logic; RDn : in std_logic;
WRn : in std_logic; WRn : in std_logic;
EOPn : in std_logic; EOPn : in std_logic;
DACKn : in std_logic; DACKn : in std_logic;
DRQ : out std_logic; DRQ : out std_logic;
INT : out std_logic; INT : out std_logic;
READY : out std_logic; READY : out std_logic;
-- SCSI bus: -- SCSI bus:
DB_INn : in std_logic_vector(7 downto 0); DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0); DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic; DB_EN : out std_logic;
DBP_INn : in std_logic; DBP_INn : in std_logic;
DBP_OUTn : out std_logic; DBP_OUTn : out std_logic;
DBP_EN : out std_logic; DBP_EN : out std_logic;
RST_INn : in std_logic; RST_INn : in std_logic;
RST_OUTn : out std_logic; RST_OUTn : out std_logic;
RST_EN : out std_logic; RST_EN : out std_logic;
BSY_INn : in std_logic; BSY_INn : in std_logic;
BSY_OUTn : out std_logic; BSY_OUTn : out std_logic;
BSY_EN : out std_logic; BSY_EN : out std_logic;
SEL_INn : in std_logic; SEL_INn : in std_logic;
SEL_OUTn : out std_logic; SEL_OUTn : out std_logic;
SEL_EN : out std_logic; SEL_EN : out std_logic;
ACK_INn : in std_logic; ACK_INn : in std_logic;
ACK_OUTn : out std_logic; ACK_OUTn : out std_logic;
ACK_EN : out std_logic; ACK_EN : out std_logic;
ATN_INn : in std_logic; ATN_INn : in std_logic;
ATN_OUTn : out std_logic; ATN_OUTn : out std_logic;
ATN_EN : out std_logic; ATN_EN : out std_logic;
REQ_INn : in std_logic; REQ_INn : in std_logic;
REQ_OUTn : out std_logic; REQ_OUTn : out std_logic;
REQ_EN : out std_logic; REQ_EN : out std_logic;
IOn_IN : in std_logic; IOn_IN : in std_logic;
IOn_OUT : out std_logic; IOn_OUT : out std_logic;
IO_EN : out std_logic; IO_EN : out std_logic;
CDn_IN : in std_logic; CDn_IN : in std_logic;
CDn_OUT : out std_logic; CDn_OUT : out std_logic;
CD_EN : out std_logic; CD_EN : out std_logic;
MSG_INn : in std_logic; MSG_INn : in std_logic;
MSG_OUTn : out std_logic; MSG_OUTn : out std_logic;
MSG_EN : out std_logic MSG_EN : out std_logic
); );
end entity WF5380_TOP_SOC; end entity WF5380_TOP_SOC;
architecture STRUCTURE of WF5380_TOP_SOC is architecture STRUCTURE of WF5380_TOP_SOC is
signal ACK_OUT_CTRLn : std_logic; signal ACK_OUT_CTRLn : std_logic;
signal AIP : std_logic; signal AIP : std_logic;
@@ -198,16 +198,16 @@ begin
I_REGISTERS: WF5380_REGISTERS I_REGISTERS: WF5380_REGISTERS
port map( port map(
CLK => CLK, CLK => CLK,
RESETn => RESETn, RESETn => RESETn,
ADR => ADR, ADR => ADR,
DATA_IN => DATA_IN, DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT, DATA_OUT => DATA_OUT,
DATA_EN => DATA_EN, DATA_EN => DATA_EN,
CSn => CSn, CSn => CSn,
RDn => RDn, RDn => RDn,
WRn => WRn, WRn => WRn,
RSTn => RST_INn, RSTn => RST_INn,
RST => RST, RST => RST,
ARB_EN => ARB_EN, ARB_EN => ARB_EN,
DMA_ACTIVE => DMA_ACTIVE, DMA_ACTIVE => DMA_ACTIVE,
@@ -240,15 +240,15 @@ begin
I_CONTROL: WF5380_CONTROL I_CONTROL: WF5380_CONTROL
port map( port map(
CLK => CLK, CLK => CLK,
RESETn => RESETn, RESETn => RESETn,
BSY_INn => BSY_INn, BSY_INn => BSY_INn,
BSY_OUTn => BSY_OUT_CTRLn, BSY_OUTn => BSY_OUT_CTRLn,
DATA_EN => DATA_EN_CTRL, DATA_EN => DATA_EN_CTRL,
SEL_INn => SEL_INn, SEL_INn => SEL_INn,
ARB_EN => ARB_EN, ARB_EN => ARB_EN,
BSY_DISn => BSY_DISn, BSY_DISn => BSY_DISn,
RSTn => RST_INn, RSTn => RST_INn,
ARB => ARB, ARB => ARB,
AIP => AIP, AIP => AIP,
LA => LA, LA => LA,

71
vhdl/testbenches/ddr_ram_model.vhd
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@@ -135,11 +135,76 @@ ARCHITECTURE rtl OF ddr_ram_model IS
CONSTANT TBITS : INTEGER := 512 * M1; CONSTANT TBITS : INTEGER := 512 * M1;
--SIGNAL BITs : UNSIGNED (B - 1 DOWNTO 0); --SIGNAL BITs : UNSIGNED (B - 1 DOWNTO 0);
SIGNAL BIT_C : UNSIGNED (NCOL - 1 DOWNTO 0); CONSTANT BIT_C : INTEGER := NCOL - 1;
CONSTANT NWORD : INTEGER := TBITS / B / NBANK; CONSTANT NWORD : INTEGER := TBITS / B / NBANK;
SIGNAL BIT_T : UNSIGNED (NCOL + ADDRTOP DOWNTO 0); CONSTANT BIT_T : INTEGER := NCOL + ADDRTOP;
SIGNAL WORD : UNSIGNED (NWORD - 1 DOWNTO 0); CONSTANT WORD : INTEGER := NWORD - 1;
CONSTANT HB : INTEGER := B / 2; CONSTANT HB : INTEGER := B / 2;
CONSTANT PWRUP_TIME : INTEGER := 0;
CONSTANT PWUP_CHECK : STD_LOGIC := '1';
CONSTANT INITIAL : INTEGER := 0;
CONSTANT HIGH : INTEGER := 1;
CONSTANT LOW : INTEGER := 0;
SIGNAL addr : STD_LOGIC_VECTOR (NBANK / 2 + ADDRTOP DOWNTO 0);
TYPE mem_array_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(B - 1 DOWNTO 0);
SIGNAL mem_a : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of a bank
SIGNAL mem_b : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of b bank
SIGNAL mem_c : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of c bank
SIGNAL mem_d : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of d bank
SIGNAL t_dqi : UNSIGNED (B - 1 DOWNTO 0);
SIGNAL dqsi : UNSIGNED (NDQS - 1 DOWNTO 0);
SIGNAL dqsi_n : UNSIGNED (NDQS - 1 DOWNTO 0);
SIGNAL dqo : UNSIGNED (B - 1 DOWNTO 0); -- output temp register declaration
SIGNAL t_tqo : UNSIGNED (B - 1 DOWNTO 0);
TYPE r_addr_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (NBANK - 1 DOWNTO 0);
SIGNAL r_addr_n : r_addr_t (ADDRTOP DOWNTO 0);
SIGNAL r_addr : UNSIGNED (ADDRTOP DOWNTO 0);
SIGNAL c_addr : UNSIGNED (BIT_C DOWNTO 0);
SIGNAL c_addr_delay : UNSIGNED (BIT_C DOWNTO 0);
SIGNAL c_addr_delay_bf : UNSIGNED (BIT_C DOWNTO 0);
SIGNAL m_addr : UNSIGNED (BIT_T DOWNTO 0); -- merge row and column address
SIGNAL m1_addr : UNSIGNED (BIT_T DOWNTO 0); -- merge row and column address pseudo
TYPE d_reg_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (PAGEDEPTH DOWNTO 0);
SIGNAL dout_reg : UNSIGNED (B - 1 DOWNTO 0);
SIGNAL din_reg : UNSIGNED (B - 1 DOWNTO 0);
SIGNAL clk_dq : UNSIGNED (B - 1 DOWNTO 0);
SIGNAL ptr : STD_LOGIC;
SIGNAL zdata : UNSIGNED(B - 1 DOWNTO 0);
SIGNAL zbyte : UNSIGNED(7 DOWNTO 0);
-- we know the phase of external signal by examining the state of its flag
SIGNAL r_bank_addr : STD_LOGIC;
SIGNAL c_bank_addr : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
SIGNAL c_bank_addr_delay : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
SIGNAL c_bank_addr_delay_bf : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag
SIGNAL prech_reg : UNSIGNED (NBANK / 2 DOWNTO 0); -- precharge mode (addr (13 DOWNTO 12) AND (addr(10))
SIGNAL auto_flag : UNSIGNED (NBANK - 1 DOWNTO 0);
SIGNAL burst_type : STD_LOGIC; -- burst type flag
SIGNAL auto_flagx : STD_LOGIC; -- auto refresh flag
SIGNAL self_flag : STD_LOGIC; -- self refresh flag
SIGNAL kill_bank : INTEGER;
SIGNAL k : INTEGER;
SIGNAL precharge_flag : UNSIGNED (NBANK - 1 DOWNTO 0); -- precharge bank check flag
SIGNAL autoprech_reg : UNSIGNED (1 DOWNTO 0);
SIGNAL pwrup_done : STD_LOGIC;
SIGNAL first_pre : UNSIGNED (NBANK - 1 DOWNTO 0);
SIGNAL auto_cnt : INTEGER;
SIGNAL i : INTEGER;
SIGNAL rfu : UNSIGNED (6 DOWNTO 0);
BEGIN BEGIN
addr <= STD_LOGIC_VECTOR(ba) & ad;
rfu <= UNSIGNED(addr(14 DOWNTO 9)) & UNSIGNED(addr(7 DOWNTO 7));
END rtl; END rtl;