diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf
index aa997ce..3737578 100755
--- a/vhdl/backend/Altera/Firebee/firebee.qsf
+++ b/vhdl/backend/Altera/Firebee/firebee.qsf
@@ -689,4 +689,5 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[2]
 set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3]
 set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
 set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/vhdl/rtl/vhdl/io_register.vhd b/vhdl/rtl/vhdl/io_register.vhd
new file mode 100644
index 0000000..318f937
--- /dev/null
+++ b/vhdl/rtl/vhdl/io_register.vhd
@@ -0,0 +1,47 @@
+LIBRARY IEEE;
+    USE IEEE.std_logic_1164.ALL;
+    USE IEEE.numeric_std.ALL;
+
+PACKAGE io_register_pkg IS
+    TYPE access_width_t IS (LONGWORD, WORD, BYTE);
+    
+    COMPONENT io_register IS
+    /*
+        GENERIC
+        (
+            NULL
+        );
+    */
+        PORT
+        (
+            adress          : IN UNSIGNED (31 DOWNTO 0);
+            address_mask    : IN UNSIGNED (31 DOWNTO 0);
+            access_type     : IN access_width_t
+            
+        );
+    END COMPONENT;
+END PACKAGE;
+
+----------------------------------------------------------------------------------------------------------------------------------------
+LIBRARY IEEE;
+    USE IEEE.std_logic_1164.ALL;
+    USE IEEE.numeric_std.ALL;
+
+ENTITY io_register IS
+/*
+    GENERIC
+    (
+        NULL
+    );
+*/
+    PORT
+    (
+        adress          : IN UNSIGNED (31 DOWNTO 0);
+        address_mask    : IN UNSIGNED (31 DOWNTO 0);
+        access_type     : IN access_width_t
+    );
+END ENTITY io_register;
+
+ARCHITECTURE rtl OF io_register IS
+BEGIN
+END rtl;
\ No newline at end of file
diff --git a/vhdl/testbenches/ddr2_ram_model.vhd b/vhdl/testbenches/ddr2_ram_model.vhd
index 08f473f..d2cbfff 100644
--- a/vhdl/testbenches/ddr2_ram_model.vhd
+++ b/vhdl/testbenches/ddr2_ram_model.vhd
@@ -99,7 +99,7 @@ ENTITY ddr2_ram_model IS
 END ENTITY ddr2_ram_model;
 
 ARCHITECTURE rtl OF ddr2_ram_model IS
-     -- DDR2 RAM size constants
+    -- DDR2 RAM size constants
     CONSTANT MEM_BITS       : INTEGER := 10;            -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
     CONSTANT AP             : INTEGER := 10;            -- the address bit that controls auto-precharge and precharge-all
     CONSTANT TDLLK          : INTEGER := 200;