diff --git a/include/MCF5475_MMU.h b/include/MCF5475_MMU.h index 334ad28..942e62e 100644 --- a/include/MCF5475_MMU.h +++ b/include/MCF5475_MMU.h @@ -62,7 +62,7 @@ /* Bit definitions and macros for MCF_MMU_MMUTR */ #define MCF_MMU_MMUTR_V (0x1) #define MCF_MMU_MMUTR_SG (0x2) -#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_ID(x) (((x) & 0xFF) << 0x2) #define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) /* Bit definitions and macros for MCF_MMU_MMUDR */ @@ -71,9 +71,9 @@ #define MCF_MMU_MMUDR_W (0x8) #define MCF_MMU_MMUDR_R (0x10) #define MCF_MMU_MMUDR_SP (0x20) -#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) -#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) -#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) +#define MCF_MMU_MMUDR_CM(x) (((x) & 0x3) << 0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x) & 0x3) << 0x8) +#define MCF_MMU_MMUDR_PA(x) (((x) & 0x3FFFFF) << 0xA) #endif /* __MCF5475_MMU_H__ */ diff --git a/include/mmu.h b/include/mmu.h index 72b6737..7cc9f84 100644 --- a/include/mmu.h +++ b/include/mmu.h @@ -24,6 +24,7 @@ #ifndef _MMU_H_ #define _MMU_H_ +#include #include "bas_types.h" /* @@ -54,10 +55,14 @@ /* * MMU page sizes */ -#define MMU_PAGE_SIZE_1M 0 -#define MMU_PAGE_SIZE_4K 1 -#define MMU_PAGE_SIZE_8K 2 -#define MMU_PAGE_SIZE_1K 3 + +enum mmu_page_size +{ + MMU_PAGE_SIZE_1M = 0, + MMU_PAGE_SIZE_4K = 1, + MMU_PAGE_SIZE_8K = 2, + MMU_PAGE_SIZE_1K = 3 +}; /* * cache modes @@ -78,13 +83,14 @@ #define ACCESS_WRITE (1 << 1) #define ACCESS_EXECUTE (1 << 2) -struct map_flags +struct mmu_map_flags { unsigned cache_mode:2; unsigned protection:1; unsigned page_id:8; unsigned access:3; - unsigned unused:18; + unsigned locked:1; + unsigned unused:17; }; /* @@ -94,6 +100,6 @@ extern long video_tlb; extern long video_sbt; extern void mmu_init(void); -extern void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags); +extern int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags); #endif /* _MMU_H_ */ diff --git a/sys/driver_mem.c b/sys/driver_mem.c index 441342a..d334010 100644 --- a/sys/driver_mem.c +++ b/sys/driver_mem.c @@ -28,7 +28,7 @@ #error "unknown machine!" #endif -// #define DBG_DM +#define DBG_DM #ifdef DBG_DM #define dbg(fmt, args...) xprintf(fmt, ##args) #else @@ -290,7 +290,7 @@ void *driver_mem_alloc(uint32_t amount) if (m != NULL) { - ret = (void *)m->m_start; + ret = (void *) m->m_start; } set_ipl(level); dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret); diff --git a/sys/exceptions.S b/sys/exceptions.S index 824d858..a9f7490 100644 --- a/sys/exceptions.S +++ b/sys/exceptions.S @@ -547,12 +547,10 @@ irq6: // MFP interrupt from FPGA lea MCF_EPORT_EPFR,a5 // clear int6 from edge port bset #6,(a5) - // there was a potential bug here before: would also clear all other edge port interrupts that might have happened... - // move.b #0x40,(a5) // clear int6 from edge port - -// screen adr change timed out? + // screen adr change timed out? move.l _video_sbt,d0 beq irq6_non_sca // nothing to do if 0 + sub.l #0x70000000,d0 // substract 14 seconds lea MCF_SLT0_SCNT,a5 cmp.l (a5),d0 // time reached? @@ -588,7 +586,7 @@ irq6: // MFP interrupt from FPGA add.l #copyback_mmudr,d1 // sonst page cb bra irq6_sca_pn1c irq6_sca_pn0: - add.l #writethrough_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked + add.l #writethrough_mmudr/*|MCF_MMU_MMUDR_LK*/,d1 // page wt and locked irq6_sca_pn1c: mvz.w #0x10b,d2 // MMU update move.l d0,MCF_MMU_MMUTR @@ -649,11 +647,6 @@ irq6_1: lea MCF_GPIO_PODR_FEC1L,a5 bset.b #4,(a5) // led off irq6_2: -// test auf protect mode --------------------- - move.b DIP_SWITCHa,d0 - btst #7,d0 - bne irq6_3 // ja-> -// ------------------------------------------- move.l 0xF0020000,a5 // vector holen add.l _rt_vbr,a5 // basis move.l (a5),d0 // vector holen @@ -662,33 +655,6 @@ irq6_2: move.l (a7)+,d0 // d0 zurück move #0x2600,sr rts -irq6_3: - move.l usp,a5 // usp holen - tst.b _rt_mod // supervisor? - bne sev_sup6 // ja -> - mov3q.l #-1,_rt_mod // auf supervisor setzen - move.l a5,_rt_usp // rt_usp speichern - move.l _rt_ssp,a5 // rt_ssp holen - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr transferieren - move.l a5,usp // usp setzen - move.l 0xF0020000,a5 // vector holen: intack routine - add.l _rt_vbr,a5 // virtuelle VBR des Systems - move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - move.b #6,2(a7) // intmaske setzen - rte // und weg -sev_sup6: - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr,vec - bset #5,2(a5) // auf super setzen - move.l a5,usp // usp setzen - move.l 0xF0020000,a5 // vector holen: intack routine - add.l _rt_vbr,a5 // virtuelle VBR des Systems - move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück - rts .data blinker:.long 0 @@ -844,7 +810,7 @@ video_copy_data_loop: bne video_copy_data_loop // eintrag suchen - move.l d0,MCF_MMU_MMUAR // adress + move.l d0,MCF_MMU_MMUAR // address move.l #0x106,d4 move.l d4,MCF_MMU_MMUOR // search -> new one will be offered if not found nop @@ -854,7 +820,7 @@ video_copy_data_loop: move.l d4,MCF_MMU_MMUAR move.l d0,d1 add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 - add.l #0x60000000|writethrough_mmudr|MCF_MMU_MMUDR_LK,d1 + add.l #0x60000000|writethrough_mmudr /* |MCF_MMU_MMUDR_LK */,d1 mvz.w #0x10b,d2 // MMU update move.l d0,MCF_MMU_MMUTR move.l d1,MCF_MMU_MMUDR diff --git a/sys/mmu.c b/sys/mmu.c index 8aa2b29..f5acc23 100644 --- a/sys/mmu.c +++ b/sys/mmu.c @@ -189,8 +189,76 @@ inline uint32_t set_mmubar(uint32_t value) return ret; } +/* + * map a page of memory using virt and phys as addresses with the Coldfire MMU. + * + * Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for + * instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them + * for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of + * TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs + * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the + * LRU algorithm) should be used sparsingly. + * + * + */ +int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags) +{ + int size_mask; + + switch (sz) + { + case MMU_PAGE_SIZE_1M: + size_mask = 0xfff00000; + break; + + case MMU_PAGE_SIZE_8K: + size_mask = 0xffffe000; + break; + + case MMU_PAGE_SIZE_4K: + size_mask = 0xfffff000; + break; + + case MMU_PAGE_SIZE_1K: + size_mask = 0xfffff800; + break; + + default: + dbg("illegal map size %d\r\n", sz); + return 0; + } + + /* + * add page to TLB + */ + MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */ + MCF_MMU_MMUTR_ID(flags->page_id) | /* address space id (ASID) */ + MCF_MMU_MMUTR_SG | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ + + MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */ + MCF_MMU_MMUDR_SZ(sz) | /* page size */ + MCF_MMU_MMUDR_CM(flags->cache_mode) | + (flags->access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ + (flags->access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ + (flags->access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */ + (flags->locked ? MCF_MMU_MMUDR_LK : 0); + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys); + + return 1; +} + void mmu_init(void) { + struct mmu_map_flags flags; + extern uint8_t _MMUBAR[]; uint32_t MMUBAR = (uint32_t) &_MMUBAR[0]; extern uint8_t _TOS[]; @@ -260,62 +328,25 @@ void mmu_init(void) /* create locked TLB entries */ - /* - * 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical - */ - MCF_MMU_MMUTR = 0x0 | /* virtual address */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = 0x0 | /* physical address */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x1) | /* cacheable, copyback */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + flags.cache_mode = CACHE_COPYBACK; + flags.protection = SV_USER; + flags.page_id = 0; + flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE; + flags.locked = true; + /* 0x0000_0000 - 0x000F_FFFF (first MB of physical memory) locked virt = phys */ + mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, &flags); + +#if defined(MACHINE_FIREBEE) /* * 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6 * mapped to physical address 0x60d0'0000 (FPGA video memory) * video RAM: read write execute normal write true */ + flags.cache_mode = CACHE_WRITETHROUGH; + flags.page_id = SCA_PAGE_ID; + mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, &flags); - MCF_MMU_MMUTR = 0x00d00000 | /* virtual address */ -#if defined(MACHINE_FIREBEE) - MCF_MMU_MMUTR_ID(SCA_PAGE_ID) | -#endif /* MACHINE_FIREBEE */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ -#if defined(MACHINE_FIREBEE) - /* map FPGA video memory for FireBee only */ - MCF_MMU_MMUDR = 0x60d00000 | /* physical address */ -#elif defined(MACHINE_M5484LITE) - MCF_MMU_MMUDR = 0x00d00000 | /* physical address */ -#elif defined(MACHINE_M54455) - MCF_MMU_MMUDR = 0x60d00000 | /* FIXME: not determined yet */ -#else -#error unknown machine! -#endif /* MACHINE_FIREBEE */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x0) | /* cachable writethrough */ - /* caveat: can't be supervisor protected since TOS puts the application stack there! */ - //MCF_MMU_MMUDR_SP | /* supervisor protect */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - -#if defined(MACHINE_FIREBEE) video_tlb = 0x2000; /* set page as video page */ video_sbt = 0x0; /* clear time */ #endif /* MACHINE_FIREBEE */ @@ -324,91 +355,48 @@ void mmu_init(void) * Make the TOS (in SDRAM) read-only * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address */ - MCF_MMU_MMUTR = TOS | /* virtual address */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = TOS | /* physical address */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x1) | /* cachable copyback */ - MCF_MMU_MMUDR_R | /* read access enable */ - //MCF_MMU_MMUDR_W | /* write access enable (FIXME: for now) */ - MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + flags.cache_mode = CACHE_COPYBACK; + flags.page_id = 0; + flags.access = ACCESS_READ | ACCESS_EXECUTE; + mmu_map_page(TOS, TOS, MMU_PAGE_SIZE_1M, &flags); -#if MACHINE_FIREBEE +#if defined(MACHINE_FIREBEE) /* * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee */ - - MCF_MMU_MMUTR = 0x00f00000 | /* virtual address */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = 0xfff00000 | /* physical address */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x2) | /* nocache precise */ - MCF_MMU_MMUDR_SP | /* supervisor protect */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.access = ACCESS_WRITE | ACCESS_READ; + mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, &flags); #endif /* MACHINE_FIREBEE */ /* * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same - * virtual address. This is also used when BaS is in RAM + * virtual address. This is also used (completely) when BaS is in RAM */ - - MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) | /* virtual address */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) | /* physical address */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x0) | /* cacheable writethrough */ - MCF_MMU_MMUDR_SP | /* supervisor protect */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + flags.cache_mode = CACHE_WRITETHROUGH; + flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE; + mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags); /* * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same * virtual address. Used uncached for drivers. */ - - MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* virtual address */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* physical address */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x2) | /* nocache precise */ - MCF_MMU_MMUDR_SP | /* supervisor protect */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - //MCF_MMU_MMUDR_X | /* execute access enable */ - MCF_MMU_MMUDR_LK; /* lock entry */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.access = ACCESS_READ | ACCESS_WRITE; + flags.protection = SV_PROTECT; + mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, &flags); } +static struct mmu_map_flags flags = +{ + .cache_mode = CACHE_COPYBACK, + .protection = SV_USER, + .page_id = 0, + .access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE, + .locked = false +}; + void mmutr_miss(uint32_t address, uint32_t pc, uint32_t format_status) { dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", address, format_status, pc); @@ -430,23 +418,9 @@ void mmutr_miss(uint32_t address, uint32_t pc, uint32_t format_status) default: /* add missed page to TLB */ - MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */ - MCF_MMU_MMUTR_SG | /* shared global */ - MCF_MMU_MMUTR_V; /* valid */ - - MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */ - MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */ - MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */ - MCF_MMU_MMUDR_R | /* read access enable */ - MCF_MMU_MMUDR_W | /* write access enable */ - MCF_MMU_MMUDR_X; /* execute access enable */ - - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ - - MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ - MCF_MMU_MMUOR_ACC | /* access TLB */ - MCF_MMU_MMUOR_UAA; /* update allocation address field */ + mmu_map_page(address, address, MMU_PAGE_SIZE_1M, &flags); + dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR); + dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n\r\n", MCF_MMU_MMUOR); } }