Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

modified jtagwait to allow to set reset start address when renamed to .TTP

Browse Source
This commit is contained in:
Markus Fröschle
2014-08-10 14:39:06 +00:00
parent 1134454984
commit 852bf8928f
6 changed files with 93 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
BaS_gcc/Makefile
View File

@@ -156,12 +156,15 @@ LIBBAS=libbas.a
LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS)) LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))
all: fls ram bfl lib all: fls ram bfl lib tos
fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS)) fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS)) ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS)) bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
lib: $(LIBS) lib: $(LIBS)
.PHONY: tos
tos:
(cd tos; make)
.PHONY: clean .PHONY: clean
clean: clean:

2
BaS_gcc/sys/init_fpga.c
View File

@@ -79,7 +79,7 @@ void config_gpio_for_jtag_config(void)
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */ /* all other bits = input */
/* /*
* unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well... * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/ */
} }

3
BaS_gcc/sys/sysinit.c
View File

@@ -1089,6 +1089,9 @@ void initialize_hardware(void)
#endif #endif
, MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__); , MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__);
extern char *rom_header;
xprintf("running from %p\r\n\r\n", &rom_header);
/* /*
* Determine cause(s) of Reset * Determine cause(s) of Reset
*/ */

11
BaS_gcc/tos/Makefile Normal file
View File

@@ -0,0 +1,11 @@
.PHONY: tos
.PHONY: jtagwait
.PHONY: mcdcook
tos: jtagwait mcdcook
jtagwait:
(cd $@; make)
mcdcook:
(cd $@; make)

2
BaS_gcc/tos/jtagwait/jtagwait.creator.user
View File

@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject> <!DOCTYPE QtCreatorProject>
<!-- Written by QtCreator 3.0.1, 2014-08-09T06:49:40. --> <!-- Written by QtCreator 3.0.1, 2014-08-10T15:03:49. -->
<qtcreator> <qtcreator>
<data> <data>
<variable>ProjectExplorer.Project.ActiveTarget</variable> <variable>ProjectExplorer.Project.ActiveTarget</variable>

117
BaS_gcc/tos/jtagwait/sources/jtagwait.c
View File

@@ -15,66 +15,95 @@ extern long _FPGA_JTAG_VALID;
#define FPGA_CONFIG (1 << 2) #define FPGA_CONFIG (1 << 2)
#define FPGA_CONF_DONE (1 << 5) #define FPGA_CONF_DONE (1 << 5)
long bas_start = 0xe0000000;
void wait_for_jtag(void) void wait_for_jtag(void)
{ {
int i; int i;
/* set supervisor stack to end of SRAM1 */ /* set supervisor stack to end of SRAM1 */
__asm__ __volatile__ ( __asm__ __volatile__ (
" move #0x2700,sr\n\t" /* disable interrupts */ " move #0x2700,sr\n\t" /* disable interrupts */
" move.l #0xff101000 + 0x1000 - 4,d0\n\t" /* 4KB on-chip core SRAM1 */ " move.l #0xff101000 + 0x1000 - 4,d0\n\t" /* 4KB on-chip core SRAM1 */
" move.l d0,sp\n\t" /* set stack pointer */ " move.l d0,sp\n\t" /* set stack pointer */
: :
: :
: "d0", "cc" /* clobber */ : "d0", "cc" /* clobber */
); );
MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */ MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */
MCF_INTC_IMRL = 0xffffffff; MCF_INTC_IMRL = 0xffffffff;
MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */ MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */
MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */ MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n"); xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
/* /*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA * configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/ */
MCF_GPIO_PDDR_FEC1L = 0 | MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */ /* all other bits = input */
xprintf("waiting for JTAG configuration start\r\n"); xprintf("waiting for JTAG configuration start\r\n");
/* /*
* now that this GPIO ports have been switched to input, we can poll for FPGA config * now that this GPIO ports have been switched to input, we can poll for FPGA config
* started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high) * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
*/ */
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */ while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */
xprintf("waiting for JTAG configuration finished\r\n"); xprintf("waiting for JTAG configuration finished\r\n");
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
xprintf("JTAG configuration finished.\r\n"); xprintf("JTAG configuration finished.\r\n");
_FPGA_JTAG_LOADED = true; /* indicate jtag loaded FPGA config to BaS */ _FPGA_JTAG_LOADED = true; /* indicate jtag loaded FPGA config to BaS */
_FPGA_JTAG_VALID = VALID_JTAG; _FPGA_JTAG_VALID = VALID_JTAG;
/* wait */ /* wait */
xprintf("wait a little to let things settle...\r\n"); xprintf("wait a little to let things settle...\r\n");
for (i = 0; i < 1000000; i++); for (i = 0; i < 1000000; i++);
__asm__ __volatile__( __asm__ __volatile__(
" jmp 0xe0000000\n\t" " jmp (%[bas_start])\n\t"
: : : : /* no output */
); : [bas_start] "a" (bas_start)
: /* clobber not needed */
);
} }
int main(int argc, char *argv[]) int main(int argc, char *argv[])
{ {
printf("\033E\r\nFPGA JTAG configuration support\r\n"); printf("\033E\r\nFPGA JTAG configuration support\r\n");
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n" printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
"and your Firebee will reboot once finished using that new configuration.\r\n"); "and your Firebee will reboot once finished using that new configuration.\r\n");
Supexec(wait_for_jtag); if (argc == 2)
{
/*
* we got an argument. This is supposed to be the address that we need to jump to after JTAG
* configuration has been finished. Meant to support BaS in RAM testing
*/
char *addr_str = argv[1];
char *addr = NULL;
char *end = NULL;
return 0; /* just to make the compiler happy, we will never return */ addr = (char *) strtol(addr_str, &end, 16);
if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
{
/*
* seems to be a valid address
*/
bas_start = (long) addr;
printf("BaS start address set to %p\r\n", addr);
}
else
{
printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
}
}
Supexec(wait_for_jtag);
return 0; /* just to make the compiler happy, we will never return */
} }