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corrected FASTRAM_END comparision

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This commit is contained in:
Markus Fröschle
2014-01-13 21:20:24 +00:00
parent 9c1befe977
commit 84a63c1554
2 changed files with 1 additions and 27 deletions
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25
BaS_gcc/sys/exceptions.S
View File

@@ -463,31 +463,6 @@ zd_end:
move.l (a7)+,a0 move.l (a7)+,a0
rte rte
#ifdef _NOT_USED_
linea:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
linef:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
format:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
//floating point
flpoow:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
#endif /* _NOT_USED */
irq1: irq1:
irq 0x64,1,0x02 irq 0x64,1,0x02

3
BaS_gcc/sys/mmu.c
View File

@@ -441,7 +441,7 @@ bool access_exception(uint32_t pc, uint32_t format_status)
else else
{ {
fault_address = MCF_MMU_MMUAR; /* retrieve fault access address from MMU */ fault_address = MCF_MMU_MMUAR; /* retrieve fault access address from MMU */
if (fault_address > FASTRAM_END) if (fault_address >= FASTRAM_END)
{ {
is_tlb_miss = false; /* this is a bus error */ is_tlb_miss = false; /* this is a bus error */
} }
@@ -459,7 +459,6 @@ bool access_exception(uint32_t pc, uint32_t format_status)
void mmutr_miss(uint32_t address) void mmutr_miss(uint32_t address)
{ {
dbg("MMU TLB MISS accessing 0x%08x\r\n", address); dbg("MMU TLB MISS accessing 0x%08x\r\n", address);
flush_and_invalidate_caches();
/* add missed page to TLB */ /* add missed page to TLB */
MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */ MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */