enabled MCDMA for fec

BaS_gcc/dma/dma.c

@@ -54,6 +54,47 @@ static struct dma_channel dma_channel[NCHANNELS] =
 	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
 };
 
+/********************************************************************/
+/*
+ * Enable all DMA interrupts
+ *
+ * Parameters:
+ *  pri     Interrupt Priority
+ *  lvl     Interrupt Level
+ */
+void dma_irq_enable(uint8_t lvl, uint8_t pri)
+{
+    /* Setup the DMA ICR (#48) */
+    MCF_INTC_ICR48 = 0
+        | MCF_INTC_ICR_IP(pri)
+        | MCF_INTC_ICR_IL(lvl);
+
+    /* Unmask all task interrupts */
+    MCF_DMA_DIMR = 0;
+
+    /* Clear the interrupt pending register */
+    MCF_DMA_DIPR = 0;
+
+    /* Unmask the DMA interrupt in the interrupt controller */
+    MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
+}
+
+/********************************************************************/
+/*
+ * Disable all DMA interrupts
+ */
+void dma_irq_disable(void)
+{
+    /* Mask all task interrupts */
+    MCF_DMA_DIMR = (uint32_t) ~0;
+
+    /* Clear any pending task interrupts */
+    MCF_DMA_DIPR = (uint32_t) ~0;
+
+    /* Mask the DMA interrupt in the interrupt controller */
+    MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
+}
+
 int dma_set_initiator(int initiator)
 {
 	switch (initiator)
@@ -365,6 +406,7 @@ void dma_clear_channel(int channel)
     dma_channel[channel].handler = NULL;
   }
 }
+
 /*
  * Return the channel being initiated by the given requestor
  *

BaS_gcc/include/dma.h

@@ -40,6 +40,9 @@ extern void dma_clear_channel(int channel);
 extern uint32_t dma_get_initiator(int requestor);
 extern int dma_set_initiator(int initiator);
 extern void dma_free_initiator(int initiator);
+extern void dma_irq_enable(uint8_t lvl, uint8_t pri);
+extern void dma_irq_disable(void);
+extern int dma_interrupt_handler(void *arg1, void *arg2);
 
 
 #endif /* _DMA_H_ */

BaS_gcc/sys/BaS.c

@@ -268,6 +268,18 @@ void network_init(void)
 		return;
 	}
 
+    /*
+     * Register the DMA interrupt handler
+     */
+    handler = dma_interrupt_handler;
+    vector = 112;
+
+    if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL,NULL))
+	{
+		xprintf("Error: Unable to register handler\n");
+		return;
+	}
+
 	nif_init(&nif1);
 	nif1.mtu = ETH_MTU;
 	nif1.send = fec0_send;
@@ -282,7 +294,9 @@ void network_init(void)
 	ip_init(&ip_info, myip, gateway, netmask);
 	nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
 
-	bootp_request(&nif1, 0);
+	dma_irq_enable(6, 0);
+
+	//bootp_request(&nif1, 0);
 }
 
 void BaS(void)
@@ -422,7 +436,7 @@ void BaS(void)
 	enable_coldfire_interrupts();
 
 	//set_ipl(0);
-	//network_init();
+	network_init();
 
 	xprintf("call EmuTOS\r\n");
 	ROM_HEADER* os_header = (ROM_HEADER*)TOS;

BaS_gcc/sys/exceptions.S

@@ -307,6 +307,7 @@ init_vec_loop:
 		move.l	a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
 		move.l	a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
 		move.l	a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
+		move.l	a1,(INT_SOURCE_DMA + 64) * 4(a0)
 
 		move.l	(sp)+,a2			// Restore registers
 		rts

BaS_gcc/sys/interrupts.c

@@ -205,6 +205,7 @@ bool isr_execute_handler(int vector)
 		if ((isrtab[index].vector == vector) &&
 				(isrtab[index].type == ISR_DBUG_ISR))
 		{
+			xprintf("calling BaS isr handler at %p\r\n", isrtab[index].handler);
 			if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
 			{
 				retval = true;
@@ -221,6 +222,7 @@ bool isr_execute_handler(int vector)
 		if ((isrtab[index].vector == vector) &&
 				(isrtab[index].type == ISR_USER_ISR))
 		{
+			xprintf("calling USR isr handler at %p\r\n", isrtab[index].handler);
 			if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
 			{
 				retval = true;