basically working config. Resolution changes still scramble the screen, however
This commit is contained in:
Markus Fröschle
@@ -1,30 +1,47 @@
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## Generated SDC file "firebee1.sdc"
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## Copyright (C) 1991-2014 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
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## DATE "Mon Sep 21 20:39:03 2015"
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##
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## DEVICE "EP3C40F484C6"
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##
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#--------------------------------------------------------------#
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# #
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# Synopsis design constraints for the Firebee project #
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# #
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# This file is part of the Firebee ACP project. #
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# http://www.experiment-s.de #
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# #
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# Description: #
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# timing constraints for the Firebee VHDL config #
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# #
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# #
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# #
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# To Do: #
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# - #
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# #
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# Author(s): #
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# Markus Fröschle, mfro@mubf.de #
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# #
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#--------------------------------------------------------------#
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# #
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# Copyright (C) 2015 Markus Fröschle & the ACP project #
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# #
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# This source file may be used and distributed without #
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# restriction provided that this copyright statement is not #
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# removed from the file and that any derivative work contains #
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# the original copyright notice and the associated disclaimer. #
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# #
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# This source file is free software; you can redistribute it #
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# and/or modify it under the terms of the GNU Lesser General #
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# Public License as published by the Free Software Foundation; #
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# either version 2.1 of the License, or (at your option) any #
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# later version. #
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# #
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# This source is distributed in the hope that it will be #
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# useful, but WITHOUT ANY WARRANTY; without even the implied #
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# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
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# PURPOSE. See the GNU Lesser General Public License for more #
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# details. #
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# #
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# You should have received a copy of the GNU Lesser General #
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# Public License along with this source; if not, download it #
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# from http://www.gnu.org/licenses/lgpl.html #
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# #
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################################################################
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#**************************************************************
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# Time Information
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@@ -51,11 +68,11 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
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#
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# PLL2: i_ddr_clock_pll
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# input: MAIN_CLK
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# c0: 132 MHz
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# c1: 132 MHz
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# c2: 132 MHz
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# c3: 132 MHz
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# c4: 66 MHz
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# c0: 132 MHz 190°
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# c1: 132 MHz 0°
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# c2: 132 MHz 180°
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# c3: 132 MHz 105°
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# c4: 66 MHz 270°
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#
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# PLL3: i_atari_clk_pll
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# input: MAIN_CLK
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@@ -101,14 +118,14 @@ derive_clock_uncertainty
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
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set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
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set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs]
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#**************************************************************
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@@ -122,7 +139,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {F
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#**************************************************************
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#
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# i_videl_clk is freely programmable
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# i_video_clk is freely programmable
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#
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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@@ -133,9 +150,6 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl
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# MAIN_CLK to DDR clk and v.v.
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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@@ -174,48 +188,6 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip
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# Set Multicycle Path
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#**************************************************************
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# Clocks used:
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# MAIN_CLK 33MHz
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#
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# PLL1: i_mfp_acia_clk_pll
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# input: MAIN_CLK
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# c0: 500 kHz
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# c1: 2.4576 MHz
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# c2: 24.576 MHz
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#
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# PLL2: i_ddr_clock_pll
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# input: MAIN_CLK
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# c0: 132 MHz
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# c1: 132 MHz
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# c2: 132 MHz
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# c3: 132 MHz
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# c4: 66 MHz
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#
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# PLL3: i_atari_clk_pll
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# input: MAIN_CLK
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# c0: 2 MHz
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# c1: 16 MHz
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# c2: 25 MHz
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# c3: 48 MHz
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#
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# PLL4_ i_video_clk_pll
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# input: USB_CLK (48 MHz, PLL3 c3)
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# c0: 96 MHz, programmable in 1MHz steps
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# 66 MHz to 33 MHz
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set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
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set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
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# 33 MHz to 66 MHz
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set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
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set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
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# 132 MHz to 33 MHz
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set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
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set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
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# 33 MHz to 132 MHz
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set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
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set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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@@ -238,3 +210,15 @@ set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {
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#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
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#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
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# restrict timing of video controller
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#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}]
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#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}]
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#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}]
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#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}]
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#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
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#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
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#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
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#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
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