added sdc file and upgraded IP components

Video/altddio_bidir0.bsf

@@ -1,99 +1,99 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 240 136)
+	(rect 0 0 272 144)
-	(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
+	(text "altddio_bidir0" (rect 94 0 202 17)(font "Dialog" (font_size 10)))
-	(text "inst" (rect 8 120 25 132)(font "Arial" ))
+	(text "inst" (rect 8 129 26 140)(font "Arial" ))
-	(port
+	(port
-		(pt 0 24)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
-		(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
-		(line (pt 0 24)(pt 88 24)(line_width 3))
+		(line (pt 0 48)(pt 96 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 64)
-		(input)
+		(input)
-		(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
-		(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
-		(line (pt 0 40)(pt 88 40)(line_width 3))
+		(line (pt 0 64)(pt 96 64)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 80)
-		(input)
+		(input)
-		(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "oe" (rect 0 0 16 13)(font "Dialog" (font_size 8)))
-		(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
+		(text "oe" (rect 4 67 18 79)(font "Dialog" (font_size 8)))
-		(line (pt 0 56)(pt 88 56)(line_width 1))
+		(line (pt 0 80)(pt 96 80))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 96)
-		(input)
+		(input)
-		(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 0 0 47 13)(font "Dialog" (font_size 8)))
-		(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 4 83 43 95)(font "Dialog" (font_size 8)))
-		(line (pt 0 72)(pt 88 72)(line_width 1))
+		(line (pt 0 96)(pt 96 96))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 112)
-		(input)
+		(input)
-		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
-		(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 99 52 111)(font "Dialog" (font_size 8)))
-		(line (pt 0 88)(pt 88 88)(line_width 1))
+		(line (pt 0 112)(pt 96 112))
-	)
+	)
-	(port
+	(port
-		(pt 240 24)
+		(pt 272 48)
-		(output)
+		(output)
-		(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 0 0 106 13)(font "Dialog" (font_size 8)))
-		(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 176 35 267 47)(font "Dialog" (font_size 8)))
-		(line (pt 240 24)(pt 144 24)(line_width 3))
+		(line (pt 272 48)(pt 160 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 240 40)
+		(pt 272 64)
-		(output)
+		(output)
-		(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 0 0 102 13)(font "Dialog" (font_size 8)))
-		(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 180 51 267 63)(font "Dialog" (font_size 8)))
-		(line (pt 240 40)(pt 144 40)(line_width 3))
+		(line (pt 272 64)(pt 160 64)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 240 72)
+		(pt 272 80)
-		(output)
+		(output)
-		(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 0 0 77 13)(font "Dialog" (font_size 8)))
-		(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 201 67 268 79)(font "Dialog" (font_size 8)))
-		(line (pt 240 72)(pt 144 72)(line_width 3))
+		(line (pt 272 80)(pt 160 80)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 240 56)
+		(pt 272 96)
-		(bidir)
+		(output)
-		(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 0 0 99 13)(font "Dialog" (font_size 8)))
-		(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 183 83 267 95)(font "Dialog" (font_size 8)))
-		(line (pt 240 56)(pt 144 56)(line_width 3))
+		(line (pt 272 96)(pt 160 96)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 160 32))
-		(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 160 128))
-		(text "power up" (rect 92 90 129 102)(font "Arial" ))
+		(line (pt 96 128)(pt 160 128))
-		(text "low" (rect 92 100 105 112)(font "Arial" ))
+		(line (pt 96 32)(pt 96 128))
-		(line (pt 88 16)(pt 144 16)(line_width 1))
+		(line (pt 0 0)(pt 272 0))
-		(line (pt 144 16)(pt 144 112)(line_width 1))
+		(line (pt 272 0)(pt 272 144))
-		(line (pt 144 112)(pt 88 112)(line_width 1))
+		(line (pt 0 144)(pt 272 144))
-		(line (pt 88 112)(pt 88 16)(line_width 1))
+		(line (pt 0 0)(pt 0 144))
-	)
+	)
-)
+)

Video/altddio_bidir0.cmp

@@ -1,29 +1,29 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component altddio_bidir0
+component altddio_bidir0
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		inclock		: IN STD_LOGIC ;
+		inclock		: IN STD_LOGIC ;
-		oe		: IN STD_LOGIC  := '1';
+		oe		: IN STD_LOGIC ;
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/altddio_bidir0.inc

@@ -1,30 +1,30 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION altddio_bidir0 
+FUNCTION altddio_bidir0 
-(
+(
-	datain_h[31..0],
+	datain_h[31..0],
-	datain_l[31..0],
+	datain_l[31..0],
-	inclock,
+	inclock,
-	oe,
+	oe,
-	outclock
+	outclock
-)
+)
-
+
-RETURNS (
+RETURNS (
-	combout[31..0],
+	combout[31..0],
-	dataout_h[31..0],
+	dataout_h[31..0],
-	dataout_l[31..0],
+	dataout_l[31..0],
-	padio[31..0]
+	padio[31..0]
-);
+);

Video/altddio_bidir0.ppf

@@ -1,16 +1,16 @@
-<?xml version="1.0" encoding="UTF-8" ?>
+<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
+<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
+<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
-<global>
+<global>
-<pin name="datain_h[31..0]" direction="input" scope="external"  />
+<pin name="datain_h[31..0]" direction="input" scope="external"  />
-<pin name="datain_l[31..0]" direction="input" scope="external"  />
+<pin name="datain_l[31..0]" direction="input" scope="external"  />
-<pin name="inclock" direction="input" scope="external" source="clock"  />
+<pin name="inclock" direction="input" scope="external" source="clock"  />
-<pin name="oe" direction="input" scope="external"  />
+<pin name="oe" direction="input" scope="external"  />
-<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
-<pin name="combout[31..0]" direction="output" scope="external"  />
+<pin name="combout[31..0]" direction="output" scope="external"  />
-<pin name="dataout_h[31..0]" direction="output" scope="external"  />
+<pin name="dataout_h[31..0]" direction="output" scope="external"  />
-<pin name="dataout_l[31..0]" direction="output" scope="external"  />
+<pin name="dataout_l[31..0]" direction="output" scope="external"  />
-<pin name="padio[31..0]" direction="bidir" scope="external"  />
+<pin name="padio[31..0]" direction="bidir" scope="external"  />
-
+
-</global>
+</global>
-</pinplan>
+</pinplan>

Video/altddio_bidir0.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]

Video/altddio_bidir0.vhd

@@ -1,172 +1,136 @@
--- megafunction wizard: %ALTDDIO_BIDIR%
+-- megafunction wizard: %ALTDDIO_BIDIR%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: altddio_bidir 
+-- MODULE: ALTDDIO_BIDIR 
-
+
--- ============================================================
+-- ============================================================
--- File Name: altddio_bidir0.vhd
+-- File Name: altddio_bidir0.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			altddio_bidir
+-- 			ALTDDIO_BIDIR
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			altera_mf
+-- 			altera_mf
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY altera_mf;
+LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
-
+
-ENTITY altddio_bidir0 IS
+ENTITY altddio_bidir0 IS
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		inclock		: IN STD_LOGIC ;
+		inclock		: IN STD_LOGIC ;
-		oe		: IN STD_LOGIC  := '1';
+		oe		: IN STD_LOGIC ;
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
+	);
-END altddio_bidir0;
+END altddio_bidir0;
-
+
-
+
-ARCHITECTURE SYN OF altddio_bidir0 IS
+ARCHITECTURE SYN OF altddio_bidir0 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-
+
-
+BEGIN
-
+	combout    <= sub_wire0(31 DOWNTO 0);
-	COMPONENT altddio_bidir
+	dataout_h    <= sub_wire1(31 DOWNTO 0);
-	GENERIC (
+	dataout_l    <= sub_wire2(31 DOWNTO 0);
-		extend_oe_disable		: STRING;
+
-		implement_input_in_lcell		: STRING;
+	ALTDDIO_BIDIR_component : ALTDDIO_BIDIR
-		intended_device_family		: STRING;
+	GENERIC MAP (
-		invert_output		: STRING;
+		extend_oe_disable => "OFF",
-		lpm_type		: STRING;
+		implement_input_in_lcell => "ON",
-		oe_reg		: STRING;
+		intended_device_family => "Cyclone III",
-		power_up_high		: STRING;
+		invert_output => "OFF",
-		width		: NATURAL
+		lpm_hint => "UNUSED",
-	);
+		lpm_type => "altddio_bidir",
-	PORT (
+		oe_reg => "UNREGISTERED",
-			outclock	: IN STD_LOGIC ;
+		power_up_high => "OFF",
-			padio	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		width => 32
-			inclock	: IN STD_LOGIC ;
+	)
-			dataout_h	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+	PORT MAP (
-			oe	: IN STD_LOGIC ;
+		datain_h => datain_h,
-			datain_h	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l => datain_l,
-			combout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		oe => oe,
-			dataout_l	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		outclock => outclock,
-			datain_l	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+		inclock => inclock,
-	);
+		combout => sub_wire0,
-	END COMPONENT;
+		dataout_h => sub_wire1,
-
+		dataout_l => sub_wire2,
-BEGIN
+		padio => padio
-	dataout_h    <= sub_wire0(31 DOWNTO 0);
+	);
-	combout    <= sub_wire1(31 DOWNTO 0);
+
-	dataout_l    <= sub_wire2(31 DOWNTO 0);
+
-
+
-	altddio_bidir_component : altddio_bidir
+END SYN;
-	GENERIC MAP (
+
-		extend_oe_disable => "UNUSED",
+-- ============================================================
-		implement_input_in_lcell => "ON",
+-- CNX file retrieval info
-		intended_device_family => "Cyclone III",
+-- ============================================================
-		invert_output => "OFF",
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-		lpm_type => "altddio_bidir",
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-		oe_reg => "UNUSED",
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-		power_up_high => "OFF",
+-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
-		width => 32
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-	)
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-	PORT MAP (
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-		outclock => outclock,
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
-		inclock => inclock,
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-		oe => oe,
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-		datain_h => datain_h,
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
-		datain_l => datain_l,
+-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]"
-		dataout_h => sub_wire0,
+-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
-		combout => sub_wire1,
+-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]"
-		dataout_l => sub_wire2,
+-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
-		padio => padio
+-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]"
-	);
+-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
-
+-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]"
-
+-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
-
+-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]"
-END SYN;
+-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
-
+-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
--- ============================================================
+-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
--- CNX file retrieval info
+-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
--- ============================================================
+-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
--- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]"
--- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
+-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE FALSE
--- Retrieval info: PRIVATE: OE NUMERIC "1"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE
--- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE TRUE
--- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE TRUE
--- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE TRUE
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE TRUE
--- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE
--- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
+-- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
--- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
--- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
--- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
--- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
--- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
--- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
--- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
--- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
--- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
--- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
--- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
--- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
--- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
--- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
--- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
--- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
--- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
--- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf

Video/altddio_out0.bsf

@@ -1,64 +1,64 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 232 120)
+	(rect 0 0 256 112)
-	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "altddio_out0" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
-	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
-	(port
+	(port
-		(pt 0 24)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 0 0 89 13)(font "Dialog" (font_size 8)))
-		(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 4 35 80 47)(font "Dialog" (font_size 8)))
-		(line (pt 0 24)(pt 88 24)(line_width 3))
+		(line (pt 0 48)(pt 96 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 64)
-		(input)
+		(input)
-		(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
-		(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 4 51 76 63)(font "Dialog" (font_size 8)))
-		(line (pt 0 40)(pt 88 40)(line_width 3))
+		(line (pt 0 64)(pt 96 64)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 80)
-		(input)
+		(input)
-		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
-		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
-		(line (pt 0 56)(pt 88 56)(line_width 1))
+		(line (pt 0 80)(pt 96 80))
-	)
+	)
-	(port
+	(port
-		(pt 232 24)
+		(pt 256 48)
-		(output)
+		(output)
-		(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
-		(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 180 35 252 47)(font "Dialog" (font_size 8)))
-		(line (pt 232 24)(pt 152 24)(line_width 3))
+		(line (pt 256 48)(pt 160 48)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 160 32))
-		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 160 96))
-		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(line (pt 96 96)(pt 160 96))
-		(text "high" (rect 92 84 109 96)(font "Arial" ))
+		(line (pt 96 32)(pt 96 96))
-		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 0 0)(pt 256 0))
-		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 256 0)(pt 256 112))
-		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 0 112)(pt 256 112))
-		(line (pt 88 96)(pt 88 16)(line_width 1))
+		(line (pt 0 0)(pt 0 112))
-	)
+	)
-)
+)

Video/altddio_out0.cmp

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component altddio_out0
+component altddio_out0
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/altddio_out0.inc

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION altddio_out0 
+FUNCTION altddio_out0 
-(
+(
-	datain_h[3..0],
+	datain_h[3..0],
-	datain_l[3..0],
+	datain_l[3..0],
-	outclock
+	outclock
-)
+)
-
+
-RETURNS (
+RETURNS (
-	dataout[3..0]
+	dataout[3..0]
-);
+);

Video/altddio_out0.ppf

@@ -1,11 +1,11 @@
-<?xml version="1.0" encoding="UTF-8" ?>
+<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
+<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
-<global>
+<global>
-<pin name="datain_h[3..0]" direction="input" scope="external"  />
+<pin name="datain_h[3..0]" direction="input" scope="external"  />
-<pin name="datain_l[3..0]" direction="input" scope="external"  />
+<pin name="datain_l[3..0]" direction="input" scope="external"  />
-<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
-<pin name="dataout[3..0]" direction="output" scope="external"  />
+<pin name="dataout[3..0]" direction="output" scope="external"  />
-
+
-</global>
+</global>
-</pinplan>
+</pinplan>

Video/altddio_out0.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]

Video/altddio_out0.vhd

@@ -1,136 +1,110 @@
--- megafunction wizard: %ALTDDIO_OUT%
+-- megafunction wizard: %ALTDDIO_OUT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: altddio_out 
+-- MODULE: ALTDDIO_OUT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: altddio_out0.vhd
+-- File Name: altddio_out0.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			altddio_out
+-- 			ALTDDIO_OUT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			altera_mf
+-- 			altera_mf
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY altera_mf;
+LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
-
+
-ENTITY altddio_out0 IS
+ENTITY altddio_out0 IS
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
+	);
-END altddio_out0;
+END altddio_out0;
-
+
-
+
-ARCHITECTURE SYN OF altddio_out0 IS
+ARCHITECTURE SYN OF altddio_out0 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
+
-
+BEGIN
-
+	dataout    <= sub_wire0(3 DOWNTO 0);
-	COMPONENT altddio_out
+
-	GENERIC (
+	ALTDDIO_OUT_component : ALTDDIO_OUT
-		extend_oe_disable		: STRING;
+	GENERIC MAP (
-		intended_device_family		: STRING;
+		extend_oe_disable => "OFF",
-		invert_output		: STRING;
+		intended_device_family => "Cyclone III",
-		lpm_type		: STRING;
+		invert_output => "ON",
-		oe_reg		: STRING;
+		lpm_hint => "UNUSED",
-		power_up_high		: STRING;
+		lpm_type => "altddio_out",
-		width		: NATURAL
+		oe_reg => "UNREGISTERED",
-	);
+		power_up_high => "ON",
-	PORT (
+		width => 4
-			dataout	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+	)
-			outclock	: IN STD_LOGIC ;
+	PORT MAP (
-			datain_h	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_h => datain_h,
-			datain_l	: IN STD_LOGIC_VECTOR (3 DOWNTO 0)
+		datain_l => datain_l,
-	);
+		outclock => outclock,
-	END COMPONENT;
+		dataout => sub_wire0
-
+	);
-BEGIN
+
-	dataout    <= sub_wire0(3 DOWNTO 0);
+
-
+
-	altddio_out_component : altddio_out
+END SYN;
-	GENERIC MAP (
+
-		extend_oe_disable => "UNUSED",
+-- ============================================================
-		intended_device_family => "Cyclone III",
+-- CNX file retrieval info
-		invert_output => "ON",
+-- ============================================================
-		lpm_type => "altddio_out",
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-		oe_reg => "UNUSED",
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-		power_up_high => "ON",
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-		width => 4
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-	)
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
-	PORT MAP (
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-		outclock => outclock,
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-		datain_h => datain_h,
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-		datain_l => datain_l,
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
-		dataout => sub_wire0
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
-	);
+-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL "datain_h[3..0]"
-
+-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
-
+-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL "datain_l[3..0]"
-
+-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
-END SYN;
+-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
-
+-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
--- ============================================================
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- CNX file retrieval info
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- ============================================================
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE FALSE
--- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.qip TRUE FALSE
--- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE TRUE
--- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE TRUE
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE TRUE
--- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE TRUE
--- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE FALSE
--- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
+-- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
--- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
--- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
--- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
--- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
--- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
--- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf

Video/altddio_out2.bsf

@@ -1,64 +1,64 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 232 120)
+	(rect 0 0 256 112)
-	(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "altddio_out2" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
-	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
-	(port
+	(port
-		(pt 0 24)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
-		(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
-		(line (pt 0 24)(pt 88 24)(line_width 3))
+		(line (pt 0 48)(pt 96 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 64)
-		(input)
+		(input)
-		(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
-		(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
-		(line (pt 0 40)(pt 88 40)(line_width 3))
+		(line (pt 0 64)(pt 96 64)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 80)
-		(input)
+		(input)
-		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
-		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
-		(line (pt 0 56)(pt 88 56)(line_width 1))
+		(line (pt 0 80)(pt 96 80))
-	)
+	)
-	(port
+	(port
-		(pt 232 24)
+		(pt 256 48)
-		(output)
+		(output)
-		(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 0 0 92 13)(font "Dialog" (font_size 8)))
-		(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 173 35 252 47)(font "Dialog" (font_size 8)))
-		(line (pt 232 24)(pt 152 24)(line_width 3))
+		(line (pt 256 48)(pt 160 48)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 160 32))
-		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 160 96))
-		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(line (pt 96 96)(pt 160 96))
-		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 96 32)(pt 96 96))
-		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 0 0)(pt 256 0))
-		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 256 0)(pt 256 112))
-		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 0 112)(pt 256 112))
-		(line (pt 88 96)(pt 88 16)(line_width 1))
+		(line (pt 0 0)(pt 0 112))
-	)
+	)
-)
+)

Video/altddio_out2.cmp

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component altddio_out2
+component altddio_out2
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/altddio_out2.inc

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION altddio_out2 
+FUNCTION altddio_out2 
-(
+(
-	datain_h[23..0],
+	datain_h[23..0],
-	datain_l[23..0],
+	datain_l[23..0],
-	outclock
+	outclock
-)
+)
-
+
-RETURNS (
+RETURNS (
-	dataout[23..0]
+	dataout[23..0]
-);
+);

Video/altddio_out2.ppf

@@ -1,11 +1,11 @@
-<?xml version="1.0" encoding="UTF-8" ?>
+<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
+<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
-<global>
+<global>
-<pin name="datain_h[23..0]" direction="input" scope="external"  />
+<pin name="datain_h[23..0]" direction="input" scope="external"  />
-<pin name="datain_l[23..0]" direction="input" scope="external"  />
+<pin name="datain_l[23..0]" direction="input" scope="external"  />
-<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
-<pin name="dataout[23..0]" direction="output" scope="external"  />
+<pin name="dataout[23..0]" direction="output" scope="external"  />
-
+
-</global>
+</global>
-</pinplan>
+</pinplan>

Video/altddio_out2.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]

Video/altddio_out2.vhd

@@ -1,136 +1,110 @@
--- megafunction wizard: %ALTDDIO_OUT%
+-- megafunction wizard: %ALTDDIO_OUT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: altddio_out 
+-- MODULE: ALTDDIO_OUT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: altddio_out2.vhd
+-- File Name: altddio_out2.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			altddio_out
+-- 			ALTDDIO_OUT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			altera_mf
+-- 			altera_mf
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY altera_mf;
+LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
-
+
-ENTITY altddio_out2 IS
+ENTITY altddio_out2 IS
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
-	);
+	);
-END altddio_out2;
+END altddio_out2;
-
+
-
+
-ARCHITECTURE SYN OF altddio_out2 IS
+ARCHITECTURE SYN OF altddio_out2 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-
+
-
+BEGIN
-
+	dataout    <= sub_wire0(23 DOWNTO 0);
-	COMPONENT altddio_out
+
-	GENERIC (
+	ALTDDIO_OUT_component : ALTDDIO_OUT
-		extend_oe_disable		: STRING;
+	GENERIC MAP (
-		intended_device_family		: STRING;
+		extend_oe_disable => "OFF",
-		invert_output		: STRING;
+		intended_device_family => "Cyclone III",
-		lpm_type		: STRING;
+		invert_output => "OFF",
-		oe_reg		: STRING;
+		lpm_hint => "UNUSED",
-		power_up_high		: STRING;
+		lpm_type => "altddio_out",
-		width		: NATURAL
+		oe_reg => "UNREGISTERED",
-	);
+		power_up_high => "OFF",
-	PORT (
+		width => 24
-			dataout	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+	)
-			outclock	: IN STD_LOGIC ;
+	PORT MAP (
-			datain_h	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_h => datain_h,
-			datain_l	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+		datain_l => datain_l,
-	);
+		outclock => outclock,
-	END COMPONENT;
+		dataout => sub_wire0
-
+	);
-BEGIN
+
-	dataout    <= sub_wire0(23 DOWNTO 0);
+
-
+
-	altddio_out_component : altddio_out
+END SYN;
-	GENERIC MAP (
+
-		extend_oe_disable => "UNUSED",
+-- ============================================================
-		intended_device_family => "Cyclone III",
+-- CNX file retrieval info
-		invert_output => "OFF",
+-- ============================================================
-		lpm_type => "altddio_out",
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-		oe_reg => "UNUSED",
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-		power_up_high => "OFF",
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-		width => 24
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-	)
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-	PORT MAP (
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-		outclock => outclock,
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-		datain_h => datain_h,
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-		datain_l => datain_l,
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-		dataout => sub_wire0
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
-	);
+-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL "datain_h[23..0]"
-
+-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
-
+-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL "datain_l[23..0]"
-
+-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
-END SYN;
+-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL "dataout[23..0]"
-
+-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
--- ============================================================
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- CNX file retrieval info
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- ============================================================
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE FALSE
--- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.qip TRUE FALSE
--- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE TRUE
--- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE TRUE
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE TRUE
--- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE TRUE
--- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE FALSE
--- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
--- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
--- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
--- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
--- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
--- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
--- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf

Video/lpm_constant0.bsf

@@ -1,42 +1,49 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 96 48)
+	(rect 0 0 112 48)
-	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "lpm_constant0" (rect 14 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
-	(port
+	(port
-		(pt 96 24)
+		(pt 112 24)
-		(output)
+		(output)
-		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
-		(line (pt 96 24)(pt 80 24)(line_width 3))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 99 27 204 64)(font "Arial" ))
-		(text "5" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
-		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 16 16)(pt 16 32))
-		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 16 16)(pt 96 16))
-		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 96 32))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 96 16)(pt 96 32))
-		(line (pt 82 28)(pt 90 20)(line_width 1))
+		(line (pt 0 0)(pt 114 0))
-	)
+		(line (pt 114 0)(pt 114 50))
-)
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_constant0.cmp

@@ -1,21 +1,21 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_constant0
+component lpm_constant0
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_constant0.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]

Video/lpm_constant0.vhd

@@ -1,108 +1,109 @@
--- megafunction wizard: %LPM_CONSTANT%
+-- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_constant 
+-- MODULE: LPM_CONSTANT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_constant0.vhd
+-- File Name: lpm_constant0.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_constant
+-- 			LPM_CONSTANT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_constant0 IS
+ENTITY lpm_constant0 IS
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
+	);
-END lpm_constant0;
+END lpm_constant0;
-
+
-
+
-ARCHITECTURE SYN OF lpm_constant0 IS
+ARCHITECTURE SYN OF lpm_constant0 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-
+
-
+
-
+
-	COMPONENT lpm_constant
+	COMPONENT lpm_constant
-	GENERIC (
+	GENERIC (
-		lpm_cvalue		: NATURAL;
+		lpm_cvalue		: NATURAL;
-		lpm_hint		: STRING;
+		lpm_hint		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			result	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+			result	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	result    <= sub_wire0(4 DOWNTO 0);
+	result    <= sub_wire0(4 DOWNTO 0);
-
+
-	lpm_constant_component : lpm_constant
+	LPM_CONSTANT_component : LPM_CONSTANT
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_cvalue => 0,
+		lpm_cvalue => 0,
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "LPM_CONSTANT",
+		lpm_type => "LPM_CONSTANT",
-		lpm_width => 5
+		lpm_width => 5
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
--- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_constant1.bsf

@@ -1,42 +1,49 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 96 48)
+	(rect 0 0 112 48)
-	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "lpm_constant1" (rect 14 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
-	(port
+	(port
-		(pt 96 24)
+		(pt 112 24)
-		(output)
+		(output)
-		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
-		(line (pt 96 24)(pt 80 24)(line_width 3))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 99 27 204 64)(font "Arial" ))
-		(text "2" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
-		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 16 16)(pt 16 32))
-		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 16 16)(pt 96 16))
-		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 96 32))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 96 16)(pt 96 32))
-		(line (pt 82 28)(pt 90 20)(line_width 1))
+		(line (pt 0 0)(pt 114 0))
-	)
+		(line (pt 114 0)(pt 114 50))
-)
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_constant1.cmp

@@ -1,21 +1,21 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_constant1
+component lpm_constant1
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_constant1.inc

@@ -1,23 +1,23 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_constant1 
+FUNCTION lpm_constant1 
-(
+(
-
+
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[1..0]
+	result[1..0]
-);
+);

Video/lpm_constant1.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]

Video/lpm_constant1.vhd

@@ -1,108 +1,109 @@
--- megafunction wizard: %LPM_CONSTANT%
+-- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_constant 
+-- MODULE: LPM_CONSTANT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_constant1.vhd
+-- File Name: lpm_constant1.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_constant
+-- 			LPM_CONSTANT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_constant1 IS
+ENTITY lpm_constant1 IS
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
+	);
-END lpm_constant1;
+END lpm_constant1;
-
+
-
+
-ARCHITECTURE SYN OF lpm_constant1 IS
+ARCHITECTURE SYN OF lpm_constant1 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-
+
-
+
-
+
-	COMPONENT lpm_constant
+	COMPONENT lpm_constant
-	GENERIC (
+	GENERIC (
-		lpm_cvalue		: NATURAL;
+		lpm_cvalue		: NATURAL;
-		lpm_hint		: STRING;
+		lpm_hint		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			result	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+			result	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	result    <= sub_wire0(1 DOWNTO 0);
+	result    <= sub_wire0(1 DOWNTO 0);
-
+
-	lpm_constant_component : lpm_constant
+	LPM_CONSTANT_component : LPM_CONSTANT
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_cvalue => 0,
+		lpm_cvalue => 0,
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "LPM_CONSTANT",
+		lpm_type => "LPM_CONSTANT",
-		lpm_width => 2
+		lpm_width => 2
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
--- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL "result[1..0]"
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_constant2.bsf

@@ -1,42 +1,49 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 96 48)
+	(rect 0 0 112 48)
-	(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "lpm_constant2" (rect 14 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
-	(port
+	(port
-		(pt 96 24)
+		(pt 112 24)
-		(output)
+		(output)
-		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
-		(line (pt 96 24)(pt 80 24)(line_width 3))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "8" (rect 99 27 204 64)(font "Arial" ))
-		(text "8" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
-		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 16 16)(pt 16 32))
-		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 16 16)(pt 96 16))
-		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 96 32))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 96 16)(pt 96 32))
-		(line (pt 82 28)(pt 90 20)(line_width 1))
+		(line (pt 0 0)(pt 114 0))
-	)
+		(line (pt 114 0)(pt 114 50))
-)
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_constant2.cmp

@@ -1,21 +1,21 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_constant2
+component lpm_constant2
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_constant2.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]

Video/lpm_constant2.vhd

@@ -1,108 +1,109 @@
--- megafunction wizard: %LPM_CONSTANT%
+-- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_constant 
+-- MODULE: LPM_CONSTANT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_constant2.vhd
+-- File Name: lpm_constant2.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_constant
+-- 			LPM_CONSTANT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_constant2 IS
+ENTITY lpm_constant2 IS
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
+	);
-END lpm_constant2;
+END lpm_constant2;
-
+
-
+
-ARCHITECTURE SYN OF lpm_constant2 IS
+ARCHITECTURE SYN OF lpm_constant2 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
+
-
+
-
+
-	COMPONENT lpm_constant
+	COMPONENT lpm_constant
-	GENERIC (
+	GENERIC (
-		lpm_cvalue		: NATURAL;
+		lpm_cvalue		: NATURAL;
-		lpm_hint		: STRING;
+		lpm_hint		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			result	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+			result	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	result    <= sub_wire0(7 DOWNTO 0);
+	result    <= sub_wire0(7 DOWNTO 0);
-
+
-	lpm_constant_component : lpm_constant
+	LPM_CONSTANT_component : LPM_CONSTANT
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_cvalue => 0,
+		lpm_cvalue => 0,
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "LPM_CONSTANT",
+		lpm_type => "LPM_CONSTANT",
-		lpm_width => 8
+		lpm_width => 8
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
--- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_constant3.bsf

@@ -1,42 +1,49 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 96 48)
+	(rect 0 0 112 48)
-	(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "lpm_constant3" (rect 14 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
-	(port
+	(port
-		(pt 96 24)
+		(pt 112 24)
-		(output)
+		(output)
-		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
-		(line (pt 96 24)(pt 80 24)(line_width 3))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "7" (rect 99 27 204 64)(font "Arial" ))
-		(text "7" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
-		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 16 16)(pt 16 32))
-		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 16 16)(pt 96 16))
-		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 96 32))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 96 16)(pt 96 32))
-		(line (pt 82 28)(pt 90 20)(line_width 1))
+		(line (pt 0 0)(pt 114 0))
-	)
+		(line (pt 114 0)(pt 114 50))
-)
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_constant3.cmp

@@ -1,21 +1,21 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_constant3
+component lpm_constant3
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_constant3.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]

Video/lpm_constant3.vhd

@@ -1,108 +1,109 @@
--- megafunction wizard: %LPM_CONSTANT%
+-- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_constant 
+-- MODULE: LPM_CONSTANT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_constant3.vhd
+-- File Name: lpm_constant3.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_constant
+-- 			LPM_CONSTANT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_constant3 IS
+ENTITY lpm_constant3 IS
-	PORT
+	PORT
-	(
+	(
-		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
-	);
+	);
-END lpm_constant3;
+END lpm_constant3;
-
+
-
+
-ARCHITECTURE SYN OF lpm_constant3 IS
+ARCHITECTURE SYN OF lpm_constant3 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-
+
-
+
-
+
-	COMPONENT lpm_constant
+	COMPONENT lpm_constant
-	GENERIC (
+	GENERIC (
-		lpm_cvalue		: NATURAL;
+		lpm_cvalue		: NATURAL;
-		lpm_hint		: STRING;
+		lpm_hint		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			result	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+			result	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	result    <= sub_wire0(6 DOWNTO 0);
+	result    <= sub_wire0(6 DOWNTO 0);
-
+
-	lpm_constant_component : lpm_constant
+	LPM_CONSTANT_component : LPM_CONSTANT
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_cvalue => 0,
+		lpm_cvalue => 0,
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "LPM_CONSTANT",
+		lpm_type => "LPM_CONSTANT",
-		lpm_width => 7
+		lpm_width => 7
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
--- Retrieval info: PRIVATE: nBit NUMERIC "7"
+-- Retrieval info: PRIVATE: nBit NUMERIC "7"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux0.bsf

@@ -1,83 +1,91 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 152 128)
+	(rect 0 0 144 128)
-	(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux0" (rect 43 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(text "inst" (rect 8 113 26 124)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 72 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 72 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 72 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
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+	)
-	(port
+	(port
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+		(pt 0 88)
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+		(input)
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+		(text "data0x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 72 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
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+		(input)
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+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 91 29 103)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 72 104)(line_width 1))
+		(line (pt 0 104)(pt 64 104))
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-		(text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 66 73 78 111)(font "Arial" (font_size 8))(vertical))
-		(line (pt 80 128)(pt 80 116)(line_width 3))
+		(line (pt 72 128)(pt 72 116)(line_width 3))
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+	)
-	(port
+	(port
-		(pt 152 72)
+		(pt 144 72)
-		(output)
+		(output)
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+		(text "result[31..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 85 59 142 71)(font "Arial" (font_size 8)))
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+		(line (pt 144 72)(pt 80 72)(line_width 3))
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+	)
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+	(drawing
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+		(line (pt 0 130)(pt 146 130))
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+		(line (pt 0 0)(pt 0 130))
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+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux0.cmp

@@ -1,27 +1,27 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux0
+component lpm_mux0
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux0.inc

@@ -1,28 +1,28 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_mux0 
+FUNCTION lpm_mux0 
-(
+(
-	clock,
+	clock,
-	data0x[31..0],
+	data0x[31..0],
-	data1x[31..0],
+	data1x[31..0],
-	data2x[31..0],
+	data2x[31..0],
-	data3x[31..0],
+	data3x[31..0],
-	sel[1..0]
+	sel[1..0]
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[31..0]
+	result[31..0]
-);
+);

Video/lpm_mux0.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]

Video/lpm_mux0.vhd

@@ -1,251 +1,252 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux0.vhd
+-- File Name: lpm_mux0.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux0 IS
+ENTITY lpm_mux0 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-	);
+	);
-END lpm_mux0;
+END lpm_mux0;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux0 IS
+ARCHITECTURE SYN OF lpm_mux0 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (31 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire5    <= data0x(31 DOWNTO 0);
+	sub_wire5    <= data0x(31 DOWNTO 0);
-	sub_wire4    <= data1x(31 DOWNTO 0);
+	sub_wire4    <= data1x(31 DOWNTO 0);
-	sub_wire3    <= data2x(31 DOWNTO 0);
+	sub_wire3    <= data2x(31 DOWNTO 0);
-	result    <= sub_wire0(31 DOWNTO 0);
+	result    <= sub_wire0(31 DOWNTO 0);
-	sub_wire1    <= data3x(31 DOWNTO 0);
+	sub_wire1    <= data3x(31 DOWNTO 0);
-	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
-	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 1)    <= sub_wire1(1);
-	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 2)    <= sub_wire1(2);
-	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 3)    <= sub_wire1(3);
-	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 4)    <= sub_wire1(4);
-	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 5)    <= sub_wire1(5);
-	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 6)    <= sub_wire1(6);
-	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 7)    <= sub_wire1(7);
-	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 8)    <= sub_wire1(8);
-	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 9)    <= sub_wire1(9);
-	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 10)    <= sub_wire1(10);
-	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 11)    <= sub_wire1(11);
-	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 12)    <= sub_wire1(12);
-	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 13)    <= sub_wire1(13);
-	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 14)    <= sub_wire1(14);
-	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 15)    <= sub_wire1(15);
-	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 16)    <= sub_wire1(16);
-	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 17)    <= sub_wire1(17);
-	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 18)    <= sub_wire1(18);
-	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 19)    <= sub_wire1(19);
-	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 20)    <= sub_wire1(20);
-	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 21)    <= sub_wire1(21);
-	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 22)    <= sub_wire1(22);
-	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 23)    <= sub_wire1(23);
-	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 24)    <= sub_wire1(24);
-	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 25)    <= sub_wire1(25);
-	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 26)    <= sub_wire1(26);
-	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 27)    <= sub_wire1(27);
-	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 28)    <= sub_wire1(28);
-	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 29)    <= sub_wire1(29);
-	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 30)    <= sub_wire1(30);
-	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(3, 31)    <= sub_wire1(31);
-	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 0)    <= sub_wire3(0);
-	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 1)    <= sub_wire3(1);
-	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 2)    <= sub_wire3(2);
-	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 3)    <= sub_wire3(3);
-	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 4)    <= sub_wire3(4);
-	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 5)    <= sub_wire3(5);
-	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 6)    <= sub_wire3(6);
-	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 7)    <= sub_wire3(7);
-	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 8)    <= sub_wire3(8);
-	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 9)    <= sub_wire3(9);
-	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 10)    <= sub_wire3(10);
-	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 11)    <= sub_wire3(11);
-	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 12)    <= sub_wire3(12);
-	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 13)    <= sub_wire3(13);
-	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 14)    <= sub_wire3(14);
-	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 15)    <= sub_wire3(15);
-	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 16)    <= sub_wire3(16);
-	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 17)    <= sub_wire3(17);
-	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 18)    <= sub_wire3(18);
-	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 19)    <= sub_wire3(19);
-	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 20)    <= sub_wire3(20);
-	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 21)    <= sub_wire3(21);
-	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 22)    <= sub_wire3(22);
-	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 23)    <= sub_wire3(23);
-	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 24)    <= sub_wire3(24);
-	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 25)    <= sub_wire3(25);
-	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 26)    <= sub_wire3(26);
-	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 27)    <= sub_wire3(27);
-	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 28)    <= sub_wire3(28);
-	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 29)    <= sub_wire3(29);
-	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 30)    <= sub_wire3(30);
-	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(2, 31)    <= sub_wire3(31);
-	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 0)    <= sub_wire4(0);
-	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 1)    <= sub_wire4(1);
-	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 2)    <= sub_wire4(2);
-	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 3)    <= sub_wire4(3);
-	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 4)    <= sub_wire4(4);
-	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 5)    <= sub_wire4(5);
-	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 6)    <= sub_wire4(6);
-	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 7)    <= sub_wire4(7);
-	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 8)    <= sub_wire4(8);
-	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 9)    <= sub_wire4(9);
-	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 10)    <= sub_wire4(10);
-	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 11)    <= sub_wire4(11);
-	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 12)    <= sub_wire4(12);
-	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 13)    <= sub_wire4(13);
-	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 14)    <= sub_wire4(14);
-	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 15)    <= sub_wire4(15);
-	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 16)    <= sub_wire4(16);
-	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 17)    <= sub_wire4(17);
-	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 18)    <= sub_wire4(18);
-	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 19)    <= sub_wire4(19);
-	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 20)    <= sub_wire4(20);
-	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 21)    <= sub_wire4(21);
-	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 22)    <= sub_wire4(22);
-	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 23)    <= sub_wire4(23);
-	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 24)    <= sub_wire4(24);
-	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 25)    <= sub_wire4(25);
-	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 26)    <= sub_wire4(26);
-	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 27)    <= sub_wire4(27);
-	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 28)    <= sub_wire4(28);
-	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 29)    <= sub_wire4(29);
-	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 30)    <= sub_wire4(30);
-	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(1, 31)    <= sub_wire4(31);
-	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 0)    <= sub_wire5(0);
-	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 1)    <= sub_wire5(1);
-	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 2)    <= sub_wire5(2);
-	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 3)    <= sub_wire5(3);
-	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 4)    <= sub_wire5(4);
-	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 5)    <= sub_wire5(5);
-	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 6)    <= sub_wire5(6);
-	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 7)    <= sub_wire5(7);
-	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 8)    <= sub_wire5(8);
-	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 9)    <= sub_wire5(9);
-	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 10)    <= sub_wire5(10);
-	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 11)    <= sub_wire5(11);
-	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 12)    <= sub_wire5(12);
-	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 13)    <= sub_wire5(13);
-	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 14)    <= sub_wire5(14);
-	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 15)    <= sub_wire5(15);
-	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 16)    <= sub_wire5(16);
-	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 17)    <= sub_wire5(17);
-	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 18)    <= sub_wire5(18);
-	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 19)    <= sub_wire5(19);
-	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 20)    <= sub_wire5(20);
-	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 21)    <= sub_wire5(21);
-	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 22)    <= sub_wire5(22);
-	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 23)    <= sub_wire5(23);
-	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 24)    <= sub_wire5(24);
-	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 25)    <= sub_wire5(25);
-	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 26)    <= sub_wire5(26);
-	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 27)    <= sub_wire5(27);
-	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 28)    <= sub_wire5(28);
-	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 29)    <= sub_wire5(29);
-	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 30)    <= sub_wire5(30);
-	sub_wire2(0, 31)    <= sub_wire5(31);
+	sub_wire2(0, 31)    <= sub_wire5(31);
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_pipeline => 4,
+		lpm_pipeline => 4,
-		lpm_size => 4,
+		lpm_size => 4,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 32,
+		lpm_width => 32,
-		lpm_widths => 2
+		lpm_widths => 2
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sel,
+		clock => clock,
-		clock => clock,
+		data => sub_wire2,
-		data => sub_wire2,
+		sel => sel,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
--- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
--- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
+-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
--- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0]
+-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
--- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL "data2x[31..0]"
--- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL "data3x[31..0]"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
--- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
--- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
--- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
--- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
--- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux1.bsf

@@ -1,111 +1,119 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 152 192)
+	(rect 0 0 144 192)
-	(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux1" (rect 43 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(text "inst" (rect 8 177 26 188)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 72 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 72 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 72 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 72 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 104)
+		(pt 0 104)
-		(input)
+		(input)
-		(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 72 104)(line_width 3))
+		(line (pt 0 104)(pt 64 104)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 120)
+		(pt 0 120)
-		(input)
+		(input)
-		(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 72 120)(line_width 3))
+		(line (pt 0 120)(pt 64 120)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 136)
+		(pt 0 136)
-		(input)
+		(input)
-		(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 4 123 67 135)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 72 136)(line_width 3))
+		(line (pt 0 136)(pt 64 136)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 152)
+		(pt 0 152)
-		(input)
+		(input)
-		(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 4 139 67 151)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 72 152)(line_width 3))
+		(line (pt 0 152)(pt 64 152)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 168)
+		(pt 0 168)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 72 168)(line_width 1))
+		(line (pt 0 168)(pt 64 168))
-	)
+	)
-	(port
+	(port
-		(pt 80 192)
+		(pt 72 192)
-		(input)
+		(input)
-		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
-		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical))
-		(line (pt 80 192)(pt 80 180)(line_width 3))
+		(line (pt 72 192)(pt 72 180)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 152 104)
+		(pt 144 104)
-		(output)
+		(output)
-		(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 85 91 142 103)(font "Arial" (font_size 8)))
-		(line (pt 152 104)(pt 88 104)(line_width 3))
+		(line (pt 144 104)(pt 80 104)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 64 24)(pt 64 184))
-		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 64 184)(pt 80 176))
-		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 80 32)(pt 80 176))
-		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 78 168)(pt 72 174)(line_width 1))
+		(line (pt 146 0)(pt 146 194))
-	)
+		(line (pt 0 194)(pt 146 194))
-)
+		(line (pt 0 0)(pt 0 194))
+		(line (pt 64 162)(pt 70 168))
+		(line (pt 70 168)(pt 64 174))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux1.cmp

@@ -1,31 +1,31 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux1
+component lpm_mux1
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux1.inc

@@ -1,32 +1,32 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_mux1 
+FUNCTION lpm_mux1 
-(
+(
-	clock,
+	clock,
-	data0x[15..0],
+	data0x[15..0],
-	data1x[15..0],
+	data1x[15..0],
-	data2x[15..0],
+	data2x[15..0],
-	data3x[15..0],
+	data3x[15..0],
-	data4x[15..0],
+	data4x[15..0],
-	data5x[15..0],
+	data5x[15..0],
-	data6x[15..0],
+	data6x[15..0],
-	data7x[15..0],
+	data7x[15..0],
-	sel[2..0]
+	sel[2..0]
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[15..0]
+	result[15..0]
-);
+);

Video/lpm_mux1.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]

Video/lpm_mux1.vhd

@@ -1,271 +1,272 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux1.vhd
+-- File Name: lpm_mux1.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux1 IS
+ENTITY lpm_mux1 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
+	);
-END lpm_mux1;
+END lpm_mux1;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux1 IS
+ARCHITECTURE SYN OF lpm_mux1 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire9    <= data0x(15 DOWNTO 0);
+	sub_wire9    <= data0x(15 DOWNTO 0);
-	sub_wire8    <= data1x(15 DOWNTO 0);
+	sub_wire8    <= data1x(15 DOWNTO 0);
-	sub_wire7    <= data2x(15 DOWNTO 0);
+	sub_wire7    <= data2x(15 DOWNTO 0);
-	sub_wire6    <= data3x(15 DOWNTO 0);
+	sub_wire6    <= data3x(15 DOWNTO 0);
-	sub_wire5    <= data4x(15 DOWNTO 0);
+	sub_wire5    <= data4x(15 DOWNTO 0);
-	sub_wire4    <= data5x(15 DOWNTO 0);
+	sub_wire4    <= data5x(15 DOWNTO 0);
-	sub_wire3    <= data6x(15 DOWNTO 0);
+	sub_wire3    <= data6x(15 DOWNTO 0);
-	result    <= sub_wire0(15 DOWNTO 0);
+	result    <= sub_wire0(15 DOWNTO 0);
-	sub_wire1    <= data7x(15 DOWNTO 0);
+	sub_wire1    <= data7x(15 DOWNTO 0);
-	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
-	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 1)    <= sub_wire1(1);
-	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 2)    <= sub_wire1(2);
-	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 3)    <= sub_wire1(3);
-	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 4)    <= sub_wire1(4);
-	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 5)    <= sub_wire1(5);
-	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 6)    <= sub_wire1(6);
-	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 7)    <= sub_wire1(7);
-	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 8)    <= sub_wire1(8);
-	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 9)    <= sub_wire1(9);
-	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 10)    <= sub_wire1(10);
-	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 11)    <= sub_wire1(11);
-	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 12)    <= sub_wire1(12);
-	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 13)    <= sub_wire1(13);
-	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 14)    <= sub_wire1(14);
-	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(7, 15)    <= sub_wire1(15);
-	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 0)    <= sub_wire3(0);
-	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 1)    <= sub_wire3(1);
-	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 2)    <= sub_wire3(2);
-	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 3)    <= sub_wire3(3);
-	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 4)    <= sub_wire3(4);
-	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 5)    <= sub_wire3(5);
-	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 6)    <= sub_wire3(6);
-	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 7)    <= sub_wire3(7);
-	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 8)    <= sub_wire3(8);
-	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 9)    <= sub_wire3(9);
-	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 10)    <= sub_wire3(10);
-	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 11)    <= sub_wire3(11);
-	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 12)    <= sub_wire3(12);
-	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 13)    <= sub_wire3(13);
-	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 14)    <= sub_wire3(14);
-	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(6, 15)    <= sub_wire3(15);
-	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 0)    <= sub_wire4(0);
-	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 1)    <= sub_wire4(1);
-	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 2)    <= sub_wire4(2);
-	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 3)    <= sub_wire4(3);
-	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 4)    <= sub_wire4(4);
-	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 5)    <= sub_wire4(5);
-	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 6)    <= sub_wire4(6);
-	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 7)    <= sub_wire4(7);
-	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 8)    <= sub_wire4(8);
-	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 9)    <= sub_wire4(9);
-	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 10)    <= sub_wire4(10);
-	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 11)    <= sub_wire4(11);
-	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 12)    <= sub_wire4(12);
-	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 13)    <= sub_wire4(13);
-	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 14)    <= sub_wire4(14);
-	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(5, 15)    <= sub_wire4(15);
-	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 0)    <= sub_wire5(0);
-	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 1)    <= sub_wire5(1);
-	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 2)    <= sub_wire5(2);
-	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 3)    <= sub_wire5(3);
-	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 4)    <= sub_wire5(4);
-	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 5)    <= sub_wire5(5);
-	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 6)    <= sub_wire5(6);
-	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 7)    <= sub_wire5(7);
-	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 8)    <= sub_wire5(8);
-	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 9)    <= sub_wire5(9);
-	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 10)    <= sub_wire5(10);
-	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 11)    <= sub_wire5(11);
-	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 12)    <= sub_wire5(12);
-	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 13)    <= sub_wire5(13);
-	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 14)    <= sub_wire5(14);
-	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(4, 15)    <= sub_wire5(15);
-	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 0)    <= sub_wire6(0);
-	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 1)    <= sub_wire6(1);
-	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 2)    <= sub_wire6(2);
-	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 3)    <= sub_wire6(3);
-	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 4)    <= sub_wire6(4);
-	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 5)    <= sub_wire6(5);
-	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 6)    <= sub_wire6(6);
-	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 7)    <= sub_wire6(7);
-	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 8)    <= sub_wire6(8);
-	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 9)    <= sub_wire6(9);
-	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 10)    <= sub_wire6(10);
-	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 11)    <= sub_wire6(11);
-	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 12)    <= sub_wire6(12);
-	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 13)    <= sub_wire6(13);
-	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 14)    <= sub_wire6(14);
-	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(3, 15)    <= sub_wire6(15);
-	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 0)    <= sub_wire7(0);
-	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 1)    <= sub_wire7(1);
-	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 2)    <= sub_wire7(2);
-	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 3)    <= sub_wire7(3);
-	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 4)    <= sub_wire7(4);
-	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 5)    <= sub_wire7(5);
-	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 6)    <= sub_wire7(6);
-	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 7)    <= sub_wire7(7);
-	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 8)    <= sub_wire7(8);
-	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 9)    <= sub_wire7(9);
-	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 10)    <= sub_wire7(10);
-	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 11)    <= sub_wire7(11);
-	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 12)    <= sub_wire7(12);
-	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 13)    <= sub_wire7(13);
-	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 14)    <= sub_wire7(14);
-	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(2, 15)    <= sub_wire7(15);
-	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 0)    <= sub_wire8(0);
-	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 1)    <= sub_wire8(1);
-	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 2)    <= sub_wire8(2);
-	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 3)    <= sub_wire8(3);
-	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 4)    <= sub_wire8(4);
-	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 5)    <= sub_wire8(5);
-	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 6)    <= sub_wire8(6);
-	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 7)    <= sub_wire8(7);
-	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 8)    <= sub_wire8(8);
-	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 9)    <= sub_wire8(9);
-	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 10)    <= sub_wire8(10);
-	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 11)    <= sub_wire8(11);
-	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 12)    <= sub_wire8(12);
-	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 13)    <= sub_wire8(13);
-	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 14)    <= sub_wire8(14);
-	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(1, 15)    <= sub_wire8(15);
-	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 0)    <= sub_wire9(0);
-	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 1)    <= sub_wire9(1);
-	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 2)    <= sub_wire9(2);
-	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 3)    <= sub_wire9(3);
-	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 4)    <= sub_wire9(4);
-	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 5)    <= sub_wire9(5);
-	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 6)    <= sub_wire9(6);
-	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 7)    <= sub_wire9(7);
-	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 8)    <= sub_wire9(8);
-	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 9)    <= sub_wire9(9);
-	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 10)    <= sub_wire9(10);
-	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 11)    <= sub_wire9(11);
-	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 12)    <= sub_wire9(12);
-	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 13)    <= sub_wire9(13);
-	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 14)    <= sub_wire9(14);
-	sub_wire2(0, 15)    <= sub_wire9(15);
+	sub_wire2(0, 15)    <= sub_wire9(15);
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_pipeline => 4,
+		lpm_pipeline => 4,
-		lpm_size => 8,
+		lpm_size => 8,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 16,
+		lpm_width => 16,
-		lpm_widths => 3
+		lpm_widths => 3
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sel,
+		clock => clock,
-		clock => clock,
+		data => sub_wire2,
-		data => sub_wire2,
+		sel => sel,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
--- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
--- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
+-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
--- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
+-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
--- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
+-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
--- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
+-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
--- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
+-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
--- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
+-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
--- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
--- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
--- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
--- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
--- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
--- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux2.bsf

@@ -1,167 +1,175 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 144 320)
+	(rect 0 0 144 320)
-	(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux2" (rect 43 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 304 25 316)(font "Arial" ))
+	(text "inst" (rect 8 305 26 316)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 72 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 72 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 72 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 72 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
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+	)
-	(port
+	(port
-		(pt 0 104)
+		(pt 0 104)
-		(input)
+		(input)
-		(text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
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-		(text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 72 104)(line_width 3))
+		(line (pt 0 104)(pt 64 104)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 120)
+		(pt 0 120)
-		(input)
+		(input)
-		(text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 72 120)(line_width 3))
+		(line (pt 0 120)(pt 64 120)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 136)
+		(pt 0 136)
-		(input)
+		(input)
-		(text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
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+	)
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+	(port
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+		(pt 0 152)
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+		(input)
-		(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 152)(pt 64 152)(line_width 3))
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+	)
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+	(port
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+		(pt 0 168)
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+		(input)
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+		(line (pt 0 168)(pt 64 168)(line_width 3))
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+	)
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+		(pt 0 184)
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+		(input)
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+		(text "data6x[7..0]" (rect 4 171 61 183)(font "Arial" (font_size 8)))
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+	)
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+		(pt 0 200)
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+	)
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+	)
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+		(pt 0 248)
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+		(input)
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+	)
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+	(port
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+		(pt 0 264)
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+		(input)
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+	)
-	(port
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+		(pt 0 280)
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-		(text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8)))
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+	)
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+	(port
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+		(input)
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+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
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+		(line (pt 0 296)(pt 64 296))
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-	(port
+	(port
-		(pt 80 320)
+		(pt 72 320)
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+		(input)
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+		(text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
-		(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 66 265 78 303)(font "Arial" (font_size 8))(vertical))
-		(line (pt 80 320)(pt 80 308)(line_width 3))
+		(line (pt 72 320)(pt 72 308)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 144 168)
+		(pt 144 168)
-		(output)
+		(output)
-		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 91 155 142 167)(font "Arial" (font_size 8)))
-		(line (pt 144 168)(pt 88 168)(line_width 3))
+		(line (pt 144 168)(pt 80 168)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 72 24)(pt 72 312)(line_width 1))
+		(line (pt 64 24)(pt 64 312))
-		(line (pt 88 32)(pt 88 304)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 64 312)(pt 80 304))
-		(line (pt 72 312)(pt 88 304)(line_width 1))
+		(line (pt 80 32)(pt 80 304))
-		(line (pt 72 290)(pt 78 296)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 78 296)(pt 72 302)(line_width 1))
+		(line (pt 146 0)(pt 146 322))
-	)
+		(line (pt 0 322)(pt 146 322))
-)
+		(line (pt 0 0)(pt 0 322))
+		(line (pt 64 290)(pt 70 296))
+		(line (pt 70 296)(pt 64 302))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux2.cmp

@@ -1,39 +1,39 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux2
+component lpm_mux2
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux2.inc

@@ -1,40 +1,40 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_mux2 
+FUNCTION lpm_mux2 
-(
+(
-	clock,
+	clock,
-	data0x[7..0],
+	data0x[7..0],
-	data10x[7..0],
+	data10x[7..0],
-	data11x[7..0],
+	data11x[7..0],
-	data12x[7..0],
+	data12x[7..0],
-	data13x[7..0],
+	data13x[7..0],
-	data14x[7..0],
+	data14x[7..0],
-	data15x[7..0],
+	data15x[7..0],
-	data1x[7..0],
+	data1x[7..0],
-	data2x[7..0],
+	data2x[7..0],
-	data3x[7..0],
+	data3x[7..0],
-	data4x[7..0],
+	data4x[7..0],
-	data5x[7..0],
+	data5x[7..0],
-	data6x[7..0],
+	data6x[7..0],
-	data7x[7..0],
+	data7x[7..0],
-	data8x[7..0],
+	data8x[7..0],
-	data9x[7..0],
+	data9x[7..0],
-	sel[3..0]
+	sel[3..0]
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[7..0]
+	result[7..0]
-);
+);

Video/lpm_mux2.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"]

Video/lpm_mux2.vhd

@@ -1,311 +1,312 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux2.vhd
+-- File Name: lpm_mux2.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux2 IS
+ENTITY lpm_mux2 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
+	);
-END lpm_mux2;
+END lpm_mux2;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux2 IS
+ARCHITECTURE SYN OF lpm_mux2 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire17    <= data0x(7 DOWNTO 0);
+	sub_wire17    <= data0x(7 DOWNTO 0);
-	sub_wire16    <= data1x(7 DOWNTO 0);
+	sub_wire16    <= data1x(7 DOWNTO 0);
-	sub_wire15    <= data2x(7 DOWNTO 0);
+	sub_wire15    <= data2x(7 DOWNTO 0);
-	sub_wire14    <= data3x(7 DOWNTO 0);
+	sub_wire14    <= data3x(7 DOWNTO 0);
-	sub_wire13    <= data4x(7 DOWNTO 0);
+	sub_wire13    <= data4x(7 DOWNTO 0);
-	sub_wire12    <= data5x(7 DOWNTO 0);
+	sub_wire12    <= data5x(7 DOWNTO 0);
-	sub_wire11    <= data6x(7 DOWNTO 0);
+	sub_wire11    <= data6x(7 DOWNTO 0);
-	sub_wire10    <= data7x(7 DOWNTO 0);
+	sub_wire10    <= data7x(7 DOWNTO 0);
-	sub_wire9    <= data8x(7 DOWNTO 0);
+	sub_wire9    <= data8x(7 DOWNTO 0);
-	sub_wire8    <= data9x(7 DOWNTO 0);
+	sub_wire8    <= data9x(7 DOWNTO 0);
-	sub_wire7    <= data10x(7 DOWNTO 0);
+	sub_wire7    <= data10x(7 DOWNTO 0);
-	sub_wire6    <= data11x(7 DOWNTO 0);
+	sub_wire6    <= data11x(7 DOWNTO 0);
-	sub_wire5    <= data12x(7 DOWNTO 0);
+	sub_wire5    <= data12x(7 DOWNTO 0);
-	sub_wire4    <= data13x(7 DOWNTO 0);
+	sub_wire4    <= data13x(7 DOWNTO 0);
-	sub_wire3    <= data14x(7 DOWNTO 0);
+	sub_wire3    <= data14x(7 DOWNTO 0);
-	result    <= sub_wire0(7 DOWNTO 0);
+	result    <= sub_wire0(7 DOWNTO 0);
-	sub_wire1    <= data15x(7 DOWNTO 0);
+	sub_wire1    <= data15x(7 DOWNTO 0);
-	sub_wire2(15, 0)    <= sub_wire1(0);
+	sub_wire2(15, 0)    <= sub_wire1(0);
-	sub_wire2(15, 1)    <= sub_wire1(1);
+	sub_wire2(15, 1)    <= sub_wire1(1);
-	sub_wire2(15, 2)    <= sub_wire1(2);
+	sub_wire2(15, 2)    <= sub_wire1(2);
-	sub_wire2(15, 3)    <= sub_wire1(3);
+	sub_wire2(15, 3)    <= sub_wire1(3);
-	sub_wire2(15, 4)    <= sub_wire1(4);
+	sub_wire2(15, 4)    <= sub_wire1(4);
-	sub_wire2(15, 5)    <= sub_wire1(5);
+	sub_wire2(15, 5)    <= sub_wire1(5);
-	sub_wire2(15, 6)    <= sub_wire1(6);
+	sub_wire2(15, 6)    <= sub_wire1(6);
-	sub_wire2(15, 7)    <= sub_wire1(7);
+	sub_wire2(15, 7)    <= sub_wire1(7);
-	sub_wire2(14, 0)    <= sub_wire3(0);
+	sub_wire2(14, 0)    <= sub_wire3(0);
-	sub_wire2(14, 1)    <= sub_wire3(1);
+	sub_wire2(14, 1)    <= sub_wire3(1);
-	sub_wire2(14, 2)    <= sub_wire3(2);
+	sub_wire2(14, 2)    <= sub_wire3(2);
-	sub_wire2(14, 3)    <= sub_wire3(3);
+	sub_wire2(14, 3)    <= sub_wire3(3);
-	sub_wire2(14, 4)    <= sub_wire3(4);
+	sub_wire2(14, 4)    <= sub_wire3(4);
-	sub_wire2(14, 5)    <= sub_wire3(5);
+	sub_wire2(14, 5)    <= sub_wire3(5);
-	sub_wire2(14, 6)    <= sub_wire3(6);
+	sub_wire2(14, 6)    <= sub_wire3(6);
-	sub_wire2(14, 7)    <= sub_wire3(7);
+	sub_wire2(14, 7)    <= sub_wire3(7);
-	sub_wire2(13, 0)    <= sub_wire4(0);
+	sub_wire2(13, 0)    <= sub_wire4(0);
-	sub_wire2(13, 1)    <= sub_wire4(1);
+	sub_wire2(13, 1)    <= sub_wire4(1);
-	sub_wire2(13, 2)    <= sub_wire4(2);
+	sub_wire2(13, 2)    <= sub_wire4(2);
-	sub_wire2(13, 3)    <= sub_wire4(3);
+	sub_wire2(13, 3)    <= sub_wire4(3);
-	sub_wire2(13, 4)    <= sub_wire4(4);
+	sub_wire2(13, 4)    <= sub_wire4(4);
-	sub_wire2(13, 5)    <= sub_wire4(5);
+	sub_wire2(13, 5)    <= sub_wire4(5);
-	sub_wire2(13, 6)    <= sub_wire4(6);
+	sub_wire2(13, 6)    <= sub_wire4(6);
-	sub_wire2(13, 7)    <= sub_wire4(7);
+	sub_wire2(13, 7)    <= sub_wire4(7);
-	sub_wire2(12, 0)    <= sub_wire5(0);
+	sub_wire2(12, 0)    <= sub_wire5(0);
-	sub_wire2(12, 1)    <= sub_wire5(1);
+	sub_wire2(12, 1)    <= sub_wire5(1);
-	sub_wire2(12, 2)    <= sub_wire5(2);
+	sub_wire2(12, 2)    <= sub_wire5(2);
-	sub_wire2(12, 3)    <= sub_wire5(3);
+	sub_wire2(12, 3)    <= sub_wire5(3);
-	sub_wire2(12, 4)    <= sub_wire5(4);
+	sub_wire2(12, 4)    <= sub_wire5(4);
-	sub_wire2(12, 5)    <= sub_wire5(5);
+	sub_wire2(12, 5)    <= sub_wire5(5);
-	sub_wire2(12, 6)    <= sub_wire5(6);
+	sub_wire2(12, 6)    <= sub_wire5(6);
-	sub_wire2(12, 7)    <= sub_wire5(7);
+	sub_wire2(12, 7)    <= sub_wire5(7);
-	sub_wire2(11, 0)    <= sub_wire6(0);
+	sub_wire2(11, 0)    <= sub_wire6(0);
-	sub_wire2(11, 1)    <= sub_wire6(1);
+	sub_wire2(11, 1)    <= sub_wire6(1);
-	sub_wire2(11, 2)    <= sub_wire6(2);
+	sub_wire2(11, 2)    <= sub_wire6(2);
-	sub_wire2(11, 3)    <= sub_wire6(3);
+	sub_wire2(11, 3)    <= sub_wire6(3);
-	sub_wire2(11, 4)    <= sub_wire6(4);
+	sub_wire2(11, 4)    <= sub_wire6(4);
-	sub_wire2(11, 5)    <= sub_wire6(5);
+	sub_wire2(11, 5)    <= sub_wire6(5);
-	sub_wire2(11, 6)    <= sub_wire6(6);
+	sub_wire2(11, 6)    <= sub_wire6(6);
-	sub_wire2(11, 7)    <= sub_wire6(7);
+	sub_wire2(11, 7)    <= sub_wire6(7);
-	sub_wire2(10, 0)    <= sub_wire7(0);
+	sub_wire2(10, 0)    <= sub_wire7(0);
-	sub_wire2(10, 1)    <= sub_wire7(1);
+	sub_wire2(10, 1)    <= sub_wire7(1);
-	sub_wire2(10, 2)    <= sub_wire7(2);
+	sub_wire2(10, 2)    <= sub_wire7(2);
-	sub_wire2(10, 3)    <= sub_wire7(3);
+	sub_wire2(10, 3)    <= sub_wire7(3);
-	sub_wire2(10, 4)    <= sub_wire7(4);
+	sub_wire2(10, 4)    <= sub_wire7(4);
-	sub_wire2(10, 5)    <= sub_wire7(5);
+	sub_wire2(10, 5)    <= sub_wire7(5);
-	sub_wire2(10, 6)    <= sub_wire7(6);
+	sub_wire2(10, 6)    <= sub_wire7(6);
-	sub_wire2(10, 7)    <= sub_wire7(7);
+	sub_wire2(10, 7)    <= sub_wire7(7);
-	sub_wire2(9, 0)    <= sub_wire8(0);
+	sub_wire2(9, 0)    <= sub_wire8(0);
-	sub_wire2(9, 1)    <= sub_wire8(1);
+	sub_wire2(9, 1)    <= sub_wire8(1);
-	sub_wire2(9, 2)    <= sub_wire8(2);
+	sub_wire2(9, 2)    <= sub_wire8(2);
-	sub_wire2(9, 3)    <= sub_wire8(3);
+	sub_wire2(9, 3)    <= sub_wire8(3);
-	sub_wire2(9, 4)    <= sub_wire8(4);
+	sub_wire2(9, 4)    <= sub_wire8(4);
-	sub_wire2(9, 5)    <= sub_wire8(5);
+	sub_wire2(9, 5)    <= sub_wire8(5);
-	sub_wire2(9, 6)    <= sub_wire8(6);
+	sub_wire2(9, 6)    <= sub_wire8(6);
-	sub_wire2(9, 7)    <= sub_wire8(7);
+	sub_wire2(9, 7)    <= sub_wire8(7);
-	sub_wire2(8, 0)    <= sub_wire9(0);
+	sub_wire2(8, 0)    <= sub_wire9(0);
-	sub_wire2(8, 1)    <= sub_wire9(1);
+	sub_wire2(8, 1)    <= sub_wire9(1);
-	sub_wire2(8, 2)    <= sub_wire9(2);
+	sub_wire2(8, 2)    <= sub_wire9(2);
-	sub_wire2(8, 3)    <= sub_wire9(3);
+	sub_wire2(8, 3)    <= sub_wire9(3);
-	sub_wire2(8, 4)    <= sub_wire9(4);
+	sub_wire2(8, 4)    <= sub_wire9(4);
-	sub_wire2(8, 5)    <= sub_wire9(5);
+	sub_wire2(8, 5)    <= sub_wire9(5);
-	sub_wire2(8, 6)    <= sub_wire9(6);
+	sub_wire2(8, 6)    <= sub_wire9(6);
-	sub_wire2(8, 7)    <= sub_wire9(7);
+	sub_wire2(8, 7)    <= sub_wire9(7);
-	sub_wire2(7, 0)    <= sub_wire10(0);
+	sub_wire2(7, 0)    <= sub_wire10(0);
-	sub_wire2(7, 1)    <= sub_wire10(1);
+	sub_wire2(7, 1)    <= sub_wire10(1);
-	sub_wire2(7, 2)    <= sub_wire10(2);
+	sub_wire2(7, 2)    <= sub_wire10(2);
-	sub_wire2(7, 3)    <= sub_wire10(3);
+	sub_wire2(7, 3)    <= sub_wire10(3);
-	sub_wire2(7, 4)    <= sub_wire10(4);
+	sub_wire2(7, 4)    <= sub_wire10(4);
-	sub_wire2(7, 5)    <= sub_wire10(5);
+	sub_wire2(7, 5)    <= sub_wire10(5);
-	sub_wire2(7, 6)    <= sub_wire10(6);
+	sub_wire2(7, 6)    <= sub_wire10(6);
-	sub_wire2(7, 7)    <= sub_wire10(7);
+	sub_wire2(7, 7)    <= sub_wire10(7);
-	sub_wire2(6, 0)    <= sub_wire11(0);
+	sub_wire2(6, 0)    <= sub_wire11(0);
-	sub_wire2(6, 1)    <= sub_wire11(1);
+	sub_wire2(6, 1)    <= sub_wire11(1);
-	sub_wire2(6, 2)    <= sub_wire11(2);
+	sub_wire2(6, 2)    <= sub_wire11(2);
-	sub_wire2(6, 3)    <= sub_wire11(3);
+	sub_wire2(6, 3)    <= sub_wire11(3);
-	sub_wire2(6, 4)    <= sub_wire11(4);
+	sub_wire2(6, 4)    <= sub_wire11(4);
-	sub_wire2(6, 5)    <= sub_wire11(5);
+	sub_wire2(6, 5)    <= sub_wire11(5);
-	sub_wire2(6, 6)    <= sub_wire11(6);
+	sub_wire2(6, 6)    <= sub_wire11(6);
-	sub_wire2(6, 7)    <= sub_wire11(7);
+	sub_wire2(6, 7)    <= sub_wire11(7);
-	sub_wire2(5, 0)    <= sub_wire12(0);
+	sub_wire2(5, 0)    <= sub_wire12(0);
-	sub_wire2(5, 1)    <= sub_wire12(1);
+	sub_wire2(5, 1)    <= sub_wire12(1);
-	sub_wire2(5, 2)    <= sub_wire12(2);
+	sub_wire2(5, 2)    <= sub_wire12(2);
-	sub_wire2(5, 3)    <= sub_wire12(3);
+	sub_wire2(5, 3)    <= sub_wire12(3);
-	sub_wire2(5, 4)    <= sub_wire12(4);
+	sub_wire2(5, 4)    <= sub_wire12(4);
-	sub_wire2(5, 5)    <= sub_wire12(5);
+	sub_wire2(5, 5)    <= sub_wire12(5);
-	sub_wire2(5, 6)    <= sub_wire12(6);
+	sub_wire2(5, 6)    <= sub_wire12(6);
-	sub_wire2(5, 7)    <= sub_wire12(7);
+	sub_wire2(5, 7)    <= sub_wire12(7);
-	sub_wire2(4, 0)    <= sub_wire13(0);
+	sub_wire2(4, 0)    <= sub_wire13(0);
-	sub_wire2(4, 1)    <= sub_wire13(1);
+	sub_wire2(4, 1)    <= sub_wire13(1);
-	sub_wire2(4, 2)    <= sub_wire13(2);
+	sub_wire2(4, 2)    <= sub_wire13(2);
-	sub_wire2(4, 3)    <= sub_wire13(3);
+	sub_wire2(4, 3)    <= sub_wire13(3);
-	sub_wire2(4, 4)    <= sub_wire13(4);
+	sub_wire2(4, 4)    <= sub_wire13(4);
-	sub_wire2(4, 5)    <= sub_wire13(5);
+	sub_wire2(4, 5)    <= sub_wire13(5);
-	sub_wire2(4, 6)    <= sub_wire13(6);
+	sub_wire2(4, 6)    <= sub_wire13(6);
-	sub_wire2(4, 7)    <= sub_wire13(7);
+	sub_wire2(4, 7)    <= sub_wire13(7);
-	sub_wire2(3, 0)    <= sub_wire14(0);
+	sub_wire2(3, 0)    <= sub_wire14(0);
-	sub_wire2(3, 1)    <= sub_wire14(1);
+	sub_wire2(3, 1)    <= sub_wire14(1);
-	sub_wire2(3, 2)    <= sub_wire14(2);
+	sub_wire2(3, 2)    <= sub_wire14(2);
-	sub_wire2(3, 3)    <= sub_wire14(3);
+	sub_wire2(3, 3)    <= sub_wire14(3);
-	sub_wire2(3, 4)    <= sub_wire14(4);
+	sub_wire2(3, 4)    <= sub_wire14(4);
-	sub_wire2(3, 5)    <= sub_wire14(5);
+	sub_wire2(3, 5)    <= sub_wire14(5);
-	sub_wire2(3, 6)    <= sub_wire14(6);
+	sub_wire2(3, 6)    <= sub_wire14(6);
-	sub_wire2(3, 7)    <= sub_wire14(7);
+	sub_wire2(3, 7)    <= sub_wire14(7);
-	sub_wire2(2, 0)    <= sub_wire15(0);
+	sub_wire2(2, 0)    <= sub_wire15(0);
-	sub_wire2(2, 1)    <= sub_wire15(1);
+	sub_wire2(2, 1)    <= sub_wire15(1);
-	sub_wire2(2, 2)    <= sub_wire15(2);
+	sub_wire2(2, 2)    <= sub_wire15(2);
-	sub_wire2(2, 3)    <= sub_wire15(3);
+	sub_wire2(2, 3)    <= sub_wire15(3);
-	sub_wire2(2, 4)    <= sub_wire15(4);
+	sub_wire2(2, 4)    <= sub_wire15(4);
-	sub_wire2(2, 5)    <= sub_wire15(5);
+	sub_wire2(2, 5)    <= sub_wire15(5);
-	sub_wire2(2, 6)    <= sub_wire15(6);
+	sub_wire2(2, 6)    <= sub_wire15(6);
-	sub_wire2(2, 7)    <= sub_wire15(7);
+	sub_wire2(2, 7)    <= sub_wire15(7);
-	sub_wire2(1, 0)    <= sub_wire16(0);
+	sub_wire2(1, 0)    <= sub_wire16(0);
-	sub_wire2(1, 1)    <= sub_wire16(1);
+	sub_wire2(1, 1)    <= sub_wire16(1);
-	sub_wire2(1, 2)    <= sub_wire16(2);
+	sub_wire2(1, 2)    <= sub_wire16(2);
-	sub_wire2(1, 3)    <= sub_wire16(3);
+	sub_wire2(1, 3)    <= sub_wire16(3);
-	sub_wire2(1, 4)    <= sub_wire16(4);
+	sub_wire2(1, 4)    <= sub_wire16(4);
-	sub_wire2(1, 5)    <= sub_wire16(5);
+	sub_wire2(1, 5)    <= sub_wire16(5);
-	sub_wire2(1, 6)    <= sub_wire16(6);
+	sub_wire2(1, 6)    <= sub_wire16(6);
-	sub_wire2(1, 7)    <= sub_wire16(7);
+	sub_wire2(1, 7)    <= sub_wire16(7);
-	sub_wire2(0, 0)    <= sub_wire17(0);
+	sub_wire2(0, 0)    <= sub_wire17(0);
-	sub_wire2(0, 1)    <= sub_wire17(1);
+	sub_wire2(0, 1)    <= sub_wire17(1);
-	sub_wire2(0, 2)    <= sub_wire17(2);
+	sub_wire2(0, 2)    <= sub_wire17(2);
-	sub_wire2(0, 3)    <= sub_wire17(3);
+	sub_wire2(0, 3)    <= sub_wire17(3);
-	sub_wire2(0, 4)    <= sub_wire17(4);
+	sub_wire2(0, 4)    <= sub_wire17(4);
-	sub_wire2(0, 5)    <= sub_wire17(5);
+	sub_wire2(0, 5)    <= sub_wire17(5);
-	sub_wire2(0, 6)    <= sub_wire17(6);
+	sub_wire2(0, 6)    <= sub_wire17(6);
-	sub_wire2(0, 7)    <= sub_wire17(7);
+	sub_wire2(0, 7)    <= sub_wire17(7);
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_pipeline => 2,
+		lpm_pipeline => 2,
-		lpm_size => 16,
+		lpm_size => 16,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 8,
+		lpm_width => 8,
-		lpm_widths => 4
+		lpm_widths => 4
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sel,
+		clock => clock,
-		clock => clock,
+		data => sub_wire2,
-		data => sub_wire2,
+		sel => sel,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
--- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0]
+-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
--- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0]
+-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]"
--- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0]
+-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]"
--- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0]
+-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]"
--- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0]
+-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]"
--- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
+-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]"
--- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
+-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]"
--- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
+-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
--- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0]
+-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
--- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0]
+-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
--- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0]
+-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]"
--- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0]
+-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]"
--- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0]
+-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]"
--- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0]
+-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]"
--- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]"
--- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
+-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
--- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
--- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
--- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
--- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux3.bsf

@@ -1,60 +1,68 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 80 80)
+	(rect 0 0 80 80)
-	(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux3" (rect 11 0 85 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 0 0 33 13)(font "Arial" (font_size 8)))
-		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 32 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 32 40)(line_width 1))
+		(line (pt 0 40)(pt 32 40))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 0 0 33 13)(font "Arial" (font_size 8)))
-		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 32 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 32 56)(line_width 1))
+		(line (pt 0 56)(pt 32 56))
-	)
+	)
-	(port
+	(port
-		(pt 40 80)
+		(pt 40 80)
-		(input)
+		(input)
-		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
-		(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
+		(text "sel" (rect 34 49 46 63)(font "Arial" (font_size 8))(vertical))
-		(line (pt 40 80)(pt 40 68)(line_width 1))
+		(line (pt 40 80)(pt 40 68))
-	)
+	)
-	(port
+	(port
-		(pt 80 48)
+		(pt 80 48)
-		(output)
+		(output)
-		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 0 0 33 13)(font "Arial" (font_size 8)))
-		(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
+		(text "result" (rect 51 35 78 47)(font "Arial" (font_size 8)))
-		(line (pt 80 48)(pt 48 48)(line_width 1))
+		(line (pt 80 48)(pt 48 48))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 32 24)(pt 32 72)(line_width 1))
+		(line (pt 32 24)(pt 32 72))
-		(line (pt 48 32)(pt 48 64)(line_width 1))
+		(line (pt 32 24)(pt 48 32))
-		(line (pt 32 24)(pt 48 32)(line_width 1))
+		(line (pt 32 72)(pt 48 64))
-		(line (pt 32 72)(pt 48 64)(line_width 1))
+		(line (pt 48 32)(pt 48 64))
-	)
+		(line (pt 0 0)(pt 82 0))
-)
+		(line (pt 82 0)(pt 82 82))
+		(line (pt 0 82)(pt 82 82))
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux3.cmp

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux3
+component lpm_mux3
-	PORT
+	PORT
-	(
+	(
-		data0		: IN STD_LOGIC ;
+		data0		: IN STD_LOGIC ;
-		data1		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC 
+		result		: OUT STD_LOGIC 
-	);
+	);
-end component;
+end component;

Video/lpm_mux3.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]

Video/lpm_mux3.vhd

@@ -1,115 +1,116 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux3.vhd
+-- File Name: lpm_mux3.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux3 IS
+ENTITY lpm_mux3 IS
-	PORT
+	PORT
-	(
+	(
-		data0		: IN STD_LOGIC ;
+		data0		: IN STD_LOGIC ;
-		data1		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC 
+		result		: OUT STD_LOGIC 
-	);
+	);
-END lpm_mux3;
+END lpm_mux3;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux3 IS
+ARCHITECTURE SYN OF lpm_mux3 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire6    <= data0;
+	sub_wire4    <= data0;
-	sub_wire1    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(0);
-	result    <= sub_wire1;
+	result    <= sub_wire1;
-	sub_wire2    <= sel;
+	sub_wire2    <= data1;
-	sub_wire3(0)    <= sub_wire2;
+	sub_wire3(1, 0)    <= sub_wire2;
-	sub_wire4    <= data1;
+	sub_wire3(0, 0)    <= sub_wire4;
-	sub_wire5(1, 0)    <= sub_wire4;
+	sub_wire5    <= sel;
-	sub_wire5(0, 0)    <= sub_wire6;
+	sub_wire6(0)    <= sub_wire5;
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_size => 2,
+		lpm_size => 2,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 1,
+		lpm_width => 1,
-		lpm_widths => 1
+		lpm_widths => 1
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sub_wire3,
+		data => sub_wire3,
-		data => sub_wire5,
+		sel => sub_wire6,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
--- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
--- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
--- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
--- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux4.bsf

@@ -1,60 +1,68 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 136 80)
+	(rect 0 0 144 80)
-	(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux4" (rect 43 0 118 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 4 27 61 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 64 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
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+		(text "data0x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 4 43 61 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 64 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 72 80)
+		(pt 72 80)
-		(input)
+		(input)
-		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
-		(text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8)))
+		(text "sel" (rect 66 49 78 63)(font "Arial" (font_size 8))(vertical))
-		(line (pt 72 80)(pt 72 68)(line_width 1))
+		(line (pt 72 80)(pt 72 68))
-	)
+	)
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+	(port
-		(pt 136 48)
+		(pt 144 48)
-		(output)
+		(output)
-		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
-		(text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 91 35 142 47)(font "Arial" (font_size 8)))
-		(line (pt 136 48)(pt 80 48)(line_width 3))
+		(line (pt 144 48)(pt 80 48)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 64 24)(pt 64 72)(line_width 1))
+		(line (pt 64 24)(pt 64 72))
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-		(line (pt 64 72)(pt 80 64)(line_width 1))
+		(line (pt 80 32)(pt 80 64))
-	)
+		(line (pt 0 0)(pt 146 0))
-)
+		(line (pt 146 0)(pt 146 82))
+		(line (pt 0 82)(pt 146 82))
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux4.cmp

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux4
+component lpm_mux4
-	PORT
+	PORT
-	(
+	(
-		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux4.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]

Video/lpm_mux4.vhd

@@ -1,125 +1,126 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux4.vhd
+-- File Name: lpm_mux4.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux4 IS
+ENTITY lpm_mux4 IS
-	PORT
+	PORT
-	(
+	(
-		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
-	);
+	);
-END lpm_mux4;
+END lpm_mux4;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux4 IS
+ARCHITECTURE SYN OF lpm_mux4 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (6 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire5    <= data0x(6 DOWNTO 0);
+	sub_wire3    <= data0x(6 DOWNTO 0);
-	result    <= sub_wire0(6 DOWNTO 0);
+	result    <= sub_wire0(6 DOWNTO 0);
-	sub_wire1    <= sel;
+	sub_wire1    <= data1x(6 DOWNTO 0);
-	sub_wire2(0)    <= sub_wire1;
+	sub_wire2(1, 0)    <= sub_wire1(0);
-	sub_wire3    <= data1x(6 DOWNTO 0);
+	sub_wire2(1, 1)    <= sub_wire1(1);
-	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire2(1, 2)    <= sub_wire1(2);
-	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire2(1, 3)    <= sub_wire1(3);
-	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire2(1, 4)    <= sub_wire1(4);
-	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire2(1, 5)    <= sub_wire1(5);
-	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire2(1, 6)    <= sub_wire1(6);
-	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire2(0, 0)    <= sub_wire3(0);
-	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire2(0, 1)    <= sub_wire3(1);
-	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 2)    <= sub_wire3(2);
-	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 3)    <= sub_wire3(3);
-	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 4)    <= sub_wire3(4);
-	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 5)    <= sub_wire3(5);
-	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 6)    <= sub_wire3(6);
-	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire4    <= sel;
-	sub_wire4(0, 6)    <= sub_wire5(6);
+	sub_wire5(0)    <= sub_wire4;
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_size => 2,
+		lpm_size => 2,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 7,
+		lpm_width => 7,
-		lpm_widths => 1
+		lpm_widths => 1
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sub_wire2,
+		data => sub_wire2,
-		data => sub_wire4,
+		sel => sub_wire5,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0]
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
--- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]"
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]"
--- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
--- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
--- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux5.bsf

@@ -1,74 +1,82 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 152 112)
+	(rect 0 0 144 112)
-	(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux5" (rect 43 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 72 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 72 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 72 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 72 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 80 112)
+		(pt 72 112)
-		(input)
+		(input)
-		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
-		(text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 66 57 78 95)(font "Arial" (font_size 8))(vertical))
-		(line (pt 80 112)(pt 80 100)(line_width 3))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 152 64)
+		(pt 144 64)
-		(output)
+		(output)
-		(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 85 51 142 63)(font "Arial" (font_size 8)))
-		(line (pt 152 64)(pt 88 64)(line_width 3))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 72 24)(pt 72 104)(line_width 1))
+		(line (pt 64 24)(pt 64 104))
-		(line (pt 88 32)(pt 88 96)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 64 104)(pt 80 96))
-		(line (pt 72 104)(pt 88 96)(line_width 1))
+		(line (pt 80 32)(pt 80 96))
-	)
+		(line (pt 0 0)(pt 146 0))
-)
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux5.cmp

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux5
+component lpm_mux5
-	PORT
+	PORT
-	(
+	(
-		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux5.inc

@@ -1,27 +1,27 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_mux5 
+FUNCTION lpm_mux5 
-(
+(
-	data0x[63..0],
+	data0x[63..0],
-	data1x[63..0],
+	data1x[63..0],
-	data2x[63..0],
+	data2x[63..0],
-	data3x[63..0],
+	data3x[63..0],
-	sel[1..0]
+	sel[1..0]
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[63..0]
+	result[63..0]
-);
+);

Video/lpm_mux5.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"]

Video/lpm_mux5.vhd

@@ -1,373 +1,374 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux5.vhd
+-- File Name: lpm_mux5.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux5 IS
+ENTITY lpm_mux5 IS
-	PORT
+	PORT
-	(
+	(
-		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
-	);
+	);
-END lpm_mux5;
+END lpm_mux5;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux5 IS
+ARCHITECTURE SYN OF lpm_mux5 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (63 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (63 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (63 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (63 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire5    <= data0x(63 DOWNTO 0);
+	sub_wire5    <= data0x(63 DOWNTO 0);
-	sub_wire4    <= data1x(63 DOWNTO 0);
+	sub_wire4    <= data1x(63 DOWNTO 0);
-	sub_wire3    <= data2x(63 DOWNTO 0);
+	sub_wire3    <= data2x(63 DOWNTO 0);
-	result    <= sub_wire0(63 DOWNTO 0);
+	result    <= sub_wire0(63 DOWNTO 0);
-	sub_wire1    <= data3x(63 DOWNTO 0);
+	sub_wire1    <= data3x(63 DOWNTO 0);
-	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
-	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 1)    <= sub_wire1(1);
-	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 2)    <= sub_wire1(2);
-	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 3)    <= sub_wire1(3);
-	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 4)    <= sub_wire1(4);
-	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 5)    <= sub_wire1(5);
-	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 6)    <= sub_wire1(6);
-	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 7)    <= sub_wire1(7);
-	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 8)    <= sub_wire1(8);
-	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 9)    <= sub_wire1(9);
-	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 10)    <= sub_wire1(10);
-	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 11)    <= sub_wire1(11);
-	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 12)    <= sub_wire1(12);
-	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 13)    <= sub_wire1(13);
-	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 14)    <= sub_wire1(14);
-	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 15)    <= sub_wire1(15);
-	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 16)    <= sub_wire1(16);
-	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 17)    <= sub_wire1(17);
-	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 18)    <= sub_wire1(18);
-	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 19)    <= sub_wire1(19);
-	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 20)    <= sub_wire1(20);
-	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 21)    <= sub_wire1(21);
-	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 22)    <= sub_wire1(22);
-	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 23)    <= sub_wire1(23);
-	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 24)    <= sub_wire1(24);
-	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 25)    <= sub_wire1(25);
-	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 26)    <= sub_wire1(26);
-	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 27)    <= sub_wire1(27);
-	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 28)    <= sub_wire1(28);
-	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 29)    <= sub_wire1(29);
-	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 30)    <= sub_wire1(30);
-	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(3, 31)    <= sub_wire1(31);
-	sub_wire2(3, 32)    <= sub_wire1(32);
+	sub_wire2(3, 32)    <= sub_wire1(32);
-	sub_wire2(3, 33)    <= sub_wire1(33);
+	sub_wire2(3, 33)    <= sub_wire1(33);
-	sub_wire2(3, 34)    <= sub_wire1(34);
+	sub_wire2(3, 34)    <= sub_wire1(34);
-	sub_wire2(3, 35)    <= sub_wire1(35);
+	sub_wire2(3, 35)    <= sub_wire1(35);
-	sub_wire2(3, 36)    <= sub_wire1(36);
+	sub_wire2(3, 36)    <= sub_wire1(36);
-	sub_wire2(3, 37)    <= sub_wire1(37);
+	sub_wire2(3, 37)    <= sub_wire1(37);
-	sub_wire2(3, 38)    <= sub_wire1(38);
+	sub_wire2(3, 38)    <= sub_wire1(38);
-	sub_wire2(3, 39)    <= sub_wire1(39);
+	sub_wire2(3, 39)    <= sub_wire1(39);
-	sub_wire2(3, 40)    <= sub_wire1(40);
+	sub_wire2(3, 40)    <= sub_wire1(40);
-	sub_wire2(3, 41)    <= sub_wire1(41);
+	sub_wire2(3, 41)    <= sub_wire1(41);
-	sub_wire2(3, 42)    <= sub_wire1(42);
+	sub_wire2(3, 42)    <= sub_wire1(42);
-	sub_wire2(3, 43)    <= sub_wire1(43);
+	sub_wire2(3, 43)    <= sub_wire1(43);
-	sub_wire2(3, 44)    <= sub_wire1(44);
+	sub_wire2(3, 44)    <= sub_wire1(44);
-	sub_wire2(3, 45)    <= sub_wire1(45);
+	sub_wire2(3, 45)    <= sub_wire1(45);
-	sub_wire2(3, 46)    <= sub_wire1(46);
+	sub_wire2(3, 46)    <= sub_wire1(46);
-	sub_wire2(3, 47)    <= sub_wire1(47);
+	sub_wire2(3, 47)    <= sub_wire1(47);
-	sub_wire2(3, 48)    <= sub_wire1(48);
+	sub_wire2(3, 48)    <= sub_wire1(48);
-	sub_wire2(3, 49)    <= sub_wire1(49);
+	sub_wire2(3, 49)    <= sub_wire1(49);
-	sub_wire2(3, 50)    <= sub_wire1(50);
+	sub_wire2(3, 50)    <= sub_wire1(50);
-	sub_wire2(3, 51)    <= sub_wire1(51);
+	sub_wire2(3, 51)    <= sub_wire1(51);
-	sub_wire2(3, 52)    <= sub_wire1(52);
+	sub_wire2(3, 52)    <= sub_wire1(52);
-	sub_wire2(3, 53)    <= sub_wire1(53);
+	sub_wire2(3, 53)    <= sub_wire1(53);
-	sub_wire2(3, 54)    <= sub_wire1(54);
+	sub_wire2(3, 54)    <= sub_wire1(54);
-	sub_wire2(3, 55)    <= sub_wire1(55);
+	sub_wire2(3, 55)    <= sub_wire1(55);
-	sub_wire2(3, 56)    <= sub_wire1(56);
+	sub_wire2(3, 56)    <= sub_wire1(56);
-	sub_wire2(3, 57)    <= sub_wire1(57);
+	sub_wire2(3, 57)    <= sub_wire1(57);
-	sub_wire2(3, 58)    <= sub_wire1(58);
+	sub_wire2(3, 58)    <= sub_wire1(58);
-	sub_wire2(3, 59)    <= sub_wire1(59);
+	sub_wire2(3, 59)    <= sub_wire1(59);
-	sub_wire2(3, 60)    <= sub_wire1(60);
+	sub_wire2(3, 60)    <= sub_wire1(60);
-	sub_wire2(3, 61)    <= sub_wire1(61);
+	sub_wire2(3, 61)    <= sub_wire1(61);
-	sub_wire2(3, 62)    <= sub_wire1(62);
+	sub_wire2(3, 62)    <= sub_wire1(62);
-	sub_wire2(3, 63)    <= sub_wire1(63);
+	sub_wire2(3, 63)    <= sub_wire1(63);
-	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 0)    <= sub_wire3(0);
-	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 1)    <= sub_wire3(1);
-	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 2)    <= sub_wire3(2);
-	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 3)    <= sub_wire3(3);
-	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 4)    <= sub_wire3(4);
-	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 5)    <= sub_wire3(5);
-	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 6)    <= sub_wire3(6);
-	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 7)    <= sub_wire3(7);
-	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 8)    <= sub_wire3(8);
-	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 9)    <= sub_wire3(9);
-	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 10)    <= sub_wire3(10);
-	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 11)    <= sub_wire3(11);
-	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 12)    <= sub_wire3(12);
-	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 13)    <= sub_wire3(13);
-	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 14)    <= sub_wire3(14);
-	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 15)    <= sub_wire3(15);
-	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 16)    <= sub_wire3(16);
-	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 17)    <= sub_wire3(17);
-	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 18)    <= sub_wire3(18);
-	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 19)    <= sub_wire3(19);
-	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 20)    <= sub_wire3(20);
-	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 21)    <= sub_wire3(21);
-	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 22)    <= sub_wire3(22);
-	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 23)    <= sub_wire3(23);
-	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 24)    <= sub_wire3(24);
-	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 25)    <= sub_wire3(25);
-	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 26)    <= sub_wire3(26);
-	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 27)    <= sub_wire3(27);
-	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 28)    <= sub_wire3(28);
-	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 29)    <= sub_wire3(29);
-	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 30)    <= sub_wire3(30);
-	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(2, 31)    <= sub_wire3(31);
-	sub_wire2(2, 32)    <= sub_wire3(32);
+	sub_wire2(2, 32)    <= sub_wire3(32);
-	sub_wire2(2, 33)    <= sub_wire3(33);
+	sub_wire2(2, 33)    <= sub_wire3(33);
-	sub_wire2(2, 34)    <= sub_wire3(34);
+	sub_wire2(2, 34)    <= sub_wire3(34);
-	sub_wire2(2, 35)    <= sub_wire3(35);
+	sub_wire2(2, 35)    <= sub_wire3(35);
-	sub_wire2(2, 36)    <= sub_wire3(36);
+	sub_wire2(2, 36)    <= sub_wire3(36);
-	sub_wire2(2, 37)    <= sub_wire3(37);
+	sub_wire2(2, 37)    <= sub_wire3(37);
-	sub_wire2(2, 38)    <= sub_wire3(38);
+	sub_wire2(2, 38)    <= sub_wire3(38);
-	sub_wire2(2, 39)    <= sub_wire3(39);
+	sub_wire2(2, 39)    <= sub_wire3(39);
-	sub_wire2(2, 40)    <= sub_wire3(40);
+	sub_wire2(2, 40)    <= sub_wire3(40);
-	sub_wire2(2, 41)    <= sub_wire3(41);
+	sub_wire2(2, 41)    <= sub_wire3(41);
-	sub_wire2(2, 42)    <= sub_wire3(42);
+	sub_wire2(2, 42)    <= sub_wire3(42);
-	sub_wire2(2, 43)    <= sub_wire3(43);
+	sub_wire2(2, 43)    <= sub_wire3(43);
-	sub_wire2(2, 44)    <= sub_wire3(44);
+	sub_wire2(2, 44)    <= sub_wire3(44);
-	sub_wire2(2, 45)    <= sub_wire3(45);
+	sub_wire2(2, 45)    <= sub_wire3(45);
-	sub_wire2(2, 46)    <= sub_wire3(46);
+	sub_wire2(2, 46)    <= sub_wire3(46);
-	sub_wire2(2, 47)    <= sub_wire3(47);
+	sub_wire2(2, 47)    <= sub_wire3(47);
-	sub_wire2(2, 48)    <= sub_wire3(48);
+	sub_wire2(2, 48)    <= sub_wire3(48);
-	sub_wire2(2, 49)    <= sub_wire3(49);
+	sub_wire2(2, 49)    <= sub_wire3(49);
-	sub_wire2(2, 50)    <= sub_wire3(50);
+	sub_wire2(2, 50)    <= sub_wire3(50);
-	sub_wire2(2, 51)    <= sub_wire3(51);
+	sub_wire2(2, 51)    <= sub_wire3(51);
-	sub_wire2(2, 52)    <= sub_wire3(52);
+	sub_wire2(2, 52)    <= sub_wire3(52);
-	sub_wire2(2, 53)    <= sub_wire3(53);
+	sub_wire2(2, 53)    <= sub_wire3(53);
-	sub_wire2(2, 54)    <= sub_wire3(54);
+	sub_wire2(2, 54)    <= sub_wire3(54);
-	sub_wire2(2, 55)    <= sub_wire3(55);
+	sub_wire2(2, 55)    <= sub_wire3(55);
-	sub_wire2(2, 56)    <= sub_wire3(56);
+	sub_wire2(2, 56)    <= sub_wire3(56);
-	sub_wire2(2, 57)    <= sub_wire3(57);
+	sub_wire2(2, 57)    <= sub_wire3(57);
-	sub_wire2(2, 58)    <= sub_wire3(58);
+	sub_wire2(2, 58)    <= sub_wire3(58);
-	sub_wire2(2, 59)    <= sub_wire3(59);
+	sub_wire2(2, 59)    <= sub_wire3(59);
-	sub_wire2(2, 60)    <= sub_wire3(60);
+	sub_wire2(2, 60)    <= sub_wire3(60);
-	sub_wire2(2, 61)    <= sub_wire3(61);
+	sub_wire2(2, 61)    <= sub_wire3(61);
-	sub_wire2(2, 62)    <= sub_wire3(62);
+	sub_wire2(2, 62)    <= sub_wire3(62);
-	sub_wire2(2, 63)    <= sub_wire3(63);
+	sub_wire2(2, 63)    <= sub_wire3(63);
-	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 0)    <= sub_wire4(0);
-	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 1)    <= sub_wire4(1);
-	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 2)    <= sub_wire4(2);
-	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 3)    <= sub_wire4(3);
-	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 4)    <= sub_wire4(4);
-	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 5)    <= sub_wire4(5);
-	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 6)    <= sub_wire4(6);
-	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 7)    <= sub_wire4(7);
-	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 8)    <= sub_wire4(8);
-	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 9)    <= sub_wire4(9);
-	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 10)    <= sub_wire4(10);
-	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 11)    <= sub_wire4(11);
-	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 12)    <= sub_wire4(12);
-	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 13)    <= sub_wire4(13);
-	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 14)    <= sub_wire4(14);
-	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 15)    <= sub_wire4(15);
-	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 16)    <= sub_wire4(16);
-	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 17)    <= sub_wire4(17);
-	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 18)    <= sub_wire4(18);
-	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 19)    <= sub_wire4(19);
-	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 20)    <= sub_wire4(20);
-	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 21)    <= sub_wire4(21);
-	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 22)    <= sub_wire4(22);
-	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 23)    <= sub_wire4(23);
-	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 24)    <= sub_wire4(24);
-	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 25)    <= sub_wire4(25);
-	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 26)    <= sub_wire4(26);
-	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 27)    <= sub_wire4(27);
-	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 28)    <= sub_wire4(28);
-	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 29)    <= sub_wire4(29);
-	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 30)    <= sub_wire4(30);
-	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(1, 31)    <= sub_wire4(31);
-	sub_wire2(1, 32)    <= sub_wire4(32);
+	sub_wire2(1, 32)    <= sub_wire4(32);
-	sub_wire2(1, 33)    <= sub_wire4(33);
+	sub_wire2(1, 33)    <= sub_wire4(33);
-	sub_wire2(1, 34)    <= sub_wire4(34);
+	sub_wire2(1, 34)    <= sub_wire4(34);
-	sub_wire2(1, 35)    <= sub_wire4(35);
+	sub_wire2(1, 35)    <= sub_wire4(35);
-	sub_wire2(1, 36)    <= sub_wire4(36);
+	sub_wire2(1, 36)    <= sub_wire4(36);
-	sub_wire2(1, 37)    <= sub_wire4(37);
+	sub_wire2(1, 37)    <= sub_wire4(37);
-	sub_wire2(1, 38)    <= sub_wire4(38);
+	sub_wire2(1, 38)    <= sub_wire4(38);
-	sub_wire2(1, 39)    <= sub_wire4(39);
+	sub_wire2(1, 39)    <= sub_wire4(39);
-	sub_wire2(1, 40)    <= sub_wire4(40);
+	sub_wire2(1, 40)    <= sub_wire4(40);
-	sub_wire2(1, 41)    <= sub_wire4(41);
+	sub_wire2(1, 41)    <= sub_wire4(41);
-	sub_wire2(1, 42)    <= sub_wire4(42);
+	sub_wire2(1, 42)    <= sub_wire4(42);
-	sub_wire2(1, 43)    <= sub_wire4(43);
+	sub_wire2(1, 43)    <= sub_wire4(43);
-	sub_wire2(1, 44)    <= sub_wire4(44);
+	sub_wire2(1, 44)    <= sub_wire4(44);
-	sub_wire2(1, 45)    <= sub_wire4(45);
+	sub_wire2(1, 45)    <= sub_wire4(45);
-	sub_wire2(1, 46)    <= sub_wire4(46);
+	sub_wire2(1, 46)    <= sub_wire4(46);
-	sub_wire2(1, 47)    <= sub_wire4(47);
+	sub_wire2(1, 47)    <= sub_wire4(47);
-	sub_wire2(1, 48)    <= sub_wire4(48);
+	sub_wire2(1, 48)    <= sub_wire4(48);
-	sub_wire2(1, 49)    <= sub_wire4(49);
+	sub_wire2(1, 49)    <= sub_wire4(49);
-	sub_wire2(1, 50)    <= sub_wire4(50);
+	sub_wire2(1, 50)    <= sub_wire4(50);
-	sub_wire2(1, 51)    <= sub_wire4(51);
+	sub_wire2(1, 51)    <= sub_wire4(51);
-	sub_wire2(1, 52)    <= sub_wire4(52);
+	sub_wire2(1, 52)    <= sub_wire4(52);
-	sub_wire2(1, 53)    <= sub_wire4(53);
+	sub_wire2(1, 53)    <= sub_wire4(53);
-	sub_wire2(1, 54)    <= sub_wire4(54);
+	sub_wire2(1, 54)    <= sub_wire4(54);
-	sub_wire2(1, 55)    <= sub_wire4(55);
+	sub_wire2(1, 55)    <= sub_wire4(55);
-	sub_wire2(1, 56)    <= sub_wire4(56);
+	sub_wire2(1, 56)    <= sub_wire4(56);
-	sub_wire2(1, 57)    <= sub_wire4(57);
+	sub_wire2(1, 57)    <= sub_wire4(57);
-	sub_wire2(1, 58)    <= sub_wire4(58);
+	sub_wire2(1, 58)    <= sub_wire4(58);
-	sub_wire2(1, 59)    <= sub_wire4(59);
+	sub_wire2(1, 59)    <= sub_wire4(59);
-	sub_wire2(1, 60)    <= sub_wire4(60);
+	sub_wire2(1, 60)    <= sub_wire4(60);
-	sub_wire2(1, 61)    <= sub_wire4(61);
+	sub_wire2(1, 61)    <= sub_wire4(61);
-	sub_wire2(1, 62)    <= sub_wire4(62);
+	sub_wire2(1, 62)    <= sub_wire4(62);
-	sub_wire2(1, 63)    <= sub_wire4(63);
+	sub_wire2(1, 63)    <= sub_wire4(63);
-	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 0)    <= sub_wire5(0);
-	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 1)    <= sub_wire5(1);
-	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 2)    <= sub_wire5(2);
-	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 3)    <= sub_wire5(3);
-	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 4)    <= sub_wire5(4);
-	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 5)    <= sub_wire5(5);
-	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 6)    <= sub_wire5(6);
-	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 7)    <= sub_wire5(7);
-	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 8)    <= sub_wire5(8);
-	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 9)    <= sub_wire5(9);
-	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 10)    <= sub_wire5(10);
-	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 11)    <= sub_wire5(11);
-	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 12)    <= sub_wire5(12);
-	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 13)    <= sub_wire5(13);
-	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 14)    <= sub_wire5(14);
-	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 15)    <= sub_wire5(15);
-	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 16)    <= sub_wire5(16);
-	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 17)    <= sub_wire5(17);
-	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 18)    <= sub_wire5(18);
-	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 19)    <= sub_wire5(19);
-	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 20)    <= sub_wire5(20);
-	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 21)    <= sub_wire5(21);
-	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 22)    <= sub_wire5(22);
-	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 23)    <= sub_wire5(23);
-	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 24)    <= sub_wire5(24);
-	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 25)    <= sub_wire5(25);
-	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 26)    <= sub_wire5(26);
-	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 27)    <= sub_wire5(27);
-	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 28)    <= sub_wire5(28);
-	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 29)    <= sub_wire5(29);
-	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 30)    <= sub_wire5(30);
-	sub_wire2(0, 31)    <= sub_wire5(31);
+	sub_wire2(0, 31)    <= sub_wire5(31);
-	sub_wire2(0, 32)    <= sub_wire5(32);
+	sub_wire2(0, 32)    <= sub_wire5(32);
-	sub_wire2(0, 33)    <= sub_wire5(33);
+	sub_wire2(0, 33)    <= sub_wire5(33);
-	sub_wire2(0, 34)    <= sub_wire5(34);
+	sub_wire2(0, 34)    <= sub_wire5(34);
-	sub_wire2(0, 35)    <= sub_wire5(35);
+	sub_wire2(0, 35)    <= sub_wire5(35);
-	sub_wire2(0, 36)    <= sub_wire5(36);
+	sub_wire2(0, 36)    <= sub_wire5(36);
-	sub_wire2(0, 37)    <= sub_wire5(37);
+	sub_wire2(0, 37)    <= sub_wire5(37);
-	sub_wire2(0, 38)    <= sub_wire5(38);
+	sub_wire2(0, 38)    <= sub_wire5(38);
-	sub_wire2(0, 39)    <= sub_wire5(39);
+	sub_wire2(0, 39)    <= sub_wire5(39);
-	sub_wire2(0, 40)    <= sub_wire5(40);
+	sub_wire2(0, 40)    <= sub_wire5(40);
-	sub_wire2(0, 41)    <= sub_wire5(41);
+	sub_wire2(0, 41)    <= sub_wire5(41);
-	sub_wire2(0, 42)    <= sub_wire5(42);
+	sub_wire2(0, 42)    <= sub_wire5(42);
-	sub_wire2(0, 43)    <= sub_wire5(43);
+	sub_wire2(0, 43)    <= sub_wire5(43);
-	sub_wire2(0, 44)    <= sub_wire5(44);
+	sub_wire2(0, 44)    <= sub_wire5(44);
-	sub_wire2(0, 45)    <= sub_wire5(45);
+	sub_wire2(0, 45)    <= sub_wire5(45);
-	sub_wire2(0, 46)    <= sub_wire5(46);
+	sub_wire2(0, 46)    <= sub_wire5(46);
-	sub_wire2(0, 47)    <= sub_wire5(47);
+	sub_wire2(0, 47)    <= sub_wire5(47);
-	sub_wire2(0, 48)    <= sub_wire5(48);
+	sub_wire2(0, 48)    <= sub_wire5(48);
-	sub_wire2(0, 49)    <= sub_wire5(49);
+	sub_wire2(0, 49)    <= sub_wire5(49);
-	sub_wire2(0, 50)    <= sub_wire5(50);
+	sub_wire2(0, 50)    <= sub_wire5(50);
-	sub_wire2(0, 51)    <= sub_wire5(51);
+	sub_wire2(0, 51)    <= sub_wire5(51);
-	sub_wire2(0, 52)    <= sub_wire5(52);
+	sub_wire2(0, 52)    <= sub_wire5(52);
-	sub_wire2(0, 53)    <= sub_wire5(53);
+	sub_wire2(0, 53)    <= sub_wire5(53);
-	sub_wire2(0, 54)    <= sub_wire5(54);
+	sub_wire2(0, 54)    <= sub_wire5(54);
-	sub_wire2(0, 55)    <= sub_wire5(55);
+	sub_wire2(0, 55)    <= sub_wire5(55);
-	sub_wire2(0, 56)    <= sub_wire5(56);
+	sub_wire2(0, 56)    <= sub_wire5(56);
-	sub_wire2(0, 57)    <= sub_wire5(57);
+	sub_wire2(0, 57)    <= sub_wire5(57);
-	sub_wire2(0, 58)    <= sub_wire5(58);
+	sub_wire2(0, 58)    <= sub_wire5(58);
-	sub_wire2(0, 59)    <= sub_wire5(59);
+	sub_wire2(0, 59)    <= sub_wire5(59);
-	sub_wire2(0, 60)    <= sub_wire5(60);
+	sub_wire2(0, 60)    <= sub_wire5(60);
-	sub_wire2(0, 61)    <= sub_wire5(61);
+	sub_wire2(0, 61)    <= sub_wire5(61);
-	sub_wire2(0, 62)    <= sub_wire5(62);
+	sub_wire2(0, 62)    <= sub_wire5(62);
-	sub_wire2(0, 63)    <= sub_wire5(63);
+	sub_wire2(0, 63)    <= sub_wire5(63);
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_size => 4,
+		lpm_size => 4,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 64,
+		lpm_width => 64,
-		lpm_widths => 2
+		lpm_widths => 2
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sel,
+		data => sub_wire2,
-		data => sub_wire2,
+		sel => sel,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0]
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
--- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
--- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0]
+-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]"
--- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0]
+-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]"
--- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
+-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]"
--- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]"
--- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
--- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
--- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
--- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
--- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
--- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_mux6.bsf

@@ -1,111 +1,119 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 152 192)
+	(rect 0 0 144 192)
-	(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "lpm_mux6" (rect 43 0 117 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(text "inst" (rect 8 177 26 188)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 72 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 72 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 72 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 72 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 104)
+		(pt 0 104)
-		(input)
+		(input)
-		(text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 72 104)(line_width 3))
+		(line (pt 0 104)(pt 64 104)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 120)
+		(pt 0 120)
-		(input)
+		(input)
-		(text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 72 120)(line_width 3))
+		(line (pt 0 120)(pt 64 120)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 136)
+		(pt 0 136)
-		(input)
+		(input)
-		(text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 4 123 67 135)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 72 136)(line_width 3))
+		(line (pt 0 136)(pt 64 136)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 152)
+		(pt 0 152)
-		(input)
+		(input)
-		(text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 4 139 67 151)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 72 152)(line_width 3))
+		(line (pt 0 152)(pt 64 152)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 168)
+		(pt 0 168)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 72 168)(line_width 1))
+		(line (pt 0 168)(pt 64 168))
-	)
+	)
-	(port
+	(port
-		(pt 80 192)
+		(pt 72 192)
-		(input)
+		(input)
-		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
-		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical))
-		(line (pt 80 192)(pt 80 180)(line_width 3))
+		(line (pt 72 192)(pt 72 180)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 152 104)
+		(pt 144 104)
-		(output)
+		(output)
-		(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
-		(text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 85 91 142 103)(font "Arial" (font_size 8)))
-		(line (pt 152 104)(pt 88 104)(line_width 3))
+		(line (pt 144 104)(pt 80 104)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 64 24)(pt 64 184))
-		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 64 184)(pt 80 176))
-		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 80 32)(pt 80 176))
-		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 78 168)(pt 72 174)(line_width 1))
+		(line (pt 146 0)(pt 146 194))
-	)
+		(line (pt 0 194)(pt 146 194))
-)
+		(line (pt 0 0)(pt 0 194))
+		(line (pt 64 162)(pt 70 168))
+		(line (pt 70 168)(pt 64 174))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_mux6.cmp

@@ -1,31 +1,31 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_mux6
+component lpm_mux6
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_mux6.inc

@@ -1,32 +1,32 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_mux6 
+FUNCTION lpm_mux6 
-(
+(
-	clock,
+	clock,
-	data0x[23..0],
+	data0x[23..0],
-	data1x[23..0],
+	data1x[23..0],
-	data2x[23..0],
+	data2x[23..0],
-	data3x[23..0],
+	data3x[23..0],
-	data4x[23..0],
+	data4x[23..0],
-	data5x[23..0],
+	data5x[23..0],
-	data6x[23..0],
+	data6x[23..0],
-	data7x[23..0],
+	data7x[23..0],
-	sel[2..0]
+	sel[2..0]
-)
+)
-
+
-RETURNS (
+RETURNS (
-	result[23..0]
+	result[23..0]
-);
+);

Video/lpm_mux6.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"]

Video/lpm_mux6.vhd

@@ -1,335 +1,336 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_mux6.vhd
+-- File Name: lpm_mux6.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_mux6 IS
+ENTITY lpm_mux6 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
-	);
+	);
-END lpm_mux6;
+END lpm_mux6;
-
+
-
+
-ARCHITECTURE SYN OF lpm_mux6 IS
+ARCHITECTURE SYN OF lpm_mux6 IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (23 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire9    <= data0x(23 DOWNTO 0);
+	sub_wire9    <= data0x(23 DOWNTO 0);
-	sub_wire8    <= data1x(23 DOWNTO 0);
+	sub_wire8    <= data1x(23 DOWNTO 0);
-	sub_wire7    <= data2x(23 DOWNTO 0);
+	sub_wire7    <= data2x(23 DOWNTO 0);
-	sub_wire6    <= data3x(23 DOWNTO 0);
+	sub_wire6    <= data3x(23 DOWNTO 0);
-	sub_wire5    <= data4x(23 DOWNTO 0);
+	sub_wire5    <= data4x(23 DOWNTO 0);
-	sub_wire4    <= data5x(23 DOWNTO 0);
+	sub_wire4    <= data5x(23 DOWNTO 0);
-	sub_wire3    <= data6x(23 DOWNTO 0);
+	sub_wire3    <= data6x(23 DOWNTO 0);
-	result    <= sub_wire0(23 DOWNTO 0);
+	result    <= sub_wire0(23 DOWNTO 0);
-	sub_wire1    <= data7x(23 DOWNTO 0);
+	sub_wire1    <= data7x(23 DOWNTO 0);
-	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
-	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 1)    <= sub_wire1(1);
-	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 2)    <= sub_wire1(2);
-	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 3)    <= sub_wire1(3);
-	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 4)    <= sub_wire1(4);
-	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 5)    <= sub_wire1(5);
-	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 6)    <= sub_wire1(6);
-	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 7)    <= sub_wire1(7);
-	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 8)    <= sub_wire1(8);
-	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 9)    <= sub_wire1(9);
-	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 10)    <= sub_wire1(10);
-	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 11)    <= sub_wire1(11);
-	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 12)    <= sub_wire1(12);
-	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 13)    <= sub_wire1(13);
-	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 14)    <= sub_wire1(14);
-	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(7, 15)    <= sub_wire1(15);
-	sub_wire2(7, 16)    <= sub_wire1(16);
+	sub_wire2(7, 16)    <= sub_wire1(16);
-	sub_wire2(7, 17)    <= sub_wire1(17);
+	sub_wire2(7, 17)    <= sub_wire1(17);
-	sub_wire2(7, 18)    <= sub_wire1(18);
+	sub_wire2(7, 18)    <= sub_wire1(18);
-	sub_wire2(7, 19)    <= sub_wire1(19);
+	sub_wire2(7, 19)    <= sub_wire1(19);
-	sub_wire2(7, 20)    <= sub_wire1(20);
+	sub_wire2(7, 20)    <= sub_wire1(20);
-	sub_wire2(7, 21)    <= sub_wire1(21);
+	sub_wire2(7, 21)    <= sub_wire1(21);
-	sub_wire2(7, 22)    <= sub_wire1(22);
+	sub_wire2(7, 22)    <= sub_wire1(22);
-	sub_wire2(7, 23)    <= sub_wire1(23);
+	sub_wire2(7, 23)    <= sub_wire1(23);
-	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 0)    <= sub_wire3(0);
-	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 1)    <= sub_wire3(1);
-	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 2)    <= sub_wire3(2);
-	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 3)    <= sub_wire3(3);
-	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 4)    <= sub_wire3(4);
-	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 5)    <= sub_wire3(5);
-	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 6)    <= sub_wire3(6);
-	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 7)    <= sub_wire3(7);
-	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 8)    <= sub_wire3(8);
-	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 9)    <= sub_wire3(9);
-	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 10)    <= sub_wire3(10);
-	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 11)    <= sub_wire3(11);
-	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 12)    <= sub_wire3(12);
-	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 13)    <= sub_wire3(13);
-	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 14)    <= sub_wire3(14);
-	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(6, 15)    <= sub_wire3(15);
-	sub_wire2(6, 16)    <= sub_wire3(16);
+	sub_wire2(6, 16)    <= sub_wire3(16);
-	sub_wire2(6, 17)    <= sub_wire3(17);
+	sub_wire2(6, 17)    <= sub_wire3(17);
-	sub_wire2(6, 18)    <= sub_wire3(18);
+	sub_wire2(6, 18)    <= sub_wire3(18);
-	sub_wire2(6, 19)    <= sub_wire3(19);
+	sub_wire2(6, 19)    <= sub_wire3(19);
-	sub_wire2(6, 20)    <= sub_wire3(20);
+	sub_wire2(6, 20)    <= sub_wire3(20);
-	sub_wire2(6, 21)    <= sub_wire3(21);
+	sub_wire2(6, 21)    <= sub_wire3(21);
-	sub_wire2(6, 22)    <= sub_wire3(22);
+	sub_wire2(6, 22)    <= sub_wire3(22);
-	sub_wire2(6, 23)    <= sub_wire3(23);
+	sub_wire2(6, 23)    <= sub_wire3(23);
-	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 0)    <= sub_wire4(0);
-	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 1)    <= sub_wire4(1);
-	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 2)    <= sub_wire4(2);
-	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 3)    <= sub_wire4(3);
-	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 4)    <= sub_wire4(4);
-	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 5)    <= sub_wire4(5);
-	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 6)    <= sub_wire4(6);
-	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 7)    <= sub_wire4(7);
-	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 8)    <= sub_wire4(8);
-	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 9)    <= sub_wire4(9);
-	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 10)    <= sub_wire4(10);
-	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 11)    <= sub_wire4(11);
-	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 12)    <= sub_wire4(12);
-	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 13)    <= sub_wire4(13);
-	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 14)    <= sub_wire4(14);
-	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(5, 15)    <= sub_wire4(15);
-	sub_wire2(5, 16)    <= sub_wire4(16);
+	sub_wire2(5, 16)    <= sub_wire4(16);
-	sub_wire2(5, 17)    <= sub_wire4(17);
+	sub_wire2(5, 17)    <= sub_wire4(17);
-	sub_wire2(5, 18)    <= sub_wire4(18);
+	sub_wire2(5, 18)    <= sub_wire4(18);
-	sub_wire2(5, 19)    <= sub_wire4(19);
+	sub_wire2(5, 19)    <= sub_wire4(19);
-	sub_wire2(5, 20)    <= sub_wire4(20);
+	sub_wire2(5, 20)    <= sub_wire4(20);
-	sub_wire2(5, 21)    <= sub_wire4(21);
+	sub_wire2(5, 21)    <= sub_wire4(21);
-	sub_wire2(5, 22)    <= sub_wire4(22);
+	sub_wire2(5, 22)    <= sub_wire4(22);
-	sub_wire2(5, 23)    <= sub_wire4(23);
+	sub_wire2(5, 23)    <= sub_wire4(23);
-	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 0)    <= sub_wire5(0);
-	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 1)    <= sub_wire5(1);
-	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 2)    <= sub_wire5(2);
-	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 3)    <= sub_wire5(3);
-	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 4)    <= sub_wire5(4);
-	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 5)    <= sub_wire5(5);
-	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 6)    <= sub_wire5(6);
-	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 7)    <= sub_wire5(7);
-	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 8)    <= sub_wire5(8);
-	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 9)    <= sub_wire5(9);
-	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 10)    <= sub_wire5(10);
-	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 11)    <= sub_wire5(11);
-	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 12)    <= sub_wire5(12);
-	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 13)    <= sub_wire5(13);
-	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 14)    <= sub_wire5(14);
-	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(4, 15)    <= sub_wire5(15);
-	sub_wire2(4, 16)    <= sub_wire5(16);
+	sub_wire2(4, 16)    <= sub_wire5(16);
-	sub_wire2(4, 17)    <= sub_wire5(17);
+	sub_wire2(4, 17)    <= sub_wire5(17);
-	sub_wire2(4, 18)    <= sub_wire5(18);
+	sub_wire2(4, 18)    <= sub_wire5(18);
-	sub_wire2(4, 19)    <= sub_wire5(19);
+	sub_wire2(4, 19)    <= sub_wire5(19);
-	sub_wire2(4, 20)    <= sub_wire5(20);
+	sub_wire2(4, 20)    <= sub_wire5(20);
-	sub_wire2(4, 21)    <= sub_wire5(21);
+	sub_wire2(4, 21)    <= sub_wire5(21);
-	sub_wire2(4, 22)    <= sub_wire5(22);
+	sub_wire2(4, 22)    <= sub_wire5(22);
-	sub_wire2(4, 23)    <= sub_wire5(23);
+	sub_wire2(4, 23)    <= sub_wire5(23);
-	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 0)    <= sub_wire6(0);
-	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 1)    <= sub_wire6(1);
-	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 2)    <= sub_wire6(2);
-	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 3)    <= sub_wire6(3);
-	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 4)    <= sub_wire6(4);
-	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 5)    <= sub_wire6(5);
-	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 6)    <= sub_wire6(6);
-	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 7)    <= sub_wire6(7);
-	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 8)    <= sub_wire6(8);
-	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 9)    <= sub_wire6(9);
-	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 10)    <= sub_wire6(10);
-	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 11)    <= sub_wire6(11);
-	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 12)    <= sub_wire6(12);
-	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 13)    <= sub_wire6(13);
-	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 14)    <= sub_wire6(14);
-	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(3, 15)    <= sub_wire6(15);
-	sub_wire2(3, 16)    <= sub_wire6(16);
+	sub_wire2(3, 16)    <= sub_wire6(16);
-	sub_wire2(3, 17)    <= sub_wire6(17);
+	sub_wire2(3, 17)    <= sub_wire6(17);
-	sub_wire2(3, 18)    <= sub_wire6(18);
+	sub_wire2(3, 18)    <= sub_wire6(18);
-	sub_wire2(3, 19)    <= sub_wire6(19);
+	sub_wire2(3, 19)    <= sub_wire6(19);
-	sub_wire2(3, 20)    <= sub_wire6(20);
+	sub_wire2(3, 20)    <= sub_wire6(20);
-	sub_wire2(3, 21)    <= sub_wire6(21);
+	sub_wire2(3, 21)    <= sub_wire6(21);
-	sub_wire2(3, 22)    <= sub_wire6(22);
+	sub_wire2(3, 22)    <= sub_wire6(22);
-	sub_wire2(3, 23)    <= sub_wire6(23);
+	sub_wire2(3, 23)    <= sub_wire6(23);
-	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 0)    <= sub_wire7(0);
-	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 1)    <= sub_wire7(1);
-	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 2)    <= sub_wire7(2);
-	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 3)    <= sub_wire7(3);
-	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 4)    <= sub_wire7(4);
-	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 5)    <= sub_wire7(5);
-	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 6)    <= sub_wire7(6);
-	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 7)    <= sub_wire7(7);
-	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 8)    <= sub_wire7(8);
-	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 9)    <= sub_wire7(9);
-	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 10)    <= sub_wire7(10);
-	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 11)    <= sub_wire7(11);
-	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 12)    <= sub_wire7(12);
-	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 13)    <= sub_wire7(13);
-	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 14)    <= sub_wire7(14);
-	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(2, 15)    <= sub_wire7(15);
-	sub_wire2(2, 16)    <= sub_wire7(16);
+	sub_wire2(2, 16)    <= sub_wire7(16);
-	sub_wire2(2, 17)    <= sub_wire7(17);
+	sub_wire2(2, 17)    <= sub_wire7(17);
-	sub_wire2(2, 18)    <= sub_wire7(18);
+	sub_wire2(2, 18)    <= sub_wire7(18);
-	sub_wire2(2, 19)    <= sub_wire7(19);
+	sub_wire2(2, 19)    <= sub_wire7(19);
-	sub_wire2(2, 20)    <= sub_wire7(20);
+	sub_wire2(2, 20)    <= sub_wire7(20);
-	sub_wire2(2, 21)    <= sub_wire7(21);
+	sub_wire2(2, 21)    <= sub_wire7(21);
-	sub_wire2(2, 22)    <= sub_wire7(22);
+	sub_wire2(2, 22)    <= sub_wire7(22);
-	sub_wire2(2, 23)    <= sub_wire7(23);
+	sub_wire2(2, 23)    <= sub_wire7(23);
-	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 0)    <= sub_wire8(0);
-	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 1)    <= sub_wire8(1);
-	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 2)    <= sub_wire8(2);
-	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 3)    <= sub_wire8(3);
-	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 4)    <= sub_wire8(4);
-	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 5)    <= sub_wire8(5);
-	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 6)    <= sub_wire8(6);
-	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 7)    <= sub_wire8(7);
-	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 8)    <= sub_wire8(8);
-	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 9)    <= sub_wire8(9);
-	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 10)    <= sub_wire8(10);
-	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 11)    <= sub_wire8(11);
-	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 12)    <= sub_wire8(12);
-	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 13)    <= sub_wire8(13);
-	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 14)    <= sub_wire8(14);
-	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(1, 15)    <= sub_wire8(15);
-	sub_wire2(1, 16)    <= sub_wire8(16);
+	sub_wire2(1, 16)    <= sub_wire8(16);
-	sub_wire2(1, 17)    <= sub_wire8(17);
+	sub_wire2(1, 17)    <= sub_wire8(17);
-	sub_wire2(1, 18)    <= sub_wire8(18);
+	sub_wire2(1, 18)    <= sub_wire8(18);
-	sub_wire2(1, 19)    <= sub_wire8(19);
+	sub_wire2(1, 19)    <= sub_wire8(19);
-	sub_wire2(1, 20)    <= sub_wire8(20);
+	sub_wire2(1, 20)    <= sub_wire8(20);
-	sub_wire2(1, 21)    <= sub_wire8(21);
+	sub_wire2(1, 21)    <= sub_wire8(21);
-	sub_wire2(1, 22)    <= sub_wire8(22);
+	sub_wire2(1, 22)    <= sub_wire8(22);
-	sub_wire2(1, 23)    <= sub_wire8(23);
+	sub_wire2(1, 23)    <= sub_wire8(23);
-	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 0)    <= sub_wire9(0);
-	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 1)    <= sub_wire9(1);
-	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 2)    <= sub_wire9(2);
-	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 3)    <= sub_wire9(3);
-	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 4)    <= sub_wire9(4);
-	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 5)    <= sub_wire9(5);
-	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 6)    <= sub_wire9(6);
-	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 7)    <= sub_wire9(7);
-	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 8)    <= sub_wire9(8);
-	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 9)    <= sub_wire9(9);
-	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 10)    <= sub_wire9(10);
-	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 11)    <= sub_wire9(11);
-	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 12)    <= sub_wire9(12);
-	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 13)    <= sub_wire9(13);
-	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 14)    <= sub_wire9(14);
-	sub_wire2(0, 15)    <= sub_wire9(15);
+	sub_wire2(0, 15)    <= sub_wire9(15);
-	sub_wire2(0, 16)    <= sub_wire9(16);
+	sub_wire2(0, 16)    <= sub_wire9(16);
-	sub_wire2(0, 17)    <= sub_wire9(17);
+	sub_wire2(0, 17)    <= sub_wire9(17);
-	sub_wire2(0, 18)    <= sub_wire9(18);
+	sub_wire2(0, 18)    <= sub_wire9(18);
-	sub_wire2(0, 19)    <= sub_wire9(19);
+	sub_wire2(0, 19)    <= sub_wire9(19);
-	sub_wire2(0, 20)    <= sub_wire9(20);
+	sub_wire2(0, 20)    <= sub_wire9(20);
-	sub_wire2(0, 21)    <= sub_wire9(21);
+	sub_wire2(0, 21)    <= sub_wire9(21);
-	sub_wire2(0, 22)    <= sub_wire9(22);
+	sub_wire2(0, 22)    <= sub_wire9(22);
-	sub_wire2(0, 23)    <= sub_wire9(23);
+	sub_wire2(0, 23)    <= sub_wire9(23);
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_pipeline => 2,
+		lpm_pipeline => 2,
-		lpm_size => 8,
+		lpm_size => 8,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 24,
+		lpm_width => 24,
-		lpm_widths => 3
+		lpm_widths => 3
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sel,
+		clock => clock,
-		clock => clock,
+		data => sub_wire2,
-		data => sub_wire2,
+		sel => sel,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
--- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0]
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
--- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0]
+-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL "data0x[23..0]"
--- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0]
+-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL "data1x[23..0]"
--- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0]
+-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL "data2x[23..0]"
--- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0]
+-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL "data3x[23..0]"
--- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0]
+-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL "data4x[23..0]"
--- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0]
+-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL "data5x[23..0]"
--- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0]
+-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL "data6x[23..0]"
--- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL "data7x[23..0]"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
--- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
--- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
--- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
--- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_muxDZ.bsf

@@ -1,76 +1,84 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2009 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 168 112)
+	(rect 0 0 144 112)
-	(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
+	(text "lpm_muxDZ" (rect 37 0 123 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 27 73 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 80 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 43 73 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 80 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 59 29 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 80 72)(line_width 1))
+		(line (pt 0 72)(pt 64 72))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 0 0 30 13)(font "Arial" (font_size 8)))
-		(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 75 29 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 80 88)(line_width 1))
+		(line (pt 0 88)(pt 64 88))
-	)
+	)
-	(port
+	(port
-		(pt 88 112)
+		(pt 72 112)
-		(input)
+		(input)
-		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
-		(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
+		(text "sel" (rect 66 81 78 95)(font "Arial" (font_size 8))(vertical))
-		(line (pt 88 112)(pt 88 100)(line_width 1))
+		(line (pt 72 112)(pt 72 100))
-	)
+	)
-	(port
+	(port
-		(pt 168 64)
+		(pt 144 64)
-		(output)
+		(output)
-		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 79 51 142 63)(font "Arial" (font_size 8)))
-		(line (pt 168 64)(pt 96 64)(line_width 3))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 80 24)(pt 80 104)(line_width 1))
+		(line (pt 64 24)(pt 64 104))
-		(line (pt 96 32)(pt 96 96)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 64 104)(pt 80 96))
-		(line (pt 80 104)(pt 96 96)(line_width 1))
+		(line (pt 80 32)(pt 80 96))
-		(line (pt 80 66)(pt 86 72)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 86 72)(pt 80 78)(line_width 1))
+		(line (pt 146 0)(pt 146 114))
-	)
+		(line (pt 0 114)(pt 146 114))
-)
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 64 66)(pt 70 72))
+		(line (pt 70 72)(pt 64 78))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_muxDZ.cmp

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2009 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_muxDZ
+component lpm_muxDZ
-	PORT
+	PORT
-	(
+	(
-		clken		: IN STD_LOGIC  := '1';
+		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_muxDZ.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]

Video/lpm_muxDZ.vhd

@@ -1,377 +1,378 @@
--- megafunction wizard: %LPM_MUX%
+-- megafunction wizard: %LPM_MUX%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_mux 
+-- MODULE: LPM_MUX 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_muxDZ.vhd
+-- File Name: lpm_muxDZ.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_mux
+-- 			LPM_MUX
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2009 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.lpm_components.all;
+USE lpm.lpm_components.all;
-
+
-ENTITY lpm_muxDZ IS
+ENTITY lpm_muxDZ IS
-	PORT
+	PORT
-	(
+	(
-		clken		: IN STD_LOGIC  := '1';
+		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		sel		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
-		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
-	);
+	);
-END lpm_muxDZ;
+END lpm_muxDZ;
-
+
-
+
-ARCHITECTURE SYN OF lpm_muxdz IS
+ARCHITECTURE SYN OF lpm_muxdz IS
-
+
---	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (127 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
+
-BEGIN
+BEGIN
-	sub_wire5    <= data0x(127 DOWNTO 0);
+	sub_wire3    <= data0x(127 DOWNTO 0);
-	result    <= sub_wire0(127 DOWNTO 0);
+	result    <= sub_wire0(127 DOWNTO 0);
-	sub_wire1    <= sel;
+	sub_wire1    <= data1x(127 DOWNTO 0);
-	sub_wire2(0)    <= sub_wire1;
+	sub_wire2(1, 0)    <= sub_wire1(0);
-	sub_wire3    <= data1x(127 DOWNTO 0);
+	sub_wire2(1, 1)    <= sub_wire1(1);
-	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire2(1, 2)    <= sub_wire1(2);
-	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire2(1, 3)    <= sub_wire1(3);
-	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire2(1, 4)    <= sub_wire1(4);
-	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire2(1, 5)    <= sub_wire1(5);
-	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire2(1, 6)    <= sub_wire1(6);
-	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire2(1, 7)    <= sub_wire1(7);
-	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire2(1, 8)    <= sub_wire1(8);
-	sub_wire4(1, 7)    <= sub_wire3(7);
+	sub_wire2(1, 9)    <= sub_wire1(9);
-	sub_wire4(1, 8)    <= sub_wire3(8);
+	sub_wire2(1, 10)    <= sub_wire1(10);
-	sub_wire4(1, 9)    <= sub_wire3(9);
+	sub_wire2(1, 11)    <= sub_wire1(11);
-	sub_wire4(1, 10)    <= sub_wire3(10);
+	sub_wire2(1, 12)    <= sub_wire1(12);
-	sub_wire4(1, 11)    <= sub_wire3(11);
+	sub_wire2(1, 13)    <= sub_wire1(13);
-	sub_wire4(1, 12)    <= sub_wire3(12);
+	sub_wire2(1, 14)    <= sub_wire1(14);
-	sub_wire4(1, 13)    <= sub_wire3(13);
+	sub_wire2(1, 15)    <= sub_wire1(15);
-	sub_wire4(1, 14)    <= sub_wire3(14);
+	sub_wire2(1, 16)    <= sub_wire1(16);
-	sub_wire4(1, 15)    <= sub_wire3(15);
+	sub_wire2(1, 17)    <= sub_wire1(17);
-	sub_wire4(1, 16)    <= sub_wire3(16);
+	sub_wire2(1, 18)    <= sub_wire1(18);
-	sub_wire4(1, 17)    <= sub_wire3(17);
+	sub_wire2(1, 19)    <= sub_wire1(19);
-	sub_wire4(1, 18)    <= sub_wire3(18);
+	sub_wire2(1, 20)    <= sub_wire1(20);
-	sub_wire4(1, 19)    <= sub_wire3(19);
+	sub_wire2(1, 21)    <= sub_wire1(21);
-	sub_wire4(1, 20)    <= sub_wire3(20);
+	sub_wire2(1, 22)    <= sub_wire1(22);
-	sub_wire4(1, 21)    <= sub_wire3(21);
+	sub_wire2(1, 23)    <= sub_wire1(23);
-	sub_wire4(1, 22)    <= sub_wire3(22);
+	sub_wire2(1, 24)    <= sub_wire1(24);
-	sub_wire4(1, 23)    <= sub_wire3(23);
+	sub_wire2(1, 25)    <= sub_wire1(25);
-	sub_wire4(1, 24)    <= sub_wire3(24);
+	sub_wire2(1, 26)    <= sub_wire1(26);
-	sub_wire4(1, 25)    <= sub_wire3(25);
+	sub_wire2(1, 27)    <= sub_wire1(27);
-	sub_wire4(1, 26)    <= sub_wire3(26);
+	sub_wire2(1, 28)    <= sub_wire1(28);
-	sub_wire4(1, 27)    <= sub_wire3(27);
+	sub_wire2(1, 29)    <= sub_wire1(29);
-	sub_wire4(1, 28)    <= sub_wire3(28);
+	sub_wire2(1, 30)    <= sub_wire1(30);
-	sub_wire4(1, 29)    <= sub_wire3(29);
+	sub_wire2(1, 31)    <= sub_wire1(31);
-	sub_wire4(1, 30)    <= sub_wire3(30);
+	sub_wire2(1, 32)    <= sub_wire1(32);
-	sub_wire4(1, 31)    <= sub_wire3(31);
+	sub_wire2(1, 33)    <= sub_wire1(33);
-	sub_wire4(1, 32)    <= sub_wire3(32);
+	sub_wire2(1, 34)    <= sub_wire1(34);
-	sub_wire4(1, 33)    <= sub_wire3(33);
+	sub_wire2(1, 35)    <= sub_wire1(35);
-	sub_wire4(1, 34)    <= sub_wire3(34);
+	sub_wire2(1, 36)    <= sub_wire1(36);
-	sub_wire4(1, 35)    <= sub_wire3(35);
+	sub_wire2(1, 37)    <= sub_wire1(37);
-	sub_wire4(1, 36)    <= sub_wire3(36);
+	sub_wire2(1, 38)    <= sub_wire1(38);
-	sub_wire4(1, 37)    <= sub_wire3(37);
+	sub_wire2(1, 39)    <= sub_wire1(39);
-	sub_wire4(1, 38)    <= sub_wire3(38);
+	sub_wire2(1, 40)    <= sub_wire1(40);
-	sub_wire4(1, 39)    <= sub_wire3(39);
+	sub_wire2(1, 41)    <= sub_wire1(41);
-	sub_wire4(1, 40)    <= sub_wire3(40);
+	sub_wire2(1, 42)    <= sub_wire1(42);
-	sub_wire4(1, 41)    <= sub_wire3(41);
+	sub_wire2(1, 43)    <= sub_wire1(43);
-	sub_wire4(1, 42)    <= sub_wire3(42);
+	sub_wire2(1, 44)    <= sub_wire1(44);
-	sub_wire4(1, 43)    <= sub_wire3(43);
+	sub_wire2(1, 45)    <= sub_wire1(45);
-	sub_wire4(1, 44)    <= sub_wire3(44);
+	sub_wire2(1, 46)    <= sub_wire1(46);
-	sub_wire4(1, 45)    <= sub_wire3(45);
+	sub_wire2(1, 47)    <= sub_wire1(47);
-	sub_wire4(1, 46)    <= sub_wire3(46);
+	sub_wire2(1, 48)    <= sub_wire1(48);
-	sub_wire4(1, 47)    <= sub_wire3(47);
+	sub_wire2(1, 49)    <= sub_wire1(49);
-	sub_wire4(1, 48)    <= sub_wire3(48);
+	sub_wire2(1, 50)    <= sub_wire1(50);
-	sub_wire4(1, 49)    <= sub_wire3(49);
+	sub_wire2(1, 51)    <= sub_wire1(51);
-	sub_wire4(1, 50)    <= sub_wire3(50);
+	sub_wire2(1, 52)    <= sub_wire1(52);
-	sub_wire4(1, 51)    <= sub_wire3(51);
+	sub_wire2(1, 53)    <= sub_wire1(53);
-	sub_wire4(1, 52)    <= sub_wire3(52);
+	sub_wire2(1, 54)    <= sub_wire1(54);
-	sub_wire4(1, 53)    <= sub_wire3(53);
+	sub_wire2(1, 55)    <= sub_wire1(55);
-	sub_wire4(1, 54)    <= sub_wire3(54);
+	sub_wire2(1, 56)    <= sub_wire1(56);
-	sub_wire4(1, 55)    <= sub_wire3(55);
+	sub_wire2(1, 57)    <= sub_wire1(57);
-	sub_wire4(1, 56)    <= sub_wire3(56);
+	sub_wire2(1, 58)    <= sub_wire1(58);
-	sub_wire4(1, 57)    <= sub_wire3(57);
+	sub_wire2(1, 59)    <= sub_wire1(59);
-	sub_wire4(1, 58)    <= sub_wire3(58);
+	sub_wire2(1, 60)    <= sub_wire1(60);
-	sub_wire4(1, 59)    <= sub_wire3(59);
+	sub_wire2(1, 61)    <= sub_wire1(61);
-	sub_wire4(1, 60)    <= sub_wire3(60);
+	sub_wire2(1, 62)    <= sub_wire1(62);
-	sub_wire4(1, 61)    <= sub_wire3(61);
+	sub_wire2(1, 63)    <= sub_wire1(63);
-	sub_wire4(1, 62)    <= sub_wire3(62);
+	sub_wire2(1, 64)    <= sub_wire1(64);
-	sub_wire4(1, 63)    <= sub_wire3(63);
+	sub_wire2(1, 65)    <= sub_wire1(65);
-	sub_wire4(1, 64)    <= sub_wire3(64);
+	sub_wire2(1, 66)    <= sub_wire1(66);
-	sub_wire4(1, 65)    <= sub_wire3(65);
+	sub_wire2(1, 67)    <= sub_wire1(67);
-	sub_wire4(1, 66)    <= sub_wire3(66);
+	sub_wire2(1, 68)    <= sub_wire1(68);
-	sub_wire4(1, 67)    <= sub_wire3(67);
+	sub_wire2(1, 69)    <= sub_wire1(69);
-	sub_wire4(1, 68)    <= sub_wire3(68);
+	sub_wire2(1, 70)    <= sub_wire1(70);
-	sub_wire4(1, 69)    <= sub_wire3(69);
+	sub_wire2(1, 71)    <= sub_wire1(71);
-	sub_wire4(1, 70)    <= sub_wire3(70);
+	sub_wire2(1, 72)    <= sub_wire1(72);
-	sub_wire4(1, 71)    <= sub_wire3(71);
+	sub_wire2(1, 73)    <= sub_wire1(73);
-	sub_wire4(1, 72)    <= sub_wire3(72);
+	sub_wire2(1, 74)    <= sub_wire1(74);
-	sub_wire4(1, 73)    <= sub_wire3(73);
+	sub_wire2(1, 75)    <= sub_wire1(75);
-	sub_wire4(1, 74)    <= sub_wire3(74);
+	sub_wire2(1, 76)    <= sub_wire1(76);
-	sub_wire4(1, 75)    <= sub_wire3(75);
+	sub_wire2(1, 77)    <= sub_wire1(77);
-	sub_wire4(1, 76)    <= sub_wire3(76);
+	sub_wire2(1, 78)    <= sub_wire1(78);
-	sub_wire4(1, 77)    <= sub_wire3(77);
+	sub_wire2(1, 79)    <= sub_wire1(79);
-	sub_wire4(1, 78)    <= sub_wire3(78);
+	sub_wire2(1, 80)    <= sub_wire1(80);
-	sub_wire4(1, 79)    <= sub_wire3(79);
+	sub_wire2(1, 81)    <= sub_wire1(81);
-	sub_wire4(1, 80)    <= sub_wire3(80);
+	sub_wire2(1, 82)    <= sub_wire1(82);
-	sub_wire4(1, 81)    <= sub_wire3(81);
+	sub_wire2(1, 83)    <= sub_wire1(83);
-	sub_wire4(1, 82)    <= sub_wire3(82);
+	sub_wire2(1, 84)    <= sub_wire1(84);
-	sub_wire4(1, 83)    <= sub_wire3(83);
+	sub_wire2(1, 85)    <= sub_wire1(85);
-	sub_wire4(1, 84)    <= sub_wire3(84);
+	sub_wire2(1, 86)    <= sub_wire1(86);
-	sub_wire4(1, 85)    <= sub_wire3(85);
+	sub_wire2(1, 87)    <= sub_wire1(87);
-	sub_wire4(1, 86)    <= sub_wire3(86);
+	sub_wire2(1, 88)    <= sub_wire1(88);
-	sub_wire4(1, 87)    <= sub_wire3(87);
+	sub_wire2(1, 89)    <= sub_wire1(89);
-	sub_wire4(1, 88)    <= sub_wire3(88);
+	sub_wire2(1, 90)    <= sub_wire1(90);
-	sub_wire4(1, 89)    <= sub_wire3(89);
+	sub_wire2(1, 91)    <= sub_wire1(91);
-	sub_wire4(1, 90)    <= sub_wire3(90);
+	sub_wire2(1, 92)    <= sub_wire1(92);
-	sub_wire4(1, 91)    <= sub_wire3(91);
+	sub_wire2(1, 93)    <= sub_wire1(93);
-	sub_wire4(1, 92)    <= sub_wire3(92);
+	sub_wire2(1, 94)    <= sub_wire1(94);
-	sub_wire4(1, 93)    <= sub_wire3(93);
+	sub_wire2(1, 95)    <= sub_wire1(95);
-	sub_wire4(1, 94)    <= sub_wire3(94);
+	sub_wire2(1, 96)    <= sub_wire1(96);
-	sub_wire4(1, 95)    <= sub_wire3(95);
+	sub_wire2(1, 97)    <= sub_wire1(97);
-	sub_wire4(1, 96)    <= sub_wire3(96);
+	sub_wire2(1, 98)    <= sub_wire1(98);
-	sub_wire4(1, 97)    <= sub_wire3(97);
+	sub_wire2(1, 99)    <= sub_wire1(99);
-	sub_wire4(1, 98)    <= sub_wire3(98);
+	sub_wire2(1, 100)    <= sub_wire1(100);
-	sub_wire4(1, 99)    <= sub_wire3(99);
+	sub_wire2(1, 101)    <= sub_wire1(101);
-	sub_wire4(1, 100)    <= sub_wire3(100);
+	sub_wire2(1, 102)    <= sub_wire1(102);
-	sub_wire4(1, 101)    <= sub_wire3(101);
+	sub_wire2(1, 103)    <= sub_wire1(103);
-	sub_wire4(1, 102)    <= sub_wire3(102);
+	sub_wire2(1, 104)    <= sub_wire1(104);
-	sub_wire4(1, 103)    <= sub_wire3(103);
+	sub_wire2(1, 105)    <= sub_wire1(105);
-	sub_wire4(1, 104)    <= sub_wire3(104);
+	sub_wire2(1, 106)    <= sub_wire1(106);
-	sub_wire4(1, 105)    <= sub_wire3(105);
+	sub_wire2(1, 107)    <= sub_wire1(107);
-	sub_wire4(1, 106)    <= sub_wire3(106);
+	sub_wire2(1, 108)    <= sub_wire1(108);
-	sub_wire4(1, 107)    <= sub_wire3(107);
+	sub_wire2(1, 109)    <= sub_wire1(109);
-	sub_wire4(1, 108)    <= sub_wire3(108);
+	sub_wire2(1, 110)    <= sub_wire1(110);
-	sub_wire4(1, 109)    <= sub_wire3(109);
+	sub_wire2(1, 111)    <= sub_wire1(111);
-	sub_wire4(1, 110)    <= sub_wire3(110);
+	sub_wire2(1, 112)    <= sub_wire1(112);
-	sub_wire4(1, 111)    <= sub_wire3(111);
+	sub_wire2(1, 113)    <= sub_wire1(113);
-	sub_wire4(1, 112)    <= sub_wire3(112);
+	sub_wire2(1, 114)    <= sub_wire1(114);
-	sub_wire4(1, 113)    <= sub_wire3(113);
+	sub_wire2(1, 115)    <= sub_wire1(115);
-	sub_wire4(1, 114)    <= sub_wire3(114);
+	sub_wire2(1, 116)    <= sub_wire1(116);
-	sub_wire4(1, 115)    <= sub_wire3(115);
+	sub_wire2(1, 117)    <= sub_wire1(117);
-	sub_wire4(1, 116)    <= sub_wire3(116);
+	sub_wire2(1, 118)    <= sub_wire1(118);
-	sub_wire4(1, 117)    <= sub_wire3(117);
+	sub_wire2(1, 119)    <= sub_wire1(119);
-	sub_wire4(1, 118)    <= sub_wire3(118);
+	sub_wire2(1, 120)    <= sub_wire1(120);
-	sub_wire4(1, 119)    <= sub_wire3(119);
+	sub_wire2(1, 121)    <= sub_wire1(121);
-	sub_wire4(1, 120)    <= sub_wire3(120);
+	sub_wire2(1, 122)    <= sub_wire1(122);
-	sub_wire4(1, 121)    <= sub_wire3(121);
+	sub_wire2(1, 123)    <= sub_wire1(123);
-	sub_wire4(1, 122)    <= sub_wire3(122);
+	sub_wire2(1, 124)    <= sub_wire1(124);
-	sub_wire4(1, 123)    <= sub_wire3(123);
+	sub_wire2(1, 125)    <= sub_wire1(125);
-	sub_wire4(1, 124)    <= sub_wire3(124);
+	sub_wire2(1, 126)    <= sub_wire1(126);
-	sub_wire4(1, 125)    <= sub_wire3(125);
+	sub_wire2(1, 127)    <= sub_wire1(127);
-	sub_wire4(1, 126)    <= sub_wire3(126);
+	sub_wire2(0, 0)    <= sub_wire3(0);
-	sub_wire4(1, 127)    <= sub_wire3(127);
+	sub_wire2(0, 1)    <= sub_wire3(1);
-	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 2)    <= sub_wire3(2);
-	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 3)    <= sub_wire3(3);
-	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 4)    <= sub_wire3(4);
-	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 5)    <= sub_wire3(5);
-	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 6)    <= sub_wire3(6);
-	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 7)    <= sub_wire3(7);
-	sub_wire4(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 8)    <= sub_wire3(8);
-	sub_wire4(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 9)    <= sub_wire3(9);
-	sub_wire4(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 10)    <= sub_wire3(10);
-	sub_wire4(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 11)    <= sub_wire3(11);
-	sub_wire4(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 12)    <= sub_wire3(12);
-	sub_wire4(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 13)    <= sub_wire3(13);
-	sub_wire4(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 14)    <= sub_wire3(14);
-	sub_wire4(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 15)    <= sub_wire3(15);
-	sub_wire4(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 16)    <= sub_wire3(16);
-	sub_wire4(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 17)    <= sub_wire3(17);
-	sub_wire4(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 18)    <= sub_wire3(18);
-	sub_wire4(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 19)    <= sub_wire3(19);
-	sub_wire4(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 20)    <= sub_wire3(20);
-	sub_wire4(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 21)    <= sub_wire3(21);
-	sub_wire4(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 22)    <= sub_wire3(22);
-	sub_wire4(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 23)    <= sub_wire3(23);
-	sub_wire4(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 24)    <= sub_wire3(24);
-	sub_wire4(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 25)    <= sub_wire3(25);
-	sub_wire4(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 26)    <= sub_wire3(26);
-	sub_wire4(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 27)    <= sub_wire3(27);
-	sub_wire4(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 28)    <= sub_wire3(28);
-	sub_wire4(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 29)    <= sub_wire3(29);
-	sub_wire4(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 30)    <= sub_wire3(30);
-	sub_wire4(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 31)    <= sub_wire3(31);
-	sub_wire4(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 32)    <= sub_wire3(32);
-	sub_wire4(0, 31)    <= sub_wire5(31);
+	sub_wire2(0, 33)    <= sub_wire3(33);
-	sub_wire4(0, 32)    <= sub_wire5(32);
+	sub_wire2(0, 34)    <= sub_wire3(34);
-	sub_wire4(0, 33)    <= sub_wire5(33);
+	sub_wire2(0, 35)    <= sub_wire3(35);
-	sub_wire4(0, 34)    <= sub_wire5(34);
+	sub_wire2(0, 36)    <= sub_wire3(36);
-	sub_wire4(0, 35)    <= sub_wire5(35);
+	sub_wire2(0, 37)    <= sub_wire3(37);
-	sub_wire4(0, 36)    <= sub_wire5(36);
+	sub_wire2(0, 38)    <= sub_wire3(38);
-	sub_wire4(0, 37)    <= sub_wire5(37);
+	sub_wire2(0, 39)    <= sub_wire3(39);
-	sub_wire4(0, 38)    <= sub_wire5(38);
+	sub_wire2(0, 40)    <= sub_wire3(40);
-	sub_wire4(0, 39)    <= sub_wire5(39);
+	sub_wire2(0, 41)    <= sub_wire3(41);
-	sub_wire4(0, 40)    <= sub_wire5(40);
+	sub_wire2(0, 42)    <= sub_wire3(42);
-	sub_wire4(0, 41)    <= sub_wire5(41);
+	sub_wire2(0, 43)    <= sub_wire3(43);
-	sub_wire4(0, 42)    <= sub_wire5(42);
+	sub_wire2(0, 44)    <= sub_wire3(44);
-	sub_wire4(0, 43)    <= sub_wire5(43);
+	sub_wire2(0, 45)    <= sub_wire3(45);
-	sub_wire4(0, 44)    <= sub_wire5(44);
+	sub_wire2(0, 46)    <= sub_wire3(46);
-	sub_wire4(0, 45)    <= sub_wire5(45);
+	sub_wire2(0, 47)    <= sub_wire3(47);
-	sub_wire4(0, 46)    <= sub_wire5(46);
+	sub_wire2(0, 48)    <= sub_wire3(48);
-	sub_wire4(0, 47)    <= sub_wire5(47);
+	sub_wire2(0, 49)    <= sub_wire3(49);
-	sub_wire4(0, 48)    <= sub_wire5(48);
+	sub_wire2(0, 50)    <= sub_wire3(50);
-	sub_wire4(0, 49)    <= sub_wire5(49);
+	sub_wire2(0, 51)    <= sub_wire3(51);
-	sub_wire4(0, 50)    <= sub_wire5(50);
+	sub_wire2(0, 52)    <= sub_wire3(52);
-	sub_wire4(0, 51)    <= sub_wire5(51);
+	sub_wire2(0, 53)    <= sub_wire3(53);
-	sub_wire4(0, 52)    <= sub_wire5(52);
+	sub_wire2(0, 54)    <= sub_wire3(54);
-	sub_wire4(0, 53)    <= sub_wire5(53);
+	sub_wire2(0, 55)    <= sub_wire3(55);
-	sub_wire4(0, 54)    <= sub_wire5(54);
+	sub_wire2(0, 56)    <= sub_wire3(56);
-	sub_wire4(0, 55)    <= sub_wire5(55);
+	sub_wire2(0, 57)    <= sub_wire3(57);
-	sub_wire4(0, 56)    <= sub_wire5(56);
+	sub_wire2(0, 58)    <= sub_wire3(58);
-	sub_wire4(0, 57)    <= sub_wire5(57);
+	sub_wire2(0, 59)    <= sub_wire3(59);
-	sub_wire4(0, 58)    <= sub_wire5(58);
+	sub_wire2(0, 60)    <= sub_wire3(60);
-	sub_wire4(0, 59)    <= sub_wire5(59);
+	sub_wire2(0, 61)    <= sub_wire3(61);
-	sub_wire4(0, 60)    <= sub_wire5(60);
+	sub_wire2(0, 62)    <= sub_wire3(62);
-	sub_wire4(0, 61)    <= sub_wire5(61);
+	sub_wire2(0, 63)    <= sub_wire3(63);
-	sub_wire4(0, 62)    <= sub_wire5(62);
+	sub_wire2(0, 64)    <= sub_wire3(64);
-	sub_wire4(0, 63)    <= sub_wire5(63);
+	sub_wire2(0, 65)    <= sub_wire3(65);
-	sub_wire4(0, 64)    <= sub_wire5(64);
+	sub_wire2(0, 66)    <= sub_wire3(66);
-	sub_wire4(0, 65)    <= sub_wire5(65);
+	sub_wire2(0, 67)    <= sub_wire3(67);
-	sub_wire4(0, 66)    <= sub_wire5(66);
+	sub_wire2(0, 68)    <= sub_wire3(68);
-	sub_wire4(0, 67)    <= sub_wire5(67);
+	sub_wire2(0, 69)    <= sub_wire3(69);
-	sub_wire4(0, 68)    <= sub_wire5(68);
+	sub_wire2(0, 70)    <= sub_wire3(70);
-	sub_wire4(0, 69)    <= sub_wire5(69);
+	sub_wire2(0, 71)    <= sub_wire3(71);
-	sub_wire4(0, 70)    <= sub_wire5(70);
+	sub_wire2(0, 72)    <= sub_wire3(72);
-	sub_wire4(0, 71)    <= sub_wire5(71);
+	sub_wire2(0, 73)    <= sub_wire3(73);
-	sub_wire4(0, 72)    <= sub_wire5(72);
+	sub_wire2(0, 74)    <= sub_wire3(74);
-	sub_wire4(0, 73)    <= sub_wire5(73);
+	sub_wire2(0, 75)    <= sub_wire3(75);
-	sub_wire4(0, 74)    <= sub_wire5(74);
+	sub_wire2(0, 76)    <= sub_wire3(76);
-	sub_wire4(0, 75)    <= sub_wire5(75);
+	sub_wire2(0, 77)    <= sub_wire3(77);
-	sub_wire4(0, 76)    <= sub_wire5(76);
+	sub_wire2(0, 78)    <= sub_wire3(78);
-	sub_wire4(0, 77)    <= sub_wire5(77);
+	sub_wire2(0, 79)    <= sub_wire3(79);
-	sub_wire4(0, 78)    <= sub_wire5(78);
+	sub_wire2(0, 80)    <= sub_wire3(80);
-	sub_wire4(0, 79)    <= sub_wire5(79);
+	sub_wire2(0, 81)    <= sub_wire3(81);
-	sub_wire4(0, 80)    <= sub_wire5(80);
+	sub_wire2(0, 82)    <= sub_wire3(82);
-	sub_wire4(0, 81)    <= sub_wire5(81);
+	sub_wire2(0, 83)    <= sub_wire3(83);
-	sub_wire4(0, 82)    <= sub_wire5(82);
+	sub_wire2(0, 84)    <= sub_wire3(84);
-	sub_wire4(0, 83)    <= sub_wire5(83);
+	sub_wire2(0, 85)    <= sub_wire3(85);
-	sub_wire4(0, 84)    <= sub_wire5(84);
+	sub_wire2(0, 86)    <= sub_wire3(86);
-	sub_wire4(0, 85)    <= sub_wire5(85);
+	sub_wire2(0, 87)    <= sub_wire3(87);
-	sub_wire4(0, 86)    <= sub_wire5(86);
+	sub_wire2(0, 88)    <= sub_wire3(88);
-	sub_wire4(0, 87)    <= sub_wire5(87);
+	sub_wire2(0, 89)    <= sub_wire3(89);
-	sub_wire4(0, 88)    <= sub_wire5(88);
+	sub_wire2(0, 90)    <= sub_wire3(90);
-	sub_wire4(0, 89)    <= sub_wire5(89);
+	sub_wire2(0, 91)    <= sub_wire3(91);
-	sub_wire4(0, 90)    <= sub_wire5(90);
+	sub_wire2(0, 92)    <= sub_wire3(92);
-	sub_wire4(0, 91)    <= sub_wire5(91);
+	sub_wire2(0, 93)    <= sub_wire3(93);
-	sub_wire4(0, 92)    <= sub_wire5(92);
+	sub_wire2(0, 94)    <= sub_wire3(94);
-	sub_wire4(0, 93)    <= sub_wire5(93);
+	sub_wire2(0, 95)    <= sub_wire3(95);
-	sub_wire4(0, 94)    <= sub_wire5(94);
+	sub_wire2(0, 96)    <= sub_wire3(96);
-	sub_wire4(0, 95)    <= sub_wire5(95);
+	sub_wire2(0, 97)    <= sub_wire3(97);
-	sub_wire4(0, 96)    <= sub_wire5(96);
+	sub_wire2(0, 98)    <= sub_wire3(98);
-	sub_wire4(0, 97)    <= sub_wire5(97);
+	sub_wire2(0, 99)    <= sub_wire3(99);
-	sub_wire4(0, 98)    <= sub_wire5(98);
+	sub_wire2(0, 100)    <= sub_wire3(100);
-	sub_wire4(0, 99)    <= sub_wire5(99);
+	sub_wire2(0, 101)    <= sub_wire3(101);
-	sub_wire4(0, 100)    <= sub_wire5(100);
+	sub_wire2(0, 102)    <= sub_wire3(102);
-	sub_wire4(0, 101)    <= sub_wire5(101);
+	sub_wire2(0, 103)    <= sub_wire3(103);
-	sub_wire4(0, 102)    <= sub_wire5(102);
+	sub_wire2(0, 104)    <= sub_wire3(104);
-	sub_wire4(0, 103)    <= sub_wire5(103);
+	sub_wire2(0, 105)    <= sub_wire3(105);
-	sub_wire4(0, 104)    <= sub_wire5(104);
+	sub_wire2(0, 106)    <= sub_wire3(106);
-	sub_wire4(0, 105)    <= sub_wire5(105);
+	sub_wire2(0, 107)    <= sub_wire3(107);
-	sub_wire4(0, 106)    <= sub_wire5(106);
+	sub_wire2(0, 108)    <= sub_wire3(108);
-	sub_wire4(0, 107)    <= sub_wire5(107);
+	sub_wire2(0, 109)    <= sub_wire3(109);
-	sub_wire4(0, 108)    <= sub_wire5(108);
+	sub_wire2(0, 110)    <= sub_wire3(110);
-	sub_wire4(0, 109)    <= sub_wire5(109);
+	sub_wire2(0, 111)    <= sub_wire3(111);
-	sub_wire4(0, 110)    <= sub_wire5(110);
+	sub_wire2(0, 112)    <= sub_wire3(112);
-	sub_wire4(0, 111)    <= sub_wire5(111);
+	sub_wire2(0, 113)    <= sub_wire3(113);
-	sub_wire4(0, 112)    <= sub_wire5(112);
+	sub_wire2(0, 114)    <= sub_wire3(114);
-	sub_wire4(0, 113)    <= sub_wire5(113);
+	sub_wire2(0, 115)    <= sub_wire3(115);
-	sub_wire4(0, 114)    <= sub_wire5(114);
+	sub_wire2(0, 116)    <= sub_wire3(116);
-	sub_wire4(0, 115)    <= sub_wire5(115);
+	sub_wire2(0, 117)    <= sub_wire3(117);
-	sub_wire4(0, 116)    <= sub_wire5(116);
+	sub_wire2(0, 118)    <= sub_wire3(118);
-	sub_wire4(0, 117)    <= sub_wire5(117);
+	sub_wire2(0, 119)    <= sub_wire3(119);
-	sub_wire4(0, 118)    <= sub_wire5(118);
+	sub_wire2(0, 120)    <= sub_wire3(120);
-	sub_wire4(0, 119)    <= sub_wire5(119);
+	sub_wire2(0, 121)    <= sub_wire3(121);
-	sub_wire4(0, 120)    <= sub_wire5(120);
+	sub_wire2(0, 122)    <= sub_wire3(122);
-	sub_wire4(0, 121)    <= sub_wire5(121);
+	sub_wire2(0, 123)    <= sub_wire3(123);
-	sub_wire4(0, 122)    <= sub_wire5(122);
+	sub_wire2(0, 124)    <= sub_wire3(124);
-	sub_wire4(0, 123)    <= sub_wire5(123);
+	sub_wire2(0, 125)    <= sub_wire3(125);
-	sub_wire4(0, 124)    <= sub_wire5(124);
+	sub_wire2(0, 126)    <= sub_wire3(126);
-	sub_wire4(0, 125)    <= sub_wire5(125);
+	sub_wire2(0, 127)    <= sub_wire3(127);
-	sub_wire4(0, 126)    <= sub_wire5(126);
+	sub_wire4    <= sel;
-	sub_wire4(0, 127)    <= sub_wire5(127);
+	sub_wire5(0)    <= sub_wire4;
-
+
-	lpm_mux_component : lpm_mux
+	LPM_MUX_component : LPM_MUX
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_pipeline => 1,
+		lpm_pipeline => 1,
-		lpm_size => 2,
+		lpm_size => 2,
-		lpm_type => "LPM_MUX",
+		lpm_type => "LPM_MUX",
-		lpm_width => 128,
+		lpm_width => 128,
-		lpm_widths => 1
+		lpm_widths => 1
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		sel => sub_wire2,
+		clock => clock,
-		clken => clken,
+		data => sub_wire2,
-		clock => clock,
+		sel => sub_wire5,
-		data => sub_wire4,
+		clken => clken,
-		result => sub_wire0
+		result => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
--- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
--- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
--- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
--- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
--- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
--- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
--- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
--- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
--- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_muxVDM.bsf

@@ -1,158 +1,166 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2009 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 168 304)
+	(rect 0 0 144 304)
-	(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
+	(text "lpm_muxVDM" (rect 31 0 131 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 288 25 300)(font "Arial" ))
+	(text "inst" (rect 8 289 26 300)(font "Arial" ))
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 40)
-		(input)
+		(input)
-		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
-		(text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 27 79 39)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 80 40)(line_width 3))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 56)
-		(input)
+		(input)
-		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
-		(text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 43 79 55)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 80 56)(line_width 3))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 72)
-		(input)
+		(input)
-		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
-		(text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 59 79 71)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 80 72)(line_width 3))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 88)
+		(pt 0 88)
-		(input)
+		(input)
-		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
-		(text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 75 79 87)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 80 88)(line_width 3))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 104)
+		(pt 0 104)
-		(input)
+		(input)
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+		(text "data11x[127..0]" (rect 0 0 88 13)(font "Arial" (font_size 8)))
-		(text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 91 79 103)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 80 104)(line_width 3))
+		(line (pt 0 104)(pt 64 104)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 120)
+		(pt 0 120)
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+		(input)
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+		(text "data10x[127..0]" (rect 4 107 79 119)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 80 120)(line_width 3))
+		(line (pt 0 120)(pt 64 120)(line_width 3))
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+	)
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+	(port
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+		(pt 0 136)
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+		(input)
-		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 123 73 135)(font "Arial" (font_size 8)))
-		(line (pt 0 136)(pt 80 136)(line_width 3))
+		(line (pt 0 136)(pt 64 136)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 152)
+		(pt 0 152)
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+		(input)
-		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 139 73 151)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 80 152)(line_width 3))
+		(line (pt 0 152)(pt 64 152)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 168)
+		(pt 0 168)
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+		(input)
-		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 155 73 167)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 80 168)(line_width 3))
+		(line (pt 0 168)(pt 64 168)(line_width 3))
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+	)
-	(port
+	(port
-		(pt 0 184)
+		(pt 0 184)
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+		(input)
-		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 171 73 183)(font "Arial" (font_size 8)))
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+		(line (pt 0 184)(pt 64 184)(line_width 3))
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+	)
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+	(port
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+		(pt 0 200)
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+		(input)
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-		(text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 187 73 199)(font "Arial" (font_size 8)))
-		(line (pt 0 200)(pt 80 200)(line_width 3))
+		(line (pt 0 200)(pt 64 200)(line_width 3))
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+	)
-	(port
+	(port
-		(pt 0 216)
+		(pt 0 216)
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+		(input)
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+		(text "data4x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 203 73 215)(font "Arial" (font_size 8)))
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+		(line (pt 0 216)(pt 64 216)(line_width 3))
-	)
+	)
-	(port
+	(port
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+		(pt 0 232)
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+		(input)
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-		(text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8)))
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+		(line (pt 0 232)(pt 64 232)(line_width 3))
-	)
+	)
-	(port
+	(port
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+		(pt 0 248)
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+		(input)
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+		(line (pt 0 248)(pt 64 248)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 264)
+		(pt 0 264)
-		(input)
+		(input)
-		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 251 73 263)(font "Arial" (font_size 8)))
-		(line (pt 0 264)(pt 80 264)(line_width 3))
+		(line (pt 0 264)(pt 64 264)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 280)
+		(pt 0 280)
-		(input)
+		(input)
-		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 267 73 279)(font "Arial" (font_size 8)))
-		(line (pt 0 280)(pt 80 280)(line_width 3))
+		(line (pt 0 280)(pt 64 280)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 88 304)
+		(pt 72 304)
-		(input)
+		(input)
-		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
-		(text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 66 249 78 287)(font "Arial" (font_size 8))(vertical))
-		(line (pt 88 304)(pt 88 292)(line_width 3))
+		(line (pt 72 304)(pt 72 292)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 168 160)
+		(pt 144 160)
-		(output)
+		(output)
-		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 79 147 142 159)(font "Arial" (font_size 8)))
-		(line (pt 168 160)(pt 96 160)(line_width 3))
+		(line (pt 144 160)(pt 80 160)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(line (pt 80 24)(pt 80 296)(line_width 1))
+		(line (pt 64 24)(pt 64 296))
-		(line (pt 96 32)(pt 96 288)(line_width 1))
+		(line (pt 64 24)(pt 80 32))
-		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 64 296)(pt 80 288))
-		(line (pt 80 296)(pt 96 288)(line_width 1))
+		(line (pt 80 32)(pt 80 288))
-	)
+		(line (pt 0 0)(pt 146 0))
-)
+		(line (pt 146 0)(pt 146 306))
+		(line (pt 0 306)(pt 146 306))
+		(line (pt 0 0)(pt 0 306))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_muxVDM.cmp

@@ -1,38 +1,38 @@
---Copyright (C) 1991-2009 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_muxVDM
+component lpm_muxVDM
-	PORT
+	PORT
-	(
+	(
-		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_muxVDM.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]

Video/lpm_shiftreg0.bsf

@@ -1,70 +1,78 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 144 128)
+	(rect 0 0 144 128)
-	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg0" (rect 33 0 128 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(text "inst" (rect 8 113 26 124)(font "Arial" ))
-	(port
+	(port
-		(pt 0 32)
+		(pt 0 32)
-		(input)
+		(input)
-		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 25 13)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 41 38)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 1))
+		(line (pt 0 32)(pt 16 32))
-	)
+	)
-	(port
+	(port
-		(pt 0 48)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 61 13)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 72 54)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 80)
+		(pt 0 80)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 51 86)(font "Arial" (font_size 8)))
-		(line (pt 0 80)(pt 16 80)(line_width 1))
+		(line (pt 0 80)(pt 16 80))
-	)
+	)
-	(port
+	(port
-		(pt 0 96)
+		(pt 0 96)
-		(input)
+		(input)
-		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 48 102)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 16 96)(line_width 1))
+		(line (pt 0 96)(pt 16 96))
-	)
+	)
-	(port
+	(port
-		(pt 144 72)
+		(pt 144 64)
-		(output)
+		(output)
-		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 91 58 126 70)(font "Arial" (font_size 8)))
-		(line (pt 144 72)(pt 128 72)(line_width 1))
+		(line (pt 144 64)(pt 128 64))
-	)
+	)
-	(drawing
+	(drawing
-		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
+		(text "left shift" (rect 96 18 227 46)(font "Arial" ))
-		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 16 16)(pt 16 112))
-		(line (pt 128 16)(pt 128 112)(line_width 1))
+		(line (pt 16 16)(pt 128 16))
-		(line (pt 128 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 128 112))
-		(line (pt 16 112)(pt 16 16)(line_width 1))
+		(line (pt 128 16)(pt 128 112))
-		(line (pt 16 74)(pt 22 80)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 22 80)(pt 16 86)(line_width 1))
+		(line (pt 146 0)(pt 146 130))
-	)
+		(line (pt 0 130)(pt 146 130))
-)
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 16 74)(pt 22 80))
+		(line (pt 22 80)(pt 16 86))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_shiftreg0.cmp

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_shiftreg0
+component lpm_shiftreg0
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		load		: IN STD_LOGIC ;
+		load		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		shiftout		: OUT STD_LOGIC 
+		shiftout		: OUT STD_LOGIC 
-	);
+	);
-end component;
+end component;

Video/lpm_shiftreg0.inc

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_shiftreg0 
+FUNCTION lpm_shiftreg0 
-(
+(
-	clock,
+	clock,
-	data[15..0],
+	data[15..0],
-	load,
+	load,
-	shiftin
+	shiftin
-)
+)
-
+
-RETURNS (
+RETURNS (
-	shiftout
+	shiftout
-);
+);

Video/lpm_shiftreg0.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]

Video/lpm_shiftreg0.vhd

@@ -1,135 +1,136 @@
--- megafunction wizard: %LPM_SHIFTREG%
+-- megafunction wizard: %LPM_SHIFTREG%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_shiftreg 
+-- MODULE: LPM_SHIFTREG 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_shiftreg0.vhd
+-- File Name: lpm_shiftreg0.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_shiftreg
+-- 			LPM_SHIFTREG
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_shiftreg0 IS
+ENTITY lpm_shiftreg0 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		load		: IN STD_LOGIC ;
+		load		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		shiftout		: OUT STD_LOGIC 
+		shiftout		: OUT STD_LOGIC 
-	);
+	);
-END lpm_shiftreg0;
+END lpm_shiftreg0;
-
+
-
+
-ARCHITECTURE SYN OF lpm_shiftreg0 IS
+ARCHITECTURE SYN OF lpm_shiftreg0 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire0	: STD_LOGIC ;
-
+
-
+
-
+
-	COMPONENT lpm_shiftreg
+	COMPONENT lpm_shiftreg
-	GENERIC (
+	GENERIC (
-		lpm_direction		: STRING;
+		lpm_direction		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			load	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
-			clock	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+			load	: IN STD_LOGIC ;
-			shiftout	: OUT STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
-			shiftin	: IN STD_LOGIC 
+			shiftin	: IN STD_LOGIC 
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	shiftout    <= sub_wire0;
+	shiftout    <= sub_wire0;
-
+
-	lpm_shiftreg_component : lpm_shiftreg
+	LPM_SHIFTREG_component : LPM_SHIFTREG
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_direction => "LEFT",
+		lpm_direction => "LEFT",
-		lpm_type => "LPM_SHIFTREG",
+		lpm_type => "LPM_SHIFTREG",
-		lpm_width => 16
+		lpm_width => 16
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		load => load,
+		clock => clock,
-		clock => clock,
+		data => data,
-		data => data,
+		load => load,
-		shiftin => shiftin,
+		shiftin => shiftin,
-		shiftout => sub_wire0
+		shiftout => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
--- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
--- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
--- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
--- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
--- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
--- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
--- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
--- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
--- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
--- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
--- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
--- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
--- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
--- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL "load"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
--- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
--- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
--- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_shiftreg4.bsf

@@ -1,56 +1,64 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 144 80)
+	(rect 0 0 144 80)
-	(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg4" (rect 33 0 129 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
-	(port
+	(port
-		(pt 0 32)
+		(pt 0 32)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 1))
+		(line (pt 0 32)(pt 16 32))
-	)
+	)
-	(port
+	(port
-		(pt 0 48)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 1))
+		(line (pt 0 48)(pt 16 48))
-	)
+	)
-	(port
+	(port
-		(pt 144 48)
+		(pt 144 48)
-		(output)
+		(output)
-		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 91 42 126 54)(font "Arial" (font_size 8)))
-		(line (pt 144 48)(pt 128 48)(line_width 1))
+		(line (pt 144 48)(pt 128 48))
-	)
+	)
-	(drawing
+	(drawing
-		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(text "right shift" (rect 90 18 220 46)(font "Arial" ))
-		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 16 16)(pt 16 64))
-		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 16 16)(pt 128 16))
-		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 128 64))
-		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64))
-		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 22 32)(pt 16 38)(line_width 1))
+		(line (pt 146 0)(pt 146 82))
-	)
+		(line (pt 0 82)(pt 146 82))
-)
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_shiftreg4.cmp

@@ -1,23 +1,23 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_shiftreg4
+component lpm_shiftreg4
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		shiftout		: OUT STD_LOGIC 
+		shiftout		: OUT STD_LOGIC 
-	);
+	);
-end component;
+end component;

Video/lpm_shiftreg4.inc

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_shiftreg4 
+FUNCTION lpm_shiftreg4 
-(
+(
-	clock,
+	clock,
-	shiftin
+	shiftin
-)
+)
-
+
-RETURNS (
+RETURNS (
-	shiftout
+	shiftout
-);
+);

Video/lpm_shiftreg4.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"]

Video/lpm_shiftreg4.vhd

@@ -1,125 +1,126 @@
--- megafunction wizard: %LPM_SHIFTREG%
+-- megafunction wizard: %LPM_SHIFTREG%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_shiftreg 
+-- MODULE: LPM_SHIFTREG 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_shiftreg4.vhd
+-- File Name: lpm_shiftreg4.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_shiftreg
+-- 			LPM_SHIFTREG
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_shiftreg4 IS
+ENTITY lpm_shiftreg4 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		shiftout		: OUT STD_LOGIC 
+		shiftout		: OUT STD_LOGIC 
-	);
+	);
-END lpm_shiftreg4;
+END lpm_shiftreg4;
-
+
-
+
-ARCHITECTURE SYN OF lpm_shiftreg4 IS
+ARCHITECTURE SYN OF lpm_shiftreg4 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire0	: STD_LOGIC ;
-
+
-
+
-
+
-	COMPONENT lpm_shiftreg
+	COMPONENT lpm_shiftreg
-	GENERIC (
+	GENERIC (
-		lpm_direction		: STRING;
+		lpm_direction		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			clock	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
-			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC ;
-			shiftin	: IN STD_LOGIC 
+			shiftout	: OUT STD_LOGIC 
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	shiftout    <= sub_wire0;
+	shiftout    <= sub_wire0;
-
+
-	lpm_shiftreg_component : lpm_shiftreg
+	LPM_SHIFTREG_component : LPM_SHIFTREG
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_direction => "RIGHT",
+		lpm_direction => "RIGHT",
-		lpm_type => "LPM_SHIFTREG",
+		lpm_type => "LPM_SHIFTREG",
-		lpm_width => 5
+		lpm_width => 5
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		clock => clock,
+		clock => clock,
-		shiftin => shiftin,
+		shiftin => shiftin,
-		shiftout => sub_wire0
+		shiftout => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
--- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
--- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
--- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
--- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
--- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
--- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
--- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
--- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
--- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
--- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
--- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
--- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
--- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

Video/lpm_shiftreg6.bsf

@@ -1,56 +1,64 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 144 80)
+	(rect 0 0 144 80)
-	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "lpm_shiftreg6" (rect 33 0 128 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
-	(port
+	(port
-		(pt 0 32)
+		(pt 0 32)
-		(input)
+		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 1))
+		(line (pt 0 32)(pt 16 32))
-	)
+	)
-	(port
+	(port
-		(pt 0 48)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 1))
+		(line (pt 0 48)(pt 16 48))
-	)
+	)
-	(port
+	(port
-		(pt 144 48)
+		(pt 144 48)
-		(output)
+		(output)
-		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 0 0 36 13)(font "Arial" (font_size 8)))
-		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 126 54)(font "Arial" (font_size 8)))
-		(line (pt 144 48)(pt 128 48)(line_width 3))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(text "right shift" (rect 90 18 220 46)(font "Arial" ))
-		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 16 16)(pt 16 64))
-		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 16 16)(pt 128 16))
-		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 128 64))
-		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64))
-		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 0 0)(pt 146 0))
-		(line (pt 22 32)(pt 16 38)(line_width 1))
+		(line (pt 146 0)(pt 146 82))
-	)
+		(line (pt 0 82)(pt 146 82))
-)
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)

Video/lpm_shiftreg6.cmp

@@ -1,23 +1,23 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component lpm_shiftreg6
+component lpm_shiftreg6
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
+	);
-end component;
+end component;

Video/lpm_shiftreg6.inc

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION lpm_shiftreg6 
+FUNCTION lpm_shiftreg6 
-(
+(
-	clock,
+	clock,
-	shiftin
+	shiftin
-)
+)
-
+
-RETURNS (
+RETURNS (
-	q[4..0]
+	q[4..0]
-);
+);

Video/lpm_shiftreg6.qip

@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"]

Video/lpm_shiftreg6.vhd

@@ -1,125 +1,126 @@
--- megafunction wizard: %LPM_SHIFTREG%
+-- megafunction wizard: %LPM_SHIFTREG%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: lpm_shiftreg 
+-- MODULE: LPM_SHIFTREG 
-
+
--- ============================================================
+-- ============================================================
--- File Name: lpm_shiftreg6.vhd
+-- File Name: lpm_shiftreg6.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			lpm_shiftreg
+-- 			LPM_SHIFTREG
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			lpm
+-- 			lpm
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY lpm;
+LIBRARY lpm;
-USE lpm.all;
+USE lpm.all;
-
+
-ENTITY lpm_shiftreg6 IS
+ENTITY lpm_shiftreg6 IS
-	PORT
+	PORT
-	(
+	(
-		clock		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
-		shiftin		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
+	);
-END lpm_shiftreg6;
+END lpm_shiftreg6;
-
+
-
+
-ARCHITECTURE SYN OF lpm_shiftreg6 IS
+ARCHITECTURE SYN OF lpm_shiftreg6 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-
+
-
+
-
+
-	COMPONENT lpm_shiftreg
+	COMPONENT lpm_shiftreg
-	GENERIC (
+	GENERIC (
-		lpm_direction		: STRING;
+		lpm_direction		: STRING;
-		lpm_type		: STRING;
+		lpm_type		: STRING;
-		lpm_width		: NATURAL
+		lpm_width		: NATURAL
-	);
+	);
-	PORT (
+	PORT (
-			clock	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
-			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			shiftin	: IN STD_LOGIC 
+			shiftin	: IN STD_LOGIC 
-	);
+	);
-	END COMPONENT;
+	END COMPONENT;
-
+
-BEGIN
+BEGIN
-	q    <= sub_wire0(4 DOWNTO 0);
+	q    <= sub_wire0(4 DOWNTO 0);
-
+
-	lpm_shiftreg_component : lpm_shiftreg
+	LPM_SHIFTREG_component : LPM_SHIFTREG
-	GENERIC MAP (
+	GENERIC MAP (
-		lpm_direction => "RIGHT",
+		lpm_direction => "RIGHT",
-		lpm_type => "LPM_SHIFTREG",
+		lpm_type => "LPM_SHIFTREG",
-		lpm_width => 5
+		lpm_width => 5
-	)
+	)
-	PORT MAP (
+	PORT MAP (
-		clock => clock,
+		clock => clock,
-		shiftin => shiftin,
+		shiftin => shiftin,
-		q => sub_wire0
+		q => sub_wire0
-	);
+	);
-
+
-
+
-
+
-END SYN;
+END SYN;
-
+
--- ============================================================
+-- ============================================================
--- CNX file retrieval info
+-- CNX file retrieval info
--- ============================================================
+-- ============================================================
--- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
--- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
--- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
--- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
--- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
--- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
--- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
--- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
--- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
--- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
--- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
--- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
--- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
--- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
--- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
--- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
--- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
+-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE
--- Retrieval info: LIB_FILE: lpm
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm

altddio_out3.bsf

@@ -1,64 +1,64 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 232 120)
+	(rect 0 0 192 112)
-	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "altddio_out3" (rect 57 0 156 17)(font "Dialog" (font_size 10)))
-	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
-	(port
+	(port
-		(pt 0 24)
+		(pt 0 48)
-		(input)
+		(input)
-		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h[0]" (rect 0 0 73 13)(font "Dialog" (font_size 8)))
-		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(text "datain_h[0]" (rect 4 35 67 47)(font "Dialog" (font_size 8)))
-		(line (pt 0 24)(pt 88 24)(line_width 1))
+		(line (pt 0 48)(pt 64 48)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 40)
+		(pt 0 64)
-		(input)
+		(input)
-		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l[0]" (rect 0 0 69 13)(font "Dialog" (font_size 8)))
-		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(text "datain_l[0]" (rect 4 51 63 63)(font "Dialog" (font_size 8)))
-		(line (pt 0 40)(pt 88 40)(line_width 1))
+		(line (pt 0 64)(pt 64 64)(line_width 3))
-	)
+	)
-	(port
+	(port
-		(pt 0 56)
+		(pt 0 80)
-		(input)
+		(input)
-		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
-		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
-		(line (pt 0 56)(pt 88 56)(line_width 1))
+		(line (pt 0 80)(pt 64 80))
-	)
+	)
-	(port
+	(port
-		(pt 232 24)
+		(pt 192 48)
-		(output)
+		(output)
-		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout[0]" (rect 0 0 68 13)(font "Dialog" (font_size 8)))
-		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(text "dataout[0]" (rect 131 35 190 47)(font "Dialog" (font_size 8)))
-		(line (pt 232 24)(pt 152 24)(line_width 1))
+		(line (pt 192 48)(pt 128 48)(line_width 3))
-	)
+	)
-	(drawing
+	(drawing
-		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(line (pt 64 32)(pt 128 32))
-		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(line (pt 128 32)(pt 128 96))
-		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(line (pt 64 96)(pt 128 96))
-		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 64 32)(pt 64 96))
-		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 0 0)(pt 192 0))
-		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 192 0)(pt 192 112))
-		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 0 112)(pt 192 112))
-		(line (pt 88 96)(pt 88 16)(line_width 1))
+		(line (pt 0 0)(pt 0 112))
-	)
+	)
-)
+)

altddio_out3.cmp

@@ -1,24 +1,24 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component altddio_out3
+component altddio_out3
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC ;
+		datain_h		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		datain_l		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC 
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
-	);
+	);
-end component;
+end component;

altddio_out3.inc

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION altddio_out3 
+FUNCTION altddio_out3 
-(
+(
-	datain_h,
+	datain_h[0..0],
-	datain_l,
+	datain_l[0..0],
-	outclock
+	outclock
-)
+)
-
+
-RETURNS (
+RETURNS (
-	dataout
+	dataout[0..0]
-);
+);

altddio_out3.ppf

@@ -1,11 +1,11 @@
-<?xml version="1.0" encoding="UTF-8" ?>
+<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
+<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
-<global>
+<global>
-<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_h[0..0]" direction="input" scope="external"  />
-<pin name="datain_l" direction="input" scope="external"  />
+<pin name="datain_l[0..0]" direction="input" scope="external"  />
-<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
-<pin name="dataout" direction="output" scope="external"  />
+<pin name="dataout[0..0]" direction="output" scope="external"  />
-
+
-</global>
+</global>
-</pinplan>
+</pinplan>

altddio_out3.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]

altddio_out3.vhd

@@ -1,146 +1,110 @@
--- megafunction wizard: %ALTDDIO_OUT%
+-- megafunction wizard: %ALTDDIO_OUT%
--- GENERATION: STANDARD
+-- GENERATION: STANDARD
--- VERSION: WM1.0
+-- VERSION: WM1.0
--- MODULE: altddio_out 
+-- MODULE: ALTDDIO_OUT 
-
+
--- ============================================================
+-- ============================================================
--- File Name: altddio_out3.vhd
+-- File Name: altddio_out3.vhd
--- Megafunction Name(s):
+-- Megafunction Name(s):
--- 			altddio_out
+-- 			ALTDDIO_OUT
---
+--
--- Simulation Library Files(s):
+-- Simulation Library Files(s):
--- 			altera_mf
+-- 			altera_mf
--- ============================================================
+-- ============================================================
--- ************************************************************
+-- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
+--
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
+-- ************************************************************
-
+
-
+
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-LIBRARY ieee;
+LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+USE ieee.std_logic_1164.all;
-
+
-LIBRARY altera_mf;
+LIBRARY altera_mf;
-USE altera_mf.all;
+USE altera_mf.altera_mf_components.all;
-
+
-ENTITY altddio_out3 IS
+ENTITY altddio_out3 IS
-	PORT
+	PORT
-	(
+	(
-		datain_h		: IN STD_LOGIC ;
+		datain_h		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		datain_l		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC 
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
-	);
+	);
-END altddio_out3;
+END altddio_out3;
-
+
-
+
-ARCHITECTURE SYN OF altddio_out3 IS
+ARCHITECTURE SYN OF altddio_out3 IS
-
+
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
+
-	SIGNAL sub_wire2	: STD_LOGIC ;
+BEGIN
-	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	dataout    <= sub_wire0(0 DOWNTO 0);
-	SIGNAL sub_wire4	: STD_LOGIC ;
+
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	ALTDDIO_OUT_component : ALTDDIO_OUT
-
+	GENERIC MAP (
-
+		extend_oe_disable => "OFF",
-
+		intended_device_family => "Cyclone III",
-	COMPONENT altddio_out
+		invert_output => "OFF",
-	GENERIC (
+		lpm_hint => "UNUSED",
-		extend_oe_disable		: STRING;
+		lpm_type => "altddio_out",
-		intended_device_family		: STRING;
+		oe_reg => "UNREGISTERED",
-		invert_output		: STRING;
+		power_up_high => "OFF",
-		lpm_type		: STRING;
+		width => 1
-		oe_reg		: STRING;
+	)
-		power_up_high		: STRING;
+	PORT MAP (
-		width		: NATURAL
+		datain_h => datain_h,
-	);
+		datain_l => datain_l,
-	PORT (
+		outclock => outclock,
-			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout => sub_wire0
-			outclock	: IN STD_LOGIC ;
+	);
-			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+
-			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+
-	);
+
-	END COMPONENT;
+END SYN;
-
+
-BEGIN
+-- ============================================================
-	sub_wire1    <= sub_wire0(0);
+-- CNX file retrieval info
-	dataout    <= sub_wire1;
+-- ============================================================
-	sub_wire2    <= datain_h;
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-	sub_wire3(0)    <= sub_wire2;
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-	sub_wire4    <= datain_l;
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-	sub_wire5(0)    <= sub_wire4;
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-	altddio_out_component : altddio_out
+-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-	GENERIC MAP (
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-		extend_oe_disable => "UNUSED",
+-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-		intended_device_family => "Cyclone III",
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-		invert_output => "OFF",
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
-		lpm_type => "altddio_out",
+-- Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
-		oe_reg => "UNUSED",
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
-		power_up_high => "OFF",
+-- Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
-		width => 1
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
-	)
+-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-	PORT MAP (
+-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-		outclock => outclock,
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
-		datain_h => sub_wire3,
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-		datain_l => sub_wire5,
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE FALSE
-		dataout => sub_wire0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.qip TRUE FALSE
-	);
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE TRUE
-
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE TRUE
-
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE TRUE
-
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE TRUE
-END SYN;
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE FALSE
-
+-- Retrieval info: LIB_FILE: altera_mf
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
--- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
--- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: OE NUMERIC "0"
--- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
--- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
--- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
--- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
--- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
--- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
--- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
--- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
--- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf

altpll1.bsf

@@ -1,100 +1,100 @@
-/*
+/*
-WARNING: Do NOT edit the input and output ports in this file in a text
+WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
+editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
+the Block Editor! File corruption is VERY likely to occur.
-*/
+*/
-/*
+/*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
+Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
+functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
+(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
+associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
+to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
+Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
+Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
+without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
+programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
+Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+applicable agreement for further details.
-*/
+*/
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
-(symbol
+(symbol
-	(rect 0 0 328 216)
+	(rect 0 0 272 176)
-	(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
+	(text "altpll1" (rect 119 0 161 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 197 31 212)(font "Arial" ))
+	(text "inst" (rect 8 161 26 172)(font "Arial" ))
-	(port
+	(port
-		(pt 0 72)
+		(pt 0 64)
-		(input)
+		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
+		(line (pt 0 64)(pt 40 64))
-	)
+	)
-	(port
+	(port
-		(pt 328 72)
+		(pt 272 64)
-		(output)
+		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
-		(line (pt 328 72)(pt 272 72)(line_width 1))
+	)
-	)
+	(port
-	(port
+		(pt 272 80)
-		(pt 328 96)
+		(output)
-		(output)
+		(text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 269 79)(font "Arial" (font_size 8)))
-		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
+	)
-		(line (pt 328 96)(pt 272 96)(line_width 1))
+	(port
-	)
+		(pt 272 96)
-	(port
+		(output)
-		(pt 328 120)
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(output)
+		(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+	)
-		(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
+	(port
-		(line (pt 328 120)(pt 272 120)(line_width 1))
+		(pt 272 112)
-	)
+		(output)
-	(port
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
-		(pt 328 144)
+		(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
-		(output)
+	)
-		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+	(drawing
-		(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
+		(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
-		(line (pt 328 144)(pt 272 144)(line_width 1))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
-	)
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
-	(drawing
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
-		(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
+		(text "Ratio" (rect 74 91 171 192)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Ph (dg)" (rect 104 91 239 192)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "DC (%)" (rect 139 91 310 192)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
-		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
+		(text "1/66" (rect 76 104 171 218)(font "Arial" ))
-		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
+		(text "0.00" (rect 110 104 239 218)(font "Arial" ))
-		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
+		(text "50.00" (rect 143 104 310 218)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "c1" (rect 54 117 119 244)(font "Arial" ))
-		(text "1/66" (rect 92 129 113 143)(font "Arial" ))
+		(text "67/900" (rect 71 117 171 244)(font "Arial" ))
-		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
+		(text "0.00" (rect 110 117 239 244)(font "Arial" ))
-		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
+		(text "50.00" (rect 143 117 310 244)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
-		(text "67/900" (rect 85 147 118 161)(font "Arial" ))
+		(text "67/90" (rect 74 130 172 270)(font "Arial" ))
-		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
+		(text "0.00" (rect 110 130 239 270)(font "Arial" ))
-		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
+		(text "50.00" (rect 143 130 310 270)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0))
-		(text "67/90" (rect 89 165 116 179)(font "Arial" ))
+		(line (pt 273 0)(pt 273 177))
-		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
+		(line (pt 0 177)(pt 273 177))
-		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
+		(line (pt 0 0)(pt 0 177))
-		(line (pt 0 0)(pt 329 0)(line_width 1))
+		(line (pt 48 89)(pt 171 89))
-		(line (pt 329 0)(pt 329 217)(line_width 1))
+		(line (pt 48 101)(pt 171 101))
-		(line (pt 0 217)(pt 329 217)(line_width 1))
+		(line (pt 48 114)(pt 171 114))
-		(line (pt 0 0)(pt 0 217)(line_width 1))
+		(line (pt 48 127)(pt 171 127))
-		(line (pt 56 108)(pt 215 108)(line_width 1))
+		(line (pt 48 140)(pt 171 140))
-		(line (pt 56 125)(pt 215 125)(line_width 1))
+		(line (pt 48 89)(pt 48 140))
-		(line (pt 56 143)(pt 215 143)(line_width 1))
+		(line (pt 68 89)(pt 68 140)(line_width 3))
-		(line (pt 56 161)(pt 215 161)(line_width 1))
+		(line (pt 101 89)(pt 101 140)(line_width 3))
-		(line (pt 56 179)(pt 215 179)(line_width 1))
+		(line (pt 136 89)(pt 136 140)(line_width 3))
-		(line (pt 56 108)(pt 56 179)(line_width 1))
+		(line (pt 170 89)(pt 170 140))
-		(line (pt 82 108)(pt 82 179)(line_width 3))
+		(line (pt 40 48)(pt 223 48))
-		(line (pt 125 108)(pt 125 179)(line_width 3))
+		(line (pt 223 48)(pt 223 159))
-		(line (pt 170 108)(pt 170 179)(line_width 3))
+		(line (pt 40 159)(pt 223 159))
-		(line (pt 214 108)(pt 214 179)(line_width 1))
+		(line (pt 40 48)(pt 40 159))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 271 64)(pt 223 64))
-		(line (pt 272 56)(pt 272 200)(line_width 1))
+		(line (pt 271 80)(pt 223 80))
-		(line (pt 48 200)(pt 272 200)(line_width 1))
+		(line (pt 271 96)(pt 223 96))
-		(line (pt 48 56)(pt 48 200)(line_width 1))
+		(line (pt 271 112)(pt 223 112))
-	)
+	)
-)
+)

altpll1.cmp

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-component altpll1
+component altpll1
-	PORT
+	PORT
-	(
+	(
-		inclk0		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
+		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
+		locked		: OUT STD_LOGIC 
-	);
+	);
-end component;
+end component;

altpll1.inc

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
+--Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
+--and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
+--functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
+--(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
+--associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
+--to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
+--Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
+--Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
+--without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
+--programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
+--Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
+--applicable agreement for further details.
-
+
-
+
-FUNCTION altpll1 
+FUNCTION altpll1 
-(
+(
-	inclk0
+	inclk0
-)
+)
-
+
-RETURNS (
+RETURNS (
-	c0,
+	c0,
-	c1,
+	c1,
-	c2,
+	c2,
-	locked
+	locked
-);
+);