added sdc file and upgraded IP components
This commit is contained in:
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
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|||||||
the Block Editor! File corruption is VERY likely to occur.
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the Block Editor! File corruption is VERY likely to occur.
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||||||
*/
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*/
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||||||
/*
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/*
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||||||
Copyright (C) 1991-2008 Altera Corporation
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Copyright (C) 1991-2013 Altera Corporation
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||||||
Your use of Altera Corporation's design tools, logic functions
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Your use of Altera Corporation's design tools, logic functions
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||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
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||||||
functions, and any output files from any of the foregoing
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functions, and any output files from any of the foregoing
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||||||
@@ -18,82 +18,82 @@ programming logic devices manufactured by Altera and sold by
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|||||||
Altera or its authorized distributors. Please refer to the
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Altera or its authorized distributors. Please refer to the
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||||||
applicable agreement for further details.
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applicable agreement for further details.
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||||||
*/
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*/
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||||||
(header "symbol" (version "1.1"))
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(header "symbol" (version "1.2"))
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||||||
(symbol
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(symbol
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||||||
(rect 0 0 240 136)
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(rect 0 0 272 144)
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||||||
(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
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(text "altddio_bidir0" (rect 94 0 202 17)(font "Dialog" (font_size 10)))
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||||||
(text "inst" (rect 8 120 25 132)(font "Arial" ))
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(text "inst" (rect 8 129 26 140)(font "Arial" ))
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||||||
(port
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(port
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||||||
(pt 0 24)
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(pt 0 48)
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||||||
(input)
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(input)
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||||||
(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
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(text "datain_h[31..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
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||||||
(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
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(text "datain_h[31..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
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||||||
(line (pt 0 24)(pt 88 24)(line_width 3))
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(line (pt 0 48)(pt 96 48)(line_width 3))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 0 40)
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(pt 0 64)
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||||||
(input)
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(input)
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||||||
(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
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(text "datain_l[31..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
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||||||
(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
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(text "datain_l[31..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
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||||||
(line (pt 0 40)(pt 88 40)(line_width 3))
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(line (pt 0 64)(pt 96 64)(line_width 3))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 0 56)
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(pt 0 80)
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||||||
(input)
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(input)
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||||||
(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
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(text "oe" (rect 0 0 16 13)(font "Dialog" (font_size 8)))
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||||||
(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
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(text "oe" (rect 4 67 18 79)(font "Dialog" (font_size 8)))
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||||||
(line (pt 0 56)(pt 88 56)(line_width 1))
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(line (pt 0 80)(pt 96 80))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 0 72)
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(pt 0 96)
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||||||
(input)
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(input)
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||||||
(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
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(text "inclock" (rect 0 0 47 13)(font "Dialog" (font_size 8)))
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||||||
(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
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(text "inclock" (rect 4 83 43 95)(font "Dialog" (font_size 8)))
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||||||
(line (pt 0 72)(pt 88 72)(line_width 1))
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(line (pt 0 96)(pt 96 96))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 0 88)
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(pt 0 112)
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||||||
(input)
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(input)
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||||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
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(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
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||||||
(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
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(text "outclock" (rect 4 99 52 111)(font "Dialog" (font_size 8)))
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||||||
(line (pt 0 88)(pt 88 88)(line_width 1))
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(line (pt 0 112)(pt 96 112))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 240 24)
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(pt 272 48)
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||||||
(output)
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(output)
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||||||
(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
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(text "dataout_h[31..0]" (rect 0 0 106 13)(font "Dialog" (font_size 8)))
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||||||
(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
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(text "dataout_h[31..0]" (rect 176 35 267 47)(font "Dialog" (font_size 8)))
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||||||
(line (pt 240 24)(pt 144 24)(line_width 3))
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(line (pt 272 48)(pt 160 48)(line_width 3))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 240 40)
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(pt 272 64)
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||||||
(output)
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(output)
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||||||
(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
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(text "dataout_l[31..0]" (rect 0 0 102 13)(font "Dialog" (font_size 8)))
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||||||
(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
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(text "dataout_l[31..0]" (rect 180 51 267 63)(font "Dialog" (font_size 8)))
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||||||
(line (pt 240 40)(pt 144 40)(line_width 3))
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(line (pt 272 64)(pt 160 64)(line_width 3))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 240 72)
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(pt 272 80)
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||||||
(output)
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(output)
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||||||
(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
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(text "padio[31..0]" (rect 0 0 77 13)(font "Dialog" (font_size 8)))
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||||||
(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
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(text "padio[31..0]" (rect 201 67 268 79)(font "Dialog" (font_size 8)))
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||||||
(line (pt 240 72)(pt 144 72)(line_width 3))
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(line (pt 272 80)(pt 160 80)(line_width 3))
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||||||
)
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)
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||||||
(port
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(port
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||||||
(pt 240 56)
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(pt 272 96)
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(bidir)
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(output)
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(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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(text "combout[31..0]" (rect 0 0 99 13)(font "Dialog" (font_size 8)))
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||||||
(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
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(text "combout[31..0]" (rect 183 83 267 95)(font "Dialog" (font_size 8)))
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||||||
(line (pt 240 56)(pt 144 56)(line_width 3))
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(line (pt 272 96)(pt 160 96)(line_width 3))
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||||||
)
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)
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||||||
(drawing
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(drawing
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||||||
(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
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(line (pt 96 32)(pt 160 32))
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||||||
(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
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(line (pt 160 32)(pt 160 128))
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||||||
(text "power up" (rect 92 90 129 102)(font "Arial" ))
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(line (pt 96 128)(pt 160 128))
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||||||
(text "low" (rect 92 100 105 112)(font "Arial" ))
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(line (pt 96 32)(pt 96 128))
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||||||
(line (pt 88 16)(pt 144 16)(line_width 1))
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(line (pt 0 0)(pt 272 0))
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||||||
(line (pt 144 16)(pt 144 112)(line_width 1))
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(line (pt 272 0)(pt 272 144))
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||||||
(line (pt 144 112)(pt 88 112)(line_width 1))
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(line (pt 0 144)(pt 272 144))
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||||||
(line (pt 88 112)(pt 88 16)(line_width 1))
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(line (pt 0 0)(pt 0 144))
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||||||
)
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)
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||||||
)
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)
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||||||
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|||||||
@@ -1,4 +1,4 @@
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|||||||
--Copyright (C) 1991-2008 Altera Corporation
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--Copyright (C) 1991-2013 Altera Corporation
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||||||
--Your use of Altera Corporation's design tools, logic functions
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--Your use of Altera Corporation's design tools, logic functions
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||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
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||||||
--functions, and any output files from any of the foregoing
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--functions, and any output files from any of the foregoing
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@@ -19,7 +19,7 @@ component altddio_bidir0
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datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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inclock : IN STD_LOGIC ;
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inclock : IN STD_LOGIC ;
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oe : IN STD_LOGIC := '1';
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oe : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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@@ -1,4 +1,4 @@
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--Copyright (C) 1991-2008 Altera Corporation
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--Copyright (C) 1991-2013 Altera Corporation
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||||||
--Your use of Altera Corporation's design tools, logic functions
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--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
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||||||
--functions, and any output files from any of the foregoing
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--functions, and any output files from any of the foregoing
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||||||
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@@ -1,5 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
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set_global_assignment -name IP_TOOL_VERSION "8.1"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
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@@ -1,12 +1,12 @@
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-- megafunction wizard: %ALTDDIO_BIDIR%
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-- megafunction wizard: %ALTDDIO_BIDIR%
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-- GENERATION: STANDARD
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- VERSION: WM1.0
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-- MODULE: altddio_bidir
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-- MODULE: ALTDDIO_BIDIR
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||||||
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-- ============================================================
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-- ============================================================
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-- File Name: altddio_bidir0.vhd
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-- File Name: altddio_bidir0.vhd
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-- Megafunction Name(s):
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-- Megafunction Name(s):
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-- altddio_bidir
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-- ALTDDIO_BIDIR
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--
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--
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-- Simulation Library Files(s):
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-- Simulation Library Files(s):
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-- altera_mf
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-- altera_mf
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@@ -14,11 +14,11 @@
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-- ************************************************************
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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--
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-- 8.1 Build 163 10/28/2008 SJ Web Edition
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-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
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-- ************************************************************
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-- ************************************************************
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||||||
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||||||
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||||||
--Copyright (C) 1991-2008 Altera Corporation
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--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
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--functions, and any output files from any of the foregoing
|
||||||
@@ -37,7 +37,7 @@ LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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LIBRARY altera_mf;
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USE altera_mf.all;
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USE altera_mf.altera_mf_components.all;
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ENTITY altddio_bidir0 IS
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ENTITY altddio_bidir0 IS
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PORT
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PORT
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@@ -45,7 +45,7 @@ ENTITY altddio_bidir0 IS
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datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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inclock : IN STD_LOGIC ;
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inclock : IN STD_LOGIC ;
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oe : IN STD_LOGIC := '1';
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oe : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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@@ -61,56 +61,31 @@ ARCHITECTURE SYN OF altddio_bidir0 IS
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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COMPONENT altddio_bidir
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GENERIC (
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extend_oe_disable : STRING;
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implement_input_in_lcell : STRING;
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intended_device_family : STRING;
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invert_output : STRING;
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lpm_type : STRING;
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oe_reg : STRING;
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power_up_high : STRING;
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width : NATURAL
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);
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PORT (
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outclock : IN STD_LOGIC ;
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padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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inclock : IN STD_LOGIC ;
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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||||||
oe : IN STD_LOGIC ;
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||||||
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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||||||
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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||||||
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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||||||
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
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||||||
);
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||||||
END COMPONENT;
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||||||
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||||||
BEGIN
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BEGIN
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||||||
dataout_h <= sub_wire0(31 DOWNTO 0);
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combout <= sub_wire0(31 DOWNTO 0);
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||||||
combout <= sub_wire1(31 DOWNTO 0);
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dataout_h <= sub_wire1(31 DOWNTO 0);
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||||||
dataout_l <= sub_wire2(31 DOWNTO 0);
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dataout_l <= sub_wire2(31 DOWNTO 0);
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||||||
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||||||
altddio_bidir_component : altddio_bidir
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ALTDDIO_BIDIR_component : ALTDDIO_BIDIR
|
||||||
GENERIC MAP (
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GENERIC MAP (
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||||||
extend_oe_disable => "UNUSED",
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extend_oe_disable => "OFF",
|
||||||
implement_input_in_lcell => "ON",
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implement_input_in_lcell => "ON",
|
||||||
intended_device_family => "Cyclone III",
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intended_device_family => "Cyclone III",
|
||||||
invert_output => "OFF",
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invert_output => "OFF",
|
||||||
|
lpm_hint => "UNUSED",
|
||||||
lpm_type => "altddio_bidir",
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lpm_type => "altddio_bidir",
|
||||||
oe_reg => "UNUSED",
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oe_reg => "UNREGISTERED",
|
||||||
power_up_high => "OFF",
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power_up_high => "OFF",
|
||||||
width => 32
|
width => 32
|
||||||
)
|
)
|
||||||
PORT MAP (
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PORT MAP (
|
||||||
outclock => outclock,
|
|
||||||
inclock => inclock,
|
|
||||||
oe => oe,
|
|
||||||
datain_h => datain_h,
|
datain_h => datain_h,
|
||||||
datain_l => datain_l,
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datain_l => datain_l,
|
||||||
dataout_h => sub_wire0,
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oe => oe,
|
||||||
combout => sub_wire1,
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outclock => outclock,
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||||||
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inclock => inclock,
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||||||
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combout => sub_wire0,
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||||||
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dataout_h => sub_wire1,
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||||||
dataout_l => sub_wire2,
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dataout_l => sub_wire2,
|
||||||
padio => padio
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padio => padio
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||||||
);
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);
|
||||||
@@ -122,51 +97,40 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- CNX file retrieval info
|
-- CNX file retrieval info
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: OE NUMERIC "1"
|
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
|
|
||||||
-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
|
|
||||||
-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
|
|
||||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
|
||||||
-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
|
-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
|
||||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||||
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
|
||||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
|
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
|
||||||
-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
|
-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]"
|
||||||
-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
|
|
||||||
-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
|
|
||||||
-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
|
|
||||||
-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
|
|
||||||
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
|
|
||||||
-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
|
|
||||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
|
||||||
-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
|
|
||||||
-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
|
-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
|
||||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]"
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
|
-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
|
-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]"
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
|
-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
|
-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]"
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
|
-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
|
-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]"
|
||||||
|
-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
|
||||||
|
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
|
||||||
|
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
|
||||||
|
-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
|
||||||
|
-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
|
||||||
|
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||||
|
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||||
|
-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]"
|
||||||
|
-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE FALSE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE TRUE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE TRUE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE TRUE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE TRUE
|
||||||
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE
|
||||||
-- Retrieval info: LIB_FILE: altera_mf
|
-- Retrieval info: LIB_FILE: altera_mf
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 232 120)
|
(rect 0 0 256 112)
|
||||||
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
(text "altddio_out0" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
|
||||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
(text "inst" (rect 8 97 26 108)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 24)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
|
(text "datain_h[3..0]" (rect 0 0 89 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
|
(text "datain_h[3..0]" (rect 4 35 80 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 24)(pt 88 24)(line_width 3))
|
(line (pt 0 48)(pt 96 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 64)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
|
(text "datain_l[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
|
(text "datain_l[3..0]" (rect 4 51 76 63)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 88 40)(line_width 3))
|
(line (pt 0 64)(pt 96 64)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 80)
|
||||||
(input)
|
(input)
|
||||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
|
||||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
(line (pt 0 80)(pt 96 80))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 232 24)
|
(pt 256 48)
|
||||||
(output)
|
(output)
|
||||||
(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
|
(text "dataout[3..0]" (rect 0 0 84 13)(font "Dialog" (font_size 8)))
|
||||||
(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
|
(text "dataout[3..0]" (rect 180 35 252 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 232 24)(pt 152 24)(line_width 3))
|
(line (pt 256 48)(pt 160 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
(line (pt 96 32)(pt 160 32))
|
||||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
(line (pt 160 32)(pt 160 96))
|
||||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
(line (pt 96 96)(pt 160 96))
|
||||||
(text "high" (rect 92 84 109 96)(font "Arial" ))
|
(line (pt 96 32)(pt 96 96))
|
||||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
(line (pt 0 0)(pt 256 0))
|
||||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
(line (pt 256 0)(pt 256 112))
|
||||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
(line (pt 0 112)(pt 256 112))
|
||||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
(line (pt 0 0)(pt 0 112))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %ALTDDIO_OUT%
|
-- megafunction wizard: %ALTDDIO_OUT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: altddio_out
|
-- MODULE: ALTDDIO_OUT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: altddio_out0.vhd
|
-- File Name: altddio_out0.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- altddio_out
|
-- ALTDDIO_OUT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- altera_mf
|
-- altera_mf
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -37,7 +37,7 @@ LIBRARY ieee;
|
|||||||
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
LIBRARY altera_mf;
|
LIBRARY altera_mf;
|
||||||
USE altera_mf.all;
|
USE altera_mf.altera_mf_components.all;
|
||||||
|
|
||||||
ENTITY altddio_out0 IS
|
ENTITY altddio_out0 IS
|
||||||
PORT
|
PORT
|
||||||
@@ -54,43 +54,24 @@ ARCHITECTURE SYN OF altddio_out0 IS
|
|||||||
|
|
||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
COMPONENT altddio_out
|
|
||||||
GENERIC (
|
|
||||||
extend_oe_disable : STRING;
|
|
||||||
intended_device_family : STRING;
|
|
||||||
invert_output : STRING;
|
|
||||||
lpm_type : STRING;
|
|
||||||
oe_reg : STRING;
|
|
||||||
power_up_high : STRING;
|
|
||||||
width : NATURAL
|
|
||||||
);
|
|
||||||
PORT (
|
|
||||||
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
|
|
||||||
outclock : IN STD_LOGIC ;
|
|
||||||
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
|
||||||
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
|
|
||||||
);
|
|
||||||
END COMPONENT;
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
dataout <= sub_wire0(3 DOWNTO 0);
|
dataout <= sub_wire0(3 DOWNTO 0);
|
||||||
|
|
||||||
altddio_out_component : altddio_out
|
ALTDDIO_OUT_component : ALTDDIO_OUT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
extend_oe_disable => "UNUSED",
|
extend_oe_disable => "OFF",
|
||||||
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
||||||
invert_output => "ON",
|
invert_output => "ON",
|
||||||
|
lpm_hint => "UNUSED",
|
||||||
lpm_type => "altddio_out",
|
lpm_type => "altddio_out",
|
||||||
oe_reg => "UNUSED",
|
oe_reg => "UNREGISTERED",
|
||||||
power_up_high => "ON",
|
power_up_high => "ON",
|
||||||
width => 4
|
width => 4
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
outclock => outclock,
|
|
||||||
datain_h => datain_h,
|
datain_h => datain_h,
|
||||||
datain_l => datain_l,
|
datain_l => datain_l,
|
||||||
|
outclock => outclock,
|
||||||
dataout => sub_wire0
|
dataout => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -101,36 +82,29 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- CNX file retrieval info
|
-- CNX file retrieval info
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
|
|
||||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
|
|
||||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
|
||||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
|
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
|
||||||
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
|
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
|
||||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
|
-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
|
||||||
-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
|
-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL "datain_h[3..0]"
|
||||||
-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
|
|
||||||
-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
|
|
||||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
|
||||||
-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
|
-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
|
||||||
|
-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL "datain_l[3..0]"
|
||||||
-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
|
-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
|
||||||
|
-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
|
||||||
-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
|
-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
|
||||||
|
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.qip TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE FALSE
|
||||||
-- Retrieval info: LIB_FILE: altera_mf
|
-- Retrieval info: LIB_FILE: altera_mf
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 232 120)
|
(rect 0 0 256 112)
|
||||||
(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
(text "altddio_out2" (rect 89 0 188 17)(font "Dialog" (font_size 10)))
|
||||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
(text "inst" (rect 8 97 26 108)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 24)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
(text "datain_h[23..0]" (rect 0 0 97 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
|
(text "datain_h[23..0]" (rect 4 35 87 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 24)(pt 88 24)(line_width 3))
|
(line (pt 0 48)(pt 96 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 64)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
(text "datain_l[23..0]" (rect 0 0 93 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
|
(text "datain_l[23..0]" (rect 4 51 83 63)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 88 40)(line_width 3))
|
(line (pt 0 64)(pt 96 64)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 80)
|
||||||
(input)
|
(input)
|
||||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
|
||||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
(line (pt 0 80)(pt 96 80))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 232 24)
|
(pt 256 48)
|
||||||
(output)
|
(output)
|
||||||
(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
|
(text "dataout[23..0]" (rect 0 0 92 13)(font "Dialog" (font_size 8)))
|
||||||
(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
|
(text "dataout[23..0]" (rect 173 35 252 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 232 24)(pt 152 24)(line_width 3))
|
(line (pt 256 48)(pt 160 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
(line (pt 96 32)(pt 160 32))
|
||||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
(line (pt 160 32)(pt 160 96))
|
||||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
(line (pt 96 96)(pt 160 96))
|
||||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
(line (pt 96 32)(pt 96 96))
|
||||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
(line (pt 0 0)(pt 256 0))
|
||||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
(line (pt 256 0)(pt 256 112))
|
||||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
(line (pt 0 112)(pt 256 112))
|
||||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
(line (pt 0 0)(pt 0 112))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %ALTDDIO_OUT%
|
-- megafunction wizard: %ALTDDIO_OUT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: altddio_out
|
-- MODULE: ALTDDIO_OUT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: altddio_out2.vhd
|
-- File Name: altddio_out2.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- altddio_out
|
-- ALTDDIO_OUT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- altera_mf
|
-- altera_mf
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -37,7 +37,7 @@ LIBRARY ieee;
|
|||||||
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
LIBRARY altera_mf;
|
LIBRARY altera_mf;
|
||||||
USE altera_mf.all;
|
USE altera_mf.altera_mf_components.all;
|
||||||
|
|
||||||
ENTITY altddio_out2 IS
|
ENTITY altddio_out2 IS
|
||||||
PORT
|
PORT
|
||||||
@@ -54,43 +54,24 @@ ARCHITECTURE SYN OF altddio_out2 IS
|
|||||||
|
|
||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
COMPONENT altddio_out
|
|
||||||
GENERIC (
|
|
||||||
extend_oe_disable : STRING;
|
|
||||||
intended_device_family : STRING;
|
|
||||||
invert_output : STRING;
|
|
||||||
lpm_type : STRING;
|
|
||||||
oe_reg : STRING;
|
|
||||||
power_up_high : STRING;
|
|
||||||
width : NATURAL
|
|
||||||
);
|
|
||||||
PORT (
|
|
||||||
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
|
|
||||||
outclock : IN STD_LOGIC ;
|
|
||||||
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
|
|
||||||
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
|
|
||||||
);
|
|
||||||
END COMPONENT;
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
dataout <= sub_wire0(23 DOWNTO 0);
|
dataout <= sub_wire0(23 DOWNTO 0);
|
||||||
|
|
||||||
altddio_out_component : altddio_out
|
ALTDDIO_OUT_component : ALTDDIO_OUT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
extend_oe_disable => "UNUSED",
|
extend_oe_disable => "OFF",
|
||||||
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
||||||
invert_output => "OFF",
|
invert_output => "OFF",
|
||||||
|
lpm_hint => "UNUSED",
|
||||||
lpm_type => "altddio_out",
|
lpm_type => "altddio_out",
|
||||||
oe_reg => "UNUSED",
|
oe_reg => "UNREGISTERED",
|
||||||
power_up_high => "OFF",
|
power_up_high => "OFF",
|
||||||
width => 24
|
width => 24
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
outclock => outclock,
|
|
||||||
datain_h => datain_h,
|
datain_h => datain_h,
|
||||||
datain_l => datain_l,
|
datain_l => datain_l,
|
||||||
|
outclock => outclock,
|
||||||
dataout => sub_wire0
|
dataout => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -101,36 +82,29 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- CNX file retrieval info
|
-- CNX file retrieval info
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
|
|
||||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
|
||||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||||
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
|
-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
|
||||||
-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
|
-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL "datain_h[23..0]"
|
||||||
-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
|
|
||||||
-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
|
|
||||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
|
||||||
-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
|
-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
|
||||||
|
-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL "datain_l[23..0]"
|
||||||
-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
|
-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
|
||||||
|
-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL "dataout[23..0]"
|
||||||
-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
|
-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
|
||||||
|
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.qip TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE FALSE
|
||||||
-- Retrieval info: LIB_FILE: altera_mf
|
-- Retrieval info: LIB_FILE: altera_mf
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,25 +18,32 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 96 48)
|
(rect 0 0 112 48)
|
||||||
(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
|
(text "lpm_constant0" (rect 14 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 32 25 44)(font "Arial" ))
|
(text "inst" (rect 8 33 26 44)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 96 24)
|
(pt 112 24)
|
||||||
(output)
|
(output)
|
||||||
(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[4..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
|
(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
|
||||||
(line (pt 96 24)(pt 80 24)(line_width 3))
|
(line (pt 112 24)(pt 96 24)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "0" (rect 75 18 80 30)(font "Arial" ))
|
(text "5" (rect 99 27 204 64)(font "Arial" ))
|
||||||
(text "5" (rect 87 25 92 37)(font "Arial" ))
|
(line (pt 106 20)(pt 98 28))
|
||||||
(line (pt 16 16)(pt 80 16)(line_width 1))
|
(line (pt 16 16)(pt 16 32))
|
||||||
(line (pt 80 16)(pt 80 32)(line_width 1))
|
(line (pt 16 16)(pt 96 16))
|
||||||
(line (pt 80 32)(pt 16 32)(line_width 1))
|
(line (pt 16 32)(pt 96 32))
|
||||||
(line (pt 16 32)(pt 16 16)(line_width 1))
|
(line (pt 96 16)(pt 96 32))
|
||||||
(line (pt 82 28)(pt 90 20)(line_width 1))
|
(line (pt 0 0)(pt 114 0))
|
||||||
|
(line (pt 114 0)(pt 114 50))
|
||||||
|
(line (pt 0 50)(pt 114 50))
|
||||||
|
(line (pt 0 0)(pt 0 50))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_CONSTANT%
|
-- megafunction wizard: %LPM_CONSTANT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_constant
|
-- MODULE: LPM_CONSTANT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_constant0.vhd
|
-- File Name: lpm_constant0.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_constant
|
-- LPM_CONSTANT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant0 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
result <= sub_wire0(4 DOWNTO 0);
|
result <= sub_wire0(4 DOWNTO 0);
|
||||||
|
|
||||||
lpm_constant_component : lpm_constant
|
LPM_CONSTANT_component : LPM_CONSTANT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_cvalue => 0,
|
lpm_cvalue => 0,
|
||||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||||
@@ -93,16 +93,17 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
|
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
|
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,25 +18,32 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 96 48)
|
(rect 0 0 112 48)
|
||||||
(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
|
(text "lpm_constant1" (rect 14 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 32 25 44)(font "Arial" ))
|
(text "inst" (rect 8 33 26 44)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 96 24)
|
(pt 112 24)
|
||||||
(output)
|
(output)
|
||||||
(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[1..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
|
(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
|
||||||
(line (pt 96 24)(pt 80 24)(line_width 3))
|
(line (pt 112 24)(pt 96 24)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "0" (rect 75 18 80 30)(font "Arial" ))
|
(text "2" (rect 99 27 204 64)(font "Arial" ))
|
||||||
(text "2" (rect 87 25 92 37)(font "Arial" ))
|
(line (pt 106 20)(pt 98 28))
|
||||||
(line (pt 16 16)(pt 80 16)(line_width 1))
|
(line (pt 16 16)(pt 16 32))
|
||||||
(line (pt 80 16)(pt 80 32)(line_width 1))
|
(line (pt 16 16)(pt 96 16))
|
||||||
(line (pt 80 32)(pt 16 32)(line_width 1))
|
(line (pt 16 32)(pt 96 32))
|
||||||
(line (pt 16 32)(pt 16 16)(line_width 1))
|
(line (pt 96 16)(pt 96 32))
|
||||||
(line (pt 82 28)(pt 90 20)(line_width 1))
|
(line (pt 0 0)(pt 114 0))
|
||||||
|
(line (pt 114 0)(pt 114 50))
|
||||||
|
(line (pt 0 50)(pt 114 50))
|
||||||
|
(line (pt 0 0)(pt 0 50))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_CONSTANT%
|
-- megafunction wizard: %LPM_CONSTANT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_constant
|
-- MODULE: LPM_CONSTANT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_constant1.vhd
|
-- File Name: lpm_constant1.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_constant
|
-- LPM_CONSTANT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant1 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
result <= sub_wire0(1 DOWNTO 0);
|
result <= sub_wire0(1 DOWNTO 0);
|
||||||
|
|
||||||
lpm_constant_component : lpm_constant
|
LPM_CONSTANT_component : LPM_CONSTANT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_cvalue => 0,
|
lpm_cvalue => 0,
|
||||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||||
@@ -93,16 +93,17 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
|
-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL "result[1..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
|
-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,25 +18,32 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 96 48)
|
(rect 0 0 112 48)
|
||||||
(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
|
(text "lpm_constant2" (rect 14 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 32 25 44)(font "Arial" ))
|
(text "inst" (rect 8 33 26 44)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 96 24)
|
(pt 112 24)
|
||||||
(output)
|
(output)
|
||||||
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
|
(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
|
||||||
(line (pt 96 24)(pt 80 24)(line_width 3))
|
(line (pt 112 24)(pt 96 24)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "0" (rect 75 18 80 30)(font "Arial" ))
|
(text "8" (rect 99 27 204 64)(font "Arial" ))
|
||||||
(text "8" (rect 87 25 92 37)(font "Arial" ))
|
(line (pt 106 20)(pt 98 28))
|
||||||
(line (pt 16 16)(pt 80 16)(line_width 1))
|
(line (pt 16 16)(pt 16 32))
|
||||||
(line (pt 80 16)(pt 80 32)(line_width 1))
|
(line (pt 16 16)(pt 96 16))
|
||||||
(line (pt 80 32)(pt 16 32)(line_width 1))
|
(line (pt 16 32)(pt 96 32))
|
||||||
(line (pt 16 32)(pt 16 16)(line_width 1))
|
(line (pt 96 16)(pt 96 32))
|
||||||
(line (pt 82 28)(pt 90 20)(line_width 1))
|
(line (pt 0 0)(pt 114 0))
|
||||||
|
(line (pt 114 0)(pt 114 50))
|
||||||
|
(line (pt 0 50)(pt 114 50))
|
||||||
|
(line (pt 0 0)(pt 0 50))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_CONSTANT%
|
-- megafunction wizard: %LPM_CONSTANT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_constant
|
-- MODULE: LPM_CONSTANT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_constant2.vhd
|
-- File Name: lpm_constant2.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_constant
|
-- LPM_CONSTANT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant2 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
result <= sub_wire0(7 DOWNTO 0);
|
result <= sub_wire0(7 DOWNTO 0);
|
||||||
|
|
||||||
lpm_constant_component : lpm_constant
|
LPM_CONSTANT_component : LPM_CONSTANT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_cvalue => 0,
|
lpm_cvalue => 0,
|
||||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||||
@@ -93,16 +93,17 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
|
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,25 +18,32 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 96 48)
|
(rect 0 0 112 48)
|
||||||
(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
|
(text "lpm_constant3" (rect 14 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 32 25 44)(font "Arial" ))
|
(text "inst" (rect 8 33 26 44)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 96 24)
|
(pt 112 24)
|
||||||
(output)
|
(output)
|
||||||
(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
|
(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
|
||||||
(line (pt 96 24)(pt 80 24)(line_width 3))
|
(line (pt 112 24)(pt 96 24)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "0" (rect 75 18 80 30)(font "Arial" ))
|
(text "7" (rect 99 27 204 64)(font "Arial" ))
|
||||||
(text "7" (rect 87 25 92 37)(font "Arial" ))
|
(line (pt 106 20)(pt 98 28))
|
||||||
(line (pt 16 16)(pt 80 16)(line_width 1))
|
(line (pt 16 16)(pt 16 32))
|
||||||
(line (pt 80 16)(pt 80 32)(line_width 1))
|
(line (pt 16 16)(pt 96 16))
|
||||||
(line (pt 80 32)(pt 16 32)(line_width 1))
|
(line (pt 16 32)(pt 96 32))
|
||||||
(line (pt 16 32)(pt 16 16)(line_width 1))
|
(line (pt 96 16)(pt 96 32))
|
||||||
(line (pt 82 28)(pt 90 20)(line_width 1))
|
(line (pt 0 0)(pt 114 0))
|
||||||
|
(line (pt 114 0)(pt 114 50))
|
||||||
|
(line (pt 0 50)(pt 114 50))
|
||||||
|
(line (pt 0 0)(pt 0 50))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_CONSTANT%
|
-- megafunction wizard: %LPM_CONSTANT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_constant
|
-- MODULE: LPM_CONSTANT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_constant3.vhd
|
-- File Name: lpm_constant3.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_constant
|
-- LPM_CONSTANT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -68,7 +68,7 @@ ARCHITECTURE SYN OF lpm_constant3 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
result <= sub_wire0(6 DOWNTO 0);
|
result <= sub_wire0(6 DOWNTO 0);
|
||||||
|
|
||||||
lpm_constant_component : lpm_constant
|
LPM_CONSTANT_component : LPM_CONSTANT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_cvalue => 0,
|
lpm_cvalue => 0,
|
||||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||||
@@ -93,16 +93,17 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
-- Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "7"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "7"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
|
-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,66 +18,74 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 152 128)
|
(rect 0 0 144 128)
|
||||||
(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux0" (rect 43 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
(text "inst" (rect 8 113 26 124)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data3x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
|
(text "data3x[31..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 72 40)(line_width 3))
|
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data2x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
|
(text "data2x[31..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 72 56)(line_width 3))
|
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 72)
|
||||||
(input)
|
(input)
|
||||||
(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data1x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
|
(text "data1x[31..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 72 72)(line_width 3))
|
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 88)
|
(pt 0 88)
|
||||||
(input)
|
(input)
|
||||||
(text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data0x[31..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
|
(text "data0x[31..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 88)(pt 72 88)(line_width 3))
|
(line (pt 0 88)(pt 64 88)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 104)
|
(pt 0 104)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
|
(text "clock" (rect 4 91 29 103)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 104)(pt 72 104)(line_width 1))
|
(line (pt 0 104)(pt 64 104))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 80 128)
|
(pt 72 128)
|
||||||
(input)
|
(input)
|
||||||
(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8)))
|
(text "sel[1..0]" (rect 66 73 78 111)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 80 128)(pt 80 116)(line_width 3))
|
(line (pt 72 128)(pt 72 116)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 152 72)
|
(pt 144 72)
|
||||||
(output)
|
(output)
|
||||||
(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "result[31..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
|
(text "result[31..0]" (rect 85 59 142 71)(font "Arial" (font_size 8)))
|
||||||
(line (pt 152 72)(pt 88 72)(line_width 3))
|
(line (pt 144 72)(pt 80 72)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 72 24)(pt 72 120)(line_width 1))
|
(line (pt 64 24)(pt 64 120))
|
||||||
(line (pt 88 32)(pt 88 112)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 72 24)(pt 88 32)(line_width 1))
|
(line (pt 64 120)(pt 80 112))
|
||||||
(line (pt 72 120)(pt 88 112)(line_width 1))
|
(line (pt 80 32)(pt 80 112))
|
||||||
(line (pt 72 98)(pt 78 104)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 78 104)(pt 72 110)(line_width 1))
|
(line (pt 146 0)(pt 146 130))
|
||||||
|
(line (pt 0 130)(pt 146 130))
|
||||||
|
(line (pt 0 0)(pt 0 130))
|
||||||
|
(line (pt 64 98)(pt 70 104))
|
||||||
|
(line (pt 70 104)(pt 64 110))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux0.vhd
|
-- File Name: lpm_mux0.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -199,7 +199,7 @@ BEGIN
|
|||||||
sub_wire2(0, 30) <= sub_wire5(30);
|
sub_wire2(0, 30) <= sub_wire5(30);
|
||||||
sub_wire2(0, 31) <= sub_wire5(31);
|
sub_wire2(0, 31) <= sub_wire5(31);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_pipeline => 4,
|
lpm_pipeline => 4,
|
||||||
lpm_size => 4,
|
lpm_size => 4,
|
||||||
@@ -208,9 +208,9 @@ BEGIN
|
|||||||
lpm_widths => 2
|
lpm_widths => 2
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -223,29 +223,30 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL "data2x[31..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL "data3x[31..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
|
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
|
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
|
-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,94 +18,102 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 152 192)
|
(rect 0 0 144 192)
|
||||||
(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux1" (rect 43 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 176 25 188)(font "Arial" ))
|
(text "inst" (rect 8 177 26 188)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data7x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
|
(text "data7x[15..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 72 40)(line_width 3))
|
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data6x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
|
(text "data6x[15..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 72 56)(line_width 3))
|
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 72)
|
||||||
(input)
|
(input)
|
||||||
(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data5x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
|
(text "data5x[15..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 72 72)(line_width 3))
|
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 88)
|
(pt 0 88)
|
||||||
(input)
|
(input)
|
||||||
(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data4x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
|
(text "data4x[15..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 88)(pt 72 88)(line_width 3))
|
(line (pt 0 88)(pt 64 88)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 104)
|
(pt 0 104)
|
||||||
(input)
|
(input)
|
||||||
(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data3x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
|
(text "data3x[15..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 104)(pt 72 104)(line_width 3))
|
(line (pt 0 104)(pt 64 104)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 120)
|
(pt 0 120)
|
||||||
(input)
|
(input)
|
||||||
(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data2x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
|
(text "data2x[15..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 120)(pt 72 120)(line_width 3))
|
(line (pt 0 120)(pt 64 120)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 136)
|
(pt 0 136)
|
||||||
(input)
|
(input)
|
||||||
(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data1x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
|
(text "data1x[15..0]" (rect 4 123 67 135)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 136)(pt 72 136)(line_width 3))
|
(line (pt 0 136)(pt 64 136)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 152)
|
(pt 0 152)
|
||||||
(input)
|
(input)
|
||||||
(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data0x[15..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
|
(text "data0x[15..0]" (rect 4 139 67 151)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 152)(pt 72 152)(line_width 3))
|
(line (pt 0 152)(pt 64 152)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 168)
|
(pt 0 168)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
|
(text "clock" (rect 4 155 29 167)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 168)(pt 72 168)(line_width 1))
|
(line (pt 0 168)(pt 64 168))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 80 192)
|
(pt 72 192)
|
||||||
(input)
|
(input)
|
||||||
(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
(text "sel[2..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
|
(text "sel[2..0]" (rect 66 137 78 175)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 80 192)(pt 80 180)(line_width 3))
|
(line (pt 72 192)(pt 72 180)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 152 104)
|
(pt 144 104)
|
||||||
(output)
|
(output)
|
||||||
(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "result[15..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
|
(text "result[15..0]" (rect 85 91 142 103)(font "Arial" (font_size 8)))
|
||||||
(line (pt 152 104)(pt 88 104)(line_width 3))
|
(line (pt 144 104)(pt 80 104)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 72 24)(pt 72 184)(line_width 1))
|
(line (pt 64 24)(pt 64 184))
|
||||||
(line (pt 88 32)(pt 88 176)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 72 24)(pt 88 32)(line_width 1))
|
(line (pt 64 184)(pt 80 176))
|
||||||
(line (pt 72 184)(pt 88 176)(line_width 1))
|
(line (pt 80 32)(pt 80 176))
|
||||||
(line (pt 72 162)(pt 78 168)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 78 168)(pt 72 174)(line_width 1))
|
(line (pt 146 0)(pt 146 194))
|
||||||
|
(line (pt 0 194)(pt 146 194))
|
||||||
|
(line (pt 0 0)(pt 0 194))
|
||||||
|
(line (pt 64 162)(pt 70 168))
|
||||||
|
(line (pt 70 168)(pt 64 174))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux1.vhd
|
-- File Name: lpm_mux1.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -211,7 +211,7 @@ BEGIN
|
|||||||
sub_wire2(0, 14) <= sub_wire9(14);
|
sub_wire2(0, 14) <= sub_wire9(14);
|
||||||
sub_wire2(0, 15) <= sub_wire9(15);
|
sub_wire2(0, 15) <= sub_wire9(15);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_pipeline => 4,
|
lpm_pipeline => 4,
|
||||||
lpm_size => 8,
|
lpm_size => 8,
|
||||||
@@ -220,9 +220,9 @@ BEGIN
|
|||||||
lpm_widths => 3
|
lpm_widths => 3
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -235,37 +235,38 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
|
-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
|
-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
|
-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
|
-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
|
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
|
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
|
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,150 +18,158 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 144 320)
|
(rect 0 0 144 320)
|
||||||
(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux2" (rect 43 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 304 25 316)(font "Arial" ))
|
(text "inst" (rect 8 305 26 316)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data15x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
|
(text "data15x[7..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 72 40)(line_width 3))
|
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data14x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
|
(text "data14x[7..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 72 56)(line_width 3))
|
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 72)
|
||||||
(input)
|
(input)
|
||||||
(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data13x[7..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
|
(text "data13x[7..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 72 72)(line_width 3))
|
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 88)
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|
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|
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(text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
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|
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|
||||||
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|
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|
||||||
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|
||||||
(text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
|
(text "data11x[7..0]" (rect 4 91 67 103)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 104)(pt 72 104)(line_width 3))
|
(line (pt 0 104)(pt 64 104)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
(text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
|
(text "data10x[7..0]" (rect 4 107 67 119)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 120)(pt 72 120)(line_width 3))
|
(line (pt 0 120)(pt 64 120)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
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|
||||||
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|
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|
||||||
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|
(input)
|
||||||
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|
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|
||||||
(text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8)))
|
(text "data9x[7..0]" (rect 4 123 61 135)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 136)(pt 72 136)(line_width 3))
|
(line (pt 0 136)(pt 64 136)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 152)
|
(pt 0 152)
|
||||||
(input)
|
(input)
|
||||||
(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data8x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8)))
|
(text "data8x[7..0]" (rect 4 139 61 151)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 152)(pt 72 152)(line_width 3))
|
(line (pt 0 152)(pt 64 152)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 168)
|
(pt 0 168)
|
||||||
(input)
|
(input)
|
||||||
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|
(text "data7x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8)))
|
(text "data7x[7..0]" (rect 4 155 61 167)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 168)(pt 72 168)(line_width 3))
|
(line (pt 0 168)(pt 64 168)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 184)
|
(pt 0 184)
|
||||||
(input)
|
(input)
|
||||||
(text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data6x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8)))
|
(text "data6x[7..0]" (rect 4 171 61 183)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 184)(pt 72 184)(line_width 3))
|
(line (pt 0 184)(pt 64 184)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 200)
|
(pt 0 200)
|
||||||
(input)
|
(input)
|
||||||
(text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data5x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8)))
|
(text "data5x[7..0]" (rect 4 187 61 199)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 200)(pt 72 200)(line_width 3))
|
(line (pt 0 200)(pt 64 200)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 216)
|
(pt 0 216)
|
||||||
(input)
|
(input)
|
||||||
(text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data4x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8)))
|
(text "data4x[7..0]" (rect 4 203 61 215)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 216)(pt 72 216)(line_width 3))
|
(line (pt 0 216)(pt 64 216)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 232)
|
(pt 0 232)
|
||||||
(input)
|
(input)
|
||||||
(text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data3x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8)))
|
(text "data3x[7..0]" (rect 4 219 61 231)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 232)(pt 72 232)(line_width 3))
|
(line (pt 0 232)(pt 64 232)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 248)
|
(pt 0 248)
|
||||||
(input)
|
(input)
|
||||||
(text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data2x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8)))
|
(text "data2x[7..0]" (rect 4 235 61 247)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 248)(pt 72 248)(line_width 3))
|
(line (pt 0 248)(pt 64 248)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 264)
|
(pt 0 264)
|
||||||
(input)
|
(input)
|
||||||
(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data1x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8)))
|
(text "data1x[7..0]" (rect 4 251 61 263)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 264)(pt 72 264)(line_width 3))
|
(line (pt 0 264)(pt 64 264)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 280)
|
(pt 0 280)
|
||||||
(input)
|
(input)
|
||||||
(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data0x[7..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8)))
|
(text "data0x[7..0]" (rect 4 267 61 279)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 280)(pt 72 280)(line_width 3))
|
(line (pt 0 280)(pt 64 280)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 296)
|
(pt 0 296)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8)))
|
(text "clock" (rect 4 283 29 295)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 296)(pt 72 296)(line_width 1))
|
(line (pt 0 296)(pt 64 296))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 80 320)
|
(pt 72 320)
|
||||||
(input)
|
(input)
|
||||||
(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
(text "sel[3..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
|
(text "sel[3..0]" (rect 66 265 78 303)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 80 320)(pt 80 308)(line_width 3))
|
(line (pt 72 320)(pt 72 308)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 144 168)
|
(pt 144 168)
|
||||||
(output)
|
(output)
|
||||||
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[7..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8)))
|
(text "result[7..0]" (rect 91 155 142 167)(font "Arial" (font_size 8)))
|
||||||
(line (pt 144 168)(pt 88 168)(line_width 3))
|
(line (pt 144 168)(pt 80 168)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 72 24)(pt 72 312)(line_width 1))
|
(line (pt 64 24)(pt 64 312))
|
||||||
(line (pt 88 32)(pt 88 304)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 72 24)(pt 88 32)(line_width 1))
|
(line (pt 64 312)(pt 80 304))
|
||||||
(line (pt 72 312)(pt 88 304)(line_width 1))
|
(line (pt 80 32)(pt 80 304))
|
||||||
(line (pt 72 290)(pt 78 296)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 78 296)(pt 72 302)(line_width 1))
|
(line (pt 146 0)(pt 146 322))
|
||||||
|
(line (pt 0 322)(pt 146 322))
|
||||||
|
(line (pt 0 0)(pt 0 322))
|
||||||
|
(line (pt 64 290)(pt 70 296))
|
||||||
|
(line (pt 70 296)(pt 64 302))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux2.vhd
|
-- File Name: lpm_mux2.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -235,7 +235,7 @@ BEGIN
|
|||||||
sub_wire2(0, 6) <= sub_wire17(6);
|
sub_wire2(0, 6) <= sub_wire17(6);
|
||||||
sub_wire2(0, 7) <= sub_wire17(7);
|
sub_wire2(0, 7) <= sub_wire17(7);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_pipeline => 2,
|
lpm_pipeline => 2,
|
||||||
lpm_size => 16,
|
lpm_size => 16,
|
||||||
@@ -244,9 +244,9 @@ BEGIN
|
|||||||
lpm_widths => 4
|
lpm_widths => 4
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -259,53 +259,54 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0]
|
-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0]
|
-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0]
|
-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0]
|
-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0]
|
-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0]
|
-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0]
|
-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0]
|
-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0]
|
-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0]
|
-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0]
|
-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0]
|
-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
|
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
|
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
|
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,43 +18,51 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 80 80)
|
(rect 0 0 80 80)
|
||||||
(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux3" (rect 11 0 85 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 64 25 76)(font "Arial" ))
|
(text "inst" (rect 8 65 26 76)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
(text "data1" (rect 0 0 33 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
|
(text "data1" (rect 4 27 32 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 32 40)(line_width 1))
|
(line (pt 0 40)(pt 32 40))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
(text "data0" (rect 0 0 33 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
|
(text "data0" (rect 4 43 32 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 32 56)(line_width 1))
|
(line (pt 0 56)(pt 32 56))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 40 80)
|
(pt 40 80)
|
||||||
(input)
|
(input)
|
||||||
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
|
(text "sel" (rect 34 49 46 63)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 40 80)(pt 40 68)(line_width 1))
|
(line (pt 40 80)(pt 40 68))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 80 48)
|
(pt 80 48)
|
||||||
(output)
|
(output)
|
||||||
(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
(text "result" (rect 0 0 33 13)(font "Arial" (font_size 8)))
|
||||||
(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
|
(text "result" (rect 51 35 78 47)(font "Arial" (font_size 8)))
|
||||||
(line (pt 80 48)(pt 48 48)(line_width 1))
|
(line (pt 80 48)(pt 48 48))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 32 24)(pt 32 72)(line_width 1))
|
(line (pt 32 24)(pt 32 72))
|
||||||
(line (pt 48 32)(pt 48 64)(line_width 1))
|
(line (pt 32 24)(pt 48 32))
|
||||||
(line (pt 32 24)(pt 48 32)(line_width 1))
|
(line (pt 32 72)(pt 48 64))
|
||||||
(line (pt 32 72)(pt 48 64)(line_width 1))
|
(line (pt 48 32)(pt 48 64))
|
||||||
|
(line (pt 0 0)(pt 82 0))
|
||||||
|
(line (pt 82 0)(pt 82 82))
|
||||||
|
(line (pt 0 82)(pt 82 82))
|
||||||
|
(line (pt 0 0)(pt 0 82))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux3.vhd
|
-- File Name: lpm_mux3.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -57,22 +57,22 @@ ARCHITECTURE SYN OF lpm_mux3 IS
|
|||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
|
||||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
|
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
sub_wire6 <= data0;
|
sub_wire4 <= data0;
|
||||||
sub_wire1 <= sub_wire0(0);
|
sub_wire1 <= sub_wire0(0);
|
||||||
result <= sub_wire1;
|
result <= sub_wire1;
|
||||||
sub_wire2 <= sel;
|
sub_wire2 <= data1;
|
||||||
sub_wire3(0) <= sub_wire2;
|
sub_wire3(1, 0) <= sub_wire2;
|
||||||
sub_wire4 <= data1;
|
sub_wire3(0, 0) <= sub_wire4;
|
||||||
sub_wire5(1, 0) <= sub_wire4;
|
sub_wire5 <= sel;
|
||||||
sub_wire5(0, 0) <= sub_wire6;
|
sub_wire6(0) <= sub_wire5;
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_size => 2,
|
lpm_size => 2,
|
||||||
lpm_type => "LPM_MUX",
|
lpm_type => "LPM_MUX",
|
||||||
@@ -80,8 +80,8 @@ BEGIN
|
|||||||
lpm_widths => 1
|
lpm_widths => 1
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sub_wire3,
|
data => sub_wire3,
|
||||||
data => sub_wire5,
|
sel => sub_wire6,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -94,22 +94,23 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||||
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
|
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
|
||||||
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
|
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
|
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
|
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||||
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
|
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,43 +18,51 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 136 80)
|
(rect 0 0 144 80)
|
||||||
(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux4" (rect 43 0 118 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 64 25 76)(font "Arial" ))
|
(text "inst" (rect 8 65 26 76)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data1x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
|
(text "data1x[6..0]" (rect 4 27 61 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 64 40)(line_width 3))
|
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "data0x[6..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
|
(text "data0x[6..0]" (rect 4 43 61 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 64 56)(line_width 3))
|
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 72 80)
|
(pt 72 80)
|
||||||
(input)
|
(input)
|
||||||
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8)))
|
(text "sel" (rect 66 49 78 63)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 72 80)(pt 72 68)(line_width 1))
|
(line (pt 72 80)(pt 72 68))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 136 48)
|
(pt 144 48)
|
||||||
(output)
|
(output)
|
||||||
(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "result[6..0]" (rect 0 0 60 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8)))
|
(text "result[6..0]" (rect 91 35 142 47)(font "Arial" (font_size 8)))
|
||||||
(line (pt 136 48)(pt 80 48)(line_width 3))
|
(line (pt 144 48)(pt 80 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 64 24)(pt 64 72)(line_width 1))
|
(line (pt 64 24)(pt 64 72))
|
||||||
(line (pt 80 32)(pt 80 64)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 64 24)(pt 80 32)(line_width 1))
|
(line (pt 64 72)(pt 80 64))
|
||||||
(line (pt 64 72)(pt 80 64)(line_width 1))
|
(line (pt 80 32)(pt 80 64))
|
||||||
|
(line (pt 0 0)(pt 146 0))
|
||||||
|
(line (pt 146 0)(pt 146 82))
|
||||||
|
(line (pt 0 82)(pt 146 82))
|
||||||
|
(line (pt 0 0)(pt 0 82))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux4.vhd
|
-- File Name: lpm_mux4.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -55,34 +55,34 @@ ARCHITECTURE SYN OF lpm_mux4 IS
|
|||||||
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
||||||
|
|
||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
||||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
||||||
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
|
||||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
||||||
SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (6 DOWNTO 0);
|
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
sub_wire5 <= data0x(6 DOWNTO 0);
|
sub_wire3 <= data0x(6 DOWNTO 0);
|
||||||
result <= sub_wire0(6 DOWNTO 0);
|
result <= sub_wire0(6 DOWNTO 0);
|
||||||
sub_wire1 <= sel;
|
sub_wire1 <= data1x(6 DOWNTO 0);
|
||||||
sub_wire2(0) <= sub_wire1;
|
sub_wire2(1, 0) <= sub_wire1(0);
|
||||||
sub_wire3 <= data1x(6 DOWNTO 0);
|
sub_wire2(1, 1) <= sub_wire1(1);
|
||||||
sub_wire4(1, 0) <= sub_wire3(0);
|
sub_wire2(1, 2) <= sub_wire1(2);
|
||||||
sub_wire4(1, 1) <= sub_wire3(1);
|
sub_wire2(1, 3) <= sub_wire1(3);
|
||||||
sub_wire4(1, 2) <= sub_wire3(2);
|
sub_wire2(1, 4) <= sub_wire1(4);
|
||||||
sub_wire4(1, 3) <= sub_wire3(3);
|
sub_wire2(1, 5) <= sub_wire1(5);
|
||||||
sub_wire4(1, 4) <= sub_wire3(4);
|
sub_wire2(1, 6) <= sub_wire1(6);
|
||||||
sub_wire4(1, 5) <= sub_wire3(5);
|
sub_wire2(0, 0) <= sub_wire3(0);
|
||||||
sub_wire4(1, 6) <= sub_wire3(6);
|
sub_wire2(0, 1) <= sub_wire3(1);
|
||||||
sub_wire4(0, 0) <= sub_wire5(0);
|
sub_wire2(0, 2) <= sub_wire3(2);
|
||||||
sub_wire4(0, 1) <= sub_wire5(1);
|
sub_wire2(0, 3) <= sub_wire3(3);
|
||||||
sub_wire4(0, 2) <= sub_wire5(2);
|
sub_wire2(0, 4) <= sub_wire3(4);
|
||||||
sub_wire4(0, 3) <= sub_wire5(3);
|
sub_wire2(0, 5) <= sub_wire3(5);
|
||||||
sub_wire4(0, 4) <= sub_wire5(4);
|
sub_wire2(0, 6) <= sub_wire3(6);
|
||||||
sub_wire4(0, 5) <= sub_wire5(5);
|
sub_wire4 <= sel;
|
||||||
sub_wire4(0, 6) <= sub_wire5(6);
|
sub_wire5(0) <= sub_wire4;
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_size => 2,
|
lpm_size => 2,
|
||||||
lpm_type => "LPM_MUX",
|
lpm_type => "LPM_MUX",
|
||||||
@@ -90,8 +90,8 @@ BEGIN
|
|||||||
lpm_widths => 1
|
lpm_widths => 1
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sub_wire2,
|
data => sub_wire2,
|
||||||
data => sub_wire4,
|
sel => sub_wire5,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -104,22 +104,23 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
|
-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
|
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||||
-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
|
-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,57 +18,65 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
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|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 152 112)
|
(rect 0 0 144 112)
|
||||||
(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux5" (rect 43 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 96 25 108)(font "Arial" ))
|
(text "inst" (rect 8 97 26 108)(font "Arial" ))
|
||||||
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|
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|
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|
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|
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|
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|
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|
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|
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(text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
|
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|
||||||
(line (pt 0 40)(pt 72 40)(line_width 3))
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
(port
|
||||||
(pt 0 72)
|
(pt 0 72)
|
||||||
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|
(input)
|
||||||
(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
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|
||||||
(text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
(port
|
(port
|
||||||
(pt 0 88)
|
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|
||||||
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|
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|
||||||
(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "data0x[63..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
|
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|
||||||
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|
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|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 80 112)
|
(pt 72 112)
|
||||||
(input)
|
(input)
|
||||||
(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8)))
|
(text "sel[1..0]" (rect 66 57 78 95)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 80 112)(pt 80 100)(line_width 3))
|
(line (pt 72 112)(pt 72 100)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 152 64)
|
(pt 144 64)
|
||||||
(output)
|
(output)
|
||||||
(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
(text "result[63..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8)))
|
(text "result[63..0]" (rect 85 51 142 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 152 64)(pt 88 64)(line_width 3))
|
(line (pt 144 64)(pt 80 64)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 72 24)(pt 72 104)(line_width 1))
|
(line (pt 64 24)(pt 64 104))
|
||||||
(line (pt 88 32)(pt 88 96)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 72 24)(pt 88 32)(line_width 1))
|
(line (pt 64 104)(pt 80 96))
|
||||||
(line (pt 72 104)(pt 88 96)(line_width 1))
|
(line (pt 80 32)(pt 80 96))
|
||||||
|
(line (pt 0 0)(pt 146 0))
|
||||||
|
(line (pt 146 0)(pt 146 114))
|
||||||
|
(line (pt 0 114)(pt 146 114))
|
||||||
|
(line (pt 0 0)(pt 0 114))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux5.vhd
|
-- File Name: lpm_mux5.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -326,7 +326,7 @@ BEGIN
|
|||||||
sub_wire2(0, 62) <= sub_wire5(62);
|
sub_wire2(0, 62) <= sub_wire5(62);
|
||||||
sub_wire2(0, 63) <= sub_wire5(63);
|
sub_wire2(0, 63) <= sub_wire5(63);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_size => 4,
|
lpm_size => 4,
|
||||||
lpm_type => "LPM_MUX",
|
lpm_type => "LPM_MUX",
|
||||||
@@ -334,8 +334,8 @@ BEGIN
|
|||||||
lpm_widths => 2
|
lpm_widths => 2
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -348,26 +348,27 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
|
-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
|
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
|
-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,94 +18,102 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
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(symbol
|
(symbol
|
||||||
(rect 0 0 152 192)
|
(rect 0 0 144 192)
|
||||||
(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
|
(text "lpm_mux6" (rect 43 0 117 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 176 25 188)(font "Arial" ))
|
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|
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|
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|
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|
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|
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|
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|
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||||||
(line (pt 88 32)(pt 88 176)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 72 24)(pt 88 32)(line_width 1))
|
(line (pt 64 184)(pt 80 176))
|
||||||
(line (pt 72 184)(pt 88 176)(line_width 1))
|
(line (pt 80 32)(pt 80 176))
|
||||||
(line (pt 72 162)(pt 78 168)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 78 168)(pt 72 174)(line_width 1))
|
(line (pt 146 0)(pt 146 194))
|
||||||
|
(line (pt 0 194)(pt 146 194))
|
||||||
|
(line (pt 0 0)(pt 0 194))
|
||||||
|
(line (pt 64 162)(pt 70 168))
|
||||||
|
(line (pt 70 168)(pt 64 174))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_mux6.vhd
|
-- File Name: lpm_mux6.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -275,7 +275,7 @@ BEGIN
|
|||||||
sub_wire2(0, 22) <= sub_wire9(22);
|
sub_wire2(0, 22) <= sub_wire9(22);
|
||||||
sub_wire2(0, 23) <= sub_wire9(23);
|
sub_wire2(0, 23) <= sub_wire9(23);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_pipeline => 2,
|
lpm_pipeline => 2,
|
||||||
lpm_size => 8,
|
lpm_size => 8,
|
||||||
@@ -284,9 +284,9 @@ BEGIN
|
|||||||
lpm_widths => 3
|
lpm_widths => 3
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -299,37 +299,38 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL "data0x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL "data1x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL "data2x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL "data3x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0]
|
-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL "data4x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0]
|
-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL "data5x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0]
|
-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL "data6x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0]
|
-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL "data7x[23..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0]
|
-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
|
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
|
-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2009 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,59 +18,67 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 168 112)
|
(rect 0 0 144 112)
|
||||||
(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
|
(text "lpm_muxDZ" (rect 37 0 123 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 96 25 108)(font "Arial" ))
|
(text "inst" (rect 8 97 26 108)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 40)
|
||||||
(input)
|
(input)
|
||||||
(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
|
(text "data1x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
|
||||||
(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
|
(text "data1x[127..0]" (rect 4 27 73 39)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 80 40)(line_width 3))
|
(line (pt 0 40)(pt 64 40)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 56)
|
||||||
(input)
|
(input)
|
||||||
(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
|
(text "data0x[127..0]" (rect 0 0 81 13)(font "Arial" (font_size 8)))
|
||||||
(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
|
(text "data0x[127..0]" (rect 4 43 73 55)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 80 56)(line_width 3))
|
(line (pt 0 56)(pt 64 56)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 72)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
|
(text "clock" (rect 4 59 29 71)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 80 72)(line_width 1))
|
(line (pt 0 72)(pt 64 72))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 88)
|
(pt 0 88)
|
||||||
(input)
|
(input)
|
||||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clken" (rect 0 0 30 13)(font "Arial" (font_size 8)))
|
||||||
(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
|
(text "clken" (rect 4 75 29 87)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 88)(pt 80 88)(line_width 1))
|
(line (pt 0 88)(pt 64 88))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 88 112)
|
(pt 72 112)
|
||||||
(input)
|
(input)
|
||||||
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
(text "sel" (rect 0 0 13 17)(font "Arial" (font_size 8))(vertical))
|
||||||
(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
|
(text "sel" (rect 66 81 78 95)(font "Arial" (font_size 8))(vertical))
|
||||||
(line (pt 88 112)(pt 88 100)(line_width 1))
|
(line (pt 72 112)(pt 72 100))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 168 64)
|
(pt 144 64)
|
||||||
(output)
|
(output)
|
||||||
(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
|
(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
||||||
(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
|
(text "result[127..0]" (rect 79 51 142 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 168 64)(pt 96 64)(line_width 3))
|
(line (pt 144 64)(pt 80 64)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 80 24)(pt 80 104)(line_width 1))
|
(line (pt 64 24)(pt 64 104))
|
||||||
(line (pt 96 32)(pt 96 96)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 80 24)(pt 96 32)(line_width 1))
|
(line (pt 64 104)(pt 80 96))
|
||||||
(line (pt 80 104)(pt 96 96)(line_width 1))
|
(line (pt 80 32)(pt 80 96))
|
||||||
(line (pt 80 66)(pt 86 72)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 86 72)(pt 80 78)(line_width 1))
|
(line (pt 146 0)(pt 146 114))
|
||||||
|
(line (pt 0 114)(pt 146 114))
|
||||||
|
(line (pt 0 0)(pt 0 114))
|
||||||
|
(line (pt 64 66)(pt 70 72))
|
||||||
|
(line (pt 70 72)(pt 64 78))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2009 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_muxDZ.vhd
|
-- File Name: lpm_muxDZ.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 9.1 Build 222 10/21/2009 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2009 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -57,276 +57,276 @@ ARCHITECTURE SYN OF lpm_muxdz IS
|
|||||||
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
||||||
|
|
||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
||||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
||||||
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
|
||||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
||||||
SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
|
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0);
|
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
sub_wire5 <= data0x(127 DOWNTO 0);
|
sub_wire3 <= data0x(127 DOWNTO 0);
|
||||||
result <= sub_wire0(127 DOWNTO 0);
|
result <= sub_wire0(127 DOWNTO 0);
|
||||||
sub_wire1 <= sel;
|
sub_wire1 <= data1x(127 DOWNTO 0);
|
||||||
sub_wire2(0) <= sub_wire1;
|
sub_wire2(1, 0) <= sub_wire1(0);
|
||||||
sub_wire3 <= data1x(127 DOWNTO 0);
|
sub_wire2(1, 1) <= sub_wire1(1);
|
||||||
sub_wire4(1, 0) <= sub_wire3(0);
|
sub_wire2(1, 2) <= sub_wire1(2);
|
||||||
sub_wire4(1, 1) <= sub_wire3(1);
|
sub_wire2(1, 3) <= sub_wire1(3);
|
||||||
sub_wire4(1, 2) <= sub_wire3(2);
|
sub_wire2(1, 4) <= sub_wire1(4);
|
||||||
sub_wire4(1, 3) <= sub_wire3(3);
|
sub_wire2(1, 5) <= sub_wire1(5);
|
||||||
sub_wire4(1, 4) <= sub_wire3(4);
|
sub_wire2(1, 6) <= sub_wire1(6);
|
||||||
sub_wire4(1, 5) <= sub_wire3(5);
|
sub_wire2(1, 7) <= sub_wire1(7);
|
||||||
sub_wire4(1, 6) <= sub_wire3(6);
|
sub_wire2(1, 8) <= sub_wire1(8);
|
||||||
sub_wire4(1, 7) <= sub_wire3(7);
|
sub_wire2(1, 9) <= sub_wire1(9);
|
||||||
sub_wire4(1, 8) <= sub_wire3(8);
|
sub_wire2(1, 10) <= sub_wire1(10);
|
||||||
sub_wire4(1, 9) <= sub_wire3(9);
|
sub_wire2(1, 11) <= sub_wire1(11);
|
||||||
sub_wire4(1, 10) <= sub_wire3(10);
|
sub_wire2(1, 12) <= sub_wire1(12);
|
||||||
sub_wire4(1, 11) <= sub_wire3(11);
|
sub_wire2(1, 13) <= sub_wire1(13);
|
||||||
sub_wire4(1, 12) <= sub_wire3(12);
|
sub_wire2(1, 14) <= sub_wire1(14);
|
||||||
sub_wire4(1, 13) <= sub_wire3(13);
|
sub_wire2(1, 15) <= sub_wire1(15);
|
||||||
sub_wire4(1, 14) <= sub_wire3(14);
|
sub_wire2(1, 16) <= sub_wire1(16);
|
||||||
sub_wire4(1, 15) <= sub_wire3(15);
|
sub_wire2(1, 17) <= sub_wire1(17);
|
||||||
sub_wire4(1, 16) <= sub_wire3(16);
|
sub_wire2(1, 18) <= sub_wire1(18);
|
||||||
sub_wire4(1, 17) <= sub_wire3(17);
|
sub_wire2(1, 19) <= sub_wire1(19);
|
||||||
sub_wire4(1, 18) <= sub_wire3(18);
|
sub_wire2(1, 20) <= sub_wire1(20);
|
||||||
sub_wire4(1, 19) <= sub_wire3(19);
|
sub_wire2(1, 21) <= sub_wire1(21);
|
||||||
sub_wire4(1, 20) <= sub_wire3(20);
|
sub_wire2(1, 22) <= sub_wire1(22);
|
||||||
sub_wire4(1, 21) <= sub_wire3(21);
|
sub_wire2(1, 23) <= sub_wire1(23);
|
||||||
sub_wire4(1, 22) <= sub_wire3(22);
|
sub_wire2(1, 24) <= sub_wire1(24);
|
||||||
sub_wire4(1, 23) <= sub_wire3(23);
|
sub_wire2(1, 25) <= sub_wire1(25);
|
||||||
sub_wire4(1, 24) <= sub_wire3(24);
|
sub_wire2(1, 26) <= sub_wire1(26);
|
||||||
sub_wire4(1, 25) <= sub_wire3(25);
|
sub_wire2(1, 27) <= sub_wire1(27);
|
||||||
sub_wire4(1, 26) <= sub_wire3(26);
|
sub_wire2(1, 28) <= sub_wire1(28);
|
||||||
sub_wire4(1, 27) <= sub_wire3(27);
|
sub_wire2(1, 29) <= sub_wire1(29);
|
||||||
sub_wire4(1, 28) <= sub_wire3(28);
|
sub_wire2(1, 30) <= sub_wire1(30);
|
||||||
sub_wire4(1, 29) <= sub_wire3(29);
|
sub_wire2(1, 31) <= sub_wire1(31);
|
||||||
sub_wire4(1, 30) <= sub_wire3(30);
|
sub_wire2(1, 32) <= sub_wire1(32);
|
||||||
sub_wire4(1, 31) <= sub_wire3(31);
|
sub_wire2(1, 33) <= sub_wire1(33);
|
||||||
sub_wire4(1, 32) <= sub_wire3(32);
|
sub_wire2(1, 34) <= sub_wire1(34);
|
||||||
sub_wire4(1, 33) <= sub_wire3(33);
|
sub_wire2(1, 35) <= sub_wire1(35);
|
||||||
sub_wire4(1, 34) <= sub_wire3(34);
|
sub_wire2(1, 36) <= sub_wire1(36);
|
||||||
sub_wire4(1, 35) <= sub_wire3(35);
|
sub_wire2(1, 37) <= sub_wire1(37);
|
||||||
sub_wire4(1, 36) <= sub_wire3(36);
|
sub_wire2(1, 38) <= sub_wire1(38);
|
||||||
sub_wire4(1, 37) <= sub_wire3(37);
|
sub_wire2(1, 39) <= sub_wire1(39);
|
||||||
sub_wire4(1, 38) <= sub_wire3(38);
|
sub_wire2(1, 40) <= sub_wire1(40);
|
||||||
sub_wire4(1, 39) <= sub_wire3(39);
|
sub_wire2(1, 41) <= sub_wire1(41);
|
||||||
sub_wire4(1, 40) <= sub_wire3(40);
|
sub_wire2(1, 42) <= sub_wire1(42);
|
||||||
sub_wire4(1, 41) <= sub_wire3(41);
|
sub_wire2(1, 43) <= sub_wire1(43);
|
||||||
sub_wire4(1, 42) <= sub_wire3(42);
|
sub_wire2(1, 44) <= sub_wire1(44);
|
||||||
sub_wire4(1, 43) <= sub_wire3(43);
|
sub_wire2(1, 45) <= sub_wire1(45);
|
||||||
sub_wire4(1, 44) <= sub_wire3(44);
|
sub_wire2(1, 46) <= sub_wire1(46);
|
||||||
sub_wire4(1, 45) <= sub_wire3(45);
|
sub_wire2(1, 47) <= sub_wire1(47);
|
||||||
sub_wire4(1, 46) <= sub_wire3(46);
|
sub_wire2(1, 48) <= sub_wire1(48);
|
||||||
sub_wire4(1, 47) <= sub_wire3(47);
|
sub_wire2(1, 49) <= sub_wire1(49);
|
||||||
sub_wire4(1, 48) <= sub_wire3(48);
|
sub_wire2(1, 50) <= sub_wire1(50);
|
||||||
sub_wire4(1, 49) <= sub_wire3(49);
|
sub_wire2(1, 51) <= sub_wire1(51);
|
||||||
sub_wire4(1, 50) <= sub_wire3(50);
|
sub_wire2(1, 52) <= sub_wire1(52);
|
||||||
sub_wire4(1, 51) <= sub_wire3(51);
|
sub_wire2(1, 53) <= sub_wire1(53);
|
||||||
sub_wire4(1, 52) <= sub_wire3(52);
|
sub_wire2(1, 54) <= sub_wire1(54);
|
||||||
sub_wire4(1, 53) <= sub_wire3(53);
|
sub_wire2(1, 55) <= sub_wire1(55);
|
||||||
sub_wire4(1, 54) <= sub_wire3(54);
|
sub_wire2(1, 56) <= sub_wire1(56);
|
||||||
sub_wire4(1, 55) <= sub_wire3(55);
|
sub_wire2(1, 57) <= sub_wire1(57);
|
||||||
sub_wire4(1, 56) <= sub_wire3(56);
|
sub_wire2(1, 58) <= sub_wire1(58);
|
||||||
sub_wire4(1, 57) <= sub_wire3(57);
|
sub_wire2(1, 59) <= sub_wire1(59);
|
||||||
sub_wire4(1, 58) <= sub_wire3(58);
|
sub_wire2(1, 60) <= sub_wire1(60);
|
||||||
sub_wire4(1, 59) <= sub_wire3(59);
|
sub_wire2(1, 61) <= sub_wire1(61);
|
||||||
sub_wire4(1, 60) <= sub_wire3(60);
|
sub_wire2(1, 62) <= sub_wire1(62);
|
||||||
sub_wire4(1, 61) <= sub_wire3(61);
|
sub_wire2(1, 63) <= sub_wire1(63);
|
||||||
sub_wire4(1, 62) <= sub_wire3(62);
|
sub_wire2(1, 64) <= sub_wire1(64);
|
||||||
sub_wire4(1, 63) <= sub_wire3(63);
|
sub_wire2(1, 65) <= sub_wire1(65);
|
||||||
sub_wire4(1, 64) <= sub_wire3(64);
|
sub_wire2(1, 66) <= sub_wire1(66);
|
||||||
sub_wire4(1, 65) <= sub_wire3(65);
|
sub_wire2(1, 67) <= sub_wire1(67);
|
||||||
sub_wire4(1, 66) <= sub_wire3(66);
|
sub_wire2(1, 68) <= sub_wire1(68);
|
||||||
sub_wire4(1, 67) <= sub_wire3(67);
|
sub_wire2(1, 69) <= sub_wire1(69);
|
||||||
sub_wire4(1, 68) <= sub_wire3(68);
|
sub_wire2(1, 70) <= sub_wire1(70);
|
||||||
sub_wire4(1, 69) <= sub_wire3(69);
|
sub_wire2(1, 71) <= sub_wire1(71);
|
||||||
sub_wire4(1, 70) <= sub_wire3(70);
|
sub_wire2(1, 72) <= sub_wire1(72);
|
||||||
sub_wire4(1, 71) <= sub_wire3(71);
|
sub_wire2(1, 73) <= sub_wire1(73);
|
||||||
sub_wire4(1, 72) <= sub_wire3(72);
|
sub_wire2(1, 74) <= sub_wire1(74);
|
||||||
sub_wire4(1, 73) <= sub_wire3(73);
|
sub_wire2(1, 75) <= sub_wire1(75);
|
||||||
sub_wire4(1, 74) <= sub_wire3(74);
|
sub_wire2(1, 76) <= sub_wire1(76);
|
||||||
sub_wire4(1, 75) <= sub_wire3(75);
|
sub_wire2(1, 77) <= sub_wire1(77);
|
||||||
sub_wire4(1, 76) <= sub_wire3(76);
|
sub_wire2(1, 78) <= sub_wire1(78);
|
||||||
sub_wire4(1, 77) <= sub_wire3(77);
|
sub_wire2(1, 79) <= sub_wire1(79);
|
||||||
sub_wire4(1, 78) <= sub_wire3(78);
|
sub_wire2(1, 80) <= sub_wire1(80);
|
||||||
sub_wire4(1, 79) <= sub_wire3(79);
|
sub_wire2(1, 81) <= sub_wire1(81);
|
||||||
sub_wire4(1, 80) <= sub_wire3(80);
|
sub_wire2(1, 82) <= sub_wire1(82);
|
||||||
sub_wire4(1, 81) <= sub_wire3(81);
|
sub_wire2(1, 83) <= sub_wire1(83);
|
||||||
sub_wire4(1, 82) <= sub_wire3(82);
|
sub_wire2(1, 84) <= sub_wire1(84);
|
||||||
sub_wire4(1, 83) <= sub_wire3(83);
|
sub_wire2(1, 85) <= sub_wire1(85);
|
||||||
sub_wire4(1, 84) <= sub_wire3(84);
|
sub_wire2(1, 86) <= sub_wire1(86);
|
||||||
sub_wire4(1, 85) <= sub_wire3(85);
|
sub_wire2(1, 87) <= sub_wire1(87);
|
||||||
sub_wire4(1, 86) <= sub_wire3(86);
|
sub_wire2(1, 88) <= sub_wire1(88);
|
||||||
sub_wire4(1, 87) <= sub_wire3(87);
|
sub_wire2(1, 89) <= sub_wire1(89);
|
||||||
sub_wire4(1, 88) <= sub_wire3(88);
|
sub_wire2(1, 90) <= sub_wire1(90);
|
||||||
sub_wire4(1, 89) <= sub_wire3(89);
|
sub_wire2(1, 91) <= sub_wire1(91);
|
||||||
sub_wire4(1, 90) <= sub_wire3(90);
|
sub_wire2(1, 92) <= sub_wire1(92);
|
||||||
sub_wire4(1, 91) <= sub_wire3(91);
|
sub_wire2(1, 93) <= sub_wire1(93);
|
||||||
sub_wire4(1, 92) <= sub_wire3(92);
|
sub_wire2(1, 94) <= sub_wire1(94);
|
||||||
sub_wire4(1, 93) <= sub_wire3(93);
|
sub_wire2(1, 95) <= sub_wire1(95);
|
||||||
sub_wire4(1, 94) <= sub_wire3(94);
|
sub_wire2(1, 96) <= sub_wire1(96);
|
||||||
sub_wire4(1, 95) <= sub_wire3(95);
|
sub_wire2(1, 97) <= sub_wire1(97);
|
||||||
sub_wire4(1, 96) <= sub_wire3(96);
|
sub_wire2(1, 98) <= sub_wire1(98);
|
||||||
sub_wire4(1, 97) <= sub_wire3(97);
|
sub_wire2(1, 99) <= sub_wire1(99);
|
||||||
sub_wire4(1, 98) <= sub_wire3(98);
|
sub_wire2(1, 100) <= sub_wire1(100);
|
||||||
sub_wire4(1, 99) <= sub_wire3(99);
|
sub_wire2(1, 101) <= sub_wire1(101);
|
||||||
sub_wire4(1, 100) <= sub_wire3(100);
|
sub_wire2(1, 102) <= sub_wire1(102);
|
||||||
sub_wire4(1, 101) <= sub_wire3(101);
|
sub_wire2(1, 103) <= sub_wire1(103);
|
||||||
sub_wire4(1, 102) <= sub_wire3(102);
|
sub_wire2(1, 104) <= sub_wire1(104);
|
||||||
sub_wire4(1, 103) <= sub_wire3(103);
|
sub_wire2(1, 105) <= sub_wire1(105);
|
||||||
sub_wire4(1, 104) <= sub_wire3(104);
|
sub_wire2(1, 106) <= sub_wire1(106);
|
||||||
sub_wire4(1, 105) <= sub_wire3(105);
|
sub_wire2(1, 107) <= sub_wire1(107);
|
||||||
sub_wire4(1, 106) <= sub_wire3(106);
|
sub_wire2(1, 108) <= sub_wire1(108);
|
||||||
sub_wire4(1, 107) <= sub_wire3(107);
|
sub_wire2(1, 109) <= sub_wire1(109);
|
||||||
sub_wire4(1, 108) <= sub_wire3(108);
|
sub_wire2(1, 110) <= sub_wire1(110);
|
||||||
sub_wire4(1, 109) <= sub_wire3(109);
|
sub_wire2(1, 111) <= sub_wire1(111);
|
||||||
sub_wire4(1, 110) <= sub_wire3(110);
|
sub_wire2(1, 112) <= sub_wire1(112);
|
||||||
sub_wire4(1, 111) <= sub_wire3(111);
|
sub_wire2(1, 113) <= sub_wire1(113);
|
||||||
sub_wire4(1, 112) <= sub_wire3(112);
|
sub_wire2(1, 114) <= sub_wire1(114);
|
||||||
sub_wire4(1, 113) <= sub_wire3(113);
|
sub_wire2(1, 115) <= sub_wire1(115);
|
||||||
sub_wire4(1, 114) <= sub_wire3(114);
|
sub_wire2(1, 116) <= sub_wire1(116);
|
||||||
sub_wire4(1, 115) <= sub_wire3(115);
|
sub_wire2(1, 117) <= sub_wire1(117);
|
||||||
sub_wire4(1, 116) <= sub_wire3(116);
|
sub_wire2(1, 118) <= sub_wire1(118);
|
||||||
sub_wire4(1, 117) <= sub_wire3(117);
|
sub_wire2(1, 119) <= sub_wire1(119);
|
||||||
sub_wire4(1, 118) <= sub_wire3(118);
|
sub_wire2(1, 120) <= sub_wire1(120);
|
||||||
sub_wire4(1, 119) <= sub_wire3(119);
|
sub_wire2(1, 121) <= sub_wire1(121);
|
||||||
sub_wire4(1, 120) <= sub_wire3(120);
|
sub_wire2(1, 122) <= sub_wire1(122);
|
||||||
sub_wire4(1, 121) <= sub_wire3(121);
|
sub_wire2(1, 123) <= sub_wire1(123);
|
||||||
sub_wire4(1, 122) <= sub_wire3(122);
|
sub_wire2(1, 124) <= sub_wire1(124);
|
||||||
sub_wire4(1, 123) <= sub_wire3(123);
|
sub_wire2(1, 125) <= sub_wire1(125);
|
||||||
sub_wire4(1, 124) <= sub_wire3(124);
|
sub_wire2(1, 126) <= sub_wire1(126);
|
||||||
sub_wire4(1, 125) <= sub_wire3(125);
|
sub_wire2(1, 127) <= sub_wire1(127);
|
||||||
sub_wire4(1, 126) <= sub_wire3(126);
|
sub_wire2(0, 0) <= sub_wire3(0);
|
||||||
sub_wire4(1, 127) <= sub_wire3(127);
|
sub_wire2(0, 1) <= sub_wire3(1);
|
||||||
sub_wire4(0, 0) <= sub_wire5(0);
|
sub_wire2(0, 2) <= sub_wire3(2);
|
||||||
sub_wire4(0, 1) <= sub_wire5(1);
|
sub_wire2(0, 3) <= sub_wire3(3);
|
||||||
sub_wire4(0, 2) <= sub_wire5(2);
|
sub_wire2(0, 4) <= sub_wire3(4);
|
||||||
sub_wire4(0, 3) <= sub_wire5(3);
|
sub_wire2(0, 5) <= sub_wire3(5);
|
||||||
sub_wire4(0, 4) <= sub_wire5(4);
|
sub_wire2(0, 6) <= sub_wire3(6);
|
||||||
sub_wire4(0, 5) <= sub_wire5(5);
|
sub_wire2(0, 7) <= sub_wire3(7);
|
||||||
sub_wire4(0, 6) <= sub_wire5(6);
|
sub_wire2(0, 8) <= sub_wire3(8);
|
||||||
sub_wire4(0, 7) <= sub_wire5(7);
|
sub_wire2(0, 9) <= sub_wire3(9);
|
||||||
sub_wire4(0, 8) <= sub_wire5(8);
|
sub_wire2(0, 10) <= sub_wire3(10);
|
||||||
sub_wire4(0, 9) <= sub_wire5(9);
|
sub_wire2(0, 11) <= sub_wire3(11);
|
||||||
sub_wire4(0, 10) <= sub_wire5(10);
|
sub_wire2(0, 12) <= sub_wire3(12);
|
||||||
sub_wire4(0, 11) <= sub_wire5(11);
|
sub_wire2(0, 13) <= sub_wire3(13);
|
||||||
sub_wire4(0, 12) <= sub_wire5(12);
|
sub_wire2(0, 14) <= sub_wire3(14);
|
||||||
sub_wire4(0, 13) <= sub_wire5(13);
|
sub_wire2(0, 15) <= sub_wire3(15);
|
||||||
sub_wire4(0, 14) <= sub_wire5(14);
|
sub_wire2(0, 16) <= sub_wire3(16);
|
||||||
sub_wire4(0, 15) <= sub_wire5(15);
|
sub_wire2(0, 17) <= sub_wire3(17);
|
||||||
sub_wire4(0, 16) <= sub_wire5(16);
|
sub_wire2(0, 18) <= sub_wire3(18);
|
||||||
sub_wire4(0, 17) <= sub_wire5(17);
|
sub_wire2(0, 19) <= sub_wire3(19);
|
||||||
sub_wire4(0, 18) <= sub_wire5(18);
|
sub_wire2(0, 20) <= sub_wire3(20);
|
||||||
sub_wire4(0, 19) <= sub_wire5(19);
|
sub_wire2(0, 21) <= sub_wire3(21);
|
||||||
sub_wire4(0, 20) <= sub_wire5(20);
|
sub_wire2(0, 22) <= sub_wire3(22);
|
||||||
sub_wire4(0, 21) <= sub_wire5(21);
|
sub_wire2(0, 23) <= sub_wire3(23);
|
||||||
sub_wire4(0, 22) <= sub_wire5(22);
|
sub_wire2(0, 24) <= sub_wire3(24);
|
||||||
sub_wire4(0, 23) <= sub_wire5(23);
|
sub_wire2(0, 25) <= sub_wire3(25);
|
||||||
sub_wire4(0, 24) <= sub_wire5(24);
|
sub_wire2(0, 26) <= sub_wire3(26);
|
||||||
sub_wire4(0, 25) <= sub_wire5(25);
|
sub_wire2(0, 27) <= sub_wire3(27);
|
||||||
sub_wire4(0, 26) <= sub_wire5(26);
|
sub_wire2(0, 28) <= sub_wire3(28);
|
||||||
sub_wire4(0, 27) <= sub_wire5(27);
|
sub_wire2(0, 29) <= sub_wire3(29);
|
||||||
sub_wire4(0, 28) <= sub_wire5(28);
|
sub_wire2(0, 30) <= sub_wire3(30);
|
||||||
sub_wire4(0, 29) <= sub_wire5(29);
|
sub_wire2(0, 31) <= sub_wire3(31);
|
||||||
sub_wire4(0, 30) <= sub_wire5(30);
|
sub_wire2(0, 32) <= sub_wire3(32);
|
||||||
sub_wire4(0, 31) <= sub_wire5(31);
|
sub_wire2(0, 33) <= sub_wire3(33);
|
||||||
sub_wire4(0, 32) <= sub_wire5(32);
|
sub_wire2(0, 34) <= sub_wire3(34);
|
||||||
sub_wire4(0, 33) <= sub_wire5(33);
|
sub_wire2(0, 35) <= sub_wire3(35);
|
||||||
sub_wire4(0, 34) <= sub_wire5(34);
|
sub_wire2(0, 36) <= sub_wire3(36);
|
||||||
sub_wire4(0, 35) <= sub_wire5(35);
|
sub_wire2(0, 37) <= sub_wire3(37);
|
||||||
sub_wire4(0, 36) <= sub_wire5(36);
|
sub_wire2(0, 38) <= sub_wire3(38);
|
||||||
sub_wire4(0, 37) <= sub_wire5(37);
|
sub_wire2(0, 39) <= sub_wire3(39);
|
||||||
sub_wire4(0, 38) <= sub_wire5(38);
|
sub_wire2(0, 40) <= sub_wire3(40);
|
||||||
sub_wire4(0, 39) <= sub_wire5(39);
|
sub_wire2(0, 41) <= sub_wire3(41);
|
||||||
sub_wire4(0, 40) <= sub_wire5(40);
|
sub_wire2(0, 42) <= sub_wire3(42);
|
||||||
sub_wire4(0, 41) <= sub_wire5(41);
|
sub_wire2(0, 43) <= sub_wire3(43);
|
||||||
sub_wire4(0, 42) <= sub_wire5(42);
|
sub_wire2(0, 44) <= sub_wire3(44);
|
||||||
sub_wire4(0, 43) <= sub_wire5(43);
|
sub_wire2(0, 45) <= sub_wire3(45);
|
||||||
sub_wire4(0, 44) <= sub_wire5(44);
|
sub_wire2(0, 46) <= sub_wire3(46);
|
||||||
sub_wire4(0, 45) <= sub_wire5(45);
|
sub_wire2(0, 47) <= sub_wire3(47);
|
||||||
sub_wire4(0, 46) <= sub_wire5(46);
|
sub_wire2(0, 48) <= sub_wire3(48);
|
||||||
sub_wire4(0, 47) <= sub_wire5(47);
|
sub_wire2(0, 49) <= sub_wire3(49);
|
||||||
sub_wire4(0, 48) <= sub_wire5(48);
|
sub_wire2(0, 50) <= sub_wire3(50);
|
||||||
sub_wire4(0, 49) <= sub_wire5(49);
|
sub_wire2(0, 51) <= sub_wire3(51);
|
||||||
sub_wire4(0, 50) <= sub_wire5(50);
|
sub_wire2(0, 52) <= sub_wire3(52);
|
||||||
sub_wire4(0, 51) <= sub_wire5(51);
|
sub_wire2(0, 53) <= sub_wire3(53);
|
||||||
sub_wire4(0, 52) <= sub_wire5(52);
|
sub_wire2(0, 54) <= sub_wire3(54);
|
||||||
sub_wire4(0, 53) <= sub_wire5(53);
|
sub_wire2(0, 55) <= sub_wire3(55);
|
||||||
sub_wire4(0, 54) <= sub_wire5(54);
|
sub_wire2(0, 56) <= sub_wire3(56);
|
||||||
sub_wire4(0, 55) <= sub_wire5(55);
|
sub_wire2(0, 57) <= sub_wire3(57);
|
||||||
sub_wire4(0, 56) <= sub_wire5(56);
|
sub_wire2(0, 58) <= sub_wire3(58);
|
||||||
sub_wire4(0, 57) <= sub_wire5(57);
|
sub_wire2(0, 59) <= sub_wire3(59);
|
||||||
sub_wire4(0, 58) <= sub_wire5(58);
|
sub_wire2(0, 60) <= sub_wire3(60);
|
||||||
sub_wire4(0, 59) <= sub_wire5(59);
|
sub_wire2(0, 61) <= sub_wire3(61);
|
||||||
sub_wire4(0, 60) <= sub_wire5(60);
|
sub_wire2(0, 62) <= sub_wire3(62);
|
||||||
sub_wire4(0, 61) <= sub_wire5(61);
|
sub_wire2(0, 63) <= sub_wire3(63);
|
||||||
sub_wire4(0, 62) <= sub_wire5(62);
|
sub_wire2(0, 64) <= sub_wire3(64);
|
||||||
sub_wire4(0, 63) <= sub_wire5(63);
|
sub_wire2(0, 65) <= sub_wire3(65);
|
||||||
sub_wire4(0, 64) <= sub_wire5(64);
|
sub_wire2(0, 66) <= sub_wire3(66);
|
||||||
sub_wire4(0, 65) <= sub_wire5(65);
|
sub_wire2(0, 67) <= sub_wire3(67);
|
||||||
sub_wire4(0, 66) <= sub_wire5(66);
|
sub_wire2(0, 68) <= sub_wire3(68);
|
||||||
sub_wire4(0, 67) <= sub_wire5(67);
|
sub_wire2(0, 69) <= sub_wire3(69);
|
||||||
sub_wire4(0, 68) <= sub_wire5(68);
|
sub_wire2(0, 70) <= sub_wire3(70);
|
||||||
sub_wire4(0, 69) <= sub_wire5(69);
|
sub_wire2(0, 71) <= sub_wire3(71);
|
||||||
sub_wire4(0, 70) <= sub_wire5(70);
|
sub_wire2(0, 72) <= sub_wire3(72);
|
||||||
sub_wire4(0, 71) <= sub_wire5(71);
|
sub_wire2(0, 73) <= sub_wire3(73);
|
||||||
sub_wire4(0, 72) <= sub_wire5(72);
|
sub_wire2(0, 74) <= sub_wire3(74);
|
||||||
sub_wire4(0, 73) <= sub_wire5(73);
|
sub_wire2(0, 75) <= sub_wire3(75);
|
||||||
sub_wire4(0, 74) <= sub_wire5(74);
|
sub_wire2(0, 76) <= sub_wire3(76);
|
||||||
sub_wire4(0, 75) <= sub_wire5(75);
|
sub_wire2(0, 77) <= sub_wire3(77);
|
||||||
sub_wire4(0, 76) <= sub_wire5(76);
|
sub_wire2(0, 78) <= sub_wire3(78);
|
||||||
sub_wire4(0, 77) <= sub_wire5(77);
|
sub_wire2(0, 79) <= sub_wire3(79);
|
||||||
sub_wire4(0, 78) <= sub_wire5(78);
|
sub_wire2(0, 80) <= sub_wire3(80);
|
||||||
sub_wire4(0, 79) <= sub_wire5(79);
|
sub_wire2(0, 81) <= sub_wire3(81);
|
||||||
sub_wire4(0, 80) <= sub_wire5(80);
|
sub_wire2(0, 82) <= sub_wire3(82);
|
||||||
sub_wire4(0, 81) <= sub_wire5(81);
|
sub_wire2(0, 83) <= sub_wire3(83);
|
||||||
sub_wire4(0, 82) <= sub_wire5(82);
|
sub_wire2(0, 84) <= sub_wire3(84);
|
||||||
sub_wire4(0, 83) <= sub_wire5(83);
|
sub_wire2(0, 85) <= sub_wire3(85);
|
||||||
sub_wire4(0, 84) <= sub_wire5(84);
|
sub_wire2(0, 86) <= sub_wire3(86);
|
||||||
sub_wire4(0, 85) <= sub_wire5(85);
|
sub_wire2(0, 87) <= sub_wire3(87);
|
||||||
sub_wire4(0, 86) <= sub_wire5(86);
|
sub_wire2(0, 88) <= sub_wire3(88);
|
||||||
sub_wire4(0, 87) <= sub_wire5(87);
|
sub_wire2(0, 89) <= sub_wire3(89);
|
||||||
sub_wire4(0, 88) <= sub_wire5(88);
|
sub_wire2(0, 90) <= sub_wire3(90);
|
||||||
sub_wire4(0, 89) <= sub_wire5(89);
|
sub_wire2(0, 91) <= sub_wire3(91);
|
||||||
sub_wire4(0, 90) <= sub_wire5(90);
|
sub_wire2(0, 92) <= sub_wire3(92);
|
||||||
sub_wire4(0, 91) <= sub_wire5(91);
|
sub_wire2(0, 93) <= sub_wire3(93);
|
||||||
sub_wire4(0, 92) <= sub_wire5(92);
|
sub_wire2(0, 94) <= sub_wire3(94);
|
||||||
sub_wire4(0, 93) <= sub_wire5(93);
|
sub_wire2(0, 95) <= sub_wire3(95);
|
||||||
sub_wire4(0, 94) <= sub_wire5(94);
|
sub_wire2(0, 96) <= sub_wire3(96);
|
||||||
sub_wire4(0, 95) <= sub_wire5(95);
|
sub_wire2(0, 97) <= sub_wire3(97);
|
||||||
sub_wire4(0, 96) <= sub_wire5(96);
|
sub_wire2(0, 98) <= sub_wire3(98);
|
||||||
sub_wire4(0, 97) <= sub_wire5(97);
|
sub_wire2(0, 99) <= sub_wire3(99);
|
||||||
sub_wire4(0, 98) <= sub_wire5(98);
|
sub_wire2(0, 100) <= sub_wire3(100);
|
||||||
sub_wire4(0, 99) <= sub_wire5(99);
|
sub_wire2(0, 101) <= sub_wire3(101);
|
||||||
sub_wire4(0, 100) <= sub_wire5(100);
|
sub_wire2(0, 102) <= sub_wire3(102);
|
||||||
sub_wire4(0, 101) <= sub_wire5(101);
|
sub_wire2(0, 103) <= sub_wire3(103);
|
||||||
sub_wire4(0, 102) <= sub_wire5(102);
|
sub_wire2(0, 104) <= sub_wire3(104);
|
||||||
sub_wire4(0, 103) <= sub_wire5(103);
|
sub_wire2(0, 105) <= sub_wire3(105);
|
||||||
sub_wire4(0, 104) <= sub_wire5(104);
|
sub_wire2(0, 106) <= sub_wire3(106);
|
||||||
sub_wire4(0, 105) <= sub_wire5(105);
|
sub_wire2(0, 107) <= sub_wire3(107);
|
||||||
sub_wire4(0, 106) <= sub_wire5(106);
|
sub_wire2(0, 108) <= sub_wire3(108);
|
||||||
sub_wire4(0, 107) <= sub_wire5(107);
|
sub_wire2(0, 109) <= sub_wire3(109);
|
||||||
sub_wire4(0, 108) <= sub_wire5(108);
|
sub_wire2(0, 110) <= sub_wire3(110);
|
||||||
sub_wire4(0, 109) <= sub_wire5(109);
|
sub_wire2(0, 111) <= sub_wire3(111);
|
||||||
sub_wire4(0, 110) <= sub_wire5(110);
|
sub_wire2(0, 112) <= sub_wire3(112);
|
||||||
sub_wire4(0, 111) <= sub_wire5(111);
|
sub_wire2(0, 113) <= sub_wire3(113);
|
||||||
sub_wire4(0, 112) <= sub_wire5(112);
|
sub_wire2(0, 114) <= sub_wire3(114);
|
||||||
sub_wire4(0, 113) <= sub_wire5(113);
|
sub_wire2(0, 115) <= sub_wire3(115);
|
||||||
sub_wire4(0, 114) <= sub_wire5(114);
|
sub_wire2(0, 116) <= sub_wire3(116);
|
||||||
sub_wire4(0, 115) <= sub_wire5(115);
|
sub_wire2(0, 117) <= sub_wire3(117);
|
||||||
sub_wire4(0, 116) <= sub_wire5(116);
|
sub_wire2(0, 118) <= sub_wire3(118);
|
||||||
sub_wire4(0, 117) <= sub_wire5(117);
|
sub_wire2(0, 119) <= sub_wire3(119);
|
||||||
sub_wire4(0, 118) <= sub_wire5(118);
|
sub_wire2(0, 120) <= sub_wire3(120);
|
||||||
sub_wire4(0, 119) <= sub_wire5(119);
|
sub_wire2(0, 121) <= sub_wire3(121);
|
||||||
sub_wire4(0, 120) <= sub_wire5(120);
|
sub_wire2(0, 122) <= sub_wire3(122);
|
||||||
sub_wire4(0, 121) <= sub_wire5(121);
|
sub_wire2(0, 123) <= sub_wire3(123);
|
||||||
sub_wire4(0, 122) <= sub_wire5(122);
|
sub_wire2(0, 124) <= sub_wire3(124);
|
||||||
sub_wire4(0, 123) <= sub_wire5(123);
|
sub_wire2(0, 125) <= sub_wire3(125);
|
||||||
sub_wire4(0, 124) <= sub_wire5(124);
|
sub_wire2(0, 126) <= sub_wire3(126);
|
||||||
sub_wire4(0, 125) <= sub_wire5(125);
|
sub_wire2(0, 127) <= sub_wire3(127);
|
||||||
sub_wire4(0, 126) <= sub_wire5(126);
|
sub_wire4 <= sel;
|
||||||
sub_wire4(0, 127) <= sub_wire5(127);
|
sub_wire5(0) <= sub_wire4;
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_pipeline => 1,
|
lpm_pipeline => 1,
|
||||||
lpm_size => 2,
|
lpm_size => 2,
|
||||||
@@ -335,10 +335,10 @@ BEGIN
|
|||||||
lpm_widths => 1
|
lpm_widths => 1
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sub_wire2,
|
|
||||||
clken => clken,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => sub_wire4,
|
data => sub_wire2,
|
||||||
|
sel => sub_wire5,
|
||||||
|
clken => clken,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -351,27 +351,28 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||||
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
|
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
|
-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
|
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
|
-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2009 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,141 +18,149 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
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|
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(text "result[127..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
|
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(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
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(line (pt 168 160)(pt 96 160)(line_width 3))
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|
)
|
||||||
(drawing
|
(drawing
|
||||||
(line (pt 80 24)(pt 80 296)(line_width 1))
|
(line (pt 64 24)(pt 64 296))
|
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(line (pt 96 32)(pt 96 288)(line_width 1))
|
(line (pt 64 24)(pt 80 32))
|
||||||
(line (pt 80 24)(pt 96 32)(line_width 1))
|
(line (pt 64 296)(pt 80 288))
|
||||||
(line (pt 80 296)(pt 96 288)(line_width 1))
|
(line (pt 80 32)(pt 80 288))
|
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|
(line (pt 0 0)(pt 146 0))
|
||||||
|
(line (pt 146 0)(pt 146 306))
|
||||||
|
(line (pt 0 306)(pt 146 306))
|
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(line (pt 0 0)(pt 0 306))
|
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|
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|
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|
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)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2009 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_MUX%
|
-- megafunction wizard: %LPM_MUX%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_mux
|
-- MODULE: LPM_MUX
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_muxVDM.vhd
|
-- File Name: lpm_muxVDM.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_mux
|
-- LPM_MUX
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 9.1 Build 222 10/21/2009 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2009 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -2154,7 +2154,7 @@ BEGIN
|
|||||||
sub_wire2(0, 126) <= sub_wire17(126);
|
sub_wire2(0, 126) <= sub_wire17(126);
|
||||||
sub_wire2(0, 127) <= sub_wire17(127);
|
sub_wire2(0, 127) <= sub_wire17(127);
|
||||||
|
|
||||||
lpm_mux_component : lpm_mux
|
LPM_MUX_component : LPM_MUX
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_size => 16,
|
lpm_size => 16,
|
||||||
lpm_type => "LPM_MUX",
|
lpm_type => "LPM_MUX",
|
||||||
@@ -2162,8 +2162,8 @@ BEGIN
|
|||||||
lpm_widths => 4
|
lpm_widths => 4
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
sel => sel,
|
|
||||||
data => sub_wire2,
|
data => sub_wire2,
|
||||||
|
sel => sel,
|
||||||
result => sub_wire0
|
result => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -2176,50 +2176,51 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
||||||
-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
|
-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
|
-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL "data10x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
|
-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL "data11x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
|
-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL "data12x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
|
-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL "data13x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
|
-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL "data14x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
|
-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL "data15x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
|
-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
|
-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL "data2x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
|
-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL "data3x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
|
-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL "data4x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
|
-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL "data5x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
|
-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL "data6x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
|
-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL "data7x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
|
-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL "data8x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
|
-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL "data9x[127..0]"
|
||||||
-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
|
-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
|
||||||
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
|
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
|
||||||
-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
|
|
||||||
-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
|
-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
|
||||||
|
-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
|
||||||
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,53 +18,61 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 144 128)
|
(rect 0 0 144 128)
|
||||||
(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
|
(text "lpm_shiftreg0" (rect 33 0 128 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
(text "inst" (rect 8 113 26 124)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 32)
|
(pt 0 32)
|
||||||
(input)
|
(input)
|
||||||
(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
|
(text "load" (rect 0 0 25 13)(font "Arial" (font_size 8)))
|
||||||
(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
|
(text "load" (rect 20 26 41 38)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
(line (pt 0 32)(pt 16 32))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 48)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
(text "data[15..0]" (rect 0 0 61 13)(font "Arial" (font_size 8)))
|
||||||
(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
|
(text "data[15..0]" (rect 20 42 72 54)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 80)
|
(pt 0 80)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
|
(text "clock" (rect 26 74 51 86)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
(line (pt 0 80)(pt 16 80))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 96)
|
(pt 0 96)
|
||||||
(input)
|
(input)
|
||||||
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||||
(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 20 90 48 102)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
(line (pt 0 96)(pt 16 96))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 144 72)
|
(pt 144 64)
|
||||||
(output)
|
(output)
|
||||||
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
|
||||||
(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
|
(text "shiftout" (rect 91 58 126 70)(font "Arial" (font_size 8)))
|
||||||
(line (pt 144 72)(pt 128 72)(line_width 1))
|
(line (pt 144 64)(pt 128 64))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "left shift" (rect 92 17 128 29)(font "Arial" ))
|
(text "left shift" (rect 96 18 227 46)(font "Arial" ))
|
||||||
(line (pt 16 16)(pt 128 16)(line_width 1))
|
(line (pt 16 16)(pt 16 112))
|
||||||
(line (pt 128 16)(pt 128 112)(line_width 1))
|
(line (pt 16 16)(pt 128 16))
|
||||||
(line (pt 128 112)(pt 16 112)(line_width 1))
|
(line (pt 16 112)(pt 128 112))
|
||||||
(line (pt 16 112)(pt 16 16)(line_width 1))
|
(line (pt 128 16)(pt 128 112))
|
||||||
(line (pt 16 74)(pt 22 80)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 22 80)(pt 16 86)(line_width 1))
|
(line (pt 146 0)(pt 146 130))
|
||||||
|
(line (pt 0 130)(pt 146 130))
|
||||||
|
(line (pt 0 0)(pt 0 130))
|
||||||
|
(line (pt 16 74)(pt 22 80))
|
||||||
|
(line (pt 22 80)(pt 16 86))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_SHIFTREG%
|
-- megafunction wizard: %LPM_SHIFTREG%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_shiftreg
|
-- MODULE: LPM_SHIFTREG
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_shiftreg0.vhd
|
-- File Name: lpm_shiftreg0.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_shiftreg
|
-- LPM_SHIFTREG
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -64,9 +64,9 @@ ARCHITECTURE SYN OF lpm_shiftreg0 IS
|
|||||||
lpm_width : NATURAL
|
lpm_width : NATURAL
|
||||||
);
|
);
|
||||||
PORT (
|
PORT (
|
||||||
load : IN STD_LOGIC ;
|
|
||||||
clock : IN STD_LOGIC ;
|
clock : IN STD_LOGIC ;
|
||||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||||
|
load : IN STD_LOGIC ;
|
||||||
shiftout : OUT STD_LOGIC ;
|
shiftout : OUT STD_LOGIC ;
|
||||||
shiftin : IN STD_LOGIC
|
shiftin : IN STD_LOGIC
|
||||||
);
|
);
|
||||||
@@ -75,16 +75,16 @@ ARCHITECTURE SYN OF lpm_shiftreg0 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
shiftout <= sub_wire0;
|
shiftout <= sub_wire0;
|
||||||
|
|
||||||
lpm_shiftreg_component : lpm_shiftreg
|
LPM_SHIFTREG_component : LPM_SHIFTREG
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_direction => "LEFT",
|
lpm_direction => "LEFT",
|
||||||
lpm_type => "LPM_SHIFTREG",
|
lpm_type => "LPM_SHIFTREG",
|
||||||
lpm_width => 16
|
lpm_width => 16
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
load => load,
|
|
||||||
clock => clock,
|
clock => clock,
|
||||||
data => data,
|
data => data,
|
||||||
|
load => load,
|
||||||
shiftin => shiftin,
|
shiftin => shiftin,
|
||||||
shiftout => sub_wire0
|
shiftout => sub_wire0
|
||||||
);
|
);
|
||||||
@@ -113,23 +113,24 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||||
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
|
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
||||||
-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
|
-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL "load"
|
||||||
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
|
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||||
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
|
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
|
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||||
|
-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
|
|
||||||
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,39 +18,47 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 144 80)
|
(rect 0 0 144 80)
|
||||||
(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
|
(text "lpm_shiftreg4" (rect 33 0 129 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 64 25 76)(font "Arial" ))
|
(text "inst" (rect 8 65 26 76)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 32)
|
(pt 0 32)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
|
(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
(line (pt 0 32)(pt 16 32))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 48)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||||
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 48)(pt 16 48)(line_width 1))
|
(line (pt 0 48)(pt 16 48))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 144 48)
|
(pt 144 48)
|
||||||
(output)
|
(output)
|
||||||
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
(text "shiftout" (rect 0 0 42 13)(font "Arial" (font_size 8)))
|
||||||
(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
|
(text "shiftout" (rect 91 42 126 54)(font "Arial" (font_size 8)))
|
||||||
(line (pt 144 48)(pt 128 48)(line_width 1))
|
(line (pt 144 48)(pt 128 48))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
|
(text "right shift" (rect 90 18 220 46)(font "Arial" ))
|
||||||
(line (pt 16 16)(pt 128 16)(line_width 1))
|
(line (pt 16 16)(pt 16 64))
|
||||||
(line (pt 128 16)(pt 128 64)(line_width 1))
|
(line (pt 16 16)(pt 128 16))
|
||||||
(line (pt 128 64)(pt 16 64)(line_width 1))
|
(line (pt 16 64)(pt 128 64))
|
||||||
(line (pt 16 64)(pt 16 16)(line_width 1))
|
(line (pt 128 16)(pt 128 64))
|
||||||
(line (pt 16 26)(pt 22 32)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 22 32)(pt 16 38)(line_width 1))
|
(line (pt 146 0)(pt 146 82))
|
||||||
|
(line (pt 0 82)(pt 146 82))
|
||||||
|
(line (pt 0 0)(pt 0 82))
|
||||||
|
(line (pt 16 26)(pt 22 32))
|
||||||
|
(line (pt 22 32)(pt 16 38))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_SHIFTREG%
|
-- megafunction wizard: %LPM_SHIFTREG%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_shiftreg
|
-- MODULE: LPM_SHIFTREG
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_shiftreg4.vhd
|
-- File Name: lpm_shiftreg4.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_shiftreg
|
-- LPM_SHIFTREG
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -63,15 +63,15 @@ ARCHITECTURE SYN OF lpm_shiftreg4 IS
|
|||||||
);
|
);
|
||||||
PORT (
|
PORT (
|
||||||
clock : IN STD_LOGIC ;
|
clock : IN STD_LOGIC ;
|
||||||
shiftout : OUT STD_LOGIC ;
|
shiftin : IN STD_LOGIC ;
|
||||||
shiftin : IN STD_LOGIC
|
shiftout : OUT STD_LOGIC
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
shiftout <= sub_wire0;
|
shiftout <= sub_wire0;
|
||||||
|
|
||||||
lpm_shiftreg_component : lpm_shiftreg
|
LPM_SHIFTREG_component : LPM_SHIFTREG
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_direction => "RIGHT",
|
lpm_direction => "RIGHT",
|
||||||
lpm_type => "LPM_SHIFTREG",
|
lpm_type => "LPM_SHIFTREG",
|
||||||
@@ -107,19 +107,20 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||||
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
|
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||||
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
|
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,39 +18,47 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 144 80)
|
(rect 0 0 144 80)
|
||||||
(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
|
(text "lpm_shiftreg6" (rect 33 0 128 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 64 25 76)(font "Arial" ))
|
(text "inst" (rect 8 65 26 76)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 32)
|
(pt 0 32)
|
||||||
(input)
|
(input)
|
||||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
|
||||||
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
|
(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
(line (pt 0 32)(pt 16 32))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 48)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||||
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
|
(text "shiftin" (rect 20 42 48 54)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 48)(pt 16 48)(line_width 1))
|
(line (pt 0 48)(pt 16 48))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 144 48)
|
(pt 144 48)
|
||||||
(output)
|
(output)
|
||||||
(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
(text "q[4..0]" (rect 0 0 36 13)(font "Arial" (font_size 8)))
|
||||||
(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
|
(text "q[4..0]" (rect 95 42 126 54)(font "Arial" (font_size 8)))
|
||||||
(line (pt 144 48)(pt 128 48)(line_width 3))
|
(line (pt 144 48)(pt 128 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
|
(text "right shift" (rect 90 18 220 46)(font "Arial" ))
|
||||||
(line (pt 16 16)(pt 128 16)(line_width 1))
|
(line (pt 16 16)(pt 16 64))
|
||||||
(line (pt 128 16)(pt 128 64)(line_width 1))
|
(line (pt 16 16)(pt 128 16))
|
||||||
(line (pt 128 64)(pt 16 64)(line_width 1))
|
(line (pt 16 64)(pt 128 64))
|
||||||
(line (pt 16 64)(pt 16 16)(line_width 1))
|
(line (pt 128 16)(pt 128 64))
|
||||||
(line (pt 16 26)(pt 22 32)(line_width 1))
|
(line (pt 0 0)(pt 146 0))
|
||||||
(line (pt 22 32)(pt 16 38)(line_width 1))
|
(line (pt 146 0)(pt 146 82))
|
||||||
|
(line (pt 0 82)(pt 146 82))
|
||||||
|
(line (pt 0 0)(pt 0 82))
|
||||||
|
(line (pt 16 26)(pt 22 32))
|
||||||
|
(line (pt 22 32)(pt 16 38))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
|
(line (pt 0 0)(pt 0 0))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
|
||||||
|
|||||||
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %LPM_SHIFTREG%
|
-- megafunction wizard: %LPM_SHIFTREG%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: lpm_shiftreg
|
-- MODULE: LPM_SHIFTREG
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: lpm_shiftreg6.vhd
|
-- File Name: lpm_shiftreg6.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- lpm_shiftreg
|
-- LPM_SHIFTREG
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- lpm
|
-- lpm
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -71,7 +71,7 @@ ARCHITECTURE SYN OF lpm_shiftreg6 IS
|
|||||||
BEGIN
|
BEGIN
|
||||||
q <= sub_wire0(4 DOWNTO 0);
|
q <= sub_wire0(4 DOWNTO 0);
|
||||||
|
|
||||||
lpm_shiftreg_component : lpm_shiftreg
|
LPM_SHIFTREG_component : LPM_SHIFTREG
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
lpm_direction => "RIGHT",
|
lpm_direction => "RIGHT",
|
||||||
lpm_type => "LPM_SHIFTREG",
|
lpm_type => "LPM_SHIFTREG",
|
||||||
@@ -107,19 +107,20 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||||
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
|
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||||
|
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||||
|
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||||
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||||
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
|
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
|
||||||
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
|
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
|
|
||||||
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
|
||||||
-- Retrieval info: LIB_FILE: lpm
|
-- Retrieval info: LIB_FILE: lpm
|
||||||
|
|||||||
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2008 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,47 +18,47 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 232 120)
|
(rect 0 0 192 112)
|
||||||
(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
(text "altddio_out3" (rect 57 0 156 17)(font "Dialog" (font_size 10)))
|
||||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
(text "inst" (rect 8 97 26 108)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 24)
|
(pt 0 48)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
(text "datain_h[0]" (rect 0 0 73 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
|
(text "datain_h[0]" (rect 4 35 67 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 24)(pt 88 24)(line_width 1))
|
(line (pt 0 48)(pt 64 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 40)
|
(pt 0 64)
|
||||||
(input)
|
(input)
|
||||||
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
(text "datain_l[0]" (rect 0 0 69 13)(font "Dialog" (font_size 8)))
|
||||||
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
|
(text "datain_l[0]" (rect 4 51 63 63)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 40)(pt 88 40)(line_width 1))
|
(line (pt 0 64)(pt 64 64)(line_width 3))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 0 56)
|
(pt 0 80)
|
||||||
(input)
|
(input)
|
||||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 0 0 55 13)(font "Dialog" (font_size 8)))
|
||||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
(text "outclock" (rect 4 67 52 79)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
(line (pt 0 80)(pt 64 80))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 232 24)
|
(pt 192 48)
|
||||||
(output)
|
(output)
|
||||||
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
(text "dataout[0]" (rect 0 0 68 13)(font "Dialog" (font_size 8)))
|
||||||
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
|
(text "dataout[0]" (rect 131 35 190 47)(font "Dialog" (font_size 8)))
|
||||||
(line (pt 232 24)(pt 152 24)(line_width 1))
|
(line (pt 192 48)(pt 128 48)(line_width 3))
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
(line (pt 64 32)(pt 128 32))
|
||||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
(line (pt 128 32)(pt 128 96))
|
||||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
(line (pt 64 96)(pt 128 96))
|
||||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
(line (pt 64 32)(pt 64 96))
|
||||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
(line (pt 0 0)(pt 192 0))
|
||||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
(line (pt 192 0)(pt 192 112))
|
||||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
(line (pt 0 112)(pt 192 112))
|
||||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
(line (pt 0 0)(pt 0 112))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -16,9 +16,9 @@
|
|||||||
component altddio_out3
|
component altddio_out3
|
||||||
PORT
|
PORT
|
||||||
(
|
(
|
||||||
datain_h : IN STD_LOGIC ;
|
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
datain_l : IN STD_LOGIC ;
|
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
outclock : IN STD_LOGIC ;
|
outclock : IN STD_LOGIC ;
|
||||||
dataout : OUT STD_LOGIC
|
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||||
);
|
);
|
||||||
end component;
|
end component;
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -15,11 +15,11 @@
|
|||||||
|
|
||||||
FUNCTION altddio_out3
|
FUNCTION altddio_out3
|
||||||
(
|
(
|
||||||
datain_h,
|
datain_h[0..0],
|
||||||
datain_l,
|
datain_l[0..0],
|
||||||
outclock
|
outclock
|
||||||
)
|
)
|
||||||
|
|
||||||
RETURNS (
|
RETURNS (
|
||||||
dataout
|
dataout[0..0]
|
||||||
);
|
);
|
||||||
|
|||||||
@@ -2,10 +2,10 @@
|
|||||||
<!DOCTYPE pinplan>
|
<!DOCTYPE pinplan>
|
||||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||||
<global>
|
<global>
|
||||||
<pin name="datain_h" direction="input" scope="external" />
|
<pin name="datain_h[0..0]" direction="input" scope="external" />
|
||||||
<pin name="datain_l" direction="input" scope="external" />
|
<pin name="datain_l[0..0]" direction="input" scope="external" />
|
||||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||||
<pin name="dataout" direction="output" scope="external" />
|
<pin name="dataout[0..0]" direction="output" scope="external" />
|
||||||
|
|
||||||
</global>
|
</global>
|
||||||
</pinplan>
|
</pinplan>
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
|
||||||
|
|||||||
102
altddio_out3.vhd
102
altddio_out3.vhd
@@ -1,12 +1,12 @@
|
|||||||
-- megafunction wizard: %ALTDDIO_OUT%
|
-- megafunction wizard: %ALTDDIO_OUT%
|
||||||
-- GENERATION: STANDARD
|
-- GENERATION: STANDARD
|
||||||
-- VERSION: WM1.0
|
-- VERSION: WM1.0
|
||||||
-- MODULE: altddio_out
|
-- MODULE: ALTDDIO_OUT
|
||||||
|
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- File Name: altddio_out3.vhd
|
-- File Name: altddio_out3.vhd
|
||||||
-- Megafunction Name(s):
|
-- Megafunction Name(s):
|
||||||
-- altddio_out
|
-- ALTDDIO_OUT
|
||||||
--
|
--
|
||||||
-- Simulation Library Files(s):
|
-- Simulation Library Files(s):
|
||||||
-- altera_mf
|
-- altera_mf
|
||||||
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2008 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -37,15 +37,15 @@ LIBRARY ieee;
|
|||||||
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
LIBRARY altera_mf;
|
LIBRARY altera_mf;
|
||||||
USE altera_mf.all;
|
USE altera_mf.altera_mf_components.all;
|
||||||
|
|
||||||
ENTITY altddio_out3 IS
|
ENTITY altddio_out3 IS
|
||||||
PORT
|
PORT
|
||||||
(
|
(
|
||||||
datain_h : IN STD_LOGIC ;
|
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
datain_l : IN STD_LOGIC ;
|
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
outclock : IN STD_LOGIC ;
|
outclock : IN STD_LOGIC ;
|
||||||
dataout : OUT STD_LOGIC
|
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||||
);
|
);
|
||||||
END altddio_out3;
|
END altddio_out3;
|
||||||
|
|
||||||
@@ -53,54 +53,25 @@ END altddio_out3;
|
|||||||
ARCHITECTURE SYN OF altddio_out3 IS
|
ARCHITECTURE SYN OF altddio_out3 IS
|
||||||
|
|
||||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
|
||||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
|
||||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
|
||||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
|
||||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
COMPONENT altddio_out
|
|
||||||
GENERIC (
|
|
||||||
extend_oe_disable : STRING;
|
|
||||||
intended_device_family : STRING;
|
|
||||||
invert_output : STRING;
|
|
||||||
lpm_type : STRING;
|
|
||||||
oe_reg : STRING;
|
|
||||||
power_up_high : STRING;
|
|
||||||
width : NATURAL
|
|
||||||
);
|
|
||||||
PORT (
|
|
||||||
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
|
||||||
outclock : IN STD_LOGIC ;
|
|
||||||
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
|
||||||
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
|
|
||||||
);
|
|
||||||
END COMPONENT;
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
sub_wire1 <= sub_wire0(0);
|
dataout <= sub_wire0(0 DOWNTO 0);
|
||||||
dataout <= sub_wire1;
|
|
||||||
sub_wire2 <= datain_h;
|
|
||||||
sub_wire3(0) <= sub_wire2;
|
|
||||||
sub_wire4 <= datain_l;
|
|
||||||
sub_wire5(0) <= sub_wire4;
|
|
||||||
|
|
||||||
altddio_out_component : altddio_out
|
ALTDDIO_OUT_component : ALTDDIO_OUT
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
extend_oe_disable => "UNUSED",
|
extend_oe_disable => "OFF",
|
||||||
intended_device_family => "Cyclone III",
|
intended_device_family => "Cyclone III",
|
||||||
invert_output => "OFF",
|
invert_output => "OFF",
|
||||||
|
lpm_hint => "UNUSED",
|
||||||
lpm_type => "altddio_out",
|
lpm_type => "altddio_out",
|
||||||
oe_reg => "UNUSED",
|
oe_reg => "UNREGISTERED",
|
||||||
power_up_high => "OFF",
|
power_up_high => "OFF",
|
||||||
width => 1
|
width => 1
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
|
datain_h => datain_h,
|
||||||
|
datain_l => datain_l,
|
||||||
outclock => outclock,
|
outclock => outclock,
|
||||||
datain_h => sub_wire3,
|
|
||||||
datain_l => sub_wire5,
|
|
||||||
dataout => sub_wire0
|
dataout => sub_wire0
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -111,36 +82,29 @@ END SYN;
|
|||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- CNX file retrieval info
|
-- CNX file retrieval info
|
||||||
-- ============================================================
|
-- ============================================================
|
||||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
|
||||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
|
||||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
||||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
|
|
||||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
|
||||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||||
|
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||||
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
|
-- Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
|
||||||
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
|
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
|
||||||
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
|
-- Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
|
||||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
|
||||||
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
|
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
|
||||||
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
|
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
|
||||||
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
|
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.qip TRUE FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE FALSE
|
||||||
-- Retrieval info: LIB_FILE: altera_mf
|
-- Retrieval info: LIB_FILE: altera_mf
|
||||||
|
|||||||
124
altpll1.bsf
124
altpll1.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2010 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 328 216)
|
(rect 0 0 272 176)
|
||||||
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
|
(text "altpll1" (rect 119 0 161 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 197 31 212)(font "Arial" ))
|
(text "inst" (rect 8 161 26 172)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 64)
|
||||||
(input)
|
(input)
|
||||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
(line (pt 0 64)(pt 40 64))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 328 72)
|
(pt 272 64)
|
||||||
(output)
|
(output)
|
||||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
|
(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 328 72)(pt 272 72)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 328 96)
|
(pt 272 80)
|
||||||
(output)
|
(output)
|
||||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
|
(text "c1" (rect 257 67 269 79)(font "Arial" (font_size 8)))
|
||||||
(line (pt 328 96)(pt 272 96)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 328 120)
|
(pt 272 96)
|
||||||
(output)
|
(output)
|
||||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
|
(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
|
||||||
(line (pt 328 120)(pt 272 120)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 328 144)
|
(pt 272 112)
|
||||||
(output)
|
(output)
|
||||||
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
|
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
|
||||||
(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
|
(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
|
||||||
(line (pt 328 144)(pt 272 144)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
|
(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
|
||||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
|
||||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
|
||||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
|
||||||
(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
|
(text "Ratio" (rect 74 91 171 192)(font "Arial" ))
|
||||||
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
|
(text "Ph (dg)" (rect 104 91 239 192)(font "Arial" ))
|
||||||
(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
|
(text "DC (%)" (rect 139 91 310 192)(font "Arial" ))
|
||||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
(text "c0" (rect 54 104 119 218)(font "Arial" ))
|
||||||
(text "1/66" (rect 92 129 113 143)(font "Arial" ))
|
(text "1/66" (rect 76 104 171 218)(font "Arial" ))
|
||||||
(text "0.00" (rect 136 129 157 143)(font "Arial" ))
|
(text "0.00" (rect 110 104 239 218)(font "Arial" ))
|
||||||
(text "50.00" (rect 178 129 205 143)(font "Arial" ))
|
(text "50.00" (rect 143 104 310 218)(font "Arial" ))
|
||||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
(text "c1" (rect 54 117 119 244)(font "Arial" ))
|
||||||
(text "67/900" (rect 85 147 118 161)(font "Arial" ))
|
(text "67/900" (rect 71 117 171 244)(font "Arial" ))
|
||||||
(text "0.00" (rect 136 147 157 161)(font "Arial" ))
|
(text "0.00" (rect 110 117 239 244)(font "Arial" ))
|
||||||
(text "50.00" (rect 178 147 205 161)(font "Arial" ))
|
(text "50.00" (rect 143 117 310 244)(font "Arial" ))
|
||||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
(text "c2" (rect 54 130 119 270)(font "Arial" ))
|
||||||
(text "67/90" (rect 89 165 116 179)(font "Arial" ))
|
(text "67/90" (rect 74 130 172 270)(font "Arial" ))
|
||||||
(text "0.00" (rect 136 165 157 179)(font "Arial" ))
|
(text "0.00" (rect 110 130 239 270)(font "Arial" ))
|
||||||
(text "50.00" (rect 178 165 205 179)(font "Arial" ))
|
(text "50.00" (rect 143 130 310 270)(font "Arial" ))
|
||||||
(line (pt 0 0)(pt 329 0)(line_width 1))
|
(line (pt 0 0)(pt 273 0))
|
||||||
(line (pt 329 0)(pt 329 217)(line_width 1))
|
(line (pt 273 0)(pt 273 177))
|
||||||
(line (pt 0 217)(pt 329 217)(line_width 1))
|
(line (pt 0 177)(pt 273 177))
|
||||||
(line (pt 0 0)(pt 0 217)(line_width 1))
|
(line (pt 0 0)(pt 0 177))
|
||||||
(line (pt 56 108)(pt 215 108)(line_width 1))
|
(line (pt 48 89)(pt 171 89))
|
||||||
(line (pt 56 125)(pt 215 125)(line_width 1))
|
(line (pt 48 101)(pt 171 101))
|
||||||
(line (pt 56 143)(pt 215 143)(line_width 1))
|
(line (pt 48 114)(pt 171 114))
|
||||||
(line (pt 56 161)(pt 215 161)(line_width 1))
|
(line (pt 48 127)(pt 171 127))
|
||||||
(line (pt 56 179)(pt 215 179)(line_width 1))
|
(line (pt 48 140)(pt 171 140))
|
||||||
(line (pt 56 108)(pt 56 179)(line_width 1))
|
(line (pt 48 89)(pt 48 140))
|
||||||
(line (pt 82 108)(pt 82 179)(line_width 3))
|
(line (pt 68 89)(pt 68 140)(line_width 3))
|
||||||
(line (pt 125 108)(pt 125 179)(line_width 3))
|
(line (pt 101 89)(pt 101 140)(line_width 3))
|
||||||
(line (pt 170 108)(pt 170 179)(line_width 3))
|
(line (pt 136 89)(pt 136 140)(line_width 3))
|
||||||
(line (pt 214 108)(pt 214 179)(line_width 1))
|
(line (pt 170 89)(pt 170 140))
|
||||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
(line (pt 40 48)(pt 223 48))
|
||||||
(line (pt 272 56)(pt 272 200)(line_width 1))
|
(line (pt 223 48)(pt 223 159))
|
||||||
(line (pt 48 200)(pt 272 200)(line_width 1))
|
(line (pt 40 159)(pt 223 159))
|
||||||
(line (pt 48 56)(pt 48 200)(line_width 1))
|
(line (pt 40 48)(pt 40 159))
|
||||||
|
(line (pt 271 64)(pt 223 64))
|
||||||
|
(line (pt 271 80)(pt 223 80))
|
||||||
|
(line (pt 271 96)(pt 223 96))
|
||||||
|
(line (pt 271 112)(pt 223 112))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2010 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,4 +1,4 @@
|
|||||||
--Copyright (C) 1991-2010 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
|
||||||
|
|||||||
32
altpll1.vhd
32
altpll1.vhd
@@ -14,11 +14,11 @@
|
|||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
--
|
--
|
||||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||||
-- ************************************************************
|
-- ************************************************************
|
||||||
|
|
||||||
|
|
||||||
--Copyright (C) 1991-2010 Altera Corporation
|
--Copyright (C) 1991-2013 Altera Corporation
|
||||||
--Your use of Altera Corporation's design tools, logic functions
|
--Your use of Altera Corporation's design tools, logic functions
|
||||||
--and other software and tools, and its AMPP partner logic
|
--and other software and tools, and its AMPP partner logic
|
||||||
--functions, and any output files from any of the foregoing
|
--functions, and any output files from any of the foregoing
|
||||||
@@ -131,22 +131,22 @@ ARCHITECTURE SYN OF altpll1 IS
|
|||||||
width_clock : NATURAL
|
width_clock : NATURAL
|
||||||
);
|
);
|
||||||
PORT (
|
PORT (
|
||||||
|
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||||
locked : OUT STD_LOGIC ;
|
locked : OUT STD_LOGIC
|
||||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||||
sub_wire3 <= sub_wire0(2);
|
sub_wire4 <= sub_wire0(2);
|
||||||
sub_wire2 <= sub_wire0(1);
|
sub_wire3 <= sub_wire0(0);
|
||||||
sub_wire1 <= sub_wire0(0);
|
sub_wire1 <= sub_wire0(1);
|
||||||
c0 <= sub_wire1;
|
c1 <= sub_wire1;
|
||||||
c1 <= sub_wire2;
|
locked <= sub_wire2;
|
||||||
c2 <= sub_wire3;
|
c0 <= sub_wire3;
|
||||||
locked <= sub_wire4;
|
c2 <= sub_wire4;
|
||||||
sub_wire5 <= inclk0;
|
sub_wire5 <= inclk0;
|
||||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||||
|
|
||||||
@@ -218,7 +218,7 @@ BEGIN
|
|||||||
PORT MAP (
|
PORT MAP (
|
||||||
inclk => sub_wire6,
|
inclk => sub_wire6,
|
||||||
clk => sub_wire0,
|
clk => sub_wire0,
|
||||||
locked => sub_wire4
|
locked => sub_wire2
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -270,7 +270,7 @@ END SYN;
|
|||||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||||
@@ -406,17 +406,17 @@ END SYN;
|
|||||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
|
||||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
|
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
|
||||||
|
|||||||
134
altpll3.bsf
134
altpll3.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
|||||||
the Block Editor! File corruption is VERY likely to occur.
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
Copyright (C) 1991-2010 Altera Corporation
|
Copyright (C) 1991-2013 Altera Corporation
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and its AMPP partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
@@ -18,88 +18,88 @@ programming logic devices manufactured by Altera and sold by
|
|||||||
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
||||||
applicable agreement for further details.
|
applicable agreement for further details.
|
||||||
*/
|
*/
|
||||||
(header "symbol" (version "1.1"))
|
(header "symbol" (version "1.2"))
|
||||||
(symbol
|
(symbol
|
||||||
(rect 0 0 304 232)
|
(rect 0 0 256 184)
|
||||||
(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
|
(text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10)))
|
||||||
(text "inst" (rect 8 213 31 228)(font "Arial" ))
|
(text "inst" (rect 8 169 26 180)(font "Arial" ))
|
||||||
(port
|
(port
|
||||||
(pt 0 72)
|
(pt 0 64)
|
||||||
(input)
|
(input)
|
||||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
(line (pt 0 64)(pt 40 64))
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 304 72)
|
(pt 256 64)
|
||||||
(output)
|
(output)
|
||||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
|
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
|
||||||
(line (pt 304 72)(pt 272 72)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 304 96)
|
(pt 256 80)
|
||||||
(output)
|
(output)
|
||||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c1" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
|
(text "c1" (rect 241 67 253 79)(font "Arial" (font_size 8)))
|
||||||
(line (pt 304 96)(pt 272 96)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 304 120)
|
(pt 256 96)
|
||||||
(output)
|
(output)
|
||||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
|
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
|
||||||
(line (pt 304 120)(pt 272 120)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(port
|
(port
|
||||||
(pt 304 144)
|
(pt 256 112)
|
||||||
(output)
|
(output)
|
||||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
||||||
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
|
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
|
||||||
(line (pt 304 144)(pt 272 144)(line_width 1))
|
|
||||||
)
|
)
|
||||||
(drawing
|
(drawing
|
||||||
(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
|
(text "Cyclone III" (rect 198 170 442 350)(font "Arial" ))
|
||||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
|
||||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
|
||||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
|
||||||
(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
|
(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
|
||||||
(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
|
(text "Ph (dg)" (rect 98 91 227 192)(font "Arial" ))
|
||||||
(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
|
(text "DC (%)" (rect 133 91 298 192)(font "Arial" ))
|
||||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
(text "c0" (rect 54 104 119 218)(font "Arial" ))
|
||||||
(text "2/33" (rect 88 129 109 143)(font "Arial" ))
|
(text "2/33" (rect 73 104 165 218)(font "Arial" ))
|
||||||
(text "0.00" (rect 129 129 150 143)(font "Arial" ))
|
(text "0.00" (rect 104 104 227 218)(font "Arial" ))
|
||||||
(text "50.00" (rect 171 129 198 143)(font "Arial" ))
|
(text "50.00" (rect 137 104 298 218)(font "Arial" ))
|
||||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
(text "c1" (rect 54 117 119 244)(font "Arial" ))
|
||||||
(text "16/33" (rect 85 147 112 161)(font "Arial" ))
|
(text "16/33" (rect 71 117 166 244)(font "Arial" ))
|
||||||
(text "0.00" (rect 129 147 150 161)(font "Arial" ))
|
(text "0.00" (rect 104 117 227 244)(font "Arial" ))
|
||||||
(text "50.00" (rect 171 147 198 161)(font "Arial" ))
|
(text "50.00" (rect 137 117 298 244)(font "Arial" ))
|
||||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
(text "c2" (rect 54 130 119 270)(font "Arial" ))
|
||||||
(text "25/33" (rect 85 165 112 179)(font "Arial" ))
|
(text "25/33" (rect 71 130 166 270)(font "Arial" ))
|
||||||
(text "0.00" (rect 129 165 150 179)(font "Arial" ))
|
(text "0.00" (rect 104 130 227 270)(font "Arial" ))
|
||||||
(text "50.00" (rect 171 165 198 179)(font "Arial" ))
|
(text "50.00" (rect 137 130 298 270)(font "Arial" ))
|
||||||
(text "c3" (rect 63 183 75 197)(font "Arial" ))
|
(text "c3" (rect 54 143 119 296)(font "Arial" ))
|
||||||
(text "16/11" (rect 85 183 112 197)(font "Arial" ))
|
(text "16/11" (rect 71 143 166 296)(font "Arial" ))
|
||||||
(text "0.00" (rect 129 183 150 197)(font "Arial" ))
|
(text "0.00" (rect 104 143 227 296)(font "Arial" ))
|
||||||
(text "50.00" (rect 171 183 198 197)(font "Arial" ))
|
(text "50.00" (rect 137 143 298 296)(font "Arial" ))
|
||||||
(line (pt 0 0)(pt 305 0)(line_width 1))
|
(line (pt 0 0)(pt 257 0))
|
||||||
(line (pt 305 0)(pt 305 233)(line_width 1))
|
(line (pt 257 0)(pt 257 185))
|
||||||
(line (pt 0 233)(pt 305 233)(line_width 1))
|
(line (pt 0 185)(pt 257 185))
|
||||||
(line (pt 0 0)(pt 0 233)(line_width 1))
|
(line (pt 0 0)(pt 0 185))
|
||||||
(line (pt 56 108)(pt 208 108)(line_width 1))
|
(line (pt 48 89)(pt 165 89))
|
||||||
(line (pt 56 125)(pt 208 125)(line_width 1))
|
(line (pt 48 101)(pt 165 101))
|
||||||
(line (pt 56 143)(pt 208 143)(line_width 1))
|
(line (pt 48 114)(pt 165 114))
|
||||||
(line (pt 56 161)(pt 208 161)(line_width 1))
|
(line (pt 48 127)(pt 165 127))
|
||||||
(line (pt 56 179)(pt 208 179)(line_width 1))
|
(line (pt 48 140)(pt 165 140))
|
||||||
(line (pt 56 197)(pt 208 197)(line_width 1))
|
(line (pt 48 153)(pt 165 153))
|
||||||
(line (pt 56 108)(pt 56 197)(line_width 1))
|
(line (pt 48 89)(pt 48 153))
|
||||||
(line (pt 82 108)(pt 82 197)(line_width 3))
|
(line (pt 68 89)(pt 68 153)(line_width 3))
|
||||||
(line (pt 118 108)(pt 118 197)(line_width 3))
|
(line (pt 95 89)(pt 95 153)(line_width 3))
|
||||||
(line (pt 163 108)(pt 163 197)(line_width 3))
|
(line (pt 130 89)(pt 130 153)(line_width 3))
|
||||||
(line (pt 207 108)(pt 207 197)(line_width 1))
|
(line (pt 164 89)(pt 164 153))
|
||||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
(line (pt 40 48)(pt 223 48))
|
||||||
(line (pt 272 56)(pt 272 216)(line_width 1))
|
(line (pt 223 48)(pt 223 167))
|
||||||
(line (pt 48 216)(pt 272 216)(line_width 1))
|
(line (pt 40 167)(pt 223 167))
|
||||||
(line (pt 48 56)(pt 48 216)(line_width 1))
|
(line (pt 40 48)(pt 40 167))
|
||||||
|
(line (pt 255 64)(pt 223 64))
|
||||||
|
(line (pt 255 80)(pt 223 80))
|
||||||
|
(line (pt 255 96)(pt 223 96))
|
||||||
|
(line (pt 255 112)(pt 223 112))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user