From 7c25bc1124d5c2d5fd6722c184b450115be62243 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 2 Nov 2013 20:43:29 +0000 Subject: [PATCH] fixed a few compile errors (still some left) --- BaS_gcc/include/pci.h | 127 +++++++++++++++++++++++++++++++++++++ BaS_gcc/include/usb.h | 2 +- BaS_gcc/sources/ohci-hcd.c | 2 +- 3 files changed, 129 insertions(+), 2 deletions(-) diff --git a/BaS_gcc/include/pci.h b/BaS_gcc/include/pci.h index b303bc7..1671c6f 100644 --- a/BaS_gcc/include/pci.h +++ b/BaS_gcc/include/pci.h @@ -26,6 +26,133 @@ #define PCI_IO_OFFSET (0xD0000000) #define PCI_IO_SIZE (0x10000000) /* 128 MByte PCI I/O window */ +#define PCIIDR 0x00 /* PCI Configuration ID Register */ +#define PCICSR 0x04 /* PCI Command/Status Register */ +#define PCICR 0x04 /* PCI Command Register */ +#define PCISR 0x06 /* PCI Status Register */ +#define PCIREV 0x08 /* PCI Revision ID Register */ +#define PCICCR 0x09 /* PCI Class Code Register */ +#define PCICLSR 0x0C /* PCI Cache Line Size Register */ +#define PCILTR 0x0D /* PCI Latency Timer Register */ +#define PCIHTR 0x0E /* PCI Header Type Register */ +#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */ +#define PCIBAR0 0x10 /* PCI Base Address Register for Memory + Accesses to Local, Runtime, and DMA */ +#define PCIBAR1 0x14 /* PCI Base Address Register for I/O + Accesses to Local, Runtime, and DMA */ +#define PCIBAR2 0x18 /* PCI Base Address Register for Memory + Accesses to Local Address Space 0 */ +#define PCIBAR3 0x1C /* PCI Base Address Register for Memory + Accesses to Local Address Space 1 */ +#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */ +#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */ +#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/ +#define PCISVID 0x2C /* PCI Subsystem Vendor ID */ +#define PCISID 0x2E /* PCI Subsystem ID */ +#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */ +#define CAP_PTR 0x34 /* New Capability Pointer */ +#define PCIILR 0x3C /* PCI Interrupt Line Register */ +#define PCIIPR 0x3D /* PCI Interrupt Pin Register */ +#define PCIMGR 0x3E /* PCI Min_Gnt Register */ +#define PCIMLR 0x3F /* PCI Max_Lat Register */ +#define PMCAPID 0x40 /* Power Management Capability ID */ +#define PMNEXT 0x41 /* Power Management Next Capability + Pointer */ +#define PMC 0x42 /* Power Management Capabilities */ +#define PMCSR 0x44 /* Power Management Control/Status */ +#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */ +#define PMDATA 0x47 /* Power Management Data */ +#define HS_CNTL 0x48 /* Hot Swap Control */ +#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */ +#define HS_CSR 0x4A /* Hot Swap Control/Status */ +#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */ +#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next + Capability Pointer */ +#define PVPDAD 0x4E /* PCI Vital Product Data Address */ +#define PVPDATA 0x50 /* PCI VPD Data */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1A /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1B /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1D +#define PCI_SEC_STATUS 0x1E /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2C +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */ + +typedef struct +{ + unsigned long *subcookie; + unsigned long version; + long routine[45]; +} PCI_COOKIE; + +typedef struct /* structure of resource descriptor */ +{ + unsigned short next; /* length of the following structure */ + unsigned short flags; /* type of resource and misc. flags */ + unsigned long start; /* start-address of resource */ + unsigned long length; /* length of resource */ + unsigned long offset; /* offset PCI to phys. CPU Address */ + unsigned long dmaoffset; /* offset for DMA-transfers */ +} PCI_RSC_DESC; + +typedef struct /* structure of address conversion */ +{ + unsigned long adr; /* calculated address (CPU<->PCI) */ + unsigned long len; /* length of memory range */ +} PCI_CONV_ADR; + +/******************************************************************************/ +/* PCI-BIOS Error Codes */ +/******************************************************************************/ +#define PCI_SUCCESSFUL 0 /* everything's fine */ +#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */ +#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */ +#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */ +#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */ +#define PCI_SET_FAILED -6 /* reserved for later use */ +#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */ +#define PCI_GENERAL_ERROR -8 /* general BIOS error code */ +#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */ + +/******************************************************************************/ +/* Flags used in Resource-Descriptor */ +/******************************************************************************/ +#define FLG_IO 0x4000 /* Ressource in IO range */ +#define FLG_ROM 0x2000 /* Expansion ROM */ +#define FLG_LAST 0x8000 /* last ressource */ +#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */ +#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */ +#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */ +#define FLG_ENDMASK 0x000F /* mask for byte ordering */ + +/******************************************************************************/ +/* Values used in FLG_ENDMASK for Byte Ordering */ +/******************************************************************************/ +#define ORD_MOTOROLA 0 /* Motorola (big endian) */ +#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */ +#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */ +#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */ + +/******************************************************************************/ +/* Status Info used in Device-Descriptor */ +/******************************************************************************/ +#define DEVICE_FREE 0 /* Device is not used */ +#define DEVICE_USED 1 /* Device is used by another driver */ +#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */ +#define DEVICE_AVAILABLE 3 /* used, not available */ +#define NO_DEVICE -1 /* no device detected */ + /* PCI configuration space macros */ /* register 0x00 macros */ diff --git a/BaS_gcc/include/usb.h b/BaS_gcc/include/usb.h index 77ad4cc..8ca3173 100644 --- a/BaS_gcc/include/usb.h +++ b/BaS_gcc/include/usb.h @@ -30,7 +30,7 @@ #include #include "pci.h" #include "mod_devicetable.h" -//#include "pci_ids.h" +#include "pci_ids.h" #include "part.h" diff --git a/BaS_gcc/sources/ohci-hcd.c b/BaS_gcc/sources/ohci-hcd.c index 798ec49..717dfa8 100644 --- a/BaS_gcc/sources/ohci-hcd.c +++ b/BaS_gcc/sources/ohci-hcd.c @@ -46,7 +46,7 @@ #include "usb.h" #include "ohci.h" -extern xQueueHandle queue_poll_hub; +//extern xQueueHandle queue_poll_hub; #undef DEBUG_PCIE