From 7adab9f89bffdd5f9a6e35271fd0725674dc5ca5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 8 Aug 2013 15:47:09 +0000 Subject: [PATCH] backported interrupts.c from i2c branch --- BaS_gcc/Makefile | 1 + BaS_gcc/include/bas_utils.h | 14 +++++++ BaS_gcc/include/interrupts.h | 64 +++++++++++++++++++++++++++++ BaS_gcc/sources/interrupts.c | 78 ++++++++++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+) create mode 100644 BaS_gcc/include/bas_utils.h create mode 100644 BaS_gcc/include/interrupts.h create mode 100644 BaS_gcc/sources/interrupts.c diff --git a/BaS_gcc/Makefile b/BaS_gcc/Makefile index 108aa6e..0d99240 100644 --- a/BaS_gcc/Makefile +++ b/BaS_gcc/Makefile @@ -62,6 +62,7 @@ CSRCS= \ $(SRCDIR)/sysinit.c \ $(SRCDIR)/init_fpga.c \ $(SRCDIR)/fault_vectors.c \ + $(SRCDIR)/interrupts.c \ $(SRCDIR)/bas_printf.c \ $(SRCDIR)/bas_string.c \ $(SRCDIR)/BaS.c \ diff --git a/BaS_gcc/include/bas_utils.h b/BaS_gcc/include/bas_utils.h new file mode 100644 index 0000000..2963d8b --- /dev/null +++ b/BaS_gcc/include/bas_utils.h @@ -0,0 +1,14 @@ +/* + * bas_utils.h + * + * Created on: 08.08.2013 + * Author: froesm1 + */ + +#ifndef _BAS_UTILS_H_ +#define _BAS_UTILS_H_ + +#define CLEAR_BIT(p,bit) p &= ~(bit) +#define CLEAR_BIT_NO(p,nr) CLEAR_BIT(p, (1 << (nr))) + +#endif /* _BAS_UTILS_H_ */ diff --git a/BaS_gcc/include/interrupts.h b/BaS_gcc/include/interrupts.h new file mode 100644 index 0000000..27c52ec --- /dev/null +++ b/BaS_gcc/include/interrupts.h @@ -0,0 +1,64 @@ +/* + * interrupts.h + * + * Created on: 08.08.2013 + * Author: froesm1 + */ + +#ifndef _INTERRUPTS_H_ +#define _INTERRUPTS_H_ + +/* interrupt sources */ +#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1 +#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2 +#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3 +#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4 +#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5 +#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6 +#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7 +#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt +#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt +#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt +#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt +#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt +#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt +#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt +#define INT_SOURCE_USB_USBISR 22 // USB general interrupt +#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt +#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts +#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow +#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt +#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt +#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt +#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt +#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt +#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt +#define INT_SOURCE_PSC3 32 // PSC3 interrupt +#define INT_SOURCE_PSC2 33 // PSC2 interrupt +#define INT_SOURCE_PSC1 34 // PSC1 interrupt +#define INT_SOURCE_PSC0 35 // PSC0 interrupt +#define INT_SOURCE_CTIMERS 36 // combined source for comm timers +#define INT_SOURCE_SEC 37 // SEC interrupt +#define INT_SOURCE_FEC1 38 // FEC1 interrupt +#define INT_SOURCE_FEC0 39 // FEC0 interrupt +#define INT_SOURCE_I2C 40 // I2C interrupt +#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt +#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt +#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt +#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt +#define INT_SOURCE_DMA 48 // multichannel DMA interrupt +#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt +#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt +#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt +#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt +#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt +#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt +#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt +#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt +#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt +#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt +#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt +#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt + + +#endif /* _INTERRUPTS_H_ */ diff --git a/BaS_gcc/sources/interrupts.c b/BaS_gcc/sources/interrupts.c new file mode 100644 index 0000000..bd6ba7d --- /dev/null +++ b/BaS_gcc/sources/interrupts.c @@ -0,0 +1,78 @@ +/* + * Interrupts + * + * Handle interrupts, the levels. + * + */ + +#include +#include "bas_utils.h" +#include "interrupts.h" +#include "MCF5475.h" + +extern uint8_t _rtl_vbr[]; +#define VBR ((uint32_t **) &_rtl_vbr[0]) + +/* + * register an interrupt handler at the Coldfire interrupt controller and add the handler to the interrupt vector table + */ +int register_handler(uint8_t priority, uint8_t intr, void (*func)()) +{ + int i; + uint8_t level = 0b01111111; + uint32_t **adr = VBR; + + intr &= 63; + priority &= 7; + + if (intr <= 0) + return -1; + + for (i = 1; i < 64; i++) + if (i != intr) + { + if ((MCF_INTC_ICR(i) & 7) == priority) + CLEAR_BIT_NO(level, (MCF_INTC_ICR(i) >> 3) & 7); + } + + for (i = 0; 1 < 7; i++) + if (level & (1 << i)) + break; + + if (i >= 7) + return -1; + + /* + * Make sure priority level is high, before changing registers + */ + __asm__ volatile ( + "move.w sr,d0\n\t" + "move.w d0,-(sp) \n\t" + "move.w #0x2700,sr\n\t" + : + : + : "sp","d0","memory" + ); + + if (intr < 32) + CLEAR_BIT(MCF_INTC_IMRL, (1 << intr)); + else + CLEAR_BIT(MCF_INTC_IMRH, (1 << (intr - 32))); + + MCF_INTC_ICR(intr) = MCF_INTC_ICR_IP(priority) | MCF_INTC_ICR_IL(i); + + adr[64 + intr] = (uint32_t *) func; /* first 64 vectors are system exceptions */ + + /* + * Return the saved priority level + */ + __asm__ volatile ( + "move.w (sp)+,d2\n\t" + "move.w d2,sr\n\t" + : + : + : "sp","d2","memory" + ); + + return 0; +}