fixed formatting
This commit is contained in:
@@ -96,7 +96,7 @@ LIBRARY IEEE;
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ENTITY firebee IS
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PORT(
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rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire
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rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire
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clk_33m : IN STD_LOGIC; -- 33 MHz clock
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clk_main : IN STD_LOGIC; -- 33 MHz clock
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@@ -108,34 +108,34 @@ ENTITY firebee IS
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fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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fb_ale : IN STD_LOGIC;
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fb_burst_n : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1);
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fb_burst_n : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1);
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fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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fb_oe_n : IN STD_LOGIC;
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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fb_ta_n : OUT STD_LOGIC;
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fb_ta_n : OUT STD_LOGIC;
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dack1_n : IN STD_LOGIC;
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dreq1_n : OUT STD_LOGIC;
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dack1_n : IN STD_LOGIC;
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dreq1_n : OUT STD_LOGIC;
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master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
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tout0_n : IN STD_LOGIC; -- Not used so far.
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master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
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tout0_n : IN STD_LOGIC; -- Not used so far.
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led_fpga_ok : OUT STD_LOGIC;
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reserved_1 : OUT STD_LOGIC;
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va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
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ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
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vwe_n : OUT STD_LOGIC;
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vwe_n : OUT STD_LOGIC;
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vcas_n : OUT STD_LOGIC;
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vras_n : OUT STD_LOGIC;
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vcs_n : OUT STD_LOGIC;
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vcs_n : OUT STD_LOGIC;
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clk_pixel : OUT STD_LOGIC;
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sync_n : OUT STD_LOGIC;
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sync_n : OUT STD_LOGIC;
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vsync : OUT STD_LOGIC;
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hsync : OUT STD_LOGIC;
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blank_n : OUT STD_LOGIC;
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blank_n : OUT STD_LOGIC;
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vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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@@ -146,17 +146,17 @@ ENTITY firebee IS
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vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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pd_vga_n : OUT STD_LOGIC;
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pd_vga_n : OUT STD_LOGIC;
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vcke : OUT STD_LOGIC;
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pic_int : IN STD_LOGIC;
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e0_int : IN STD_LOGIC;
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dvi_int : IN STD_LOGIC;
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pci_inta_n : IN STD_LOGIC;
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pci_intb_n : IN STD_LOGIC;
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pci_intc_n : IN STD_LOGIC;
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pci_intd_n : IN STD_LOGIC;
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pci_inta_n : IN STD_LOGIC;
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pci_intb_n : IN STD_LOGIC;
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pci_intc_n : IN STD_LOGIC;
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pci_intd_n : IN STD_LOGIC;
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irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2);
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irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2);
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tin0 : OUT STD_LOGIC;
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ym_qa : OUT STD_LOGIC;
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@@ -182,7 +182,7 @@ ENTITY firebee IS
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pic_amkb_rx : IN STD_LOGIC;
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amkb_rx : IN STD_LOGIC;
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amkb_tx : OUT STD_LOGIC;
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dack0_n : IN STD_LOGIC; -- Not used.
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dack0_n : IN STD_LOGIC; -- Not used.
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scsi_drqn : IN STD_LOGIC;
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SCSI_MSGn : IN STD_LOGIC;
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@@ -201,7 +201,7 @@ ENTITY firebee IS
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ACSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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ACSI_CSn : OUT STD_LOGIC;
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ACSI_A1 : OUT STD_LOGIC;
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ACSI_reset_n : OUT STD_LOGIC;
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ACSI_reset_n : OUT STD_LOGIC;
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ACSI_ACKn : OUT STD_LOGIC;
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ACSI_DRQn : IN STD_LOGIC;
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ACSI_INTn : IN STD_LOGIC;
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@@ -257,9 +257,9 @@ ARCHITECTURE Structure of firebee is
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COMPONENT altpll1
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PORT(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c0 : OUT STD_LOGIC;
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c1 : OUT STD_LOGIC;
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c2 : OUT STD_LOGIC;
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locked : OUT STD_LOGIC
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);
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END COMPONENT;
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@@ -267,10 +267,10 @@ ARCHITECTURE Structure of firebee is
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COMPONENT altpll2
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PORT(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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c0 : OUT STD_LOGIC;
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c1 : OUT STD_LOGIC;
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c2 : OUT STD_LOGIC;
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c3 : OUT STD_LOGIC;
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c4 : OUT STD_LOGIC
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);
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END COMPONENT;
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@@ -287,12 +287,12 @@ ARCHITECTURE Structure of firebee is
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COMPONENT altpll4
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PORT(
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areset : IN STD_LOGIC := '0';
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configupdate : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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scanclk : IN STD_LOGIC := '1';
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scanclkena : IN STD_LOGIC := '0';
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scandata : IN STD_LOGIC := '0';
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areset : IN STD_LOGIC := '0';
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configupdate : IN STD_LOGIC := '0';
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inclk0 : IN STD_LOGIC := '0';
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scanclk : IN STD_LOGIC := '1';
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scanclkena : IN STD_LOGIC := '0';
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scandata : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC;
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locked : OUT STD_LOGIC;
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scandataOUT : OUT STD_LOGIC;
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@@ -397,8 +397,8 @@ ARCHITECTURE Structure of firebee is
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SIGNAL fb_ad_out_rtc : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL fb_ad_out_video : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL fb_adr : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL fb_b0 : STD_LOGIC; -- UPPER Byte BEI 16 STD_LOGIC BUS
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SIGNAL fb_b1 : STD_LOGIC; -- LOWER Byte BEI 16 STD_LOGIC BUS
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SIGNAL fb_b0 : STD_LOGIC; -- UPPER Byte BEI 16 STD_LOGIC BUS
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SIGNAL fb_b1 : STD_LOGIC; -- LOWER Byte BEI 16 STD_LOGIC BUS
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SIGNAL fb_ddr : STD_LOGIC_VECTOR (127 DOWNTO 0);
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SIGNAL fb_le : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL fb_vdoe : STD_LOGIC_VECTOR (3 DOWNTO 0);
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@@ -754,7 +754,7 @@ BEGIN
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variable DDR_D_OUT_H : STD_LOGIC_VECTOR(31 DOWNTO 0);
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variable DDR_D_OUT_L : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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IF clk_ddr(3) = '1' and clk_ddr(3)' event THEN
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IF RISING_EDGE(clk_ddr(3)) THEN
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DDR_D_OUT_H := vdp_out(63 DOWNTO 32);
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DDR_D_OUT_L := vdp_out(31 DOWNTO 0);
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vd_en <= sr_ddr_wr OR ddr_wr;
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