diff --git a/sources/mmc.c b/sources/mmc.c
index 21494f9..3a8bb2f 100644
--- a/sources/mmc.c
+++ b/sources/mmc.c
@@ -23,7 +23,7 @@
 
 
 #define	CS_HIGH()	{ dspi_fifo_val &= ~MCF_DSPI_DTFR_CS5; }
-#define	CS_LOW()	{ dspi_fifo_val |= MCF_DSPI_DTFR_CS5; }
+#define	CS_LOW()		{ dspi_fifo_val |= MCF_DSPI_DTFR_CS5; }
 
 #define SPICLK_FAST() { MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) |	/* transfer size = 8 bit */ \
 					  MCF_DSPI_DCTAR_PCSSCK(0b01) |	/* 1 clock DSPICS to DSPISCK delay prescaler */ \
@@ -55,26 +55,26 @@
 
 
 /* MMC/SD command */
-#define CMD0	(0)			/* GO_IDLE_STATE */
-#define CMD1	(1)			/* SEND_OP_COND (MMC) */
-#define	ACMD41	(0x80+41)	/* SEND_OP_COND (SDC) */
-#define CMD8	(8)			/* SEND_IF_COND */
-#define CMD9	(9)			/* SEND_CSD */
-#define CMD10	(10)		/* SEND_CID */
-#define CMD12	(12)		/* STOP_TRANSMISSION */
-#define ACMD13	(0x80+13)	/* SD_STATUS (SDC) */
-#define CMD16	(16)		/* SET_BLOCKLEN */
-#define CMD17	(17)		/* READ_SINGLE_BLOCK */
-#define CMD18	(18)		/* READ_MULTIPLE_BLOCK */
-#define CMD23	(23)		/* SET_BLOCK_COUNT (MMC) */
-#define	ACMD23	(0x80+23)	/* SET_WR_BLK_ERASE_COUNT (SDC) */
-#define CMD24	(24)		/* WRITE_BLOCK */
-#define CMD25	(25)		/* WRITE_MULTIPLE_BLOCK */
-#define CMD32	(32)		/* ERASE_ER_BLK_START */
-#define CMD33	(33)		/* ERASE_ER_BLK_END */
-#define CMD38	(38)		/* ERASE */
-#define CMD55	(55)		/* APP_CMD */
-#define CMD58	(58)		/* READ_OCR */
+#define CMD0	(0)				/* GO_IDLE_STATE */
+#define CMD1	(1)				/* SEND_OP_COND (MMC) */
+#define ACMD41	(0x80+41)		/* SEND_OP_COND (SDC) */
+#define CMD8	(8)				/* SEND_IF_COND */
+#define CMD9	(9)				/* SEND_CSD */
+#define CMD10	(10)				/* SEND_CID */
+#define CMD12	(12)				/* STOP_TRANSMISSION */
+#define ACMD13	(0x80+13)		/* SD_STATUS (SDC) */
+#define CMD16	(16)				/* SET_BLOCKLEN */
+#define CMD17	(17)				/* READ_SINGLE_BLOCK */
+#define CMD18	(18)				/* READ_MULTIPLE_BLOCK */
+#define CMD23	(23)				/* SET_BLOCK_COUNT (MMC) */
+#define ACMD23	(0x80+23)		/* SET_WR_BLK_ERASE_COUNT (SDC) */
+#define CMD24	(24)				/* WRITE_BLOCK */
+#define CMD25	(25)				/* WRITE_MULTIPLE_BLOCK */
+#define CMD32	(32)				/* ERASE_ER_BLK_START */
+#define CMD33	(33)				/* ERASE_ER_BLK_END */
+#define CMD38	(38)				/* ERASE */
+#define CMD55	(55)				/* APP_CMD */
+#define CMD58	(58)				/* READ_OCR */
 
 
 static volatile DSTATUS Stat = 0 /* STA_NOINIT */;	/* Physical drive status */
@@ -99,7 +99,7 @@ static uint8_t xchg_spi(uint8_t byte)
 
 	MCF_DSPI_DTFR = fifo;
 	while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF));	/* wait until DSPI transfer complete */
-	MCF_DSPI_DSR = 0xffffffff;						/* clear DSPI status register */
+	MCF_DSPI_DSR = 0xffffffff;							/* clear DSPI status register */
 
 	fifo = MCF_DSPI_DRFR;
 
@@ -205,22 +205,22 @@ static void power_on (void)	/* Enable SSP module */
 	 * initialize DSPI module configuration register
 	 */
 	MCF_DSPI_DMCR = MCF_DSPI_DMCR_MSTR |	/* FireBee is DSPI master*/
-				MCF_DSPI_DMCR_CSIS5 |	/* CS5 inactive state high */
-				MCF_DSPI_DMCR_CSIS3 |	/* CS3 inactive state high */
-				MCF_DSPI_DMCR_CSIS2 |	/* CS2 inactive state high */
-				MCF_DSPI_DMCR_DTXF |	/* disable transmit FIFO */
-				MCF_DSPI_DMCR_DRXF |	/* disable receive FIFO */
-				MCF_DSPI_DMCR_CTXF |	/* clear transmit FIFO */
-				MCF_DSPI_DMCR_CRXF;		/* clear receive FIFO */
+				MCF_DSPI_DMCR_CSIS5 |			/* CS5 inactive state high */
+				MCF_DSPI_DMCR_CSIS3 |			/* CS3 inactive state high */
+				MCF_DSPI_DMCR_CSIS2 |			/* CS2 inactive state high */
+				MCF_DSPI_DMCR_DTXF |				/* disable transmit FIFO */
+				MCF_DSPI_DMCR_DRXF |				/* disable receive FIFO */
+				MCF_DSPI_DMCR_CTXF |				/* clear transmit FIFO */
+				MCF_DSPI_DMCR_CRXF;				/* clear receive FIFO */
 
 	/* initialize DSPI clock and transfer attributes register 0 */
-	MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) |	/* transfer size = 8 bit */
-					  MCF_DSPI_DCTAR_PCSSCK(0b01) |	/* 3 clock DSPICS to DSPISCK delay prescaler */
-					  MCF_DSPI_DCTAR_PASC_3CLK |	/* 3 clock DSPISCK to DSPICS negation prescaler */
-					  MCF_DSPI_DCTAR_PDT_3CLK |		/* 3 clock delay between DSPICS assertions prescaler */
-					  MCF_DSPI_DCTAR_PBR_3CLK |		/* 3 clock prescaler */
-					  MCF_DSPI_DCTAR_ASC(0b1001) |	/* 1024 */
-					  MCF_DSPI_DCTAR_DT(0b1001) |	/* 1024 */
+	MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) |		/* transfer size = 8 bit */
+					  MCF_DSPI_DCTAR_PCSSCK(0b01) |			/* 3 clock DSPICS to DSPISCK delay prescaler */
+					  MCF_DSPI_DCTAR_PASC_3CLK |				/* 3 clock DSPISCK to DSPICS negation prescaler */
+					  MCF_DSPI_DCTAR_PDT_3CLK |				/* 3 clock delay between DSPICS assertions prescaler */
+					  MCF_DSPI_DCTAR_PBR_3CLK |				/* 3 clock prescaler */
+					  MCF_DSPI_DCTAR_ASC(0b1001) |			/* 1024 */
+					  MCF_DSPI_DCTAR_DT(0b1001) |				/* 1024 */
 					  MCF_DSPI_DCTAR_BR(0b0111);
 
 	CS_HIGH();					/* Set CS# high */
diff --git a/sources/xhdi_sd.c b/sources/xhdi_sd.c
index 4a42cb4..787d6ee 100644
--- a/sources/xhdi_sd.c
+++ b/sources/xhdi_sd.c
@@ -136,7 +136,7 @@ uint32_t xhdi_read_write(uint16_t major, uint16_t minor, uint16_t rwflag,
 					retries++;
 					if (retries < max_retries) continue;
 
-					xprintf("error: %d\r\n", ret);
+					xprintf("SD card R/W error: %d\r\n", ret);
 					return ERROR;
 				}
 			} while (retries < max_retries && ret != RES_OK);