From 78d1969b75baf6956dd50f94a7596608e6a65e17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 20 Dec 2013 15:01:54 +0000 Subject: [PATCH] added dbug's fec and network routines --- Makefile | 4 +- dma/MCD_dmaApi.c | 89 +-- dma/MCD_tasks.c | 370 +++++------ dma/MCD_tasksInit.c | 274 ++++----- dma/dma.c | 55 +- include/MCD_dma.h | 118 ++-- include/arp.h | 99 +++ include/bas_types.h | 5 +- include/dma.h | 15 +- include/eth.h | 57 ++ include/fec.h | 164 +++++ include/fecbd.h | 99 +++ include/icmp.h | 121 ++++ include/interrupts.h | 19 + include/ip.h | 100 +++ include/nbuf.h | 85 +++ include/net.h | 32 + include/nif.h | 62 ++ include/queue.h | 53 ++ include/tftp.h | 158 +++++ include/udp.h | 61 ++ net/fec.c | 1390 ++++++++++++++++++++++++++++++++++++++++++ net/nbuf.c | 227 +++++++ 23 files changed, 3219 insertions(+), 438 deletions(-) create mode 100644 include/arp.h create mode 100644 include/eth.h create mode 100644 include/fec.h create mode 100644 include/fecbd.h create mode 100644 include/icmp.h create mode 100644 include/ip.h create mode 100644 include/nbuf.h create mode 100644 include/net.h create mode 100644 include/nif.h create mode 100644 include/queue.h create mode 100644 include/tftp.h create mode 100644 include/udp.h create mode 100644 net/fec.c create mode 100644 net/nbuf.c diff --git a/Makefile b/Makefile index 5772c56..5de21d4 100644 --- a/Makefile +++ b/Makefile @@ -43,7 +43,7 @@ TRGTDIRS= ./firebee ./m5484lite OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS)) TOOLDIR=util -VPATH=dma:exe:flash:fs:if:kbd:pci:spi:sys:usb:util:xhdi +VPATH=dma:exe:flash:fs:if:kbd:pci:spi:sys:usb:net:util:xhdi # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) LDCFILE=bas.lk @@ -93,6 +93,8 @@ CSRCS= \ \ ikbd.c \ \ + fec.c\ + \ basflash.c \ basflash_start.c diff --git a/dma/MCD_dmaApi.c b/dma/MCD_dmaApi.c index 5c1803a..d57a15d 100755 --- a/dma/MCD_dmaApi.c +++ b/dma/MCD_dmaApi.c @@ -8,6 +8,7 @@ #include "MCD_dma.h" #include "MCD_tasksInit.h" #include "MCD_progCheck.h" +#include "bas_types.h" /********************************************************************/ /* @@ -42,7 +43,7 @@ static int MCD_chStatus[NCHANNELS] = /* * Prototypes for local functions */ -static void MCD_memcpy(int *dest, int *src, u32 size); +static void MCD_memcpy(int *dest, int *src, uint32_t size); static void MCD_resmActions(int channel); /* @@ -115,9 +116,9 @@ struct MCD_remVariants_struct { int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ - s16 remDestIncr[NCHANNELS]; /* DestIncr */ - s16 remSrcIncr[NCHANNELS]; /* srcIncr */ - u32 remXferSize[NCHANNELS]; /* xferSize */ + int16_t remDestIncr[NCHANNELS]; /* DestIncr */ + int16_t remSrcIncr[NCHANNELS]; /* srcIncr */ + uint32_t remXferSize[NCHANNELS]; /* xferSize */ }; /* @@ -138,9 +139,9 @@ MCD_remVariant MCD_remVariants; * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned * MCD_OK otherwise */ -extern u32 MCD_funcDescTab0[]; +extern uint32_t MCD_funcDescTab0[]; -int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) +int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, uint32_t flags) { int i; TaskTableEntry *entryPtr; @@ -152,7 +153,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) if ((flags & MCD_RELOC_TASKS) != 0) { int fixedSize; - u32 *fixedPtr; + uint32_t *fixedPtr; /*int *tablePtr = taskTableDest;TBD*/ int varTabsOffset, funcDescTabsOffset, contextSavesOffset; int taskDescTabsOffset; @@ -162,7 +163,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) int i; /* check if physical address is aligned on 512 byte boundary */ - if (((u32) taskTableDest & 0x000001ff) != 0) + if (((uint32_t) taskTableDest & 0x000001ff) != 0) return (MCD_TABLE_UNALIGNED); MCD_taskTable = taskTableDest; /* set up local pointer to task Table */ @@ -178,7 +179,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) taskTableSize = NCHANNELS * sizeof(TaskTableEntry); /* align variable tables to size */ - varTabsOffset = taskTableSize + (u32) taskTableDest; + varTabsOffset = taskTableSize + (uint32_t) taskTableDest; if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE); /* align function descriptor tables */ @@ -196,7 +197,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) + contextSavesSize; /* zero the thing out */ - fixedPtr = (u32 *) taskTableDest; + fixedPtr = (uint32_t *) taskTableDest; for (i = 0; i < (fixedSize / 4); i++) fixedPtr[i] = 0; @@ -204,10 +205,10 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) /* set up fixed pointers */ for (i = 0; i < NCHANNELS; i++) { - entryPtr[i].varTab = (u32) varTabsOffset; /* update ptr to local value */ - entryPtr[i].FDTandFlags = (u32) funcDescTabsOffset + entryPtr[i].varTab = (uint32_t) varTabsOffset; /* update ptr to local value */ + entryPtr[i].FDTandFlags = (uint32_t) funcDescTabsOffset | MCD_TT_FLAGS_DEF; - entryPtr[i].contextSaveSpace = (u32) contextSavesOffset; + entryPtr[i].contextSaveSpace = (uint32_t) contextSavesOffset; varTabsOffset += VAR_TAB_SIZE; #ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */ funcDescTabsOffset += FUNCDESC_TAB_SIZE; @@ -229,7 +230,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) entryPtr = MCD_modelTaskTable; /* point to local version of model task table */ - taskDescTabsOffset = (u32) MCD_modelTaskTable + taskDescTabsOffset = (uint32_t) MCD_modelTaskTable + (NUMOFVARIANTS * sizeof(TaskTableEntry)); /* copy actual task code and update TDT ptrs in local model task table */ @@ -238,9 +239,9 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4; MCD_memcpy((void*) taskDescTabsOffset, (void*) entryPtr[i].TDTstart, taskDescTabSize); - entryPtr[i].TDTstart = (u32) taskDescTabsOffset; + entryPtr[i].TDTstart = (uint32_t) taskDescTabsOffset; taskDescTabsOffset += taskDescTabSize; - entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4; + entryPtr[i].TDTend = (uint32_t) taskDescTabsOffset - 4; } #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls where they are since DMA might write to them */ @@ -255,7 +256,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) /* point the would-be relocated task tables and the buffer descriptors to the ones the linker generated */ - if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0) + if (((uint32_t) MCD_realTaskTableSrc & 0x000001ff) != 0) return (MCD_TABLE_UNALIGNED); /* need to add code to make sure that every thing else is aligned properly TBD*/ @@ -276,7 +277,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) /* Make all channels as totally inactive, and remember them as such: */ - MCD_dmaBar->taskbar = (u32) MCD_taskTable; + MCD_dmaBar->taskbar = (uint32_t) MCD_taskTable; for (i = 0; i < NCHANNELS; i++) { MCD_dmaBar->taskControl[i] = 0x0; @@ -308,7 +309,7 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) */ int MCD_dmaStatus(int channel) { - u16 tcrValue; + uint16_t tcrValue; if ((channel < 0) || (channel >= NCHANNELS)) return (MCD_CHANNEL_INVALID); @@ -349,18 +350,18 @@ int MCD_dmaStatus(int channel) */ int MCD_startDma(int channel, /* the channel on which to run the DMA */ -s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ -s16 srcIncr, /* the amount to increment the source address per transfer */ -s8 *destAddr, /* the address to move data to */ -s16 destIncr, /* the amount to increment the destination address per transfer */ -u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ -u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ -u32 initiator, /* what device initiates the DMA */ +int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ +int16_t srcIncr, /* the amount to increment the source address per transfer */ +int8_t *destAddr, /* the address to move data to */ +int16_t destIncr, /* the amount to increment the destination address per transfer */ +uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */ +uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ +uint32_t initiator, /* what device initiates the DMA */ int priority, /* priority of the DMA */ -u32 flags, /* flags describing the DMA */ -u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +uint32_t flags, /* flags describing the DMA */ +uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ #ifdef MCD_NEED_ADDR_TRANS - s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/ + int8_t *srcAddrVirt /* virtual buffer descriptor address TBD*/ #endif ) { @@ -369,7 +370,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ short xferSizeIncr; int tcrCount = 0; #ifdef MCD_INCLUDE_EU - u32 *realFuncArray; + uint32_t *realFuncArray; #endif if ((channel < 0) || (channel >= NCHANNELS)) @@ -389,7 +390,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ since the register involved is in the same longword as other registers that users are in control of, setting it more than once is probably preferable. That since the documentation doesn't seem to be completely consistent about the nature of the PTD control register. */ - MCD_dmaBar->ptdControl |= (u16) 0x8000; + MCD_dmaBar->ptdControl |= (uint16_t) 0x8000; #if 1 /* Not sure what we need to keep here rtm TBD */ /* Calculate additional parameters to the regular DMA calls. */ srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); @@ -409,7 +410,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ + CURRBD; #ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */ - realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); + realFuncArray = (uint32_t *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */ realFuncArray[(LURC*16)] = xferSize == 4 ? funcDesc : xferSize == 2 ? @@ -434,7 +435,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; } - MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK; + MCD_dmaBar->priority[channel] = (uint8_t) priority & PRIORITY_PRI_MASK; /* should be albe to handle this stuff with only one write to ts reg - tbd */ if (channel < 8 && channel >= 0) { @@ -492,7 +493,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ ((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; ((volatile int *) MCD_taskTable[channel].contextSaveSpace)[CURRBD - + CSAVE_OFFSET] = (u32) &(MCD_relocBuffDesc[channel]); + + CSAVE_OFFSET] = (uint32_t) &(MCD_relocBuffDesc[channel]); /* tbd - need to keep the user from trying to call the EU routine when MCD_INCLUDE_EU is not defined */ if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) @@ -536,7 +537,7 @@ u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ ((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; ((volatile int *) MCD_taskTable[channel].contextSaveSpace)[CURRBD - + CSAVE_OFFSET] = (u32) srcAddr; + + CSAVE_OFFSET] = (uint32_t) srcAddr; if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) { @@ -605,7 +606,7 @@ int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) int destDiffBytes; /* Total number of bytes that we think actually got xfered. */ int numIterations; /* number of iterations */ int bytesNotXfered; /* bytes that did not get xfered. */ - s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; + int8_t *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; int subModVal, addModVal; /* Mode values to added and subtracted from the final destAddr */ @@ -614,10 +615,10 @@ int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) /* Read a trial value for the progress-reporting values*/ prevRep.lastSrcAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + (int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; prevRep.lastDestAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + (int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT @@ -633,10 +634,10 @@ int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */ /* Check them again: */ progRep->lastSrcAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + (int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; progRep->lastDestAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + (int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT @@ -739,7 +740,7 @@ int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) */ static void MCD_resmActions(int channel) { - u32 debugStatus; + uint32_t debugStatus; MCD_dmaBar->debugControl = DBG_CTL_DISABLE; debugStatus = MCD_dmaBar->debugStatus; @@ -907,7 +908,7 @@ int MCD_resumeDma(int channel) * Notes: * */ -int MCD_csumQuery(int channel, u32 *csum) +int MCD_csumQuery(int channel, uint32_t *csum) { #ifdef MCD_INCLUDE_EU if((channel < 0) || (channel >= NCHANNELS)) @@ -958,9 +959,9 @@ int MCD_getVersion(char **longVersion) /* Private version of memcpy() * Note that everything this is used for is longword-aligned. */ -static void MCD_memcpy(int *dest, int *src, u32 size) +static void MCD_memcpy(int *dest, int *src, uint32_t size) { - u32 i; + uint32_t i; for (i = 0; i < size; i += sizeof(int), dest++, src++) *dest = *src; diff --git a/dma/MCD_tasks.c b/dma/MCD_tasks.c index 76e8e37..ded6ff3 100755 --- a/dma/MCD_tasks.c +++ b/dma/MCD_tasks.c @@ -7,253 +7,253 @@ #include "MCD_dma.h" -u32 MCD_varTab0[]; -u32 MCD_varTab1[]; -u32 MCD_varTab2[]; -u32 MCD_varTab3[]; -u32 MCD_varTab4[]; -u32 MCD_varTab5[]; -u32 MCD_varTab6[]; -u32 MCD_varTab7[]; -u32 MCD_varTab8[]; -u32 MCD_varTab9[]; -u32 MCD_varTab10[]; -u32 MCD_varTab11[]; -u32 MCD_varTab12[]; -u32 MCD_varTab13[]; -u32 MCD_varTab14[]; -u32 MCD_varTab15[]; +uint32_t MCD_varTab0[]; +uint32_t MCD_varTab1[]; +uint32_t MCD_varTab2[]; +uint32_t MCD_varTab3[]; +uint32_t MCD_varTab4[]; +uint32_t MCD_varTab5[]; +uint32_t MCD_varTab6[]; +uint32_t MCD_varTab7[]; +uint32_t MCD_varTab8[]; +uint32_t MCD_varTab9[]; +uint32_t MCD_varTab10[]; +uint32_t MCD_varTab11[]; +uint32_t MCD_varTab12[]; +uint32_t MCD_varTab13[]; +uint32_t MCD_varTab14[]; +uint32_t MCD_varTab15[]; -u32 MCD_funcDescTab0[]; +uint32_t MCD_funcDescTab0[]; #ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]; -u32 MCD_funcDescTab2[]; -u32 MCD_funcDescTab3[]; -u32 MCD_funcDescTab4[]; -u32 MCD_funcDescTab5[]; -u32 MCD_funcDescTab6[]; -u32 MCD_funcDescTab7[]; -u32 MCD_funcDescTab8[]; -u32 MCD_funcDescTab9[]; -u32 MCD_funcDescTab10[]; -u32 MCD_funcDescTab11[]; -u32 MCD_funcDescTab12[]; -u32 MCD_funcDescTab13[]; -u32 MCD_funcDescTab14[]; -u32 MCD_funcDescTab15[]; +uint32_t MCD_funcDescTab1[]; +uint32_t MCD_funcDescTab2[]; +uint32_t MCD_funcDescTab3[]; +uint32_t MCD_funcDescTab4[]; +uint32_t MCD_funcDescTab5[]; +uint32_t MCD_funcDescTab6[]; +uint32_t MCD_funcDescTab7[]; +uint32_t MCD_funcDescTab8[]; +uint32_t MCD_funcDescTab9[]; +uint32_t MCD_funcDescTab10[]; +uint32_t MCD_funcDescTab11[]; +uint32_t MCD_funcDescTab12[]; +uint32_t MCD_funcDescTab13[]; +uint32_t MCD_funcDescTab14[]; +uint32_t MCD_funcDescTab15[]; #endif -u32 MCD_contextSave0[]; -u32 MCD_contextSave1[]; -u32 MCD_contextSave2[]; -u32 MCD_contextSave3[]; -u32 MCD_contextSave4[]; -u32 MCD_contextSave5[]; -u32 MCD_contextSave6[]; -u32 MCD_contextSave7[]; -u32 MCD_contextSave8[]; -u32 MCD_contextSave9[]; -u32 MCD_contextSave10[]; -u32 MCD_contextSave11[]; -u32 MCD_contextSave12[]; -u32 MCD_contextSave13[]; -u32 MCD_contextSave14[]; -u32 MCD_contextSave15[]; +uint32_t MCD_contextSave0[]; +uint32_t MCD_contextSave1[]; +uint32_t MCD_contextSave2[]; +uint32_t MCD_contextSave3[]; +uint32_t MCD_contextSave4[]; +uint32_t MCD_contextSave5[]; +uint32_t MCD_contextSave6[]; +uint32_t MCD_contextSave7[]; +uint32_t MCD_contextSave8[]; +uint32_t MCD_contextSave9[]; +uint32_t MCD_contextSave10[]; +uint32_t MCD_contextSave11[]; +uint32_t MCD_contextSave12[]; +uint32_t MCD_contextSave13[]; +uint32_t MCD_contextSave14[]; +uint32_t MCD_contextSave15[]; -u32 MCD_realTaskTableSrc[] = +uint32_t MCD_realTaskTableSrc[] = { 0x00000000, 0x00000000, - (u32)MCD_varTab0, /* Task 0 Variable Table */ - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_varTab0, /* Task 0 Variable Table */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ 0x00000000, 0x00000000, - (u32)MCD_contextSave0, /* Task 0 context save space */ + (uint32_t)MCD_contextSave0, /* Task 0 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab1, /* Task 1 Variable Table */ + (uint32_t)MCD_varTab1, /* Task 1 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave1, /* Task 1 context save space */ + (uint32_t)MCD_contextSave1, /* Task 1 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab2, /* Task 2 Variable Table */ + (uint32_t)MCD_varTab2, /* Task 2 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave2, /* Task 2 context save space */ + (uint32_t)MCD_contextSave2, /* Task 2 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab3, /* Task 3 Variable Table */ + (uint32_t)MCD_varTab3, /* Task 3 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave3, /* Task 3 context save space */ + (uint32_t)MCD_contextSave3, /* Task 3 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab4, /* Task 4 Variable Table */ + (uint32_t)MCD_varTab4, /* Task 4 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave4, /* Task 4 context save space */ + (uint32_t)MCD_contextSave4, /* Task 4 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab5, /* Task 5 Variable Table */ + (uint32_t)MCD_varTab5, /* Task 5 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave5, /* Task 5 context save space */ + (uint32_t)MCD_contextSave5, /* Task 5 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab6, /* Task 6 Variable Table */ + (uint32_t)MCD_varTab6, /* Task 6 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave6, /* Task 6 context save space */ + (uint32_t)MCD_contextSave6, /* Task 6 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab7, /* Task 7 Variable Table */ + (uint32_t)MCD_varTab7, /* Task 7 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave7, /* Task 7 context save space */ + (uint32_t)MCD_contextSave7, /* Task 7 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab8, /* Task 8 Variable Table */ + (uint32_t)MCD_varTab8, /* Task 8 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave8, /* Task 8 context save space */ + (uint32_t)MCD_contextSave8, /* Task 8 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab9, /* Task 9 Variable Table */ + (uint32_t)MCD_varTab9, /* Task 9 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave9, /* Task 9 context save space */ + (uint32_t)MCD_contextSave9, /* Task 9 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab10, /* Task 10 Variable Table */ + (uint32_t)MCD_varTab10, /* Task 10 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave10, /* Task 10 context save space */ + (uint32_t)MCD_contextSave10, /* Task 10 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab11, /* Task 11 Variable Table */ + (uint32_t)MCD_varTab11, /* Task 11 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave11, /* Task 11 context save space */ + (uint32_t)MCD_contextSave11, /* Task 11 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab12, /* Task 12 Variable Table */ + (uint32_t)MCD_varTab12, /* Task 12 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave12, /* Task 12 context save space */ + (uint32_t)MCD_contextSave12, /* Task 12 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab13, /* Task 13 Variable Table */ + (uint32_t)MCD_varTab13, /* Task 13 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave13, /* Task 13 context save space */ + (uint32_t)MCD_contextSave13, /* Task 13 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab14, /* Task 14 Variable Table */ + (uint32_t)MCD_varTab14, /* Task 14 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave14, /* Task 14 context save space */ + (uint32_t)MCD_contextSave14, /* Task 14 context save space */ 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_varTab15, /* Task 15 Variable Table */ + (uint32_t)MCD_varTab15, /* Task 15 Variable Table */ #ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ #else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + (uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ #endif 0x00000000, 0x00000000, - (u32)MCD_contextSave15, /* Task 15 context save space */ + (uint32_t)MCD_contextSave15, /* Task 15 context save space */ 0x00000000, }; -u32 MCD_varTab0[] = +uint32_t MCD_varTab0[] = { /* Task 0 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -290,7 +290,7 @@ u32 MCD_varTab0[] = }; -u32 MCD_varTab1[] = +uint32_t MCD_varTab1[] = { /* Task 1 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -326,7 +326,7 @@ u32 MCD_varTab1[] = 0x00000000, /* inc[7] */ }; -u32 MCD_varTab2[]= +uint32_t MCD_varTab2[]= { /* Task 2 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -362,7 +362,7 @@ u32 MCD_varTab2[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab3[]= +uint32_t MCD_varTab3[]= { /* Task 3 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -398,7 +398,7 @@ u32 MCD_varTab3[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab4[]= +uint32_t MCD_varTab4[]= { /* Task 4 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -434,7 +434,7 @@ u32 MCD_varTab4[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab5[]= +uint32_t MCD_varTab5[]= { /* Task 5 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -470,7 +470,7 @@ u32 MCD_varTab5[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab6[]= +uint32_t MCD_varTab6[]= { /* Task 6 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -506,7 +506,7 @@ u32 MCD_varTab6[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab7[]= +uint32_t MCD_varTab7[]= { /* Task 7 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -542,7 +542,7 @@ u32 MCD_varTab7[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab8[]= +uint32_t MCD_varTab8[]= { /* Task 8 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -578,7 +578,7 @@ u32 MCD_varTab8[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab9[]= +uint32_t MCD_varTab9[]= { /* Task 9 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -614,7 +614,7 @@ u32 MCD_varTab9[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab10[]= +uint32_t MCD_varTab10[]= { /* Task 10 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -650,7 +650,7 @@ u32 MCD_varTab10[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab11[]= +uint32_t MCD_varTab11[]= { /* Task 11 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -686,7 +686,7 @@ u32 MCD_varTab11[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab12[]= +uint32_t MCD_varTab12[]= { /* Task 12 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -722,7 +722,7 @@ u32 MCD_varTab12[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab13[]= +uint32_t MCD_varTab13[]= { /* Task 13 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -758,7 +758,7 @@ u32 MCD_varTab13[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab14[]= +uint32_t MCD_varTab14[]= { /* Task 14 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -794,7 +794,7 @@ u32 MCD_varTab14[]= 0x00000000, /* inc[7] */ }; -u32 MCD_varTab15[]= +uint32_t MCD_varTab15[]= { /* Task 15 Variable Table */ 0x00000000, /* var[0] */ 0x00000000, /* var[1] */ @@ -830,7 +830,7 @@ u32 MCD_varTab15[]= 0x00000000, /* inc[7] */ }; -u32 MCD_funcDescTab0[]= +uint32_t MCD_funcDescTab0[]= { /* Task 0 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -899,7 +899,7 @@ u32 MCD_funcDescTab0[]= }; #ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]= +uint32_t MCD_funcDescTab1[]= { /* Task 1 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -967,7 +967,7 @@ u32 MCD_funcDescTab1[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab2[]= +uint32_t MCD_funcDescTab2[]= { /* Task 2 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1035,7 +1035,7 @@ u32 MCD_funcDescTab2[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab3[]= +uint32_t MCD_funcDescTab3[]= { /* Task 3 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1103,7 +1103,7 @@ u32 MCD_funcDescTab3[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab4[]= +uint32_t MCD_funcDescTab4[]= { /* Task 4 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1171,7 +1171,7 @@ u32 MCD_funcDescTab4[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab5[]= +uint32_t MCD_funcDescTab5[]= { /* Task 5 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1239,7 +1239,7 @@ u32 MCD_funcDescTab5[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab6[]= +uint32_t MCD_funcDescTab6[]= { /* Task 6 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1307,7 +1307,7 @@ u32 MCD_funcDescTab6[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab7[]= +uint32_t MCD_funcDescTab7[]= { /* Task 7 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1375,7 +1375,7 @@ u32 MCD_funcDescTab7[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab8[]= +uint32_t MCD_funcDescTab8[]= { /* Task 8 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1443,7 +1443,7 @@ u32 MCD_funcDescTab8[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab9[]= +uint32_t MCD_funcDescTab9[]= { /* Task 9 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1511,7 +1511,7 @@ u32 MCD_funcDescTab9[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab10[]= +uint32_t MCD_funcDescTab10[]= { /* Task 10 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1579,7 +1579,7 @@ u32 MCD_funcDescTab10[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab11[]= +uint32_t MCD_funcDescTab11[]= { /* Task 11 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1647,7 +1647,7 @@ u32 MCD_funcDescTab11[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab12[]= +uint32_t MCD_funcDescTab12[]= { /* Task 12 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1715,7 +1715,7 @@ u32 MCD_funcDescTab12[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab13[]= +uint32_t MCD_funcDescTab13[]= { /* Task 13 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1783,7 +1783,7 @@ u32 MCD_funcDescTab13[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab14[]= +uint32_t MCD_funcDescTab14[]= { /* Task 14 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1851,7 +1851,7 @@ u32 MCD_funcDescTab14[]= 0x202f2000, /* andCrcRestartBit(), EU# 3 */ }; -u32 MCD_funcDescTab15[]= +uint32_t MCD_funcDescTab15[]= { /* Task 15 Function Descriptor Table */ 0x00000000, 0x00000000, @@ -1920,45 +1920,45 @@ u32 MCD_funcDescTab15[]= }; #endif /*MCD_INCLUDE_EU*/ -u32 MCD_contextSave0[128]; /* Task 0 context save space */ -u32 MCD_contextSave1[128]; /* Task 1 context save space */ -u32 MCD_contextSave2[128]; /* Task 2 context save space */ -u32 MCD_contextSave3[128]; /* Task 3 context save space */ -u32 MCD_contextSave4[128]; /* Task 4 context save space */ -u32 MCD_contextSave5[128]; /* Task 5 context save space */ -u32 MCD_contextSave6[128]; /* Task 6 context save space */ -u32 MCD_contextSave7[128]; /* Task 7 context save space */ -u32 MCD_contextSave8[128]; /* Task 8 context save space */ -u32 MCD_contextSave9[128]; /* Task 9 context save space */ -u32 MCD_contextSave10[128]; /* Task 10 context save space */ -u32 MCD_contextSave11[128]; /* Task 11 context save space */ -u32 MCD_contextSave12[128]; /* Task 12 context save space */ -u32 MCD_contextSave13[128]; /* Task 13 context save space */ -u32 MCD_contextSave14[128]; /* Task 14 context save space */ -u32 MCD_contextSave15[128]; /* Task 15 context save space */ +uint32_t MCD_contextSave0[128]; /* Task 0 context save space */ +uint32_t MCD_contextSave1[128]; /* Task 1 context save space */ +uint32_t MCD_contextSave2[128]; /* Task 2 context save space */ +uint32_t MCD_contextSave3[128]; /* Task 3 context save space */ +uint32_t MCD_contextSave4[128]; /* Task 4 context save space */ +uint32_t MCD_contextSave5[128]; /* Task 5 context save space */ +uint32_t MCD_contextSave6[128]; /* Task 6 context save space */ +uint32_t MCD_contextSave7[128]; /* Task 7 context save space */ +uint32_t MCD_contextSave8[128]; /* Task 8 context save space */ +uint32_t MCD_contextSave9[128]; /* Task 9 context save space */ +uint32_t MCD_contextSave10[128]; /* Task 10 context save space */ +uint32_t MCD_contextSave11[128]; /* Task 11 context save space */ +uint32_t MCD_contextSave12[128]; /* Task 12 context save space */ +uint32_t MCD_contextSave13[128]; /* Task 13 context save space */ +uint32_t MCD_contextSave14[128]; /* Task 14 context save space */ +uint32_t MCD_contextSave15[128]; /* Task 15 context save space */ -u32 MCD_ChainNoEu_TDT[]; -u32 MCD_SingleNoEu_TDT[]; +uint32_t MCD_ChainNoEu_TDT[]; +uint32_t MCD_SingleNoEu_TDT[]; #ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]; -u32 MCD_SingleEu_TDT[]; +uint32_t MCD_ChainEu_TDT[]; +uint32_t MCD_SingleEu_TDT[]; #endif -u32 MCD_ENetRcv_TDT[]; -u32 MCD_ENetXmit_TDT[]; +uint32_t MCD_ENetRcv_TDT[]; +uint32_t MCD_ENetXmit_TDT[]; -u32 MCD_modelTaskTableSrc[]= +uint32_t MCD_modelTaskTableSrc[]= { - (u32)MCD_ChainNoEu_TDT, - (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c], + (uint32_t)MCD_ChainNoEu_TDT, + (uint32_t)&((uint8_t*)MCD_ChainNoEu_TDT)[0x0000016c], 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_SingleNoEu_TDT, - (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4], + (uint32_t)MCD_SingleNoEu_TDT, + (uint32_t)&((uint8_t*)MCD_SingleNoEu_TDT)[0x000000d4], 0x00000000, 0x00000000, 0x00000000, @@ -1966,16 +1966,16 @@ u32 MCD_modelTaskTableSrc[]= 0x00000000, 0x00000000, #ifdef MCD_INCLUDE_EU - (u32)MCD_ChainEu_TDT, - (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4], + (uint32_t)MCD_ChainEu_TDT, + (uint32_t)&((uint8_t*)MCD_ChainEu_TDT)[0x000001b4], 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_SingleEu_TDT, - (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124], + (uint32_t)MCD_SingleEu_TDT, + (uint32_t)&((uint8_t*)MCD_SingleEu_TDT)[0x00000124], 0x00000000, 0x00000000, 0x00000000, @@ -1983,16 +1983,16 @@ u32 MCD_modelTaskTableSrc[]= 0x00000000, 0x00000000, #endif - (u32)MCD_ENetRcv_TDT, - (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c], + (uint32_t)MCD_ENetRcv_TDT, + (uint32_t)&((uint8_t*)MCD_ENetRcv_TDT)[0x0000009c], 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - (u32)MCD_ENetXmit_TDT, - (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0], + (uint32_t)MCD_ENetXmit_TDT, + (uint32_t)&((uint8_t*)MCD_ENetXmit_TDT)[0x000000d0], 0x00000000, 0x00000000, 0x00000000, @@ -2000,7 +2000,7 @@ u32 MCD_modelTaskTableSrc[]= 0x00000000, 0x00000000, }; -u32 MCD_ChainNoEu_TDT[]= +uint32_t MCD_ChainNoEu_TDT[]= { 0x80004000, /* 0000(:370): LCDEXT: idx0 = 0x00000000; ; */ 0x8118801b, /* 0004(:370): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ @@ -2095,7 +2095,7 @@ u32 MCD_ChainNoEu_TDT[]= 0x000001f8, /* 0168(:0): NOP */ 0x000001f8, /* 016C(:0): NOP */ }; -u32 MCD_SingleNoEu_TDT[]= +uint32_t MCD_SingleNoEu_TDT[]= { 0x8198001b, /* 0000(:657): LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */ 0x7000000d, /* 0004(:658): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ @@ -2153,7 +2153,7 @@ u32 MCD_SingleNoEu_TDT[]= 0x040001f8, /* 00D4(:713): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ }; #ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]= +uint32_t MCD_ChainEu_TDT[]= { 0x80004000, /* 0000(:947): LCDEXT: idx0 = 0x00000000; ; */ 0x8198801b, /* 0004(:947): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ @@ -2266,7 +2266,7 @@ u32 MCD_ChainEu_TDT[]= 0x000001f8, /* 01B0(:0): NOP */ 0x000001f8, /* 01B4(:0): NOP */ }; -u32 MCD_SingleEu_TDT[]= +uint32_t MCD_SingleEu_TDT[]= { 0x8218001b, /* 0000(:1248): LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */ 0x7000000d, /* 0004(:1249): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ @@ -2344,7 +2344,7 @@ u32 MCD_SingleEu_TDT[]= 0x040001f8, /* 0124(:1316): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ }; #endif -u32 MCD_ENetRcv_TDT[]= +uint32_t MCD_ENetRcv_TDT[]= { 0x80004000, /* 0000(:1389): LCDEXT: idx0 = 0x00000000; ; */ 0x81988000, /* 0004(:1389): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ @@ -2387,7 +2387,7 @@ u32 MCD_ENetRcv_TDT[]= 0x040001f8, /* 0098(:1441): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ 0x000001f8, /* 009C(:0): NOP */ }; -u32 MCD_ENetXmit_TDT[]= +uint32_t MCD_ENetXmit_TDT[]= { 0x80004000, /* 0000(:1516): LCDEXT: idx0 = 0x00000000; ; */ 0x81988000, /* 0004(:1516): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ diff --git a/dma/MCD_tasksInit.c b/dma/MCD_tasksInit.c index 58ab8ce..fd4ec2a 100755 --- a/dma/MCD_tasksInit.c +++ b/dma/MCD_tasksInit.c @@ -23,33 +23,33 @@ extern dmaRegs *MCD_dmaBar; void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xferSize); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)0x00000000); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x80000000); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x00000010); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x08000000); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000001); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x40000000); /* inc[6] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } @@ -60,26 +60,26 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)destAddr); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)dmaSize); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)flags); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)currBD); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000004); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x08000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000001); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x40000000); /* inc[5] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } @@ -90,36 +90,36 @@ void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */ - MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 12, (uint32_t)xferSize); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000000); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x00000000); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x80000000); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000010); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000001); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 17, (uint32_t)0x00000004); /* var[17] */ + MCD_SET_VAR(taskTable+channel, 18, (uint32_t)0x08000000); /* var[18] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0xc0000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000); /* inc[7] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } @@ -130,30 +130,30 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)destAddr); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)dmaSize); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)flags); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000001); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000004); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x08000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xc0000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000); /* inc[7] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } @@ -164,26 +164,26 @@ void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short d void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)rcvFifoPtr); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x0000ffff); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x30000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x0fffffff); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000008); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x20000004); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x40000000); /* inc[3] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } @@ -194,32 +194,32 @@ void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) { - MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */ + MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xmitFifoPtr); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x0000ffff); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0xffffffff); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000008); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x40000000); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0xc000fffc); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xe0000004); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x4000ffff); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0xe0000001); /* inc[7] */ /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; + MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000; } diff --git a/dma/dma.c b/dma/dma.c index 89d5860..97f4315 100644 --- a/dma/dma.c +++ b/dma/dma.c @@ -37,12 +37,61 @@ extern char _SYS_SRAM[]; #define SYS_SRAM &_SYS_SRAM[0] -void print_sp(void) +struct dma_channel { - register char *sp asm("sp"); - xprintf("sp=%x\r\n", sp); + int req; + void (*handler)(void); +}; + +static struct dma_channel dma_channel[NCHANNELS] = +{ + {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, + {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, + {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, + {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, +}; + +/* + * return the channel being initiated by the given requestor + */ +int dma_get_channel(int requestor) +{ + int i; + + for (i = 0; i < NCHANNELS; i++) + { + if (dma_channel[i].req == requestor) + { + return i; + } + } + return -1; } +int dma_set_channel(int requestor, void (*handler)(void)) +{ + int i; + + /* check to see if requestor is already assigned to a channel */ + if ((i = dma_get_channel(requestor)) != -1) + { + return i; + } + + for (i = 0; i < NCHANNELS; i++) + { + if (dma_channel[i].req == -1) + { + dma_channel[i].req = requestor; + dma_channel[i].handler = handler; + + return i; + } + } + + /* all channels taken */ + return -1; +} void *dma_memcpy(void *dst, void *src, size_t n) { diff --git a/include/MCD_dma.h b/include/MCD_dma.h index 1506fff..02a1cc7 100755 --- a/include/MCD_dma.h +++ b/include/MCD_dma.h @@ -7,6 +7,8 @@ #ifndef _MCD_API_H #define _MCD_API_H +#include "bas_types.h" + /* * Turn Execution Unit tasks ON (#define) or OFF (#undef) */ @@ -47,39 +49,33 @@ /* * Portability typedefs */ -typedef int s32; -typedef unsigned int u32; -typedef short s16; -typedef unsigned short u16; -typedef char s8; -typedef unsigned char u8; /* * These structures represent the internal registers of the * multi-channel DMA */ struct dmaRegs_s { - u32 taskbar; /* task table base address register */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending register */ - u32 intMask; /* interrupt mask register */ - u16 taskControl[16]; /* task control registers */ - u8 priority[32]; /* priority registers */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control register 0. */ - u32 taskSize1; /* task size control register 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ + uint32_t taskbar; /* task table base address register */ + uint32_t currPtr; + uint32_t endPtr; + uint32_t varTablePtr; + uint16_t dma_rsvd0; + uint16_t ptdControl; /* ptd control */ + uint32_t intPending; /* interrupt pending register */ + uint32_t intMask; /* interrupt mask register */ + uint16_t taskControl[16]; /* task control registers */ + uint8_t priority[32]; /* priority registers */ + uint32_t initiatorMux; /* initiator mux control */ + uint32_t taskSize0; /* task size control register 0. */ + uint32_t taskSize1; /* task size control register 1. */ + uint32_t dma_rsvd1; /* reserved */ + uint32_t dma_rsvd2; /* reserved */ + uint32_t debugComp1; /* debug comparator 1 */ + uint32_t debugComp2; /* debug comparator 2 */ + uint32_t debugControl; /* debug control */ + uint32_t debugStatus; /* debug status */ + uint32_t ptdDebug; /* priority task decode debug */ + uint32_t dma_rsvd3[31]; /* reserved */ }; typedef volatile struct dmaRegs_s dmaRegs; @@ -165,7 +161,7 @@ typedef volatile struct dmaRegs_s dmaRegs; */ /* Byte swapping: */ #define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ -#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ +#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each uint32_t of the DMAed data. */ #define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of each 32-bit data value being DMAed.*/ #define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each @@ -232,44 +228,44 @@ typedef volatile struct dmaRegs_s dmaRegs; /* Task Table Entry struct*/ typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start and flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; + uint32_t TDTstart; /* task descriptor table start */ + uint32_t TDTend; /* task descriptor table end */ + uint32_t varTab; /* variable table start */ + uint32_t FDTandFlags; /* function descriptor table start and flags */ + volatile uint32_t descAddrAndStatus; + volatile uint32_t modifiedVarTab; + uint32_t contextSaveSpace; /* context save space start */ + uint32_t literalBases; } TaskTableEntry; /* Chained buffer descriptor */ typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; struct MCD_bufDesc_struct { - u32 flags; /* flags describing the DMA */ - u32 csumResult; /* checksum from checksumming performed since last checksum reset */ - s8 *srcAddr; /* the address to move data from */ - s8 *destAddr; /* the address to move data to */ - s8 *lastDestAddr; /* the last address written to */ - u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ + uint32_t flags; /* flags describing the DMA */ + uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */ + int8_t *srcAddr; /* the address to move data from */ + int8_t *destAddr; /* the address to move data to */ + int8_t *lastDestAddr; /* the last address written to */ + uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */ MCD_bufDesc *next; /* next buffer descriptor in chain */ - u32 info; /* private information about this descriptor; DMA does not affect it */ + uint32_t info; /* private information about this descriptor; DMA does not affect it */ }; /* Progress Query struct */ typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ - s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ - u32 dmaSize; /* the amount of data transferred for the current buffer */ + int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */ + int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */ + uint32_t dmaSize; /* the amount of data transferred for the current buffer */ MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ } MCD_XferProg; /* FEC buffer descriptor */ typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; + uint16_t statCtrl; + uint16_t length; + uint32_t dataPointer; } MCD_bufDescFec; @@ -283,16 +279,16 @@ typedef volatile struct MCD_bufDescFec_struct { */ int MCD_startDma ( int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, /* the amount to increment the destination address per transfer */ - u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ + int8_t *srcAddr, /* the address to move data from, or buffer-descriptor address */ + int16_t srcIncr, /* the amount to increment the source address per transfer */ + int8_t *destAddr, /* the address to move data to */ + int16_t destIncr, /* the amount to increment the destination address per transfer */ + uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */ + uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ + uint32_t initiator, /* what device initiates the DMA */ int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ + uint32_t flags, /* flags describing the DMA */ + uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ ); /* @@ -300,7 +296,7 @@ int MCD_startDma ( * registers, relocating and creating the appropriate task structures, and * setting up some global settings */ -int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, uint32_t flags); /* * MCD_dmaStatus() returns the status of the DMA on the requested channel. @@ -339,7 +335,7 @@ int MCD_resumeDma (int channel); /* * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */ -int MCD_csumQuery (int channel, u32 *csum); +int MCD_csumQuery (int channel, uint32_t *csum); /* * MCD_getCodeSize provides the packed size required by the microcoded task @@ -354,7 +350,7 @@ int MCD_getCodeSize(void); int MCD_getVersion(char **longVersion); /* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value +#define MCD_SET_VAR(taskTab,idx,value) ((uint32_t *)(taskTab)->varTab)[idx] = value /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, so I'm avoiding surrounding it with "do {} while(0)" */ diff --git a/include/arp.h b/include/arp.h new file mode 100644 index 0000000..d4f78e9 --- /dev/null +++ b/include/arp.h @@ -0,0 +1,99 @@ +/* + * File: arp.h + * Purpose: ARP definitions. + * + * Notes: + */ + +#ifndef _ARP_H +#define _ARP_H + +/********************************************************************/ + +/* + * This data definition is defined for Ethernet only! + */ +typedef struct +{ + uint16_t ar_hrd; + uint16_t ar_pro; + uint8_t ar_hln; + uint8_t ar_pln; + uint16_t opcode; + uint8_t ar_sha[6]; /* ethernet hw address */ + uint8_t ar_spa[4]; /* ip address */ + uint8_t ar_tha[6]; /* ethernet hw address */ + uint8_t ar_tpa[4]; /* ip address */ +} arp_frame_hdr; + +#define ARP_HDR_LEN sizeof(arp_frame_hdr) + +/* + * ARP table entry definition. Note that this table only designed + * with Ethernet and IP in mind. + */ +#define MAX_HWA_SIZE (6) /* 6 is enough for Ethernet address */ +#define MAX_PA_SIZE (4) /* 4 is enough for Protocol address */ +typedef struct +{ + uint16_t protocol; + uint8_t hwa_size; + uint8_t hwa[MAX_HWA_SIZE]; + uint8_t pa_size; + uint8_t pa[MAX_PA_SIZE]; + int longevity; +} ARPENTRY; +#define MAX_ARP_ENTRY (10) + +typedef struct +{ + unsigned int tab_size; + ARPENTRY table[MAX_ARP_ENTRY]; +} ARP_INFO; + +#define ARP_ENTRY_EMPTY (0) +#define ARP_ENTRY_PERM (1) +#define ARP_ENTRY_TEMP (2) + + +#define ETHERNET (1) +#define ARP_REQUEST (1) +#define ARP_REPLY (2) + +#define ARP_TIMEOUT (1) /* Timeout in seconds */ + +/* Protocol Header information */ +#define ARP_HDR_OFFSET ETH_HDR_LEN + +/********************************************************************/ + +uint8_t * +arp_get_mypa (void); + +uint8_t * +arp_get_myha (void); + +uint8_t * +arp_get_broadcast (void); + +void +arp_merge (ARP_INFO *, uint16_t, int, uint8_t *, int, uint8_t *, int); + +void +arp_remove (ARP_INFO *, uint16_t, uint8_t *, uint8_t *); + +void +arp_request (NIF *, uint8_t *); + +void +arp_handler (NIF *, NBUF *); + +uint8_t * +arp_resolve (NIF *, uint16_t, uint8_t *); + +void +arp_init (ARP_INFO *); + +/********************************************************************/ + +#endif /* _ARP_H */ diff --git a/include/bas_types.h b/include/bas_types.h index a77d287..c7e219c 100644 --- a/include/bas_types.h +++ b/include/bas_types.h @@ -28,10 +28,7 @@ #ifndef BAS_TYPES_H_ #define BAS_TYPES_H_ -#ifndef __cplusplus +#include #include -#endif /* __cplusplus */ - - #endif /* BAS_TYPES_H_ */ diff --git a/include/dma.h b/include/dma.h index 0eea4ec..4edcc95 100644 --- a/include/dma.h +++ b/include/dma.h @@ -20,12 +20,21 @@ * Author: Markus Fröschle */ -#ifndef _SPIDMA_H_ -#define _SPIDMA_H_ +#ifndef _DMA_H_ +#define _DMA_H_ #include +#define DMA_INTC_LVL 6 +#define DMA_INTC_PRI 0 + extern int dma_init(void); +extern int dma_get_channel(int requestor); +extern int dma_set_channel(int, void (*)(void)); +extern void dma_free_channel(int requestor); +extern uint32_t dma_get_initiator(int requestor); +extern int dma_set_initiator(int initiator); +extern void dma_free_initiator(int initiator); -#endif /* _SPIDMA_H_ */ +#endif /* _DMA_H_ */ diff --git a/include/eth.h b/include/eth.h new file mode 100644 index 0000000..424bc39 --- /dev/null +++ b/include/eth.h @@ -0,0 +1,57 @@ +/* + * File: eth.h + * Purpose: Definitions for Ethernet Frames. + * + * Modifications: + */ + +#ifndef _ETH_H +#define _ETH_H + +#include "bas_types.h" + +/*******************************************************************/ + +/* Ethernet standard lengths in bytes*/ +#define ETH_ADDR_LEN (6) +#define ETH_TYPE_LEN (2) +#define ETH_CRC_LEN (4) +#define ETH_MAX_DATA (1500) +#define ETH_MIN_DATA (46) +#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN) + +/* Defined Ethernet Frame Types */ +#define ETH_FRM_IP (0x0800) +#define ETH_FRM_ARP (0x0806) +#define ETH_FRM_RARP (0x8035) +#define ETH_FRM_TEST (0xA5A5) + +/* Maximum and Minimum Ethernet Frame Sizes */ +#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN) +#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN) +#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA) + +/* Ethernet Addresses */ +typedef uint8_t ETH_ADDR[ETH_ADDR_LEN]; + +/* 16-bit Ethernet Frame Type, ie. Protocol */ +typedef uint16_t ETH_FRM_TYPE; + +/* Ethernet Frame Header definition */ +typedef struct +{ + ETH_ADDR dest; + ETH_ADDR src; + ETH_FRM_TYPE type; +} ETH_HDR; + +/* Ethernet Frame definition */ +typedef struct +{ + ETH_HDR head; + uint8_t* data; +} ETH_FRAME; + +/*******************************************************************/ + +#endif /* _ETH_H */ diff --git a/include/fec.h b/include/fec.h new file mode 100644 index 0000000..16e1cbf --- /dev/null +++ b/include/fec.h @@ -0,0 +1,164 @@ +/* + * File: fec.h + * Purpose: Driver for the Fast Ethernet Controller (FEC) + * + * Notes: + */ + +#ifndef _FEC_H_ +#define _FEC_H_ + +/********************************************************************/ +/* MII Speed Settings */ +#define FEC_MII_10BASE_T 0 +#define FEC_MII_100BASE_TX 1 + +/* MII Duplex Settings */ +#define FEC_MII_HALF_DUPLEX 0 +#define FEC_MII_FULL_DUPLEX 1 + +/* Timeout for MII communications */ +#define FEC_MII_TIMEOUT 0x10000 + +/* External Interface Modes */ +#define FEC_MODE_7WIRE 0 +#define FEC_MODE_MII 1 +#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */ + +/* + * FEC Event Log + */ +typedef struct { + int total; /* total count of errors */ + int hberr; /* heartbeat error */ + int babr; /* babbling receiver */ + int babt; /* babbling transmitter */ + int gra; /* graceful stop complete */ + int txf; /* transmit frame */ + int mii; /* MII */ + int lc; /* late collision */ + int rl; /* collision retry limit */ + int xfun; /* transmit FIFO underrrun */ + int xferr; /* transmit FIFO error */ + int rferr; /* receive FIFO error */ + int dtxf; /* DMA transmit frame */ + int drxf; /* DMA receive frame */ + int rfsw_inv; /* Invalid bit in RFSW */ + int rfsw_l; /* RFSW Last in Frame */ + int rfsw_m; /* RFSW Miss */ + int rfsw_bc; /* RFSW Broadcast */ + int rfsw_mc; /* RFSW Multicast */ + int rfsw_lg; /* RFSW Length Violation */ + int rfsw_no; /* RFSW Non-octet */ + int rfsw_cr; /* RFSW Bad CRC */ + int rfsw_ov; /* RFSW Overflow */ + int rfsw_tr; /* RFSW Truncated */ +} FEC_EVENT_LOG; + + +int +fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t ); + +int +fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *); + +void +fec_mii_init(uint8_t, uint32_t); + +void +fec_mib_init(uint8_t); + +void +fec_mib_dump(uint8_t); + +void +fec_log_init(uint8_t); + +void +fec_log_dump(uint8_t); + +void +fec_debug_dump(uint8_t); + +void +fec_duplex (uint8_t, uint8_t); + +uint8_t +fec_hash_address(const uint8_t *); + +void +fec_set_address (uint8_t ch, const uint8_t *); + +void +fec_reset (uint8_t); + +void +fec_init (uint8_t, uint8_t, const uint8_t *); + +void +fec_rx_start(uint8_t, int8_t *); + +void +fec_rx_restart(uint8_t); + +void +fec_rx_stop (uint8_t); + +void +fec_rx_frame(uint8_t, NIF *); + +void +fec0_rx_frame(void); + +void +fec1_rx_frame(void); + +void +fec_tx_start(uint8_t, int8_t *); + +void +fec_tx_restart(uint8_t); + +void +fec_tx_stop (uint8_t); + +void +fec0_tx_frame(void); + +void +fec1_tx_frame(void); + +int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +int +fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); + +int +fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); + +void +fec_irq_enable(uint8_t, uint8_t, uint8_t); + +void +fec_irq_disable(uint8_t); + +void +fec_interrupt_handler(uint8_t); + +int +fec0_interrupt_handler(void *, void *); + +int +fec1_interrupt_handler(void *, void *); + +void +fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *); + +void +fec_eth_reset(uint8_t); + +void +fec_eth_stop(uint8_t); + +/********************************************************************/ + +#endif /* _FEC_H_ */ diff --git a/include/fecbd.h b/include/fecbd.h new file mode 100644 index 0000000..dc76f6f --- /dev/null +++ b/include/fecbd.h @@ -0,0 +1,99 @@ +/* + * File: fecbd.h + * Purpose: + * + * Purpose: Provide a simple buffer management driver + */ + +#ifndef _FECBD_H_ +#define _FECBD_H_ + +/********************************************************************/ + +#define Rx 1 +#define Tx 0 + +/* + * Buffer sizes in bytes + */ +#ifndef RX_BUF_SZ +#define RX_BUF_SZ NBUF_SZ +#endif +#ifndef TX_BUF_SZ +#define TX_BUF_SZ NBUF_SZ +#endif + +/* + * Number of Rx and Tx Buffers and Buffer Descriptors + */ +#ifndef NRXBD +#define NRXBD 10 +#endif +#ifndef NTXBD +#define NTXBD 4 +#endif + +/* + * Buffer Descriptor Format + */ +typedef struct +{ + uint16_t status; /* control and status */ + uint16_t length; /* transfer length */ + uint8_t *data; /* buffer address */ +} FECBD; + +/* + * Bit level definitions for status field of buffer descriptors + */ +#define TX_BD_R 0x8000 +#define TX_BD_TO1 0x4000 +#define TX_BD_W 0x2000 +#define TX_BD_TO2 0x1000 +#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ +#define TX_BD_L 0x0800 +#define TX_BD_TC 0x0400 +#define TX_BD_DEF 0x0200 /* MCF5272 Only */ +#define TX_BD_ABC 0x0200 +#define TX_BD_HB 0x0100 /* MCF5272 Only */ +#define TX_BD_LC 0x0080 /* MCF5272 Only */ +#define TX_BD_RL 0x0040 /* MCF5272 Only */ +#define TX_BD_UN 0x0002 /* MCF5272 Only */ +#define TX_BD_CSL 0x0001 /* MCF5272 Only */ + +#define RX_BD_E 0x8000 +#define RX_BD_R01 0x4000 +#define RX_BD_W 0x2000 +#define RX_BD_R02 0x1000 +#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ +#define RX_BD_L 0x0800 +#define RX_BD_M 0x0100 +#define RX_BD_BC 0x0080 +#define RX_BD_MC 0x0040 +#define RX_BD_LG 0x0020 +#define RX_BD_NO 0x0010 +#define RX_BD_CR 0x0004 +#define RX_BD_OV 0x0002 +#define RX_BD_TR 0x0001 +#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR) + +/* + * Functions provided in fec_bd.c + */ +void +fecbd_init(uint8_t); + +uint32_t fecbd_get_start(uint8_t, uint8_t); + +FECBD * +fecbd_rx_alloc(uint8_t); + +FECBD * +fecbd_tx_alloc(uint8_t); + +FECBD * +fecbd_tx_free(uint8_t); + +/*******************************************************************/ + +#endif /* _FECBD_H_ */ diff --git a/include/icmp.h b/include/icmp.h new file mode 100644 index 0000000..2231692 --- /dev/null +++ b/include/icmp.h @@ -0,0 +1,121 @@ +/* + * File: icmp.h + * Purpose: Handle Internet Control Message Protocol packets. + * + * Notes: See RFC 792 "Internet Control Message Protocol" + * for more details. + */ + +#ifndef _ICMP_H +#define _ICMP_H + +/********************************************************************/ + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_dest_unreachable; +#define ICMP_DEST_UNREACHABLE (3) /* type */ +#define ICMP_NET_UNREACHABLE (0) /* code */ +#define ICMP_HOST_UNREACHABLE (1) +#define ICMP_PROTOCOL_UNREACHABLE (2) +#define ICMP_PORT_UNREACHABLE (3) +#define ICMP_FRAG_NEEDED (4) +#define ICMP_ROUTE_FAILED (5) + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_time_exceeded; +#define ICMP_TIME_EXCEEDED (11) /* type */ +#define ICMP_TTL_EXCEEDED (0) /* code */ +#define ICMP_FRAG_TIME_EXCEEDED (1) + +typedef struct +{ + uint8_t pointer; + uint8_t unused1; + uint16_t unused2; + uint8_t ih_dg; +} icmp_parameter_problem; +#define ICMP_PARAMETER_PROBLEM (12) /* type */ +#define ICMP_POINTER (0) /* code -- not */ + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_source_quench; +#define ICMP_SOURCE_QUENCH (4) /* type */ + +typedef struct +{ + uint32_t gateway_addr; + uint8_t ih_dg; +} icmp_redirect; +#define ICMP_REDIRECT (5) /* type */ +#define ICMP_REDIRECT_NET (0) /* code */ +#define ICMP_REDIRECT_HOST (1) +#define ICMP_REDIRECT_TOS_NET (2) +#define ICMP_REDIRECT_TOS_HOST (3) + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; + uint8_t data; +} icmp_echo; +#define ICMP_ECHO (8) /* type */ +#define ICMP_ECHO_REPLY (0) /* type */ + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; +} icmp_information; +#define ICMP_INFORMATION_REQUEST (15) /* type */ +#define ICMP_INFORMATION_REPLY (16) /* type */ + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; + uint32_t originate_ts; + uint32_t receive_ts; + uint32_t transmit_ts; +} icmp_timestamp; +#define ICMP_TIMESTAMP (13) /* type */ +#define ICMP_TIMESTAMP_REPLY (14) /* type */ + +typedef struct +{ + uint8_t type; + uint8_t code; + uint16_t chksum; + union + { + icmp_dest_unreachable dest_unreachable; + icmp_source_quench source_quench; + icmp_redirect redirect; + icmp_time_exceeded time_exceeded; + icmp_parameter_problem parameter_problem; + icmp_timestamp timestamp; + icmp_information information; + icmp_echo echo; + } msg; +} icmp_message; + +/********************************************************************/ + +/* Protocol Header information */ +#define ICMP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE) +#define ICMP_HDR_SIZE 8 + +void +icmp_handler(NIF *, NBUF *); + +/********************************************************************/ + +#endif /* _ICMP_H */ diff --git a/include/interrupts.h b/include/interrupts.h index 77f5a38..188562d 100644 --- a/include/interrupts.h +++ b/include/interrupts.h @@ -76,6 +76,25 @@ #define INT_SOURCE_GPT1 61 // GPT1 timer interrupt #define INT_SOURCE_GPT0 62 // GPT0 timer interrupt +#define DMA_INTC_LVL 6 /* interrupt level for DMA interrupt */ +#define DMA_INTC_PRI 0 /* interrupt priority for DMA interrupt */ + +#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */ +#define FEC0_INTC_PRI 0 /* interrupt priority for FEC0 */ + +#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */ +#define FEC1_INTC_PRI 1 /* interrupt priority for FEC1 */ + +#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL) +#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI) + +#define FEC0RX_DMA_PRI 5 +#define FEC1RX_DMA_PRI 5 +#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI) +#define FEC0TX_DMA_PRI 6 +#define FEC1TX_DMA_PRI 6 +#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI) extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void)); + #endif /* _INTERRUPTS_H_ */ diff --git a/include/ip.h b/include/ip.h new file mode 100644 index 0000000..9b3d562 --- /dev/null +++ b/include/ip.h @@ -0,0 +1,100 @@ +/* + * File: ip.h + * Purpose: Definitions for the Internet Protocol, IP. + * + * Notes: See RFC 791 "DARPA Internet Program Protocol + * Specification" for more details. + */ + +#ifndef _IP_H +#define _IP_H + +/********************************************************************/ + +/* 32-bit IP Addresses */ +typedef uint8_t IP_ADDR[4]; + +/* Pointer to an IP Address */ +typedef uint8_t IP_ADDR_P[]; + +/* Definition of an IP packet header */ +typedef struct +{ + uint8_t version_ihl; + uint8_t service_type; + uint16_t total_length; + uint16_t identification; + uint16_t flags_frag_offset; + uint8_t ttl; + uint8_t protocol; + uint16_t checksum; + IP_ADDR source_addr; + IP_ADDR dest_addr; + uint8_t options; /* actually an array of undetermined length */ +} ip_frame_hdr; + +/* Macros for accessing an IP datagram. */ +#define IP_VERSION(a) ((a->version_ihl & 0x00F0) >> 4) +#define IP_IHL(a) ((a->version_ihl & 0x000F)) +#define IP_SERVICE(a) (a->service_type) +#define IP_LENGTH(a) (a->total_length) +#define IP_IDENT(a) (a->identification) +#define IP_FLAGS(a) ((a->flags_frag_offset & 0x0000E000) >> 13) +#define IP_FRAGMENT(a) ((a->flags_frag_offset & 0x00001FFF)) +#define IP_TTL(a) (a->ttl) +#define IP_PROTOCOL(a) (a->protocol) +#define IP_CHKSUM(a) (a->checksum) +#define IP_SRC(a) (&a->source_addr[0]) +#define IP_DEST(a) (&a->dest_addr[0]) +#define IP_OPTIONS(a) (&a->options) +#define IP_DATA(a) (&((uint8_t *)a)[IP_IHL(a) * 4]) + +/* Defined IP protocols */ +#define IP_PROTO_ICMP (1) +#define IP_PROTO_UDP (17) + +/* Protocol Header information */ +#define IP_HDR_OFFSET ETH_HDR_LEN +#define IP_HDR_SIZE 20 /* no options */ + +/********************************************************************/ + +typedef struct +{ + IP_ADDR myip; + IP_ADDR gateway; + IP_ADDR netmask; + IP_ADDR broadcast; + unsigned int rx; + unsigned int rx_unsup; + unsigned int tx; + unsigned int err; +} IP_INFO; + +/********************************************************************/ + +void +ip_handler (NIF *, NBUF *); + +uint16_t +ip_chksum (uint16_t *, int); + +int +ip_send (NIF *, + uint8_t *, /* destination IP */ + uint8_t *, /* source IP */ + uint8_t, /* protocol */ + NBUF * /* buffer descriptor */); + +void +ip_init (IP_INFO *, IP_ADDR_P, IP_ADDR_P, IP_ADDR_P); + +uint8_t * +ip_get_myip (IP_INFO *); + +uint8_t * +ip_resolve_route (NIF *, IP_ADDR_P); + +/********************************************************************/ + +#endif /* _IP_H */ diff --git a/include/nbuf.h b/include/nbuf.h new file mode 100644 index 0000000..ca6da52 --- /dev/null +++ b/include/nbuf.h @@ -0,0 +1,85 @@ +/* + * File: nbuf.h + * Purpose: Definitions for network buffer management + * + * Notes: These routines implement a network buffer scheme + */ + +#ifndef _NBUF_H_ +#define _NBUF_H_ + +/********************************************************************/ +/* + * Include the Queue structure definitions + */ +#include "queue.h" + +/* + * Number of network buffers to use + */ +#define NBUF_MAX 30 + +/* + * Size of each buffer in bytes + */ +#ifndef NBUF_SZ +#define NBUF_SZ 1520 +#endif + +/* + * Defines to identify all the buffer queues + * - FREE must always be defined as 0 + */ +#define NBUF_FREE 0 /* available buffers */ +#define NBUF_TX_RING 1 /* buffers in the Tx BD ring */ +#define NBUF_RX_RING 2 /* buffers in the Rx BD ring */ +#define NBUF_SCRATCH 3 /* misc */ +#define NBUF_MAXQ 4 /* total number of queueus */ + +/* + * Buffer Descriptor Format + * + * Fields: + * next Pointer to next node in the queue + * data Pointer to the data buffer + * offset Index into buffer + * length Remaining bytes in buffer from (data + offset) + */ +typedef struct +{ + QNODE node; + uint8_t *data; + uint16_t offset; + uint16_t length; +} NBUF; + +/* + * Functions to manipulate the network buffers. + */ +int +nbuf_init(void); + +void +nbuf_flush(void); + +NBUF * +nbuf_alloc (void); + +void +nbuf_free(NBUF *); + +NBUF * +nbuf_remove(int); + +void +nbuf_add(int, NBUF *); + +void +nbuf_reset(void); + +void +nbuf_debug_dump(void); + +/********************************************************************/ + +#endif /* _NBUF_H_ */ diff --git a/include/net.h b/include/net.h new file mode 100644 index 0000000..b7bb149 --- /dev/null +++ b/include/net.h @@ -0,0 +1,32 @@ +/* + * File: net.h + * Purpose: Network definitions and prototypes for dBUG. + * + * Notes: + */ + +#ifndef _NET_H +#define _NET_H + +/********************************************************************/ + +/* + * Include information and prototypes for all protocols + */ +#include "eth.h" +#include "nbuf.h" +#include "nif.h" +#include "ip.h" +#include "icmp.h" +#include "arp.h" +#include "udp.h" +#include "tftp.h" + +/********************************************************************/ + +int net_init(void); + +/********************************************************************/ + +#endif /* _NET_H */ + diff --git a/include/nif.h b/include/nif.h new file mode 100644 index 0000000..e74283b --- /dev/null +++ b/include/nif.h @@ -0,0 +1,62 @@ +/* + * File: nif.h + * Purpose: Definition of a Network InterFace. + * + * Notes: + */ + +#ifndef _NIF_H +#define _NIF_H + +/********************************************************************/ + +/* + * Maximum number of supported protoocls: IP, ARP, RARP + */ +#define MAX_SUP_PROTO (3) + +typedef struct NIF_t +{ + ETH_ADDR hwa; /* ethernet card hardware address */ + ETH_ADDR broadcast; /* broadcast address */ + int mtu; /* hardware maximum transmission unit */ + int ch; /* ethernet channel associated with this NIF */ + + struct SUP_PROTO_t + { + uint16_t protocol; + void (*handler)(struct NIF_t *, NBUF *); + void *info; + } protocol[MAX_SUP_PROTO]; + + unsigned short num_protocol; + + int (*send)(struct NIF_t *, uint8_t *, uint8_t *, uint16_t, NBUF *); + + unsigned int f_rx; + unsigned int f_tx; + unsigned int f_rx_err; + unsigned int f_tx_err; + unsigned int f_err; +} NIF; + +/********************************************************************/ + +NIF * +nif_init (NIF *); + +int +nif_protocol_exist (NIF *, uint16_t); + +void +nif_protocol_handler (NIF *, uint16_t, NBUF *); + +void * +nif_get_protocol_info (NIF *, uint16_t); + +int +nif_bind_protocol (NIF *, uint16_t, void (*)(NIF *, NBUF *), void *); + +/********************************************************************/ + +#endif /* _NIF_H */ diff --git a/include/queue.h b/include/queue.h new file mode 100644 index 0000000..b8d53e9 --- /dev/null +++ b/include/queue.h @@ -0,0 +1,53 @@ +/* + * File: queue.h + * Purpose: Implement a first in, first out linked list + * + * Notes: + */ + +#ifndef _QUEUE_H_ +#define _QUEUE_H_ + +/********************************************************************/ + +/* + * Individual queue node + */ +typedef struct NODE +{ + struct NODE *next; +} QNODE; + +/* + * Queue Struture - linked list of qentry items + */ +typedef struct +{ + QNODE *head; + QNODE *tail; +} QUEUE; + +/* + * Functions provided by queue.c + */ +void +queue_init(QUEUE *); + +int +queue_isempty(QUEUE *); + +void +queue_add(QUEUE *, QNODE *); + +QNODE* +queue_remove(QUEUE *); + +QNODE* +queue_peek(QUEUE *); + +void +queue_move(QUEUE *, QUEUE *); + +/********************************************************************/ + +#endif /* _QUEUE_H_ */ diff --git a/include/tftp.h b/include/tftp.h new file mode 100644 index 0000000..b3aab02 --- /dev/null +++ b/include/tftp.h @@ -0,0 +1,158 @@ +/* + * File: tftp.h + * Purpose: Data definitions for TFTP + * + * Notes: + */ + +#ifndef _TFTP_H +#define _TFTP_H + +/********************************************************************/ + +#define TFTP_RRQ (1) +#define TFTP_WRQ (2) +#define TFTP_DATA (3) +#define TFTP_ACK (4) +#define TFTP_ERROR (5) + +#define TFTP_ERR_FNF 1 +#define TFTP_ERR_AV 2 +#define TFTP_ERR_DF 3 +#define TFTP_ERR_ILL 4 +#define TFTP_ERR_TID 5 +#define TFTP_FE 6 +#define TFTP_NSU 7 +#define TFTP_ERR_UD 0 + +#define OCTET "octet" +#define NETASCII "netascii" + +/* Protocol Header information */ +#define TFTP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE) + +/* Timeout in seconds */ +#define TFTP_TIMEOUT 2 + +/* Maximum TFTP Packet Size (payload only - no header) */ +#define TFTP_PKTSIZE 512 + +/* Number of TFTP Data Buffers */ +#define NUM_TFTPBD 6 + +/********************************************************************/ + +/* Data Buffer Pointer Structure */ +typedef struct +{ + uint8_t data[TFTP_PKTSIZE]; + uint16_t bytes; +} DATA_BUF; + +/* TFTP RRQ/WRQ Packet */ +typedef struct +{ + uint16_t opcode; + char filename_mode[TFTP_PKTSIZE - 2]; +} RWRQ; + +/* TFTP DATA Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t blocknum; + uint8_t data[TFTP_PKTSIZE - 4]; +} DATA; + +/* TFTP Acknowledge Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t blocknum; +} ACK; + +/* TFTP Error Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t code; + char msg[TFTP_PKTSIZE - 4]; +} ERROR; + +/* TFTP Generic Packet */ +typedef struct +{ + uint16_t opcode; +} GEN; + +union TFTPpacket +{ + RWRQ rwrq; + DATA data; + ACK ack; + ERROR error; + GEN generic; +}; + +/* TFTP Connection Status */ +typedef struct +{ + /* Pointer to next character in buffer ring */ + uint8_t *next_char; + + /* Direction of current connection, read or write */ + uint8_t dir; + + /* Connection established flag */ + uint8_t open; + + /* Pointer to our Network InterFace */ + NIF *nif; + + /* File being transferred */ + char *file; + + /* Server IP address */ + IP_ADDR server_ip; + + /* Queue to hold the TFTP packets */ + QUEUE queue; + + /* Bytes received counter */ + uint32_t bytes_recv; + + /* Bytes sent counter */ + uint32_t bytes_sent; + + /* Bytes remaining in current Rx buffer */ + uint32_t rem_bytes; + + /* Server UDP port */ + uint16_t server_port; + + /* My UDP port */ + uint16_t my_port; + + /* Expected TFTP block number */ + uint16_t exp_blocknum; + + /* Keep track of the last packet acknowledged */ + uint16_t last_ack; + + /* Error Flag */ + uint8_t error; + +} TFTP_Connection; + + +/********************************************************************/ + +void tftp_handler(NIF *, NBUF *) ; +int tftp_write (NIF *, char *, IP_ADDR_P, uint32_t, uint32_t); +int tftp_read(NIF *, char *, IP_ADDR_P); +void tftp_end(int); +int tftp_in_char(void); + +/********************************************************************/ + +#endif /* _TFTP_H */ diff --git a/include/udp.h b/include/udp.h new file mode 100644 index 0000000..c2ce44e --- /dev/null +++ b/include/udp.h @@ -0,0 +1,61 @@ +/* + * File: udp.h + * Purpose: User Datagram Protocol, UDP, data definitions + * + * Notes: + */ + +#ifndef _UDP_H +#define _UDP_H + +/********************************************************************/ + +typedef struct +{ + uint16_t src_port; + uint16_t dest_port; + uint16_t length; + uint16_t chksum; +} udp_frame_hdr; + +#define UDP_SOURCE(a) (a->src_port) +#define UDP_DEST(a) (a->dest_port) +#define UDP_LENGTH(a) (a->length) +#define UDP_CHKSUM(a) (a->chksum) + +#define DEFAULT_UDP_PORT (0x4321) +#define UDP_PORT_TELNET (23) +#define UDP_PORT_FTP (21) +#define UDP_PORT_TFTP (69) + +/* Protocol Header information */ +#define UDP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE) +#define UDP_HDR_SIZE 8 + + +/********************************************************************/ + +void +udp_init (void); + +void +udp_prime_port (uint16_t); + +uint16_t +udp_obtain_free_port (void); + +void +udp_bind_port ( uint16_t, void (*)(NIF *,NBUF *)); + +void +udp_free_port (uint16_t); + +int +udp_send (NIF *, uint8_t *, int, int, NBUF *); + +void +udp_handler (NIF *, NBUF *); + +/********************************************************************/ + +#endif /* _UDP_H */ diff --git a/net/fec.c b/net/fec.c new file mode 100644 index 0000000..d4d6f4a --- /dev/null +++ b/net/fec.c @@ -0,0 +1,1390 @@ +/* + * File: fec.c + * Purpose: Driver for the Fast Ethernet Controller (FEC) + * + * Notes: + */ + +#include "net.h" +#include "fec.h" +#include "fecbd.h" +#include "exceptions.h" +#include "interrupts.h" +#include "MCF5475.h" +#include "MCD_dma.h" +#include "mcd_initiators.h" +#include "dma.h" +#include "bas_string.h" +#include "bas_printf.h" +#include + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#else +#error Unknown machine! +#endif + + +/********************************************************************/ + +FEC_EVENT_LOG fec_log[2]; + +/********************************************************************/ +/* + * Write a value to a PHY's MII register. + * + * Parameters: + * ch FEC channel + * phy_addr Address of the PHY. + * reg_addr Address of the register in the PHY. + * data Data to be written to the PHY register. + * + * Return Values: + * 1 on failure + * 0 on success. + * + * Please refer to your PHY manual for registers and their meanings. + * mii_write() polls for the FEC's MII interrupt event (which should + * be masked from the interrupt handler) and clears it. If after a + * suitable amount of time the event isn't triggered, a value of 0 + * is returned. + */ +int fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + int timeout; + uint32_t eimr; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Write to the MII Management Frame Register to kick-off + * the MII write + */ + MCF_FEC_MMFR(ch) = 0 + | MCF_FEC_MMFR_ST_01 + | MCF_FEC_MMFR_OP_WRITE + | MCF_FEC_MMFR_PA(phy_addr) + | MCF_FEC_MMFR_RA(reg_addr) + | MCF_FEC_MMFR_TA_10 + | MCF_FEC_MMFR_DATA(data); + + /* + * Mask the MII interrupt + */ + eimr = MCF_FEC_EIMR(ch); + MCF_FEC_EIMR(ch) &= ~MCF_FEC_EIMR_MII; + + /* + * Poll for the MII interrupt (interrupt should be masked) + */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) + break; + } + if(timeout == FEC_MII_TIMEOUT) + return 1; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Restore the EIMR + */ + MCF_FEC_EIMR(ch) = eimr; + + return 0; +} + +/********************************************************************/ +/* + * Read a value from a PHY's MII register. + * + * Parameters: + * ch FEC channel + * phy_addr Address of the PHY. + * reg_addr Address of the register in the PHY. + * data Pointer to storage for the Data to be read + * from the PHY register (passed by reference) + * + * Return Values: + * 1 on failure + * 0 on success. + * + * Please refer to your PHY manual for registers and their meanings. + * mii_read() polls for the FEC's MII interrupt event (which should + * be masked from the interrupt handler) and clears it. If after a + * suitable amount of time the event isn't triggered, a value of 0 + * is returned. + */ +int fec_mii_read(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + int timeout; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Write to the MII Management Frame Register to kick-off + * the MII read + */ + MCF_FEC_MMFR(ch) = 0 + | MCF_FEC_MMFR_ST_01 + | MCF_FEC_MMFR_OP_READ + | MCF_FEC_MMFR_PA(phy_addr) + | MCF_FEC_MMFR_RA(reg_addr) + | MCF_FEC_MMFR_TA_10; + + /* + * Poll for the MII interrupt (interrupt should be masked) + */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) + break; + } + + if(timeout == FEC_MII_TIMEOUT) + return 1; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + *data = (uint16_t)(MCF_FEC_MMFR(ch) & 0x0000FFFF); + + return 0; +} + +/********************************************************************/ +/* + * Initialize the MII interface controller + * + * Parameters: + * ch FEC channel + * sys_clk System Clock Frequency (in MHz) + */ +void fec_mii_init(uint8_t ch, uint32_t sys_clk) +{ + /* + * Initialize the MII clock (EMDC) frequency + * + * Desired MII clock is 2.5MHz + * MII Speed Setting = System_Clock / (2.5MHz * 2) + * (plus 1 to make sure we round up) + */ + MCF_FEC_MSCR(ch) = MCF_FEC_MSCR_MII_SPEED((sys_clk/5)+1); +} + +/********************************************************************/ +/* Initialize the MIB counters + * + * Parameters: + * ch FEC channel + */ +void fec_mib_init(uint8_t ch) +{ +//To do +} + +/********************************************************************/ +/* Display the MIB counters + * + * Parameters: + * ch FEC channel + */ +void fec_mib_dump(uint8_t ch) +{ +//To do +} + +/********************************************************************/ +/* Initialize the FEC log + * + * Parameters: + * ch FEC channel + */ +void fec_log_init(uint8_t ch) +{ + memset(&fec_log[ch],0,sizeof(FEC_EVENT_LOG)); +} + +/********************************************************************/ +/* Display the FEC log + * + * Parameters: + * ch FEC channel + */ +void fec_log_dump(uint8_t ch) +{ + xprintf("\n FEC%d Log\n---------------\n",ch); + xprintf("Total: %4d\n",fec_log[ch].total); + xprintf("hberr: %4d\n",fec_log[ch].hberr); + xprintf("babr: %4d\n",fec_log[ch].babr); + xprintf("babt: %4d\n",fec_log[ch].babt); + xprintf("gra: %4d\n",fec_log[ch].gra); + xprintf("txf: %4d\n",fec_log[ch].txf); + xprintf("mii: %4d\n",fec_log[ch].mii); + xprintf("lc: %4d\n",fec_log[ch].lc); + xprintf("rl: %4d\n",fec_log[ch].rl); + xprintf("xfun: %4d\n",fec_log[ch].xfun); + xprintf("xferr: %4d\n",fec_log[ch].xferr); + xprintf("rferr: %4d\n",fec_log[ch].rferr); + xprintf("dtxf: %4d\n",fec_log[ch].dtxf); + xprintf("drxf: %4d\n",fec_log[ch].drxf); + xprintf("\nRFSW:\n"); + xprintf("inv: %4d\n",fec_log[ch].rfsw_inv); + xprintf("m: %4d\n",fec_log[ch].rfsw_m); + xprintf("bc: %4d\n",fec_log[ch].rfsw_bc); + xprintf("mc: %4d\n",fec_log[ch].rfsw_mc); + xprintf("lg: %4d\n",fec_log[ch].rfsw_lg); + xprintf("no: %4d\n",fec_log[ch].rfsw_no); + xprintf("cr: %4d\n",fec_log[ch].rfsw_cr); + xprintf("ov: %4d\n",fec_log[ch].rfsw_ov); + xprintf("tr: %4d\n",fec_log[ch].rfsw_tr); + xprintf("---------------\n\n"); +} + +/********************************************************************/ +/* + * Display some of the registers for debugging + * + * Parameters: + * ch FEC channel + */ +void fec_debug_dump(uint8_t ch) +{ + xprintf("\n------------- FEC%d -------------\n",ch); + xprintf("EIR %08x \n",MCF_FEC_EIR(ch)); + xprintf("EIMR %08x \n",MCF_FEC_EIMR(ch)); + xprintf("ECR %08x \n",MCF_FEC_ECR(ch)); + xprintf("RCR %08x \n",MCF_FEC_RCR(ch)); + xprintf("R_HASH %08x \n",MCF_FEC_RHR_HASH(ch)); + xprintf("TCR %08x \n",MCF_FEC_TCR(ch)); + xprintf("FECTFWR %08x \n",MCF_FEC_FECTFWR(ch)); + xprintf("FECRFSR %08x \n",MCF_FEC_FECRFSR(ch)); + xprintf("FECRFCR %08x \n",MCF_FEC_FECRFCR(ch)); + xprintf("FECRLRFP %08x \n",MCF_FEC_FECRLRFP(ch)); + xprintf("FECRLWFP %08x \n",MCF_FEC_FECRLWFP(ch)); + xprintf("FECRFAR %08x \n",MCF_FEC_FECRFAR(ch)); + xprintf("FECRFRP %08x \n",MCF_FEC_FECRFRP(ch)); + xprintf("FECRFWP %08x \n",MCF_FEC_FECRFWP(ch)); + xprintf("FECTFSR %08x \n",MCF_FEC_FECTFSR(ch)); + xprintf("FECTFCR %08x \n",MCF_FEC_FECTFCR(ch)); + xprintf("FECTLRFP %08x \n",MCF_FEC_FECTLRFP(ch)); + xprintf("FECTLWFP %08x \n",MCF_FEC_FECTLWFP(ch)); + xprintf("FECTFAR %08x \n",MCF_FEC_FECTFAR(ch)); + xprintf("FECTFRP %08x \n",MCF_FEC_FECTFRP(ch)); + xprintf("FECTFWP %08x \n",MCF_FEC_FECTFWP(ch)); + xprintf("FRST %08x \n",MCF_FEC_FECFRST(ch)); + xprintf("--------------------------------\n\n"); +} + +/********************************************************************/ +/* + * Set the duplex on the selected FEC controller + * + * Parameters: + * ch FEC channel + * duplex FEC_MII_FULL_DUPLEX or FEC_MII_HALF_DUPLEX + */ +void fec_duplex (uint8_t ch, uint8_t duplex) +{ + switch (duplex) + { + case FEC_MII_HALF_DUPLEX: + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_DRT; + MCF_FEC_TCR(ch) &= (uint32_t)~MCF_FEC_TCR_FDEN; + break; + case FEC_MII_FULL_DUPLEX: + default: + MCF_FEC_RCR(ch) &= (uint32_t)~MCF_FEC_RCR_DRT; + MCF_FEC_TCR(ch) |= MCF_FEC_TCR_FDEN; + break; + } +} + +/********************************************************************/ +/* + * Generate the hash table settings for the given address + * + * Parameters: + * addr 48-bit (6 byte) Address to generate the hash for + * + * Return Value: + * The 6 most significant bits of the 32-bit CRC result + */ +uint8_t fec_hash_address(const uint8_t *addr) +{ + uint32_t crc; + uint8_t byte; + int i, j; + + crc = 0xFFFFFFFF; + for(i=0; i<6; ++i) + { + byte = addr[i]; + for(j=0; j<8; ++j) + { + if((byte & 0x01)^(crc & 0x01)) + { + crc >>= 1; + crc = crc ^ 0xEDB88320; + } + else + crc >>= 1; + byte >>= 1; + } + } + return (uint8_t)(crc >> 26); +} + +/********************************************************************/ +/* + * Set the Physical (Hardware) Address and the Individual Address + * Hash in the selected FEC + * + * Parameters: + * ch FEC channel + * pa Physical (Hardware) Address for the selected FEC + */ +void fec_set_address (uint8_t ch, const uint8_t *pa) +{ + uint8_t crc; + + /* + * Set the Physical Address + */ + MCF_FEC_PALR(ch) = (uint32_t)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]); + MCF_FEC_PAHR(ch) = (uint32_t)((pa[4]<<24) | (pa[5]<<16)); + + /* + * Calculate and set the hash for given Physical Address + * in the Individual Address Hash registers + */ + crc = fec_hash_address(pa); + if(crc >= 32) + MCF_FEC_IAUR(ch) |= (uint32_t)(1 << (crc - 32)); + else + MCF_FEC_IALR(ch) |= (uint32_t)(1 << crc); +} + +/********************************************************************/ +/* + * Reset the selected FEC controller + * + * Parameters: + * ch FEC channel + */ +void fec_reset (uint8_t ch) +{ + int i; + + /* Clear any events in the FIFO status registers */ + MCF_FEC_FECRFSR(ch) = (0 + | MCF_FEC_FECRFSR_OF + | MCF_FEC_FECRFSR_UF + | MCF_FEC_FECRFSR_RXW + | MCF_FEC_FECRFSR_FAE + | MCF_FEC_FECRFSR_IP); + MCF_FEC_FECTFSR(ch) = (0 + | MCF_FEC_FECRFSR_OF + | MCF_FEC_FECRFSR_UF + | MCF_FEC_FECRFSR_RXW + | MCF_FEC_FECRFSR_FAE + | MCF_FEC_FECRFSR_IP); + + /* Reset the FIFOs */ + MCF_FEC_FECFRST(ch) |= MCF_FEC_FECFRST_SW_RST; + MCF_FEC_FECFRST(ch) &= ~MCF_FEC_FECFRST_SW_RST; + + /* Set the Reset bit and clear the Enable bit */ + MCF_FEC_ECR(ch) = MCF_FEC_ECR_RESET; + + /* Wait at least 8 clock cycles */ + for (i=0; i<10; ++i) + nop(); +} + +/********************************************************************/ +/* + * Initialize the selected FEC + * + * Parameters: + * ch FEC channel + * mode External interface mode (MII, 7-wire, or internal loopback) + * pa Physical (Hardware) Address for the selected FEC + */ +void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa) +{ + /* + * Enable all the external interface signals + */ + if (mode == FEC_MODE_7WIRE) + { + if (ch == 1) + MCF_PAD_PAR_FECI2CIRQ |= MCF_PAD_PAR_FECI2CIRQ_PAR_E17; + else + MCF_PAD_PAR_FECI2CIRQ |= MCF_PAD_PAR_FECI2CIRQ_PAR_E07; + } + else if (mode == FEC_MODE_MII) + { + if (ch == 1) + MCF_PAD_PAR_FECI2CIRQ |= 0 + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII + | MCF_PAD_PAR_FECI2CIRQ_PAR_E17; + else + MCF_PAD_PAR_FECI2CIRQ |= 0 + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII + | MCF_PAD_PAR_FECI2CIRQ_PAR_E07; + } + + /* + * Clear the Individual and Group Address Hash registers + */ + MCF_FEC_IALR(ch) = 0; + MCF_FEC_IAUR(ch) = 0; + MCF_FEC_GALR(ch) = 0; + MCF_FEC_GAUR(ch) = 0; + + /* + * Set the Physical Address for the selected FEC + */ + fec_set_address(ch, pa); + + /* + * Mask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; + + /* + * Clear all FEC interrupt events + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; + + /* + * Initialize the Receive Control Register + */ + MCF_FEC_RCR(ch) = 0 + | MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) + #ifdef FEC_PROMISCUOUS + | MCF_FEC_RCR_PROM + #endif + | MCF_FEC_RCR_FCE; + + if (mode == FEC_MODE_MII) + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_MII_MODE; + + else if (mode == FEC_MODE_LOOPBACK) + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_LOOP; + + /* + * Initialize the Transmit Control Register + */ + MCF_FEC_TCR(ch) = MCF_FEC_TCR_FDEN; + + /* + * Set Rx FIFO alarm and granularity + */ + MCF_FEC_FECRFCR(ch) = 0 + | MCF_FEC_FECRFCR_FRMEN + | MCF_FEC_FECRFCR_RXW_MSK + | MCF_FEC_FECRFCR_GR(7); + MCF_FEC_FECRFAR(ch) = MCF_FEC_FECRFAR_ALARM(768); + + /* + * Set Tx FIFO watermark, alarm and granularity + */ + MCF_FEC_FECTFCR(ch) = 0 + | MCF_FEC_FECTFCR_FRMEN + | MCF_FEC_FECTFCR_TXW_MASK + | MCF_FEC_FECTFCR_GR(7); + MCF_FEC_FECTFAR(ch) = MCF_FEC_FECTFAR_ALARM(256); + MCF_FEC_FECTFWR(ch) = MCF_FEC_FECTFWR_X_WMRK_256; + + /* + * Enable the transmitter to append the CRC + */ + MCF_FEC_FECCTCWR(ch) = 0 + | MCF_FEC_FECCTCWR_TFCW + | MCF_FEC_FECCTCWR_CRC; +} + +/********************************************************************/ +/* + * Start the FEC Rx DMA task + * + * Parameters: + * ch FEC channel + * rxbd First Rx buffer descriptor in the chain + */ +void fec_rx_start(uint8_t ch, int8_t *rxbd) +{ + uint32_t initiator; + int channel, result; + + /* + * Make the initiator assignment + */ + result = dma_set_initiator(DMA_FEC_RX(ch)); + + /* + * Grab the initiator number + */ + initiator = dma_get_initiator(DMA_FEC_RX(ch)); + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_set_channel(DMA_FEC_RX(ch), + (ch == 0) ? fec0_rx_frame : fec1_rx_frame); + + /* + * Start the Rx DMA task + */ + /* + * Start the Rx DMA task + */ + MCD_startDma(channel, + (int8_t *) rxbd, + 0, + (int8_t *) MCF_FEC_FECRFDR(ch), + 0, + RX_BUF_SZ, + 0, + initiator, + FECRX_DMA_PRI(ch), + 0 + | MCD_FECRX_DMA + | MCD_INTERRUPT + | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_RL + | MCD_TT_FLAGS_SP + , + 0 + | MCD_NO_CSUM + | MCD_NO_BYTE_SWAP + ); +} + +/********************************************************************/ +/* + * Continue the Rx DMA task + * + * This routine is called after the DMA task has halted after + * encountering an Rx buffer descriptor that wasn't marked as + * ready. There is no harm in calling the DMA continue routine + * if the DMA is not halted. + * + * Parameters: + * ch FEC channel + */ +void fec_rx_continue(uint8_t ch) +{ + int channel; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_RX(ch)); + /* + * Continue/restart the DMA task + */ + MCD_continDma(channel); +} + +/********************************************************************/ +/* + * Stop all frame receptions on the selected FEC + * + * Parameters: + * ch FEC channel + */ +void fec_rx_stop (uint8_t ch) +{ + uint32_t mask; + int channel; + + /* Save off the EIMR value */ + mask = MCF_FEC_EIMR(ch); + + /* Mask all interrupts */ + MCF_FEC_EIMR(ch) = 0; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_RX(ch)); + /* Kill the FEC Rx DMA task */ + MCD_killDma(channel); + + /* + * Free up the FEC requestor from the software maintained + * initiator list + */ + dma_free_initiator(DMA_FEC_RX(ch)); + + /* Free up the DMA channel */ + dma_free_channel(DMA_FEC_RX(ch)); + + /* Restore the interrupt mask register value */ + MCF_FEC_EIMR(ch) = mask; +} + +/********************************************************************/ +/* + * Receive Frame interrupt handler - this handler is called by the + * DMA interrupt handler indicating that a packet was successfully + * transferred out of the Rx FIFO. + * + * Parameters: + * nif Pointer to Network Interface structure + * ch FEC channel + */ +void fec_rx_frame(uint8_t ch, NIF *nif) +{ + ETH_HDR *eth_hdr; + FECBD *pRxBD; + NBUF *cur_nbuf, *new_nbuf; + int keep; + + while ((pRxBD = fecbd_rx_alloc(ch)) != NULL) + { + fec_log[ch].drxf++; + keep = true; + + /* + * Check the Receive Frame Status Word for errors + * - The L bit should always be set + * - No undefined bits should be set + * - The upper 5 bits of the length should be cleared + */ + if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) + || (pRxBD->length & 0xF800)) + { + keep = false; + fec_log[ch].rfsw_inv++; + } + else if (pRxBD->status & RX_BD_ERROR) + { + keep = false; + if (pRxBD->status & RX_BD_NO) + fec_log[ch].rfsw_no++; + if (pRxBD->status & RX_BD_CR) + fec_log[ch].rfsw_cr++; + if (pRxBD->status & RX_BD_OV) + fec_log[ch].rfsw_ov++; + if (pRxBD->status & RX_BD_TR) + fec_log[ch].rfsw_tr++; + } + else + { + if (pRxBD->status & RX_BD_LG) + fec_log[ch].rfsw_lg++; + if (pRxBD->status & RX_BD_M) + fec_log[ch].rfsw_m++; + if (pRxBD->status & RX_BD_BC) + fec_log[ch].rfsw_bc++; + if (pRxBD->status & RX_BD_MC) + fec_log[ch].rfsw_mc++; + } + + if (keep) + { + /* + * Pull the network buffer off the Rx ring queue + */ + cur_nbuf = nbuf_remove(NBUF_RX_RING); + + /* + * Copy the buffer descriptor information to the network buffer + */ + cur_nbuf->length = (pRxBD->length - (ETH_HDR_LEN + ETH_CRC_LEN)); + cur_nbuf->offset = ETH_HDR_LEN; + + /* + * Get a new buffer pointer for this buffer descriptor + */ + new_nbuf = nbuf_alloc(); + if (new_nbuf == NULL) + { + #ifdef DEBUG_PRINT + xprintf("nbuf_alloc() failed\n"); + #endif + /* + * Can't allocate a new network buffer, so we + * have to trash the received data and reuse the buffer + * hoping that some buffers will free up in the system + * and this frame will be re-transmitted by the host + */ + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + nbuf_add(NBUF_RX_RING, cur_nbuf); + fec_rx_continue(ch); + continue; + } + + /* + * Add the new network buffer to the Rx ring queue + */ + nbuf_add(NBUF_RX_RING, new_nbuf); + + /* + * Re-initialize the buffer descriptor - pointing it + * to the new data buffer. The previous data buffer + * will be passed up the stack + */ + pRxBD->data = new_nbuf->data; + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + + + /* + * Let the DMA know that there is a new Rx BD (in case the + * ring was full and the DMA was waiting for an empty one) + */ + fec_rx_continue(ch); + + /* + * Get pointer to the frame data inside the network buffer + */ + eth_hdr = (ETH_HDR *)cur_nbuf->data; + + /* + * Pass the received packet up the network stack if the + * protocol is supported in our network interface (NIF) + */ + if (nif_protocol_exist(nif,eth_hdr->type)) + { + nif_protocol_handler(nif, eth_hdr->type, cur_nbuf); + } + else + nbuf_free(cur_nbuf); + } + else + { + /* + * This frame isn't a keeper + * Reset the status and length, but don't need to get another + * buffer since we are trashing the data in the current one + */ + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + + /* + * Move the current buffer from the beginning to the end of the + * Rx ring queue + */ + cur_nbuf = nbuf_remove(NBUF_RX_RING); + nbuf_add(NBUF_RX_RING, cur_nbuf); + + /* + * Let the DMA know that there are new Rx BDs (in case + * it is waiting for an empty one) + */ + fec_rx_continue(ch); + } + } +} + +void fec0_rx_frame(void) +{ + extern NIF nif1; + fec_rx_frame(0, &nif1); +} + +void fec1_rx_frame(void) +{ + extern NIF nif1; + fec_rx_frame(1, &nif1); +} + +/********************************************************************/ +/* + * Start the FEC Tx DMA task + * + * Parameters: + * ch FEC channel + * txbd First Tx buffer descriptor in the chain + */ +void fec_tx_start(uint8_t ch, int8_t *txbd) +{ + uint32_t initiator; + int channel, result; + void fec0_tx_frame(void); + void fec1_tx_frame(void); + + /* + * Make the initiator assignment + */ + result = dma_set_initiator(DMA_FEC_TX(ch)); + + /* + * Grab the initiator number + */ + initiator = dma_get_initiator(DMA_FEC_TX(ch)); + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_set_channel(DMA_FEC_TX(ch), + (ch == 0) ? fec0_tx_frame : fec1_tx_frame); + + /* + * Start the Tx DMA task + */ + MCD_startDma(channel, + (int8_t *) txbd, + 0, + (int8_t*) MCF_FEC_FECTFDR(ch), + 0, + ETH_MTU, + 0, + initiator, + FECTX_DMA_PRI(ch), + 0 + | MCD_FECTX_DMA + | MCD_INTERRUPT + | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_RL + | MCD_TT_FLAGS_SP + , + 0 + | MCD_NO_CSUM + | MCD_NO_BYTE_SWAP + ); +} + +/********************************************************************/ +/* + * Continue the Tx DMA task + * + * This routine is called after the DMA task has halted after + * encountering an Tx buffer descriptor that wasn't marked as + * ready. There is no harm in calling the continue DMA routine + * if the DMA was not paused. + * + * Parameters: + * ch FEC channel + */ +void fec_tx_continue(uint8_t ch) +{ + int channel; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_TX(ch)); + + /* + * Continue/restart the DMA task + */ + MCD_continDma((int)channel); +} + +/********************************************************************/ +/* + * Stop all transmissions on the selected FEC and kill the DMA task + * + * Parameters: + * ch FEC channel + */ +void fec_tx_stop (uint8_t ch) +{ + uint32_t mask; + int channel; + + + /* Save off the EIMR value */ + mask = MCF_FEC_EIMR(ch); + + /* Mask all interrupts */ + MCF_FEC_EIMR(ch) = 0; + + /* If the Ethernet is still enabled... */ + if (MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN) + { + /* Issue the Graceful Transmit Stop */ + MCF_FEC_TCR(ch) |= MCF_FEC_TCR_GTS; + + /* Wait for the Graceful Stop Complete interrupt */ + while(!(MCF_FEC_EIR(ch) & MCF_FEC_EIR_GRA)) + { + if (!(MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN)) + break; + } + + /* Clear the Graceful Stop Complete interrupt */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_GRA; + } + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_TX(ch)); + + /* Kill the FEC Tx DMA task */ + MCD_killDma(channel); + + /* + * Free up the FEC requestor from the software maintained + * initiator list + */ + dma_free_initiator(DMA_FEC_TX(ch)); + + /* Free up the DMA channel */ + dma_free_channel(DMA_FEC_TX(ch)); + + /* Restore the interrupt mask register value */ + MCF_FEC_EIMR(ch) = mask; +} + +/********************************************************************/ +/* + * Trasmit Frame interrupt handler - this handler is called by the + * DMA interrupt handler indicating that a packet was successfully + * transferred to the Tx FIFO. + * + * Parameters: + * ch FEC channel + */ +void fec_tx_frame(uint8_t ch) +{ + FECBD *pTxBD; + NBUF *pNbuf; + + while ((pTxBD = fecbd_tx_free(ch)) != NULL) + { + fec_log[ch].dtxf++; + + /* + * Grab the network buffer associated with this buffer descriptor + */ + pNbuf = nbuf_remove(NBUF_TX_RING); + + /* + * Free up the network buffer that was just transmitted + */ + nbuf_free(pNbuf); + + /* + * Re-initialize the Tx BD + */ + pTxBD->data = NULL; + pTxBD->length = 0; + } +} + +void fec0_tx_frame(void) +{ + fec_tx_frame(0); +} + +void fec1_tx_frame(void) +{ + fec_tx_frame(1); +} + +/********************************************************************/ +/* + * Send a packet out the selected FEC + * + * Parameters: + * ch FEC channel + * nif Pointer to Network Interface (NIF) structure + * dst Destination MAC Address + * src Source MAC Address + * type Ethernet Frame Type + * length Number of bytes to be transmitted (doesn't include type, + * src, or dest byte count) + * pkt Pointer packet network buffer + * + * Return Value: + * 1 success + * 0 otherwise + */ +int fec_send (uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + FECBD *pTxBD; + + /* Check the length */ + if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU) + return 0; + + /* + * Copy the destination address, source address, and Ethernet + * type into the packet + */ + memcpy(&nbuf->data[0], dst, 6); + memcpy(&nbuf->data[6], src, 6); + memcpy(&nbuf->data[12], &type, 2); + + /* + * Grab the next available Tx Buffer Descriptor + */ + while ((pTxBD = fecbd_tx_alloc(ch)) == NULL) {}; + + /* + * Put the network buffer into the Tx waiting queue + */ + nbuf_add(NBUF_TX_RING, nbuf); + + /* + * Setup the buffer descriptor for transmission + */ + pTxBD->data = nbuf->data; + pTxBD->length = nbuf->length + ETH_HDR_LEN; + pTxBD->status |= (TX_BD_R | TX_BD_L); + + /* + * Continue the Tx DMA task (in case it was waiting for a new + * TxBD to be ready + */ + fec_tx_continue(ch); + + return 1; +} + +int fec0_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + return fec_send(0, nif, dst, src, type, nbuf); +} + +int fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + return fec_send(1, nif, dst, src, type, nbuf); +} +/********************************************************************/ +/* + * Enable interrupts on the selected FEC + * + * Parameters: + * ch FEC channel + * pri Interrupt Priority + * lvl Interrupt Level + */ +void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri) +{ + /* + * Setup the appropriate ICR + */ + MCF_INTC_ICR((ch == 0) ? 39 : 38) = (uint8_t)(0 + | MCF_INTC_ICR_IP(pri) + | MCF_INTC_ICR_IL(lvl)); + + /* + * Clear any pending FEC interrupt events + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; + + /* + * Unmask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_UNMASK_ALL; + + /* + * Unmask the FEC interrupt in the interrupt controller + */ + if (ch == 0) + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK39; + else + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38; +} + +/********************************************************************/ +/* + * Disable interrupts on the selected FEC + * + * Parameters: + * ch FEC channel + */ +void fec_irq_disable(uint8_t ch) +{ + + /* + * Mask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; + + /* + * Mask the FEC interrupt in the interrupt controller + */ + if (ch == 0) + MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK39; + else + MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38; +} + +/********************************************************************/ +/* + * FEC interrupt handler + * All interrupts are multiplexed into a single vector for each + * FEC module. The lower level interrupt handler passes in the + * channel to this handler. Note that the receive interrupt is + * generated by the Multi-channel DMA FEC Rx task. + * + * Parameters: + * ch FEC channel + */ +static void fec_irq_handler(uint8_t ch) +{ + uint32_t event, eir; + + /* + * Determine which interrupt(s) asserted by AND'ing the + * pending interrupts with those that aren't masked. + */ + eir = MCF_FEC_EIR(ch); + event = eir & MCF_FEC_EIMR(ch); + + #ifdef DEBUG + if (event != eir) + xprintf("Pending but not enabled: 0x%08X\n",(event ^ eir)); + #endif + + /* + * Clear the event(s) in the EIR immediately + */ + MCF_FEC_EIR(ch) = event; + + if (event & MCF_FEC_EIR_RFERR) + { + fec_log[ch].total++; + fec_log[ch].rferr++; + #ifdef DEBUG + xprintf("RFERR\n"); + xprintf("FECRFSR%d = 0x%08x\n",ch,MCF_FEC_FECRFSR(ch)); + fec_eth_stop(ch); + #endif + } + if (event & MCF_FEC_EIR_XFERR) + { + fec_log[ch].total++; + fec_log[ch].xferr++; + #ifdef DEBUG + xprintf("XFERR\n"); + #endif + } + if (event & MCF_FEC_EIR_XFUN) + { + fec_log[ch].total++; + fec_log[ch].xfun++; + #ifdef DEBUG + xprintf("XFUN\n"); + fec_eth_stop(ch); + #endif + } + if (event & MCF_FEC_EIR_RL) + { + fec_log[ch].total++; + fec_log[ch].rl++; + #ifdef DEBUG + xprintf("RL\n"); + #endif + } + if (event & MCF_FEC_EIR_LC) + { + fec_log[ch].total++; + fec_log[ch].lc++; + #ifdef DEBUG + xprintf("LC\n"); + #endif + } + if (event & MCF_FEC_EIR_MII) + { + fec_log[ch].mii++; + } + if (event & MCF_FEC_EIR_TXF) + { + fec_log[ch].txf++; + } + if (event & MCF_FEC_EIR_GRA) + { + fec_log[ch].gra++; + } + if (event & MCF_FEC_EIR_BABT) + { + fec_log[ch].total++; + fec_log[ch].babt++; + #ifdef DEBUG + xprintf("BABT\n"); + #endif + } + if (event & MCF_FEC_EIR_BABR) + { + fec_log[ch].total++; + fec_log[ch].babr++; + #ifdef DEBUG + xprintf("BABR\n"); + #endif + } + if (event & MCF_FEC_EIR_HBERR) + { + fec_log[ch].total++; + fec_log[ch].hberr++; + #ifdef DEBUG + xprintf("HBERR\n"); + #endif + } +} + +int fec0_interrupt_handler(void* arg1, void* arg2) +{ + (void) arg1; + (void) arg2; + fec_irq_handler(0); + return 1; +} + +int fec1_interrupt_handler(void* arg1, void* arg2) +{ + (void) arg1; + (void) arg2; + fec_irq_handler(1); + return 1; +} + +/********************************************************************/ +/* + * Configure the selected Ethernet port and enable all operations + * + * Parameters: + * ch FEC channel + * trcvr Transceiver mode (MII, 7-Wire or internal loopback) + * speed Maximum operating speed (MII only) + * duplex Full or Half-duplex (MII only) + * mac Physical (MAC) Address + */ +void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, const uint8_t *mac) +{ + /* + * Disable FEC interrupts + */ + fec_irq_disable(ch); + + /* + * Initialize the event log + */ + fec_log_init(ch); + + /* + * Initialize the network buffers and fec buffer descriptors + */ + nbuf_init(); + fecbd_init(ch); + + /* + * Initialize the FEC + */ + fec_reset(ch); + fec_init(ch,trcvr,mac); + + if (trcvr == FEC_MODE_MII) + { + /* + * Initialize the MII interface + */ + fec_mii_init(ch, SYSCLK); + } + + /* + * Initialize and enable FEC interrupts + */ + fec_irq_enable(ch, FEC_INTC_LVL(ch), FEC_INTC_PRI(ch)); + + /* + * Enable the multi-channel DMA tasks + */ + fec_rx_start(ch, (int8_t*) fecbd_get_start(ch,Rx)); + fec_tx_start(ch, (int8_t*) fecbd_get_start(ch,Tx)); + + /* + * Enable the FEC channel + */ + MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN; +} + +/********************************************************************/ +/* + * Reset the selected Ethernet port + * + * Parameters: + * ch FEC channel + */ +void fec_eth_reset(uint8_t ch) +{ +// To do +} + +/********************************************************************/ +/* + * Stop the selected Ethernet port + * + * Parameters: + * ch FEC channel + */ +void fec_eth_stop(uint8_t ch) +{ + int level; + + /* + * Disable interrupts + */ + level = set_ipl(7); + + /* + * Gracefully disable the receiver and transmitter + */ + fec_tx_stop(ch); + fec_rx_stop(ch); + + /* + * Disable FEC interrupts + */ + fec_irq_disable(ch); + + /* + * Disable the FEC channel + */ + MCF_FEC_ECR(ch) &= ~MCF_FEC_ECR_ETHER_EN; + + #ifdef DEBUG_PRINT + nbuf_debug_dump(); + fec_log_dump(ch); + #endif + + /* + * Flush the network buffers + */ + nbuf_flush(); + + /* + * Restore interrupt level + */ + set_ipl(level); +} +/********************************************************************/ + diff --git a/net/nbuf.c b/net/nbuf.c new file mode 100644 index 0000000..f315fac --- /dev/null +++ b/net/nbuf.c @@ -0,0 +1,227 @@ +/* + * File: nbuf.c + * Purpose: Implementation of network buffer scheme. + * + * Notes: + */ +#include "src/include/dbug.h" +#include "src/uif/net/queue.h" +#include "src/uif/net/net.h" + +#ifdef DBUG_NETWORK + +/********************************************************************/ +/* + * Queues used for network buffer storage + */ +QUEUE nbuf_queue[NBUF_MAXQ]; + +/* + * Some devices require line-aligned buffers. In order to accomplish + * this, the nbuf data is over-allocated and adjusted. The following + * array keeps track of the original data pointer returned by malloc + */ +ADDRESS unaligned_buffers[NBUF_MAX]; + +/********************************************************************/ +/* + * Initialize all the network buffer queues + * + * Return Value: + * 0 success + * 1 failure + */ +int +nbuf_init(void) +{ + int i; + NBUF *nbuf; + + for (i=0; idata = (uint8 *)((uint32)(unaligned_buffers[i] + 15) & 0xFFFFFFF0); + if (!nbuf->data) + { + ASSERT(nbuf->data); + return 1; + } + + /* Initialize the network buffer */ + nbuf->offset = 0; + nbuf->length = 0; + + /* Add the network buffer to the free list */ + queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf); + } + + #ifdef DEBUG_PRINT + printf("NBUF allocation complete\n"); + nbuf_debug_dump(); + #endif + + return 0; +} +/********************************************************************/ +/* + * Return all the allocated memory to the heap + */ +void +nbuf_flush(void) +{ + NBUF *nbuf; + int i, level = asm_set_ipl(7); + int n = 0; + + for (i=0; ioffset = 0; + nbuf->length = NBUF_SZ; + queue_add(&nbuf_queue[NBUF_FREE],(QNODE *)nbuf); + + asm_set_ipl(level); +} +/********************************************************************/ +/* + * Remove a network buffer from the specified queue + * + * Parameters: + * q The index that identifies the queue to pull the buffer from + */ +NBUF * +nbuf_remove(int q) +{ + NBUF *nbuf; + int level = asm_set_ipl(7); + + nbuf = (NBUF *)queue_remove(&nbuf_queue[q]); + asm_set_ipl(level); + return nbuf; +} +/********************************************************************/ +/* + * Add a network buffer to the specified queue + * + * Parameters: + * q The index that identifies the queue to add the buffer to + */ +void +nbuf_add(int q, NBUF *nbuf) +{ + int level = asm_set_ipl(7); + queue_add(&nbuf_queue[q],(QNODE *)nbuf); + asm_set_ipl(level); +} +/********************************************************************/ +/* + * Put all the network buffers back into the free list + */ +void +nbuf_reset(void) +{ + NBUF *nbuf; + int i, level = asm_set_ipl(7); + + for (i=1; idata, + nbuf->offset, + nbuf->length); + nbuf = (NBUF *)nbuf->node.next; + } + } + + asm_set_ipl(level); +#endif +} +/********************************************************************/ + +#endif /* #ifdef DBUG_NETWORK */