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changed types to use <stdint.h>

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This commit is contained in:
Markus Fröschle
2012-10-12 15:45:50 +00:00
parent a485a7c204
commit 78848eb4cf
44 changed files with 1990 additions and 1290 deletions
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142
.cproject Normal file
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@@ -0,0 +1,142 @@
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82
.project Normal file
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66
.settings/org.eclipse.cdt.codan.core.prefs Normal file
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eclipse.preferences.version=1
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org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
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org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
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org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={no_break_comment\=>"no break",last_case_param\=>true,empty_case_param\=>false}
org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
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org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
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org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
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useParentScope=false

2
Makefile
View File

@@ -23,13 +23,13 @@ OBJDIR=objs
EXEC=bas.hex EXEC=bas.hex
CSRCS= \ CSRCS= \
$(SRCDIR)/startcf.c \
$(SRCDIR)/sysinit.c \ $(SRCDIR)/sysinit.c \
$(SRCDIR)/BaS.c \ $(SRCDIR)/BaS.c \
$(SRCDIR)/sd_card.c \ $(SRCDIR)/sd_card.c \
$(SRCDIR)/last.c $(SRCDIR)/last.c
ASRCS= \ ASRCS= \
$(SRCDIR)/startcf.S \
$(SRCDIR)/mmu.S \ $(SRCDIR)/mmu.S \
$(SRCDIR)/exceptions.S \ $(SRCDIR)/exceptions.S \
$(SRCDIR)/supervisor.S \ $(SRCDIR)/supervisor.S \

57
cfg/DDRAM.cfg Normal file
View File

@@ -0,0 +1,57 @@
; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
ResetHalt
;Set VBR - debugger must know this in order
; to do exception capture
writecontrolreg 0x0801 0x00000000
; If MBAR changes all following writes must change
; and if a memory configuration file is used,
; the reserved areas in the register block must
; change also.
;Turn on MBAR at 0xFF00_0000
writecontrolreg 0x0C0F 0xFF000000
;Turn on RAMBAR0 at address FF10_0000
writecontrolreg 0x0C04 0xFF100035
;Turn on RAMBAR1 at address FF10_1000
writecontrolreg 0x0C05 0xFF101035
;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xE0000000;
writemem.l 0xFF000508 0x00101980; 16-bit port
writemem.l 0xFF000504 0x007F0001;
;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
;writemem.l 0xFF000108 0x73611730; SDCFG1
writemem.l 0xFF000108 0x53611730; SDCFG1
;writemem.l 0xFF00010C 0x46770000; SDCFG2
writemem.l 0xFF00010C 0x24730000; SDCFG2
;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR)
writemem.l 0xFF000100 0x04890000; SDMR (write to LMR)
;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR)
writemem.l 0xFF000100 0x00890000; SDMR (write to LMR)
;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh)
delay 1000

47
cfg/DDRAM.mem Normal file
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@@ -0,0 +1,47 @@
// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// LogicPD COLDARI1
//
// Reference:
// MCF5475RM.pdf
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address MBAR_BASE 0xFF000000
address MMUBAR_BASE 0xFF040000
usederivative "MCF5475"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
reserved 0x20000000 0x5FFFFFFF
range 0x60000000 0x7FFFFFFF 4 ReadWrite
range 0x80000000 0xCFFFFFFF 4 ReadWrite
range 0xD0000000 0xFBFFFFFF 4 ReadWrite
reserved 0xFC000000 $MBAR_BASE-1
$MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers
range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF
reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR
range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)

11
cfg/flash.cfg Normal file
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@@ -0,0 +1,11 @@
; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xFE000000;
writemem.l 0xFF000508 0x00101980; 16-bit port
writemem.l 0xFF000504 0x007F0001;

48
cfg/mem.cfg Normal file
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@@ -0,0 +1,48 @@
; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
; $RCSfile: M5475EVB.cfg,v $
; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $
; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
ResetHalt
;Set VBR - debugger must know this in order
; to do exception capture
writecontrolreg 0x0801 0x00000000
; If MBAR changes all following writes must change
; and if a memory configuration file is used,
; the reserved areas in the register block must
; change also.
;Turn on MBAR at 0xFF00_0000
writecontrolreg 0x0C0F 0xFF000000
;Turn on RAMBAR0 at address FF10_0000
writecontrolreg 0x0C04 0xFF100035
;Turn on RAMBAR1 at address FF10_1000
writecontrolreg 0x0C05 0xFF101035
;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
writemem.l 0xFF000500 0xE0000000;
writemem.l 0xFF000508 0x00001180; 16-bit port
writemem.l 0xFF000504 0x007F0001;
;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration
writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
writemem.l 0xFF000108 0x53722938; SDCFG1
writemem.l 0xFF00010C 0x24330000; SDCFG2
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR)
writemem.l 0xFF000100 0x05890000; SDRM (write to LMR)
writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh)
writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh)
writemem.l 0xFF000100 0x01890000; SDMR (write to LMR)
writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh)
delay 1000

38
cfg/mem.mem Normal file
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@@ -0,0 +1,38 @@
// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// LogicPD COLDARI1
//
// Reference:
// MCF5475RM.pdf
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address MBAR_BASE 0xFF000000
address MMUBAR_BASE 0xFF040000
usederivative "MCF5475"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM
reserved 0x20000000 $MBAR_BASE-1
$MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers
range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM
reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF
$MMUBAR_BASE $MMUBAR_BASE+0x001B
reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF
range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0)
range 0xFF101000 0xFF101FFF 4 ReadWrite // 4K SRAM1 (RAMBAR1)

BIN
firebeeV1.mcp Normal file
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Binary file not shown.

47
flash_config.xml Normal file
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@@ -0,0 +1,47 @@
<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<fpconfig>
<targetconfwindow>
<usecustomsettings>true</usecustomsettings>
<targetprocessor>5474</targetprocessor>
<connection>PEMICRO_USB</connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg</targetinitfile>
<targetmembuffaddr>0x00000000</targetmembuffaddr>
<targetmembuffsize>0x00006000</targetmembuffsize>
<enablelogging>true</enablelogging>
<verifywrites>false</verifywrites>
</targetconfwindow>
<flashconfwindow>
<membaseaddr>0xE0000000</membaseaddr>
<device>M29W640DB</device>
<organization>4Mx16x1</organization>
<flashstart>0xE0000000</flashstart>
<flashend>0xE07FFFFF</flashend>
</flashconfwindow>
<programverifywindow>
<useselectedfile>true</useselectedfile>
<projbuildtargetfile>C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19</projbuildtargetfile>
<fileiotype>Auto Detect</fileiotype>
<restrictaddrrange>false</restrictaddrrange>
<restrictaddrrangestart>0xFF800000</restrictaddrrangestart>
<restrictaddrrangeend>0xFFFFFFFF</restrictaddrrangeend>
<applyaddroffset>false</applyaddroffset>
<addroffset>0xC0200000</addroffset>
</programverifywindow>
<eraseblankcheckwindow>
<eraseallsectors>false</eraseallsectors>
<sector/>
<processsectorsindividually>false</processsectorsindividually>
</eraseblankcheckwindow>
<checksumwindow>
<computechecksumover>FileOnTarg</computechecksumover>
<addrstart>0xFF800000</addrstart>
<addrsize>0x007FFFFF</addrsize>
</checksumwindow>
</fpconfig>

40
hardware_diagnostic.xml Normal file
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@@ -0,0 +1,40 @@
<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<configsettings>
<confwindow>
<usecustomsettings>true</usecustomsettings>
<targetprocessor>5474</targetprocessor>
<connection>PEMICRO_USB</connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg</targetinitfile>
</confwindow>
<memoryreadwritewindow>
<accesstype>read</accesstype>
<accesssize>long_word</accesssize>
<targetaddress>0x60001000</targetaddress>
<valuetowrite>FFFFFFFF</valuetowrite>
</memoryreadwritewindow>
<scopelooptestwindow>
<accesstype>read</accesstype>
<accesssize>long_word</accesssize>
<targetaddress>0x00100000</targetaddress>
<valuetowrite>0x67</valuetowrite>
<speed>1000</speed>
</scopelooptestwindow>
<memorytestswindow>
<runwalking1s>true</runwalking1s>
<runbusnoise>true</runbusnoise>
<runaddress>true</runaddress>
<startaddress>0x00DE1000</startaddress>
<endaddress>0x00DE11FF</endaddress>
<accesssize>long_word</accesssize>
<passes>1</passes>
<usetargetcpu>false</usetargetcpu>
<targetscratchmemstart>0x00000100</targetscratchmemstart>
<targetscratchmemend>0x0000FFFF</targetscratchmemend>
</memorytestswindow>
</configsettings>

74
include/MCF5475.h
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@@ -16,69 +16,26 @@
#ifndef __MCF5475_H__ #ifndef __MCF5475_H__
#define __MCF5475_H__ #define __MCF5475_H__
#include <stdint.h>
/********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
#ifdef __cplusplus
extern "C" {
#endif
#pragma define_section system ".system" far_absolute RW
/* get rid of __declspec */
#if __GNUC__
#undef __declspec
/* the following should work if we had an ELF capable toolchain. Unfortunately, it doesn't
* for the current m68k-atari-mint aoutx toolchain since it does not support the
* __attribute__ ((section("x"))) syntax.
*/
/* #define __declspec(a) __attribute__ ((section ("a"))) */
#define __declspec(a) /* */
/*** /***
* MCF5475 Derivative Memory map definitions from linker command files: * MCF5475 Derivative Memory map definitions from linker command files:
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
* linker symbols must be defined in the linker command file. * linker symbols must be defined in the linker command file.
*/ */
#ifdef __GNUC__ extern uint8_t __MBAR[];
/* get rid of the __declspec() keyword */ extern uint8_t __MMUBAR[];
#undef __declspec extern uint8_t __RAMBAR0[];
#define __declspec(a) /* */ extern uint8_t __RAMBAR0_SIZE[];
extern uint8_t __RAMBAR1[];
extern uint8_t __RAMBAR1_SIZE[];
/* the same for "far" */ #define MBAR_ADDRESS (uint32_t)__MBAR
#undef far #define MMUBAR_ADDRESS (uint32_t)__MMUBAR
#define far /* */ #define RAMBAR0_ADDRESS (uint32_t)__RAMBAR0
#endif #define RAMBAR0_SIZE (uint32_t)__RAMBAR0_SIZE
#define RAMBAR1_ADDRESS (uint32_t)__RAMBAR1
extern __declspec(system) uint8 __MBAR[]; #define RAMBAR1_SIZE (uint32_t)__RAMBAR1_SIZE
extern __declspec(system) uint8 __MMUBAR[];
extern __declspec(system) uint8 __RAMBAR0[];
extern __declspec(system) uint8 __RAMBAR0_SIZE[];
extern __declspec(system) uint8 __RAMBAR1[];
extern __declspec(system) uint8 __RAMBAR1_SIZE[];
#define MBAR_ADDRESS (uint32)__MBAR
#define MMUBAR_ADDRESS (uint32)__MMUBAR
#define RAMBAR0_ADDRESS (uint32)__RAMBAR0
#define RAMBAR0_SIZE (uint32)__RAMBAR0_SIZE
#define RAMBAR1_ADDRESS (uint32)__RAMBAR1
#define RAMBAR1_SIZE (uint32)__RAMBAR1_SIZE
#include "MCF5475_SIU.h" #include "MCF5475_SIU.h"
@@ -105,9 +62,4 @@ extern __declspec(system) uint8 __RAMBAR1_SIZE[];
#include "MCF5475_SRAM.h" #include "MCF5475_SRAM.h"
#include "MCF5475_SEC.h" #include "MCF5475_SEC.h"
#ifdef __cplusplus
}
#endif
#endif /* __MCF5475_H__ */ #endif /* __MCF5475_H__ */

2
include/MCF5475_CLOCK.h
View File

@@ -24,7 +24,7 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_CLOCK_SPCR (*(vuint32*)(&__MBAR[0x300])) #define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&__MBAR[0x300]))
/* Bit definitions and macros for MCF_CLOCK_SPCR */ /* Bit definitions and macros for MCF_CLOCK_SPCR */

20
include/MCF5475_CTM.h
View File

@@ -24,16 +24,16 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_CTM_CTCR0 (*(vuint32*)(&__MBAR[0x7F00])) #define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&__MBAR[0x7F00]))
#define MCF_CTM_CTCR1 (*(vuint32*)(&__MBAR[0x7F04])) #define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&__MBAR[0x7F04]))
#define MCF_CTM_CTCR2 (*(vuint32*)(&__MBAR[0x7F08])) #define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&__MBAR[0x7F08]))
#define MCF_CTM_CTCR3 (*(vuint32*)(&__MBAR[0x7F0C])) #define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&__MBAR[0x7F0C]))
#define MCF_CTM_CTCR4 (*(vuint32*)(&__MBAR[0x7F10])) #define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&__MBAR[0x7F10]))
#define MCF_CTM_CTCR5 (*(vuint32*)(&__MBAR[0x7F14])) #define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&__MBAR[0x7F14]))
#define MCF_CTM_CTCR6 (*(vuint32*)(&__MBAR[0x7F18])) #define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&__MBAR[0x7F18]))
#define MCF_CTM_CTCR7 (*(vuint32*)(&__MBAR[0x7F1C])) #define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&__MBAR[0x7F1C]))
#define MCF_CTM_CTCRF(x) (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)])) #define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&__MBAR[0x7F00 + ((x)*0x4)]))
#define MCF_CTM_CTCRV(x) (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) #define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&__MBAR[0x7F10 + ((x-4)*0x4)]))
/* Bit definitions and macros for MCF_CTM_CTCRF */ /* Bit definitions and macros for MCF_CTM_CTCRF */

126
include/MCF5475_DMA.h
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@@ -24,69 +24,69 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_DMA_TASKBAR (*(vuint32*)(&__MBAR[0x8000])) #define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&__MBAR[0x8000]))
#define MCF_DMA_CP (*(vuint32*)(&__MBAR[0x8004])) #define MCF_DMA_CP (*(volatile uint32_t*)(&__MBAR[0x8004]))
#define MCF_DMA_EP (*(vuint32*)(&__MBAR[0x8008])) #define MCF_DMA_EP (*(volatile uint32_t*)(&__MBAR[0x8008]))
#define MCF_DMA_VP (*(vuint32*)(&__MBAR[0x800C])) #define MCF_DMA_VP (*(volatile uint32_t*)(&__MBAR[0x800C]))
#define MCF_DMA_PTD (*(vuint32*)(&__MBAR[0x8010])) #define MCF_DMA_PTD (*(volatile uint32_t*)(&__MBAR[0x8010]))
#define MCF_DMA_DIPR (*(vuint32*)(&__MBAR[0x8014])) #define MCF_DMA_DIPR (*(volatile uint32_t*)(&__MBAR[0x8014]))
#define MCF_DMA_DIMR (*(vuint32*)(&__MBAR[0x8018])) #define MCF_DMA_DIMR (*(volatile uint32_t*)(&__MBAR[0x8018]))
#define MCF_DMA_TCR0 (*(vuint16*)(&__MBAR[0x801C])) #define MCF_DMA_TCR0 (*(volatile uint16_t*)(&__MBAR[0x801C]))
#define MCF_DMA_TCR1 (*(vuint16*)(&__MBAR[0x801E])) #define MCF_DMA_TCR1 (*(volatile uint16_t*)(&__MBAR[0x801E]))
#define MCF_DMA_TCR2 (*(vuint16*)(&__MBAR[0x8020])) #define MCF_DMA_TCR2 (*(volatile uint16_t*)(&__MBAR[0x8020]))
#define MCF_DMA_TCR3 (*(vuint16*)(&__MBAR[0x8022])) #define MCF_DMA_TCR3 (*(volatile uint16_t*)(&__MBAR[0x8022]))
#define MCF_DMA_TCR4 (*(vuint16*)(&__MBAR[0x8024])) #define MCF_DMA_TCR4 (*(volatile uint16_t*)(&__MBAR[0x8024]))
#define MCF_DMA_TCR5 (*(vuint16*)(&__MBAR[0x8026])) #define MCF_DMA_TCR5 (*(volatile uint16_t*)(&__MBAR[0x8026]))
#define MCF_DMA_TCR6 (*(vuint16*)(&__MBAR[0x8028])) #define MCF_DMA_TCR6 (*(volatile uint16_t*)(&__MBAR[0x8028]))
#define MCF_DMA_TCR7 (*(vuint16*)(&__MBAR[0x802A])) #define MCF_DMA_TCR7 (*(volatile uint16_t*)(&__MBAR[0x802A]))
#define MCF_DMA_TCR8 (*(vuint16*)(&__MBAR[0x802C])) #define MCF_DMA_TCR8 (*(volatile uint16_t*)(&__MBAR[0x802C]))
#define MCF_DMA_TCR9 (*(vuint16*)(&__MBAR[0x802E])) #define MCF_DMA_TCR9 (*(volatile uint16_t*)(&__MBAR[0x802E]))
#define MCF_DMA_TCR10 (*(vuint16*)(&__MBAR[0x8030])) #define MCF_DMA_TCR10 (*(volatile uint16_t*)(&__MBAR[0x8030]))
#define MCF_DMA_TCR11 (*(vuint16*)(&__MBAR[0x8032])) #define MCF_DMA_TCR11 (*(volatile uint16_t*)(&__MBAR[0x8032]))
#define MCF_DMA_TCR12 (*(vuint16*)(&__MBAR[0x8034])) #define MCF_DMA_TCR12 (*(volatile uint16_t*)(&__MBAR[0x8034]))
#define MCF_DMA_TCR13 (*(vuint16*)(&__MBAR[0x8036])) #define MCF_DMA_TCR13 (*(volatile uint16_t*)(&__MBAR[0x8036]))
#define MCF_DMA_TCR14 (*(vuint16*)(&__MBAR[0x8038])) #define MCF_DMA_TCR14 (*(volatile uint16_t*)(&__MBAR[0x8038]))
#define MCF_DMA_TCR15 (*(vuint16*)(&__MBAR[0x803A])) #define MCF_DMA_TCR15 (*(volatile uint16_t*)(&__MBAR[0x803A]))
#define MCF_DMA_PRIOR0 (*(vuint8 *)(&__MBAR[0x803C])) #define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&__MBAR[0x803C]))
#define MCF_DMA_PRIOR1 (*(vuint8 *)(&__MBAR[0x803D])) #define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&__MBAR[0x803D]))
#define MCF_DMA_PRIOR2 (*(vuint8 *)(&__MBAR[0x803E])) #define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&__MBAR[0x803E]))
#define MCF_DMA_PRIOR3 (*(vuint8 *)(&__MBAR[0x803F])) #define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&__MBAR[0x803F]))
#define MCF_DMA_PRIOR4 (*(vuint8 *)(&__MBAR[0x8040])) #define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&__MBAR[0x8040]))
#define MCF_DMA_PRIOR5 (*(vuint8 *)(&__MBAR[0x8041])) #define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&__MBAR[0x8041]))
#define MCF_DMA_PRIOR6 (*(vuint8 *)(&__MBAR[0x8042])) #define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&__MBAR[0x8042]))
#define MCF_DMA_PRIOR7 (*(vuint8 *)(&__MBAR[0x8043])) #define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&__MBAR[0x8043]))
#define MCF_DMA_PRIOR8 (*(vuint8 *)(&__MBAR[0x8044])) #define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&__MBAR[0x8044]))
#define MCF_DMA_PRIOR9 (*(vuint8 *)(&__MBAR[0x8045])) #define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&__MBAR[0x8045]))
#define MCF_DMA_PRIOR10 (*(vuint8 *)(&__MBAR[0x8046])) #define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&__MBAR[0x8046]))
#define MCF_DMA_PRIOR11 (*(vuint8 *)(&__MBAR[0x8047])) #define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&__MBAR[0x8047]))
#define MCF_DMA_PRIOR12 (*(vuint8 *)(&__MBAR[0x8048])) #define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&__MBAR[0x8048]))
#define MCF_DMA_PRIOR13 (*(vuint8 *)(&__MBAR[0x8049])) #define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&__MBAR[0x8049]))
#define MCF_DMA_PRIOR14 (*(vuint8 *)(&__MBAR[0x804A])) #define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&__MBAR[0x804A]))
#define MCF_DMA_PRIOR15 (*(vuint8 *)(&__MBAR[0x804B])) #define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&__MBAR[0x804B]))
#define MCF_DMA_PRIOR16 (*(vuint8 *)(&__MBAR[0x804C])) #define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&__MBAR[0x804C]))
#define MCF_DMA_PRIOR17 (*(vuint8 *)(&__MBAR[0x804D])) #define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&__MBAR[0x804D]))
#define MCF_DMA_PRIOR18 (*(vuint8 *)(&__MBAR[0x804E])) #define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&__MBAR[0x804E]))
#define MCF_DMA_PRIOR19 (*(vuint8 *)(&__MBAR[0x804F])) #define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&__MBAR[0x804F]))
#define MCF_DMA_PRIOR20 (*(vuint8 *)(&__MBAR[0x8050])) #define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&__MBAR[0x8050]))
#define MCF_DMA_PRIOR21 (*(vuint8 *)(&__MBAR[0x8051])) #define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&__MBAR[0x8051]))
#define MCF_DMA_PRIOR22 (*(vuint8 *)(&__MBAR[0x8052])) #define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&__MBAR[0x8052]))
#define MCF_DMA_PRIOR23 (*(vuint8 *)(&__MBAR[0x8053])) #define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&__MBAR[0x8053]))
#define MCF_DMA_PRIOR24 (*(vuint8 *)(&__MBAR[0x8054])) #define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&__MBAR[0x8054]))
#define MCF_DMA_PRIOR25 (*(vuint8 *)(&__MBAR[0x8055])) #define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&__MBAR[0x8055]))
#define MCF_DMA_PRIOR26 (*(vuint8 *)(&__MBAR[0x8056])) #define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&__MBAR[0x8056]))
#define MCF_DMA_PRIOR27 (*(vuint8 *)(&__MBAR[0x8057])) #define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&__MBAR[0x8057]))
#define MCF_DMA_PRIOR28 (*(vuint8 *)(&__MBAR[0x8058])) #define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&__MBAR[0x8058]))
#define MCF_DMA_PRIOR29 (*(vuint8 *)(&__MBAR[0x8059])) #define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&__MBAR[0x8059]))
#define MCF_DMA_PRIOR30 (*(vuint8 *)(&__MBAR[0x805A])) #define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&__MBAR[0x805A]))
#define MCF_DMA_PRIOR31 (*(vuint8 *)(&__MBAR[0x805B])) #define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&__MBAR[0x805B]))
#define MCF_DMA_IMCR (*(vuint32*)(&__MBAR[0x805C])) #define MCF_DMA_IMCR (*(volatile uint32_t*)(&__MBAR[0x805C]))
#define MCF_DMA_TSKSZ0 (*(vuint32*)(&__MBAR[0x8060])) #define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&__MBAR[0x8060]))
#define MCF_DMA_TSKSZ1 (*(vuint32*)(&__MBAR[0x8064])) #define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&__MBAR[0x8064]))
#define MCF_DMA_DBGCOMP0 (*(vuint32*)(&__MBAR[0x8070])) #define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&__MBAR[0x8070]))
#define MCF_DMA_DBGCOMP2 (*(vuint32*)(&__MBAR[0x8074])) #define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&__MBAR[0x8074]))
#define MCF_DMA_DBGCTL (*(vuint32*)(&__MBAR[0x8078])) #define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&__MBAR[0x8078]))
#define MCF_DMA_TCR(x) (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)])) #define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&__MBAR[0x801C + ((x)*0x2)]))
#define MCF_DMA_PRIOR(x) (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)])) #define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&__MBAR[0x803C + ((x)*0x1)]))
/* Bit definitions and macros for MCF_DMA_TASKBAR */ /* Bit definitions and macros for MCF_DMA_TASKBAR */

50
include/MCF5475_DSPI.h
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@@ -24,31 +24,31 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_DSPI_DMCR (*(vuint32*)(&__MBAR[0x8A00])) #define MCF_DSPI_DMCR (*(volatile uint32_t*)(&__MBAR[0x8A00]))
#define MCF_DSPI_DTCR (*(vuint32*)(&__MBAR[0x8A08])) #define MCF_DSPI_DTCR (*(volatile uint32_t*)(&__MBAR[0x8A08]))
#define MCF_DSPI_DCTAR0 (*(vuint32*)(&__MBAR[0x8A0C])) #define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&__MBAR[0x8A0C]))
#define MCF_DSPI_DCTAR1 (*(vuint32*)(&__MBAR[0x8A10])) #define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&__MBAR[0x8A10]))
#define MCF_DSPI_DCTAR2 (*(vuint32*)(&__MBAR[0x8A14])) #define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&__MBAR[0x8A14]))
#define MCF_DSPI_DCTAR3 (*(vuint32*)(&__MBAR[0x8A18])) #define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&__MBAR[0x8A18]))
#define MCF_DSPI_DCTAR4 (*(vuint32*)(&__MBAR[0x8A1C])) #define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&__MBAR[0x8A1C]))
#define MCF_DSPI_DCTAR5 (*(vuint32*)(&__MBAR[0x8A20])) #define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&__MBAR[0x8A20]))
#define MCF_DSPI_DCTAR6 (*(vuint32*)(&__MBAR[0x8A24])) #define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&__MBAR[0x8A24]))
#define MCF_DSPI_DCTAR7 (*(vuint32*)(&__MBAR[0x8A28])) #define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&__MBAR[0x8A28]))
#define MCF_DSPI_DSR (*(vuint32*)(&__MBAR[0x8A2C])) #define MCF_DSPI_DSR (*(volatile uint32_t*)(&__MBAR[0x8A2C]))
#define MCF_DSPI_DIRSR (*(vuint32*)(&__MBAR[0x8A30])) #define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&__MBAR[0x8A30]))
#define MCF_DSPI_DTFR (*(vuint32*)(&__MBAR[0x8A34])) #define MCF_DSPI_DTFR (*(volatile uint32_t*)(&__MBAR[0x8A34]))
#define MCF_DSPI_DRFR (*(vuint32*)(&__MBAR[0x8A38])) #define MCF_DSPI_DRFR (*(volatile uint32_t*)(&__MBAR[0x8A38]))
#define MCF_DSPI_DTFDR0 (*(vuint32*)(&__MBAR[0x8A3C])) #define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A3C]))
#define MCF_DSPI_DTFDR1 (*(vuint32*)(&__MBAR[0x8A40])) #define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A40]))
#define MCF_DSPI_DTFDR2 (*(vuint32*)(&__MBAR[0x8A44])) #define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A44]))
#define MCF_DSPI_DTFDR3 (*(vuint32*)(&__MBAR[0x8A48])) #define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A48]))
#define MCF_DSPI_DRFDR0 (*(vuint32*)(&__MBAR[0x8A7C])) #define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A7C]))
#define MCF_DSPI_DRFDR1 (*(vuint32*)(&__MBAR[0x8A80])) #define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A80]))
#define MCF_DSPI_DRFDR2 (*(vuint32*)(&__MBAR[0x8A84])) #define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A84]))
#define MCF_DSPI_DRFDR3 (*(vuint32*)(&__MBAR[0x8A88])) #define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A88]))
#define MCF_DSPI_DCTAR(x) (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)])) #define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&__MBAR[0x8A0C + ((x)*0x4)]))
#define MCF_DSPI_DTFDR(x) (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)])) #define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A3C + ((x)*0x4)]))
#define MCF_DSPI_DRFDR(x) (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)])) #define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A7C + ((x)*0x4)]))
/* Bit definitions and macros for MCF_DSPI_DMCR */ /* Bit definitions and macros for MCF_DSPI_DMCR */

12
include/MCF5475_EPORT.h
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@@ -24,12 +24,12 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_EPORT_EPPAR (*(vuint16*)(&__MBAR[0xF00])) #define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&__MBAR[0xF00]))
#define MCF_EPORT_EPDDR (*(vuint8 *)(&__MBAR[0xF04])) #define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&__MBAR[0xF04]))
#define MCF_EPORT_EPIER (*(vuint8 *)(&__MBAR[0xF05])) #define MCF_EPORT_EPIER (*(volatile uint8_t *)(&__MBAR[0xF05]))
#define MCF_EPORT_EPDR (*(vuint8 *)(&__MBAR[0xF08])) #define MCF_EPORT_EPDR (*(volatile uint8_t *)(&__MBAR[0xF08]))
#define MCF_EPORT_EPPDR (*(vuint8 *)(&__MBAR[0xF09])) #define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&__MBAR[0xF09]))
#define MCF_EPORT_EPFR (*(vuint8 *)(&__MBAR[0xF0C])) #define MCF_EPORT_EPFR (*(volatile uint8_t *)(&__MBAR[0xF0C]))

42
include/MCF5475_FBCS.h
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@@ -24,33 +24,33 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_FBCS0_CSAR (*(vuint32*)(&__MBAR[0x500])) #define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&__MBAR[0x500]))
#define MCF_FBCS0_CSMR (*(vuint32*)(&__MBAR[0x504])) #define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&__MBAR[0x504]))
#define MCF_FBCS0_CSCR (*(vuint32*)(&__MBAR[0x508])) #define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&__MBAR[0x508]))
#define MCF_FBCS1_CSAR (*(vuint32*)(&__MBAR[0x50C])) #define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&__MBAR[0x50C]))
#define MCF_FBCS1_CSMR (*(vuint32*)(&__MBAR[0x510])) #define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&__MBAR[0x510]))
#define MCF_FBCS1_CSCR (*(vuint32*)(&__MBAR[0x514])) #define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&__MBAR[0x514]))
#define MCF_FBCS2_CSAR (*(vuint32*)(&__MBAR[0x518])) #define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&__MBAR[0x518]))
#define MCF_FBCS2_CSMR (*(vuint32*)(&__MBAR[0x51C])) #define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&__MBAR[0x51C]))
#define MCF_FBCS2_CSCR (*(vuint32*)(&__MBAR[0x520])) #define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&__MBAR[0x520]))
#define MCF_FBCS3_CSAR (*(vuint32*)(&__MBAR[0x524])) #define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&__MBAR[0x524]))
#define MCF_FBCS3_CSMR (*(vuint32*)(&__MBAR[0x528])) #define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&__MBAR[0x528]))
#define MCF_FBCS3_CSCR (*(vuint32*)(&__MBAR[0x52C])) #define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&__MBAR[0x52C]))
#define MCF_FBCS4_CSAR (*(vuint32*)(&__MBAR[0x530])) #define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&__MBAR[0x530]))
#define MCF_FBCS4_CSMR (*(vuint32*)(&__MBAR[0x534])) #define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&__MBAR[0x534]))
#define MCF_FBCS4_CSCR (*(vuint32*)(&__MBAR[0x538])) #define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&__MBAR[0x538]))
#define MCF_FBCS5_CSAR (*(vuint32*)(&__MBAR[0x53C])) #define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&__MBAR[0x53C]))
#define MCF_FBCS5_CSMR (*(vuint32*)(&__MBAR[0x540])) #define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&__MBAR[0x540]))
#define MCF_FBCS5_CSCR (*(vuint32*)(&__MBAR[0x544])) #define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&__MBAR[0x544]))
#define MCF_FBCS_CSAR(x) (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)])) #define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&__MBAR[0x500 + ((x)*0xC)]))
#define MCF_FBCS_CSMR(x) (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)])) #define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&__MBAR[0x504 + ((x)*0xC)]))
#define MCF_FBCS_CSCR(x) (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)])) #define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&__MBAR[0x508 + ((x)*0xC)]))
/* Bit definitions and macros for MCF_FBCS_CSAR */ /* Bit definitions and macros for MCF_FBCS_CSAR */

540
include/MCF5475_FEC.h
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@@ -24,278 +24,278 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_FEC0_EIR (*(vuint32*)(&__MBAR[0x9004])) #define MCF_FEC0_EIR (*(volatile uint32_t*)(&__MBAR[0x9004]))
#define MCF_FEC0_EIMR (*(vuint32*)(&__MBAR[0x9008])) #define MCF_FEC0_EIMR (*(volatile uint32_t*)(&__MBAR[0x9008]))
#define MCF_FEC0_ECR (*(vuint32*)(&__MBAR[0x9024])) #define MCF_FEC0_ECR (*(volatile uint32_t*)(&__MBAR[0x9024]))
#define MCF_FEC0_MMFR (*(vuint32*)(&__MBAR[0x9040])) #define MCF_FEC0_MMFR (*(volatile uint32_t*)(&__MBAR[0x9040]))
#define MCF_FEC0_MSCR (*(vuint32*)(&__MBAR[0x9044])) #define MCF_FEC0_MSCR (*(volatile uint32_t*)(&__MBAR[0x9044]))
#define MCF_FEC0_MIBC (*(vuint32*)(&__MBAR[0x9064])) #define MCF_FEC0_MIBC (*(volatile uint32_t*)(&__MBAR[0x9064]))
#define MCF_FEC0_RCR (*(vuint32*)(&__MBAR[0x9084])) #define MCF_FEC0_RCR (*(volatile uint32_t*)(&__MBAR[0x9084]))
#define MCF_FEC0_RHR (*(vuint32*)(&__MBAR[0x9088])) #define MCF_FEC0_RHR (*(volatile uint32_t*)(&__MBAR[0x9088]))
#define MCF_FEC0_TCR (*(vuint32*)(&__MBAR[0x90C4])) #define MCF_FEC0_TCR (*(volatile uint32_t*)(&__MBAR[0x90C4]))
#define MCF_FEC0_PALR (*(vuint32*)(&__MBAR[0x90E4])) #define MCF_FEC0_PALR (*(volatile uint32_t*)(&__MBAR[0x90E4]))
#define MCF_FEC0_PAHR (*(vuint32*)(&__MBAR[0x90E8])) #define MCF_FEC0_PAHR (*(volatile uint32_t*)(&__MBAR[0x90E8]))
#define MCF_FEC0_OPD (*(vuint32*)(&__MBAR[0x90EC])) #define MCF_FEC0_OPD (*(volatile uint32_t*)(&__MBAR[0x90EC]))
#define MCF_FEC0_IAUR (*(vuint32*)(&__MBAR[0x9118])) #define MCF_FEC0_IAUR (*(volatile uint32_t*)(&__MBAR[0x9118]))
#define MCF_FEC0_IALR (*(vuint32*)(&__MBAR[0x911C])) #define MCF_FEC0_IALR (*(volatile uint32_t*)(&__MBAR[0x911C]))
#define MCF_FEC0_GAUR (*(vuint32*)(&__MBAR[0x9120])) #define MCF_FEC0_GAUR (*(volatile uint32_t*)(&__MBAR[0x9120]))
#define MCF_FEC0_GALR (*(vuint32*)(&__MBAR[0x9124])) #define MCF_FEC0_GALR (*(volatile uint32_t*)(&__MBAR[0x9124]))
#define MCF_FEC0_FECTFWR (*(vuint32*)(&__MBAR[0x9144])) #define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9144]))
#define MCF_FEC0_FECRFDR (*(vuint32*)(&__MBAR[0x9184])) #define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9184]))
#define MCF_FEC0_FECRFSR (*(vuint32*)(&__MBAR[0x9188])) #define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9188]))
#define MCF_FEC0_FECRFCR (*(vuint32*)(&__MBAR[0x918C])) #define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x918C]))
#define MCF_FEC0_FECRLRFP (*(vuint32*)(&__MBAR[0x9190])) #define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9190]))
#define MCF_FEC0_FECRLWFP (*(vuint32*)(&__MBAR[0x9194])) #define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9194]))
#define MCF_FEC0_FECRFAR (*(vuint32*)(&__MBAR[0x9198])) #define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9198]))
#define MCF_FEC0_FECRFRP (*(vuint32*)(&__MBAR[0x919C])) #define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x919C]))
#define MCF_FEC0_FECRFWP (*(vuint32*)(&__MBAR[0x91A0])) #define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x91A0]))
#define MCF_FEC0_FECTFDR (*(vuint32*)(&__MBAR[0x91A4])) #define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x91A4]))
#define MCF_FEC0_FECTFSR (*(vuint32*)(&__MBAR[0x91A8])) #define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x91A8]))
#define MCF_FEC0_FECTFCR (*(vuint32*)(&__MBAR[0x91AC])) #define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x91AC]))
#define MCF_FEC0_FECTLRFP (*(vuint32*)(&__MBAR[0x91B0])) #define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x91B0]))
#define MCF_FEC0_FECTLWFP (*(vuint32*)(&__MBAR[0x91B4])) #define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x91B4]))
#define MCF_FEC0_FECTFAR (*(vuint32*)(&__MBAR[0x91B8])) #define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x91B8]))
#define MCF_FEC0_FECTFRP (*(vuint32*)(&__MBAR[0x91BC])) #define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x91BC]))
#define MCF_FEC0_FECTFWP (*(vuint32*)(&__MBAR[0x91C0])) #define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x91C0]))
#define MCF_FEC0_FECFRST (*(vuint32*)(&__MBAR[0x91C4])) #define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&__MBAR[0x91C4]))
#define MCF_FEC0_FECCTCWR (*(vuint32*)(&__MBAR[0x91C8])) #define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x91C8]))
#define MCF_FEC0_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9200])) #define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9200]))
#define MCF_FEC0_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9204])) #define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9204]))
#define MCF_FEC0_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9208])) #define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9208]))
#define MCF_FEC0_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x920C])) #define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x920C]))
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9210])) #define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9210]))
#define MCF_FEC0_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9214])) #define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9214]))
#define MCF_FEC0_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9218])) #define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9218]))
#define MCF_FEC0_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x921C])) #define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x921C]))
#define MCF_FEC0_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9220])) #define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9220]))
#define MCF_FEC0_RMON_T_COL (*(vuint32*)(&__MBAR[0x9224])) #define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9224]))
#define MCF_FEC0_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9228])) #define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9228]))
#define MCF_FEC0_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x922C])) #define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x922C]))
#define MCF_FEC0_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9230])) #define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9230]))
#define MCF_FEC0_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9234])) #define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9234]))
#define MCF_FEC0_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9238])) #define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9238]))
#define MCF_FEC0_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x923C])) #define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x923C]))
#define MCF_FEC0_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9240])) #define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9240]))
#define MCF_FEC0_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9244])) #define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9244]))
#define MCF_FEC0_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9248])) #define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9248]))
#define MCF_FEC0_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x924C])) #define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x924C]))
#define MCF_FEC0_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9250])) #define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9250]))
#define MCF_FEC0_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9254])) #define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9254]))
#define MCF_FEC0_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9258])) #define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9258]))
#define MCF_FEC0_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x925C])) #define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x925C]))
#define MCF_FEC0_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9260])) #define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9260]))
#define MCF_FEC0_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9264])) #define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9264]))
#define MCF_FEC0_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9268])) #define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9268]))
#define MCF_FEC0_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x926C])) #define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x926C]))
#define MCF_FEC0_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9270])) #define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9270]))
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9274])) #define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9274]))
#define MCF_FEC0_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9280])) #define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9280]))
#define MCF_FEC0_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9284])) #define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9284]))
#define MCF_FEC0_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9288])) #define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9288]))
#define MCF_FEC0_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x928C])) #define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x928C]))
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9290])) #define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9290]))
#define MCF_FEC0_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9294])) #define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9294]))
#define MCF_FEC0_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9298])) #define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9298]))
#define MCF_FEC0_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x929C])) #define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x929C]))
#define MCF_FEC0_RMON_R_JAB (*(vuint32*)(&__MBAR[0x92A0])) #define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x92A0]))
#define MCF_FEC0_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x92A4])) #define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x92A4]))
#define MCF_FEC0_RMON_R_P64 (*(vuint32*)(&__MBAR[0x92A8])) #define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x92A8]))
#define MCF_FEC0_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x92AC])) #define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x92AC]))
#define MCF_FEC0_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x92B0])) #define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x92B0]))
#define MCF_FEC0_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x92B4])) #define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x92B4]))
#define MCF_FEC0_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x92B8])) #define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x92B8]))
#define MCF_FEC0_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x92BC])) #define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x92BC]))
#define MCF_FEC0_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x92C0])) #define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x92C0]))
#define MCF_FEC0_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x92C4])) #define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x92C4]))
#define MCF_FEC0_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x92C8])) #define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x92C8]))
#define MCF_FEC0_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x92CC])) #define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x92CC]))
#define MCF_FEC0_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x92D0])) #define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x92D0]))
#define MCF_FEC0_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x92D4])) #define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x92D4]))
#define MCF_FEC0_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x92D8])) #define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x92D8]))
#define MCF_FEC0_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x92DC])) #define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x92DC]))
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x92E0])) #define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x92E0]))
#define MCF_FEC1_EIR (*(vuint32*)(&__MBAR[0x9804])) #define MCF_FEC1_EIR (*(volatile uint32_t*)(&__MBAR[0x9804]))
#define MCF_FEC1_EIMR (*(vuint32*)(&__MBAR[0x9808])) #define MCF_FEC1_EIMR (*(volatile uint32_t*)(&__MBAR[0x9808]))
#define MCF_FEC1_ECR (*(vuint32*)(&__MBAR[0x9824])) #define MCF_FEC1_ECR (*(volatile uint32_t*)(&__MBAR[0x9824]))
#define MCF_FEC1_MMFR (*(vuint32*)(&__MBAR[0x9840])) #define MCF_FEC1_MMFR (*(volatile uint32_t*)(&__MBAR[0x9840]))
#define MCF_FEC1_MSCR (*(vuint32*)(&__MBAR[0x9844])) #define MCF_FEC1_MSCR (*(volatile uint32_t*)(&__MBAR[0x9844]))
#define MCF_FEC1_MIBC (*(vuint32*)(&__MBAR[0x9864])) #define MCF_FEC1_MIBC (*(volatile uint32_t*)(&__MBAR[0x9864]))
#define MCF_FEC1_RCR (*(vuint32*)(&__MBAR[0x9884])) #define MCF_FEC1_RCR (*(volatile uint32_t*)(&__MBAR[0x9884]))
#define MCF_FEC1_RHR (*(vuint32*)(&__MBAR[0x9888])) #define MCF_FEC1_RHR (*(volatile uint32_t*)(&__MBAR[0x9888]))
#define MCF_FEC1_TCR (*(vuint32*)(&__MBAR[0x98C4])) #define MCF_FEC1_TCR (*(volatile uint32_t*)(&__MBAR[0x98C4]))
#define MCF_FEC1_PALR (*(vuint32*)(&__MBAR[0x98E4])) #define MCF_FEC1_PALR (*(volatile uint32_t*)(&__MBAR[0x98E4]))
#define MCF_FEC1_PAHR (*(vuint32*)(&__MBAR[0x98E8])) #define MCF_FEC1_PAHR (*(volatile uint32_t*)(&__MBAR[0x98E8]))
#define MCF_FEC1_OPD (*(vuint32*)(&__MBAR[0x98EC])) #define MCF_FEC1_OPD (*(volatile uint32_t*)(&__MBAR[0x98EC]))
#define MCF_FEC1_IAUR (*(vuint32*)(&__MBAR[0x9918])) #define MCF_FEC1_IAUR (*(volatile uint32_t*)(&__MBAR[0x9918]))
#define MCF_FEC1_IALR (*(vuint32*)(&__MBAR[0x991C])) #define MCF_FEC1_IALR (*(volatile uint32_t*)(&__MBAR[0x991C]))
#define MCF_FEC1_GAUR (*(vuint32*)(&__MBAR[0x9920])) #define MCF_FEC1_GAUR (*(volatile uint32_t*)(&__MBAR[0x9920]))
#define MCF_FEC1_GALR (*(vuint32*)(&__MBAR[0x9924])) #define MCF_FEC1_GALR (*(volatile uint32_t*)(&__MBAR[0x9924]))
#define MCF_FEC1_FECTFWR (*(vuint32*)(&__MBAR[0x9944])) #define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9944]))
#define MCF_FEC1_FECRFDR (*(vuint32*)(&__MBAR[0x9984])) #define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9984]))
#define MCF_FEC1_FECRFSR (*(vuint32*)(&__MBAR[0x9988])) #define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9988]))
#define MCF_FEC1_FECRFCR (*(vuint32*)(&__MBAR[0x998C])) #define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x998C]))
#define MCF_FEC1_FECRLRFP (*(vuint32*)(&__MBAR[0x9990])) #define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9990]))
#define MCF_FEC1_FECRLWFP (*(vuint32*)(&__MBAR[0x9994])) #define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9994]))
#define MCF_FEC1_FECRFAR (*(vuint32*)(&__MBAR[0x9998])) #define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9998]))
#define MCF_FEC1_FECRFRP (*(vuint32*)(&__MBAR[0x999C])) #define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x999C]))
#define MCF_FEC1_FECRFWP (*(vuint32*)(&__MBAR[0x99A0])) #define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x99A0]))
#define MCF_FEC1_FECTFDR (*(vuint32*)(&__MBAR[0x99A4])) #define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x99A4]))
#define MCF_FEC1_FECTFSR (*(vuint32*)(&__MBAR[0x99A8])) #define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x99A8]))
#define MCF_FEC1_FECTFCR (*(vuint32*)(&__MBAR[0x99AC])) #define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x99AC]))
#define MCF_FEC1_FECTLRFP (*(vuint32*)(&__MBAR[0x99B0])) #define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x99B0]))
#define MCF_FEC1_FECTLWFP (*(vuint32*)(&__MBAR[0x99B4])) #define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x99B4]))
#define MCF_FEC1_FECTFAR (*(vuint32*)(&__MBAR[0x99B8])) #define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x99B8]))
#define MCF_FEC1_FECTFRP (*(vuint32*)(&__MBAR[0x99BC])) #define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x99BC]))
#define MCF_FEC1_FECTFWP (*(vuint32*)(&__MBAR[0x99C0])) #define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x99C0]))
#define MCF_FEC1_FECFRST (*(vuint32*)(&__MBAR[0x99C4])) #define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&__MBAR[0x99C4]))
#define MCF_FEC1_FECCTCWR (*(vuint32*)(&__MBAR[0x99C8])) #define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x99C8]))
#define MCF_FEC1_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9A00])) #define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A00]))
#define MCF_FEC1_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9A04])) #define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A04]))
#define MCF_FEC1_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9A08])) #define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A08]))
#define MCF_FEC1_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x9A0C])) #define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A0C]))
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A10])) #define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A10]))
#define MCF_FEC1_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A14])) #define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A14]))
#define MCF_FEC1_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9A18])) #define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A18]))
#define MCF_FEC1_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x9A1C])) #define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A1C]))
#define MCF_FEC1_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9A20])) #define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9A20]))
#define MCF_FEC1_RMON_T_COL (*(vuint32*)(&__MBAR[0x9A24])) #define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9A24]))
#define MCF_FEC1_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9A28])) #define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9A28]))
#define MCF_FEC1_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x9A2C])) #define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9A2C]))
#define MCF_FEC1_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9A30])) #define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9A30]))
#define MCF_FEC1_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9A34])) #define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9A34]))
#define MCF_FEC1_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9A38])) #define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9A38]))
#define MCF_FEC1_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x9A3C])) #define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9A3C]))
#define MCF_FEC1_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9A40])) #define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9A40]))
#define MCF_FEC1_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9A44])) #define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9A44]))
#define MCF_FEC1_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9A48])) #define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A48]))
#define MCF_FEC1_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x9A4C])) #define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9A4C]))
#define MCF_FEC1_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9A50])) #define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9A50]))
#define MCF_FEC1_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9A54])) #define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9A54]))
#define MCF_FEC1_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9A58])) #define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9A58]))
#define MCF_FEC1_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x9A5C])) #define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x9A5C]))
#define MCF_FEC1_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9A60])) #define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9A60]))
#define MCF_FEC1_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9A64])) #define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9A64]))
#define MCF_FEC1_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9A68])) #define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9A68]))
#define MCF_FEC1_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x9A6C])) #define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x9A6C]))
#define MCF_FEC1_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9A70])) #define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9A70]))
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9A74])) #define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9A74]))
#define MCF_FEC1_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9A80])) #define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9A80]))
#define MCF_FEC1_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9A84])) #define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A84]))
#define MCF_FEC1_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9A88])) #define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A88]))
#define MCF_FEC1_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x9A8C])) #define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A8C]))
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A90])) #define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A90]))
#define MCF_FEC1_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A94])) #define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A94]))
#define MCF_FEC1_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9A98])) #define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A98]))
#define MCF_FEC1_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x9A9C])) #define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A9C]))
#define MCF_FEC1_RMON_R_JAB (*(vuint32*)(&__MBAR[0x9AA0])) #define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x9AA0]))
#define MCF_FEC1_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x9AA4])) #define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x9AA4]))
#define MCF_FEC1_RMON_R_P64 (*(vuint32*)(&__MBAR[0x9AA8])) #define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x9AA8]))
#define MCF_FEC1_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x9AAC])) #define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9AAC]))
#define MCF_FEC1_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x9AB0])) #define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9AB0]))
#define MCF_FEC1_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x9AB4])) #define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9AB4]))
#define MCF_FEC1_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x9AB8])) #define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9AB8]))
#define MCF_FEC1_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x9ABC])) #define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9ABC]))
#define MCF_FEC1_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x9AC0])) #define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9AC0]))
#define MCF_FEC1_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x9AC4])) #define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9AC4]))
#define MCF_FEC1_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x9AC8])) #define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9AC8]))
#define MCF_FEC1_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x9ACC])) #define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9ACC]))
#define MCF_FEC1_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x9AD0])) #define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x9AD0]))
#define MCF_FEC1_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x9AD4])) #define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9AD4]))
#define MCF_FEC1_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x9AD8])) #define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x9AD8]))
#define MCF_FEC1_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x9ADC])) #define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9ADC]))
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x9AE0])) #define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9AE0]))
#define MCF_FEC_EIR(x) (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)])) #define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&__MBAR[0x9004 + ((x)*0x800)]))
#define MCF_FEC_EIMR(x) (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)])) #define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&__MBAR[0x9008 + ((x)*0x800)]))
#define MCF_FEC_ECR(x) (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)])) #define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&__MBAR[0x9024 + ((x)*0x800)]))
#define MCF_FEC_MMFR(x) (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)])) #define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&__MBAR[0x9040 + ((x)*0x800)]))
#define MCF_FEC_MSCR(x) (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)])) #define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&__MBAR[0x9044 + ((x)*0x800)]))
#define MCF_FEC_MIBC(x) (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)])) #define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&__MBAR[0x9064 + ((x)*0x800)]))
#define MCF_FEC_RCR(x) (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)])) #define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&__MBAR[0x9084 + ((x)*0x800)]))
#define MCF_FEC_RHR(x) (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)])) #define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&__MBAR[0x9088 + ((x)*0x800)]))
#define MCF_FEC_TCR(x) (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)])) #define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&__MBAR[0x90C4 + ((x)*0x800)]))
#define MCF_FEC_PALR(x) (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)])) #define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&__MBAR[0x90E4 + ((x)*0x800)]))
#define MCF_FEC_PAHR(x) (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)])) #define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&__MBAR[0x90E8 + ((x)*0x800)]))
#define MCF_FEC_OPD(x) (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)])) #define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&__MBAR[0x90EC + ((x)*0x800)]))
#define MCF_FEC_IAUR(x) (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)])) #define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9118 + ((x)*0x800)]))
#define MCF_FEC_IALR(x) (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)])) #define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&__MBAR[0x911C + ((x)*0x800)]))
#define MCF_FEC_GAUR(x) (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)])) #define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9120 + ((x)*0x800)]))
#define MCF_FEC_GALR(x) (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)])) #define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&__MBAR[0x9124 + ((x)*0x800)]))
#define MCF_FEC_FECTFWR(x) (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)])) #define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&__MBAR[0x9144 + ((x)*0x800)]))
#define MCF_FEC_FECRFDR(x) (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)])) #define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x9184 + ((x)*0x800)]))
#define MCF_FEC_FECRFSR(x) (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)])) #define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&__MBAR[0x9188 + ((x)*0x800)]))
#define MCF_FEC_FECRFCR(x) (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)])) #define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x918C + ((x)*0x800)]))
#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)])) #define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x9190 + ((x)*0x800)]))
#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)])) #define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x9194 + ((x)*0x800)]))
#define MCF_FEC_FECRFAR(x) (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)])) #define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&__MBAR[0x9198 + ((x)*0x800)]))
#define MCF_FEC_FECRFRP(x) (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)])) #define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&__MBAR[0x919C + ((x)*0x800)]))
#define MCF_FEC_FECRFWP(x) (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)])) #define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91A0 + ((x)*0x800)]))
#define MCF_FEC_FECTFDR(x) (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)])) #define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x91A4 + ((x)*0x800)]))
#define MCF_FEC_FECTFSR(x) (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)])) #define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&__MBAR[0x91A8 + ((x)*0x800)]))
#define MCF_FEC_FECTFCR(x) (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)])) #define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x91AC + ((x)*0x800)]))
#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)])) #define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B0 + ((x)*0x800)]))
#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)])) #define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B4 + ((x)*0x800)]))
#define MCF_FEC_FECTFAR(x) (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)])) #define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&__MBAR[0x91B8 + ((x)*0x800)]))
#define MCF_FEC_FECTFRP(x) (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)])) #define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&__MBAR[0x91BC + ((x)*0x800)]))
#define MCF_FEC_FECTFWP(x) (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)])) #define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91C0 + ((x)*0x800)]))
#define MCF_FEC_FECFRST(x) (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)])) #define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&__MBAR[0x91C4 + ((x)*0x800)]))
#define MCF_FEC_FECCTCWR(x) (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)])) #define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&__MBAR[0x91C8 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)])) #define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9200 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)])) #define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9204 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)])) #define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9208 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)])) #define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x920C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)])) #define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9210 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)])) #define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9214 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)])) #define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9218 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)])) #define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x921C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)])) #define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x9220 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)])) #define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&__MBAR[0x9224 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)])) #define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&__MBAR[0x9228 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)])) #define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x922C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)])) #define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x9230 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)])) #define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x9234 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)])) #define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x9238 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)])) #define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x923C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)])) #define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x9240 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)])) #define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x9244 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9248 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)])) #define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x924C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&__MBAR[0x9250 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9254 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&__MBAR[0x9258 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)])) #define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&__MBAR[0x925C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9260 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x9264 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&__MBAR[0x9268 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)])) #define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&__MBAR[0x926C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x9270 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)])) #define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x9274 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_DROP(x) (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)])) #define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9280 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)])) #define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9284 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)])) #define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9288 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)])) #define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x928C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)])) #define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9290 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)])) #define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9294 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)])) #define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9298 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)])) #define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x929C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)])) #define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x92A0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)])) #define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&__MBAR[0x92A4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)])) #define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&__MBAR[0x92A8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)])) #define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x92AC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)])) #define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x92B0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)])) #define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x92B4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P512TO1023(x) (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)])) #define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x92B8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)])) #define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x92BC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)])) #define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x92C0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)])) #define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x92C4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)])) #define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x92C8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)])) #define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92CC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)])) #define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&__MBAR[0x92D0 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)])) #define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x92D4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)])) #define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x92D8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)])) #define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x92DC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)])) #define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92E0 + ((x)*0x800)]))
/* Bit definitions and macros for MCF_FEC_EIR */ /* Bit definitions and macros for MCF_FEC_EIR */

104
include/MCF5475_GPIO.h
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@@ -24,70 +24,70 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00])) #define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10])) #define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20])) #define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30])) #define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01])) #define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11])) #define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21])) #define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31])) #define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA31]))
#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02])) #define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&__MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12])) #define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22])) #define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32])) #define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&__MBAR[0xA32]))
#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04])) #define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14])) #define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24])) #define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34])) #define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05])) #define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15])) #define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25])) #define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35])) #define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06])) #define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16])) #define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26])) #define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36])) #define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07])) #define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17])) #define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27])) #define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37])) #define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA37]))
#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08])) #define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18])) #define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28])) #define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38])) #define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA38]))
#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09])) #define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19])) #define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29])) #define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39])) #define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A])) #define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A])) #define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A])) #define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A])) #define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA3A]))
#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C])) #define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C])) #define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C])) #define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C])) #define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA3C]))
#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D])) #define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D])) #define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D])) #define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D])) #define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA3D]))
#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E])) #define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E])) #define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E])) #define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E])) #define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA3E]))

40
include/MCF5475_GPT.h
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@@ -24,30 +24,30 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_GPT0_GMS (*(vuint32*)(&__MBAR[0x800])) #define MCF_GPT0_GMS (*(volatile uint32_t*)(&__MBAR[0x800]))
#define MCF_GPT0_GCIR (*(vuint32*)(&__MBAR[0x804])) #define MCF_GPT0_GCIR (*(volatile uint32_t*)(&__MBAR[0x804]))
#define MCF_GPT0_GPWM (*(vuint32*)(&__MBAR[0x808])) #define MCF_GPT0_GPWM (*(volatile uint32_t*)(&__MBAR[0x808]))
#define MCF_GPT0_GSR (*(vuint32*)(&__MBAR[0x80C])) #define MCF_GPT0_GSR (*(volatile uint32_t*)(&__MBAR[0x80C]))
#define MCF_GPT1_GMS (*(vuint32*)(&__MBAR[0x810])) #define MCF_GPT1_GMS (*(volatile uint32_t*)(&__MBAR[0x810]))
#define MCF_GPT1_GCIR (*(vuint32*)(&__MBAR[0x814])) #define MCF_GPT1_GCIR (*(volatile uint32_t*)(&__MBAR[0x814]))
#define MCF_GPT1_GPWM (*(vuint32*)(&__MBAR[0x818])) #define MCF_GPT1_GPWM (*(volatile uint32_t*)(&__MBAR[0x818]))
#define MCF_GPT1_GSR (*(vuint32*)(&__MBAR[0x81C])) #define MCF_GPT1_GSR (*(volatile uint32_t*)(&__MBAR[0x81C]))
#define MCF_GPT2_GMS (*(vuint32*)(&__MBAR[0x820])) #define MCF_GPT2_GMS (*(volatile uint32_t*)(&__MBAR[0x820]))
#define MCF_GPT2_GCIR (*(vuint32*)(&__MBAR[0x824])) #define MCF_GPT2_GCIR (*(volatile uint32_t*)(&__MBAR[0x824]))
#define MCF_GPT2_GPWM (*(vuint32*)(&__MBAR[0x828])) #define MCF_GPT2_GPWM (*(volatile uint32_t*)(&__MBAR[0x828]))
#define MCF_GPT2_GSR (*(vuint32*)(&__MBAR[0x82C])) #define MCF_GPT2_GSR (*(volatile uint32_t*)(&__MBAR[0x82C]))
#define MCF_GPT3_GMS (*(vuint32*)(&__MBAR[0x830])) #define MCF_GPT3_GMS (*(volatile uint32_t*)(&__MBAR[0x830]))
#define MCF_GPT3_GCIR (*(vuint32*)(&__MBAR[0x834])) #define MCF_GPT3_GCIR (*(volatile uint32_t*)(&__MBAR[0x834]))
#define MCF_GPT3_GPWM (*(vuint32*)(&__MBAR[0x838])) #define MCF_GPT3_GPWM (*(volatile uint32_t*)(&__MBAR[0x838]))
#define MCF_GPT3_GSR (*(vuint32*)(&__MBAR[0x83C])) #define MCF_GPT3_GSR (*(volatile uint32_t*)(&__MBAR[0x83C]))
#define MCF_GPT_GMS(x) (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)])) #define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&__MBAR[0x800 + ((x)*0x10)]))
#define MCF_GPT_GCIR(x) (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)])) #define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&__MBAR[0x804 + ((x)*0x10)]))
#define MCF_GPT_GPWM(x) (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)])) #define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&__MBAR[0x808 + ((x)*0x10)]))
#define MCF_GPT_GSR(x) (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)])) #define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&__MBAR[0x80C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_GPT_GMS */ /* Bit definitions and macros for MCF_GPT_GMS */

12
include/MCF5475_I2C.h
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@@ -24,12 +24,12 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_I2C_I2ADR (*(vuint8 *)(&__MBAR[0x8F00])) #define MCF_I2C_I2ADR (*(volatile uint8_t *)(&__MBAR[0x8F00]))
#define MCF_I2C_I2FDR (*(vuint8 *)(&__MBAR[0x8F04])) #define MCF_I2C_I2FDR (*(volatile uint8_t *)(&__MBAR[0x8F04]))
#define MCF_I2C_I2CR (*(vuint8 *)(&__MBAR[0x8F08])) #define MCF_I2C_I2CR (*(volatile uint8_t *)(&__MBAR[0x8F08]))
#define MCF_I2C_I2SR (*(vuint8 *)(&__MBAR[0x8F0C])) #define MCF_I2C_I2SR (*(volatile uint8_t *)(&__MBAR[0x8F0C]))
#define MCF_I2C_I2DR (*(vuint8 *)(&__MBAR[0x8F10])) #define MCF_I2C_I2DR (*(volatile uint8_t *)(&__MBAR[0x8F10]))
#define MCF_I2C_I2ICR (*(vuint8 *)(&__MBAR[0x8F20])) #define MCF_I2C_I2ICR (*(volatile uint8_t *)(&__MBAR[0x8F20]))

162
include/MCF5475_INTC.h
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@@ -24,87 +24,87 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_INTC_IPRH (*(vuint32*)(&__MBAR[0x700])) #define MCF_INTC_IPRH (*(volatile uint32_t*)(&__MBAR[0x700]))
#define MCF_INTC_IPRL (*(vuint32*)(&__MBAR[0x704])) #define MCF_INTC_IPRL (*(volatile uint32_t*)(&__MBAR[0x704]))
#define MCF_INTC_IMRH (*(vuint32*)(&__MBAR[0x708])) #define MCF_INTC_IMRH (*(volatile uint32_t*)(&__MBAR[0x708]))
#define MCF_INTC_IMRL (*(vuint32*)(&__MBAR[0x70C])) #define MCF_INTC_IMRL (*(volatile uint32_t*)(&__MBAR[0x70C]))
#define MCF_INTC_INTFRCH (*(vuint32*)(&__MBAR[0x710])) #define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&__MBAR[0x710]))
#define MCF_INTC_INTFRCL (*(vuint32*)(&__MBAR[0x714])) #define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&__MBAR[0x714]))
#define MCF_INTC_IRLR (*(vuint8 *)(&__MBAR[0x718])) #define MCF_INTC_IRLR (*(volatile uint8_t *)(&__MBAR[0x718]))
#define MCF_INTC_IACKLPR (*(vuint8 *)(&__MBAR[0x719])) #define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&__MBAR[0x719]))
#define MCF_INTC_ICR01 (*(vuint8 *)(&__MBAR[0x741])) #define MCF_INTC_ICR01 (*(volatile uint8_t *)(&__MBAR[0x741]))
#define MCF_INTC_ICR02 (*(vuint8 *)(&__MBAR[0x742])) #define MCF_INTC_ICR02 (*(volatile uint8_t *)(&__MBAR[0x742]))
#define MCF_INTC_ICR03 (*(vuint8 *)(&__MBAR[0x743])) #define MCF_INTC_ICR03 (*(volatile uint8_t *)(&__MBAR[0x743]))
#define MCF_INTC_ICR04 (*(vuint8 *)(&__MBAR[0x744])) #define MCF_INTC_ICR04 (*(volatile uint8_t *)(&__MBAR[0x744]))
#define MCF_INTC_ICR05 (*(vuint8 *)(&__MBAR[0x745])) #define MCF_INTC_ICR05 (*(volatile uint8_t *)(&__MBAR[0x745]))
#define MCF_INTC_ICR06 (*(vuint8 *)(&__MBAR[0x746])) #define MCF_INTC_ICR06 (*(volatile uint8_t *)(&__MBAR[0x746]))
#define MCF_INTC_ICR07 (*(vuint8 *)(&__MBAR[0x747])) #define MCF_INTC_ICR07 (*(volatile uint8_t *)(&__MBAR[0x747]))
#define MCF_INTC_ICR08 (*(vuint8 *)(&__MBAR[0x748])) #define MCF_INTC_ICR08 (*(volatile uint8_t *)(&__MBAR[0x748]))
#define MCF_INTC_ICR09 (*(vuint8 *)(&__MBAR[0x749])) #define MCF_INTC_ICR09 (*(volatile uint8_t *)(&__MBAR[0x749]))
#define MCF_INTC_ICR10 (*(vuint8 *)(&__MBAR[0x74A])) #define MCF_INTC_ICR10 (*(volatile uint8_t *)(&__MBAR[0x74A]))
#define MCF_INTC_ICR11 (*(vuint8 *)(&__MBAR[0x74B])) #define MCF_INTC_ICR11 (*(volatile uint8_t *)(&__MBAR[0x74B]))
#define MCF_INTC_ICR12 (*(vuint8 *)(&__MBAR[0x74C])) #define MCF_INTC_ICR12 (*(volatile uint8_t *)(&__MBAR[0x74C]))
#define MCF_INTC_ICR13 (*(vuint8 *)(&__MBAR[0x74D])) #define MCF_INTC_ICR13 (*(volatile uint8_t *)(&__MBAR[0x74D]))
#define MCF_INTC_ICR14 (*(vuint8 *)(&__MBAR[0x74E])) #define MCF_INTC_ICR14 (*(volatile uint8_t *)(&__MBAR[0x74E]))
#define MCF_INTC_ICR15 (*(vuint8 *)(&__MBAR[0x74F])) #define MCF_INTC_ICR15 (*(volatile uint8_t *)(&__MBAR[0x74F]))
#define MCF_INTC_ICR16 (*(vuint8 *)(&__MBAR[0x750])) #define MCF_INTC_ICR16 (*(volatile uint8_t *)(&__MBAR[0x750]))
#define MCF_INTC_ICR17 (*(vuint8 *)(&__MBAR[0x751])) #define MCF_INTC_ICR17 (*(volatile uint8_t *)(&__MBAR[0x751]))
#define MCF_INTC_ICR18 (*(vuint8 *)(&__MBAR[0x752])) #define MCF_INTC_ICR18 (*(volatile uint8_t *)(&__MBAR[0x752]))
#define MCF_INTC_ICR19 (*(vuint8 *)(&__MBAR[0x753])) #define MCF_INTC_ICR19 (*(volatile uint8_t *)(&__MBAR[0x753]))
#define MCF_INTC_ICR20 (*(vuint8 *)(&__MBAR[0x754])) #define MCF_INTC_ICR20 (*(volatile uint8_t *)(&__MBAR[0x754]))
#define MCF_INTC_ICR21 (*(vuint8 *)(&__MBAR[0x755])) #define MCF_INTC_ICR21 (*(volatile uint8_t *)(&__MBAR[0x755]))
#define MCF_INTC_ICR22 (*(vuint8 *)(&__MBAR[0x756])) #define MCF_INTC_ICR22 (*(volatile uint8_t *)(&__MBAR[0x756]))
#define MCF_INTC_ICR23 (*(vuint8 *)(&__MBAR[0x757])) #define MCF_INTC_ICR23 (*(volatile uint8_t *)(&__MBAR[0x757]))
#define MCF_INTC_ICR24 (*(vuint8 *)(&__MBAR[0x758])) #define MCF_INTC_ICR24 (*(volatile uint8_t *)(&__MBAR[0x758]))
#define MCF_INTC_ICR25 (*(vuint8 *)(&__MBAR[0x759])) #define MCF_INTC_ICR25 (*(volatile uint8_t *)(&__MBAR[0x759]))
#define MCF_INTC_ICR26 (*(vuint8 *)(&__MBAR[0x75A])) #define MCF_INTC_ICR26 (*(volatile uint8_t *)(&__MBAR[0x75A]))
#define MCF_INTC_ICR27 (*(vuint8 *)(&__MBAR[0x75B])) #define MCF_INTC_ICR27 (*(volatile uint8_t *)(&__MBAR[0x75B]))
#define MCF_INTC_ICR28 (*(vuint8 *)(&__MBAR[0x75C])) #define MCF_INTC_ICR28 (*(volatile uint8_t *)(&__MBAR[0x75C]))
#define MCF_INTC_ICR29 (*(vuint8 *)(&__MBAR[0x75D])) #define MCF_INTC_ICR29 (*(volatile uint8_t *)(&__MBAR[0x75D]))
#define MCF_INTC_ICR30 (*(vuint8 *)(&__MBAR[0x75E])) #define MCF_INTC_ICR30 (*(volatile uint8_t *)(&__MBAR[0x75E]))
#define MCF_INTC_ICR31 (*(vuint8 *)(&__MBAR[0x75F])) #define MCF_INTC_ICR31 (*(volatile uint8_t *)(&__MBAR[0x75F]))
#define MCF_INTC_ICR32 (*(vuint8 *)(&__MBAR[0x760])) #define MCF_INTC_ICR32 (*(volatile uint8_t *)(&__MBAR[0x760]))
#define MCF_INTC_ICR33 (*(vuint8 *)(&__MBAR[0x761])) #define MCF_INTC_ICR33 (*(volatile uint8_t *)(&__MBAR[0x761]))
#define MCF_INTC_ICR34 (*(vuint8 *)(&__MBAR[0x762])) #define MCF_INTC_ICR34 (*(volatile uint8_t *)(&__MBAR[0x762]))
#define MCF_INTC_ICR35 (*(vuint8 *)(&__MBAR[0x763])) #define MCF_INTC_ICR35 (*(volatile uint8_t *)(&__MBAR[0x763]))
#define MCF_INTC_ICR36 (*(vuint8 *)(&__MBAR[0x764])) #define MCF_INTC_ICR36 (*(volatile uint8_t *)(&__MBAR[0x764]))
#define MCF_INTC_ICR37 (*(vuint8 *)(&__MBAR[0x765])) #define MCF_INTC_ICR37 (*(volatile uint8_t *)(&__MBAR[0x765]))
#define MCF_INTC_ICR38 (*(vuint8 *)(&__MBAR[0x766])) #define MCF_INTC_ICR38 (*(volatile uint8_t *)(&__MBAR[0x766]))
#define MCF_INTC_ICR39 (*(vuint8 *)(&__MBAR[0x767])) #define MCF_INTC_ICR39 (*(volatile uint8_t *)(&__MBAR[0x767]))
#define MCF_INTC_ICR40 (*(vuint8 *)(&__MBAR[0x768])) #define MCF_INTC_ICR40 (*(volatile uint8_t *)(&__MBAR[0x768]))
#define MCF_INTC_ICR41 (*(vuint8 *)(&__MBAR[0x769])) #define MCF_INTC_ICR41 (*(volatile uint8_t *)(&__MBAR[0x769]))
#define MCF_INTC_ICR42 (*(vuint8 *)(&__MBAR[0x76A])) #define MCF_INTC_ICR42 (*(volatile uint8_t *)(&__MBAR[0x76A]))
#define MCF_INTC_ICR43 (*(vuint8 *)(&__MBAR[0x76B])) #define MCF_INTC_ICR43 (*(volatile uint8_t *)(&__MBAR[0x76B]))
#define MCF_INTC_ICR44 (*(vuint8 *)(&__MBAR[0x76C])) #define MCF_INTC_ICR44 (*(volatile uint8_t *)(&__MBAR[0x76C]))
#define MCF_INTC_ICR45 (*(vuint8 *)(&__MBAR[0x76D])) #define MCF_INTC_ICR45 (*(volatile uint8_t *)(&__MBAR[0x76D]))
#define MCF_INTC_ICR46 (*(vuint8 *)(&__MBAR[0x76E])) #define MCF_INTC_ICR46 (*(volatile uint8_t *)(&__MBAR[0x76E]))
#define MCF_INTC_ICR47 (*(vuint8 *)(&__MBAR[0x76F])) #define MCF_INTC_ICR47 (*(volatile uint8_t *)(&__MBAR[0x76F]))
#define MCF_INTC_ICR48 (*(vuint8 *)(&__MBAR[0x770])) #define MCF_INTC_ICR48 (*(volatile uint8_t *)(&__MBAR[0x770]))
#define MCF_INTC_ICR49 (*(vuint8 *)(&__MBAR[0x771])) #define MCF_INTC_ICR49 (*(volatile uint8_t *)(&__MBAR[0x771]))
#define MCF_INTC_ICR50 (*(vuint8 *)(&__MBAR[0x772])) #define MCF_INTC_ICR50 (*(volatile uint8_t *)(&__MBAR[0x772]))
#define MCF_INTC_ICR51 (*(vuint8 *)(&__MBAR[0x773])) #define MCF_INTC_ICR51 (*(volatile uint8_t *)(&__MBAR[0x773]))
#define MCF_INTC_ICR52 (*(vuint8 *)(&__MBAR[0x774])) #define MCF_INTC_ICR52 (*(volatile uint8_t *)(&__MBAR[0x774]))
#define MCF_INTC_ICR53 (*(vuint8 *)(&__MBAR[0x775])) #define MCF_INTC_ICR53 (*(volatile uint8_t *)(&__MBAR[0x775]))
#define MCF_INTC_ICR54 (*(vuint8 *)(&__MBAR[0x776])) #define MCF_INTC_ICR54 (*(volatile uint8_t *)(&__MBAR[0x776]))
#define MCF_INTC_ICR55 (*(vuint8 *)(&__MBAR[0x777])) #define MCF_INTC_ICR55 (*(volatile uint8_t *)(&__MBAR[0x777]))
#define MCF_INTC_ICR56 (*(vuint8 *)(&__MBAR[0x778])) #define MCF_INTC_ICR56 (*(volatile uint8_t *)(&__MBAR[0x778]))
#define MCF_INTC_ICR57 (*(vuint8 *)(&__MBAR[0x779])) #define MCF_INTC_ICR57 (*(volatile uint8_t *)(&__MBAR[0x779]))
#define MCF_INTC_ICR58 (*(vuint8 *)(&__MBAR[0x77A])) #define MCF_INTC_ICR58 (*(volatile uint8_t *)(&__MBAR[0x77A]))
#define MCF_INTC_ICR59 (*(vuint8 *)(&__MBAR[0x77B])) #define MCF_INTC_ICR59 (*(volatile uint8_t *)(&__MBAR[0x77B]))
#define MCF_INTC_ICR60 (*(vuint8 *)(&__MBAR[0x77C])) #define MCF_INTC_ICR60 (*(volatile uint8_t *)(&__MBAR[0x77C]))
#define MCF_INTC_ICR61 (*(vuint8 *)(&__MBAR[0x77D])) #define MCF_INTC_ICR61 (*(volatile uint8_t *)(&__MBAR[0x77D]))
#define MCF_INTC_ICR62 (*(vuint8 *)(&__MBAR[0x77E])) #define MCF_INTC_ICR62 (*(volatile uint8_t *)(&__MBAR[0x77E]))
#define MCF_INTC_ICR63 (*(vuint8 *)(&__MBAR[0x77F])) #define MCF_INTC_ICR63 (*(volatile uint8_t *)(&__MBAR[0x77F]))
#define MCF_INTC_SWIACK (*(vuint8 *)(&__MBAR[0x7E0])) #define MCF_INTC_SWIACK (*(volatile uint8_t *)(&__MBAR[0x7E0]))
#define MCF_INTC_L1IACK (*(vuint8 *)(&__MBAR[0x7E4])) #define MCF_INTC_L1IACK (*(volatile uint8_t *)(&__MBAR[0x7E4]))
#define MCF_INTC_L2IACK (*(vuint8 *)(&__MBAR[0x7E8])) #define MCF_INTC_L2IACK (*(volatile uint8_t *)(&__MBAR[0x7E8]))
#define MCF_INTC_L3IACK (*(vuint8 *)(&__MBAR[0x7EC])) #define MCF_INTC_L3IACK (*(volatile uint8_t *)(&__MBAR[0x7EC]))
#define MCF_INTC_L4IACK (*(vuint8 *)(&__MBAR[0x7F0])) #define MCF_INTC_L4IACK (*(volatile uint8_t *)(&__MBAR[0x7F0]))
#define MCF_INTC_L5IACK (*(vuint8 *)(&__MBAR[0x7F4])) #define MCF_INTC_L5IACK (*(volatile uint8_t *)(&__MBAR[0x7F4]))
#define MCF_INTC_L6IACK (*(vuint8 *)(&__MBAR[0x7F8])) #define MCF_INTC_L6IACK (*(volatile uint8_t *)(&__MBAR[0x7F8]))
#define MCF_INTC_L7IACK (*(vuint8 *)(&__MBAR[0x7FC])) #define MCF_INTC_L7IACK (*(volatile uint8_t *)(&__MBAR[0x7FC]))
#define MCF_INTC_ICR(x) (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)])) #define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&__MBAR[0x741 + ((x-1)*0x1)]))
#define MCF_INTC_LIACK(x) (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) #define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&__MBAR[0x7E4 + ((x-1)*0x4)]))

12
include/MCF5475_MMU.h
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@@ -24,12 +24,12 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_MMU_MMUCR (*(vuint32*)(&__MMUBAR[0])) #define MCF_MMU_MMUCR (*(volatile uint32_t*)(&__MMUBAR[0]))
#define MCF_MMU_MMUOR (*(vuint32*)(&__MMUBAR[0x4])) #define MCF_MMU_MMUOR (*(volatile uint32_t*)(&__MMUBAR[0x4]))
#define MCF_MMU_MMUSR (*(vuint32*)(&__MMUBAR[0x8])) #define MCF_MMU_MMUSR (*(volatile uint32_t*)(&__MMUBAR[0x8]))
#define MCF_MMU_MMUAR (*(vuint32*)(&__MMUBAR[0x10])) #define MCF_MMU_MMUAR (*(volatile uint32_t*)(&__MMUBAR[0x10]))
#define MCF_MMU_MMUTR (*(vuint32*)(&__MMUBAR[0x14])) #define MCF_MMU_MMUTR (*(volatile uint32_t*)(&__MMUBAR[0x14]))
#define MCF_MMU_MMUDR (*(vuint32*)(&__MMUBAR[0x18])) #define MCF_MMU_MMUDR (*(volatile uint32_t*)(&__MMUBAR[0x18]))
/* Bit definitions and macros for MCF_MMU_MMUCR */ /* Bit definitions and macros for MCF_MMU_MMUCR */

24
include/MCF5475_PAD.h
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@@ -24,18 +24,18 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_PAD_PAR_FBCTL (*(vuint16*)(&__MBAR[0xA40])) #define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&__MBAR[0xA40]))
#define MCF_PAD_PAR_FBCS (*(vuint8 *)(&__MBAR[0xA42])) #define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA42]))
#define MCF_PAD_PAR_DMA (*(vuint8 *)(&__MBAR[0xA43])) #define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&__MBAR[0xA43]))
#define MCF_PAD_PAR_FECI2CIRQ (*(vuint16*)(&__MBAR[0xA44])) #define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&__MBAR[0xA44]))
#define MCF_PAD_PAR_PCIBG (*(vuint16*)(&__MBAR[0xA48])) #define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&__MBAR[0xA48]))
#define MCF_PAD_PAR_PCIBR (*(vuint16*)(&__MBAR[0xA4A])) #define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&__MBAR[0xA4A]))
#define MCF_PAD_PAR_PSC3 (*(vuint8 *)(&__MBAR[0xA4C])) #define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&__MBAR[0xA4C]))
#define MCF_PAD_PAR_PSC2 (*(vuint8 *)(&__MBAR[0xA4D])) #define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&__MBAR[0xA4D]))
#define MCF_PAD_PAR_PSC1 (*(vuint8 *)(&__MBAR[0xA4E])) #define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&__MBAR[0xA4E]))
#define MCF_PAD_PAR_PSC0 (*(vuint8 *)(&__MBAR[0xA4F])) #define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&__MBAR[0xA4F]))
#define MCF_PAD_PAR_DSPI (*(vuint16*)(&__MBAR[0xA50])) #define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&__MBAR[0xA50]))
#define MCF_PAD_PAR_TIMER (*(vuint8 *)(&__MBAR[0xA52])) #define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&__MBAR[0xA52]))
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ /* Bit definitions and macros for MCF_PAD_PAR_FBCTL */

94
include/MCF5475_PCI.h
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@@ -24,53 +24,53 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_PCI_PCIIDR (*(vuint32*)(&__MBAR[0xB00])) #define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&__MBAR[0xB00]))
#define MCF_PCI_PCISCR (*(vuint32*)(&__MBAR[0xB04])) #define MCF_PCI_PCISCR (*(volatile uint32_t*)(&__MBAR[0xB04]))
#define MCF_PCI_PCICCRIR (*(vuint32*)(&__MBAR[0xB08])) #define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&__MBAR[0xB08]))
#define MCF_PCI_PCICR1 (*(vuint32*)(&__MBAR[0xB0C])) #define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&__MBAR[0xB0C]))
#define MCF_PCI_PCIBAR0 (*(vuint32*)(&__MBAR[0xB10])) #define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&__MBAR[0xB10]))
#define MCF_PCI_PCIBAR1 (*(vuint32*)(&__MBAR[0xB14])) #define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&__MBAR[0xB14]))
#define MCF_PCI_PCICCPR (*(vuint32*)(&__MBAR[0xB28])) #define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&__MBAR[0xB28]))
#define MCF_PCI_PCISID (*(vuint32*)(&__MBAR[0xB2C])) #define MCF_PCI_PCISID (*(volatile uint32_t*)(&__MBAR[0xB2C]))
#define MCF_PCI_PCICR2 (*(vuint32*)(&__MBAR[0xB3C])) #define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&__MBAR[0xB3C]))
#define MCF_PCI_PCIGSCR (*(vuint32*)(&__MBAR[0xB60])) #define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&__MBAR[0xB60]))
#define MCF_PCI_PCITBATR0 (*(vuint32*)(&__MBAR[0xB64])) #define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&__MBAR[0xB64]))
#define MCF_PCI_PCITBATR1 (*(vuint32*)(&__MBAR[0xB68])) #define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&__MBAR[0xB68]))
#define MCF_PCI_PCITCR (*(vuint32*)(&__MBAR[0xB6C])) #define MCF_PCI_PCITCR (*(volatile uint32_t*)(&__MBAR[0xB6C]))
#define MCF_PCI_PCIIW0BTAR (*(vuint32*)(&__MBAR[0xB70])) #define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&__MBAR[0xB70]))
#define MCF_PCI_PCIIW1BTAR (*(vuint32*)(&__MBAR[0xB74])) #define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&__MBAR[0xB74]))
#define MCF_PCI_PCIIW2BTAR (*(vuint32*)(&__MBAR[0xB78])) #define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&__MBAR[0xB78]))
#define MCF_PCI_PCIIWCR (*(vuint32*)(&__MBAR[0xB80])) #define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&__MBAR[0xB80]))
#define MCF_PCI_PCIICR (*(vuint32*)(&__MBAR[0xB84])) #define MCF_PCI_PCIICR (*(volatile uint32_t*)(&__MBAR[0xB84]))
#define MCF_PCI_PCIISR (*(vuint32*)(&__MBAR[0xB88])) #define MCF_PCI_PCIISR (*(volatile uint32_t*)(&__MBAR[0xB88]))
#define MCF_PCI_PCICAR (*(vuint32*)(&__MBAR[0xBF8])) #define MCF_PCI_PCICAR (*(volatile uint32_t*)(&__MBAR[0xBF8]))
#define MCF_PCI_PCITPSR (*(vuint32*)(&__MBAR[0x8400])) #define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&__MBAR[0x8400]))
#define MCF_PCI_PCITSAR (*(vuint32*)(&__MBAR[0x8404])) #define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&__MBAR[0x8404]))
#define MCF_PCI_PCITTCR (*(vuint32*)(&__MBAR[0x8408])) #define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&__MBAR[0x8408]))
#define MCF_PCI_PCITER (*(vuint32*)(&__MBAR[0x840C])) #define MCF_PCI_PCITER (*(volatile uint32_t*)(&__MBAR[0x840C]))
#define MCF_PCI_PCITNAR (*(vuint32*)(&__MBAR[0x8410])) #define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&__MBAR[0x8410]))
#define MCF_PCI_PCITLWR (*(vuint32*)(&__MBAR[0x8414])) #define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&__MBAR[0x8414]))
#define MCF_PCI_PCITDCR (*(vuint32*)(&__MBAR[0x8418])) #define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&__MBAR[0x8418]))
#define MCF_PCI_PCITSR (*(vuint32*)(&__MBAR[0x841C])) #define MCF_PCI_PCITSR (*(volatile uint32_t*)(&__MBAR[0x841C]))
#define MCF_PCI_PCITFDR (*(vuint32*)(&__MBAR[0x8440])) #define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&__MBAR[0x8440]))
#define MCF_PCI_PCITFSR (*(vuint32*)(&__MBAR[0x8444])) #define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&__MBAR[0x8444]))
#define MCF_PCI_PCITFCR (*(vuint32*)(&__MBAR[0x8448])) #define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&__MBAR[0x8448]))
#define MCF_PCI_PCITFAR (*(vuint32*)(&__MBAR[0x844C])) #define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&__MBAR[0x844C]))
#define MCF_PCI_PCITFRPR (*(vuint32*)(&__MBAR[0x8450])) #define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&__MBAR[0x8450]))
#define MCF_PCI_PCITFWPR (*(vuint32*)(&__MBAR[0x8454])) #define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&__MBAR[0x8454]))
#define MCF_PCI_PCIRPSR (*(vuint32*)(&__MBAR[0x8480])) #define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&__MBAR[0x8480]))
#define MCF_PCI_PCIRSAR (*(vuint32*)(&__MBAR[0x8484])) #define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&__MBAR[0x8484]))
#define MCF_PCI_PCIRTCR (*(vuint32*)(&__MBAR[0x8488])) #define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&__MBAR[0x8488]))
#define MCF_PCI_PCIRER (*(vuint32*)(&__MBAR[0x848C])) #define MCF_PCI_PCIRER (*(volatile uint32_t*)(&__MBAR[0x848C]))
#define MCF_PCI_PCIRNAR (*(vuint32*)(&__MBAR[0x8490])) #define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&__MBAR[0x8490]))
#define MCF_PCI_PCIRDCR (*(vuint32*)(&__MBAR[0x8498])) #define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&__MBAR[0x8498]))
#define MCF_PCI_PCIRSR (*(vuint32*)(&__MBAR[0x849C])) #define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&__MBAR[0x849C]))
#define MCF_PCI_PCIRFDR (*(vuint32*)(&__MBAR[0x84C0])) #define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&__MBAR[0x84C0]))
#define MCF_PCI_PCIRFSR (*(vuint32*)(&__MBAR[0x84C4])) #define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&__MBAR[0x84C4]))
#define MCF_PCI_PCIRFCR (*(vuint32*)(&__MBAR[0x84C8])) #define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&__MBAR[0x84C8]))
#define MCF_PCI_PCIRFAR (*(vuint32*)(&__MBAR[0x84CC])) #define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&__MBAR[0x84CC]))
#define MCF_PCI_PCIRFRPR (*(vuint32*)(&__MBAR[0x84D0])) #define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&__MBAR[0x84D0]))
#define MCF_PCI_PCIRFWPR (*(vuint32*)(&__MBAR[0x84D4])) #define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&__MBAR[0x84D4]))
/* Bit definitions and macros for MCF_PCI_PCIIDR */ /* Bit definitions and macros for MCF_PCI_PCIIDR */

4
include/MCF5475_PCIARB.h
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@@ -24,8 +24,8 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_PCIARB_PACR (*(vuint32*)(&__MBAR[0xC00])) #define MCF_PCIARB_PACR (*(volatile uint32_t*)(&__MBAR[0xC00]))
#define MCF_PCIARB_PASR (*(vuint32*)(&__MBAR[0xC04])) #define MCF_PCIARB_PASR (*(volatile uint32_t*)(&__MBAR[0xC04]))
/* Bit definitions and macros for MCF_PCIARB_PACR */ /* Bit definitions and macros for MCF_PCIARB_PACR */

438
include/MCF5475_PSC.h
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@@ -24,229 +24,229 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_PSC0_PSCMR2 (*(vuint8 *)(&__MBAR[0x8600])) #define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8600]))
#define MCF_PSC0_PSCMR1 (*(vuint8 *)(&__MBAR[0x8600])) #define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8600]))
#define MCF_PSC0_PSCCSR (*(vuint8 *)(&__MBAR[0x8604])) #define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8604]))
#define MCF_PSC0_PSCSR (*(vuint16*)(&__MBAR[0x8604])) #define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8604]))
#define MCF_PSC0_PSCCR (*(vuint8 *)(&__MBAR[0x8608])) #define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8608]))
#define MCF_PSC0_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x860C])) #define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C]))
#define MCF_PSC0_PSCIPCR (*(vuint8 *)(&__MBAR[0x8610])) #define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8610]))
#define MCF_PSC0_PSCACR (*(vuint8 *)(&__MBAR[0x8610])) #define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8610]))
#define MCF_PSC0_PSCIMR (*(vuint16*)(&__MBAR[0x8614])) #define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8614]))
#define MCF_PSC0_PSCISR (*(vuint16*)(&__MBAR[0x8614])) #define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8614]))
#define MCF_PSC0_PSCCTUR (*(vuint8 *)(&__MBAR[0x8618])) #define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8618]))
#define MCF_PSC0_PSCCTLR (*(vuint8 *)(&__MBAR[0x861C])) #define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x861C]))
#define MCF_PSC0_PSCIP (*(vuint8 *)(&__MBAR[0x8634])) #define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8634]))
#define MCF_PSC0_PSCOPSET (*(vuint8 *)(&__MBAR[0x8638])) #define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8638]))
#define MCF_PSC0_PSCOPRESET (*(vuint8 *)(&__MBAR[0x863C])) #define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x863C]))
#define MCF_PSC0_PSCSICR (*(vuint8 *)(&__MBAR[0x8640])) #define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8640]))
#define MCF_PSC0_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8644])) #define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8644]))
#define MCF_PSC0_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8648])) #define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8648]))
#define MCF_PSC0_PSCIRSDR (*(vuint8 *)(&__MBAR[0x864C])) #define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x864C]))
#define MCF_PSC0_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8650])) #define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8650]))
#define MCF_PSC0_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8654])) #define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8654]))
#define MCF_PSC0_PSCRFCNT (*(vuint16*)(&__MBAR[0x8658])) #define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8658]))
#define MCF_PSC0_PSCTFCNT (*(vuint16*)(&__MBAR[0x865C])) #define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x865C]))
#define MCF_PSC0_PSCRFDR (*(vuint32*)(&__MBAR[0x8660])) #define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8660]))
#define MCF_PSC0_PSCRFSR (*(vuint16*)(&__MBAR[0x8664])) #define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8664]))
#define MCF_PSC0_PSCRFCR (*(vuint32*)(&__MBAR[0x8668])) #define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8668]))
#define MCF_PSC0_PSCRFAR (*(vuint16*)(&__MBAR[0x866E])) #define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x866E]))
#define MCF_PSC0_PSCRFRP (*(vuint16*)(&__MBAR[0x8672])) #define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8672]))
#define MCF_PSC0_PSCRFWP (*(vuint16*)(&__MBAR[0x8676])) #define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8676]))
#define MCF_PSC0_PSCRLRFP (*(vuint16*)(&__MBAR[0x867A])) #define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x867A]))
#define MCF_PSC0_PSCRLWFP (*(vuint16*)(&__MBAR[0x867E])) #define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x867E]))
#define MCF_PSC0_PSCTFDR (*(vuint32*)(&__MBAR[0x8680])) #define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8680]))
#define MCF_PSC0_PSCTFSR (*(vuint16*)(&__MBAR[0x8684])) #define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8684]))
#define MCF_PSC0_PSCTFCR (*(vuint32*)(&__MBAR[0x8688])) #define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8688]))
#define MCF_PSC0_PSCTFAR (*(vuint16*)(&__MBAR[0x868E])) #define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x868E]))
#define MCF_PSC0_PSCTFRP (*(vuint16*)(&__MBAR[0x8692])) #define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8692]))
#define MCF_PSC0_PSCTFWP (*(vuint16*)(&__MBAR[0x8696])) #define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8696]))
#define MCF_PSC0_PSCTLRFP (*(vuint16*)(&__MBAR[0x869A])) #define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x869A]))
#define MCF_PSC0_PSCTLWFP (*(vuint16*)(&__MBAR[0x869E])) #define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x869E]))
#define MCF_PSC1_PSCMR2 (*(vuint8 *)(&__MBAR[0x8700])) #define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8700]))
#define MCF_PSC1_PSCMR1 (*(vuint8 *)(&__MBAR[0x8700])) #define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8700]))
#define MCF_PSC1_PSCCSR (*(vuint8 *)(&__MBAR[0x8704])) #define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8704]))
#define MCF_PSC1_PSCSR (*(vuint16*)(&__MBAR[0x8704])) #define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8704]))
#define MCF_PSC1_PSCCR (*(vuint8 *)(&__MBAR[0x8708])) #define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8708]))
#define MCF_PSC1_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x870C])) #define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C]))
#define MCF_PSC1_PSCIPCR (*(vuint8 *)(&__MBAR[0x8710])) #define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8710]))
#define MCF_PSC1_PSCACR (*(vuint8 *)(&__MBAR[0x8710])) #define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8710]))
#define MCF_PSC1_PSCIMR (*(vuint16*)(&__MBAR[0x8714])) #define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8714]))
#define MCF_PSC1_PSCISR (*(vuint16*)(&__MBAR[0x8714])) #define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8714]))
#define MCF_PSC1_PSCCTUR (*(vuint8 *)(&__MBAR[0x8718])) #define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8718]))
#define MCF_PSC1_PSCCTLR (*(vuint8 *)(&__MBAR[0x871C])) #define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x871C]))
#define MCF_PSC1_PSCIP (*(vuint8 *)(&__MBAR[0x8734])) #define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8734]))
#define MCF_PSC1_PSCOPSET (*(vuint8 *)(&__MBAR[0x8738])) #define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8738]))
#define MCF_PSC1_PSCOPRESET (*(vuint8 *)(&__MBAR[0x873C])) #define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x873C]))
#define MCF_PSC1_PSCSICR (*(vuint8 *)(&__MBAR[0x8740])) #define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8740]))
#define MCF_PSC1_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8744])) #define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8744]))
#define MCF_PSC1_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8748])) #define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8748]))
#define MCF_PSC1_PSCIRSDR (*(vuint8 *)(&__MBAR[0x874C])) #define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x874C]))
#define MCF_PSC1_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8750])) #define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8750]))
#define MCF_PSC1_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8754])) #define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8754]))
#define MCF_PSC1_PSCRFCNT (*(vuint16*)(&__MBAR[0x8758])) #define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8758]))
#define MCF_PSC1_PSCTFCNT (*(vuint16*)(&__MBAR[0x875C])) #define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x875C]))
#define MCF_PSC1_PSCRFDR (*(vuint32*)(&__MBAR[0x8760])) #define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8760]))
#define MCF_PSC1_PSCRFSR (*(vuint16*)(&__MBAR[0x8764])) #define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8764]))
#define MCF_PSC1_PSCRFCR (*(vuint32*)(&__MBAR[0x8768])) #define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8768]))
#define MCF_PSC1_PSCRFAR (*(vuint16*)(&__MBAR[0x876E])) #define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x876E]))
#define MCF_PSC1_PSCRFRP (*(vuint16*)(&__MBAR[0x8772])) #define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8772]))
#define MCF_PSC1_PSCRFWP (*(vuint16*)(&__MBAR[0x8776])) #define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8776]))
#define MCF_PSC1_PSCRLRFP (*(vuint16*)(&__MBAR[0x877A])) #define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x877A]))
#define MCF_PSC1_PSCRLWFP (*(vuint16*)(&__MBAR[0x877E])) #define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x877E]))
#define MCF_PSC1_PSCTFDR (*(vuint32*)(&__MBAR[0x8780])) #define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8780]))
#define MCF_PSC1_PSCTFSR (*(vuint16*)(&__MBAR[0x8784])) #define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8784]))
#define MCF_PSC1_PSCTFCR (*(vuint32*)(&__MBAR[0x8788])) #define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8788]))
#define MCF_PSC1_PSCTFAR (*(vuint16*)(&__MBAR[0x878E])) #define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x878E]))
#define MCF_PSC1_PSCTFRP (*(vuint16*)(&__MBAR[0x8792])) #define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8792]))
#define MCF_PSC1_PSCTFWP (*(vuint16*)(&__MBAR[0x8796])) #define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8796]))
#define MCF_PSC1_PSCTLRFP (*(vuint16*)(&__MBAR[0x879A])) #define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x879A]))
#define MCF_PSC1_PSCTLWFP (*(vuint16*)(&__MBAR[0x879E])) #define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x879E]))
#define MCF_PSC2_PSCMR2 (*(vuint8 *)(&__MBAR[0x8800])) #define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8800]))
#define MCF_PSC2_PSCMR1 (*(vuint8 *)(&__MBAR[0x8800])) #define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8800]))
#define MCF_PSC2_PSCCSR (*(vuint8 *)(&__MBAR[0x8804])) #define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8804]))
#define MCF_PSC2_PSCSR (*(vuint16*)(&__MBAR[0x8804])) #define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8804]))
#define MCF_PSC2_PSCCR (*(vuint8 *)(&__MBAR[0x8808])) #define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8808]))
#define MCF_PSC2_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x880C])) #define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C]))
#define MCF_PSC2_PSCIPCR (*(vuint8 *)(&__MBAR[0x8810])) #define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8810]))
#define MCF_PSC2_PSCACR (*(vuint8 *)(&__MBAR[0x8810])) #define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8810]))
#define MCF_PSC2_PSCIMR (*(vuint16*)(&__MBAR[0x8814])) #define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8814]))
#define MCF_PSC2_PSCISR (*(vuint16*)(&__MBAR[0x8814])) #define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8814]))
#define MCF_PSC2_PSCCTUR (*(vuint8 *)(&__MBAR[0x8818])) #define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8818]))
#define MCF_PSC2_PSCCTLR (*(vuint8 *)(&__MBAR[0x881C])) #define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x881C]))
#define MCF_PSC2_PSCIP (*(vuint8 *)(&__MBAR[0x8834])) #define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8834]))
#define MCF_PSC2_PSCOPSET (*(vuint8 *)(&__MBAR[0x8838])) #define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8838]))
#define MCF_PSC2_PSCOPRESET (*(vuint8 *)(&__MBAR[0x883C])) #define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x883C]))
#define MCF_PSC2_PSCSICR (*(vuint8 *)(&__MBAR[0x8840])) #define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8840]))
#define MCF_PSC2_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8844])) #define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8844]))
#define MCF_PSC2_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8848])) #define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8848]))
#define MCF_PSC2_PSCIRSDR (*(vuint8 *)(&__MBAR[0x884C])) #define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x884C]))
#define MCF_PSC2_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8850])) #define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8850]))
#define MCF_PSC2_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8854])) #define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8854]))
#define MCF_PSC2_PSCRFCNT (*(vuint16*)(&__MBAR[0x8858])) #define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8858]))
#define MCF_PSC2_PSCTFCNT (*(vuint16*)(&__MBAR[0x885C])) #define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x885C]))
#define MCF_PSC2_PSCRFDR (*(vuint32*)(&__MBAR[0x8860])) #define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8860]))
#define MCF_PSC2_PSCRFSR (*(vuint16*)(&__MBAR[0x8864])) #define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8864]))
#define MCF_PSC2_PSCRFCR (*(vuint32*)(&__MBAR[0x8868])) #define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8868]))
#define MCF_PSC2_PSCRFAR (*(vuint16*)(&__MBAR[0x886E])) #define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x886E]))
#define MCF_PSC2_PSCRFRP (*(vuint16*)(&__MBAR[0x8872])) #define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8872]))
#define MCF_PSC2_PSCRFWP (*(vuint16*)(&__MBAR[0x8876])) #define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8876]))
#define MCF_PSC2_PSCRLRFP (*(vuint16*)(&__MBAR[0x887A])) #define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x887A]))
#define MCF_PSC2_PSCRLWFP (*(vuint16*)(&__MBAR[0x887E])) #define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x887E]))
#define MCF_PSC2_PSCTFDR (*(vuint32*)(&__MBAR[0x8880])) #define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8880]))
#define MCF_PSC2_PSCTFSR (*(vuint16*)(&__MBAR[0x8884])) #define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8884]))
#define MCF_PSC2_PSCTFCR (*(vuint32*)(&__MBAR[0x8888])) #define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8888]))
#define MCF_PSC2_PSCTFAR (*(vuint16*)(&__MBAR[0x888E])) #define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x888E]))
#define MCF_PSC2_PSCTFRP (*(vuint16*)(&__MBAR[0x8892])) #define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8892]))
#define MCF_PSC2_PSCTFWP (*(vuint16*)(&__MBAR[0x8896])) #define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8896]))
#define MCF_PSC2_PSCTLRFP (*(vuint16*)(&__MBAR[0x889A])) #define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x889A]))
#define MCF_PSC2_PSCTLWFP (*(vuint16*)(&__MBAR[0x889E])) #define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x889E]))
#define MCF_PSC3_PSCMR2 (*(vuint8 *)(&__MBAR[0x8900])) #define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8900]))
#define MCF_PSC3_PSCMR1 (*(vuint8 *)(&__MBAR[0x8900])) #define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8900]))
#define MCF_PSC3_PSCCSR (*(vuint8 *)(&__MBAR[0x8904])) #define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8904]))
#define MCF_PSC3_PSCSR (*(vuint16*)(&__MBAR[0x8904])) #define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8904]))
#define MCF_PSC3_PSCCR (*(vuint8 *)(&__MBAR[0x8908])) #define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8908]))
#define MCF_PSC3_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x890C])) #define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C]))
#define MCF_PSC3_PSCIPCR (*(vuint8 *)(&__MBAR[0x8910])) #define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8910]))
#define MCF_PSC3_PSCACR (*(vuint8 *)(&__MBAR[0x8910])) #define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8910]))
#define MCF_PSC3_PSCIMR (*(vuint16*)(&__MBAR[0x8914])) #define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8914]))
#define MCF_PSC3_PSCISR (*(vuint16*)(&__MBAR[0x8914])) #define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8914]))
#define MCF_PSC3_PSCCTUR (*(vuint8 *)(&__MBAR[0x8918])) #define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8918]))
#define MCF_PSC3_PSCCTLR (*(vuint8 *)(&__MBAR[0x891C])) #define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x891C]))
#define MCF_PSC3_PSCIP (*(vuint8 *)(&__MBAR[0x8934])) #define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8934]))
#define MCF_PSC3_PSCOPSET (*(vuint8 *)(&__MBAR[0x8938])) #define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8938]))
#define MCF_PSC3_PSCOPRESET (*(vuint8 *)(&__MBAR[0x893C])) #define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x893C]))
#define MCF_PSC3_PSCSICR (*(vuint8 *)(&__MBAR[0x8940])) #define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8940]))
#define MCF_PSC3_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8944])) #define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8944]))
#define MCF_PSC3_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8948])) #define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8948]))
#define MCF_PSC3_PSCIRSDR (*(vuint8 *)(&__MBAR[0x894C])) #define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x894C]))
#define MCF_PSC3_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8950])) #define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8950]))
#define MCF_PSC3_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8954])) #define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8954]))
#define MCF_PSC3_PSCRFCNT (*(vuint16*)(&__MBAR[0x8958])) #define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8958]))
#define MCF_PSC3_PSCTFCNT (*(vuint16*)(&__MBAR[0x895C])) #define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x895C]))
#define MCF_PSC3_PSCRFDR (*(vuint32*)(&__MBAR[0x8960])) #define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8960]))
#define MCF_PSC3_PSCRFSR (*(vuint16*)(&__MBAR[0x8964])) #define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8964]))
#define MCF_PSC3_PSCRFCR (*(vuint32*)(&__MBAR[0x8968])) #define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8968]))
#define MCF_PSC3_PSCRFAR (*(vuint16*)(&__MBAR[0x896E])) #define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x896E]))
#define MCF_PSC3_PSCRFRP (*(vuint16*)(&__MBAR[0x8972])) #define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8972]))
#define MCF_PSC3_PSCRFWP (*(vuint16*)(&__MBAR[0x8976])) #define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8976]))
#define MCF_PSC3_PSCRLRFP (*(vuint16*)(&__MBAR[0x897A])) #define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x897A]))
#define MCF_PSC3_PSCRLWFP (*(vuint16*)(&__MBAR[0x897E])) #define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x897E]))
#define MCF_PSC3_PSCTFDR (*(vuint32*)(&__MBAR[0x8980])) #define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8980]))
#define MCF_PSC3_PSCTFSR (*(vuint16*)(&__MBAR[0x8984])) #define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8984]))
#define MCF_PSC3_PSCTFCR (*(vuint32*)(&__MBAR[0x8988])) #define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8988]))
#define MCF_PSC3_PSCTFAR (*(vuint16*)(&__MBAR[0x898E])) #define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x898E]))
#define MCF_PSC3_PSCTFRP (*(vuint16*)(&__MBAR[0x8992])) #define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8992]))
#define MCF_PSC3_PSCTFWP (*(vuint16*)(&__MBAR[0x8996])) #define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8996]))
#define MCF_PSC3_PSCTLRFP (*(vuint16*)(&__MBAR[0x899A])) #define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x899A]))
#define MCF_PSC3_PSCTLWFP (*(vuint16*)(&__MBAR[0x899E])) #define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x899E]))
#define MCF_PSC_PSCMR(x) (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)])) #define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&__MBAR[0x8600 + ((x)*0x100)]))
#define MCF_PSC_PSCCSR(x) (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)])) #define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&__MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCSR(x) (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)])) #define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&__MBAR[0x8604 + ((x)*0x100)]))
#define MCF_PSC_PSCCR(x) (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)])) #define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&__MBAR[0x8608 + ((x)*0x100)]))
#define MCF_PSC_PSCRB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCRB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCTB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) #define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)]))
#define MCF_PSC_PSCIPCR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) #define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCACR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) #define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)]))
#define MCF_PSC_PSCIMR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) #define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCISR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) #define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)]))
#define MCF_PSC_PSCCTUR(x) (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)])) #define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&__MBAR[0x8618 + ((x)*0x100)]))
#define MCF_PSC_PSCCTLR(x) (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)])) #define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&__MBAR[0x861C + ((x)*0x100)]))
#define MCF_PSC_PSCIP(x) (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)])) #define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&__MBAR[0x8634 + ((x)*0x100)]))
#define MCF_PSC_PSCOPSET(x) (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)])) #define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&__MBAR[0x8638 + ((x)*0x100)]))
#define MCF_PSC_PSCOPRESET(x) (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)])) #define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&__MBAR[0x863C + ((x)*0x100)]))
#define MCF_PSC_PSCSICR(x) (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)])) #define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&__MBAR[0x8640 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR1(x) (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)])) #define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&__MBAR[0x8644 + ((x)*0x100)]))
#define MCF_PSC_PSCIRCR2(x) (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)])) #define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&__MBAR[0x8648 + ((x)*0x100)]))
#define MCF_PSC_PSCIRSDR(x) (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)])) #define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&__MBAR[0x864C + ((x)*0x100)]))
#define MCF_PSC_PSCIRMDR(x) (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)])) #define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&__MBAR[0x8650 + ((x)*0x100)]))
#define MCF_PSC_PSCIRFDR(x) (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)])) #define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&__MBAR[0x8654 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCNT(x) (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)])) #define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x8658 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCNT(x) (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)])) #define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x865C + ((x)*0x100)]))
#define MCF_PSC_PSCRFDR(x) (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)])) #define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8660 + ((x)*0x100)]))
#define MCF_PSC_PSCRFSR(x) (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)])) #define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8664 + ((x)*0x100)]))
#define MCF_PSC_PSCRFCR(x) (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)])) #define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8668 + ((x)*0x100)]))
#define MCF_PSC_PSCRFAR(x) (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)])) #define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&__MBAR[0x866E + ((x)*0x100)]))
#define MCF_PSC_PSCRFRP(x) (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)])) #define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8672 + ((x)*0x100)]))
#define MCF_PSC_PSCRFWP(x) (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)])) #define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8676 + ((x)*0x100)]))
#define MCF_PSC_PSCRLRFP(x) (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)])) #define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x867A + ((x)*0x100)]))
#define MCF_PSC_PSCRLWFP(x) (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)])) #define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x867E + ((x)*0x100)]))
#define MCF_PSC_PSCTFDR(x) (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)])) #define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8680 + ((x)*0x100)]))
#define MCF_PSC_PSCTFSR(x) (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)])) #define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8684 + ((x)*0x100)]))
#define MCF_PSC_PSCTFCR(x) (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)])) #define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8688 + ((x)*0x100)]))
#define MCF_PSC_PSCTFAR(x) (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)])) #define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&__MBAR[0x868E + ((x)*0x100)]))
#define MCF_PSC_PSCTFRP(x) (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)])) #define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8692 + ((x)*0x100)]))
#define MCF_PSC_PSCTFWP(x) (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)])) #define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8696 + ((x)*0x100)]))
#define MCF_PSC_PSCTLRFP(x) (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)])) #define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x869A + ((x)*0x100)]))
#define MCF_PSC_PSCTLWFP(x) (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)])) #define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x869E + ((x)*0x100)]))
/* Bit definitions and macros for MCF_PSC_PSCMR */ /* Bit definitions and macros for MCF_PSC_PSCMR */
#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) #define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0)

20
include/MCF5475_SDRAMC.h
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@@ -24,16 +24,16 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SDRAMC_SDRAMDS (*(vuint32*)(&__MBAR[0x4])) #define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&__MBAR[0x4]))
#define MCF_SDRAMC_CS0CFG (*(vuint32*)(&__MBAR[0x20])) #define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&__MBAR[0x20]))
#define MCF_SDRAMC_CS1CFG (*(vuint32*)(&__MBAR[0x24])) #define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&__MBAR[0x24]))
#define MCF_SDRAMC_CS2CFG (*(vuint32*)(&__MBAR[0x28])) #define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&__MBAR[0x28]))
#define MCF_SDRAMC_CS3CFG (*(vuint32*)(&__MBAR[0x2C])) #define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&__MBAR[0x2C]))
#define MCF_SDRAMC_SDMR (*(vuint32*)(&__MBAR[0x100])) #define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&__MBAR[0x100]))
#define MCF_SDRAMC_SDCR (*(vuint32*)(&__MBAR[0x104])) #define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&__MBAR[0x104]))
#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(&__MBAR[0x108])) #define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&__MBAR[0x108]))
#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(&__MBAR[0x10C])) #define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&__MBAR[0x10C]))
#define MCF_SDRAMC_CSCFG(x) (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)])) #define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&__MBAR[0x20 + ((x)*0x4)]))
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ /* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */

96
include/MCF5475_SEC.h
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@@ -24,54 +24,54 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000])) #define MCF_SEC_EUACRH (*(volatile uint32_t*)(&__MBAR[0x21000]))
#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004])) #define MCF_SEC_EUACRL (*(volatile uint32_t*)(&__MBAR[0x21004]))
#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008])) #define MCF_SEC_SIMRH (*(volatile uint32_t*)(&__MBAR[0x21008]))
#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C])) #define MCF_SEC_SIMRL (*(volatile uint32_t*)(&__MBAR[0x2100C]))
#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010])) #define MCF_SEC_SISRH (*(volatile uint32_t*)(&__MBAR[0x21010]))
#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014])) #define MCF_SEC_SISRL (*(volatile uint32_t*)(&__MBAR[0x21014]))
#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018])) #define MCF_SEC_SICRH (*(volatile uint32_t*)(&__MBAR[0x21018]))
#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C])) #define MCF_SEC_SICRL (*(volatile uint32_t*)(&__MBAR[0x2101C]))
#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020])) #define MCF_SEC_SIDR (*(volatile uint32_t*)(&__MBAR[0x21020]))
#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028])) #define MCF_SEC_EUASRH (*(volatile uint32_t*)(&__MBAR[0x21028]))
#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C])) #define MCF_SEC_EUASRL (*(volatile uint32_t*)(&__MBAR[0x2102C]))
#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030])) #define MCF_SEC_SMCR (*(volatile uint32_t*)(&__MBAR[0x21030]))
#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038])) #define MCF_SEC_MEAR (*(volatile uint32_t*)(&__MBAR[0x21038]))
#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C])) #define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&__MBAR[0x2200C]))
#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010])) #define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&__MBAR[0x22010]))
#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014])) #define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&__MBAR[0x22014]))
#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044])) #define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&__MBAR[0x22044]))
#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C])) #define MCF_SEC_FR0 (*(volatile uint32_t*)(&__MBAR[0x2204C]))
#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C])) #define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&__MBAR[0x2300C]))
#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010])) #define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&__MBAR[0x23010]))
#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014])) #define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&__MBAR[0x23014]))
#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044])) #define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&__MBAR[0x23044]))
#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C])) #define MCF_SEC_FR1 (*(volatile uint32_t*)(&__MBAR[0x2304C]))
#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018])) #define MCF_SEC_AFRCR (*(volatile uint32_t*)(&__MBAR[0x28018]))
#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028])) #define MCF_SEC_AFSR (*(volatile uint32_t*)(&__MBAR[0x28028]))
#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030])) #define MCF_SEC_AFISR (*(volatile uint32_t*)(&__MBAR[0x28030]))
#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038])) #define MCF_SEC_AFIMR (*(volatile uint32_t*)(&__MBAR[0x28038]))
#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018])) #define MCF_SEC_DRCR (*(volatile uint32_t*)(&__MBAR[0x2A018]))
#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028])) #define MCF_SEC_DSR (*(volatile uint32_t*)(&__MBAR[0x2A028]))
#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030])) #define MCF_SEC_DISR (*(volatile uint32_t*)(&__MBAR[0x2A030]))
#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038])) #define MCF_SEC_DIMR (*(volatile uint32_t*)(&__MBAR[0x2A038]))
#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018])) #define MCF_SEC_MDRCR (*(volatile uint32_t*)(&__MBAR[0x2C018]))
#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028])) #define MCF_SEC_MDSR (*(volatile uint32_t*)(&__MBAR[0x2C028]))
#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030])) #define MCF_SEC_MDISR (*(volatile uint32_t*)(&__MBAR[0x2C030]))
#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038])) #define MCF_SEC_MDIMR (*(volatile uint32_t*)(&__MBAR[0x2C038]))
#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018])) #define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&__MBAR[0x2E018]))
#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028])) #define MCF_SEC_RNGSR (*(volatile uint32_t*)(&__MBAR[0x2E028]))
#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030])) #define MCF_SEC_RNGISR (*(volatile uint32_t*)(&__MBAR[0x2E030]))
#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038])) #define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&__MBAR[0x2E038]))
#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018])) #define MCF_SEC_AESRCR (*(volatile uint32_t*)(&__MBAR[0x32018]))
#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028])) #define MCF_SEC_AESSR (*(volatile uint32_t*)(&__MBAR[0x32028]))
#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030])) #define MCF_SEC_AESISR (*(volatile uint32_t*)(&__MBAR[0x32030]))
#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038])) #define MCF_SEC_AESIMR (*(volatile uint32_t*)(&__MBAR[0x32038]))
#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)])) #define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&__MBAR[0x2200C + ((x)*0x1000)]))
#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)])) #define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&__MBAR[0x22010 + ((x)*0x1000)]))
#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)])) #define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&__MBAR[0x22014 + ((x)*0x1000)]))
#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)])) #define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&__MBAR[0x22044 + ((x)*0x1000)]))
#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)])) #define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&__MBAR[0x2204C + ((x)*0x1000)]))
/* Bit definitions and macros for MCF_SEC_EUACRH */ /* Bit definitions and macros for MCF_SEC_EUACRH */

8
include/MCF5475_SIU.h
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@@ -24,10 +24,10 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SIU_SBCR (*(vuint32*)(&__MBAR[0x10])) #define MCF_SIU_SBCR (*(volatile uint32_t*)(&__MBAR[0x10]))
#define MCF_SIU_SECSACR (*(vuint32*)(&__MBAR[0x38])) #define MCF_SIU_SECSACR (*(volatile uint32_t*)(&__MBAR[0x38]))
#define MCF_SIU_RSR (*(vuint32*)(&__MBAR[0x44])) #define MCF_SIU_RSR (*(volatile uint32_t*)(&__MBAR[0x44]))
#define MCF_SIU_JTAGID (*(vuint32*)(&__MBAR[0x50])) #define MCF_SIU_JTAGID (*(volatile uint32_t*)(&__MBAR[0x50]))
/* Bit definitions and macros for MCF_SIU_SBCR */ /* Bit definitions and macros for MCF_SIU_SBCR */

24
include/MCF5475_SLT.h
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@@ -24,20 +24,20 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SLT0_STCNT (*(vuint32*)(&__MBAR[0x900])) #define MCF_SLT0_STCNT (*(volatile uint32_t*)(&__MBAR[0x900]))
#define MCF_SLT0_SCR (*(vuint32*)(&__MBAR[0x904])) #define MCF_SLT0_SCR (*(volatile uint32_t*)(&__MBAR[0x904]))
#define MCF_SLT0_SCNT (*(vuint32*)(&__MBAR[0x908])) #define MCF_SLT0_SCNT (*(volatile uint32_t*)(&__MBAR[0x908]))
#define MCF_SLT0_SSR (*(vuint32*)(&__MBAR[0x90C])) #define MCF_SLT0_SSR (*(volatile uint32_t*)(&__MBAR[0x90C]))
#define MCF_SLT1_STCNT (*(vuint32*)(&__MBAR[0x910])) #define MCF_SLT1_STCNT (*(volatile uint32_t*)(&__MBAR[0x910]))
#define MCF_SLT1_SCR (*(vuint32*)(&__MBAR[0x914])) #define MCF_SLT1_SCR (*(volatile uint32_t*)(&__MBAR[0x914]))
#define MCF_SLT1_SCNT (*(vuint32*)(&__MBAR[0x918])) #define MCF_SLT1_SCNT (*(volatile uint32_t*)(&__MBAR[0x918]))
#define MCF_SLT1_SSR (*(vuint32*)(&__MBAR[0x91C])) #define MCF_SLT1_SSR (*(volatile uint32_t*)(&__MBAR[0x91C]))
#define MCF_SLT_STCNT(x) (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)])) #define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&__MBAR[0x900 + ((x)*0x10)]))
#define MCF_SLT_SCR(x) (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)])) #define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&__MBAR[0x904 + ((x)*0x10)]))
#define MCF_SLT_SCNT(x) (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)])) #define MCF_SLT_SCNT(x) (*(volatile uint32_t*)(&__MBAR[0x908 + ((x)*0x10)]))
#define MCF_SLT_SSR(x) (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)])) #define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&__MBAR[0x90C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_SLT_STCNT */ /* Bit definitions and macros for MCF_SLT_STCNT */

10
include/MCF5475_SRAM.h
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@@ -24,11 +24,11 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SRAM_SSCR (*(vuint32*)(&__MBAR[0x1FFC0])) #define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
#define MCF_SRAM_TCCR (*(vuint32*)(&__MBAR[0x1FFC4])) #define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
#define MCF_SRAM_TCCRDR (*(vuint32*)(&__MBAR[0x1FFC8])) #define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
#define MCF_SRAM_TCCRDW (*(vuint32*)(&__MBAR[0x1FFCC])) #define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
#define MCF_SRAM_TCCRSEC (*(vuint32*)(&__MBAR[0x1FFD0])) #define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
/* Bit definitions and macros for MCF_SRAM_SSCR */ /* Bit definitions and macros for MCF_SRAM_SSCR */

462
include/MCF5475_USB.h
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@@ -24,237 +24,237 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_USB_USBAISR (*(vuint8 *)(&__MBAR[0xB000])) #define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000]))
#define MCF_USB_USBAIMR (*(vuint8 *)(&__MBAR[0xB001])) #define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001]))
#define MCF_USB_EPINFO (*(vuint8 *)(&__MBAR[0xB003])) #define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003]))
#define MCF_USB_CFGR (*(vuint8 *)(&__MBAR[0xB004])) #define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004]))
#define MCF_USB_CFGAR (*(vuint8 *)(&__MBAR[0xB005])) #define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005]))
#define MCF_USB_SPEEDR (*(vuint8 *)(&__MBAR[0xB006])) #define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006]))
#define MCF_USB_FRMNUMR (*(vuint16*)(&__MBAR[0xB00E])) #define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E]))
#define MCF_USB_EPTNR (*(vuint16*)(&__MBAR[0xB010])) #define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010]))
#define MCF_USB_IFUR (*(vuint16*)(&__MBAR[0xB014])) #define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014]))
#define MCF_USB_IFR0 (*(vuint16*)(&__MBAR[0xB040])) #define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040]))
#define MCF_USB_IFR1 (*(vuint16*)(&__MBAR[0xB042])) #define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042]))
#define MCF_USB_IFR2 (*(vuint16*)(&__MBAR[0xB044])) #define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044]))
#define MCF_USB_IFR3 (*(vuint16*)(&__MBAR[0xB046])) #define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046]))
#define MCF_USB_IFR4 (*(vuint16*)(&__MBAR[0xB048])) #define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048]))
#define MCF_USB_IFR5 (*(vuint16*)(&__MBAR[0xB04A])) #define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A]))
#define MCF_USB_IFR6 (*(vuint16*)(&__MBAR[0xB04C])) #define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C]))
#define MCF_USB_IFR7 (*(vuint16*)(&__MBAR[0xB04E])) #define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E]))
#define MCF_USB_IFR8 (*(vuint16*)(&__MBAR[0xB050])) #define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050]))
#define MCF_USB_IFR9 (*(vuint16*)(&__MBAR[0xB052])) #define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052]))
#define MCF_USB_IFR10 (*(vuint16*)(&__MBAR[0xB054])) #define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054]))
#define MCF_USB_IFR11 (*(vuint16*)(&__MBAR[0xB056])) #define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056]))
#define MCF_USB_IFR12 (*(vuint16*)(&__MBAR[0xB058])) #define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058]))
#define MCF_USB_IFR13 (*(vuint16*)(&__MBAR[0xB05A])) #define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A]))
#define MCF_USB_IFR14 (*(vuint16*)(&__MBAR[0xB05C])) #define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C]))
#define MCF_USB_IFR15 (*(vuint16*)(&__MBAR[0xB05E])) #define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E]))
#define MCF_USB_IFR16 (*(vuint16*)(&__MBAR[0xB060])) #define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060]))
#define MCF_USB_IFR17 (*(vuint16*)(&__MBAR[0xB062])) #define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062]))
#define MCF_USB_IFR18 (*(vuint16*)(&__MBAR[0xB064])) #define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064]))
#define MCF_USB_IFR19 (*(vuint16*)(&__MBAR[0xB066])) #define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066]))
#define MCF_USB_IFR20 (*(vuint16*)(&__MBAR[0xB068])) #define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068]))
#define MCF_USB_IFR21 (*(vuint16*)(&__MBAR[0xB06A])) #define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A]))
#define MCF_USB_IFR22 (*(vuint16*)(&__MBAR[0xB06C])) #define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C]))
#define MCF_USB_IFR23 (*(vuint16*)(&__MBAR[0xB06E])) #define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E]))
#define MCF_USB_IFR24 (*(vuint16*)(&__MBAR[0xB070])) #define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070]))
#define MCF_USB_IFR25 (*(vuint16*)(&__MBAR[0xB072])) #define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072]))
#define MCF_USB_IFR26 (*(vuint16*)(&__MBAR[0xB074])) #define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074]))
#define MCF_USB_IFR27 (*(vuint16*)(&__MBAR[0xB076])) #define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076]))
#define MCF_USB_IFR28 (*(vuint16*)(&__MBAR[0xB078])) #define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078]))
#define MCF_USB_IFR29 (*(vuint16*)(&__MBAR[0xB07A])) #define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A]))
#define MCF_USB_IFR30 (*(vuint16*)(&__MBAR[0xB07C])) #define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C]))
#define MCF_USB_IFR31 (*(vuint16*)(&__MBAR[0xB07E])) #define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E]))
#define MCF_USB_PPCNT (*(vuint16*)(&__MBAR[0xB080])) #define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080]))
#define MCF_USB_DPCNT (*(vuint16*)(&__MBAR[0xB082])) #define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082]))
#define MCF_USB_CRCECNT (*(vuint16*)(&__MBAR[0xB084])) #define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084]))
#define MCF_USB_BSECNT (*(vuint16*)(&__MBAR[0xB086])) #define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086]))
#define MCF_USB_PIDECNT (*(vuint16*)(&__MBAR[0xB088])) #define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088]))
#define MCF_USB_FRMECNT (*(vuint16*)(&__MBAR[0xB08A])) #define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A]))
#define MCF_USB_TXPCNT (*(vuint16*)(&__MBAR[0xB08C])) #define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C]))
#define MCF_USB_CNTOVR (*(vuint8 *)(&__MBAR[0xB08E])) #define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E]))
#define MCF_USB_EP0ACR (*(vuint8 *)(&__MBAR[0xB101])) #define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101]))
#define MCF_USB_EP0MPSR (*(vuint16*)(&__MBAR[0xB102])) #define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102]))
#define MCF_USB_EP0IFR (*(vuint8 *)(&__MBAR[0xB104])) #define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104]))
#define MCF_USB_EP0SR (*(vuint8 *)(&__MBAR[0xB105])) #define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105]))
#define MCF_USB_BMRTR (*(vuint8 *)(&__MBAR[0xB106])) #define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106]))
#define MCF_USB_BRTR (*(vuint8 *)(&__MBAR[0xB107])) #define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107]))
#define MCF_USB_WVALUER (*(vuint16*)(&__MBAR[0xB108])) #define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108]))
#define MCF_USB_WINDEXR (*(vuint16*)(&__MBAR[0xB10A])) #define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A]))
#define MCF_USB_WLENGTHR (*(vuint16*)(&__MBAR[0xB10C])) #define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C]))
#define MCF_USB_EP1OUTACR (*(vuint8 *)(&__MBAR[0xB131])) #define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131]))
#define MCF_USB_EP1OUTMPSR (*(vuint16*)(&__MBAR[0xB132])) #define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132]))
#define MCF_USB_EP1OUTIFR (*(vuint8 *)(&__MBAR[0xB134])) #define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134]))
#define MCF_USB_EP1OUTSR (*(vuint8 *)(&__MBAR[0xB135])) #define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135]))
#define MCF_USB_EP1OUTSFR (*(vuint16*)(&__MBAR[0xB13E])) #define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E]))
#define MCF_USB_EP1INACR (*(vuint8 *)(&__MBAR[0xB149])) #define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149]))
#define MCF_USB_EP1INMPSR (*(vuint16*)(&__MBAR[0xB14A])) #define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A]))
#define MCF_USB_EP1INIFR (*(vuint8 *)(&__MBAR[0xB14C])) #define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C]))
#define MCF_USB_EP1INSR (*(vuint8 *)(&__MBAR[0xB14D])) #define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D]))
#define MCF_USB_EP1INSFR (*(vuint16*)(&__MBAR[0xB156])) #define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156]))
#define MCF_USB_EP2OUTACR (*(vuint8 *)(&__MBAR[0xB161])) #define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161]))
#define MCF_USB_EP2OUTMPSR (*(vuint16*)(&__MBAR[0xB162])) #define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162]))
#define MCF_USB_EP2OUTIFR (*(vuint8 *)(&__MBAR[0xB164])) #define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164]))
#define MCF_USB_EP2OUTSR (*(vuint8 *)(&__MBAR[0xB165])) #define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165]))
#define MCF_USB_EP2OUTSFR (*(vuint16*)(&__MBAR[0xB16E])) #define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E]))
#define MCF_USB_EP2INACR (*(vuint8 *)(&__MBAR[0xB179])) #define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179]))
#define MCF_USB_EP2INMPSR (*(vuint16*)(&__MBAR[0xB17A])) #define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A]))
#define MCF_USB_EP2INIFR (*(vuint8 *)(&__MBAR[0xB17C])) #define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C]))
#define MCF_USB_EP2INSR (*(vuint8 *)(&__MBAR[0xB17D])) #define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D]))
#define MCF_USB_EP2INSFR (*(vuint16*)(&__MBAR[0xB186])) #define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186]))
#define MCF_USB_EP3OUTACR (*(vuint8 *)(&__MBAR[0xB191])) #define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191]))
#define MCF_USB_EP3OUTMPSR (*(vuint16*)(&__MBAR[0xB192])) #define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192]))
#define MCF_USB_EP3OUTIFR (*(vuint8 *)(&__MBAR[0xB194])) #define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194]))
#define MCF_USB_EP3OUTSR (*(vuint8 *)(&__MBAR[0xB195])) #define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195]))
#define MCF_USB_EP3OUTSFR (*(vuint16*)(&__MBAR[0xB19E])) #define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E]))
#define MCF_USB_EP3INACR (*(vuint8 *)(&__MBAR[0xB1A9])) #define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
#define MCF_USB_EP3INMPSR (*(vuint16*)(&__MBAR[0xB1AA])) #define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
#define MCF_USB_EP3INIFR (*(vuint8 *)(&__MBAR[0xB1AC])) #define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
#define MCF_USB_EP3INSR (*(vuint8 *)(&__MBAR[0xB1AD])) #define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
#define MCF_USB_EP3INSFR (*(vuint16*)(&__MBAR[0xB1B6])) #define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
#define MCF_USB_EP4OUTACR (*(vuint8 *)(&__MBAR[0xB1C1])) #define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
#define MCF_USB_EP4OUTMPSR (*(vuint16*)(&__MBAR[0xB1C2])) #define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
#define MCF_USB_EP4OUTIFR (*(vuint8 *)(&__MBAR[0xB1C4])) #define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
#define MCF_USB_EP4OUTSR (*(vuint8 *)(&__MBAR[0xB1C5])) #define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
#define MCF_USB_EP4OUTSFR (*(vuint16*)(&__MBAR[0xB1CE])) #define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
#define MCF_USB_EP4INACR (*(vuint8 *)(&__MBAR[0xB1D9])) #define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
#define MCF_USB_EP4INMPSR (*(vuint16*)(&__MBAR[0xB1DA])) #define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
#define MCF_USB_EP4INIFR (*(vuint8 *)(&__MBAR[0xB1DC])) #define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
#define MCF_USB_EP4INSR (*(vuint8 *)(&__MBAR[0xB1DD])) #define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
#define MCF_USB_EP4INSFR (*(vuint16*)(&__MBAR[0xB1E6])) #define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
#define MCF_USB_EP5OUTACR (*(vuint8 *)(&__MBAR[0xB1F1])) #define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
#define MCF_USB_EP5OUTMPSR (*(vuint16*)(&__MBAR[0xB1F2])) #define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
#define MCF_USB_EP5OUTIFR (*(vuint8 *)(&__MBAR[0xB1F4])) #define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
#define MCF_USB_EP5OUTSR (*(vuint8 *)(&__MBAR[0xB1F5])) #define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
#define MCF_USB_EP5OUTSFR (*(vuint16*)(&__MBAR[0xB1FE])) #define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
#define MCF_USB_EP5INACR (*(vuint8 *)(&__MBAR[0xB209])) #define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209]))
#define MCF_USB_EP5INMPSR (*(vuint16*)(&__MBAR[0xB20A])) #define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A]))
#define MCF_USB_EP5INIFR (*(vuint8 *)(&__MBAR[0xB20C])) #define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C]))
#define MCF_USB_EP5INSR (*(vuint8 *)(&__MBAR[0xB20D])) #define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D]))
#define MCF_USB_EP5INSFR (*(vuint16*)(&__MBAR[0xB216])) #define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216]))
#define MCF_USB_EP6OUTACR (*(vuint8 *)(&__MBAR[0xB221])) #define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221]))
#define MCF_USB_EP6OUTMPSR (*(vuint16*)(&__MBAR[0xB222])) #define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222]))
#define MCF_USB_EP6OUTIFR (*(vuint8 *)(&__MBAR[0xB224])) #define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224]))
#define MCF_USB_EP6OUTSR (*(vuint8 *)(&__MBAR[0xB225])) #define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225]))
#define MCF_USB_EP6OUTSFR (*(vuint16*)(&__MBAR[0xB22E])) #define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E]))
#define MCF_USB_EP6INACR (*(vuint8 *)(&__MBAR[0xB239])) #define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239]))
#define MCF_USB_EP6INMPSR (*(vuint16*)(&__MBAR[0xB23A])) #define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A]))
#define MCF_USB_EP6INIFR (*(vuint8 *)(&__MBAR[0xB23C])) #define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C]))
#define MCF_USB_EP6INSR (*(vuint8 *)(&__MBAR[0xB23D])) #define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D]))
#define MCF_USB_EP6INSFR (*(vuint16*)(&__MBAR[0xB246])) #define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246]))
#define MCF_USB_USBSR (*(vuint32*)(&__MBAR[0xB400])) #define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400]))
#define MCF_USB_USBCR (*(vuint32*)(&__MBAR[0xB404])) #define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404]))
#define MCF_USB_DRAMCR (*(vuint32*)(&__MBAR[0xB408])) #define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408]))
#define MCF_USB_DRAMDR (*(vuint32*)(&__MBAR[0xB40C])) #define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C]))
#define MCF_USB_USBISR (*(vuint32*)(&__MBAR[0xB410])) #define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410]))
#define MCF_USB_USBIMR (*(vuint32*)(&__MBAR[0xB414])) #define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414]))
#define MCF_USB_EP0STAT (*(vuint32*)(&__MBAR[0xB440])) #define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440]))
#define MCF_USB_EP0ISR (*(vuint32*)(&__MBAR[0xB444])) #define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444]))
#define MCF_USB_EP0IMR (*(vuint32*)(&__MBAR[0xB448])) #define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448]))
#define MCF_USB_EP0FRCFGR (*(vuint32*)(&__MBAR[0xB44C])) #define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C]))
#define MCF_USB_EP0FDR (*(vuint32*)(&__MBAR[0xB450])) #define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450]))
#define MCF_USB_EP0FSR (*(vuint32*)(&__MBAR[0xB454])) #define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454]))
#define MCF_USB_EP0FCR (*(vuint32*)(&__MBAR[0xB458])) #define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458]))
#define MCF_USB_EP0FAR (*(vuint32*)(&__MBAR[0xB45C])) #define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C]))
#define MCF_USB_EP0FRP (*(vuint32*)(&__MBAR[0xB460])) #define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460]))
#define MCF_USB_EP0FWP (*(vuint32*)(&__MBAR[0xB464])) #define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464]))
#define MCF_USB_EP0LRFP (*(vuint32*)(&__MBAR[0xB468])) #define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468]))
#define MCF_USB_EP0LWFP (*(vuint32*)(&__MBAR[0xB46C])) #define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C]))
#define MCF_USB_EP1STAT (*(vuint32*)(&__MBAR[0xB470])) #define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470]))
#define MCF_USB_EP1ISR (*(vuint32*)(&__MBAR[0xB474])) #define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474]))
#define MCF_USB_EP1IMR (*(vuint32*)(&__MBAR[0xB478])) #define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478]))
#define MCF_USB_EP1FRCFGR (*(vuint32*)(&__MBAR[0xB47C])) #define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C]))
#define MCF_USB_EP1FDR (*(vuint32*)(&__MBAR[0xB480])) #define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480]))
#define MCF_USB_EP1FSR (*(vuint32*)(&__MBAR[0xB484])) #define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484]))
#define MCF_USB_EP1FCR (*(vuint32*)(&__MBAR[0xB488])) #define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488]))
#define MCF_USB_EP1FAR (*(vuint32*)(&__MBAR[0xB48C])) #define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C]))
#define MCF_USB_EP1FRP (*(vuint32*)(&__MBAR[0xB490])) #define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490]))
#define MCF_USB_EP1FWP (*(vuint32*)(&__MBAR[0xB494])) #define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494]))
#define MCF_USB_EP1LRFP (*(vuint32*)(&__MBAR[0xB498])) #define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498]))
#define MCF_USB_EP1LWFP (*(vuint32*)(&__MBAR[0xB49C])) #define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C]))
#define MCF_USB_EP2STAT (*(vuint32*)(&__MBAR[0xB4A0])) #define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
#define MCF_USB_EP2ISR (*(vuint32*)(&__MBAR[0xB4A4])) #define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
#define MCF_USB_EP2IMR (*(vuint32*)(&__MBAR[0xB4A8])) #define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
#define MCF_USB_EP2FRCFGR (*(vuint32*)(&__MBAR[0xB4AC])) #define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
#define MCF_USB_EP2FDR (*(vuint32*)(&__MBAR[0xB4B0])) #define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
#define MCF_USB_EP2FSR (*(vuint32*)(&__MBAR[0xB4B4])) #define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
#define MCF_USB_EP2FCR (*(vuint32*)(&__MBAR[0xB4B8])) #define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
#define MCF_USB_EP2FAR (*(vuint32*)(&__MBAR[0xB4BC])) #define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
#define MCF_USB_EP2FRP (*(vuint32*)(&__MBAR[0xB4C0])) #define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
#define MCF_USB_EP2FWP (*(vuint32*)(&__MBAR[0xB4C4])) #define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
#define MCF_USB_EP2LRFP (*(vuint32*)(&__MBAR[0xB4C8])) #define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
#define MCF_USB_EP2LWFP (*(vuint32*)(&__MBAR[0xB4CC])) #define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
#define MCF_USB_EP3STAT (*(vuint32*)(&__MBAR[0xB4D0])) #define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
#define MCF_USB_EP3ISR (*(vuint32*)(&__MBAR[0xB4D4])) #define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
#define MCF_USB_EP3IMR (*(vuint32*)(&__MBAR[0xB4D8])) #define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
#define MCF_USB_EP3FRCFGR (*(vuint32*)(&__MBAR[0xB4DC])) #define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
#define MCF_USB_EP3FDR (*(vuint32*)(&__MBAR[0xB4E0])) #define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
#define MCF_USB_EP3FSR (*(vuint32*)(&__MBAR[0xB4E4])) #define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
#define MCF_USB_EP3FCR (*(vuint32*)(&__MBAR[0xB4E8])) #define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
#define MCF_USB_EP3FAR (*(vuint32*)(&__MBAR[0xB4EC])) #define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
#define MCF_USB_EP3FRP (*(vuint32*)(&__MBAR[0xB4F0])) #define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
#define MCF_USB_EP3FWP (*(vuint32*)(&__MBAR[0xB4F4])) #define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
#define MCF_USB_EP3LRFP (*(vuint32*)(&__MBAR[0xB4F8])) #define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
#define MCF_USB_EP3LWFP (*(vuint32*)(&__MBAR[0xB4FC])) #define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
#define MCF_USB_EP4STAT (*(vuint32*)(&__MBAR[0xB500])) #define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500]))
#define MCF_USB_EP4ISR (*(vuint32*)(&__MBAR[0xB504])) #define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504]))
#define MCF_USB_EP4IMR (*(vuint32*)(&__MBAR[0xB508])) #define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508]))
#define MCF_USB_EP4FRCFGR (*(vuint32*)(&__MBAR[0xB50C])) #define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C]))
#define MCF_USB_EP4FDR (*(vuint32*)(&__MBAR[0xB510])) #define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510]))
#define MCF_USB_EP4FSR (*(vuint32*)(&__MBAR[0xB514])) #define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514]))
#define MCF_USB_EP4FCR (*(vuint32*)(&__MBAR[0xB518])) #define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518]))
#define MCF_USB_EP4FAR (*(vuint32*)(&__MBAR[0xB51C])) #define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C]))
#define MCF_USB_EP4FRP (*(vuint32*)(&__MBAR[0xB520])) #define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520]))
#define MCF_USB_EP4FWP (*(vuint32*)(&__MBAR[0xB524])) #define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524]))
#define MCF_USB_EP4LRFP (*(vuint32*)(&__MBAR[0xB528])) #define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528]))
#define MCF_USB_EP4LWFP (*(vuint32*)(&__MBAR[0xB52C])) #define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C]))
#define MCF_USB_EP5STAT (*(vuint32*)(&__MBAR[0xB530])) #define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530]))
#define MCF_USB_EP5ISR (*(vuint32*)(&__MBAR[0xB534])) #define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534]))
#define MCF_USB_EP5IMR (*(vuint32*)(&__MBAR[0xB538])) #define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538]))
#define MCF_USB_EP5FRCFGR (*(vuint32*)(&__MBAR[0xB53C])) #define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C]))
#define MCF_USB_EP5FDR (*(vuint32*)(&__MBAR[0xB540])) #define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540]))
#define MCF_USB_EP5FSR (*(vuint32*)(&__MBAR[0xB544])) #define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544]))
#define MCF_USB_EP5FCR (*(vuint32*)(&__MBAR[0xB548])) #define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548]))
#define MCF_USB_EP5FAR (*(vuint32*)(&__MBAR[0xB54C])) #define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C]))
#define MCF_USB_EP5FRP (*(vuint32*)(&__MBAR[0xB550])) #define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550]))
#define MCF_USB_EP5FWP (*(vuint32*)(&__MBAR[0xB554])) #define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554]))
#define MCF_USB_EP5LRFP (*(vuint32*)(&__MBAR[0xB558])) #define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558]))
#define MCF_USB_EP5LWFP (*(vuint32*)(&__MBAR[0xB55C])) #define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C]))
#define MCF_USB_EP6STAT (*(vuint32*)(&__MBAR[0xB560])) #define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560]))
#define MCF_USB_EP6ISR (*(vuint32*)(&__MBAR[0xB564])) #define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564]))
#define MCF_USB_EP6IMR (*(vuint32*)(&__MBAR[0xB568])) #define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568]))
#define MCF_USB_EP6FRCFGR (*(vuint32*)(&__MBAR[0xB56C])) #define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C]))
#define MCF_USB_EP6FDR (*(vuint32*)(&__MBAR[0xB570])) #define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570]))
#define MCF_USB_EP6FSR (*(vuint32*)(&__MBAR[0xB574])) #define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574]))
#define MCF_USB_EP6FCR (*(vuint32*)(&__MBAR[0xB578])) #define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578]))
#define MCF_USB_EP6FAR (*(vuint32*)(&__MBAR[0xB57C])) #define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C]))
#define MCF_USB_EP6FRP (*(vuint32*)(&__MBAR[0xB580])) #define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580]))
#define MCF_USB_EP6FWP (*(vuint32*)(&__MBAR[0xB584])) #define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584]))
#define MCF_USB_EP6LRFP (*(vuint32*)(&__MBAR[0xB588])) #define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588]))
#define MCF_USB_EP6LWFP (*(vuint32*)(&__MBAR[0xB58C])) #define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C]))
#define MCF_USB_IFR(x) (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)])) #define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
#define MCF_USB_EPOUTACR(x) (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)])) #define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTMPSR(x) (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)])) #define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTIFR(x) (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)])) #define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSR(x) (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)])) #define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
#define MCF_USB_EPOUTSFR(x) (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)])) #define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
#define MCF_USB_EPINACR(x) (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)])) #define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
#define MCF_USB_EPINMPSR(x) (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)])) #define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
#define MCF_USB_EPINIFR(x) (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)])) #define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
#define MCF_USB_EPINSR(x) (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)])) #define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
#define MCF_USB_EPINSFR(x) (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)])) #define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
#define MCF_USB_EPSTAT(x) (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)])) #define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
#define MCF_USB_EPISR(x) (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)])) #define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
#define MCF_USB_EPIMR(x) (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)])) #define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
#define MCF_USB_EPFRCFGR(x) (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)])) #define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
#define MCF_USB_EPFDR(x) (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)])) #define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
#define MCF_USB_EPFSR(x) (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)])) #define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
#define MCF_USB_EPFCR(x) (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)])) #define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
#define MCF_USB_EPFAR(x) (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)])) #define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
#define MCF_USB_EPFRP(x) (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)])) #define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
#define MCF_USB_EPFWP(x) (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)])) #define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
#define MCF_USB_EPLRFP(x) (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)])) #define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
#define MCF_USB_EPLWFP(x) (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)])) #define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
/* Bit definitions and macros for MCF_USB_USBAISR */ /* Bit definitions and macros for MCF_USB_USBAISR */

22
include/MCF5475_XLB.h
View File

@@ -24,17 +24,17 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_XLB_XARB_CFG (*(vuint32*)(&__MBAR[0x240])) #define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&__MBAR[0x240]))
#define MCF_XLB_XARB_VER (*(vuint32*)(&__MBAR[0x244])) #define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&__MBAR[0x244]))
#define MCF_XLB_XARB_SR (*(vuint32*)(&__MBAR[0x248])) #define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&__MBAR[0x248]))
#define MCF_XLB_XARB_IMR (*(vuint32*)(&__MBAR[0x24C])) #define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&__MBAR[0x24C]))
#define MCF_XLB_XARB_ADRCAP (*(vuint32*)(&__MBAR[0x250])) #define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&__MBAR[0x250]))
#define MCF_XLB_XARB_SIGCAP (*(vuint32*)(&__MBAR[0x254])) #define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&__MBAR[0x254]))
#define MCF_XLB_XARB_ADRTO (*(vuint32*)(&__MBAR[0x258])) #define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&__MBAR[0x258]))
#define MCF_XLB_XARB_DATTO (*(vuint32*)(&__MBAR[0x25C])) #define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&__MBAR[0x25C]))
#define MCF_XLB_XARB_BUSTO (*(vuint32*)(&__MBAR[0x260])) #define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&__MBAR[0x260]))
#define MCF_XLB_XARB_PRIEN (*(vuint32*)(&__MBAR[0x264])) #define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&__MBAR[0x264]))
#define MCF_XLB_XARB_PRI (*(vuint32*)(&__MBAR[0x268])) #define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&__MBAR[0x268]))
/* Bit definitions and macros for MCF_XLB_XARB_CFG */ /* Bit definitions and macros for MCF_XLB_XARB_CFG */

88
lcf/DDRAM.lcf Normal file
View File

@@ -0,0 +1,88 @@
# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
code (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0
}
SECTIONS {
#BaS Basis adresse
___Bas_base = 0x1FE00000;
# Board Memory map definitions from linker command files:
# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE
# linker symbols must be defined in the linker command file.
#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
___BOOT_FLASH = 0xE0000000;
___BOOT_FLASH_SIZE = 0x00800000;
#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
___SDRAM = 0x00000000;
___SDRAM_SIZE = 0x20000000;
#VIDEO RAM BASIS
___VRAM = 0x60000000;
# MCF5475 Derivative Memory map definitions from linker command files:
# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
# linker symbols must be defined in the linker command file.
# Memory mapped registers
___MBAR = 0xFF000000;
___MMUBAR = 0xFF040000;
# 4KB on-chip Core SRAM0: -> exception table and exception stack
___RAMBAR0 = 0xFF100000;
___RAMBAR0_SIZE = 0x00001000;
___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
# 4KB on-chip Core SRAM1: -> modified code
___RAMBAR1 = 0xFF101000;
___RAMBAR1_SIZE = 0x00001000;
# Systemveriablem:******************************************
# RAMBAR0 0 bis 0x7FF -> exception vectoren
_rt_mod = ___RAMBAR0 + 0x800;
_rt_ssp = ___RAMBAR0 + 0x804;
_rt_usp = ___RAMBAR0 + 0x808;
_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01
_rt_cacr = ___RAMBAR0 + 0x810; # 002
_rt_asid = ___RAMBAR0 + 0x814; # 003
_rt_acr0 = ___RAMBAR0 + 0x818; # 004
_rt_acr1 = ___RAMBAR0 + 0x81c; # 005
_rt_acr2 = ___RAMBAR0 + 0x820; # 006
_rt_acr3 = ___RAMBAR0 + 0x824; # 007
_rt_mmubar = ___RAMBAR0 + 0x828; # 008
_rt_sr = ___RAMBAR0 + 0x82c;
_d0_save = ___RAMBAR0 + 0x830;
_a7_save = ___RAMBAR0 + 0x834;
_video_tlb = ___RAMBAR0 + 0x838;
_video_sbt = ___RAMBAR0 + 0x83C;
_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f
#***********************************************************
# 32KB on-chip System SRAM
___SYS_SRAM = 0xFF010000;
___SYS_SRAM_SIZE = 0x00008000;
.text :
{
startcf.c(.text)
sysinit.c(.text)
BaS.c(.text)
sd_card.c(.text)
mmu.s(.text)
exceptions.s(.text)
supervisor.s(.text)
ewf.s(.text)
illegal_instruction.s(.text)
last.c(.text)
. = ALIGN (0x4);
} > code
}

88
lcf/FLASH.lcf Normal file
View File

@@ -0,0 +1,88 @@
# Sample Linker Command File for CodeWarrior for ColdFire
KEEP_SECTION {.vectortable}
# Memory ranges
MEMORY {
code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000
}
SECTIONS {
#BaS Basis adresse
___Bas_base = 0x1FE00000;
# Board Memory map definitions from linker command files:
# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE
# linker symbols must be defined in the linker command file.
#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
___BOOT_FLASH = 0xE0000000;
___BOOT_FLASH_SIZE = 0x00800000;
#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
___SDRAM = 0x00000000;
___SDRAM_SIZE = 0x20000000;
#VIDEO RAM BASIS
___VRAM = 0x60000000;
# MCF5475 Derivative Memory map definitions from linker command files:
# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
# linker symbols must be defined in the linker command file.
# Memory mapped registers
___MBAR = 0xFF000000;
___MMUBAR = 0xFF040000;
# 4KB on-chip Core SRAM0: -> exception table and exception stack
___RAMBAR0 = 0xFF100000;
___RAMBAR0_SIZE = 0x00001000;
___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
# 4KB on-chip Core SRAM1: -> modified code
___RAMBAR1 = 0xFF101000;
___RAMBAR1_SIZE = 0x00001000;
# Systemveriablem:******************************************
# RAMBAR0 0 bis 0x7FF -> exception vectoren
_rt_mod = ___RAMBAR0 + 0x800;
_rt_ssp = ___RAMBAR0 + 0x804;
_rt_usp = ___RAMBAR0 + 0x808;
_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01
_rt_cacr = ___RAMBAR0 + 0x810; # 002
_rt_asid = ___RAMBAR0 + 0x814; # 003
_rt_acr0 = ___RAMBAR0 + 0x818; # 004
_rt_acr1 = ___RAMBAR0 + 0x81c; # 005
_rt_acr2 = ___RAMBAR0 + 0x820; # 006
_rt_acr3 = ___RAMBAR0 + 0x824; # 007
_rt_mmubar = ___RAMBAR0 + 0x828; # 008
_rt_sr = ___RAMBAR0 + 0x82c;
_d0_save = ___RAMBAR0 + 0x830;
_a7_save = ___RAMBAR0 + 0x834;
_video_tlb = ___RAMBAR0 + 0x838;
_video_sbt = ___RAMBAR0 + 0x83C;
_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f
#***********************************************************
# 32KB on-chip System SRAM
___SYS_SRAM = 0xFF010000;
___SYS_SRAM_SIZE = 0x00008000;
.code : {} > code
.text :
{
startcf.c(.text)
sysinit.c(.text)
BaS.c(.text)
sd_card.c(.text)
mmu.s(.text)
exceptions.s(.text)
supervisor.s(.text)
ewf.s(.text)
illegal_instruction.s(.text)
last.c(.text)
} >> code
}

2
sources/BaS.c
View File

@@ -203,7 +203,7 @@ void BaS(void)
/* TT-RAM */ /* TT-RAM */
* (uint32_t *) 0x5a4 = __Bas_base; /* ramtop TOS system variable */ * (uint32_t *) 0x5a4 = (uint32_t *) __Bas_base; /* ramtop TOS system variable */
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
/* init ACIA */ /* init ACIA */

67
sources/sd_card.c
View File

@@ -3,6 +3,7 @@
*/ */
#include <MCF5475.h> #include <MCF5475.h>
#include <stdint.h>
#define dspi_dtar0 0x0c #define dspi_dtar0 0x0c
#define dspi_dsr 0x2c #define dspi_dsr 0x2c
@@ -13,54 +14,48 @@
extern void wait_10ms(void); extern void wait_10ms(void);
void sd_com(void) // byt senden und holen --------------------- uint8_t sd_com(uint32_t cmd)
{ {
uint8_t res;
asm MCF_DSPI_DTFR = cmd;
{ while (! MCF_DSPI_DSR & (1 << 7));
move.l d4,dspi_dtfr(a0) res = MCF_DSPI_DRFR;
wait_auf_complett: MCF_DSPI_DSR = -1L;
btst.b #7,dspi_dsr(a0)
beq wait_auf_complett return res;
move.l dspi_drfr(a0),d5
mov3q.l #-1,dspi_dsr(a0) // clr status register
}
} }
void sd_get_status(void) // status holen ------------------------------- /*
* fetch status from SD controller
*/
uint8_t sd_get_status(void)
{ {
asm uint8_t res;
{
sd_get_status: while ((res = sd_com(0xff)) == 0xff);
move.b #0xff,d4
bsr sd_com return res;
cmp.b #0xff,d5
beq sd_get_status
}
} }
void sd_rcv_info(void) // daten holen ---------------------------- void sd_rcv_info(uint8_t *buf, uint32_t size)
{ {
asm uint32_t rcvd = 0;
{
moveq #18,d3 // 16 byts + 2 byts crc while (sd_get_status() != 0xfe); /* loop until data available */
move.b #0xff,d4
sd_rcv_rb_w: do {
bsr sd_get_status *buf++ = sd_com(0x18);
cmp.b #0xfe,d5 // daten bereit? rcvd++;
bne sd_rcv_rb_w // nein-> } while (rcvd <= size);
sd_rcv_rd_rb:
bsr sd_com
move.b d5,(a2)+
subq.l #1,d3
bne sd_rcv_rd_rb
}
} }
void sd_card_idle(void) void sd_card_idle(void)
{ {
#ifdef _NOT_USED_
asm asm
{ {
// sd idle // sd idle
@@ -85,8 +80,11 @@ void sd_card_idle(void)
move.b #0x95,d4 move.b #0x95,d4
bsr sd_com bsr sd_com
} }
#endif
} }
#ifdef _NOT_USED_
int sd_card_init(void) int sd_card_init(void)
{ {
@@ -591,3 +589,4 @@ sd_csw_ok:
} }
return status; return status;
} }
#endif /* _NOT_USED */

10
sources/sd_ide.c
View File

@@ -3,10 +3,10 @@
#include "MCF5475.h" #include "MCF5475.h"
#include "startcf.h" #include "startcf.h"
extern unsigned long far __SP_AFTER_RESET[]; extern unsigned long __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[]; extern unsigned long __Bas_base[];
/* imported routines */ /* imported routines */
//extern int warten_20ms(); //extern int warten_20ms();
//extern int warten_200us(); //extern int warten_200us();
//extern int warten_10us(); //extern int warten_10us();
@@ -112,7 +112,7 @@ wait_of_aktiv:
sd_init_ok: sd_init_ok:
// blockgr<67>sse 512byt // blockgr<67>sse 512byt
sd_bg: sd_bg:
bsr sd_16clk bsr sd_16clk
moveq #0x50,d4 moveq #0x50,d4
@@ -451,7 +451,7 @@ ide_test_loop3:
bsr drq_wait bsr drq_wait
bsr ds_tx bsr ds_tx
bsr wait_int bsr wait_int
// fertig und zur<75>ck // fertig und zur<75>ck
nop nop
rts rts
// wait auf int // wait auf int

29
sources/startcf.S → sources/startcf.c
View File

@@ -16,37 +16,31 @@
* main it will call C++ destructors and call exit to terminate. * main it will call C++ destructors and call exit to terminate.
*/ */
#ifdef __cplusplus
#pragma cplusplus off
#endif
#pragma PID off
#pragma PIC off
#include <MCF5475.h> #include <MCF5475.h>
/* imported data */
/* imported data */ extern uint32_t _SP_INIT, _SDA_BASE;
extern uint32_t _START_BSS, _END_BSS;
extern uint32_t _START_SBSS, _END_SBSS;
extern uint32_t __DATA_RAM, __DATA_ROM, __DATA_END;
extern uint32_t __Bas_base;
extern unsigned long far _SP_INIT, _SDA_BASE; extern uint32_t __SUP_SP,__BOOT_FLASH;
extern unsigned long far _START_BSS, _END_BSS; extern uint32_t rt_mbar;
extern unsigned long far _START_SBSS, _END_SBSS;
extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
extern unsigned long far __Bas_base;
extern unsigned long far __SUP_SP,__BOOT_FLASH; /* imported routines */
extern unsigned long far rt_mbar;
/* imported routines */
extern int BaS(int, char **); extern int BaS(int, char **);
/* exported routines */ /* exported routines */
extern void __initialize_hardware(void); extern void __initialize_hardware(void);
extern void init_slt(void); extern void init_slt(void);
void _startup(void) void _startup(void)
{ {
#ifdef _NOT_USED_
asm("\n\t" asm("\n\t"
"bra warmstart\n\t" "bra warmstart\n\t"
"jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t" "jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t"
@@ -79,4 +73,5 @@ void _startup(void)
// initialize any hardware specific issues // initialize any hardware specific issues
bra __initialize_hardware bra __initialize_hardware
"); ");
#endif /* _NOT_USED_ */
} }

2
sources/startcf.h
View File

@@ -40,7 +40,7 @@
#define halten_movep #define halten_movep
#define halten_ewf #define halten_ewf
#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C])) #define DIP_SWITCH (*(volatile uint8_t *)(&__MBAR[0xA2C]))
#define DIP_SWITCHa ___MBAR + 0xA2C #define DIP_SWITCHa ___MBAR + 0xA2C
#define sca_page_ID 6 #define sca_page_ID 6

6
sources/sysinit.c
View File

@@ -237,7 +237,7 @@ void init_fpga(void)
/* /*
* excerpt from an Altera configuration manual: * excerpt from an Altera configuration manual:
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
* configuration cycle consists of 3 stages<65>reset, configuration, and initialization. * configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
* While nCONFIG is low, the device is in reset. When the device comes out of reset, * While nCONFIG is low, the device is in reset. When the device comes out of reset,
* nCONFIG must be at a logic high level in order for the device to release the open-drain * nCONFIG must be at a logic high level in order for the device to release the open-drain
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
@@ -527,8 +527,8 @@ void test_upd720101(void)
* TFP410 (vdi) einschalten /* * TFP410 (vdi) einschalten /*
*/ */
void vdi_on(void) { void vdi_on(void) {
uint8 RBYT; uint8_t RBYT;
uint8 DBYT; uint8_t DBYT;
int versuche; int versuche;
int startzeit; int startzeit;