From 756ab9cd6e56671ae169dd42d8f0f462cbc1488a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20G=C3=A1lvez?= Date: Mon, 3 Jan 2011 08:10:50 +0000 Subject: [PATCH] Moved source_fa into trunk --- .../FireBee/Flash/BaS_15_12_10.S19 | 362 + .../FireBee/Flash/BaS_15_12_10.zip | Bin 0 -> 7354 bytes BaS_codewarrior/FireBee/Flash/emutos2.s19 | 23921 ++++++++ .../FireBee/Flash/firebee_fpga_15_12_10.rbf | Bin 0 -> 428953 bytes .../FireBee/Flash/firebee_fpga_15_12_10.zip | Bin 0 -> 192203 bytes .../FireBee/Flash/firetos_firebee.hex | 45217 ++++++++++++++++ .../FireBee/MLAB/firebee1/Makefile | 19 + .../FireBee/MLAB/firebee1/NMakefile | 19 + .../FireBee/MLAB/firebee1/PS2Atari_v1_4.asm | 619 + .../FireBee/MLAB/firebee1/Thumbs.db | Bin 0 -> 22528 bytes .../FireBee/MLAB/firebee1/circuit.bmp | Bin 0 -> 32062 bytes .../FireBee/MLAB/firebee1/firebee1.asm | 845 + .../FireBee/MLAB/firebee1/firebee1.cof | Bin 0 -> 13640 bytes .../FireBee/MLAB/firebee1/firebee1.err | 0 .../FireBee/MLAB/firebee1/firebee1.hex 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FPGA_quartus/altpll4.cmp | 30 + FPGA_quartus/altpll4.inc | 31 + FPGA_quartus/altpll4.mif | 174 + FPGA_quartus/altpll4.ppf | 17 + FPGA_quartus/altpll4.qip | 7 + FPGA_quartus/altpll4.tdf | 298 + FPGA_quartus/altpll_reconfig0.bsf | 162 + FPGA_quartus/altpll_reconfig0.qip | 5 + FPGA_quartus/altpll_reconfig1.bsf | 162 + FPGA_quartus/altpll_reconfig1.cmp | 38 + FPGA_quartus/altpll_reconfig1.inc | 39 + FPGA_quartus/altpll_reconfig1.qip | 6 + FPGA_quartus/altpll_reconfig1.tdf | 144 + FPGA_quartus/altpll_reconfig1_pllrcfg_bju.tdf | 583 + FPGA_quartus/altpll_reconfig1_pllrcfg_t4q.tdf | 582 + FPGA_quartus/firebee1.asm.rpt | 128 + FPGA_quartus/firebee1.bdf | 5837 ++ FPGA_quartus/firebee1.done | 1 + FPGA_quartus/firebee1.dpf | 12 + FPGA_quartus/firebee1.fit.rpt | 6866 +++ FPGA_quartus/firebee1.fit.summary | 16 + FPGA_quartus/firebee1.flow.rpt | 380 + FPGA_quartus/firebee1.map.rpt | 8590 +++ FPGA_quartus/firebee1.map.summary | 14 + FPGA_quartus/firebee1.pin | 557 + FPGA_quartus/firebee1.qsf | 740 + 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| 22 + FPGA_quartus/lpm_counter0.qip | 5 + FPGA_quartus/lpm_counter0.vhd | 126 + FPGA_quartus/lpm_counter0_wave0.jpg | Bin 0 -> 56372 bytes FPGA_quartus/lpm_counter0_waveforms.html | 13 + FPGA_quartus/lpm_counter1_waveforms.html | 16 + FPGA_quartus/lpm_fifo_dc0_waveforms.html | 16 + FPGA_quartus/lpm_latch0.bsf | 53 + FPGA_quartus/lpm_latch0.cmp | 23 + FPGA_quartus/lpm_latch0.qip | 5 + FPGA_quartus/lpm_latch0.vhd | 110 + FPGA_quartus/serv_req_info.txt | 115 + FPGA_quartus/undo_redo.txt | 0 Flash/BaS_15_12_10.S19 | 362 + Flash/BaS_15_12_10.zip | Bin 0 -> 7354 bytes Flash/emutos2.s19 | 23921 ++++++++ Flash/firebee_fpga_15_12_10.rbf | Bin 0 -> 428953 bytes Flash/firebee_fpga_15_12_10.zip | Bin 0 -> 192203 bytes Flash/firetos_firebee.hex | 45217 ++++++++++++++++ MLAB/firebee1/Makefile | 19 + MLAB/firebee1/NMakefile | 19 + MLAB/firebee1/PS2Atari_v1_4.asm | 619 + MLAB/firebee1/Thumbs.db | Bin 0 -> 22528 bytes MLAB/firebee1/circuit.bmp | Bin 0 -> 32062 bytes MLAB/firebee1/firebee1.asm | 845 + MLAB/firebee1/firebee1.cof | Bin 0 -> 13640 bytes MLAB/firebee1/firebee1.err | 0 MLAB/firebee1/firebee1.hex | 82 + MLAB/firebee1/firebee1.lst | 1979 + MLAB/firebee1/firebee1.map | 188 + MLAB/firebee1/firebee1.mcp | 53 + MLAB/firebee1/firebee1.mcs | 71 + MLAB/firebee1/firebee1.mcw | Bin 0 -> 33280 bytes MLAB/firebee1/firebeei1.map | 156 + MLAB/firebee1/readme.txt | 125 + usb/store/config.h | 4 +- usb/store/main.c | 1 + usb/store/makefile | 2 +- usb/store/usb_storage.c | 8 +- 657 files changed, 288732 insertions(+), 7 deletions(-) create mode 100644 BaS_codewarrior/FireBee/Flash/BaS_15_12_10.S19 create mode 100644 BaS_codewarrior/FireBee/Flash/BaS_15_12_10.zip create mode 100644 BaS_codewarrior/FireBee/Flash/emutos2.s19 create mode 100644 BaS_codewarrior/FireBee/Flash/firebee_fpga_15_12_10.rbf create mode 100644 BaS_codewarrior/FireBee/Flash/firebee_fpga_15_12_10.zip create mode 100644 BaS_codewarrior/FireBee/Flash/firetos_firebee.hex create mode 100644 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zUblYTGk@PcLdfvn?JySkkKzQFHN{!4PK@TDqEH;}?cjHV-^8Jdzx75&iO6kP#_6F=Nw`M+`z;u(QMINBSF|7X8R(PT7W)IVO-Cw&JMU{}OB^~I!r z+Tovla8mD@9sE%6Q~VMCA_xEQ{)y2hU0&3Co9_dSQ3U;%|C0`W?b|B4TI+vQO~OA3 p@{N65{H*6{q6-kPRIV!={`Ngo^!GyrADWoRc?OxnUYxIs{~xh1VGaNQ literal 0 HcmV?d00001 diff --git a/BaS_codewarrior/firebeeV1/flash_config.xml b/BaS_codewarrior/firebeeV1/flash_config.xml new file mode 100644 index 0000000..ce2e67e --- /dev/null +++ b/BaS_codewarrior/firebeeV1/flash_config.xml @@ -0,0 +1,47 @@ + + + + + true + 5474 + PEMICRO_USB + true + C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg + 0x00000000 + 0x00006000 + true + false + + + + 0xE0000000 + M29W640DB + 4Mx16x1 + 0xE0000000 + 0xE07FFFFF + + + + true + C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19 + Auto Detect + false + 0xFF800000 + 0xFFFFFFFF + false + 0xC0200000 + + + + false + + false + + + + FileOnTarg + 0xFF800000 + 0x007FFFFF + + + diff --git a/BaS_codewarrior/firebeeV1/hardware_diagnostic.xml b/BaS_codewarrior/firebeeV1/hardware_diagnostic.xml new file mode 100644 index 0000000..b45676f --- /dev/null +++ b/BaS_codewarrior/firebeeV1/hardware_diagnostic.xml @@ -0,0 +1,40 @@ + + + + + true + 5474 + PEMICRO_USB + true + {CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg + + + + read + long_word + 0x60001000 + FFFFFFFF + + + + read + long_word + 0x00100000 + 0x67 + 1000 + + + + true + true + true + 0x00DE1000 + 0x00DE11FF + long_word + 1 + false + 0x00000100 + 0x0000FFFF + + + diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475.h b/BaS_codewarrior/firebeeV1/headers/MCF5475.h new file mode 100644 index 0000000..8feab2d --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475.h @@ -0,0 +1,93 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + + +/********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +#ifdef __cplusplus +extern "C" { +#endif + +#pragma define_section system ".system" far_absolute RW + +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +extern __declspec(system) uint8 __MBAR[]; +extern __declspec(system) uint8 __MMUBAR[]; +extern __declspec(system) uint8 __RAMBAR0[]; +extern __declspec(system) uint8 __RAMBAR0_SIZE[]; +extern __declspec(system) uint8 __RAMBAR1[]; +extern __declspec(system) uint8 __RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32)__MBAR +#define MMUBAR_ADDRESS (uint32)__MMUBAR +#define RAMBAR0_ADDRESS (uint32)__RAMBAR0 +#define RAMBAR0_SIZE (uint32)__RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32)__RAMBAR1 +#define RAMBAR1_SIZE (uint32)__RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#ifdef __cplusplus +} +#endif + + +#endif /* __MCF5475_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_CLOCK.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_CLOCK.h new file mode 100644 index 0000000..96e173f --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(vuint32*)(&__MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_CTM.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_CTM.h new file mode 100644 index 0000000..1b516fd --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(vuint32*)(&__MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(vuint32*)(&__MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(vuint32*)(&__MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(vuint32*)(&__MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(vuint32*)(&__MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(vuint32*)(&__MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(vuint32*)(&__MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(vuint32*)(&__MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_DMA.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_DMA.h new file mode 100644 index 0000000..a9667c1 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_DMA.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(vuint32*)(&__MBAR[0x8000])) +#define MCF_DMA_CP (*(vuint32*)(&__MBAR[0x8004])) +#define MCF_DMA_EP (*(vuint32*)(&__MBAR[0x8008])) +#define MCF_DMA_VP (*(vuint32*)(&__MBAR[0x800C])) +#define MCF_DMA_PTD (*(vuint32*)(&__MBAR[0x8010])) +#define MCF_DMA_DIPR (*(vuint32*)(&__MBAR[0x8014])) +#define MCF_DMA_DIMR (*(vuint32*)(&__MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(vuint16*)(&__MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(vuint16*)(&__MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(vuint16*)(&__MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(vuint16*)(&__MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(vuint16*)(&__MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(vuint16*)(&__MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(vuint16*)(&__MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(vuint16*)(&__MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(vuint16*)(&__MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(vuint16*)(&__MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(vuint16*)(&__MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(vuint16*)(&__MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(vuint16*)(&__MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(vuint16*)(&__MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(vuint16*)(&__MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(vuint16*)(&__MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(vuint8 *)(&__MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(vuint8 *)(&__MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(vuint8 *)(&__MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(vuint8 *)(&__MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(vuint8 *)(&__MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(vuint8 *)(&__MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(vuint8 *)(&__MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(vuint8 *)(&__MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(vuint8 *)(&__MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(vuint8 *)(&__MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(vuint8 *)(&__MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(vuint8 *)(&__MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(vuint8 *)(&__MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(vuint8 *)(&__MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(vuint8 *)(&__MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(vuint8 *)(&__MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(vuint8 *)(&__MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(vuint8 *)(&__MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(vuint8 *)(&__MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(vuint8 *)(&__MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(vuint8 *)(&__MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(vuint8 *)(&__MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(vuint8 *)(&__MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(vuint8 *)(&__MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(vuint8 *)(&__MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(vuint8 *)(&__MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(vuint8 *)(&__MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(vuint8 *)(&__MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(vuint8 *)(&__MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(vuint8 *)(&__MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(vuint8 *)(&__MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(vuint8 *)(&__MBAR[0x805B])) +#define MCF_DMA_IMCR (*(vuint32*)(&__MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(vuint32*)(&__MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(vuint32*)(&__MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(vuint32*)(&__MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(vuint32*)(&__MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(vuint32*)(&__MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC0(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC1(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC2(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC3(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC4(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC6(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC7(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC8(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC9(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC11(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC12(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC13(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC14(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC15(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_DSPI.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_DSPI.h new file mode 100644 index 0000000..ec4369d --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(vuint32*)(&__MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(vuint32*)(&__MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(vuint32*)(&__MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(vuint32*)(&__MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(vuint32*)(&__MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(vuint32*)(&__MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(vuint32*)(&__MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(vuint32*)(&__MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(vuint32*)(&__MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(vuint32*)(&__MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(vuint32*)(&__MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(vuint32*)(&__MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(vuint32*)(&__MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(vuint32*)(&__MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(vuint32*)(&__MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(vuint32*)(&__MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(vuint32*)(&__MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(vuint32*)(&__MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(vuint32*)(&__MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(vuint32*)(&__MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(vuint32*)(&__MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(vuint32*)(&__MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_EPORT.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_EPORT.h new file mode 100644 index 0000000..6616406 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(vuint16*)(&__MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(vuint8 *)(&__MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(vuint8 *)(&__MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(vuint8 *)(&__MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(vuint8 *)(&__MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(vuint8 *)(&__MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_FBCS.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_FBCS.h new file mode 100644 index 0000000..26bb585 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(vuint32*)(&__MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(vuint32*)(&__MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(vuint32*)(&__MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(vuint32*)(&__MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(vuint32*)(&__MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(vuint32*)(&__MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(vuint32*)(&__MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(vuint32*)(&__MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(vuint32*)(&__MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(vuint32*)(&__MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(vuint32*)(&__MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(vuint32*)(&__MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(vuint32*)(&__MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(vuint32*)(&__MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(vuint32*)(&__MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(vuint32*)(&__MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(vuint32*)(&__MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(vuint32*)(&__MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_FEC.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_FEC.h new file mode 100644 index 0000000..01a0ae7 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(vuint32*)(&__MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(vuint32*)(&__MBAR[0x9008])) +#define MCF_FEC0_ECR (*(vuint32*)(&__MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(vuint32*)(&__MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(vuint32*)(&__MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(vuint32*)(&__MBAR[0x9064])) +#define MCF_FEC0_RCR (*(vuint32*)(&__MBAR[0x9084])) +#define MCF_FEC0_RHR (*(vuint32*)(&__MBAR[0x9088])) +#define MCF_FEC0_TCR (*(vuint32*)(&__MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(vuint32*)(&__MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(vuint32*)(&__MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(vuint32*)(&__MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(vuint32*)(&__MBAR[0x9118])) +#define MCF_FEC0_IALR (*(vuint32*)(&__MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(vuint32*)(&__MBAR[0x9120])) +#define MCF_FEC0_GALR (*(vuint32*)(&__MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(vuint32*)(&__MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(vuint32*)(&__MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(vuint32*)(&__MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(vuint32*)(&__MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(vuint32*)(&__MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(vuint32*)(&__MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(vuint32*)(&__MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(vuint32*)(&__MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(vuint32*)(&__MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(vuint32*)(&__MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(vuint32*)(&__MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(vuint32*)(&__MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(vuint32*)(&__MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(vuint32*)(&__MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(vuint32*)(&__MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(vuint32*)(&__MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(vuint32*)(&__MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(vuint32*)(&__MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(vuint32*)(&__MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(vuint32*)(&__MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(vuint32*)(&__MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(vuint32*)(&__MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(vuint32*)(&__MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(vuint32*)(&__MBAR[0x9808])) +#define MCF_FEC1_ECR (*(vuint32*)(&__MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(vuint32*)(&__MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(vuint32*)(&__MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(vuint32*)(&__MBAR[0x9864])) +#define MCF_FEC1_RCR (*(vuint32*)(&__MBAR[0x9884])) +#define MCF_FEC1_RHR (*(vuint32*)(&__MBAR[0x9888])) +#define MCF_FEC1_TCR (*(vuint32*)(&__MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(vuint32*)(&__MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(vuint32*)(&__MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(vuint32*)(&__MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(vuint32*)(&__MBAR[0x9918])) +#define MCF_FEC1_IALR (*(vuint32*)(&__MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(vuint32*)(&__MBAR[0x9920])) +#define MCF_FEC1_GALR (*(vuint32*)(&__MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(vuint32*)(&__MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(vuint32*)(&__MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(vuint32*)(&__MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(vuint32*)(&__MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(vuint32*)(&__MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(vuint32*)(&__MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(vuint32*)(&__MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(vuint32*)(&__MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(vuint32*)(&__MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(vuint32*)(&__MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(vuint32*)(&__MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(vuint32*)(&__MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(vuint32*)(&__MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(vuint32*)(&__MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(vuint32*)(&__MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(vuint32*)(&__MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(vuint32*)(&__MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(vuint32*)(&__MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(vuint32*)(&__MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(vuint32*)(&__MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(vuint32*)(&__MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(vuint32*)(&__MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_GPIO.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_GPIO.h new file mode 100644 index 0000000..7ef3dce --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_GPT.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_GPT.h new file mode 100644 index 0000000..ab99d05 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(vuint32*)(&__MBAR[0x800])) +#define MCF_GPT0_GCIR (*(vuint32*)(&__MBAR[0x804])) +#define MCF_GPT0_GPWM (*(vuint32*)(&__MBAR[0x808])) +#define MCF_GPT0_GSR (*(vuint32*)(&__MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(vuint32*)(&__MBAR[0x810])) +#define MCF_GPT1_GCIR (*(vuint32*)(&__MBAR[0x814])) +#define MCF_GPT1_GPWM (*(vuint32*)(&__MBAR[0x818])) +#define MCF_GPT1_GSR (*(vuint32*)(&__MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(vuint32*)(&__MBAR[0x820])) +#define MCF_GPT2_GCIR (*(vuint32*)(&__MBAR[0x824])) +#define MCF_GPT2_GPWM (*(vuint32*)(&__MBAR[0x828])) +#define MCF_GPT2_GSR (*(vuint32*)(&__MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(vuint32*)(&__MBAR[0x830])) +#define MCF_GPT3_GCIR (*(vuint32*)(&__MBAR[0x834])) +#define MCF_GPT3_GPWM (*(vuint32*)(&__MBAR[0x838])) +#define MCF_GPT3_GSR (*(vuint32*)(&__MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_I2C.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_I2C.h new file mode 100644 index 0000000..dbbd626 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(vuint8 *)(&__MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(vuint8 *)(&__MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_INTC.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_INTC.h new file mode 100644 index 0000000..4dfc6d2 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(vuint32*)(&__MBAR[0x700])) +#define MCF_INTC_IPRL (*(vuint32*)(&__MBAR[0x704])) +#define MCF_INTC_IMRH (*(vuint32*)(&__MBAR[0x708])) +#define MCF_INTC_IMRL (*(vuint32*)(&__MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(vuint32*)(&__MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(vuint32*)(&__MBAR[0x714])) +#define MCF_INTC_IRLR (*(vuint8 *)(&__MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(vuint8 *)(&__MBAR[0x719])) +#define MCF_INTC_ICR01 (*(vuint8 *)(&__MBAR[0x741])) +#define MCF_INTC_ICR02 (*(vuint8 *)(&__MBAR[0x742])) +#define MCF_INTC_ICR03 (*(vuint8 *)(&__MBAR[0x743])) +#define MCF_INTC_ICR04 (*(vuint8 *)(&__MBAR[0x744])) +#define MCF_INTC_ICR05 (*(vuint8 *)(&__MBAR[0x745])) +#define MCF_INTC_ICR06 (*(vuint8 *)(&__MBAR[0x746])) +#define MCF_INTC_ICR07 (*(vuint8 *)(&__MBAR[0x747])) +#define MCF_INTC_ICR08 (*(vuint8 *)(&__MBAR[0x748])) +#define MCF_INTC_ICR09 (*(vuint8 *)(&__MBAR[0x749])) +#define MCF_INTC_ICR10 (*(vuint8 *)(&__MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(vuint8 *)(&__MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(vuint8 *)(&__MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(vuint8 *)(&__MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(vuint8 *)(&__MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(vuint8 *)(&__MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(vuint8 *)(&__MBAR[0x750])) +#define MCF_INTC_ICR17 (*(vuint8 *)(&__MBAR[0x751])) +#define MCF_INTC_ICR18 (*(vuint8 *)(&__MBAR[0x752])) +#define MCF_INTC_ICR19 (*(vuint8 *)(&__MBAR[0x753])) +#define MCF_INTC_ICR20 (*(vuint8 *)(&__MBAR[0x754])) +#define MCF_INTC_ICR21 (*(vuint8 *)(&__MBAR[0x755])) +#define MCF_INTC_ICR22 (*(vuint8 *)(&__MBAR[0x756])) +#define MCF_INTC_ICR23 (*(vuint8 *)(&__MBAR[0x757])) +#define MCF_INTC_ICR24 (*(vuint8 *)(&__MBAR[0x758])) +#define MCF_INTC_ICR25 (*(vuint8 *)(&__MBAR[0x759])) +#define MCF_INTC_ICR26 (*(vuint8 *)(&__MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(vuint8 *)(&__MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(vuint8 *)(&__MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(vuint8 *)(&__MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(vuint8 *)(&__MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(vuint8 *)(&__MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(vuint8 *)(&__MBAR[0x760])) +#define MCF_INTC_ICR33 (*(vuint8 *)(&__MBAR[0x761])) +#define MCF_INTC_ICR34 (*(vuint8 *)(&__MBAR[0x762])) +#define MCF_INTC_ICR35 (*(vuint8 *)(&__MBAR[0x763])) +#define MCF_INTC_ICR36 (*(vuint8 *)(&__MBAR[0x764])) +#define MCF_INTC_ICR37 (*(vuint8 *)(&__MBAR[0x765])) +#define MCF_INTC_ICR38 (*(vuint8 *)(&__MBAR[0x766])) +#define MCF_INTC_ICR39 (*(vuint8 *)(&__MBAR[0x767])) +#define MCF_INTC_ICR40 (*(vuint8 *)(&__MBAR[0x768])) +#define MCF_INTC_ICR41 (*(vuint8 *)(&__MBAR[0x769])) +#define MCF_INTC_ICR42 (*(vuint8 *)(&__MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(vuint8 *)(&__MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(vuint8 *)(&__MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(vuint8 *)(&__MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(vuint8 *)(&__MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(vuint8 *)(&__MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(vuint8 *)(&__MBAR[0x770])) +#define MCF_INTC_ICR49 (*(vuint8 *)(&__MBAR[0x771])) +#define MCF_INTC_ICR50 (*(vuint8 *)(&__MBAR[0x772])) +#define MCF_INTC_ICR51 (*(vuint8 *)(&__MBAR[0x773])) +#define MCF_INTC_ICR52 (*(vuint8 *)(&__MBAR[0x774])) +#define MCF_INTC_ICR53 (*(vuint8 *)(&__MBAR[0x775])) +#define MCF_INTC_ICR54 (*(vuint8 *)(&__MBAR[0x776])) +#define MCF_INTC_ICR55 (*(vuint8 *)(&__MBAR[0x777])) +#define MCF_INTC_ICR56 (*(vuint8 *)(&__MBAR[0x778])) +#define MCF_INTC_ICR57 (*(vuint8 *)(&__MBAR[0x779])) +#define MCF_INTC_ICR58 (*(vuint8 *)(&__MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(vuint8 *)(&__MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(vuint8 *)(&__MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(vuint8 *)(&__MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(vuint8 *)(&__MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(vuint8 *)(&__MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(vuint8 *)(&__MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(vuint8 *)(&__MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(vuint8 *)(&__MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(vuint8 *)(&__MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(vuint8 *)(&__MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(vuint8 *)(&__MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(vuint8 *)(&__MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(vuint8 *)(&__MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_MMU.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_MMU.h new file mode 100644 index 0000000..84d57b9 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_MMU.h @@ -0,0 +1,77 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MMU_MMUCR (*(vuint32*)(&__MMUBAR[0])) +#define MCF_MMU_MMUOR (*(vuint32*)(&__MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(vuint32*)(&__MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(vuint32*)(&__MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(vuint32*)(&__MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(vuint32*)(&__MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_PAD.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_PAD.h new file mode 100644 index 0000000..9c0fcf7 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(vuint16*)(&__MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(vuint8 *)(&__MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(vuint8 *)(&__MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(vuint16*)(&__MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(vuint16*)(&__MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(vuint16*)(&__MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(vuint8 *)(&__MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(vuint8 *)(&__MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(vuint8 *)(&__MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(vuint8 *)(&__MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(vuint16*)(&__MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(vuint8 *)(&__MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_PCI.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_PCI.h new file mode 100644 index 0000000..47e9e98 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(vuint32*)(&__MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(vuint32*)(&__MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(vuint32*)(&__MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(vuint32*)(&__MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(vuint32*)(&__MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(vuint32*)(&__MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(vuint32*)(&__MBAR[0xB28])) +#define MCF_PCI_PCISID (*(vuint32*)(&__MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(vuint32*)(&__MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(vuint32*)(&__MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(vuint32*)(&__MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(vuint32*)(&__MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(vuint32*)(&__MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(vuint32*)(&__MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(vuint32*)(&__MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(vuint32*)(&__MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(vuint32*)(&__MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(vuint32*)(&__MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(vuint32*)(&__MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(vuint32*)(&__MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(vuint32*)(&__MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(vuint32*)(&__MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(vuint32*)(&__MBAR[0x8408])) +#define MCF_PCI_PCITER (*(vuint32*)(&__MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(vuint32*)(&__MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(vuint32*)(&__MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(vuint32*)(&__MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(vuint32*)(&__MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(vuint32*)(&__MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(vuint32*)(&__MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(vuint32*)(&__MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(vuint32*)(&__MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(vuint32*)(&__MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(vuint32*)(&__MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(vuint32*)(&__MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(vuint32*)(&__MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(vuint32*)(&__MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(vuint32*)(&__MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(vuint32*)(&__MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(vuint32*)(&__MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(vuint32*)(&__MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(vuint32*)(&__MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(vuint32*)(&__MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(vuint32*)(&__MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(vuint32*)(&__MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(vuint32*)(&__MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(vuint32*)(&__MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_PCIARB.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_PCIARB.h new file mode 100644 index 0000000..3e793a1 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(vuint32*)(&__MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(vuint32*)(&__MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_PSC.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_PSC.h new file mode 100644 index 0000000..2165c57 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(vuint8 *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(vuint8 *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(vuint8 *)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(vuint16*)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(vuint8 *)(&__MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(vuint8 *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(vuint8 *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(vuint16*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(vuint16*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(vuint8 *)(&__MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(vuint8 *)(&__MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(vuint8 *)(&__MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(vuint8 *)(&__MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(vuint8 *)(&__MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(vuint8 *)(&__MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(vuint8 *)(&__MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(vuint16*)(&__MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(vuint16*)(&__MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(vuint32*)(&__MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(vuint16*)(&__MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(vuint32*)(&__MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(vuint16*)(&__MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(vuint16*)(&__MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(vuint16*)(&__MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(vuint16*)(&__MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(vuint16*)(&__MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(vuint32*)(&__MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(vuint16*)(&__MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(vuint32*)(&__MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(vuint16*)(&__MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(vuint16*)(&__MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(vuint16*)(&__MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(vuint16*)(&__MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(vuint16*)(&__MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(vuint8 *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(vuint8 *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(vuint8 *)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(vuint16*)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(vuint8 *)(&__MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(vuint8 *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(vuint8 *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(vuint16*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(vuint16*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(vuint8 *)(&__MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(vuint8 *)(&__MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(vuint8 *)(&__MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(vuint8 *)(&__MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(vuint8 *)(&__MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(vuint8 *)(&__MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(vuint8 *)(&__MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(vuint16*)(&__MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(vuint16*)(&__MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(vuint32*)(&__MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(vuint16*)(&__MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(vuint32*)(&__MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(vuint16*)(&__MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(vuint16*)(&__MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(vuint16*)(&__MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(vuint16*)(&__MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(vuint16*)(&__MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(vuint32*)(&__MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(vuint16*)(&__MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(vuint32*)(&__MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(vuint16*)(&__MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(vuint16*)(&__MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(vuint16*)(&__MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(vuint16*)(&__MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(vuint16*)(&__MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(vuint8 *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(vuint8 *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(vuint8 *)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(vuint16*)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(vuint8 *)(&__MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(vuint8 *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(vuint8 *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(vuint16*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(vuint16*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(vuint8 *)(&__MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(vuint8 *)(&__MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(vuint8 *)(&__MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(vuint8 *)(&__MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(vuint8 *)(&__MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(vuint8 *)(&__MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(vuint8 *)(&__MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(vuint16*)(&__MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(vuint16*)(&__MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(vuint32*)(&__MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(vuint16*)(&__MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(vuint32*)(&__MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(vuint16*)(&__MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(vuint16*)(&__MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(vuint16*)(&__MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(vuint16*)(&__MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(vuint16*)(&__MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(vuint32*)(&__MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(vuint16*)(&__MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(vuint32*)(&__MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(vuint16*)(&__MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(vuint16*)(&__MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(vuint16*)(&__MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(vuint16*)(&__MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(vuint16*)(&__MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(vuint8 *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(vuint8 *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(vuint8 *)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(vuint16*)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(vuint8 *)(&__MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(vuint8 *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(vuint8 *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(vuint16*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(vuint16*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(vuint8 *)(&__MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(vuint8 *)(&__MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(vuint8 *)(&__MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(vuint8 *)(&__MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(vuint8 *)(&__MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(vuint8 *)(&__MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(vuint8 *)(&__MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(vuint16*)(&__MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(vuint16*)(&__MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(vuint32*)(&__MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(vuint16*)(&__MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(vuint32*)(&__MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(vuint16*)(&__MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(vuint16*)(&__MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(vuint16*)(&__MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(vuint16*)(&__MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(vuint16*)(&__MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(vuint32*)(&__MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(vuint16*)(&__MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(vuint32*)(&__MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(vuint16*)(&__MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(vuint16*)(&__MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(vuint16*)(&__MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(vuint16*)(&__MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(vuint16*)(&__MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_SDRAMC.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_SDRAMC.h new file mode 100644 index 0000000..843ac12 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(vuint32*)(&__MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(vuint32*)(&__MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(vuint32*)(&__MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(vuint32*)(&__MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(vuint32*)(&__MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(vuint32*)(&__MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(vuint32*)(&__MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(&__MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(&__MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_SEC.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_SEC.h new file mode 100644 index 0000000..ce02c30 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010])) +#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014])) +#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018])) +#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030])) +#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044])) +#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044])) +#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018])) +#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028])) +#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038])) +#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018])) +#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028])) +#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018])) +#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028])) +#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_SIU.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_SIU.h new file mode 100644 index 0000000..498aa91 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_SIU.h @@ -0,0 +1,52 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(vuint32*)(&__MBAR[0x10])) +#define MCF_SIU_SECSACR (*(vuint32*)(&__MBAR[0x38])) +#define MCF_SIU_RSR (*(vuint32*)(&__MBAR[0x44])) +#define MCF_SIU_JTAGID (*(vuint32*)(&__MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_SIU_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_SLT.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_SLT.h new file mode 100644 index 0000000..44a74c6 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(vuint32*)(&__MBAR[0x900])) +#define MCF_SLT0_SCR (*(vuint32*)(&__MBAR[0x904])) +#define MCF_SLT0_SCNT (*(vuint32*)(&__MBAR[0x908])) +#define MCF_SLT0_SSR (*(vuint32*)(&__MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(vuint32*)(&__MBAR[0x910])) +#define MCF_SLT1_SCR (*(vuint32*)(&__MBAR[0x914])) +#define MCF_SLT1_SCNT (*(vuint32*)(&__MBAR[0x918])) +#define MCF_SLT1_SSR (*(vuint32*)(&__MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_SRAM.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_SRAM.h new file mode 100644 index 0000000..7e645fe --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(vuint32*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(vuint32*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(vuint32*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(vuint32*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(vuint32*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_USB.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_USB.h new file mode 100644 index 0000000..da9e6db --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(vuint8 *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(vuint8 *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(vuint8 *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(vuint8 *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(vuint8 *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(vuint8 *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(vuint16*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(vuint16*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(vuint16*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(vuint16*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(vuint16*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(vuint16*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(vuint16*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(vuint16*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(vuint16*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(vuint16*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(vuint16*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(vuint16*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(vuint16*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(vuint16*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(vuint16*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(vuint16*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(vuint16*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(vuint16*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(vuint16*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(vuint16*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(vuint16*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(vuint16*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(vuint16*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(vuint16*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(vuint16*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(vuint16*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(vuint16*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(vuint16*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(vuint16*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(vuint16*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(vuint16*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(vuint16*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(vuint16*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(vuint16*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(vuint16*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(vuint16*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(vuint16*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(vuint16*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(vuint16*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(vuint16*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(vuint16*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(vuint16*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(vuint8 *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(vuint8 *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(vuint16*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(vuint8 *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(vuint8 *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(vuint8 *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(vuint8 *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(vuint16*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(vuint16*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(vuint16*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(vuint8 *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(vuint16*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(vuint8 *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(vuint8 *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(vuint16*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(vuint8 *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(vuint16*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(vuint8 *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(vuint8 *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(vuint16*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(vuint8 *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(vuint16*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(vuint8 *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(vuint8 *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(vuint16*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(vuint8 *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(vuint16*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(vuint8 *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(vuint8 *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(vuint16*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(vuint8 *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(vuint16*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(vuint8 *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(vuint8 *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(vuint16*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(vuint8 *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(vuint16*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(vuint8 *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(vuint8 *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(vuint16*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(vuint8 *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(vuint16*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(vuint8 *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(vuint8 *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(vuint16*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(vuint8 *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(vuint16*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(vuint8 *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(vuint8 *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(vuint16*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(vuint8 *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(vuint16*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(vuint8 *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(vuint8 *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(vuint16*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(vuint8 *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(vuint16*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(vuint8 *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(vuint8 *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(vuint16*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(vuint8 *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(vuint16*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(vuint8 *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(vuint8 *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(vuint16*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(vuint8 *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(vuint16*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(vuint8 *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(vuint8 *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(vuint16*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(vuint32*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(vuint32*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(vuint32*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(vuint32*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(vuint32*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(vuint32*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(vuint32*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(vuint32*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(vuint32*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(vuint32*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(vuint32*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(vuint32*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(vuint32*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(vuint32*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(vuint32*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(vuint32*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(vuint32*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(vuint32*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(vuint32*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(vuint32*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(vuint32*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(vuint32*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(vuint32*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(vuint32*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(vuint32*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(vuint32*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(vuint32*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(vuint32*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(vuint32*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(vuint32*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(vuint32*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(vuint32*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(vuint32*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(vuint32*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(vuint32*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(vuint32*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(vuint32*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(vuint32*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(vuint32*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(vuint32*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(vuint32*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(vuint32*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(vuint32*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(vuint32*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(vuint32*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(vuint32*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(vuint32*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(vuint32*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(vuint32*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(vuint32*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(vuint32*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(vuint32*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(vuint32*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(vuint32*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(vuint32*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(vuint32*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(vuint32*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(vuint32*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(vuint32*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(vuint32*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(vuint32*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(vuint32*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(vuint32*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(vuint32*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(vuint32*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(vuint32*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(vuint32*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(vuint32*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(vuint32*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(vuint32*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(vuint32*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(vuint32*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(vuint32*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(vuint32*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(vuint32*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(vuint32*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(vuint32*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(vuint32*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(vuint32*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(vuint32*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(vuint32*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(vuint32*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(vuint32*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(vuint32*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(vuint32*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(vuint32*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(vuint32*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(vuint32*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(vuint32*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(vuint32*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/BaS_codewarrior/firebeeV1/headers/MCF5475_XLB.h b/BaS_codewarrior/firebeeV1/headers/MCF5475_XLB.h new file mode 100644 index 0000000..f13a20c --- /dev/null +++ b/BaS_codewarrior/firebeeV1/headers/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(vuint32*)(&__MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(vuint32*)(&__MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(vuint32*)(&__MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(vuint32*)(&__MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(vuint32*)(&__MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(vuint32*)(&__MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(vuint32*)(&__MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(vuint32*)(&__MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(vuint32*)(&__MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(vuint32*)(&__MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(vuint32*)(&__MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/BaS_codewarrior/firebeeV1/lcf/DDRAM.lcf b/BaS_codewarrior/firebeeV1/lcf/DDRAM.lcf new file mode 100644 index 0000000..795732d --- /dev/null +++ b/BaS_codewarrior/firebeeV1/lcf/DDRAM.lcf @@ -0,0 +1,88 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + code (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0 +} + +SECTIONS { + +#BaS Basis adresse + ___Bas_base = 0x1FE00000; + +# Board Memory map definitions from linker command files: +# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE +# linker symbols must be defined in the linker command file. + +#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) + ___BOOT_FLASH = 0xE0000000; + ___BOOT_FLASH_SIZE = 0x00800000; +#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + +#VIDEO RAM BASIS + ___VRAM = 0x60000000; + +# MCF5475 Derivative Memory map definitions from linker command files: +# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE +# linker symbols must be defined in the linker command file. + +# Memory mapped registers + ___MBAR = 0xFF000000; + ___MMUBAR = 0xFF040000; +# 4KB on-chip Core SRAM0: -> exception table and exception stack + ___RAMBAR0 = 0xFF100000; + ___RAMBAR0_SIZE = 0x00001000; + + ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + +# 4KB on-chip Core SRAM1: -> modified code + ___RAMBAR1 = 0xFF101000; + ___RAMBAR1_SIZE = 0x00001000; + +# Systemveriablem:****************************************** +# RAMBAR0 0 bis 0x7FF -> exception vectoren +_rt_mod = ___RAMBAR0 + 0x800; +_rt_ssp = ___RAMBAR0 + 0x804; +_rt_usp = ___RAMBAR0 + 0x808; +_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 +_rt_cacr = ___RAMBAR0 + 0x810; # 002 +_rt_asid = ___RAMBAR0 + 0x814; # 003 +_rt_acr0 = ___RAMBAR0 + 0x818; # 004 +_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 +_rt_acr2 = ___RAMBAR0 + 0x820; # 006 +_rt_acr3 = ___RAMBAR0 + 0x824; # 007 +_rt_mmubar = ___RAMBAR0 + 0x828; # 008 +_rt_sr = ___RAMBAR0 + 0x82c; +_d0_save = ___RAMBAR0 + 0x830; +_a7_save = ___RAMBAR0 + 0x834; +_video_tlb = ___RAMBAR0 + 0x838; +_video_sbt = ___RAMBAR0 + 0x83C; +_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f +#*********************************************************** + +# 32KB on-chip System SRAM + ___SYS_SRAM = 0xFF010000; + ___SYS_SRAM_SIZE = 0x00008000; + + + .text : + { + startcf.c(.text) + sysinit.c(.text) + BaS.c(.text) + sd_card.c(.text) + mmu.s(.text) + exceptions.s(.text) + supervisor.s(.text) + ewf.s(.text) + illegal_instruction.s(.text) + last.c(.text) + . = ALIGN (0x4); + } > code + +} \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/lcf/FLASH.lcf b/BaS_codewarrior/firebeeV1/lcf/FLASH.lcf new file mode 100644 index 0000000..0315e2f --- /dev/null +++ b/BaS_codewarrior/firebeeV1/lcf/FLASH.lcf @@ -0,0 +1,88 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 +} + +SECTIONS { + +#BaS Basis adresse + ___Bas_base = 0x1FE00000; + +# Board Memory map definitions from linker command files: +# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE +# linker symbols must be defined in the linker command file. + +#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) + ___BOOT_FLASH = 0xE0000000; + ___BOOT_FLASH_SIZE = 0x00800000; +#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + +#VIDEO RAM BASIS + ___VRAM = 0x60000000; + +# MCF5475 Derivative Memory map definitions from linker command files: +# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE +# linker symbols must be defined in the linker command file. + +# Memory mapped registers + ___MBAR = 0xFF000000; + ___MMUBAR = 0xFF040000; +# 4KB on-chip Core SRAM0: -> exception table and exception stack + ___RAMBAR0 = 0xFF100000; + ___RAMBAR0_SIZE = 0x00001000; + + ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + +# 4KB on-chip Core SRAM1: -> modified code + ___RAMBAR1 = 0xFF101000; + ___RAMBAR1_SIZE = 0x00001000; + +# Systemveriablem:****************************************** +# RAMBAR0 0 bis 0x7FF -> exception vectoren +_rt_mod = ___RAMBAR0 + 0x800; +_rt_ssp = ___RAMBAR0 + 0x804; +_rt_usp = ___RAMBAR0 + 0x808; +_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 +_rt_cacr = ___RAMBAR0 + 0x810; # 002 +_rt_asid = ___RAMBAR0 + 0x814; # 003 +_rt_acr0 = ___RAMBAR0 + 0x818; # 004 +_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 +_rt_acr2 = ___RAMBAR0 + 0x820; # 006 +_rt_acr3 = ___RAMBAR0 + 0x824; # 007 +_rt_mmubar = ___RAMBAR0 + 0x828; # 008 +_rt_sr = ___RAMBAR0 + 0x82c; +_d0_save = ___RAMBAR0 + 0x830; +_a7_save = ___RAMBAR0 + 0x834; +_video_tlb = ___RAMBAR0 + 0x838; +_video_sbt = ___RAMBAR0 + 0x83C; +_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f +#*********************************************************** + +# 32KB on-chip System SRAM + ___SYS_SRAM = 0xFF010000; + ___SYS_SRAM_SIZE = 0x00008000; + + .code : {} > code + + .text : + { + startcf.c(.text) + sysinit.c(.text) + BaS.c(.text) + sd_card.c(.text) + mmu.s(.text) + exceptions.s(.text) + supervisor.s(.text) + ewf.s(.text) + illegal_instruction.s(.text) + last.c(.text) + } >> code + +} \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/BaS.c b/BaS_codewarrior/firebeeV1/sources/BaS.c new file mode 100644 index 0000000..2b2699d --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/BaS.c @@ -0,0 +1,287 @@ +/* + * BaS + * + */ + + +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +extern int mmu_init(); +extern int mmutr_miss(); +extern int vec_init(); +extern int illegal_table_make(); +extern int cf68k_initialize(); + +/********************************************************************/ + /* warte_routinen /* +********************************************************************/ + +void warte_10ms(void) +{ + asm + { +warte_10ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320000,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void warte_1ms(void) +{ + asm + { +warte_1ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #132000,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void warte_100us(void) +{ + asm + { + warte_100us: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #13200,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void warte_50us(void) +{ + asm + { +warte_50us: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #6600,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} +void warte_10us(void) +{ + asm + { +warte_10us: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void warte_1us(void) +{ + asm + { +warte_1us: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #132,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +/********************************************************************/ +void BaS(void) +{ + int az_sectors; + int sd_status,i; + + az_sectors = sd_card_init(); + + if(az_sectors>0) + { + sd_card_idle(); + } + + asm +{ + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + beq firetos_kopieren + lea MCF_PSC0_PSCTB_8BIT,a6 + lea MCF_PSC3_PSCTB_8BIT,a3 + lea MCF_PSC3_PSCRB_8BIT,a4 + lea MCF_PSC3_PSCRFCNT,a5 + move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT + bsr warte_10ms + move.l #'PIC ',(a6) + move.b (a4),d0 + move.b d0,(a6) + move.b (a4),d1 + move.b d1,(a6) + move.b (a4),d2 + move.b d2,(a6) + move.l #0x0a0d,(a6) + move.b #0x01,(a3) // RTC DATEN ANFORDERN +// TOS kopieren + lea 0x00e00000,a0 + lea 0xe0600000,a1 // default tos + lea 0xe0700000,a2 // 1MB + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + bne cptos_loop +firetos_kopieren: + lea 0x00e00000,a0 + lea 0xe0400000,a1 + lea 0xe0500000,a2 // 1MB +cptos_loop: + move.l (a1)+,(a0)+ + cmp.l a2,a1 + blt cptos_loop +/***************************************************************/ +/* div inits +/***************************************************************/ +div_inits: + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + beq video_setup +// rtc daten, mmu set, etc nur wenn switch 6 = off + lea 0xffff8961,a0 + clr.l d1 + moveq #64,d2 + move.b (a4),d0 + cmp.b #0x81,d0 + bne not_rtc +loop_sr: + move.b (a4),d0 + move.b d1,(a0) + move.b d0,2(a0) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr + + move.b #63,(a0) + move.b 2(a0),d0 + add #1,d0 + move.b d0,2(a0) +not_rtc: + bsr mmu_init + bsr vec_init + bsr illegal_table_make + +// interrupts + clr.l 0xf0010004 // disable all interrupts + lea MCF_EPORT_EPPAR,a0 + move.w #0xaaa8,(a0) // falling edge all, + +// timer 0 on mit int -> video change ------------------------------------------- + move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge + move.l d0,MCF_GPT0_GMS + moveq.l #0x3f,d0 // max prority interrutp + move.b d0,MCF_INTC_ICR62 // setzen +// ------------------------------------------------- + move.b #0xfe,d0 + move.b d0,0xf0010004 // enable int 1-7 + nop + lea MCF_EPORT_EPIER,a0 + move.b #0xfe,(a0) // int 1-7 on + nop + lea MCF_EPORT_EPFR,a0 + move.b #0xff,(a0) // alle pending interrupts löschen + nop + lea MCF_INTC_IMRL,a0 + move.l #0xFFFFFF00,(a0) // int 1-7 on + lea MCF_INTC_IMRH,a0 + move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on + + move.l #MCF_MMU_MMUCR_EN,d0 + move.l d0,MCF_MMU_MMUCR // mmu on + nop + nop +/********************************************************************/ +/* IDE reset +/********************************************************************/ + lea 0xffff8802,a0 + move.b #14,-2(a0) + move.b #0x80,(a0) + bsr warte_1ms + clr.b (a0) +/********************************************************************/ +/* video setup +/********************************************************************/ +video_setup: + lea 0xf0000410,a0 +// 25MHz + move.l #0x032002ba,(a0)+ // horizontal 640x480 + move.l #0x020c020a,(a0)+ // vertikal 640x480 + move.l #0x0190015d,(a0)+ // horizontal 320x240 + move.l #0x020C020A,(a0)+ // vertikal 320x240 */ +/* +// 32MHz + move.l #0x037002ba,(a0)+ // horizontal 640x480 + move.l #0x020d020a,(a0)+ // vertikal 640x480 + move.l #0x02A001e0,(a0)+ // horizontal 320x240 + move.l #0x05a00160,(a0)+ // vertikal 320x240 +*/ + lea -0x20(a0),a0 + move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on, +/********************************************************************/ +/* memory setup +/********************************************************************/ + lea 0x400,a0 + lea 0x800,a1 +mem_clr_loop: + clr.l (a0)+ + clr.l (a0)+ + clr.l (a0)+ + clr.l (a0)+ + cmp.l a0,a1 + bgt mem_clr_loop + + moveq #0x48,d0 + move.b d0,0xffff8007 +// stram + move.l #0xe00000,d0 // ende stram + move.l d0,0x42e + move.l #0x752019f3,d0 // memvalid + move.l d0,0x420 + move.l #0x237698aa,d0 // memval2 + move.l d0,0x43a + move.l #0x5555aaaa,d0 // memval3 + move.l d0,0x51a +// ttram + move.l #__Bas_base,d0 // ende ttram + move.l d0,0x5a4 + move.l #0x1357bd13,d0 // ramvalid + move.l d0,0x5a8 + +// test auf protect mode --------------------- + move.b DIP_SWITCH,d0 + btst #7,d0 + beq no_protect // nein-> + move.w #0x0700,sr +no_protect: + jmp 0xe00030 + +} +} diff --git a/BaS_codewarrior/firebeeV1/sources/div.s b/BaS_codewarrior/firebeeV1/sources/div.s new file mode 100644 index 0000000..f5f151c --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/div.s @@ -0,0 +1,1326 @@ + +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +sd_test: + lea 0x40000,a5 // basis addresse + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit 4MHz + move.l #0x38551120,d0 + move.l d0,dspi_dtar0(a0) // + move.l #0x08200000,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + move.b #0xc0,(a0) // 8 bit 4MHz + bsr warte_1ms + move.b #0x80,(a0) // 8 bit 4MHz +// sd idle + moveq.l #100,d6 // 100 versuche +sd_idle: + bsr sd_16clk + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x01,d5 + beq wait_of_aktiv + subq.l #1,d6 + beq sd_not + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + + +wait_of_aktiv2: + bsr sd_16clk + move.b #0x69,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + move.b #0x50,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + move.l a5,a4 // adresse setzen + bsr sd_rcv_block + +// write block +sd_wb: + bsr sd_16clk + move.b #0x58,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_wb + + bsr sd_send_block + +// read block 2 +sd_rb2: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + bsr sd_rcv_block + clr.l d0 + halt + halt + rts +// status holen ------------------------------- +sd_not: + moveq.l #-1,d0 + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_block: + move.l #512,d3 // 512 byts + 2 ccr byts + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb +// crc holen + bsr sd_com // crc 1.byt + move.b d5,d1 + bsr sd_com // crc 2.byt + move.b d5,d2 + rts + +// daten schreiben ----------------------- +sd_send_block: + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b #0xc7,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b d1,d4 + bsr sd_com // crc 1.byt + move.b d2,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + cmp.b #0x05,d5 + bne sd_send_wr_ww +sd_sendwait_wr_f: + bsr sd_com + cmp.b #0xff,d5 + bne sd_sendwait_wr_f + rts +// clock einfügen ------------------------------------- +sd_16clk: + move.b #0xc0,(a0) // 8 bit 4MHz + nop + move.b #0x80,(a0) // 8 bit 4MHz + rts +// cdm 58 +read_ocr: + bsr sd_16clk + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + + halt + + move.l #'Ver1',d6 + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_csd + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com +/******************************************/ +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/********************************************************************/ +// sd card +/********************************************************************/ +sd_test: + lea 0x40000,a5 // basis addresse + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + move.l a5,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + move.l #513,d7 + moveq.l #0xbb,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0xbb,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + +halt +halt + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) // nCS=0 +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + bclr.b #0,(a1) // default 0 bit senden + btst d2,d4 // ist 0? + beq sd_com2 // ja-> + bset.b #0,(a1) // sonst auf 1 +sd_com2: + bsr sd_clk // clocken + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) // nCS=1 + bset.b #0,(a1) // daten = 0 + bsr warten_200us + rts +// clocken +sd_clk: + tst.b 0xfffff700 // wait + tst.b 0xfffff700 + bset.b #2,(a1) // clock high + tst.b 0xfffff700 // wait + tst.b 0xfffff700 // wait + move.b (a2),d3 // bit holen + bclr.b #2,(a1) // clock low + rts + +sd_16clk: + move.l #160,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +/********************************************************************/ +// video pll +/********************************************************************/ + lea 0xf0000800,a1 + + lea 0xf0000600,a0 + move.l #128,d0 +clr_pll: + bsr wait_pll + clr.w (a0) + addq.l #4,a0 + subq.l #1,d0 + bne clr_pll + + lea 0xf0000600,a0 + bsr wait_pll + move.w #27,0x48(a0) // loopfilter r + bsr wait_pll + move.w #1,0x08(a0) // charge pump I + bsr wait_pll + move.w #12,0x0(a0) // N counter high = 12 + bsr wait_pll + move.w #12,0x40(a0) // N counter low = 12 + bsr wait_pll + move.w #1,0x114(a0) // ck1 bypass + bsr wait_pll + move.w #1,0x118(a0) // ck2 bypass + bsr wait_pll + move.w #1,0x11c(a0) // ck3 bypass + bsr wait_pll + move.w #1,0x10(a0) // ck0 high = 1 + bsr wait_pll + move.w #1,0x50(a0) // ck0 low = 1 + + bsr wait_pll + move.w #1,0x144(a0) // M odd division + bsr wait_pll + move.w #1,0x44(a0) // M low = 1 + + bsr wait_pll + move.w #99,0x04(a0) // M high = 100 + + bsr wait_pll + clr.b (a1) // set + +set_pll: + bsr read_pll + halt + move.w d0,(a0) + bsr wait_pll + clr.b (a1) + bra set_pll + +read_pll: + lea 0xf0000600,a3 + lea 0x10000,a2 + move.l #128,d3 +read1_pll: + bsr wait_pll + move.w (a3),d1 + bsr wait_pll + move.w (a3),(a2) + addq.l #4,a3 + addq.l #4,a2 + subq.l #1,d3 + bne read1_pll + rts +wait_pll: + tst.w (a1) + bmi wait_pll + rts + +/********************************************************************/ +void ide_test(void) +/********************************************************************/ +{ + asm + { + halt + lea 0xfff00000,a0 + lea 0x80000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rxl +// read sector normal + move.b #1,seccnt(a0) // 1 sector 0x200 + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rxl +// write pattern 0x400 + move.l a1,a4 //a4=400 + move.l #256,d0 + clr.l d1 +ide_test_loop3: + move.w d1,(a1)+ + addq.l #1,d1 + subq.l #1,d0 + bne ide_test_loop3 + move.l a4,a1 +// write testpattern sector 0x400 + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + move.l a1,a2 //a2=600 + move.l #256,d4 +loop_rw: +// read testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rxl +// verändere testpattern + move.l a2,a1 +// halt + move.l #256,d0 + move.l #0x100,d1 +verae_loop: + move.w (a1),d2 + add.l d1,d2 + move.w d2,(a1)+ + subq.l #1,d0 + bne verae_loop +// write testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + subq.l #1,d4 +// bra verae_loop + bne loop_rw +// sector vergleichen +// halt + move.l #128,d0 + moveq.l #-1,d1 +verg_loop: + move.l (a2)+,d2 + cmp.l (a4)+,d2 + bne error + subq.l #1,d0 + bne verg_loop + clr.l d1 +error: + halt + rts +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_txl + + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben long +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts + } +} +/********************************************************************/ diff --git a/BaS_codewarrior/firebeeV1/sources/ewf.s b/BaS_codewarrior/firebeeV1/sources/ewf.s new file mode 100644 index 0000000..7f5a644 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ewf.s @@ -0,0 +1,1565 @@ +/*************************************************************************************************/ +// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört +//------------------------------------------------------------------------------ + +.include "ii_macro.h" + +.global ewf +//----------------------------------------------------------- +.text +ewferr: + nop + halt + nop +//----------------------------------------------------------- +ewf: + mvz.b (a0)+,d1 // 1. byt ewf + mvs.w ewf_table-*-2(pc,d1*2),d1 + jmp ewf_table-*-2(pc,d1) +ewf_table: + .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table + .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table + .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table + .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table + .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table + .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table + .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table + .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table + .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table + .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table + .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table + .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table + .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table + .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table + .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table + .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table + .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table + .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table + .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table + .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table + .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table + .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table + .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table + .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table + .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table + .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table + .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table + .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table + .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table + .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table + .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table + .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table + .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table + .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table + .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table + .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table + .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table + .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table + .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table + .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table + .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table + .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table + .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table + .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table + .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table + .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table + .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table + .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table + .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table + .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table + .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table + .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table + .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table + .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table + .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table + .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table + .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table + .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table + .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table + .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table + .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table + .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table + .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table + .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table +//d0.w * 1 +ewf_00: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_01: + mvs.w d0_off+6(a7),d0 + bra ewf_full +//d0.w * 2 +ewf_02: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_03: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 4 +ewf_04: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_05: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 8 +ewf_06: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_07: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 1 +ewf_09: + move.l d0_off+4(a7),d0 + bra ewf_full +//d0.l * 2 +ewf_0b: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 4 +ewf_0d: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 8 +ewf_0f: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 1 +ewf_10: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_11: + mvs.w d1_off+6(a7),d0 + bra ewf_full +//d1.w * 2 +ewf_12: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_13: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 4 +ewf_14: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_15: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 8 +ewf_16: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_17: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 1 +ewf_19: + move.l d1_off+4(a7),d0 + bra ewf_full +//d1.l * 2 +ewf_1b: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 4 +ewf_1d: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 8 +ewf_1f: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 1 +ewf_20: + mvs.b (a0)+,d1 + mvs.w d2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_21: + mvs.w d2,d0 + bra ewf_full +//d2.w * 2 +ewf_22: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_23: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 4 +ewf_24: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_25: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 8 +ewf_26: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_27: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 1 +ewf_29: + move.l d2,d0 + bra ewf_full +//d2.l * 2 +ewf_2b: + move.l d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 4 +ewf_2d: + move.l d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 8 +ewf_2f: + move.l d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 1 +ewf_30: + mvs.b (a0)+,d1 + mvs.w d3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_31: + mvs.w d3,d0 + bra ewf_full +//d3.w * 2 +ewf_32: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_33: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 4 +ewf_34: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_35: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 8 +ewf_36: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_37: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 1 +ewf_39: + move.l d3,d0 + bra ewf_full +//d3.l * 3 +ewf_3b: + move.l d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 4 +ewf_3d: + move.l d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 8 +ewf_3f: + move.l d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 1 +ewf_40: + mvs.b (a0)+,d1 + mvs.w d4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_41: + mvs.w d4,d0 + bra ewf_full +//d4.w * 2 +ewf_42: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_43: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 4 +ewf_44: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_45: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 8 +ewf_46: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_47: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 1 +ewf_49: + move.l d4,d0 + bra ewf_full +//d4.l * 4 +ewf_4b: + move.l d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 4 +ewf_4d: + move.l d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 8 +ewf_4f: + move.l d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 1 +ewf_50: + mvs.b (a0)+,d1 + mvs.w d5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_51: + mvs.w d5,d0 + bra ewf_full +//d5.w * 2 +ewf_52: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_53: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 4 +ewf_54: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_55: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 8 +ewf_56: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_57: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 1 +ewf_59: + move.l d5,d0 + bra ewf_full +//d5.l * 5 +ewf_5b: + move.l d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 4 +ewf_5d: + move.l d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 8 +ewf_5f: + move.l d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 1 +ewf_60: + mvs.b (a0)+,d1 + mvs.w d6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_61: + mvs.w d6,d0 + bra ewf_full +//d6.w * 2 +ewf_62: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_63: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 4 +ewf_64: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_65: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 8 +ewf_66: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_67: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 1 +ewf_69: + move.l d6,d0 + bra ewf_full +//d6.l * 6 +ewf_6b: + move.l d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 4 +ewf_6d: + move.l d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 8 +ewf_6f: + move.l d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 1 +ewf_70: + mvs.b (a0)+,d1 + mvs.w d7,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_71: + mvs.w d7,d0 + bra ewf_full +//d7.w * 2 +ewf_72: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_73: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 4 +ewf_74: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_75: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 8 +ewf_76: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_77: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 1 +ewf_79: + move.l d7,d0 + bra ewf_full +//d7.l * 7 +ewf_7b: + move.l d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 4 +ewf_7d: + move.l d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 8 +ewf_7f: + move.l d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 1 +ewf_80: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_81: + mvs.w a0_off+6(a7),d0 + bra ewf_full +//a0.w * 2 +ewf_82: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_83: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 4 +ewf_84: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_85: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 8 +ewf_86: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_87: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 1 +ewf_89: + move.l a0_off+4(a7),d0 + bra ewf_full +//a0.l * 2 +ewf_8b: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 4 +ewf_8d: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 8 +ewf_8f: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 1 +ewf_90: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_91: + mvs.w a1_off+6(a7),d0 + bra ewf_full +//a1.w * 2 +ewf_92: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_93: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 4 +ewf_94: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_95: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 8 +ewf_96: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_97: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 1 +ewf_99: + move.l a1_off+4(a7),d0 + bra ewf_full +//a1.l * 2 +ewf_9b: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 4 +ewf_9d: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 8 +ewf_9f: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 1 +ewf_a0: + mvs.b (a0)+,d1 + mvs.w a2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_a1: + mvs.w a2,d0 + bra ewf_full +//a2.w * 2 +ewf_a2: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_a3: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 4 +ewf_a4: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a5: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 8 +ewf_a6: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a7: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 1 +ewf_a9: + move.l a2,d0 + bra ewf_full +//a2.l * 2 +ewf_ab: + move.l a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 4 +ewf_ad: + move.l a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 8 +ewf_af: + move.l a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 1 +ewf_b0: + mvs.b (a0)+,d1 + mvs.w a3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_b1: + mvs.w a3,d0 + bra ewf_full +//a3.w * 2 +ewf_b2: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_b3: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 4 +ewf_b4: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b5: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 8 +ewf_b6: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b7: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 1 +ewf_b9: + move.l a3,d0 + bra ewf_full +//a3.l * 3 +ewf_bb: + move.l a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 4 +ewf_bd: + move.l a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 8 +ewf_bf: + move.l a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 1 +ewf_c0: + mvs.b (a0)+,d1 + mvs.w a4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_c1: + mvs.w a4,d0 + bra ewf_full +//a4.w * 2 +ewf_c2: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_c3: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 4 +ewf_c4: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c5: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 8 +ewf_c6: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c7: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 1 +ewf_c9: + move.l a4,d0 + bra ewf_full +//a4.l * 4 +ewf_cb: + move.l a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 4 +ewf_cd: + move.l a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 8 +ewf_cf: + move.l a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 1 +ewf_d0: + mvs.b (a0)+,d1 + mvs.w a5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_d1: + mvs.w a5,d0 + bra ewf_full +//a5.w * 2 +ewf_d2: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_d3: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 4 +ewf_d4: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d5: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 8 +ewf_d6: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d7: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 1 +ewf_d9: + move.l a5,d0 + bra ewf_full +//a5.l * 5 +ewf_db: + move.l a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 4 +ewf_dd: + move.l a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 8 +ewf_df: + move.l a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 1 +ewf_e0: + mvs.b (a0)+,d1 + mvs.w a6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_e1: + mvs.w a6,d0 + bra ewf_full +//a6.w * 2 +ewf_e2: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_e3: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 4 +ewf_e4: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e5: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 8 +ewf_e6: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e7: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 1 +ewf_e9: + move.l a6,d0 + bra ewf_full +//a6.l * 6 +ewf_eb: + move.l a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 4 +ewf_ed: + move.l a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 8 +ewf_ef: + move.l a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 1 +ewf_f0: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + add.l d1,a1 + rts +ewf_f1: + move.l a1,-(a7) + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + bra ewf_full +//usp.w * 2 +ewf_f2: + mvs.b (a0)+,d1 + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_f3: + move.l usp,a1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 4 +ewf_f4: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f5: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 8 +ewf_f6: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f7: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 1 +ewf_f9: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + bra ewf_full +//usp.l * 7 +ewf_fb: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 4 +ewf_fd: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 8 +ewf_ff: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//----------------------------------------------------------------------------------- +// extension full format rest von ewf +//-------------------------------------------------------------------- +ewf_full: + mvz.b (a0)+,d1 + mvs.w ewff_table-*-2(pc,d1*2),d1 + jmp ewff_table-*-2(pc,d1) +ewff_table: + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 + .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 + .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table +ewff_end: + rts +ewff_bsw: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_bsl: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_i0v: + add.l d0,a1 + move.l (a1),a1 + rts +ewff_iwv: + add.l d0,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_ilv: + add.l d0,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_i0n: + move.l (a1),a1 + add.l d0,a1 + rts +ewff_iwn: + move.l (a1),a1 + add.l d0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_iln: + move.l (a1),a1 + add.l d0,a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_mi0: + add.l d0,a1 + rts +ewff_miw: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_mil: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wi0: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_wiw: + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wil: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_li0: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_liw: + move.l (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_lil: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_w0v: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_wwv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_wlv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_l0v: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_lwv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_llv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_w0n: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_wwn: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_wln: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_l0n: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_lwn: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_lln: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +/**************************************************************************************************************** + diff --git a/BaS_codewarrior/firebeeV1/sources/exceptions.s b/BaS_codewarrior/firebeeV1/sources/exceptions.s new file mode 100644 index 0000000..9f23af4 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/exceptions.s @@ -0,0 +1,799 @@ +/********************************************************/ +/* exception vectoren intialisieren +/********************************************************/ + +.include "startcf.h" + +.extern ___Bas_base +.extern ___SUP_SP +.extern ___BOOT_FLASH +.extern ___RAMBAR0 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _illegal_instruction +.extern _privileg_violation +.extern _mmutr_miss +.extern ___MBAR +.extern ___MMUBAR +.extern _video_tlb +.extern _video_sbt +.extern cpusha + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +#define MCF_EPORT_EPPAR ___MBAR+0xF00 +#define MCF_EPORT_EPDDR ___MBAR+0xF04 +#define MCF_EPORT_EPIER ___MBAR+0xF05 +#define MCF_EPORT_EPDR ___MBAR+0xF08 +#define MCF_EPORT_EPPDR ___MBAR+0xF09 +#define MCF_EPORT_EPFR ___MBAR+0xF0C + +#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 + +#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C + +#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C + +.public _vec_init + +//mmu --------------------------------------------------- +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +//--------------------------------------------------- +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS ___MBAR+0x800 + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +#define MCF_SLT0_SCNT ___MBAR+0x908 + +/**********************************************************/ +// macros +/**********************************************************/ +irq: .macro vector,int_mask,clr_int + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #clr_int,(a5) // clear int pending +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne @irq_protect // ja-> +// ------------------------------------------- + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.l vector,-(a7) + move #0x2\200,sr + rts +@irq_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne @sev_supint // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben +#endif + bra @irq_end +@sev_supint: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif +@irq_end: + move.l a5,usp // usp setzen + lea vector,a5 + adda.l _rt_vbr,a5 + move.l (a5),12(a7) // vectoradresse eintragen + move.b #int_mask,10(a7) // intmaske setzen + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg + .endm +/*********************************************************/ +.text +_vec_init: + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #___RAMBAR0,d0 // sind in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // mal standard vector für alle setzen + subq.l #1,d0 + bne init_vec_loop + + move.l #___SUP_SP,(a0) + lea reset_vector(pc),a1 + move.l a1,0x04(a0) + lea acess(pc),a1 + move.l a1,0x08(a0) + + move.b DIP_SWITCHa,d0 // ++ vr + btst #7,d0 + beq no_protect_vectors + + lea _illegal_instruction(pc),a1 + move.l a1,0x0c(a0) + lea _illegal_instruction(pc),a1 + move.l a1,0x10(a0) + lea zero_divide(pc),a1 + move.l a1,0x14(a0) + lea _privileg_violation(pc),a1 + move.l a1,0x20(a0) + lea linea(pc),a1 + move.l a1,0x28(a0) + lea linef(pc),a1 + move.l a1,0x2c(a0) + lea format(pc),a1 + move.l a1,0x38(a0) + + // floating point overflow + lea flpoow(pc),a1 + move.l a1,0xc0(a0) + lea flpoow(pc),a1 + move.l a1,0xc4(a0) + lea flpoow(pc),a1 + move.l a1,0xc8(a0) + lea flpoow(pc),a1 + move.l a1,0xcc(a0) + lea flpoow(pc),a1 + move.l a1,0xd0(a0) + lea flpoow(pc),a1 + move.l a1,0xd4(a0) + lea flpoow(pc),a1 + move.l a1,0xd8(a0) + lea flpoow(pc),a1 + move.l a1,0xdc(a0) +no_protect_vectors: + + +// int 1-7 + lea irq1(pc),a1 + move.l a1,0x104(a0) + lea irq2(pc),a1 + move.l a1,0x108(a0) + lea irq3(pc),a1 + move.l a1,0x10c(a0) + lea irq4(pc),a1 + move.l a1,0x110(a0) + lea irq5(pc),a1 + move.l a1,0x114(a0) + lea irq6(pc),a1 + move.l a1,0x118(a0) + lea irq7(pc),a1 + move.l a1,0x11c(a0) +//psc_vectors + lea psc3(pc),a1 + move.l a1,0x180(a0) +//timer 1 vectors + lea timer0(pc),a1 + move.l a1,0x1f8(a0) + rts +/********************************************************/ +/* exception vector routinen +/********************************************************/ +vector_table_start: +std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern +// test auf protect mode ------------------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne stv_protect // ja-> +//------------------------------------------------------ + move.w 8(a7),d0 // vector holen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),d0 + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) + move.w 10(a7),d0 + bset #13,d0 // super + move.w d0,sr // orginal sr wert in super setzen + move.l (a7)+,d0 // d0 zurück + rts +stv_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +sev_sup: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + bset #13,d0 // war aus rt super + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren + bset #5,(a5) // war aus super +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +//******************************************* +reset_vector: + move.w #0x2700,sr // disable interrupt + move.l #0x31415926,d0 + cmp.l 0x426,d0 // reset vector gültg? + beq std_exc_vec // ja-> + jmp ___BOOT_FLASH // sonst kaltstart +acess: + move.w #0x2700,sr // disable interrupt + move.l d0,-(sp) // ++ vr + move.w 4(sp),d0 + andi.l #0x0c03,d0 + cmpi.l #0x0401,d0 + beq access_mmu + cmpi.l #0x0402,d0 + beq access_mmu + cmpi.l #0x0802,d0 + beq access_mmu + cmpi.l #0x0c02,d0 + beq access_mmu + bra bus_error +access_mmu: + move.l MCF_MMU_MMUSR,d0 + btst #1,d0 + bne bus_error + move.l MCF_MMU_MMUAR,d0 + cmp.l #___Bas_base,d0 // max User RAM Bereich + bge bus_error // grösser -> bus error + bra _mmutr_miss +bus_error: + move.l (sp)+,d0 + bra std_exc_vec + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(a7) + move.l d0,-(a7) + move.l 12(a7),a0 // pc + move.w (a0)+,d0 // befehlscode + btst #7,d0 // long? + beq zd_word // nein-> + addq.l #2,a0 +zd_word: + and.l 0x3f,d0 // ea ausmaskieren + cmp.w #0x08,d0 // -(ax) oder weniger + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // nein-> + btst #7,d0 // long? + beq zd_end // nein + addq.l #2,a0 +zd_end: + move.l a0,12(a7) + move.l (a7)+,d0 + move.l (a7)+,a0 + rte + +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +irq1: + irq 0x64,1,0x02 +irq2: //vsync + // move.b #3,2(a7) + // rte + irq 0x68,2,0x04 +irq3: + irq 0x6c,3,0x08 +irq4: // vsync + irq 0x70,4,0x10 +irq5: // acp + irq 0x74,5,0x20 +irq6: // mfp + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #0x40,(a5) // clear int6 +// test auf timeout screen adr change ------------------------------------------------------- + move.l _video_sbt,d0 + beq irq6_non_sca // wenn 0 nichts zu tun + sub.l #0x70000000,d0 // 14 sec abzählen + lea MCF_SLT0_SCNT,a5 + cmp.l (a5),d0 // aktuelle zeit weg + ble irq6_non_sca // noch nicht abgelaufen + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) // register sichern + clr.l d3 // beginn mit 0 + bsr cpusha // cache leeren + // eintrag suchen + irq6_next_sca: + move.l d3,d0 + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + mvz.w #0x10e,d4 + move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu + nop + move.l MCF_MMU_MMUTR,d4 // ID holen + lsr.l #2,d4 // bit 9 bis 2 + cmp.w #sca_page_ID,d4 // ist screen change ID? + bne irq6_sca_pn // nein -> page keine screen area next +// eintrag ändern + add.l #std_mmutr,d0 + move.l d3,d1 // page 0? + beq irq6_sca_pn0 // ja -> + add.l #cb_mmudr,d1 // sonst page cb + bra irq6_sca_pn1c +irq6_sca_pn0: + add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked +irq6_sca_pn1c: + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setze tlb data only + nop +// page copy + move.l d3,a0 + add.l #0x60000000,a0 + move.l d3,a1 + move.l #0x10000,d4 // die ganze page +irq6_vcd0_loop: + move.l (a0)+,(a1)+ // page copy + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne irq6_vcd0_loop + nop +irq6_sca_pn: + add.l #0x00100000,d3 // next + cmp.l #0x00d00000,d3 // ende? + blt irq6_next_sca // nein-> + + move.l #0x2000,d0 + move.l d0,_video_tlb // anfangszustand wieder herstellen + clr.l _video_sbt // zeit löschen + + movem.l (a7),d0-d4/a0-a1 // register zurück + lea 28(a7),a7 +irq6_non_sca: +// test auf acsi dma ----------------------------------------------------------------- + lea 0xfffffa0b,a5 + bset #7,-4(a5) // int ena + btst.b #7,(a5) // acsi dma int? + beq non_acsi_dma + bsr acsi_dma +non_acsi_dma: +// ---------------------------------------------------------------------------------- + tst.b (a5) + bne irq6_1 + tst.b 2(a5) + bne irq6_1 + movem.l (a7),d0/a5 + addq.l #8,a7 + rte +irq6_1: + lea MCF_GPIO_PODR_FEC1L,a5 + bclr.b #4,(a5) // led on + lea blinker(pc),a5 + addq.l #1,(a5) // +1 + move.l (a5),d0 + and.l #0x80,d0 + bne irq6_2 + lea MCF_GPIO_PODR_FEC1L,a5 + bset.b #4,(a5) // led off +irq6_2: +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq6_3 // ja-> +// ------------------------------------------- + move.l 0xF0020000,a5 // vector holen + add.l _rt_vbr,a5 // basis + move.l (a5),d0 // vector holen + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) // vector eintragen + move.l (a7)+,d0 // d0 zurück + move #0x2600,sr + rts +irq6_3: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup6 // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr transferieren +#else + move.w 8(a7),-(a5) // vector transferieren + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.b #6,2(a7) // intmaske setzen + rte // und weg +sev_sup6: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + rts +blinker:.long 0 +/**************************************************/ +/* pseudo dma */ +/**************************************************/ +acsi_dma: // atari dma + move.l a1,-(a7) + move.l d1,-(a7) + + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + move.l #'DMA ',(a1) + move.l #'INT!',(a1) + + lea 0xf0020110,a5 // fifo daten +acsi_dma_start: + move.l -12(a5),a1 // dma adresse + move.l -8(a5),d0 // byt counter + ble acsi_dma_end + btst.b #0,-16(a5) // write? (dma modus reg) + bne acsi_dma_wl // ja-> +acsi_dma_rl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_rl + bra acsi_dma_fertig +acsi_dma_wl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_wl +acsi_dma_fertig: + move.l a1,-12(a5) // adresse zurück + move.l d0,-8(a5) // byt counter zurück +acsi_dma_end: + tst.b -4(a5) // dma req? + bmi acsi_dma_start // ja-> + lea 0xfffffa0b,a5 + bclr.b #7,4(a5) // clear int in service mfp + bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b + + move.w #0x0d0a,d1 + move.w d1,MCF_PSC0_PSCTB_8BIT + + move.l (a7)+,d1 + move.l (a7)+,a1 + rts +/**************************************************/ +/* irq 7 = pseudo bus error */ +/**************************************************/ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l ___RAMBAR0+0x008,a0 // Real Access Error handler + move.l a0,8(sp) // This will be the return address for rts + + move.w 12(sp),d0 // Format/Vector word + andi.l #0xf000,d0 // Keep only the Format + ori.l #2*4,d0 // Simulate Vector #2, no Fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + move.b #0x80,(a0) // clear int7 + move.l (sp)+,d0 + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +/**************************************************/ +/* psc3 com PIC MCF */ +/**************************************************/ +psc3: + move.w #0x2700,sr // disable interrupt + lea -20(a7),a7 + movem.l d0-d2/a0/a3,(a7) + lea MCF_PSC3_PSCRB_8BIT,a3 + move.b (a3),d1 + cmp.b #2,d1 // anforderung rtc daten? + bne psc3_fertig + + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + move.l #'PIC ',(a0) + move.l #'INT ',(a0) + move.l #'RTC!',(a0) + move.l #0x0d0a,(a0) + + lea 0xffff8961,a0 + lea MCF_PSC3_PSCTB_8BIT,a3 + clr.l d1 + moveq #64,d2 + move.b #0x82,(a3) // header: rtcd mcf->pic +loop_sr2: + move.b d1,(a0) + move.b 2(a0),d0 + move.b d0,(a3) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr2 +psc3_fertig: + movem.l (a7),d0-d2/a0/a3 // register zurück + lea 20(a7),a7 + RTE +/**************************************************/ +/* timer 0: video change later also others +/**************************************************/ +timer0: + move #0x2700,sr +// halt + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) + mvz.b 0xffff8201,d0 // löschen und high byt + cmp.w #2,d0 + blt video_chg_end + cmp.w #0xd0,d0 // normale addresse + blt sca_other // nein-> + lea MCF_SLT0_SCNT,a0 + move.l (a0),d4 + move.l d4,_video_sbt // time sichern +sca_other: + lsl.l #8,d0 + move.b 0xffff8203,d0 // mid byt + lsl.l #8,d0 + move.b 0xffff820d,d0 // low byt + move.l d0,d3 +video_chg_1page: +// test ob page schon gesetzt + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + bne video_chg_2page // schon gesetzt gewesen? ja->weg + move.l d4,_video_tlb + bsr cpusha // cache leeren +// daten copieren +video_copy_data: + move.l d4,_video_tlb + and.l #0x00f00000,d0 + move.l d0,a0 + move.l a0,a1 + add.l #0x60000000,a1 + move.l #0x10000,d4 // die ganze page +video_copy_data_loop: + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne video_copy_data_loop +// eintrag suchen + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + move.l d0,d1 + add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data + nop +video_chg_2page: +// test ob evt. anschliessende page gesetzt werden muss + move.l d3,d0 + mvz.w 0xffff8210,d4 // byts pro zeile + mvz.w 0xffff82aa,d2 // zeilen ende + mvz.w 0xffff82a8,d1 // zeilenstart + sub.l d1,d2 // differenz = anzahl zeilen + mulu d2,d4 // maximal 480 zeilen + add.l d4,d0 // video grösse + cmp.l #0xe00000,d0 // maximale addresse + bge video_chg_end // wenn gleich oder grösser -> fertig + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + beq video_copy_data // nein nochmal +video_chg_end: +// int pending löschen + lea MCF_GPT0_GMS,a0 + bclr.b #0,3(a0) + nop + bset.b #0,3(a0) + + movem.l (a7),d0-d4/a0-a1 + lea 28(a7),a7 +//-------------------------------------------------------------------------------------------------------- + RTE + diff --git a/BaS_codewarrior/firebeeV1/sources/ii_add.h b/BaS_codewarrior/firebeeV1/sources/ii_add.h new file mode 100644 index 0000000..bc23f63 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_add.h @@ -0,0 +1,581 @@ +//-------------------------------------------------------------------- +// add +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// add.b #im,dx +//-------------------------------------------------------------------- +addbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + add.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx +//-------------------------------------------------------------------- +adddd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddd:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +adddda:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddai:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(ay),dx +//-------------------------------------------------------------------- +addd16ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(ay,dy),dx +//-------------------------------------------------------------------- +addd8ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.w,dx +//-------------------------------------------------------------------- +addxwd:.macro +#ifdef halten_add + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.l,dx +//-------------------------------------------------------------------- +addxld:.macro +#ifdef halten_add + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(pc),dx +//-------------------------------------------------------------------- +addd16pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(pc,dy),dx +//-------------------------------------------------------------------- +addd8pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// add dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addeda:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addedai:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ +//-------------------------------------------------------------------- +addedaid:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedadd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,d16(ay) +//-------------------------------------------------------------------- +adde16ad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add.w d8(ay,dy),dx +//-------------------------------------------------------------------- +adde8ad:.macro +#ifdef halten_add + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.w +//-------------------------------------------------------------------- +addxwe:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.l +//-------------------------------------------------------------------- +addxle:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addaw:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + adda.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// add.w ea,usp +//-------------------------------------------------------------------- +addawa7:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + add.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawu:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + adda.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawua7:.macro + addawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(ay),ax +//-------------------------------------------------------------------- +addawd16a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +addawd8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.w,ax +//-------------------------------------------------------------------- +addawxwax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.l,ax +//-------------------------------------------------------------------- +addawxlax:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(pc),ax +//-------------------------------------------------------------------- +addawd16pcax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +addawd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w #im,ax +//-------------------------------------------------------------------- +addawim:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +addald8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +addakd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// addx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +adddx:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + addx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +adddax:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + addx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_codewarrior/firebeeV1/sources/ii_and.h b/BaS_codewarrior/firebeeV1/sources/ii_and.h new file mode 100644 index 0000000..f74afde --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_and.h @@ -0,0 +1,441 @@ +//-------------------------------------------------------------------- +// and +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// and.b #im,dx +//-------------------------------------------------------------------- +andbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + and.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea,dx +//-------------------------------------------------------------------- +anddd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +andddd:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and (ea)->dy,dx +//-------------------------------------------------------------------- +anddda:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +andddai:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,-(ay),dx +//-------------------------------------------------------------------- +andddad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(ay),dx +//-------------------------------------------------------------------- +andd16ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(ay,dy),dx +//-------------------------------------------------------------------- +andd8ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.w,dx +//-------------------------------------------------------------------- +andxwd:.macro +#ifdef halten_and + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.l,dx +//-------------------------------------------------------------------- +andxld:.macro +#ifdef halten_and + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(pc),dx +//-------------------------------------------------------------------- +andd16pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(pc,dy),dx +//-------------------------------------------------------------------- +andd8pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// and dx,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // and dx,(ea)->dy +//-------------------------------------------------------------------- +andeda:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedai:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedaid:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedadd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,d16(ay) +//-------------------------------------------------------------------- +ande16ad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ande8ad:.macro +#ifdef halten_and + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.w +//-------------------------------------------------------------------- +andxwe:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.l +//-------------------------------------------------------------------- +andxle:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // anda.w ea,ax +//-------------------------------------------------------------------- +andaw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// and.w ea,usp +//-------------------------------------------------------------------- +andawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,ax +//-------------------------------------------------------------------- +andawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,usp +//-------------------------------------------------------------------- +andawua7:.macro + andawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(ay),ax +//-------------------------------------------------------------------- +andawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +andawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.w,ax +//-------------------------------------------------------------------- +andawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.l,ax +//-------------------------------------------------------------------- +andawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(pc),ax +//-------------------------------------------------------------------- +andawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +andawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w #im,ax +//-------------------------------------------------------------------- +andawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +andald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +andald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +anddx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +anddax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_codewarrior/firebeeV1/sources/ii_dbcc.h b/BaS_codewarrior/firebeeV1/sources/ii_dbcc.h new file mode 100644 index 0000000..652cdbe --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_dbcc.h @@ -0,0 +1,117 @@ +//-------------------------------------------------------------------- +// dbcc,trapcc +//-------------------------------------------------------------------- +.text +ii_lset_dbcc:.macro +// dbra + ii_lset_opeau 51,c + ii_lset_opeau 52,c + ii_lset_opeau 53,c + ii_lset_opeau 54,c + ii_lset_opeau 55,c + ii_lset_opeau 56,c + ii_lset_opeau 57,c + ii_lset_opeau 58,c + ii_lset_opeau 59,c + ii_lset_opeau 5a,c + ii_lset_opeau 5b,c + ii_lset_opeau 5c,c + ii_lset_opeau 5d,c + ii_lset_opeau 5e,c + ii_lset_opeau 5f,c +.endm + +ii_dbcc_func:.macro +ii_0x51c8: + dbra_macro d0_off+2(a7) +ii_0x51c9: + dbra_macro d1_off+2(a7) +ii_0x51ca: + dbra_macro d2 +ii_0x51cb: + dbra_macro d3 +ii_0x51cc: + dbra_macro d4 +ii_0x51cd: + dbra_macro d5 +ii_0x51ce: + dbra_macro d6 +ii_0x51cf: + dbra_macro d7 +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- + ii_dbcc 2,hi + ii_dbcc 3,ls + ii_dbcc 4,cc + ii_dbcc 5,cs + ii_dbcc 6,ne + ii_dbcc 7,eq + ii_dbcc 8,vc + ii_dbcc 9,vs + ii_dbcc a,pl + ii_dbcc b,mi + ii_dbcc c,ge + ii_dbcc d,lt + ii_dbcc e,gt + ii_dbcc f,le +.endm +//--------------------------------------------------------------------------------------------- +// dbra dx +//--------------------------------------------------------------------------------------------- +dbra_macro:.macro +#ifdef halten_dbcc + halt +#endif + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbra\@ // bra if plus? + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbra\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- +dbcc_macro:.macro +#ifdef halten_dbcc + halt +#endif + b\2 dbncc\@ + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbcc\@ // bra if plus? +dbncc\@: + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbcc\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//db +ii_dbcc:.macro +ii_0x5\1c8: + dbcc_macro d0_off+2(a7),\2 +ii_0x5\1c9: + dbcc_macro d1_off+2(a7),\2 +ii_0x5\1ca: + dbcc_macro d2,\2 +ii_0x5\1cb: + dbcc_macro d3,\2 +ii_0x5\1cc: + dbcc_macro d4,\2 +ii_0x5\1cd: + dbcc_macro d5,\2 +ii_0x5\1ce: + dbcc_macro d6,\2 +ii_0x5\1cf: + dbcc_macro d7,\2 +.endm \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/ii_ewf.h b/BaS_codewarrior/firebeeV1/sources/ii_ewf.h new file mode 100644 index 0000000..34d2483 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_ewf.h @@ -0,0 +1,181 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +.text +ii_ewf_lset:.macro +// pea + ii_lset_opeag 48,7 + ii_lset 0x487b +// jmp + ii_lset_opeag 4e,f + ii_lset 0x4efb +// jsr + ii_lset_opeag 4e,b + ii_lset 0x4ebb +// tas + ii_lset_opeag 4a,f + ii_lset 0x4ebb +// tst.b + ii_lset_opeag 4a,3 + ii_lset 0x4ebb +// tst.w + ii_lset_opeag 4a,7 + ii_lset 0x4ebb +// tst.l + ii_lset_opeag 4a,b + ii_lset 0x4ebb +// clr.b + ii_lset_opeag 42,3 + ii_lset 0x423b +// clr.w + ii_lset_opeag 42,7 + ii_lset 0x423b +// clr.l + ii_lset_opeag 42,b + ii_lset 0x423b +.endm +//--------------------------------------------------------------------------------------------- +ii_ewf_func:.macro + ewf_func_macro pea,487 + ewf_func_macro jmp,4ef + ewf_func_macro jsr,4eb + ewf_func_macro tas,4af + ewf_func_macro tstb,4a3 + ewf_func_macro tstw,4a7 + ewf_func_macro tstl,4ab + ewf_func_macro clrb,423 + ewf_func_macro clrw,427 + ewf_func_macro clrl,42b +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm + +jmp_macro:.macro + jsr ewf + move.l a1,a0 + ii_end +.endm + +jsr_macro:.macro + jsr ewf + move.l a1,d0 + move.l usp,a1 + move.l a0,-(a1) + move.l a1,usp + move.l d0,a0 + ii_end +.endm + +tas_macro:.macro + jsr ewf + tas (a1) + set_cc0 + ii_end +.endm + +tstb_macro:.macro + jsr ewf + tst.b (a1) + set_cc0 + ii_end +.endm + +tstw_macro:.macro + jsr ewf + tst.w (a1) + set_cc0 + ii_end +.endm + +tstl_macro:.macro + jsr ewf + tst.l (a1) + set_cc0 + ii_end +.endm + +clrb_macro:.macro + jsr ewf + clr.b (a1) + set_cc0 + ii_end +.endm + +clrw_macro:.macro + jsr ewf + clr.w (a1) + set_cc0 + ii_end +.endm + +clrl_macro:.macro + jsr ewf + clr.l (a1) + set_cc0 + ii_end +.endm +//-------------------------------------------------------------------- +ewf_func_macro:.macro //1=art 2=code +ii_0x\20: +#ifdef halten_ewf + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_ewf + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_ewf + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_ewf + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_ewf + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_ewf + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_ewf + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_ewf + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_ewf + halt +#endif + move.l a0,a1 + \1_macro +.endm + diff --git a/BaS_codewarrior/firebeeV1/sources/ii_exg.h b/BaS_codewarrior/firebeeV1/sources/ii_exg.h new file mode 100644 index 0000000..a0544af --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_exg.h @@ -0,0 +1,120 @@ +//-------------------------------------------------------------------- +// exg +//-------------------------------------------------------------------- +.text +ii_exg_lset:.macro +/* ii_lset_dxu c,40 //dx,d0 + ii_lset_dxu c,41 //dx,d1 + ii_lset_dxu c,42 //dx,d2 + ii_lset_dxu c,43 //dx,d3 + ii_lset_dxu c,44 //dx,d4 + ii_lset_dxu c,45 //dx,d5 + ii_lset_dxu c,46 //dx,d6 + ii_lset_dxu c,47 //dx,d7 + ii_lset_dxu c,48 //ax,a0 + ii_lset_dxu c,49 //ax,a1 + ii_lset_dxu c,4a //ax,a2 + ii_lset_dxu c,4b //ax,a3 + ii_lset_dxu c,4c //ax,a4 + ii_lset_dxu c,4d //ax,a5 + ii_lset_dxu c,4e //ax,a6 + ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" + ii_lset_dxu c,88 //dx,a0 + ii_lset_dxu c,89 //dx,a1 + ii_lset_dxu c,8a //dx,a2 + ii_lset_dxu c,8b //dx,a3 + ii_lset_dxu c,8c //dx,a4 + ii_lset_dxu c,8d //dx,a5 + ii_lset_dxu c,8e //dx,a6 + ii_lset_dxu c,8f //dx,a7 +.endm +//--------------------------------------------------------------------------------------------- +ii_exg_func:.macro +// exg dx,dy + ii_exg_dx_dx 14,d0_off(a7) + ii_exg_dx_dx 34,d1_off(a7) + ii_exg_dx_dx 54,d2 + ii_exg_dx_dx 74,d3 + ii_exg_dx_dx 94,d4 + ii_exg_dx_dx b4,d5 + ii_exg_dx_dx d4,d6 + ii_exg_dx_dx f4,d7 +// exg ax,ay + ii_exg_to_ax 14,a0_off(a7) + ii_exg_to_ax 34,a1_off(a7) + ii_exg_to_ax 54,a2 + ii_exg_to_ax 74,a3 + ii_exg_to_ax 94,a4 + ii_exg_to_ax b4,a5 + ii_exg_to_ax d4,a6 + ii_exg_to_ax f4,usp +// exg dx,ay + ii_exg_to_ax 18,d0_off(a7) + ii_exg_to_ax 38,d1_off(a7) + ii_exg_to_ax 58,d2 + ii_exg_to_ax 78,d3 + ii_exg_to_ax 98,d4 + ii_exg_to_ax b8,d5 + ii_exg_to_ax d8,d6 + ii_exg_to_ax f8,d7 +.endm +//--------------------------------------------------------------------------------------------- +exg_macro:.macro +#ifdef halten_exg + halt +#endif + move.l \1,a1 +.ifc \2,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 +.else + .ifc \1,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 + .else + move.l \2,\1 + .endif +.endif + move.l a1,\2 + ii_end +.endm +ii_exg_dx_dx:.macro +ii_0xc\10: + exg_macro \2,d0_off(a7) +ii_0xc\11: + exg_macro \2,d1_off(a7) +ii_0xc\12: + exg_macro \2,d2 +ii_0xc\13: + exg_macro \2,d3 +ii_0xc\14: + exg_macro \2,d4 +ii_0xc\15: + exg_macro \2,d5 +ii_0xc\16: + exg_macro \2,d6 +ii_0xc\17: + exg_macro \2,d7 +.endm +ii_exg_to_ax:.macro +ii_0xc\18: + exg_macro \2,a0_off(a7) +ii_0xc\19: + exg_macro \2,a1_off(a7) +ii_0xc\1a: + exg_macro \2,a2 +ii_0xc\1b: + exg_macro \2,a3 +ii_0xc\1c: + exg_macro \2,a4 +ii_0xc\1d: + exg_macro \2,a5 +ii_0xc\1e: + exg_macro \2,a6 +ii_0xc\1f: + exg_macro \2,usp +.endm \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/ii_func.h b/BaS_codewarrior/firebeeV1/sources/ii_func.h new file mode 100644 index 0000000..f545f47 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_func.h @@ -0,0 +1,945 @@ +//-------------------------------------------------------------------- +// functionen macros +//-------------------------------------------------------------------- +ii_lset_func:.macro +/******************************************************/ +// byt +/******************************************************/ +// func.b dy,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// func.b ax,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// func.b (ax),dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// func.b (ax)+,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// func.b -(ax),dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// func.b d16(ax),dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// func.b dd8(ax,dy),dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// func.b xxx.w,dx + ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b xxx.l,dx + ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d8(pc,dy),dx + ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b #im,dx + ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// word +/******************************************************/ +// func.w dy,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// func.w ax,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// func.w (ax),dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// func.w (ax)+,dx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// func.w -(ax),dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// func.w d16(ax),dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// func.w d8(ax,dy),dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// func.w xxx.w,dx + ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w xxx.l,dx + ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d8(pc,dy),dx + ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w #im,dx + ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// long +/******************************************************/ +// func.l ax,dx -> -(ay),-(ax) + ii_lset_dxu \1,c8 + ii_lset_dxu \1,c9 + ii_lset_dxu \1,ca + ii_lset_dxu \1,cb + ii_lset_dxu \1,cc + ii_lset_dxu \1,cd + ii_lset_dxu \1,ce + ii_lset_dxu \1,cf +// func.w d8(ax,dy),dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// func.l d8(pc,dy),dx + ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// adress register +/******************************************************/ +//func.w dy,ax + ii_lset_dxg \1,c0 + ii_lset_dxg \1,c1 + ii_lset_dxg \1,c2 + ii_lset_dxg \1,c3 + ii_lset_dxg \1,c4 + ii_lset_dxg \1,c5 + ii_lset_dxg \1,c6 + ii_lset_dxg \1,c7 +//func.w ay,ax + ii_lset_dxg \1,c8 + ii_lset_dxg \1,c9 + ii_lset_dxg \1,ca + ii_lset_dxg \1,cb + ii_lset_dxg \1,cc + ii_lset_dxg \1,cd + ii_lset_dxg \1,ce + ii_lset_dxg \1,cf +//func.w (ay),ax + ii_lset_dxg \1,d0 + ii_lset_dxg \1,d1 + ii_lset_dxg \1,d2 + ii_lset_dxg \1,d3 + ii_lset_dxg \1,d4 + ii_lset_dxg \1,d5 + ii_lset_dxg \1,d6 + ii_lset_dxg \1,d7 +//func.w (ay)+,ax + ii_lset_dxg \1,d8 + ii_lset_dxg \1,d9 + ii_lset_dxg \1,da + ii_lset_dxg \1,db + ii_lset_dxg \1,dc + ii_lset_dxg \1,dd + ii_lset_dxg \1,de + ii_lset_dxg \1,df +//func.w -(ay),ax + ii_lset_dxg \1,e0 + ii_lset_dxg \1,e1 + ii_lset_dxg \1,e2 + ii_lset_dxg \1,e3 + ii_lset_dxg \1,e4 + ii_lset_dxg \1,e5 + ii_lset_dxg \1,e6 + ii_lset_dxg \1,e7 +//func.w d16(ay),ax + ii_lset_dxg \1,e8 + ii_lset_dxg \1,e9 + ii_lset_dxg \1,ea + ii_lset_dxg \1,eb + ii_lset_dxg \1,ec + ii_lset_dxg \1,ed + ii_lset_dxg \1,ee + ii_lset_dxg \1,ef +//func.w d8(ay,dy),ax + ii_lset_dxg \1,f0 + ii_lset_dxg \1,f1 + ii_lset_dxg \1,f2 + ii_lset_dxg \1,f3 + ii_lset_dxg \1,f4 + ii_lset_dxg \1,f5 + ii_lset_dxg \1,f6 + ii_lset_dxg \1,f7 +// func.w xxx.w,ax + ii_lset_dxg \1,f8 +// func.w xxx.l,ax + ii_lset_dxg \1,f9 +// func.w d16(pc),ax + ii_lset_dxg \1,fa +// func.w d8(pc,dy),ax + ii_lset_dxg \1,fb +// func.w #im,ax + ii_lset_dxg \1,fc +//-------------------------------------------------------------------- +// ende + .endm; +/*****************************************************************************************/ +ii_func:.macro +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b ds,dx +//-------------------------------------------------------------------- + funcbeadx \1,00,\2dd,d0_off+3(a7) + funcbeadx \1,01,\2dd,d1_off+3(a7) + funcbeadx \1,02,\2dd,d2 + funcbeadx \1,03,\2dd,d3 + funcbeadx \1,04,\2dd,d4 + funcbeadx \1,05,\2dd,d5 + funcbeadx \1,06,\2dd,d6 + funcbeadx \1,07,\2dd,d7 +//-------------------------------------------------------------------- +// func.b (ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,10,\2dda,a0_off(a7) + funcbeadx \1,11,\2dda,a1_off(a7) + funcbeadx \1,12,\2dd,(a2) + funcbeadx \1,13,\2dd,(a3) + funcbeadx \1,14,\2dd,(a4) + funcbeadx \1,15,\2dd,(a5) + funcbeadx \1,16,\2dd,(a6) + funcbeadx \1,17,\2dda,usp +//-------------------------------------------------------------------- +// func.b (ax)+,dx +//-------------------------------------------------------------------- + funcbeadx \1,18,\2ddai,a0_off(a7) + funcbeadx \1,19,\2ddai,a1_off(a7) + funcbeadx \1,1a,\2dd,(a2)+ + funcbeadx \1,1b,\2dd,(a3)+ + funcbeadx \1,1c,\2dd,(a4)+ + funcbeadx \1,1d,\2dd,(a5)+ + funcbeadx \1,1e,\2dd,(a6)+ + funcbeadx \1,1f,\2ddai,usp +//-------------------------------------------------------------------- +// func.b -(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,20,\2ddad,a0_off(a7) + funcbeadx \1,21,\2ddad,a1_off(a7) + funcbeadx \1,22,\2dd,-(a2) + funcbeadx \1,23,\2dd,-(a3) + funcbeadx \1,24,\2dd,-(a4) + funcbeadx \1,25,\2dd,-(a5) + funcbeadx \1,26,\2dd,-(a6) + funcbeadx \1,27,\2ddad,usp +//-------------------------------------------------------------------- +// func.b d16(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,28,\2d16ad,a0_off(a7) + funcbeadx \1,29,\2d16ad,a1_off(a7) + funcbeadx \1,2a,\2d16ad,a2 + funcbeadx \1,2b,\2d16ad,a3 + funcbeadx \1,2c,\2d16ad,a4 + funcbeadx \1,2d,\2d16ad,a5 + funcbeadx \1,2e,\2d16ad,a6 + funcbeadx \1,2f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.b d8(ax,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,30,\2d8ad,a0_off(a7) + funcbeadx \1,31,\2d8ad,a1_off(a7) + funcbeadx \1,32,\2d8ad,a2 + funcbeadx \1,33,\2d8ad,a3 + funcbeadx \1,34,\2d8ad,a4 + funcbeadx \1,35,\2d8ad,a5 + funcbeadx \1,36,\2d8ad,a6 + funcbeadx \1,37,\2d8ad,usp +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,38,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,39,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.b d16(pc),dx +//-------------------------------------------------------------------- + funcbeadx \1,3a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.b d8(pc,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.b #im,dx +//-------------------------------------------------------------------- + funcbeadx \1,3c,\2bir_macro,(a0)+ +//-------------------------------------------------------------------- +// func.b dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b dx,dd -> addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcbdxea \1,00,\2dx,d0_off+3(a7) + funcbdxea \1,01,\2dx,d1_off+3(a7) + funcbdxea \1,02,\2dx,d2 + funcbdxea \1,03,\2dx,d3 + funcbdxea \1,04,\2dx,d4 + funcbdxea \1,05,\2dx,d5 + funcbdxea \1,06,\2dx,d6 + funcbdxea \1,07,\2dx,d7 +//-------------------------------------------------------------------- +// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcaxay \1,08,\2dax,a0_off(a7),b + funcaxay \1,09,\2dax,a1_off(a7).b + funcaxay \1,0a,\2dax,a2,b + funcaxay \1,0b,\2dax,a3,b + funcaxay \1,0c,\2dax,a4,b + funcaxay \1,0d,\2dax,a5,b + funcaxay \1,0e,\2dax,a6,b + funcaxay \1,0f,\2dax,usp,b +//-------------------------------------------------------------------- +// func.b dy,(ax) +//-------------------------------------------------------------------- + funcbdxea \1,10,\2eda,a0_off(a7) + funcbdxea \1,11,\2eda,a1_off(a7) + funcbdxea \1,12,\2dd,(a2) + funcbdxea \1,13,\2dd,(a3) + funcbdxea \1,14,\2dd,(a4) + funcbdxea \1,15,\2dd,(a5) + funcbdxea \1,16,\2dd,(a6) + funcbdxea \1,17,\2eda,usp +//-------------------------------------------------------------------- +// func.b dy,(ax)+ +//-------------------------------------------------------------------- + funcbdxea \1,18,\2edai,a0_off(a7) + funcbdxea \1,19,\2edai,a1_off(a7) + funcbdxea \1,1a,\2edaid,(a2) + funcbdxea \1,1b,\2edaid,(a3) + funcbdxea \1,1c,\2edaid,(a4) + funcbdxea \1,1d,\2edaid,(a5) + funcbdxea \1,1e,\2edaid,(a6) + funcbdxea \1,1f,\2edai,usp +//-------------------------------------------------------------------- +// func.b dy,-(ax) +//-------------------------------------------------------------------- + funcbdxea \1,20,\2edad,a0_off(a7) + funcbdxea \1,21,\2edad,a1_off(a7) + funcbdxea \1,22,\2edadd,(a2) + funcbdxea \1,23,\2edadd,(a3) + funcbdxea \1,24,\2edadd,(a4) + funcbdxea \1,25,\2edadd,(a5) + funcbdxea \1,26,\2edadd,(a6) + funcbdxea \1,27,\2edad,usp +//-------------------------------------------------------------------- +// func.b dy,d16(ax) +//-------------------------------------------------------------------- + funcbdxea \1,28,\2e16ad,a0_off(a7) + funcbdxea \1,29,\2e16ad,a1_off(a7) + funcbdxea \1,2a,\2e16ad,a2 + funcbdxea \1,2b,\2e16ad,a3 + funcbdxea \1,2c,\2e16ad,a4 + funcbdxea \1,2d,\2e16ad,a5 + funcbdxea \1,2e,\2e16ad,a6 + funcbdxea \1,2f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.b dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcbdxea \1,30,\2e8ad,a0_off(a7) + funcbdxea \1,31,\2e8ad,a1_off(a7) + funcbdxea \1,32,\2e8ad,a2 + funcbdxea \1,33,\2e8ad,a3 + funcbdxea \1,34,\2e8ad,a4 + funcbdxea \1,35,\2e8ad,a5 + funcbdxea \1,36,\2e8ad,a6 + funcbdxea \1,37,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,38,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,39,\2xld,(a0)+ +/*****************************************************************************************/ +// word +/*****************************************************************************************/ +// func.w ds,dx +//-------------------------------------------------------------------- + funcweadx \1,40,\2dd,d0_off+2(a7) + funcweadx \1,41,\2dd,d1_off+2(a7) + funcweadx \1,42,\2dd,d2 + funcweadx \1,43,\2dd,d3 + funcweadx \1,44,\2dd,d4 + funcweadx \1,45,\2dd,d5 + funcweadx \1,46,\2dd,d6 + funcweadx \1,47,\2dd,d7 +//-------------------------------------------------------------------- +// func.w ax,dx +//-------------------------------------------------------------------- + funcweadx \1,48,\2dd,a0_off+2(a7) + funcweadx \1,49,\2dd,a1_off+2(a7) + funcweadx \1,4a,\2dd,a2 + funcweadx \1,4b,\2dd,a3 + funcweadx \1,4c,\2dd,a4 + funcweadx \1,4d,\2dd,a5 + funcweadx \1,4e,\2dd,a6 + funcweadx \1,4f,\2ddd,usp +//-------------------------------------------------------------------- +// func.w (ax),dx +//-------------------------------------------------------------------- + funcweadx \1,50,\2dda,a0_off(a7) + funcweadx \1,51,\2dda,a1_off(a7) + funcweadx \1,52,\2dd,(a2) + funcweadx \1,53,\2dd,(a3) + funcweadx \1,54,\2dd,(a4) + funcweadx \1,55,\2dd,(a5) + funcweadx \1,56,\2dd,(a6) + funcweadx \1,57,\2dda,usp +//-------------------------------------------------------------------- +// func.w (ax)+,dx +//-------------------------------------------------------------------- + funcweadx \1,58,\2ddai,a0_off(a7) + funcweadx \1,59,\2ddai,a1_off(a7) + funcweadx \1,5a,\2dd,(a2)+ + funcweadx \1,5b,\2dd,(a3)+ + funcweadx \1,5c,\2dd,(a4)+ + funcweadx \1,5d,\2dd,(a5)+ + funcweadx \1,5e,\2dd,(a6)+ + funcweadx \1,5f,\2ddai,usp +//-------------------------------------------------------------------- +// func.w -(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,60,\2ddad,a0_off(a7) + funcweadx \1,61,\2ddad,a1_off(a7) + funcweadx \1,62,\2dd,-(a2) + funcweadx \1,63,\2dd,-(a3) + funcweadx \1,64,\2dd,-(a4) + funcweadx \1,65,\2dd,-(a5) + funcweadx \1,66,\2dd,-(a6) + funcweadx \1,67,\2ddad,usp +//-------------------------------------------------------------------- +// func.w d16(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,68,\2d16ad,a0_off(a7) + funcweadx \1,69,\2d16ad,a1_off(a7) + funcweadx \1,6a,\2d16ad,a2 + funcweadx \1,6b,\2d16ad,a3 + funcweadx \1,6c,\2d16ad,a4 + funcweadx \1,6d,\2d16ad,a5 + funcweadx \1,6e,\2d16ad,a6 + funcweadx \1,6f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.w d8(ax,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,70,\2d8ad,a0_off(a7) + funcweadx \1,71,\2d8ad,a1_off(a7) + funcweadx \1,72,\2d8ad,a2 + funcweadx \1,73,\2d8ad,a3 + funcweadx \1,74,\2d8ad,a4 + funcweadx \1,75,\2d8ad,a5 + funcweadx \1,76,\2d8ad,a6 + funcweadx \1,77,\2d8ad,usp +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,78,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,79,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),dx +//-------------------------------------------------------------------- + funcweadx \1,7a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,dx +//-------------------------------------------------------------------- + funcweadx \1,7c,\2dd,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.w dx,dd -> addx subx etc. +//-------------------------------------------------------------------- +.ifnc \2,and //platz für exg + funcwdxea \1,40,\2dx,d0_off+2(a7) + funcwdxea \1,41,\2dx,d1_off+2(a7) + funcwdxea \1,42,\2dx,d2 + funcwdxea \1,43,\2dx,d3 + funcwdxea \1,44,\2dx,d4 + funcwdxea \1,45,\2dx,d5 + funcwdxea \1,46,\2dx,d6 + funcwdxea \1,47,\2dx,d7 +//-------------------------------------------------------------------- +// func.w -(ax),-(ay) -> addx,subx +//-------------------------------------------------------------------- + funcaxay \1,48,\2dax,a0_off(a7),w + funcaxay \1,49,\2dax,a1_off(a7).w + funcaxay \1,4a,\2dax,a2,w + funcaxay \1,4b,\2dax,a3,w + funcaxay \1,4c,\2dax,a4,w + funcaxay \1,4d,\2dax,a5,w + funcaxay \1,4e,\2dax,a6,w + funcaxay \1,4f,\2dax,usp,w +.endif +//-------------------------------------------------------------------- +// func.w dy,(ax) +//-------------------------------------------------------------------- + funcwdxea \1,50,\2eda,a0_off(a7) + funcwdxea \1,51,\2eda,a1_off(a7) + funcwdxea \1,52,\2dd,(a2) + funcwdxea \1,53,\2dd,(a3) + funcwdxea \1,54,\2dd,(a4) + funcwdxea \1,55,\2dd,(a5) + funcwdxea \1,56,\2dd,(a6) + funcwdxea \1,57,\2eda,usp +//-------------------------------------------------------------------- +// func.w dy,(ax)+ +//-------------------------------------------------------------------- + funcwdxea \1,58,\2edai,a0_off(a7) + funcwdxea \1,59,\2edai,a1_off(a7) + funcwdxea \1,5a,\2edaid,(a2) + funcwdxea \1,5b,\2edaid,(a3) + funcwdxea \1,5c,\2edaid,(a4) + funcwdxea \1,5d,\2edaid,(a5) + funcwdxea \1,5e,\2edaid,(a6) + funcwdxea \1,5f,\2edai,usp +//-------------------------------------------------------------------- +// func.w dy,-(ax) +//-------------------------------------------------------------------- + funcwdxea \1,60,\2edad,a0_off(a7) + funcwdxea \1,61,\2edad,a1_off(a7) + funcwdxea \1,62,\2edadd,(a2) + funcwdxea \1,63,\2edadd,(a3) + funcwdxea \1,64,\2edadd,(a4) + funcwdxea \1,65,\2edadd,(a5) + funcwdxea \1,66,\2edadd,(a6) + funcwdxea \1,67,\2edad,usp +//-------------------------------------------------------------------- +// func.w dy,d16(ax) +//-------------------------------------------------------------------- + funcwdxea \1,68,\2e16ad,a0_off(a7) + funcwdxea \1,69,\2e16ad,a1_off(a7) + funcwdxea \1,6a,\2e16ad,a2 + funcwdxea \1,6b,\2e16ad,a3 + funcwdxea \1,6c,\2e16ad,a4 + funcwdxea \1,6d,\2e16ad,a5 + funcwdxea \1,6e,\2e16ad,a6 + funcwdxea \1,6f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.w dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcwdxea \1,70,\2e8ad,a0_off(a7) + funcwdxea \1,71,\2e8ad,a1_off(a7) + funcwdxea \1,72,\2e8ad,a2 + funcwdxea \1,73,\2e8ad,a3 + funcwdxea \1,74,\2e8ad,a4 + funcwdxea \1,75,\2e8ad,a5 + funcwdxea \1,76,\2e8ad,a6 + funcwdxea \1,77,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,78,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,79,\2xld,(a0)+ +/*****************************************************************************************/ +// long +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// func.l -(ax),-(ay) +//-------------------------------------------------------------------- + funcaxay \1,c8,\2dax,a0_off(a7),l + funcaxay \1,c9,\2dax,a1_off(a7).l + funcaxay \1,ca,\2dax,a2,l + funcaxay \1,cb,\2dax,a3,l + funcaxay \1,cc,\2dax,a4,l + funcaxay \1,cd,\2dax,a5,l + funcaxay \1,ce,\2dax,a6,l + funcaxay \1,cf,\2dax,usp,l +//-------------------------------------------------------------------- +// func.l d8(ax,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,b0,\2d8ad,a0_off(a7) + funcleadx \1,b1,\2d8ad,a1_off(a7) + funcleadx \1,b2,\2d8ad,a2 + funcleadx \1,b3,\2d8ad,a3 + funcleadx \1,b4,\2d8ad,a4 + funcleadx \1,b5,\2d8ad,a5 + funcleadx \1,b6,\2d8ad,a6 + funcleadx \1,b7,\2d8ad,usp +//-------------------------------------------------------------------- +// func.l d8(pc,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.l dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcldxea \1,b0,\2e8ad,a0_off(a7) + funcldxea \1,b1,\2e8ad,a1_off(a7) + funcldxea \1,b2,\2e8ad,a2 + funcldxea \1,b3,\2e8ad,a3 + funcldxea \1,b4,\2e8ad,a4 + funcldxea \1,b5,\2e8ad,a5 + funcldxea \1,b6,\2e8ad,a6 + funcldxea \1,b7,\2e8ad,usp +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// func.w ea,ax +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// func.w dx,ax +//-------------------------------------------------------------------- + funcweaax \1,c0,\2aw,d0 + funcweaax \1,c1,\2aw,d1 + funcweaax \1,c2,\2aw,d2 + funcweaax \1,c3,\2aw,d3 + funcweaax \1,c4,\2aw,d4 + funcweaax \1,c5,\2aw,d5 + funcweaax \1,c6,\2aw,d6 + funcweaax \1,c7,\2aw,d7 +//-------------------------------------------------------------------- +// func.w ay,ax +//-------------------------------------------------------------------- + funcweaax \1,c8,\2aw,a0 + funcweaax \1,c9,\2aw,a1 + funcweaax \1,ca,\2aw,a2 + funcweaax \1,cb,\2aw,a3 + funcweaax \1,cc,\2aw,a4 + funcweaax \1,cd,\2aw,a5 + funcweaax \1,ce,\2aw,a6 + funcweaax \1,cf,\2awu,a7 +//-------------------------------------------------------------------- +// func.w (ay),ax +//-------------------------------------------------------------------- + funcweaax \1,d0,\2aw,(a0) + funcweaax \1,d1,\2aw,(a1) + funcweaax \1,d2,\2aw,(a2) + funcweaax \1,d3,\2aw,(a3) + funcweaax \1,d4,\2aw,(a4) + funcweaax \1,d5,\2aw,(a5) + funcweaax \1,d6,\2aw,(a6) + funcweaax \1,d7,\2awu,(a7) +//-------------------------------------------------------------------- +// func.w (ay)+,ax +//-------------------------------------------------------------------- + funcweaax \1,d8,\2aw,(a0)+ + funcweaax \1,d9,\2aw,(a1)+ + funcweaax \1,da,\2aw,(a2)+ + funcweaax \1,db,\2aw,(a3)+ + funcweaax \1,dc,\2aw,(a4)+ + funcweaax \1,dd,\2aw,(a5)+ + funcweaax \1,de,\2aw,(a6)+ + funcweaax \1,df,\2awu,(a7)+ +//-------------------------------------------------------------------- +// func.w -(ay),ax +//-------------------------------------------------------------------- + funcweaax \1,e0,\2aw,-(a0) + funcweaax \1,e1,\2aw,-(a1) + funcweaax \1,e2,\2aw,-(a2) + funcweaax \1,e3,\2aw,-(a3) + funcweaax \1,e4,\2aw,-(a4) + funcweaax \1,e5,\2aw,-(a5) + funcweaax \1,e6,\2aw,-(a6) + funcweaax \1,e7,\2awu,-(a7) +//-------------------------------------------------------------------- +// func.w d16(ay),ax +//-------------------------------------------------------------------- + funcweaaxn \1,e8,\2awd16a,a0_off(a7) + funcweaaxn \1,e9,\2awd16a,a1_off(a7) + funcweaaxn \1,ea,\2awd16a,a2 + funcweaaxn \1,eb,\2awd16a,a3 + funcweaaxn \1,ec,\2awd16a,a4 + funcweaaxn \1,ed,\2awd16a,a5 + funcweaaxn \1,ee,\2awd16a,a6 + funcweaaxn \1,ef,\2awd16a,usp +//-------------------------------------------------------------------- +// func.w d8(ay,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,f0,\2awd8a,a0_off(a7) + funcweaaxn \1,f1,\2awd8a,a1_off(a7) + funcweaaxn \1,f2,\2awd8a,a2 + funcweaaxn \1,f3,\2awd8a,a3 + funcweaaxn \1,f4,\2awd8a,a4 + funcweaaxn \1,f5,\2awd8a,a5 + funcweaaxn \1,f6,\2awd8a,a6 + funcweaaxn \1,f7,\2awd8a,usp +//-------------------------------------------------------------------- +// func.w xxx.w,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f8,\2awxwax,(a0)+ +//-------------------------------------------------------------------- +// func.w xxxlw,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f9,\2awxlax,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fa,\2awd16pcax,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,ax +//-------------------------------------------------------------------- + funcweaaxn \1,fc,\2awim,(a0)+ +//-------------------------------------------------------------------- +// ende + .endm; +//-------------------------------------------------------------------- +// byt +funcbeadx:.macro // function byt: im,dx +ii_0x\10\2: + \3 \4,d0_off+3(a7),b +ii_0x\12\2: + \3 \4,d1_off+3(a7),b +ii_0x\14\2: + \3 \4,d2,b +ii_0x\16\2: + \3 \4,d3,b +ii_0x\18\2: + \3 \4,d4,b +ii_0x\1a\2: + \3 \4,d5,b +ii_0x\1c\2: + \3 \4,d6,b +ii_0x\1e\2: + \3 \4,d7,b + .endm; +funcbdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+3(a7),\4,b +ii_0x\13\2: + \3 d1_off+3(a7),\4,b +ii_0x\15\2: + \3 d2,\4,b +ii_0x\17\2: + \3 d3,\4,b +ii_0x\19\2: + \3 d4,\4,b +ii_0x\1b\2: + \3 d5,\4,b +ii_0x\1d\2: + \3 d6,\4,b +ii_0x\1f\2: + \3 d7,\4,b + .endm; +//-------------------------------------------------------------------- +// word +funcweadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off+2(a7),w +ii_0x\12\2: + \3 \4,d1_off+2(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcwdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+2(a7),\4,w +ii_0x\13\2: + \3 d1_off+2(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------------- +// long +funcleadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off(a7),w +ii_0x\12\2: + \3 \4,d1_off(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcldxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off(a7),\4,w +ii_0x\13\2: + \3 d1_off(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------- +// address +funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0 +ii_0x\12\2: + \3 \4,a1 +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3a7 \4,a7 // "a7" beachten wegen usp + .endm; +funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0_off(a7) +ii_0x\12\2: + \3 \4,a1_off(a7) +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3 \4,usp + .endm; +//-------------------------------------------------------------- +// byt, word, long +//-------------------------------------------------------------- +funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size +ii_0x\11\2: + \3 a0_off(a7),\4,\5 +ii_0x\13\2: + \3 a1_off(a7),\4,\5 +ii_0x\15\2: + \3 a2,\4,\5 +ii_0x\17\2: + \3 a3,\4,\5 +ii_0x\19\2: + \3 a4,\4,\5 +ii_0x\1b\2: + \3 a5,\4,\5 +ii_0x\1d\2: + \3 a6,\4,\5 +ii_0x\1f\2: + \3 usp,\4,\5 + .endm; diff --git a/BaS_codewarrior/firebeeV1/sources/ii_jmp.h b/BaS_codewarrior/firebeeV1/sources/ii_jmp.h new file mode 100644 index 0000000..1896118 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_jmp.h @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +ii_\1_func:.macro +ii_0x\20: +#ifdef halten_\1 + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_\1 + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_\1 + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_\1 + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_\1 + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_\1 + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_\1 + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_\1 + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_\1 + halt +#endif + move.l a0,a1 + \1_macro +.endm diff --git a/BaS_codewarrior/firebeeV1/sources/ii_lea.h b/BaS_codewarrior/firebeeV1/sources/ii_lea.h new file mode 100644 index 0000000..7a422a7 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_lea.h @@ -0,0 +1,105 @@ +//------------------------------------------------------------------- +// lea +//------------------------------------------------------------------- +.text +ii_lea_lset:.macro + ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 + ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 + ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 + ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 + ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 + ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 + ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 + ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 + ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 +.endm + +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_lea_sub:.macro +ii_0x4\1\2: +#ifdef halten_lea + halt +#endif + move.l \4,a1 + jsr ewf + move.l a1,\3 + ii_end +.endm +ii_lea_func:.macro +//lea d8(ax,dy.w),a0-a7 + ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) + ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) + ii_lea_sub 1,f2,a0_off(a7),a2 + ii_lea_sub 1,f3,a0_off(a7),a3 + ii_lea_sub 1,f4,a0_off(a7),a4 + ii_lea_sub 1,f5,a0_off(a7),a5 + ii_lea_sub 1,f6,a0_off(a7),a6 + ii_lea_sub 1,f7,a0_off(a7),usp + ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) + ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) + ii_lea_sub 3,f2,a1_off(a7),a2 + ii_lea_sub 3,f3,a1_off(a7),a3 + ii_lea_sub 3,f4,a1_off(a7),a4 + ii_lea_sub 3,f5,a1_off(a7),a5 + ii_lea_sub 3,f6,a1_off(a7),a6 + ii_lea_sub 3,f7,a1_off(a7),usp + ii_lea_sub 5,f0,a2,a0_off(a7) + ii_lea_sub 5,f1,a2,a1_off(a7) + ii_lea_sub 5,f2,a2,a2 + ii_lea_sub 5,f3,a2,a3 + ii_lea_sub 5,f4,a2,a4 + ii_lea_sub 5,f5,a2,a5 + ii_lea_sub 5,f6,a2,a6 + ii_lea_sub 5,f7,a2,usp + ii_lea_sub 7,f0,a3,a0_off(a7) + ii_lea_sub 7,f1,a3,a1_off(a7) + ii_lea_sub 7,f2,a3,a2 + ii_lea_sub 7,f3,a3,a3 + ii_lea_sub 7,f4,a3,a4 + ii_lea_sub 7,f5,a3,a5 + ii_lea_sub 7,f6,a3,a6 + ii_lea_sub 7,f7,a3,usp + ii_lea_sub 9,f0,a4,a0_off(a7) + ii_lea_sub 9,f1,a4,a1_off(a7) + ii_lea_sub 9,f2,a4,a2 + ii_lea_sub 9,f3,a4,a3 + ii_lea_sub 9,f4,a4,a4 + ii_lea_sub 9,f5,a4,a5 + ii_lea_sub 9,f6,a4,a6 + ii_lea_sub 9,f7,a4,usp + ii_lea_sub b,f0,a5,a0_off(a7) + ii_lea_sub b,f1,a5,a1_off(a7) + ii_lea_sub b,f2,a5,a2 + ii_lea_sub b,f3,a5,a3 + ii_lea_sub b,f4,a5,a4 + ii_lea_sub b,f5,a5,a5 + ii_lea_sub b,f6,a5,a6 + ii_lea_sub b,f7,a6,usp + ii_lea_sub d,f0,a6,a0_off(a7) + ii_lea_sub d,f1,a6,a1_off(a7) + ii_lea_sub d,f2,a6,a2 + ii_lea_sub d,f3,a6,a3 + ii_lea_sub d,f4,a6,a4 + ii_lea_sub d,f5,a6,a5 + ii_lea_sub d,f6,a6,a6 + ii_lea_sub d,f7,a6,usp + ii_lea_sub f,f0,usp,a0_off(a7) + ii_lea_sub f,f1,usp,a1_off(a7) + ii_lea_sub f,f2,usp,a2 + ii_lea_sub f,f3,usp,a3 + ii_lea_sub f,f4,usp,a4 + ii_lea_sub f,f5,usp,a5 + ii_lea_sub f,f6,usp,a6 + ii_lea_sub f,f7,usp,usp +// lea d8(pc,dy.w),az + ii_lea_sub 1,fb,a0_off(a7),a0 + ii_lea_sub 3,fb,a1_off(a7),a0 + ii_lea_sub 5,fb,a2,a0 + ii_lea_sub 7,fb,a3,a0 + ii_lea_sub 9,fb,a4,a0 + ii_lea_sub b,fb,a5,a0 + ii_lea_sub d,fb,a6,a0 + ii_lea_sub f,fb,usp,a0 +.endm \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/ii_macro.h b/BaS_codewarrior/firebeeV1/sources/ii_macro.h new file mode 100644 index 0000000..5db7460 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_macro.h @@ -0,0 +1,144 @@ +/*******************************************************/ +// constanten +/*******************************************************/ +.extern ___RAMBAR1 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _d0_save +.extern _a7_save + +ii_ss = 16 +d0_off = 0 +d1_off = 4 +a0_off = 8 +a1_off = 12 +format_off = 16 +sr_off = 18 +ccr_off = 19 +pc_off = 20 + +#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle + +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +ii_end: .macro + move.l a0,pc_off(a7) + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 + rte + .endm; + +set_cc0:.macro + move.w ccr,d0 + move.b d0,ccr_off(a7) + .endm; + +ii_esr: .macro // geht nicht!!?? + movem.l (a7),d0/d1/a0/a1 + lea ii_ss+8(a7),a7 // stack erhöhen + move.w d0,_d0_save // d0.w sicheren + move.w -6(a7),d0 // sr holen + move.w d0,sr // sr setzen + nop + move.w _d0_save,d0 // d0.w zurück + .endm; + +ii_end_mvm:.macro + move.l a0_off(a7),a0 + lea 16(a7),a7 + rte + .endm; + +ii_endj:.macro + movem.l (a7),d0/d1/a0/a1 // register zurück + lea ii_ss(a7),a7 // korr + rte // ende + .endm; + +set_nzvc:.macro // set ccr bits nzvc + move.w ccr,d1 + bclr #4,d1 + btst #4,ccr_off(a7) + beq snzvc2\@ + bset #4,d1 +snzvc2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc1:.macro + move.w ccr,d1 + move.b d1,ccr_off(a7) + .endm; + +set_cc_b:.macro + move.w ccr,d1 + btst #7,d0 // byt negativ? + beq set_cc_b2\@ + bset #3,d1 // make negativ +set_cc_b2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc_w:.macro + move.w ccr,d1 + btst #15,d0 // byt negativ? + beq set_cc_w2\@ + bset #3,d1 // make negativ +set_cc_w2\@: + move.b d1,ccr_off(a7) + .endm; + +get_pc: .macro + lea.l (a0),a1 + .endm; + +//-------------------------------------------------------------------- +ii_lset:.macro + lea table+\1*4,a0 + move.l #ii_\1,(a0) + .endm; +ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + ii_lset_dxg \1,\2 + ii_lset_dxu \1,\2 + .endm; +ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + lea table+0x\10\2*4,a0 + move.l #ii_0x\10\2,(a0) + lea 0x800(a0),a0 // 4 * 0x200 + move.l #ii_0x\12\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\14\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\16\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\18\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1a\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1c\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1e\2,(a0) + .endm; +ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 + lea table+0x\11\2*4,a0 + move.l #ii_0x\11\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\13\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\15\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\17\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\19\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1b\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1d\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1f\2,(a0) + .endm; + diff --git a/BaS_codewarrior/firebeeV1/sources/ii_move.h b/BaS_codewarrior/firebeeV1/sources/ii_move.h new file mode 100644 index 0000000..1ae8213 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_move.h @@ -0,0 +1,1271 @@ +//------------------------------------------------------------------- +// move +//------------------------------------------------------------------- +.extern ewf + +.text +ii_move_lset:.macro +//------------------------------------------------------------------------- +// 0x1000 move.b +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 11,e +// move.x d16(ax),xxx.l + ii_lset_opeau 13,e +// move.x d16(pc),xxx.w + ii_lset 0x11fa +// move.x d16(pc),xxx.l + ii_lset 0x13fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 1,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 1,79 +// move.x #xx,d16(ax) + ii_lset_dxu 1,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x11f8 +// move.x xxx.l,xxx.w + ii_lset 0x11f9 +// move.x xxx.w,xxx.l + ii_lset 0x13f8 +// move.x xxx.l,xxx.l + ii_lset 0x13f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x11fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x13fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 11,8 + ii_lset_opeag 13,8 + ii_lset_opeag 15,8 + ii_lset_opeag 17,8 + ii_lset_opeag 19,8 + ii_lset_opeag 1b,8 + ii_lset_opeag 1d,8 + ii_lset_opeag 1f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 11,9 + ii_lset_opea 13,9 + ii_lset_opea 15,9 + ii_lset_opea 17,9 + ii_lset_opea 19,9 + ii_lset_opea 1b,9 + ii_lset_opea 1d,9 + ii_lset_opea 1f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 11,a + ii_lset_opeag 13,a + ii_lset_opeag 15,a + ii_lset_opeag 17,a + ii_lset_opeag 19,a + ii_lset_opeag 1b,a + ii_lset_opeag 1d,a + ii_lset_opeag 1f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) + ii_lset_opeag 17,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 17,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 17,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 10,3 + ii_lset_opeag 12,3 + ii_lset_opeag 14,3 + ii_lset_opeag 16,3 + ii_lset_opeag 18,3 + ii_lset_opeag 1a,3 + ii_lset_opeag 1c,3 + ii_lset_opeag 1e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 10,7 + ii_lset_opeag 12,7 + ii_lset_opeag 14,7 + ii_lset_opeag 16,7 + ii_lset_opeag 18,7 + ii_lset_opeag 1a,7 + ii_lset_opeag 1c,7 + ii_lset_opeag 1e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 10,b + ii_lset_opeag 12,b + ii_lset_opeag 14,b + ii_lset_opeag 16,b + ii_lset_opeag 18,b + ii_lset_opeag 1a,b + ii_lset_opeag 1c,b + ii_lset_opeag 1e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 10,f + ii_lset_opeag 12,f + ii_lset_opeag 14,f + ii_lset_opeag 16,f + ii_lset_opeag 18,f + ii_lset_opeag 1a,f + ii_lset_opeag 1c,f + ii_lset_opeag 1e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 11,3 + ii_lset_opeag 13,3 + ii_lset_opeag 15,3 + ii_lset_opeag 17,3 + ii_lset_opeag 19,3 + ii_lset_opeag 1b,3 + ii_lset_opeag 1d,3 + ii_lset_opeag 1f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 1,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 1,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 1,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 1,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 1,3b +//------------------------------------------------------------------------- +// 0x2000 move.l +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 21,e +// move.x d16(ax),xxx.l + ii_lset_opeau 23,e +// move.x d16(pc),xxx.w + ii_lset 0x21fa +// move.x d16(pc),xxx.l + ii_lset 0x23fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 2,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 2,79 +// move.x #xx,d16(ax) + ii_lset_dxu 2,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x21f8 +// move.x xxx.l,xxx.w + ii_lset 0x21f9 +// move.x xxx.w,xxx.l + ii_lset 0x23f8 +// move.x xxx.l,xxx.l + ii_lset 0x23f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x21fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x23fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 21,8 + ii_lset_opeag 23,8 + ii_lset_opeag 25,8 + ii_lset_opeag 27,8 + ii_lset_opeag 29,8 + ii_lset_opeag 2b,8 + ii_lset_opeag 2d,8 + ii_lset_opeag 2f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 21,9 + ii_lset_opea 23,9 + ii_lset_opea 25,9 + ii_lset_opea 27,9 + ii_lset_opea 29,9 + ii_lset_opea 2b,9 + ii_lset_opea 2d,9 + ii_lset_opea 2f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 21,a + ii_lset_opeag 23,a + ii_lset_opeag 25,a + ii_lset_opeag 27,a + ii_lset_opeag 29,a + ii_lset_opeag 2b,a + ii_lset_opeag 2d,a + ii_lset_opeag 2f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 27,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 27,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 27,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 20,3 + ii_lset_opeag 22,3 + ii_lset_opeag 24,3 + ii_lset_opeag 26,3 + ii_lset_opeag 28,3 + ii_lset_opeag 2a,3 + ii_lset_opeag 2c,3 + ii_lset_opeag 2e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 20,7 + ii_lset_opeag 22,7 + ii_lset_opeag 24,7 + ii_lset_opeag 26,7 + ii_lset_opeag 28,7 + ii_lset_opeag 2a,7 + ii_lset_opeag 2c,7 + ii_lset_opeag 2e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 20,b + ii_lset_opeag 22,b + ii_lset_opeag 24,b + ii_lset_opeag 26,b + ii_lset_opeag 28,b + ii_lset_opeag 2a,b + ii_lset_opeag 2c,b + ii_lset_opeag 2e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 20,f + ii_lset_opeag 22,f + ii_lset_opeag 24,f + ii_lset_opeag 26,f + ii_lset_opeag 28,f + ii_lset_opeag 2a,f + ii_lset_opeag 2c,f + ii_lset_opeag 2e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 21,3 + ii_lset_opeag 23,3 + ii_lset_opeag 25,3 + ii_lset_opeag 27,3 + ii_lset_opeag 29,3 + ii_lset_opeag 2b,3 + ii_lset_opeag 2d,3 + ii_lset_opeag 2f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 2,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 2,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 2,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 2,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 2,3b +//------------------------------------------------------------------------- +// 0x3000 move.w +///------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 31,e +// move.x d16(ax),xxx.l + ii_lset_opeau 33,e +// move.x d16(pc),xxx.w + ii_lset 0x31fa +// move.x d16(pc),xxx.l + ii_lset 0x33fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 3,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 3,79 +// move.x #xx,d16(ax) + ii_lset_dxu 3,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x31f8 +// move.x xxx.l,xxx.w + ii_lset 0x31f9 +// move.x xxx.w,xxx.l + ii_lset 0x33f8 +// move.x xxx.l,xxx.l + ii_lset 0x33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x33fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 31,8 + ii_lset_opeag 33,8 + ii_lset_opeag 35,8 + ii_lset_opeag 37,8 + ii_lset_opeag 39,8 + ii_lset_opeag 3b,8 + ii_lset_opeag 3d,8 + ii_lset_opeag 3f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 31,9 + ii_lset_opea 33,9 + ii_lset_opea 35,9 + ii_lset_opea 37,9 + ii_lset_opea 39,9 + ii_lset_opea 3b,9 + ii_lset_opea 3d,9 + ii_lset_opea 3f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 31,a + ii_lset_opeag 33,a + ii_lset_opeag 35,a + ii_lset_opeag 37,a + ii_lset_opeag 39,a + ii_lset_opeag 3b,a + ii_lset_opeag 3d,a + ii_lset_opeag 3f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 37,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 37,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 37,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 30,3 + ii_lset_opeag 32,3 + ii_lset_opeag 34,3 + ii_lset_opeag 36,3 + ii_lset_opeag 38,3 + ii_lset_opeag 3a,3 + ii_lset_opeag 3c,3 + ii_lset_opeag 3e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 30,7 + ii_lset_opeag 32,7 + ii_lset_opeag 34,7 + ii_lset_opeag 36,7 + ii_lset_opeag 38,7 + ii_lset_opeag 3a,7 + ii_lset_opeag 3c,7 + ii_lset_opeag 3e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 30,b + ii_lset_opeag 32,b + ii_lset_opeag 34,b + ii_lset_opeag 36,b + ii_lset_opeag 38,b + ii_lset_opeag 3a,b + ii_lset_opeag 3c,b + ii_lset_opeag 3e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 30,f + ii_lset_opeag 32,f + ii_lset_opeag 34,f + ii_lset_opeag 36,f + ii_lset_opeag 38,f + ii_lset_opeag 3a,f + ii_lset_opeag 3c,f + ii_lset_opeag 3e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 31,3 + ii_lset_opeag 33,3 + ii_lset_opeag 35,3 + ii_lset_opeag 37,3 + ii_lset_opeag 39,3 + ii_lset_opeag 3b,3 + ii_lset_opeag 3d,3 + ii_lset_opeag 3f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 3,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 3,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 3,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 3,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 3,3b +.endm +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_move_op:.macro +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_move_d16ax_xxx 1e8,a0_off(a7),w + ii_move_d16ax_xxx 1e9,a1_off(a7),w + ii_move_d16ax_xxx 1ea,a2,w + ii_move_d16ax_xxx 1eb,a3,w + ii_move_d16ax_xxx 1ec,a4,w + ii_move_d16ax_xxx 1ed,a5,w + ii_move_d16ax_xxx 1ee,a6,w + ii_move_d16ax_xxx 1ef,usp,w +// move.x d16(ax),xxx.l + ii_move_d16ax_xxx 3e8,a0_off(a7),l + ii_move_d16ax_xxx 3e9,a1_off(a7),l + ii_move_d16ax_xxx 3ea,a2,l + ii_move_d16ax_xxx 3eb,a3,l + ii_move_d16ax_xxx 3ec,a4,l + ii_move_d16ax_xxx 3ed,a5,l + ii_move_d16ax_xxx 3ee,a6,l + ii_move_d16ax_xxx 3ef,usp,l +// move.x d16(pc),xxx.w + ii_move_d16ax_xxx 1fa,a0,w +// move.x d16(pc),xxx.l + ii_move_d16ax_xxx 3fa,a0,l +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) + ii_move_xxx_d16ax 1,a0_off(a7) + ii_move_xxx_d16ax 3,a1_off(a7) + ii_move_xxx_d16ax 5,a2 + ii_move_xxx_d16ax 7,a3 + ii_move_xxx_d16ax 9,a4 + ii_move_xxx_d16ax b,a5 + ii_move_xxx_d16ax d,a6 + ii_move_xxx_d16ax f,usp +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_move_xxx_xxx b,w,w,11f8 + ii_move_xxx_xxx l,w,w,21f8 + ii_move_xxx_xxx w,w,w,31f8 +// move.x xxx.l,xxx.w + ii_move_xxx_xxx b,l,w,11f9 + ii_move_xxx_xxx l,l,w,21f9 + ii_move_xxx_xxx w,l,w,31f9 +// move.x xxx.w,xxx.l + ii_move_xxx_xxx b,w,l,13f8 + ii_move_xxx_xxx l,w,l,23f8 + ii_move_xxx_xxx w,w,l,33f8 +// move.x xxx.l,xxx.l + ii_move_xxx_xxx b,l,l,13f9 + ii_move_xxx_xxx l,l,l,23f9 + ii_move_xxx_xxx w,l,l,33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_move_im_xxx b,w,11fc + ii_move_im_xxx l,w,21fc + ii_move_im_xxx w,w,31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_move_im_xxx b,l,13fc + ii_move_im_xxx l,l,23fc + ii_move_im_xxx w,l,33fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(ax/pc,dy) + ii_move_dxxia d0_off(a7),80,id,d,c0 + ii_move_dxxia d1_off(a7),81,id,d,c1 + ii_move_dxxia d2,82,d,d,c2 + ii_move_dxxia d3,83,d,d,c3 + ii_move_dxxia d4,84,d,d,c4 + ii_move_dxxia d5,85,d,d,c5 + ii_move_dxxia d6,86,d,d,c6 + ii_move_dxxia d7,87,d,d,c7 +// move.x ax,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),88,id,d,c8 + ii_move_dxxia a1_off(a7),89,id,d,c9 + ii_move_dxxia a2,8a,d,da,ca + ii_move_dxxia a3,8b,d,da,cb + ii_move_dxxia a4,8c,d,da,cc + ii_move_dxxia a5,8d,d,da,cd + ii_move_dxxia a6,8e,d,da,ce + ii_move_dxxia a7,8f,a7,da,cf +// move.x (ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),90,ia,d,d0 + ii_move_dxxia a1_off(a7),91,ia,d,d1 + ii_move_dxxia (a2),92,d,d,d2 + ii_move_dxxia (a3),93,d,d,d3 + ii_move_dxxia (a4),94,d,d,d4 + ii_move_dxxia (a5),95,d,d,d5 + ii_move_dxxia (a6),96,d,d,d6 + ii_move_dxxia (a7),97,a7,d,d7 +// move.x (ax)+,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),98,iap,d,d8 + ii_move_dxxia a1_off(a7),99,iap,d,d9 + ii_move_dxxia (a2)+,9a,d,d,da + ii_move_dxxia (a3)+,9b,d,d,db + ii_move_dxxia (a4)+,9c,d,d,dc + ii_move_dxxia (a5)+,9d,d,d,dd + ii_move_dxxia (a6)+,9e,d,d,de + ii_move_dxxia (a7)+,9f,a7,d,df +// move.x -(ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),a0,iam,d,e0 + ii_move_dxxia a1_off(a7),a1,iam,d,e1 + ii_move_dxxia -(a2),a2,d,d,e2 + ii_move_dxxia -(a3),a3,d,d,e3 + ii_move_dxxia -(a4),a4,d,d,e4 + ii_move_dxxia -(a5),a5,d,d,e5 + ii_move_dxxia -(a6),a6,d,d,e6 + ii_move_dxxia -(a7),a7,a7,d,e7 +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),dz + ii_move_d8_dest d0,id,03,dx + ii_move_d8_dest d1,id,23,dx + ii_move_d8_dest d2,d,43,dx + ii_move_d8_dest d3,d,63,dx + ii_move_d8_dest d4,d,83,dx + ii_move_d8_dest d5,d,a3,dx + ii_move_d8_dest d6,d,c3,dx + ii_move_d8_dest d7,d,e3,dx +// move.x d8(ax/pc,dy),az + ii_move_d8_dest a0,id,07,ax + ii_move_d8_dest a1,id,27,ax + ii_move_d8_dest a2,d,47,ax + ii_move_d8_dest a3,d,67,ax + ii_move_d8_dest a4,d,87,ax + ii_move_d8_dest a5,d,a7,ax + ii_move_d8_dest a6,d,c7,ax + ii_move_d8_dest usp,id,e7,ax +// move.x d8(ax/pc,dy),(az) + ii_move_d8_dest a0_off(a7),id,0b,ia + ii_move_d8_dest a1_off(a7),id,2b,ia + ii_move_d8_dest (a2),d,4b,ia + ii_move_d8_dest (a3),d,6b,ia + ii_move_d8_dest (a4),d,8b,ia + ii_move_d8_dest (a5),d,ab,ia + ii_move_d8_dest (a6),d,cb,ia + ii_move_d8_dest usp,id,eb,ia +// move.x d8(ax/pc,dy),(az)+ + ii_move_d8_dest a0_off(a7),id,0f,iap + ii_move_d8_dest a1_off(a7),id,2f,iap + ii_move_d8_dest (a2)+,d,4f,iap + ii_move_d8_dest (a3)+,d,6f,iap + ii_move_d8_dest (a4)+,d,8f,iap + ii_move_d8_dest (a5)+,d,af,iap + ii_move_d8_dest (a6)+,d,cf,iap + ii_move_d8_dest usp,id,ef,iap +// move.x d8(ax/pc,dy),-(az) + ii_move_d8_dest a0_off(a7),id,13,iam + ii_move_d8_dest a1_off(a7),id,33,iam + ii_move_d8_dest -(a2),d,53,iam + ii_move_d8_dest -(a3),d,73,iam + ii_move_d8_dest -(a4),d,93,iam + ii_move_d8_dest -(a5),d,b3,iam + ii_move_d8_dest -(a6),d,d3,iam + ii_move_d8_dest usp,id,f3,iam +.endm //end function +//==================================================================== +// subs ---------------------------------------------------------- +//==================================================================== +// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size +ii_move_d16ax_xxx:.macro +ii_0x1\1: //byt: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.b (a1),d0 + move.\3 (a0)+,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\1: //long: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.l (a1),d0 + move.\3 (a0)+,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x3\1: //word: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.w (a1),d0 + move.\3 (a0)+,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +//---------------------------------------- +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) +ii_move_xxx_d16ax:.macro //1=code 2=adress register +ii_0x1\178: //byt xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\179: //byt xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\17c: //byt #x +#ifdef halten_move + halt +#endif + mvs.b (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\178: //long xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\179: //long xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\17c: //long #x +#ifdef halten_move + halt +#endif + move.l (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end + ii_end +ii_0x3\178: //word xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\179: //word xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\17c: //word #x +#ifdef halten_move + halt +#endif + move.w (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +// move.x xxx,xxx +ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code +ii_0x\4: +#ifdef halten_move + halt +#endif + move.\2 (a0)+,a1 + move.\1 (a1),d0 + move.\3 (a0)+,d1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +// move.x im,xxx +ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code +ii_0x\3: +#ifdef halten_move + halt +#endif +.ifc 1,b + move.w (a0)+,d0 +.else + move.\1 (a0)+,d0 +.endif + move.\2 (a0)+,a1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// ea=dx,ax,(ax),(ax)+,-(ax) +//--------------------------------------------------------------------- +ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) +.ifc \3,id + ii_move_dxxi b,\1+3,1,\2,\3,\5 + ii_move_dxxi w,\1+2,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 +.else + .ifc \4,da + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .else + ii_move_dxxi b,\1,1,\2,\3,\5 + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .endif +.endif +.endm + +ii_move_dxxi:.macro +ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + move_end \1,\2,\5 +ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + move_end \1,\2,\5 +ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a2,a1 + move_end \1,\2,\5 +ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a3,a1 + move_end \1,\2,\5 +ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a4,a1 + move_end \1,\2,\5 +ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a5,a1 + move_end \1,\2,\5 +ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a6,a1 + move_end \1,\2,\5 +ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l usp,a1 + move_end \1,\2,\5 +ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0,a1 + move_end \1,\2,\5 +.endm +//------------------------------------ +move_end:.macro + jsr ewf +.ifc 3,a7 + move.l a7,d1 // a7 sichern + move.l usp,a7 // a7 holen +.endif +.ifc 3,ia + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2),(a1) + move.l d1,a2 // a2 zurück +.else + .ifc 3,iap + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2)+,(a1) + .else + .ifc 3,iam + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 -(a2),(a1) + .else + move.\1 \2,(a1) + .endif + .endif +.endif +.ifc 3,a7 + movea.l a7,usp // a7 zurück + movea.l d1,a7 // a7 setzen +.endif + set_cc0 +.ifc 3,iap + move.l d1,a2 // a2 zurück +.endif +.ifc 3,iam + move.l d1,a2 // a2 zurück +.endif + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) +//--------------------------------------------------------------------- + +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea --------------------------------------------- +//--------------------------------------------------------------------- +ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse +//byt +ii_0x1\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//long +ii_0x2\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movel_a1_src\4 \1,\2 +ii_0x2\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movel_a1_src\4 \1,\2 +ii_0x2\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movel_a1_src\4 \1,\2 +ii_0x2\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movel_a1_src\4 \1,\2 +ii_0x2\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movel_a1_src\4 \1,\2 +ii_0x2\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movel_a1_src\4 \1,\2 +ii_0x2\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//word +ii_0x3\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movew_a1_src\4 \1,\2 +ii_0x3\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movew_a1_src\4 \1,\2 +ii_0x3\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movew_a1_src\4 \1,\2 +ii_0x3\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movew_a1_src\4 \1,\2 +ii_0x3\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movew_a1_src\4 \1,\2 +ii_0x3\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movew_a1_src\4 \1,\2 +ii_0x3\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +.endm +//--------------------------------------------------------------------- +//dx +moveb_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.b (a1),\1_off+3(a7) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.l (a1),\1_off(a7) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.w (a1),\1_off+2(a7) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// ax +moveb_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.l (a1),a1 + move.l a1,usp + .else + move.l (a1),\1_off(a7) + .endif +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax) +moveb_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax)+ +moveb_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1)+ + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1)+ + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1)+ + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// -(ax) +moveb_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,-(a1) + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,-(a1) + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,-(a1) + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm + +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea +//--------------------------------------------------------------------- + + + +/*============================================================ +// move.w dx,(a0,dx.w*SF) + ii_lset 0x3180 + ii_lset 0x3181 + ii_lset 0x3182 + ii_lset 0x3183 + ii_lset 0x3184 + ii_lset 0x3185 + ii_lset 0x3186 + ii_lset 0x3187 + +//-------------------------------------------------------------------- +// // move.w dx,d(ay,dz.w*sf) +//-------------------------------------------------------------------- +movew_ewfw:.macro + move.l \2,a1 + jsr ewf + move.w \1,(a1) + set_cc0 + ii_end + .endm +ii_0x3180: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3181: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3182: + movew_ewfw d2,a0_off(a7) +ii_0x3183: + movew_ewfw d3,a0_off(a7) +ii_0x3184: + movew_ewfw d4,a0_off(a7) +ii_0x3185: + movew_ewfw d5,a0_off(a7) +ii_0x3186: + movew_ewfw d6,a0_off(a7) +ii_0x3187: + movew_ewfw d7,a0_off(a7) diff --git a/BaS_codewarrior/firebeeV1/sources/ii_movem.h b/BaS_codewarrior/firebeeV1/sources/ii_movem.h new file mode 100644 index 0000000..5e8a470 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_movem.h @@ -0,0 +1,374 @@ +//***********************************************************************************/ +// movem +//***********************************************************************************/ +ii_movem_lset: .macro +// movem.l rx,xxx.L + ii_lset 0x48f9 +// movem.l xxx.L,rx + ii_lset 0x4cf9 +// movem.w rx,xxx.L + ii_lset 0x48b9 +// movem.w xxx.L,rx + ii_lset 0x4cb9 +// movem.l rx,-(ax) + ii_lset 0x48e0 + ii_lset 0x48e1 + ii_lset 0x48e2 + ii_lset 0x48e3 + ii_lset 0x48e4 + ii_lset 0x48e5 + ii_lset 0x48e6 + ii_lset 0x48e7 +// movem.l (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +.endm +//***********************************************************************************/ +ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//------------------------------------------------------------------------------- +ii_0x48e0: // movem.l reglist,-(a0) + mvm_mem_macro 0x48d0,a0_off(a7),2 +ii_0x48e1: // movem.l reglist,-(a1) + mvm_mem_macro 0x48d1,a1_off(a7),2 +ii_0x48e2: // movem.l reglist,-(a2) + mvm_mem_macro 0x48d2,a2,2 +ii_0x48e3: // movem.l reglist,-(a3) + mvm_mem_macro 0x48d3,a3,2 +ii_0x48e4: // movem.l reglist,-(a4) + mvm_mem_macro 0x48d4,a4,2 +ii_0x48e5: // movem.l reglist,-(a5) + mvm_mem_macro 0x48d5,a5,2 +ii_0x48e6: // movem.l reglist,-(a6) + mvm_mem_macro 0x48d6,a6,2 +ii_0x48e7: // movem.l reglist,-(a7) + mvm_mem_macro 0x48d7,usp,2 +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_reg_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_reg_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_reg_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_reg_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_reg_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_reg_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_reg_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_reg_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro l +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro l +//---------------------------------------------------------------------------- +ii_0x48b9: // movem.w reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro w +//--------------------------------------------------------------------------------------------- +ii_0x4cb9: // movem.w xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro w +.endm +//============================================================== +mvm_mem_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lsl.l #\3,d1 // * anzahl byts pro wert + move.l \2,a1 + sub.l d1,a1 // ax-anzahl byts + move.l a1,\2 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x reg_list,-(a7) + move.w (a0)+,(a1)+ // register list + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +mvm_reg_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mrm_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7\@ // -> +mrm_dx\@: + lsr.l #1,d0 + bcc mmrm_nd0\@ +.ifc 1,l + move.l d0_off(a7),(a1)+ +.else + move.w d0_off+2(a7),(a1)+ +.endif +mmrm_nd0\@: + lsr.l #1,d0 + bcc mmrm_nd1\@ +.ifc 1,l + move.l d1_off(a7),(a1)+ +.else + move.w d1_off+2(a7),(a1)+ +.endif +mmrm_nd1\@: + lsr.l #1,d0 + bcc mmrm_nd2\@ + move.\1 d2,(a1)+ +mmrm_nd2\@: + lsr.l #1,d0 + bcc mmrm_nd3\@ + move.\1 d3,(a1)+ +mmrm_nd3\@: + lsr.l #1,d0 + bcc mmrm_nd4\@ + move.\1 d4,(a1)+ +mmrm_nd4\@: + lsr.l #1,d0 + bcc mmrm_nd5\@ + move.\1 d5,(a1)+ +mmrm_nd5\@: + lsr.l #1,d0 + bcc mmrm_nd6\@ + move.l d6,(a1)+ +mmrm_nd6\@: + lsr.l #1,d0 + bcc mmrm_nd7\@ + move.\1 d7,(a1)+ +mmrm_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7\@ + lsr.l #1,d0 + bcc mmrm_na0\@ +.ifc 1,l + move.l a0_off(a7),(a1)+ +.else + move.w a0_off+2(a7),(a1)+ +.endif +mmrm_na0\@: + lsr.l #1,d0 + bcc mmrm_na1\@ +.ifc 1,l + move.l a1_off(a7),(a1)+ +.else + move.w a1_off+2(a7),(a1)+ +.endif +mmrm_na1\@: + lsr.l #1,d0 + bcc mmrm_na2\@ + move.\1 a2,(a1)+ +mmrm_na2\@: + lsr.l #1,d0 + bcc mmrm_na3\@ + move.\1 a3,(a1)+ +mmrm_na3\@: + lsr.l #1,d0 + bcc mmrm_na4\@ + move.\1 a4,(a1)+ +mmrm_na4\@: + lsr.l #1,d0 + bcc mmrm_na5\@ + move.\1 a5,(a1)+ +mmrm_na5\@: + lsr.l #1,d0 + bcc mmrm_na6\@ + move.\1 a6,(a1)+ +mmrm_na6\@: + lsr.l #1,d0 + bcc mmrm_na7\@ + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.\1 a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7\@: + ii_end + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mmr_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7\@ // -> +mmr_dx\@: + lsr.l #1,d0 + bcc mmmr_nd0\@ +.ifc 1,l + move.l (a1)+,d0_off(a7) +.else + move.w (a1)+,d0_off+2(a7) +.endif +mmmr_nd0\@: + lsr.l #1,d0 + bcc mmmr_nd1\@ +.ifc 1,l + move.l (a1)+,d1_off(a7) +.else + move.w (a1)+,d1_off+2(a7) +.endif +mmmr_nd1\@: + lsr.l #1,d0 + bcc mmmr_nd2\@ + move.\1 (a1)+,d2 +mmmr_nd2\@: + lsr.l #1,d0 + bcc mmmr_nd3\@ + move.\1 (a1)+,d3 +mmmr_nd3\@: + lsr.l #1,d0 + bcc mmmr_nd4\@ + move.\1 (a1)+,d4 +mmmr_nd4\@: + lsr.l #1,d0 + bcc mmmr_nd5\@ + move.\1 (a1)+,d5 +mmmr_nd5\@: + lsr.l #1,d0 + bcc mmmr_nd6\@ + move.\1 (a1)+,d6 +mmmr_nd6\@: + lsr.l #1,d0 + bcc mmmr_nd7\@ + move.\1 (a1)+,d7 +mmmr_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7\@ // nein-> + lsr.l #1,d0 + bcc mmmr_na0\@ +.ifc 1,l + move.l (a1)+,a0_off(a7) +.else + move.w (a1)+,a0_off+2(a7) +.endif +mmmr_na0\@: + lsr.l #1,d0 + bcc mmmr_na1\@ +.ifc 1,l + move.l (a1)+,a1_off(a7) +.else + move.w (a1)+,a1_off+2(a7) +.endif +mmmr_na1\@: + lsr.l #1,d0 + bcc mmmr_na2\@ + move.\1 (a1)+,a2 +mmmr_na2\@: + lsr.l #1,d0 + bcc mmmr_na3\@ + move.\1 (a1)+,a3 +mmmr_na3\@: + lsr.l #1,d0 + bcc mmmr_na4\@ + move.\1 (a1)+,a4 +mmmr_na4\@: + lsr.l #1,d0 + bcc mmmr_na5\@ + move.\1 (a1)+,a5 +mmmr_na5\@: + lsr.l #1,d0 + bcc mmmr_na6\@ + move.\1 (a1)+,a6 +mmmr_na6\@: + lsr.l #1,d0 + bcc mmmr_na7\@ + move.\1 (a1)+,a1 // nach a0 + move.l a1,usp // war ja usp +mmmr_na7\@: + ii_end + .endm diff --git a/BaS_codewarrior/firebeeV1/sources/ii_movep.h b/BaS_codewarrior/firebeeV1/sources/ii_movep.h new file mode 100644 index 0000000..830fdf7 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_movep.h @@ -0,0 +1,179 @@ +//-------------------------------------------------------------------- +// movep +//-------------------------------------------------------------------- +.text +ii_movep_lset:.macro + ii_lset_opeau 01,0 //movep.w d(a0-7),d0 + ii_lset_opeau 03,0 //movep.w d(a0-7),d1 + ii_lset_opeau 05,0 //movep.w d(a0-7),d2 + ii_lset_opeau 07,0 //movep.w d(a0-7),d3 + ii_lset_opeau 09,0 //movep.w d(a0-7),d4 + ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 + ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 + ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 + + ii_lset_opeau 01,4 //movep.w d0,d(a0-7) + ii_lset_opeau 03,4 //movep.w d1,d(a0-7) + ii_lset_opeau 05,4 //movep.w d2,d(a0-7) + ii_lset_opeau 07,4 //movep.w d3,d(a0-7) + ii_lset_opeau 09,4 //movep.w d4,d(a0-7) + ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) + ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) + ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) + + ii_lset_opeau 01,8 //movep.l d(a0-7),d0 + ii_lset_opeau 03,8 //movep.l d(a0-7),d1 + ii_lset_opeau 05,8 //movep.l d(a0-7),d2 + ii_lset_opeau 07,8 //movep.l d(a0-7),d3 + ii_lset_opeau 09,8 //movep.l d(a0-7),d4 + ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 + ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 + ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 + + ii_lset_opeau 01,c //movep.l d0,d(a0-7) + ii_lset_opeau 03,c //movep.l d1,d(a0-7) + ii_lset_opeau 05,c //movep.l d2,d(a0-7) + ii_lset_opeau 07,c //movep.l d3,d(a0-7) + ii_lset_opeau 09,c //movep.l d4,d(a0-7) + ii_lset_opeau 0b,c //movep.l d5,d(a0-7) + ii_lset_opeau 0d,c //movep.l d6,d(a0-7) + ii_lset_opeau 0f,c //movep.l d7,d(a0-7) +.endm +//--------------------------------------------------------------------------------------------- +ii_movep_func:.macro +//movep.w d(a0-7),d0-7 + ii_movep 010,d0_off(a7),wad + ii_movep 030,d1_off(a7),wad + ii_movep 050,d2,wad + ii_movep 070,d3,wad + ii_movep 090,d4,wad + ii_movep 0b0,d5,wad + ii_movep 0d0,d6,wad + ii_movep 0f0,d7,wad +//movep.w d0-7,d(a0-7) + ii_movep 014,d0_off(a7),wda + ii_movep 034,d1_off(a7),wda + ii_movep 054,d2,wda + ii_movep 074,d3,wda + ii_movep 094,d4,wda + ii_movep 0b4,d5,wda + ii_movep 0d4,d6,wda + ii_movep 0f4,d7,wda +//movep.l d(a0-7),d0-7 + ii_movep 018,d0_off(a7),lad + ii_movep 038,d1_off(a7),lad + ii_movep 058,d2,lad + ii_movep 078,d3,lad + ii_movep 098,d4,lad + ii_movep 0b8,d5,lad + ii_movep 0d8,d6,lad + ii_movep 0f8,d7,lad +//movep.l d0-7,d(a0-7) + ii_movep 01c,d0_off(a7),lda + ii_movep 03c,d1_off(a7),lda + ii_movep 05c,d2,lda + ii_movep 07c,d3,lda + ii_movep 09c,d4,lda + ii_movep 0bc,d5,lda + ii_movep 0dc,d6,lda + ii_movep 0fc,d7,lda +.endm +//--------------------------------------------------------------------------------------------- +ii_movep:.macro //1=code ziffer 1-3 2=register 3=art +ii_0x\18: +#ifdef halten_movep + halt +#endif + move.l a0_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\19: +#ifdef halten_movep + halt +#endif + move.l a1_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\1a: +#ifdef halten_movep + halt +#endif + move.l a2,a1 + ii_movep\3_up1 \2 +ii_0x\1b: +#ifdef halten_movep + halt +#endif + move.l a3,a1 + ii_movep\3_up1 \2 +ii_0x\1c: +#ifdef halten_movep + halt +#endif + move.l a4,a1 + ii_movep\3_up1 \2 +ii_0x\1d: +#ifdef halten_movep + halt +#endif + move.l a5,a1 + ii_movep\3_up1 \2 +ii_0x\1e: +#ifdef halten_movep + halt +#endif + move.l a6,a1 + ii_movep\3_up1 \2 +ii_0x\1f: +#ifdef halten_movep + halt +#endif + move.l usp,a1 + ii_movep\3_up1 \2 +.endm + +ii_movepwad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1,d1.l),d0 + move.w d0,\1 + ii_end +.endm + +ii_movepwda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.w \1,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm + +ii_moveplad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1),d0 + lsl.l #8,d0 + move.b 4(a1),d0 + lsl.l #8,d0 + move.b 6(a1),d0 + move.l d0,\1 + ii_end +.endm + +ii_moveplda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.l \1,d0 + move.b d0,6(a1) + lsr.l #8,d0 + move.b d0,4(a1) + lsr.l #8,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm diff --git a/BaS_codewarrior/firebeeV1/sources/ii_op.h b/BaS_codewarrior/firebeeV1/sources/ii_op.h new file mode 100644 index 0000000..a3fc0cf --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_op.h @@ -0,0 +1,661 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_op:.macro +//byt + ii_lset_opea \1,0 // dx,ax + ii_lset_opea \1,1 // (ax), (ax)+ + ii_lset_opea \1,2 // -(ax),d16(ax) + ii_lset_opeag \1,3 // d8(ax,dy) + lea table+0x\1\238*4,a0 + move.l #ii_0x\138,(a0)+ // xxx.w + move.l #ii_0x\139,(a0)+ // xxx.l +//word + ii_lset_opea \1,4 // dx,ax + ii_lset_opea \1,5 // (ax), (ax)+ + ii_lset_opea \1,6 // -(ax),d16(ax) + ii_lset_opeag \1,7 // d8(ax,dy) + lea table+0x\178*4,a0 + move.l #ii_0x\178,(a0)+ // xxx.w + move.l #ii_0x\179,(a0)+ // xxx.l +//long + ii_lset_opea \1,8 // dx,ax + ii_lset_opea \1,9 // (ax), (ax)+ + ii_lset_opea \1,a // -(ax),d16(ax) + ii_lset_opeag \1,b // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +ii_lset_opeag:.macro // 0x1120-0x1127 + lea table+0x\1\20*4,a0 + move.l #ii_0x\1\20,(a0)+ + move.l #ii_0x\1\21,(a0)+ + move.l #ii_0x\1\22,(a0)+ + move.l #ii_0x\1\23,(a0)+ + move.l #ii_0x\1\24,(a0)+ + move.l #ii_0x\1\25,(a0)+ + move.l #ii_0x\1\26,(a0)+ + move.l #ii_0x\1\27,(a0)+ + .endm; + +ii_lset_opeau:.macro // 0x1128-0x112f + lea table+0x\1\28*4,a0 + move.l #ii_0x\1\28,(a0)+ + move.l #ii_0x\1\29,(a0)+ + move.l #ii_0x\1\2a,(a0)+ + move.l #ii_0x\1\2b,(a0)+ + move.l #ii_0x\1\2c,(a0)+ + move.l #ii_0x\1\2d,(a0)+ + move.l #ii_0x\1\2e,(a0)+ + move.l #ii_0x\1\2f,(a0)+ + .endm; + +ii_lset_opea:.macro + ii_lset_opeag \1,\2 + ii_lset_opeau \1,\2 + .endm +/******************************************************/ +ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick +// byt + opdx \1,\2,b,0,\3 // dx,ax + opia \1,\2,b,1,\3 // (ax),(ax)+ + opdia \1,\2,b,2,\3 // -(ax),d16(ax) + opd8a \1,\2,b,3,\3 // d8(ax),xxx +// word + opdx \1,\2,w,4,\3 // dx,ax + opia \1,\2,w,5,\3 // (ax),(ax)+ + opdia \1,\2,w,6,\3 // -(ax),d16(ax) + opd8a \1,\2,w,7,\3 // d8(ax),xxx +// long + opdx \1,\2,l,8,\3 // dx,ax + opia \1,\2,l,9,\3 // (ax),(ax)+ + opdia \1,\2,l,a,\3 // -(ax),d16(ax) + opd8a \1,\2,l,b,\3 // d8(ax),xxx + .endm +/******************************************************/ +// byt word long +/******************************************************/ +opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +//ax +ii_0x\1\48: + opa\5smd \2,a0_off(a7),a0_off(a7),\3 +ii_0x\1\49: + opa\5smd \2,a1_off(a7),a1_off(a7),\3 +ii_0x\1\4a: + opa\5smd \2,a2,a2,\3 +ii_0x\1\4b: + opa\5smd \2,a3,a3,\3 +ii_0x\1\4c: + opa\5smd \2,a4,a4,\3 +ii_0x\1\4d: + opa\5smd \2,a5,a5,\3 +ii_0x\1\4e: + opa\5smd \2,a6,a6,\3 +ii_0x\1\4f: + opa\5smd \2,usp,usp,\3 +.endm; +//----------------------------------------------- +opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +//(ax) +ii_0x\1\40: + op\5sia \2,a0_off(a7),(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,(a1),(a1),\3 +//(ax)+ +ii_0x\1\48: + op\5sia \2,a0_off(a7),(a1),(a1)+,\3 +ii_0x\1\49: + op\5sia \2,a1_off(a7),(a1),(a1)+,\3 +ii_0x\1\4a: + op\5smd \2,(a2),(a2)+,\3 +ii_0x\1\4b: + op\5smd \2,(a3),(a3)+,\3 +ii_0x\1\4c: + op\5smd \2,(a4),(a4)+,\3 +ii_0x\1\4d: + op\5smd \2,(a5),(a5)+,\3 +ii_0x\1\4e: + op\5smd \2,(a6),(a6)+,\3 +ii_0x\1\4f: + op\5sia \2,usp,(a1),(a1)+,\3 +.endm; +//----------------------------------------------- +opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sia \2,a0_off(a7),-(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),-(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,-(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,-(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,-(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,-(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,-(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,-(a1),(a1),\3 + +ii_0x\1\48: + op\5sd16a \2,a0_off(a7),\3 +ii_0x\1\49: + op\5sd16a \2,a1_off(a7),\3 +ii_0x\1\4a: + op\5sd16a \2,a2,\3 +ii_0x\1\4b: + op\5sd16a \2,a3,\3 +ii_0x\1\4c: + op\5sd16a \2,a4,\3 +ii_0x\1\4d: + op\5sd16a \2,a5,\3 +ii_0x\1\4e: + op\5sd16a \2,a6,\3 +ii_0x\1\4f: + op\5sd16a \2,usp,\3 +.endm; +//----------------------------------------------- +opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sd8a \2,a0_off(a7),\3 +ii_0x\1\41: + op\5sd8a \2,a1_off(a7),\3 +ii_0x\1\42: + op\5sd8a \2,a2,\3 +ii_0x\1\43: + op\5sd8a \2,a3,\3 +ii_0x\1\44: + op\5sd8a \2,a4,\3 +ii_0x\1\45: + op\5sd8a \2,a5,\3 +ii_0x\1\46: + op\5sd8a \2,a6,\3 +ii_0x\1\47: + op\5sd8a \2,usp,\3 + +ii_0x\1\48: + op\5sxx \2,\3,w +ii_0x\1\49: + op\5sxx \2,\3,l +.endm; +//----------------------------------------------- +opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end +.endm; + +opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse +#ifdef halten_op + halt +#endif + +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + move.\3 (a0)+,a1 + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; +//*******************************************************************************3 +opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\4 d1,\3 +.endif + ii_end +.endm; + +opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d0,d1 +.ifnc \1,cmp.l +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif +.endif + ii_end +.endm; + +opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + +.ifc \5,l + move.l (a0)+,d0 +.else + .ifc \5,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\5 d1,\4 +.endif + ii_end +.endm; + +opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\2 d1,(a1) +.endif + ii_end + .endm; +//*******************************************************************************3 +opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 ,d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse +#ifdef halten_op + halt +#endif + + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_codewarrior/firebeeV1/sources/ii_opc.h b/BaS_codewarrior/firebeeV1/sources/ii_opc.h new file mode 100644 index 0000000..8b887ce --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_opc.h @@ -0,0 +1,263 @@ +/*****************************************************************************************/ +// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax +// zusammen mit op.h +/*****************************************************************************************/ +ii_lset_opc:.macro + ii_lset_opeag \1,c // dx,ax + ii_lset_opea \1,d // (ax), (ax)+ + ii_lset_opea \1,e // -(ax),d16(ax) + ii_lset_opeag \1,f // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +/******************************************************/ +ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat + opcdx \1,\2,l,c,\3 // dx,ax + opia \1,\2,l,d,\3 // (ax),(ax)+ + opdia \1,\2,l,e,\3 // -(ax),d16(ax) + opd8a \1,\2,l,f,\3 // d8(ax),xxx + .endm +//*******************************************************************************3 +/******************************************************/ +// byt word long +/******************************************************/ +opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: +#ifdef halten_opc + halt +#endif + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +.endm +//----------------------------------------------------- +opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 + set_cc0 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse +#ifdef halten_opc + halt +#endif + +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_codewarrior/firebeeV1/sources/ii_or.h b/BaS_codewarrior/firebeeV1/sources/ii_or.h new file mode 100644 index 0000000..dfe4450 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_or.h @@ -0,0 +1,442 @@ +//-------------------------------------------------------------------- +// or +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// or.b #im,dx +//-------------------------------------------------------------------- +orbir_macro:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + or.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea,dx +//-------------------------------------------------------------------- +ordd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +orddd:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +ordda:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +orddai:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,-(ay),dx +//-------------------------------------------------------------------- +orddad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(ay),dx +//-------------------------------------------------------------------- +ord16ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(ay,dy),dx +//-------------------------------------------------------------------- +ord8ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.w,dx +//-------------------------------------------------------------------- +orxwd:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.l,dx +//-------------------------------------------------------------------- +orxld:.macro +#ifdef halten_or + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(pc),dx +//-------------------------------------------------------------------- +ord16pcd:.macro + halt + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(pc,dy),dx +//-------------------------------------------------------------------- +ord8pcd:.macro +#ifdef halten_or + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// or dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +oreda:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredai:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredaid:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredadd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,d16(ay) +//-------------------------------------------------------------------- +ore16ad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ore8ad:.macro +#ifdef halten_or + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.w +//-------------------------------------------------------------------- +orxwe:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.l +//-------------------------------------------------------------------- +orxle:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // ora.w ea,ax +//-------------------------------------------------------------------- +oraw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// or.w ea,usp +//-------------------------------------------------------------------- +orawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,ax +//-------------------------------------------------------------------- +orawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,usp +//-------------------------------------------------------------------- +orawua7:.macro + orawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(ay),ax +//-------------------------------------------------------------------- +orawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(ay,dy),ax +//-------------------------------------------------------------------- +orawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.w,ax +//-------------------------------------------------------------------- +orawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.l,ax +//-------------------------------------------------------------------- +orawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(pc),ax +//-------------------------------------------------------------------- +orawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(pc,dy),ax +//-------------------------------------------------------------------- +orawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w #im,ax +//-------------------------------------------------------------------- +orawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(ay,dy),ax +//-------------------------------------------------------------------- +orald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(pc,dy),ax +//-------------------------------------------------------------------- +orald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +ordx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +ordax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_codewarrior/firebeeV1/sources/ii_pea.h b/BaS_codewarrior/firebeeV1/sources/ii_pea.h new file mode 100644 index 0000000..69f69d0 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_pea.h @@ -0,0 +1,74 @@ +//-------------------------------------------------------------------- +// pea +//-------------------------------------------------------------------- +.text +ii_pea_lset:.macro + ii_lset_opeag 48,7 + ii_lset 0x487b +.endm +//--------------------------------------------------------------------------------------------- +ii_pea_func:.macro +ii_0x4870: +#ifdef halten_pea + halt +#endif + move.l a0_off(a7),a1 + pea_macro +ii_0x4871: +#ifdef halten_pea + halt +#endif + move.l a1_off(a7),a1 + pea_macro +ii_0x4872: +#ifdef halten_pea + halt +#endif + move.l a2,a1 + pea_macro +ii_0x4873: +#ifdef halten_pea + halt +#endif + move.l a3,a1 + pea_macro +ii_0x4874: +#ifdef halten_pea + halt +#endif + move.l a4,a1 + pea_macro +ii_0x4875: +#ifdef halten_pea + halt +#endif + move.l a5,a1 + pea_macro +ii_0x4876: +#ifdef halten_pea + halt +#endif + move.l a6,a1 + pea_macro +ii_0x4877: +#ifdef halten_pea + halt +#endif + move.l usp,a1 + pea_macro +ii_0x487b: +#ifdef halten_pea + halt +#endif + move.l a0,a1 + pea_macro +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/ii_shd.h b/BaS_codewarrior/firebeeV1/sources/ii_shd.h new file mode 100644 index 0000000..ecace29 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_shd.h @@ -0,0 +1,247 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_shd:.macro + ii_lset_shdx e0 //r d0 + ii_lset_shdx e2 //r d1 + ii_lset_shdx e4 //r d2 + ii_lset_shdx e6 //r d3 + ii_lset_shdx e8 //r d4 + ii_lset_shdx ea //r d5 + ii_lset_shdx ec //r d6 + ii_lset_shdx ee //r d7 + + ii_lset_shdx e1 //l d0 + ii_lset_shdx e3 //l d1 + ii_lset_shdx e4 //l d2 + ii_lset_shdx e5 //l d3 + ii_lset_shdx e9 //l d4 + ii_lset_shdx eb //l d5 + ii_lset_shdx ed //l d6 + ii_lset_shdx ef //l d7 + .endm + +ii_lset_shdx:.macro +//byt + ii_lset_opea \1,0 // as,ls #im,dx + ii_lset_opea \1,1 // rox,ro #im,dx + ii_lset_opea \1,2 // as,ls dy,dx + ii_lset_opea \1,3 // rox,ro dy,dx +//word + ii_lset_opea \1,4 // as,ls #im,dx + ii_lset_opea \1,5 // rox,ro #im,dx + ii_lset_opea \1,6 // as,ls dy,dx + ii_lset_opea \1,7 // rox,ro dy,dx +//long +// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden + ii_lset_opea \1,9 // rox,ro #im,dx +// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden + ii_lset_opea \1,b // rox,ro dy,dx + .endm +/******************************************************/ +ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat +// byt + opdx \1,\2,b,0,\3 // dx +// word + opdx \1,\2,w,4,\3 // dx +// long + opdx \1,\2,l,8,\3 // dx + .endm +/******************************************************/ +// byt word long routinen +/******************************************************/ +sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvs.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_shal:.macro + move.w \3,d0 + \1.l d0,d1 + set_cc0 + move.\4 d1,\2 + .endm + +sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 +.ifc \4,b + byterev.l d1 +.else + swap.w d1 +.endif + sh_asr \1,\2,\3,\4 + .endm + +sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 / + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsr.l d0,d1 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + .else + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + move.w ccr,d0 + and.l #1,d1 // ist auch carry bit + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsl.l d0,d1 + lsr.l #8,d1 + moveq #7,d0 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + swap.w d1 + moveq #15,d0 + .else + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + moveq #31,d0 + .endif +.endif + move.\4 d1,\2 + lsr.l d0,d1 // carry bit schieben + move.w ccr,d0 + and.l #1,d1 + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + move.w \3,d0 + and.l #0x7,d0 + lsr.l d0,d1 + set_cc0 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #8,d1 + move.w \2,d1 + move.w \3,d0 + and.l #0xf,d0 + lsr.l d0,d1 + set_cc0 + .else + bitrev.l d0 + move.l \2,d1 + lsr.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + +sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + lsl.l #8,d1 + lsl.l #7,d1 + move.w \3,d0 + and.l #0x7,d0 + lsl.l d0,d1 + set_cc0 + byterev.l d1 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #7,d1 + mvz.w \2,d0 + lsr.l #1,d0 + add.l d0,d1 + move.w \3,d0 + and.l #0xf,d0 + lsl.l d0,d1 + set_cc0 + swap.w d1 + .else + move.l \2,d1 + lsl.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + + \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/ii_shift.h b/BaS_codewarrior/firebeeV1/sources/ii_shift.h new file mode 100644 index 0000000..f83bfcb --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_shift.h @@ -0,0 +1,687 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_shift_lset:.macro +/******************************************************/ +// byt +/******************************************************/ +// asx.b #,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// lsx.b #,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// roxx.b #,dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// rox.b #,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// asx.b dy,dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// lsx.b dy,dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// roxx.dy,dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// rox.b dy,dx + ii_lset_dx \1,38 + ii_lset_dx \1,39 + ii_lset_dx \1,3a + ii_lset_dx \1,3b + ii_lset_dx \1,3c + ii_lset_dx \1,3d + ii_lset_dx \1,3e + ii_lset_dx \1,3f +/******************************************************/ +// word +/******************************************************/ +// asx.w #x,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// lsx.w #,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// roxx.w #,dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// rox.w #xdx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// asx.w dy,dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// lsx.w dy,dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// roxx.w dy,dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// rox.w dy,dx + ii_lset_dx \1,78 + ii_lset_dx \1,79 + ii_lset_dx \1,7a + ii_lset_dx \1,7b + ii_lset_dx \1,7c + ii_lset_dx \1,7d + ii_lset_dx \1,7e + ii_lset_dx \1,7f +/******************************************************/ +// long +/******************************************************/ +// roxx.l #,dx + ii_lset_dx \1,90 + ii_lset_dx \1,91 + ii_lset_dx \1,92 + ii_lset_dx \1,93 + ii_lset_dx \1,94 + ii_lset_dx \1,95 + ii_lset_dx \1,96 + ii_lset_dx \1,97 +// rox.l #xdx + ii_lset_dx \1,98 + ii_lset_dx \1,99 + ii_lset_dx \1,9a + ii_lset_dx \1,9b + ii_lset_dx \1,9c + ii_lset_dx \1,9d + ii_lset_dx \1,9e + ii_lset_dx \1,9f +// roxx.l dy,dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// rox.l dy,dx + ii_lset_dx \1,b8 + ii_lset_dx \1,b9 + ii_lset_dx \1,ba + ii_lset_dx \1,bb + ii_lset_dx \1,bc + ii_lset_dx \1,bd + ii_lset_dx \1,be + ii_lset_dx \1,bf +//-------------------------------------------------------------------- +// asr.w ea + ii_lset_opea \10,d // (ax), (ax)+ + ii_lset_opea \10,e // -(ax),d16(ax) + ii_lset_opeag \10,f // d8(ax,dy) + lea table+0x\10\2f8*4,a0 + move.l #ii_0x\10f8,(a0)+ // xxx.w + move.l #ii_0x\10f9,(a0)+ // xxx.l +// asl.w ea + ii_lset_opea \11,d // (ax), (ax)+ + ii_lset_opea \11,e // -(ax),d16(ax) + ii_lset_opeag \11,f // d8(ax,dy) + lea table+0x\11\2f8*4,a0 + move.l #ii_0x\11f8,(a0)+ // xxx.w + move.l #ii_0x\11f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \12,d // (ax), (ax)+ + ii_lset_opea \12,e // -(ax),d16(ax) + ii_lset_opeag \12,f // d8(ax,dy) + lea table+0x\12\2f8*4,a0 + move.l #ii_0x\12f8,(a0)+ // xxx.w + move.l #ii_0x\12f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \13,d // (ax), (ax)+ + ii_lset_opea \13,e // -(ax),d16(ax) + ii_lset_opeag \13,f // d8(ax,dy) + lea table+0x\13\2f8*4,a0 + move.l #ii_0x\13f8,(a0)+ // xxx.w + move.l #ii_0x\13f9,(a0)+ // xxx.l +// roxr.w ea + ii_lset_opea \14,d // (ax), (ax)+ + ii_lset_opea \14,e // -(ax),d16(ax) + ii_lset_opeag \14,f // d8(ax,dy) + lea table+0x\14\2f8*4,a0 + move.l #ii_0x\14f8,(a0)+ // xxx.w + move.l #ii_0x\14f9,(a0)+ // xxx.l +// roxl.w ea + ii_lset_opea \15,e // (ax), (ax)+ + ii_lset_opea \15,e // -(ax),d16(ax) + ii_lset_opeag \15,f // d8(ax,dy) + lea table+0x\15\2f8*4,a0 + move.l #ii_0x\15f8,(a0)+ // xxx.w + move.l #ii_0x\15f9,(a0)+ // xxx.l +// ror.w ea + ii_lset_opea \16,d // (ax), (ax)+ + ii_lset_opea \16,e // -(ax),d16(ax) + ii_lset_opeag \16,f // d8(ax,dy) + lea table+0x\16\2f8*4,a0 + move.l #ii_0x\16f8,(a0)+ // xxx.w + move.l #ii_0x\16f9,(a0)+ // xxx.l +// rol.w ea + ii_lset_opea \17,d // (ax), (ax)+ + ii_lset_opea \17,e // -(ax),d16(ax) + ii_lset_opeag \17,f // d8(ax,dy) + lea table+0x\17\2f8*4,a0 + move.l #ii_0x\17f8,(a0)+ // xxx.w + move.l #ii_0x\17f9,(a0)+ // xxx.l +// ende +.endm; +/******************************************************/ +ii_shift_op:.macro // 1=code +//byt------------------------------- +//asx.b #x,dx + ii_shift_op2agb 0,as,a +//lsx.b #x,dx + ii_shift_op2aub 0,ls,a +//roxx.b #x,dx + ii_shift_op2agb 1,rox,a +//rox.b #x,dx + ii_shift_op2aub 1,ro,a +//asx.b dy,dx + ii_shift_op2agb 2,as,b +//lsx.b dy,dx + ii_shift_op2aub 2,ls,b +//roxx.b dy,dx + ii_shift_op2agb 3,rox,b +//rox.b dy,dx + ii_shift_op2aub 3,ro,b +// word --------------------------------------- +//asx.w #x,dx + ii_shift_op2agw 4,as,a +//lsx.w #x,dx + ii_shift_op2auw 4,ls,a +//roxx.w #x,dx + ii_shift_op2agw 5,rox,a +//rox.w #x,dx + ii_shift_op2auw 5,ro,a +//asx.w dy,dx + ii_shift_op2agw 6,as,b +//lsx.w dy,dx + ii_shift_op2auw 6,ls,b +//roxx.w dy,dx + ii_shift_op2agw 7,rox,b +//rox.w dy,dx + ii_shift_op2auw 7,ro,b +// long --------------------------------------- +//roxx.l #x,dx + ii_shift_op2agw 9,rox,a +//rox.l #x,dx + ii_shift_op2auw 9,ro,a +//roxx.l dy,dx + ii_shift_op2agw b,rox,b +//rox.l dy,dx + ii_shift_op2auw b,ro,b +// ea --------------------------------------- +//asr.w #1,ea + ii_shift_op2ea 0,asr +//asl.w #1,ea + ii_shift_op2ea 1,asl +//lsr.w #1,ea + ii_shift_op2ea 2,lsr, +//lsl.w #1,ea + ii_shift_op2ea 3,lsl +//roxr.w #1,ea + ii_shift_op2ea 4,roxr +//roxl.w #1,ea + ii_shift_op2ea 5,roxl +//ror.w #1,ea + ii_shift_op2ea 6,ror +//rol.w #1,ea + ii_shift_op2ea 7,rol +.endm +//byt ============================================ +ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3b \1,0,\2,d0_off+3(a7) + ii_shift_op1\3b \1,1,\2,d1_off+3(a7) + ii_shift_op1\3b \1,2,\2,d2 + ii_shift_op1\3b \1,3,\2,d3 + ii_shift_op1\3b \1,4,\2,d4 + ii_shift_op1\3b \1,5,\2,d5 + ii_shift_op1\3b \1,6,\2,d6 + ii_shift_op1\3b \1,7,\2,d7 +.endm + +ii_shift_op2aub:.macro //byt: 1=code 2=operation + ii_shift_op1\3b \1,8,\2,d0_off+3(a7) + ii_shift_op1\3b \1,9,\2,d1_off+3(a7) + ii_shift_op1\3b \1,a,\2,d2 + ii_shift_op1\3b \1,b,\2,d3 + ii_shift_op1\3b \1,c,\2,d4 + ii_shift_op1\3b \1,d,\2,d5 + ii_shift_op1\3b \1,e,\2,d6 + ii_shift_op1\3b \1,f,\2,d7 +.endm + +ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,b,\3r,#8,\4 + ii_shift_op0 2\1\2,b,\3r,#1,\4 + ii_shift_op0 4\1\2,b,\3r,#2,\4 + ii_shift_op0 6\1\2,b,\3r,#3,\4 + ii_shift_op0 8\1\2,b,\3r,#4,\4 + ii_shift_op0 a\1\2,b,\3r,#5,\4 + ii_shift_op0 c\1\2,b,\3r,#6,\4 + ii_shift_op0 e\1\2,b,\3r,#7,\4 + ii_shift_op0 1\1\2,b,\3l,#8,\4 + ii_shift_op0 3\1\2,b,\3l,#1,\4 + ii_shift_op0 5\1\2,b,\3l,#2,\4 + ii_shift_op0 7\1\2,b,\3l,#3,\4 + ii_shift_op0 9\1\2,b,\3l,#4,\4 + ii_shift_op0 b\1\2,b,\3l,#5,\4 + ii_shift_op0 d\1\2,b,\3l,#6,\4 + ii_shift_op0 f\1\2,b,\3l,#7,\4 +.endm + +ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,b,\3r,d2,\4 + ii_shift_op0 6\1\2,b,\3r,d3,\4 + ii_shift_op0 8\1\2,b,\3r,d4,\4 + ii_shift_op0 a\1\2,b,\3r,d5,\4 + ii_shift_op0 c\1\2,b,\3r,d6,\4 + ii_shift_op0 e\1\2,b,\3r,d7,\4 + ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,b,\3l,d2,\4 + ii_shift_op0 7\1\2,b,\3l,d3,\4 + ii_shift_op0 9\1\2,b,\3l,d4,\4 + ii_shift_op0 b\1\2,b,\3l,d5,\4 + ii_shift_op0 d\1\2,b,\3l,d6,\4 + ii_shift_op0 f\1\2,b,\3l,d7,\4 +.endm +// word --------------------------------------- +ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3w \1,0,\2,d0_off+2(a7) + ii_shift_op1\3w \1,1,\2,d1_off+2(a7) + ii_shift_op1\3w \1,2,\2,d2 + ii_shift_op1\3w \1,3,\2,d3 + ii_shift_op1\3w \1,4,\2,d4 + ii_shift_op1\3w \1,5,\2,d5 + ii_shift_op1\3w \1,6,\2,d6 + ii_shift_op1\3w \1,7,\2,d7 +.endm + +ii_shift_op2auw:.macro //byt: 1=code 2=operation + ii_shift_op1\3w \1,8,\2,d0_off+2(a7) + ii_shift_op1\3w \1,9,\2,d1_off+2(a7) + ii_shift_op1\3w \1,a,\2,d2 + ii_shift_op1\3w \1,b,\2,d3 + ii_shift_op1\3w \1,c,\2,d4 + ii_shift_op1\3w \1,d,\2,d5 + ii_shift_op1\3w \1,e,\2,d6 + ii_shift_op1\3w \1,f,\2,d7 +.endm + +ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,w,\3r,#8,\4 + ii_shift_op0 2\1\2,w,\3r,#1,\4 + ii_shift_op0 4\1\2,w,\3r,#2,\4 + ii_shift_op0 6\1\2,w,\3r,#3,\4 + ii_shift_op0 8\1\2,w,\3r,#4,\4 + ii_shift_op0 a\1\2,w,\3r,#5,\4 + ii_shift_op0 c\1\2,w,\3r,#6,\4 + ii_shift_op0 e\1\2,w,\3r,#7,\4 + ii_shift_op0 1\1\2,w,\3l,#8,\4 + ii_shift_op0 3\1\2,w,\3l,#1,\4 + ii_shift_op0 5\1\2,w,\3l,#2,\4 + ii_shift_op0 7\1\2,w,\3l,#3,\4 + ii_shift_op0 9\1\2,w,\3l,#4,\4 + ii_shift_op0 b\1\2,w,\3l,#5,\4 + ii_shift_op0 d\1\2,w,\3l,#6,\4 + ii_shift_op0 f\1\2,w,\3l,#7,\4 +.endm + +ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,w,\3r,d2,\4 + ii_shift_op0 6\1\2,w,\3r,d3,\4 + ii_shift_op0 8\1\2,w,\3r,d4,\4 + ii_shift_op0 a\1\2,w,\3r,d5,\4 + ii_shift_op0 c\1\2,w,\3r,d6,\4 + ii_shift_op0 e\1\2,w,\3r,d7,\4 + ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,w,\3l,d2,\4 + ii_shift_op0 7\1\2,w,\3l,d3,\4 + ii_shift_op0 9\1\2,w,\3l,d4,\4 + ii_shift_op0 b\1\2,w,\3l,d5,\4 + ii_shift_op0 d\1\2,w,\3l,d6,\4 + ii_shift_op0 f\1\2,w,\3l,d7,\4 +.endm +// long --------------------------------------- +ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3l \1,0,\2,d0_off(a7) + ii_shift_op1\3l \1,1,\2,d1_off(a7) + ii_shift_op1\3l \1,2,\2,d2 + ii_shift_op1\3l \1,3,\2,d3 + ii_shift_op1\3l \1,4,\2,d4 + ii_shift_op1\3l \1,5,\2,d5 + ii_shift_op1\3l \1,6,\2,d6 + ii_shift_op1\3l \1,7,\2,d7 +.endm + +ii_shift_op2aul:.macro //byt: 1=code 2=operation + ii_shift_op1\3l \1,8,\2,d0_off(a7) + ii_shift_op1\3l \1,9,\2,d1_off(a7) + ii_shift_op1\3l \1,a,\2,d2 + ii_shift_op1\3l \1,b,\2,d3 + ii_shift_op1\3l \1,c,\2,d4 + ii_shift_op1\3l \1,d,\2,d5 + ii_shift_op1\3l \1,e,\2,d6 + ii_shift_op1\3l \1,f,\2,d7 +.endm + +ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,l,\3r,#8,\4 + ii_shift_op0 2\1\2,l,\3r,#1,\4 + ii_shift_op0 4\1\2,l,\3r,#2,\4 + ii_shift_op0 6\1\2,l,\3r,#3,\4 + ii_shift_op0 8\1\2,l,\3r,#4,\4 + ii_shift_op0 a\1\2,l,\3r,#5,\4 + ii_shift_op0 c\1\2,l,\3r,#6,\4 + ii_shift_op0 e\1\2,l,\3r,#7,\4 + ii_shift_op0 1\1\2,l,\3l,#8,\4 + ii_shift_op0 3\1\2,l,\3l,#1,\4 + ii_shift_op0 5\1\2,l,\3l,#2,\4 + ii_shift_op0 7\1\2,l,\3l,#3,\4 + ii_shift_op0 9\1\2,l,\3l,#4,\4 + ii_shift_op0 b\1\2,l,\3l,#5,\4 + ii_shift_op0 d\1\2,l,\3l,#6,\4 + ii_shift_op0 f\1\2,l,\3l,#7,\4 +.endm + +ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,l,\3r,d2,\4 + ii_shift_op0 6\1\2,l,\3r,d3,\4 + ii_shift_op0 8\1\2,l,\3r,d4,\4 + ii_shift_op0 a\1\2,l,\3r,d5,\4 + ii_shift_op0 c\1\2,l,\3r,d6,\4 + ii_shift_op0 e\1\2,l,\3r,d7,\4 + ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,l,\3l,d2,\4 + ii_shift_op0 7\1\2,l,\3l,d3,\4 + ii_shift_op0 9\1\2,l,\3l,d4,\4 + ii_shift_op0 b\1\2,l,\3l,d5,\4 + ii_shift_op0 d\1\2,l,\3l,d6,\4 + ii_shift_op0 f\1\2,l,\3l,d7,\4 +.endm +// .word ea ============================================ +ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart +// (a0) bis (a7) ---------------------------- +ii_0xe\1d0: + move.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d1: + move.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d2: + ii_shift_typ w,\2,#1,(a2),(a2). +ii_0xe\1d3: + ii_shift_typ w,\2,#1,(a3),(a3). +ii_0xe\1d4: + ii_shift_typ w,\2,#1,(a4),(a4). +ii_0xe\1d5: + ii_shift_typ w,\2,#1,(a5),(a5). +ii_0xe\1d6: + ii_shift_typ w,\2,#1,(a6),(a6). +ii_0xe\1d7: + move.l usp,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// (a0)+ bis (a7)+ ----------------------------- +ii_0xe\1d8: + move.l a0_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d9: + move.l a1_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1da: + ii_shift_typ w,\2,#1,(a2),(a2)+. +ii_0xe\1db: + ii_shift_typ w,\2,#1,(a3),(a3)+ +ii_0xe\1dc: + ii_shift_typ w,\2,#1,(a4),(a4)+ +ii_0xe\1dd: + ii_shift_typ w,\2,#1,(a5),(a5)+ +ii_0xe\1de: + ii_shift_typ w,\2,#1,(a6),(a6)+ +ii_0xe\1df: + move.l usp,a1 + addq.l #2,a1 + move.l a1,usp + subq.l #2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// -(a0) bis -(a7) ----------------------------- +ii_0xe\1e0: + move.l a0_off(a7),a1 + subq.l #2,a1 + move.l a1,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e1: + move.l a1_off(a7),a1 + subq.l #2,a1 + move.l a1,a1_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e2: + ii_shift_typ w,\2,#1,-(a2),(a2). +ii_0xe\1e3: + ii_shift_typ w,\2,#1,-(a3),(a3) +ii_0xe\1e4: + ii_shift_typ w,\2,#1,-(a4),(a4) +ii_0xe\1e5: + ii_shift_typ w,\2,#1,-(a5),(a5) +ii_0xe\1e6: + ii_shift_typ w,\2,#1,-(a6),(a6) +ii_0xe\1e7: + move.l usp,a1 + subq.l #2,a1 + move.l a1,usp + ii_shift_typ w,\2,#1,(a1),(a1). +// d16(a0) bis d16(a7) ----------------------------- +ii_0xe\1e8: + move.w (a0)+,a1 + add.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e9: + move.w (a0)+,a1 + add.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1ea: + move.w (a0)+,a1 + add.l a2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1eb: + move.w (a0)+,a1 + add.l a3,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ec: + move.w (a0)+,a1 + add.l a4,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ed: + move.w (a0)+,a1 + add.l a5,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ee: + move.w (a0)+,a1 + add.l a6,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ef: + mvs.w (a0)+,d0 + move.l usp,a1 + add.l d0,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// d8(a0,dy) bis d8(a7,dy) ----------------------------- +ii_0xe\1f0: + move.l a0_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f1: + move.l a1_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f2: + move.l a2,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f3: + move.l a3,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f4: + move.l a4,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f5: + move.l a5,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f6: + move.l a6,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f7: + move.l usp,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +// xxx.w xxx.l +ii_0xe\1f8: + move.w (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f9: + move.l (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +.endm +//============================================================================ +//subroutine +//------------------------------ +ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + ii_shift_typ \2,\3,\4,\5,\5 +.endm + +ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + move.l \4,d0 + ii_shift_typ \2,\3,d0,\5,\5 +.endm + +ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest +#ifdef halten + halt +#endif +.ifc asr,\2 + mvs.\1 \4,d1 +.else + mvz.\1 \4,d1 +.endif +.ifc roxr,\2 + nop +.else + .ifc roxl,\2 + nop + .else + .ifc ror,\2 + nop + .else + .ifc rol,\2 + nop + .else + \2.l \3,d1 + .endif + .endif + .endif +.endif + set_cc0 + move.\1 d1,\5 + ii_end +.endm diff --git a/BaS_codewarrior/firebeeV1/sources/ii_sub.h b/BaS_codewarrior/firebeeV1/sources/ii_sub.h new file mode 100644 index 0000000..1405e1a --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/ii_sub.h @@ -0,0 +1,584 @@ +//-------------------------------------------------------------------- +// sub +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// sub.b #im,dx +//-------------------------------------------------------------------- +subbir_macro:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + sub.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea,dx +//-------------------------------------------------------------------- +subdd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +subddd:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subdda:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +subddai:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,-(ay),dx +//-------------------------------------------------------------------- +subddad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(ay),dx +//-------------------------------------------------------------------- +subd16ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(ay,dy),dx +//-------------------------------------------------------------------- +subd8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.w,dx +//-------------------------------------------------------------------- +subxwd:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.l,dx +//-------------------------------------------------------------------- +subxld:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(pc),dx +//-------------------------------------------------------------------- +subd16pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(pc,dy),dx +//-------------------------------------------------------------------- +subd8pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// sub dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subeda:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedai:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedaid:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedadd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d16(ay) +//-------------------------------------------------------------------- +sube16ad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d8(ay,dy) +//-------------------------------------------------------------------- +sube8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.w +//-------------------------------------------------------------------- +subxwe:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.l +//-------------------------------------------------------------------- +subxle:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // suba.w ea,ax +//-------------------------------------------------------------------- +subaw:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + suba.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// sub.w ea,usp +//-------------------------------------------------------------------- +subawa7:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + sub.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,ax +//-------------------------------------------------------------------- +subawu:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + suba.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,usp +//-------------------------------------------------------------------- +subawua7:.macro + subawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(ay),ax +//-------------------------------------------------------------------- +subawd16a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(ay,dy),ax +//-------------------------------------------------------------------- +subawd8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.w,ax +//-------------------------------------------------------------------- +subawxwax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.l,ax +//-------------------------------------------------------------------- +subawxlax:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(pc),ax +//-------------------------------------------------------------------- +subawd16pcax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(pc,dy),ax +//-------------------------------------------------------------------- +subawd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w #im,ax +//-------------------------------------------------------------------- +subawim:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(ay,dy),ax +//-------------------------------------------------------------------- +subald8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(pc,dy),ax +//-------------------------------------------------------------------- +subakd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// subx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // subx dy,dx +//-------------------------------------------------------------------- +subdx:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + subx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // subx -(ay),-(ax) +//-------------------------------------------------------------------- +subdax:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + subx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_codewarrior/firebeeV1/sources/illegal_instruction.s b/BaS_codewarrior/firebeeV1/sources/illegal_instruction.s new file mode 100644 index 0000000..21461b3 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/illegal_instruction.s @@ -0,0 +1,328 @@ +.public _illegal_instruction +.public _illegal_table_make + +.include "startcf.h" +.include "ii_macro.h" +.include "ii_func.h" +.include "ii_op.h" +.include "ii_opc.h" +.include "ii_add.h" +.include "ii_sub.h" +.include "ii_or.h" +.include "ii_and.h" +.include "ii_dbcc.h" +.include "ii_shd.h" +.include "ii_movem.h" +.include "ii_lea.h" +.include "ii_shift.h" +.include "ii_exg.h" +.include "ii_movep.h" +.include "ii_ewf.h" +.include "ii_move.h" + +.extern _ii_shift_vec +.extern ewf + +/*******************************************************/ +.text +ii_error: + nop + halt + nop + nop + +_illegal_instruction: +#ifdef ii_on + move.w #0x2700,sr + lea -ii_ss(a7),a7 + movem.l d0/d1/a0/a1,(a7) + move.l pc_off(a7),a0 // pc + mvz.w (a0)+,d0 // code + lea table,a1 + move.l 0(a1,d0*4),a1 + jmp (a1) +/*************************************************************************************************/ +#endif +_illegal_table_make: +#ifdef ii_on + lea table,a0 + moveq #0,d0 +_itm_loop: + move.l #ii_error,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itm_loop +//------------------------------------------------------------------------- + ii_ewf_lset // diverse fehlende adressierungn +//------------------------------------------------------------------------- +// 0x0000 +// ori + ii_lset_op 00 +// andi + ii_lset_op 02 +// subi + ii_lset_op 04 +// addi + ii_lset_op 06 +// eori + ii_lset_op 0a +// cmpi + ii_lset_op 0c +// movep + ii_movep_lset +//------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_lset +//------------------------------------------------------------------------- +// 0x4000 +//------------------------------------------------------------------------- +// negx + ii_lset_op 40 +// neg + ii_lset_op 44 +// not + ii_lset_op 46 +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_lset +//------------------------------------------------------------------- +// movem +//------------------------------------------------------------------- + ii_movem_lset +//------------------------------------------------------------------------- +// 0x5000 +//------------------------------------------------------------------------- +// addq, subq + ii_lset_op 50 + ii_lset_op 51 + ii_lset_op 52 + ii_lset_op 53 + ii_lset_op 54 + ii_lset_op 55 + ii_lset_op 56 + ii_lset_op 57 + ii_lset_op 58 + ii_lset_op 59 + ii_lset_op 5a + ii_lset_op 5b + ii_lset_op 5c + ii_lset_op 5d + ii_lset_op 5e + ii_lset_op 5f +// dbcc + ii_lset_dbcc +// scc + ii_lset_opc 50 + ii_lset_opc 51 + ii_lset_opc 52 + ii_lset_opc 53 + ii_lset_opc 54 + ii_lset_opc 55 + ii_lset_opc 56 + ii_lset_opc 57 + ii_lset_opc 58 + ii_lset_opc 59 + ii_lset_opc 5a + ii_lset_opc 5b + ii_lset_opc 5c + ii_lset_opc 5d + ii_lset_opc 5e + ii_lset_opc 5f +//------------------------------------------------------------------------- +// 0x8000 or +//------------------------------------------------------------------------- + ii_lset_func 8 +//------------------------------------------------------------------------- +// 0x9000 sub +//------------------------------------------------------------------------- + ii_lset_func 9 +//------------------------------------------------------------------------- +// 0xb000 +//------------------------------------------------------------------------- +// eor + ii_lset_op b1 + ii_lset_op b3 + ii_lset_op b5 + ii_lset_op b7 + ii_lset_op b9 + ii_lset_op bb + ii_lset_op bd + ii_lset_op bf +//------------------------------------------------------------------------- +// 0xc000 +//------------------------------------------------------------------------- +// and + ii_lset_func c +// exg + ii_exg_lset +//------------------------------------------------------------------------- +// 0xd000 add +//------------------------------------------------------------------------- + ii_lset_func d +//------------------------------------------------------------------------- +// 0xe000 +//------------------------------------------------------------------------- +// shift register + ii_shift_lset e +//------------------------------------------------- +// differenz zwischen orginal und gemoved korrigieren + lea ii_error(pc),a1 + move.l a1,d1 + sub.l #ii_error,d1 + lea table,a0 + moveq #0,d0 +_itkorr_loop: + add.l d1,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itkorr_loop +#endif + rts +#ifdef ii_on +//***********************************************************************************/ +//------------------------------------------------------------------------- + ii_ewf_func // diverse fehlende adressierungn +//------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x0000 +//-------------------------------------------------------------------- +// ori 00 + ii_op 00,or.l,i +//-------------------------------------------------------------------- +// andi 02 + ii_op 02,and.l,i +//-------------------------------------------------------------------- +// subi 04 + ii_op 04,and.l,i +//-------------------------------------------------------------------- +// addi 06 + ii_op 06,add.l,i +//-------------------------------------------------------------------- +// eori 0a + ii_op 0a,eor.l,i +//-------------------------------------------------------------------- +// cmpi 0c + ii_op 0c,cmp.l,i +//-------------------------------------------------------------------- +// movep + ii_movep_func +///--------------------------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_op +//--------------------------------------------------------------------------------------------- +// 0x4000 +//--------------------------------------------------------------------------------------------- +// neg 0x40.. + ii_op 40,negx.l,n +//--------------------------------------------------------------------------------------------- +// neg 0x44.. + ii_op 44,neg.l,n +//--------------------------------------------------------------------------------------------- +// not 0x46.. + ii_op 46,not.l,n +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_func +//------------------------------------------------------------------- +// movem +//-------------------------------------------------------------------- +ii_movem_func +//--------------------------------------------------------------------------------------------- +// 0x5000 +//--------------------------------------------------------------------------------------------- +//dbcc + ii_dbcc_func +// addq 0x5... + ii_op 50,addq.l #8,q + ii_op 52,addq.l #1,q + ii_op 54,addq.l #2,q + ii_op 56,addq.l #3,q + ii_op 58,addq.l #4,q + ii_op 5a,addq.l #5,q + ii_op 5c,addq.l #6,q + ii_op 5e,addq.l #7,q +//--------------------------------------------------------------------------------------------- +// subq 0x5... + ii_op 51,subq.l #8,q + ii_op 53,subq.l #1,q + ii_op 55,subq.l #2,q + ii_op 57,subq.l #3,q + ii_op 59,subq.l #4,q + ii_op 5b,subq.l #5,q + ii_op 5d,subq.l #6,q + ii_op 5f,subq.l #7,q +//--------------------------------------------------------------------------------------------- +// 0x5... scc + ii_opc 50,st,c + ii_opc 51,sf,c + ii_opc 52,shi,c + ii_opc 53,sls,c + ii_opc 54,scc,c + ii_opc 55,scs,c + ii_opc 56,sne,c + ii_opc 57,seq,c + ii_opc 58,svc,c + ii_opc 59,svs,c + ii_opc 5a,spl,c + ii_opc 5b,smi,c + ii_opc 5c,sge,c + ii_opc 5d,slt,c + ii_opc 5e,sgt,c + ii_opc 5f,sle,c +//--------------------------------------------------------------------------------------------- +// 0x6000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x7000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x8000 +//--------------------------------------------------------------------------------------------- +// or + ii_func 8,or +//--------------------------------------------------------------------------------------------- +// 0x9000 +//--------------------------------------------------------------------------------------------- +// sub + ii_func 9,sub +//--------------------------------------------------------------------------------------------- +// 0xa000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0xb000 +//--------------------------------------------------------------------------------------------- +// eor + ii_op b1,eor.l d0,q + ii_op b3,eor.l d1,q + ii_op b5,eor.l d2,q + ii_op b7,eor.l d3,q + ii_op b9,eor.l d4,q + ii_op bb,eor.l d5,q + ii_op bd,eor.l d6,q + ii_op bf,eor.l d7,q +//--------------------------------------------------------------------------------------------- +// 0xc000 +//--------------------------------------------------------------------------------------------- +// and + ii_func c,and +// exg + ii_exg_func +//--------------------------------------------------------------------------------------------- +// 0xd000 +//--------------------------------------------------------------------------------------------- +// add + ii_func d,add +//--------------------------------------------------------------------------------------------- +// 0xe000 shift +//-------------------------------------------------------------------- + ii_shift_op +//-------------------------------------------------------------------- +// 0xf000 +//-------------------------------------------------------------------- +#endif \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/last.c b/BaS_codewarrior/firebeeV1/sources/last.c new file mode 100644 index 0000000..0cb3a3e --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/last.c @@ -0,0 +1,11 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +void copy_end(void) +{ + asm + { +copy_end: + nop + } +} \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/last.s b/BaS_codewarrior/firebeeV1/sources/last.s new file mode 100644 index 0000000..c9dfe7a --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/last.s @@ -0,0 +1,10 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +.global copy_end + +.text + nop +copy_end: + nop +.asciz 'ende copy'; \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/macro.h b/BaS_codewarrior/firebeeV1/sources/macro.h new file mode 100644 index 0000000..2afa44e --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/macro.h @@ -0,0 +1,10 @@ +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +.text +wait_pll: .macro +wait1_pll\@: + tst.w (a1) + bmi wait1_pll\@ + rts +.endm diff --git a/BaS_codewarrior/firebeeV1/sources/mmu.s b/BaS_codewarrior/firebeeV1/sources/mmu.s new file mode 100644 index 0000000..0d3fade --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/mmu.s @@ -0,0 +1,196 @@ +/********************************************************************/ + /* INIT ACR und MMU /* +/********************************************************************/ + +.include "startcf.h" + +.extern _rt_vbr +.extern _rt_cacr +.extern _rt_asid +.extern _rt_acr0 +.extern _rt_acr1 +.extern _rt_acr2 +.extern _rt_acr3 +.extern _rt_mmubar +.extern ___MMUBAR +.extern cpusha +.extern _video_tlb +.extern _video_sbt + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) + +.public _mmu_init +.public _mmutr_miss + +.text +_mmu_init: + clr.l d0 + movec d0,ASID // ASID allways 0 + move.l d0,_rt_asid // sichern + movec d0,cacr // cache aus + move.l d0,_rt_cacr // sichern + nop + + move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff + movec d0,ACR0 + move.l d0,_rt_acr0 // sichern + + move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff + movec d0,ACR1 + move.l d0,_rt_acr1 // sichern + + move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff + movec d0,ACR2 + move.l d0,_rt_acr2 // sichern + + clr.l d0 // acr3 aus + movec d0,ACR3 + move.l d0,_rt_acr3 // sichern + + move.l #___MMUBAR+1,d0 + movec d0,MMUBAR //mmubar setzen + move.l d0,_rt_mmubar // sichern + + nop + + move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries, + move.l d0,MCF_MMU_MMUOR + nop +// 0000'0000 locked + moveq.l #0x00000000|std_mmutr,d0 + moveq.l #0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + moveq.l #mmuord_d,d2 // MMU update date + moveq.l #mmuord_i,d3 // MMU update instruction + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l d3,MCF_MMU_MMUOR // MMU update instruction + +//--------------------------------------------------------------------------------------- +// 00d0'0000 locked ID=6 +// video ram: read write execute normal write true + move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + move.l #0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l #0x00d00000|std_mmutr,d0 + move.l d3,MCF_MMU_MMUOR // MMU update instruction + + move.l #0x2000,d0 + move.l d0,_video_tlb // setze page als video page + clr.l _video_sbt // zeit löschen +//------------------------------------------------------------------------------------- +// 00e0'0000 locked + move.l #0x00e00000|std_mmutr,d0 + move.l #0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht + move.l d3,MCF_MMU_MMUOR // setzen +// 00f0'0000 locked + move.l #0x00f00000|std_mmutr,d0 + move.l #0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // maped to ffffxxx, precise, + move.l d3,MCF_MMU_MMUOR // maped to ffffxxx, precise, +// 1fe0'0000 locked + move.l #0x1FE00000|std_mmutr,d0 + move.l #0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// 1ff0'0000 locked + move.l #0x1FF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung +/* move.l #0xFFF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d3,MCF_MMU_MMUOR // setzen instr +*/ + move.l #0xa10ca120,d0 + move.l d0,_rt_cacr // sichern + movec d0,cacr + nop + rts + +/********************************************************************/ + /* MMU table search /* +/********************************************************************/ +_mmutr_miss: + bsr cpusha + and.l #0xFFF00000,d0 + or.l #std_mmutr,d0 + move.l d0,MCF_MMU_MMUTR + and.l #0xFFF00000,d0 + or.l #cb_mmudr,d0 + move.l d0,MCF_MMU_MMUDR + moveq.l #mmuord_d,d0 // MMU update data + move.l d0,MCF_MMU_MMUOR // setzen + moveq.l #mmuord_i,d0 // MMU update instruction + move.l d0,MCF_MMU_MMUOR // setzen + move.l (sp)+,d0 + rte diff --git a/BaS_codewarrior/firebeeV1/sources/movem.h b/BaS_codewarrior/firebeeV1/sources/movem.h new file mode 100644 index 0000000..b79349d --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/movem.h @@ -0,0 +1,256 @@ +// movem +_ii_movem_lset: .macro +// movem rx,xxx.L + ii_lset 0x48f9 +// movem rx,-(ax) + +// movem (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +// movem xxx.L,rx + ii_lset 0x4cf9 +.endm +//***********************************************************************************/ +_ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro + ii_end +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro + ii_end +.endm +//============================================================== +mvm_macro:.macro +halt + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +halt + tst.b d0 // datenregister zu verschieben? + bne mrm_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7 // -> +mrm_dx: + lsr.l #1,d0 + bcc mmrm_nd0 + move.l d0_off(a7),(a1)+ +mmrm_nd0: + lsr.l #1,d0 + bcc mmrm_nd1 + move.l d1_off(a7),(a1)+ +mmrm_nd1: + lsr.l #1,d0 + bcc mmrm_nd2 + move.l d2,(a1)+ +mmrm_nd2: + lsr.l #1,d0 + bcc mmrm_nd3 + move.l d3,(a1)+ +mmrm_nd3: + lsr.l #1,d0 + bcc mmrm_nd4 + move.l d4,(a1)+ +mmrm_nd4: + lsr.l #1,d0 + bcc mmrm_nd5 + move.l d5,(a1)+ +mmrm_nd5: + lsr.l #1,d0 + bcc mmrm_nd6 + move.l d6,(a1)+ +mmrm_nd6: + lsr.l #1,d0 + bcc mmrm_nd7 + move.l d7,(a1)+ +mmrm_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7 + lsr.l #1,d0 + bcc mmrm_na0 + move.l a0_off(a7),(a1)+ +mmrm_na0: + lsr.l #1,d0 + bcc mmrm_na1 + move.l a1_off(a7),(a1)+ +mmrm_na1: + lsr.l #1,d0 + bcc mmrm_na2 + move.l a2,(a1)+ +mmrm_na2: + lsr.l #1,d0 + bcc mmrm_na3 + move.l a3,(a1)+ +mmrm_na3: + lsr.l #1,d0 + bcc mmrm_na4 + move.l a4,(a1)+ +mmrm_na4: + lsr.l #1,d0 + bcc mmrm_na5 + move.l a5,(a1)+ +mmrm_na5: + lsr.l #1,d0 + bcc mmrm_na6 + move.l a6,(a1)+ +mmrm_na6: + lsr.l #1,d0 + bcc mmrm_na7 + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.l a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7: + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +halt + tst.b d0 // datenregister zu verschieben? + bne mmr_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7 // -> +mmr_dx: + lsr.l #1,d0 + bcc mmmr_nd0 + move.l (a1)+,d0_off(a7) +mmmr_nd0: + lsr.l #1,d0 + bcc mmmr_nd1 + move.l (a1)+,d1_off(a7) +mmmr_nd1: + lsr.l #1,d0 + bcc mmmr_nd2 + move.l (a1)+,d2 +mmmr_nd2: + lsr.l #1,d0 + bcc mmmr_nd3 + move.l (a1)+,d3 +mmmr_nd3: + lsr.l #1,d0 + bcc mmmr_nd4 + move.l (a1)+,d4 +mmmr_nd4: + lsr.l #1,d0 + bcc mmmr_nd5 + move.l (a1)+,d5 +mmmr_nd5: + lsr.l #1,d0 + bcc mmmr_nd6 + move.l (a1)+,d6 +mmmr_nd6: + lsr.l #1,d0 + bcc mmmr_nd7 + move.l (a1)+,d7 +mmmr_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7 // nein-> + lsr.l #1,d0 + bcc mmmr_na0 + move.l (a1)+,a0_off(a7) +mmmr_na0: + lsr.l #1,d0 + bcc mmmr_na1 + move.l (a1)+,a1_off(a7) +mmmr_na1: + lsr.l #1,d0 + bcc mmmr_na2 + move.l (a1)+,a2 +mmmr_na2: + lsr.l #1,d0 + bcc mmmr_na3 + move.l (a1)+,a3 +mmmr_na3: + lsr.l #1,d0 + bcc mmmr_na4 + move.l (a1)+,a4 +mmmr_na4: + lsr.l #1,d0 + bcc mmmr_na5 + move.l (a1)+,a5 +mmmr_na5: + lsr.l #1,d0 + bcc mmmr_na6 + move.l (a1)+,a6 +mmmr_na6: + lsr.l #1,d0 + bcc mmmr_na7 + move.l a0,d1 // sichern + move.l (a1)+,a0 // nach a0 + move.l a0,usp // war ja usp + move.l d1,a0 // pc zurück +mmmr_na7: + .endm diff --git a/BaS_codewarrior/firebeeV1/sources/sd_card.c b/BaS_codewarrior/firebeeV1/sources/sd_card.c new file mode 100644 index 0000000..58c48bd --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sd_card.c @@ -0,0 +1,605 @@ +/********************************************************************/ +// sd card +/********************************************************************/ + +#define __MBAR 0xff000000 +#define MCF_SLT0_SCNT __MBAR + 0x908 +#define MCF_PSC0_PSCTB_8BIT __MBAR + 0x860C +#define MCF_PAD_PAR_DSPI __MBAR + 0xA50 +#define MCF_DSPI_DMCR __MBAR + 0x8A00 //dspi control + +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 +#define time1us 1320 + + +void wait_10ms(void) +{ + asm + { +warte_10ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320000,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void sd_com(void) // byt senden und holen --------------------- +{ + + asm + { + + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + } +} + +void sd_get_status(void) // status holen ------------------------------- +{ + asm + { +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + } +} + +void sd_rcv_info(void) // daten holen ---------------------------- +{ + asm + { + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a2)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + } +} + +void sd_card_idle(void) +{ + + asm + { +// sd idle +// speed =400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + lea MCF_DSPI_DMCR,a0 + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + + move.b #0xff,d4 + bsr sd_com // clocks + move.b #0x40,d4 // cmd idle + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + } +} + +int sd_card_init(void) +{ + + long az_sectors; + + asm + { + lea MCF_PSC0_PSCTB_8BIT,a1 + move.l #'SD-C',(a1) + move.l #'ard ',(a1) + + move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit cs off clear fifo + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + move.l d4,dspi_dtfr // und setzen + mov3q.l #-1,dspi_dsr(a0) // status register löschen + + move.l #0xc00d3c00,(a0) // clock on cs ist on + bsr wait_10ms + move.l #0x802d3c00,(a0) // clock off cs off + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // cs on + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // cs off + bsr sd_com + bsr sd_com + bsr wait_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + bsr sd_card_idle + + move.l #10,d7 + move.b #0xff,d4 +sd_idle_leeren: + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d7 + bne sd_idle_leeren + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: + +// cdm 8 +read_ic: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + bsr sd_com // 4byts zum wegwerfen + bsr sd_com + bsr sd_com + bsr sd_com + cmp.b #0xaa,d5 // pattern zurückgekommen? + bne sd_testd3 // nein -> + + move.l #'SDHC',(a1) + move.b #' ',(a1) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #'Ver1',d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + bsr sd_com // 4 byts zum wegwerfen + bsr sd_com + bsr sd_com + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// fullspeed + move.l #0x38551120,d0 // 22Mbit/sec + move.l d0,dspi_dtar0(a0) // setzen + +// cdm 10 +read_cid: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a2 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a2 + moveq #7,d7 +sd_nam_loop: + move.b (a2)+,(a1) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a1) + +// cdm 9 +read_csd: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a2 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + move.l d1,d3 + lsr.l #6,d3 //x65636 /64 -> anzahl sectors + move.l d3,az_sectors + lsl.l #1,d1 + bcc sd_16G + move.l #'32GB',(a1) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #'16GB',(a1) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #' 8GB',(a1) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #' 4GB',(a1) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #' 2GB',(a1) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #' 1GB',(a1) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a1) + move.l #'12MB',(a1) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a1) + move.l #'56MB',(a1) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a1) + move.l #'28MB',(a1) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #'64MB',(a1) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #'32MB',(a1) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #'16MB',(a1) + bra sd_ok +sd_8M: + move.l #'<9MB',(a1) +sd_ok: + move.l #' OK!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_ok +// subs ende ------------------------------- +sd_error: + move.l #'Erro',(a1) + move.l #'r!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_error +sd_not: + move.l #'non!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_not +buffer: dc.l 0,0,0,0,0,0,0,0 + } +sd_c_ok: + return az_sectors; +sd_c_not: + return -2; +sd_c_error: + return -1; +} + +void sd_rcv_sector(void) // 1 sector daten holen ---------------------------- +{ + asm + { + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rs_end // nein-> error + move.l #512,d3 // sonst 512 byts abholen +sd_rs_loop: + bsr sd_com + move.b d5,(a2)+ + subq.l #1,d3 + bne sd_rs_loop +// crc holen + bsr sd_com + bsr sd_com + clr.l d5 // alles ok +sd_rs_end: + } +} + +int sd_card_sector_read(long sec_nr,long buf_adr) +{ + int status ; + asm + { + lea MCF_DSPI_DMCR,a0 + move.l #0x082000ff,d4 // tx vorbesetzen + + move.l sec_nr,d0 + move.l buf_adr,a2 + + lsl.l #8,d0 + add.l d0,d0 // x 512 ! + move.l d0,d1 // byts kehren + swap d1 + move.l d1,d2 + lsr.l #8,d1 + + move.b #0xff,d4 // clocks + bsr sd_com + + move.b #0x51,d4 + bsr sd_com + move.b d1,d4 + bsr sd_com + move.b d2,d4 + bsr sd_com + move.l d0,d2 + lsr.l #8,d2 + move.b d2,d4 + bsr sd_com + move.b d0,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + clr.l d5 // alles auf no error + clr.l status + + bsr sd_get_status // status holen + tst.b d5 + bne sd_csr_end // wenn nicht ok -> weg +// sector holen + bsr sd_rcv_sector +sd_csr_end: + tst.b d5 + beq sd_csr_ok + neg.l d5 // wenn nicht ok status auf negativ + move.l d5,status +sd_csr_ok: + } + return status; +} + +void sd_send_sector(void) // 1 sector daten senden ---------------------------- +{ + asm + { + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b (a2)+,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b #1,d4 + bsr sd_com // crc 1.byt + move.b #1,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + clr.l d6 //status auf OK + cmp.b #5,d5 //data accepted? + beq sd_send_end //ja -> + move.l d5,d6 //sonst status sichern +sd_send_end: + bsr sd_com + tst.b d5 // warte auf geschrieben + beq sd_send_end + move.l d6,d5 // status zurück + } +} + +int sd_card_sector_write(long sec_nr,long buf_adr) +{ + int status; + asm + { + lea MCF_DSPI_DMCR,a0 + move.l #0x082000ff,d4 // tx vorbesetzen + + move.l sec_nr,d0 + move.l buf_adr,a2 + + lsl.l #8,d0 + add.l d0,d0 // x 512 ! + move.l d0,d1 // byts kehren + swap d1 + move.l d1,d2 + lsr.l #8,d1 + + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x58,d4 + bsr sd_com + move.b d1,d4 + bsr sd_com + move.b d2,d4 + bsr sd_com + move.l d0,d2 + lsr.l #8,d2 + move.b d2,d4 + bsr sd_com + move.b d0,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + clr.l d5 // alles auf no error + clr.l status + bsr sd_get_status // status holen + tst.b d5 + bne sd_csw_end // wenn nicht ok -> weg +// sector schreiben + bsr sd_send_sector +sd_csw_end: + tst.b d5 + beq sd_csw_ok + neg.l d5 // wenn nicht ok status auf negativ + move.l d5,status +sd_csw_ok: + } + return status; +} diff --git a/BaS_codewarrior/firebeeV1/sources/sd_card.s b/BaS_codewarrior/firebeeV1/sources/sd_card.s new file mode 100644 index 0000000..c51147c --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sd_card.s @@ -0,0 +1,406 @@ +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +.text +sd_test: + lea MCF_PSC0_PSCTB_8BIT,a6 + move.l #'SD-C',(a6) + move.l #'ard ',(a6) + + move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x800d3c00,(a0) // 8 bit cs5 on + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + bsr warte_1ms + move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off + bsr warte_10ms + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + clr.b d4 + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + move.b #0xff,d4 + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + bsr warte_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.b #0xff,d4 // receive byt + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: +// cdm 8 +read_ic: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + cmp.b #0xaa,d5 + bne sd_testd3 + + move.l #'SDHC',(a6) + move.b #' ',(a6) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #'Ver1',d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// cdm 10 +read_cid: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a4 + moveq #7,d7 +sd_nam_loop: + move.b (a4)+,(a6) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a6) + +// cdm 9 +read_csd: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + lsl.l #1,d1 + bcc sd_16G + move.l #'32GB',(a6) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #'16GB',(a6) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #' 8GB',(a6) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #' 4GB',(a6) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #' 2GB',(a6) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #' 1GB',(a6) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a6) + move.l #'12MB',(a6) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a6) + move.l #'56MB',(a6) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a6) + move.l #'28MB',(a6) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #'64MB',(a6) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #'32MB',(a6) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #'16MB',(a6) + bra sd_ok +sd_8M: + move.l #'<9MB',(a6) +sd_ok: + move.l #' OK!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +// subs ende ------------------------------- +sd_V1: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_error: + move.l #'Erro',(a6) + move.l #'r!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_not: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_info: + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + rts +/******************************************/ diff --git a/BaS_codewarrior/firebeeV1/sources/sd_ide.c b/BaS_codewarrior/firebeeV1/sources/sd_ide.c new file mode 100644 index 0000000..092f95e --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sd_ide.c @@ -0,0 +1,543 @@ + + +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ diff --git a/BaS_codewarrior/firebeeV1/sources/sd_ide.s b/BaS_codewarrior/firebeeV1/sources/sd_ide.s new file mode 100644 index 0000000..4d31184 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sd_ide.s @@ -0,0 +1,458 @@ + + +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/* +sd_test: + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ diff --git a/BaS_codewarrior/firebeeV1/sources/startcf.c b/BaS_codewarrior/firebeeV1/sources/startcf.c new file mode 100644 index 0000000..7249338 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/startcf.c @@ -0,0 +1,83 @@ +/* + * CF_Startup.c - Default init/startup/termination routines for + * Embedded Metrowerks C++ + * + * Copyright © 1993-1998 Metrowerks, Inc. All Rights Reserved. + * Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved. + * + * + * THEORY OF OPERATION + * + * This version of thestartup code is intended for linker relocated + * executables. The startup code will assign the stack pointer to + * __SP_INIT, assign the address of the data relative base address + * to a5, initialize the .bss/.sbss sections to zero, call any + * static C++ initializers and then call main. Upon returning from + * main it will call C++ destructors and call exit to terminate. + */ + +#ifdef __cplusplus +#pragma cplusplus off +#endif +#pragma PID off +#pragma PIC off + +#include "MCF5475.h" + + + /* imported data */ + +extern unsigned long far _SP_INIT, _SDA_BASE; +extern unsigned long far _START_BSS, _END_BSS; +extern unsigned long far _START_SBSS, _END_SBSS; +extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END; +extern unsigned long far __Bas_base; + +extern unsigned long far __SUP_SP,__BOOT_FLASH; +extern unsigned long far rt_mbar; + + /* imported routines */ + +extern int BaS(int, char **); + + /* exported routines */ +extern void __initialize_hardware(void); +extern void init_slt(void); + + +void _startup(void) +{ + asm +{ + bra warmstart + jmp __BOOT_FLASH + 8 // ist zugleich reset vector + /* disable interrupts */ +warmstart: +// disable interrupts + move.w #0x2700,sr +// Initialize MBAR + MOVE.L #__MBAR,D0 + MOVEC D0,MBAR + move.l d0,rt_mbar +// mmu off + move.l #__MMUBAR+1,d0 + movec d0,MMUBAR //mmubar setzen + clr.l d0 + move.l d0,MCF_MMU_MMUCR // mmu off + /* Initialize RAMBARs: locate SRAM and validate it */ \ + move.l #__RAMBAR0 + 0x7,d0 // supervisor only + movec d0,RAMBAR0 + move.l #__RAMBAR1 + 0x1,d0 // on for all + movec d0,RAMBAR1 + +// STACKPOINTER AUF ENDE SRAM1 + lea __SUP_SP,a7 + +// instruction cache on + move.l #0x000C8100,d0 + movec d0,cacr + nop +// initialize any hardware specific issues + bra __initialize_hardware +} +} \ No newline at end of file diff --git a/BaS_codewarrior/firebeeV1/sources/startcf.h b/BaS_codewarrior/firebeeV1/sources/startcf.h new file mode 100644 index 0000000..c538f16 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/startcf.h @@ -0,0 +1,47 @@ +/****************************************************************************** + FILE : startcf.h + PURPOSE : startup code for ColdFire + LANGUAGE: C + + + Notes: + 1) Default entry point is _startup. + . disable interrupts + . the SP is set to __SP_AFTER_RESET + . SP must be initialized to valid memory + in case the memory it points to is not valid using MEMORY_INIT macro + 2) __initialize_hardware is called. Here you can initialize memory and some peripherics + at this point global variables are not initialized yet + 3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform + needed initialisations for the language (clear memory, data rom copy). + 4) void __initialize_system(void); is called + to allow additional hardware initialization (UART, GPIOs, etc...) + 5) Jump to main + +*/ +/********************************************************************************/ + +#define cf_stack + +//#define ii_on +#define halten +#define halten_dbcc +#define halten_and +#define halten_add +#define halten_sub +#define halten_or +#define halten_op +#define halten_opc +#define halten_movem +#define halten_lea +#define halten_shift +#define halten_move +#define halten_exg +#define halten_movep +#define halten_ewf + +#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C])) +#define DIP_SWITCHa ___MBAR + 0xA2C + +#define sca_page_ID 6 + diff --git a/BaS_codewarrior/firebeeV1/sources/supervisor.s b/BaS_codewarrior/firebeeV1/sources/supervisor.s new file mode 100644 index 0000000..29cd97f --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/supervisor.s @@ -0,0 +1,585 @@ +/********************************************************/ +/* user/supervisor handler +/********************************************************/ + +.include "startcf.h" + +.extern _rt_cacr; +.extern _rt_mod; +.extern _rt_ssp; +.extern _rt_usp; +.extern ___MMUBAR + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +.public _privileg_violation +.public cpusha + +.text +_privileg_violation: + move.w #0x2700,sr + lea -12(a7),a7 + movem.l d0/a0/a5,(a7) +#ifndef cf_stack + lea 0x52f0,a0 + move.l #0x20,(a0) // set auf 68030 +#endif + lea _rt_mod,a0 // zugriff setzen + tst.b (a0) // vom rt_supervisormodus? + bne pv_work // ja-> +// tatsächlich privileg violation + mov3q.l #-1,(a0) // sr_mod setzen + move.l usp,a5 // usp holen + move.l a5,8(a0) // sichern + move.l 4(a0),a5 // rt_ssp holen +#ifdef cf_stack + move.l 16(a7),-(a5) // pc verschieben + move.l 12(a7),-(a5) // sr verschieben + bset #5,2(a5) // auf super setzen +#else + move.w 12(a7),-(a5) // vector nr. + move.l 16(a7),-(a5) // pc verschieben + move.w 14(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp + move.l 12(a0),a5 // rt_vbr + lea 0x18(a5),a5 // vector + move.l (a5),16(a7) // vector privileg violation + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// privileg violation +pv_work: + move.l 16(a7),a5 // fault pc + move.b (a5),d0 // fault code + cmp.b #0x4e,d0 // 1.byt 0x4e + beq pv_4e // ja-> + cmp.b #0x46,d0 // 1.byt 0x46 + beq pv_46 // ja-> + cmp.b #0x40,d0 // 1.byt 0x40 + beq pv_40 // ja-> + cmp.b #0xf4,d0 // 0xf4? + beq pv_f4 + cmp.b #0xf3,d0 // 0xf3? + beq pv_f3 +// hierher sollt man nicht kommen + nop + halt + nop +// code 0x4exx ******************************************** +pv_4e: + move.b 1(a5),d0 + cmp.b #0x73,d0 //rte? + beq pv_rte //ja-> + cmp.b #0x72,d0 //stop? + beq pv_stop //ja-> + cmp.b #0x7B,d0 //movec? + beq pv_movec //ja-> +// move usp + btst #3,d0 // to or from + bne pv_usp_to_ax // usp -> ax +// move ax->usp + cmp.b #0x60,d0 //movec? + beq pv_a0_usp //ja-> + cmp.b #0x61,d0 //movec? + beq pv_a1_usp //ja-> + cmp.b #0x62,d0 //movec? + beq pv_a2_usp //ja-> + cmp.b #0x63,d0 //movec? + beq pv_a3_usp //ja-> + cmp.b #0x64,d0 //movec? + beq pv_a4_usp //ja-> + cmp.b #0x65,d0 //movec? + beq pv_a5_usp //ja-> + cmp.b #0x66,d0 //movec? + beq pv_a6_usp //ja-> + halt + bra pv_a7_usp //ja-> +// move usp->ax +pv_usp_to_ax: + move.l 8(a0),a5 //rt_usp holen + cmp.b #0x68,d0 //movec? + beq pv_usp_a0 //ja-> + cmp.b #0x69,d0 //movec? + beq pv_usp_a1 //ja-> + cmp.b #0x6a,d0 //movec? + beq pv_usp_a2 //ja-> + cmp.b #0x6b,d0 //movec? + beq pv_usp_a3 //ja-> + cmp.b #0x6c,d0 //movec? + beq pv_usp_a4 //ja-> + cmp.b #0x6d,d0 //movec? + beq pv_usp_a5 //ja-> + cmp.b #0x6e,d0 //movec? + beq pv_usp_a6 //ja-> +// usp->a7 + move.l a5,4(a0) // rt usp -> rt ssp + move.l a5,usp // und setzen + bra pv_usp_ax +// a0->usp +pv_a0_usp: move.l 4(a7),a5 + bra pv_ax_usp +// a1->usp +pv_a1_usp: move.l a1,a5 + bra pv_ax_usp +// a2->usp +pv_a2_usp: move.l a2,a5 + bra pv_ax_usp +// a3->usp +pv_a3_usp: move.l a3,a5 + bra pv_ax_usp +// a4->usp +pv_a4_usp: move.l a4,a5 + bra pv_ax_usp +// a5->usp +pv_a5_usp: move.l 8(a7),a5 + bra pv_ax_usp +// a6->usp +pv_a6_usp: move.l a6,a5 + bra pv_ax_usp +// a7->usp +pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 +pv_ax_usp: + move.l a5,8(a0) // usp -> rt_usp + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// usp->a0 +pv_usp_a0: + move.l a5,4(a7) + bra pv_usp_ax +pv_usp_a1: + move.l a5,a1 + bra pv_usp_ax +pv_usp_a2: + move.l a5,a2 + bra pv_usp_ax +pv_usp_a3: + move.l a5,a3 + bra pv_usp_ax +pv_usp_a4: + move.l a5,a4 + bra pv_usp_ax +pv_usp_a5: + move.l a5,8(a7) + bra pv_usp_ax +pv_usp_a6: + move.l a5,a6 +pv_usp_ax: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// rte +pv_rte: + move.l usp,a5 +#ifdef cf_stack + move.l (a5)+,12(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben +#else + move.w (a5)+,14(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben + move.w (a5)+,12(a7) // vector +#endif + bclr #5,14(a7) // war es von super? + bne pv_rte_sup // ja-> + clr.l (a0) // rt_mod auf user + move.l a5,4(a0) // rt_ssp sichern + move.l 8(a0),a5 // rt_usp holen +pv_rte_sup: + move.l a5,usp // usp setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// stop +pv_stop: + move.b 2(a5),d0 // sr wert + and.l #0x0700,d0 // int mask + cmp.w #0x700,d0 + beq stop7 + cmp.w #0x600,d0 + beq stop6 + cmp.w #0x500,d0 + beq stop5 + cmp.w #0x400,d0 + beq stop4 + cmp.w #0x300,d0 + beq stop3 + cmp.w #0x200,d0 + beq stop2 + cmp.w #0x100,d0 + beq stop1 + stop #0x2000 + bra stop_weiter +stop1: + stop #0x2100 + bra stop_weiter +stop2: + stop #0x2200 + bra stop_weiter +stop3: + stop #0x2300 + bra stop_weiter +stop4: + stop #0x2400 + bra stop_weiter +stop5: + stop #0x2500 + bra stop_weiter +stop6: + stop #0x2600 + bra stop_weiter +stop7: + stop #0x2700 +stop_weiter: + addq.l #4,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// movec ??????? +pv_movec: + move.w 2(a5),d0 // 2.word holen + and.l #0xf000,d0 + btst #15,d0 // addressregister? + bne pv_movec_ax // ja-> + tst.w d0 // d0? + bne pvm_d1 // nein-> + move.l (a7),-(a7) // d0 holen und sichern + bra pvm_me +pvm_d1: + cmp.w #0x1000,d0 // d1? + bne pvm_d2 // nein-> + move.l d1,-(a7) // d1 holen und sichern + bra pvm_me // fertig machen +pvm_d2: + cmp.w #0x2000,d0 // d1? + bne pvm_d3 // nein-> + move.l d2,-(a7) // d2 holen und sichern + bra pvm_me // fertig machen +pvm_d3: + cmp.w #0x3000,d0 // d1? + bne pvm_d4 // nein-> + move.l d3,-(a7) // d3 holen und sichern + bra pvm_me // fertig machen +pvm_d4: + cmp.w #0x4000,d0 // d1? + bne pvm_d5 // nein-> + move.l d4,-(a7) // d4 holen und sichern + bra pvm_me // fertig machen +pvm_d5: + cmp.w #0x5000,d0 // d1? + bne pvm_d6 // nein-> + move.l d5,-(a7) // d5 holen und sichern + bra pvm_me // fertig machen +pvm_d6: + cmp.w #0x6000,d0 // d1? + bne pvm_d7 // nein-> + move.l d6,-(a7) // d6 holen und sichern + bra pvm_me // fertig machen +pvm_d7: + move.l d7,-(a7) // d7 holen und sichern + bra pvm_me // fertig machen +pv_movec_ax: + cmp.w #0x8000,d0 // a0? + bne pvm_a1 // nein-> + move.l 4(a7),-(a7) // a0 holen und sichern + bra pvm_me // fertig machen +pvm_a1: + cmp.w #0x9000,d0 // a0? + bne pvm_a2 // nein-> + move.l a1,-(a7) // a1 holen und sichern + bra pvm_me // fertig machen +pvm_a2: + cmp.w #0xa000,d0 // a0? + bne pvm_a3 // nein-> + move.l a2,-(a7) // a2 holen und sichern + bra pvm_me // fertig machen +pvm_a3: + cmp.w #0xb000,d0 // a0? + bne pvm_a4 // nein-> + move.l a3,-(a7) // a3 holen und sichern + bra pvm_me // fertig machen +pvm_a4: + cmp.w #0xc000,d0 // a0? + bne pvm_a5 // nein-> + move.l a4,-(a7) // a4 holen und sichern + bra pvm_me // fertig machen +pvm_a5: + cmp.w #0xd000,d0 // a0? + bne pvm_a6 // nein-> + move.l 8(a7),-(a7) // a5 holen und sichern + bra pvm_me // fertig machen +pvm_a6: + cmp.w #0xe000,d0 // a0? + bne pvm_a7 // nein-> + move.l a6,-(a7) // a6 holen und sichern + bra pvm_me // fertig machen +pvm_a7: + move.l 4(a7),-(a7) // a7 holen und sichern +pvm_me: + move.w 2(a5),d0 // 2.word holen + andi.l #0xf,d0 // nur letzte 4 bits + move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long + jsr cpusha // gesammten cache flushen + rte +// code 0x46xx ***************************************** +pv_46: + move.b 1(a5),d0 + cmp.b #0xfc,d0 //#d16->sr + beq im_sr //ja-> +//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation + cmp.b #0xc0,d0 //d0->sr? + bne d1_sr //nein-> + move.w 2(a7),d0 //hier ist d0 gesichert + bra d0_sr +d1_sr: + cmp.b #0xc1,d0 //d1->sr? + bne d2_sr //nein-> + move.w d1,d0 + bra d0_sr +d2_sr: + cmp.b #0xc2,d0 //d2->sr? + bne d3_sr + move.w d2,d0 + bra d0_sr +d3_sr: + cmp.b #0xc3,d0 //d3->sr? + bne d4_sr + move.w d3,d0 + bra d0_sr +d4_sr: + cmp.b #0xc4,d0 //d4->sr? + bne d5_sr + move.w d4,d0 + bra d0_sr +d5_sr: + cmp.b #0xc5,d0 //d5->sr? + bne d6_sr + move.w d5,d0 + bra d0_sr +d6_sr: + cmp.b #0xc6,d0 //d6->sr? + bne d7_sr + move.w d6,d0 + bra d0_sr +d7_sr: + move.w d7,d0 // sonst d7->sr +d0_sr: + addq.l #2,16(a7) // next + bra pv_set_sr_end // fertig machen +// move #xxxx,sr +im_sr: + addq.l #4,16(a7) // next + move.w 2(a5),d0 // data +pv_set_sr_end: + bclr #13,d0 // war super? + bne pv_sre2 // ja -> + clr.l (a0) + move.l usp,a5 // usp + move.l a5,4(a0) // rt_ssp speichern + move.l 8(a0),a5 // rt_usp holen + move.l a5,usp // setzen +pv_sre2: + move.w d0,14(a7) // sr setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// code 0x40xx ***************************************** +pv_40: + move.b 1(a5),d0 // 2.byt + cmp.b #0xe7,d0 + beq pv_strldsr +// move sr->dx + move.l 12(a7),a5 // sr holen + tst.b (a0) // super? + beq pv_40_user // nein? + lea 0x2000(a5),a5 // super zuaddieren +pv_40_user: + cmp.b #0xc0,d0 + bne nsr_d1 + move.w a5,2(a7) + bra sr_dx_end +nsr_d1: + cmp.b #0xc1,d0 + bne nsr_d2 + move.w a5,d1 + bra sr_dx_end +nsr_d2: + cmp.b #0xc2,d0 + bne nsr_d3 + move.w a5,d2 + bra sr_dx_end +nsr_d3: + cmp.b #0xc3,d0 + bne nsr_d4 + move.w a5,d3 + bra sr_dx_end +nsr_d4: + cmp.b #0xc4,d0 + bne nsr_d5 + move.w a5,d4 + bra sr_dx_end +nsr_d5: + cmp.b #0xc5,d0 + bne nsr_d6 + move.w a5,d5 + bra sr_dx_end +nsr_d6: + cmp.b #0xc6,d0 + bne nsr_d7 + move.w a5,d6 + bra sr_dx_end +nsr_d7: + move.w a5,d7 + halt +sr_dx_end: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// strldsr +pv_strldsr: + nop + halt + nop +// code 0xf4xx *********************************** +pv_f4: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2.byt + bsr pv_ax_a0 // richtiges register + move.b 1(a5),d0 // 2.byt + cmp.b #0x30,d0 // >0xf430 + blo pv_intouch +// cpushl + cpushl bc,(a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_intouch: + intouch (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// subroutine register ax->a0 +pv_ax_a0: + and.l #0x7,d0 // nur register nummer + subq.l #1,d0 + bmi pv_a0_a0 + subq.l #1,d0 + bmi pv_a1_a0 + subq.l #1,d0 + bmi pv_a2_a0 + subq.l #1,d0 + bmi pv_a3_a0 + subq.l #1,d0 + bmi pv_a4_a0 + subq.l #1,d0 + bmi pv_a5_a0 + subq.l #1,d0 + bmi pv_a6_a0 + move.l a7,a0 + rts +pv_a0_a0: + move.l 8(a7),a0 + rts +pv_a1_a0: + move.l a1,a0 + rts +pv_a2_a0: + move.l a2,a0 + rts +pv_a3_a0: + move.l a3,a0 + rts +pv_a4_a0: + move.l a4,a0 + rts +pv_a5_a0: + move.l 12(a7),a0 + rts +pv_a6_a0: + move.l a6,a0 + rts +// code 0xf4xx *********************************** +pv_f3: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2. byt + cmp.b #0x40,d0 + bgt pv_frestore +//fsave (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x20,d0 +// +d16 + blt pv_f3_ax + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_f3_ax: + fsave (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_frestore: + cmp.b #0x7a,d0 + beq pv_f_d16pc +// frestore (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x60,d0 + blt pv_frestore_ax +pv_fend: + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_frestore_ax: + frestore (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// frestore d16(pc) +pv_f_d16pc: + move.l 16(a7),a0 // pc holen + bra pv_fend +//***************************************************** +cpusha: + lea -16(a7),a7 + movem.l d0-d2/a0,(a7) // register sichern + move sr,d2 + nop + move #0x2700,sr // no interrupts + + clr.l d0 + clr.l d1 + move.l d0,a0 +cfa_setloop: + cpushl bc,(a0) // flush + lea 0x10(a0),a0 // index+1 + addq.l #1,d1 // index+1 + cmpi.w #512,d1 // alle sets? + bne cfa_setloop // nein-> + clr.l d1 + addq.l #1,d0 + move.l d0,a0 + cmpi.w #4,d0 // all ways? + bne cfa_setloop // nein-> + nop + move.l _rt_cacr,d0 // holen + movec d0,cacr // setzen + move.w d2,sr // alte interrupt maske + movem.l (a7),d0-d2/a0 // register zurück + lea 16(a7),a7 + + rts +//*******************************************************33 + diff --git a/BaS_codewarrior/firebeeV1/sources/sysinit.c b/BaS_codewarrior/firebeeV1/sources/sysinit.c new file mode 100644 index 0000000..9d75090 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sysinit.c @@ -0,0 +1,833 @@ +/* + * File: sysinit.c + * Purpose: Power-on Reset configuration of the COLDARI board. + * + * Notes: + * + */ +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __VRAM; +extern unsigned long far __Bas_base; +extern unsigned long far BaS; +extern unsigned long far __BOOT_FLASH[]; +extern int copy_end(); +extern int warte_10us(); +extern int warte_1ms(); +extern int warte_10ms(); +extern int warte_50us(); + +extern unsigned long far rt_cacr; + +/********************************************************************/ +// init SLICE TIMER 0 +// all = 32.538 sec = 30.736mHz +// BYT0 = 127.1ms/tick = 7.876Hz offset 0 +// BYT1 = 496.5us/tick = 2.014kHz offset 1 +// BYT2 = 1.939us/tick = 515.6kHz offset 2 +// BYT3 = 7.576ns/tick = 132.00MHz offset 3 +// count down!!! 132MHz!!! +/********************************************************************/ + +void init_slt(void) +{ + asm + { + lea MCF_SLT0_STCNT,a0 + move.l #0xffffffff,(a0) + lea MCF_SLT0_SCR,a0 + move.b #0x05,(a0) + + } + MCF_PSC0_PSCTB_8BIT = 'SLT '; + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/********************************************************************/ +// init GPIO ETC. +/********************************************************************/ + +void init_gpio(void) +{ + + +// PAD REGISTER P.S.:FBCTL UND FBCS WERDEN RICHTIG GESETZT BEIM RESET + MCF_PAD_PAR_DMA = 0b11111111; // NORMAL ALS DREQ DACK + MCF_PAD_PAR_FECI2CIRQ = 0b1111001111001111; // FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6 + MCF_PAD_PAR_PCIBG = 0b0000001000111111; // #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL + MCF_PAD_PAR_PCIBR = 0b0000001000111111; // #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL + MCF_PAD_PAR_PSC3 = 0b00001100; // PSC3=TX,RX CTS+RTS=I/O + MCF_PAD_PAR_PSC1 = 0b11111100; // PSC1 NORMAL SERIELL + MCF_PAD_PAR_PSC0 = 0b11111100; // PSC0 NORMAL SERIELL + MCF_PAD_PAR_DSPI = 0b0001111111111111; // DSPI NORMAL + MCF_PAD_PAR_TIMER = 0b00101101; // TIN3..2=#IRQ3..2;TOUT3..2=NORMAL +// ALLE OUTPUTS NORMAL LOW + +// ALLE DIR NORMAL INPUT = 0 + MCF_GPIO_PDDR_FEC1L = 0b00011110; // OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) + +} + +/********************************************************************/ +// init seriel +/********************************************************************/ + +void init_seriel(void) +{ + +// PSC0: SER1 ---------- + MCF_PSC0_PSCSICR = 0; // UART + MCF_PSC0_PSCCSR = 0xDD; + MCF_PSC0_PSCCTUR = 0x00; + MCF_PSC0_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC0_PSCCR = 0x20; + MCF_PSC0_PSCCR = 0x30; + MCF_PSC0_PSCCR = 0x40; + MCF_PSC0_PSCCR = 0x50; + MCF_PSC0_PSCCR = 0x10; + MCF_PSC0_PSCIMR = 0x8700; + MCF_PSC0_PSCACR = 0x03; + MCF_PSC0_PSCMR1= 0xb3; + MCF_PSC0_PSCMR2= 0x07; + MCF_PSC0_PSCRFCR = 0x0F; + MCF_PSC0_PSCTFCR = 0x0F; + MCF_PSC0_PSCRFAR = 0x00F0; + MCF_PSC0_PSCTFAR = 0x00F0; + MCF_PSC0_PSCOPSET = 0x01; + MCF_PSC0_PSCCR = 0x05; +// PSC3: PIC ---------- + MCF_PSC3_PSCSICR = 0; // UART + MCF_PSC3_PSCCSR = 0xDD; + MCF_PSC3_PSCCTUR = 0x00; + MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC3_PSCCR = 0x20; + MCF_PSC3_PSCCR = 0x30; + MCF_PSC3_PSCCR = 0x40; + MCF_PSC3_PSCCR = 0x50; + MCF_PSC3_PSCCR = 0x10; + MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable + MCF_PSC3_PSCACR = 0x03; + MCF_PSC3_PSCMR1= 0xb3; + MCF_PSC3_PSCMR2= 0x07; + MCF_PSC3_PSCRFCR = 0x0F; + MCF_PSC3_PSCTFCR = 0x0F; + MCF_PSC3_PSCRFAR = 0x00F0; + MCF_PSC3_PSCTFAR = 0x00F0; + MCF_PSC3_PSCOPSET = 0x01; + MCF_PSC3_PSCCR = 0x05; + MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/ + + MCF_PSC0_PSCTB_8BIT = 0x0a0d; + MCF_PSC0_PSCTB_8BIT = 'SERI'; + MCF_PSC0_PSCTB_8BIT = 'AL O'; + MCF_PSC0_PSCTB_8BIT = 'K! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} +/********************************************************************/ + /* Initialize DDR DIMMs on the EVB board */ +/********************************************************************/ + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + + +void init_ddram(void) +{ + MCF_PSC0_PSCTB_8BIT = 'DDRA'; + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) + { + + /* Basic configuration and initialization */ + MCF_SDRAMC_SDRAMDS = 0x000002AA; // SDRAMDS configuration + MCF_SDRAMC_CS0CFG = 0x0000001A; // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) + MCF_SDRAMC_CS1CFG = 0x0800001A; // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) + MCF_SDRAMC_CS2CFG = 0x1000001A; // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) + MCF_SDRAMC_CS3CFG = 0x1800001A; // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +// MCF_SDRAMC_SDCFG1 = 0x53722938; // SDCFG1 + MCF_SDRAMC_SDCFG1 = 0x73622830; // SDCFG1 +// MCF_SDRAMC_SDCFG2 = 0x24330000; // SDCFG2 + MCF_SDRAMC_SDCFG2 = 0x46770000; // SDCFG2 +// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL + MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL + MCF_SDRAMC_SDMR = 0x40010000; // SDMR (write to LEMR) +// MCF_SDRAMC_SDMR = 0x05890000; // SDRM (write to LMR) + MCF_SDRAMC_SDMR = 0x048D0000; // SDRM (write to LMR) +// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL + MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL +// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (first refresh) + MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (first refresh) +// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (second refresh) + MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (second refresh) +/// MCF_SDRAMC_SDMR = 0x01890000; // SDMR (write to LMR) + MCF_SDRAMC_SDMR = 0x008D0000; // SDMR (write to LMR) +// MCF_SDRAMC_SDCR = 0x710F0F00; // SDCR (lock SDMR and enable refresh) + MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh) + } + MCF_PSC0_PSCTB_8BIT = 'M OK'; + MCF_PSC0_PSCTB_8BIT = '! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} +/********************************************************************/ + /* init FB_CSx /* +/********************************************************************/ +void init_fbcs() +{ + MCF_PSC0_PSCTB_8BIT = 'FBCS'; + /* Flash */ + MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS + MCF_FBCS0_CSCR = 0x00001180 // 16 bit 4ws aa + | MCF_FBCS_CSCR_RDAH(1); // READ HOLD TIME 1 CYCLUS + MCF_FBCS0_CSMR = 0x007F0001; // 8MB on + + MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS + MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT + | MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS + | MCF_FBCS_CSCR_RDAH(1) // READ HOLD TIME 1 CYCLUS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M + | MCF_FBCS_CSMR_V); + + MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS + | MCF_FBCS_CSCR_RDAH(1) // READ HOLD TIME 1 CYCLUS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT + | MCF_FBCS_CSCR_WS(0) // 0WS + | MCF_FBCS_CSCR_RDAH(1) // READ HOLD TIME 1 CYCLUS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA + MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE + | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE + MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_PSC0_PSCTB_8BIT = ' OK!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/********************************************************************/ + /* FPGA LADEN /* +/********************************************************************/ + + +void init_fpga(void) +{ + + MCF_PSC0_PSCTB_8BIT = 'FPGA'; +asm + { + lea MCF_GPIO_PODR_FEC1L,a1 // register adresse:write + lea MCF_GPIO_PPDSDR_FEC1L,a2 // reads + bclr #1,(a1) // clk auf low + bclr #2,(a1) // #config=low +test_nSTATUS: + btst #0,(a2) // nSTATUS==0 + bne test_nSTATUS // nein-> + btst #5,(a2) // conf done==0 + bne test_nSTATUS // nein-> + jsr warte_10us // warten + bset #2,(a1) // #config=high + jsr warte_10us // warten +test_STATUS: + btst #0,(a2) // status high? + beq test_STATUS // nein-> + jsr warte_10us // warten + + lea 0xE0700000,a0 // startadresse fpga daten +word_send_loop: + cmp.l #0xE0800000,a0 + bgt fpga_error + move.b (a0)+,d0 // 32 bit holen + moveq #8,d1 // 32 bit ausgeben +bit_send_loop: + lsr.l #1,d0 // bit rausschieben + bcs bit_is_1 + bclr #3,(a1) + bra bit_send +bit_is_1: + bset #3,(a1) +bit_send: + bset #1,(a1) // clock=high + bclr #1,(a1) // clock=low + subq.l #1,d1 + bne bit_send_loop // wiederholen bis fertig + btst #5,(a2) // fpga fertig, conf_done=high? + beq word_send_loop // nein, next word-> + move.l #4000,d1 +overclk: + bset #1,(a1) // clock=high + nop + bclr #1,(a1) // clock=low + subq.l #1,d1 + bne overclk // weiter bis fertig + bra init_fpga_end + +//--------------------------------------------------------- +wait_pll: + lea MCF_SLT0_SCNT,a3 + move.l (a3),d0 + move.l #100000,d6 // ca 1ms +wait_pll_loop: + tst.w (a1) + bpl wait_pll_ok + move.l (a3),d1 + sub.l d0,d1 + add.l d6,d1 + bpl wait_pll_loop +wait_pll_ok: + rts +// fertig +fpga_error: + } + MCF_PSC0_PSCTB_8BIT = ' NOT'; +init_fpga_end: + MCF_PSC0_PSCTB_8BIT = ' OK!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; + +// init pll + MCF_PSC0_PSCTB_8BIT = 'PLL '; +asm +{ + lea 0xf0000600,a0 + lea 0xf0000800,a1 + bsr wait_pll + move.w #27,0x48(a0) // loopfilter r + bsr wait_pll + move.w #1,0x08(a0) // charge pump I + bsr wait_pll + move.w #12,0x0(a0) // N counter high = 12 + bsr wait_pll + move.w #12,0x40(a0) // N counter low = 12 + bsr wait_pll + move.w #1,0x114(a0) // ck1 bypass + bsr wait_pll + move.w #1,0x118(a0) // ck2 bypass + bsr wait_pll + move.w #1,0x11c(a0) // ck3 bypass + bsr wait_pll + move.w #1,0x10(a0) // ck0 high = 1 + bsr wait_pll + move.w #1,0x50(a0) // ck0 low = 1 + + bsr wait_pll + move.w #1,0x144(a0) // M odd division + bsr wait_pll + move.w #1,0x44(a0) // M low = 1 + + bsr wait_pll + move.w #165,0x04(a0) // M high = 145 = 146MHz + + bsr wait_pll + clr.b (a1) // set +} + MCF_PSC0_PSCTB_8BIT = 'SET!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/********************************************************************/ + /* INIT VIDEO DDR RAM /* +/********************************************************************/ + +void init_video_ddr(void) +{ + asm + { + +// init video ram + moveq.l #0xB,d0 + move.w d0,0xF0000400 //set cke=1, cs=1 config=1 + nop + lea __VRAM,a0 //zeiger auf video ram + nop + move.l #0x00050400,(a0) //IPALL + nop + move.l #0x00072000,(a0) //load EMR pll on + nop + move.l #0x00070122,(a0) //load MR: reset pll, cl=2 BURST=4lw + nop + move.l #0x00050400,(a0) //IPALL + nop + move.l #0x00060000,(a0) //auto refresh + nop + move.l #0x00060000,(a0) //auto refresh + nop + move.l #0000070022,(a0) //load MR dll on + nop + move.l #0x01070002,d0 // fifo on, refresh on, ddrcs und cke on, video dac on, + move.l d0,0xf0000400 + } +} + +/********************************************************************/ + /* video mit auflösung 1280x1000 137MHz /* +/********************************************************************/ + +void video_1280_1024(void) +{ +extern int wait_pll; + + asm + { + + +// SPEICHER FÜLLEM + +//testmuster 1 + lea __VRAM,a2 + lea __VRAM+0x600000,a3 + clr.l d0 + move.l #0x1000102,d1 +loop5: move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + move.l d0,(a2)+ + add.l d1,d0 +flo6: cmp.l a2,a3 + bgt loop5 + +// screen setzen +//horizontal 1280 + lea 0xffff8282,a0 + move.w #1800,(a0)+ + move.w #1380,(a0)+ + move.w #99,(a0)+ + move.w #100,(a0)+ + move.w #1379,(a0)+ + move.w #1500,(a0) +//vertical 1024 + lea 0xffff82a2,a0 + move.w #1150,(a0)+ + move.w #1074,(a0)+ + move.w #49,(a0)+ + move.w #50,(a0)+ + move.w #1073,(a0)+ + move.w #1100,(a0)+ +// acp video on + move.l #0x01070207,d0 + move.l d0,0xf0000400 + + +// clut setzen + lea 0xf0000000,a0 + move.l #0xffffffff,(a0)+ + move.l #0xff,(a0)+ + move.l #0xff00,(a0)+ + move.l #0xff0000,(a0) + +// halt + + } + +} +/********************************************************************/ + /* INIT PCI /* +/********************************************************************/ + +#define PCI_MEMORY_OFFSET (0x80000000) +#define PCI_MEMORY_SIZE (0x40000000) +#define PCI_IO_OFFSET (0xD0000000) +#define PCI_IO_SIZE (0x10000000) + + +void init_PCI(void) +{ + + MCF_PSC0_PSCTB_8BIT = 'PCI '; +asm + { + // Setup the arbiter + move.l #MCF_PCIARB_PACR_INTMPRI \ + + MCF_PCIARB_PACR_EXTMPRI(0x1F) \ + + MCF_PCIARB_PACR_INTMINTEN \ + + MCF_PCIARB_PACR_EXTMINTEN(0x1F),D0 + move.l D0,MCF_PCIARB_PACR + // Setup burst parameters + move.l #MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32),D0 + move.l D0,MCF_PCI_PCICR1 + move.l #MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16),D0 + move.l D0,MCF_PCI_PCICR2 + // Turn on error signaling + move.l #MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_IAE + MCF_PCI_PCIICR_REE + 32,D0 + move.l D0,MCF_PCI_PCIICR + move.l #MCF_PCI_PCIGSCR_SEE,D0 + or.l D0,MCF_PCI_PCIGSCR + // Configure Initiator Windows */ + move.l #PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8),D0 + clr.w D0 + move.l D0,MCF_PCI_PCIIW0BTAR // Initiator Window 0 Base / Translation Address Register + + move.l #PCI_IO_OFFSET+((PCI_IO_SIZE-1)>>8),D0 + clr.w D0 + move.l D0,MCF_PCI_PCIIW1BTAR // Initiator Window 1 Base / Translation Address Register + + clr.l MCF_PCI_PCIIW2BTAR // not used + + move.l #MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO,D0 + move.l D0,MCF_PCI_PCIIWCR // Initiator Window Configuration Register + + /* Clear PCI Reset and wait for devices to reset */ + move.l #~MCF_PCI_PCIGSCR_PR,D0 + and.l D0,MCF_PCI_PCIGSCR + } + + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} +/********************************************************************/ + /* test UPC720101 (USB) /* +/********************************************************************/ + +void test_upd720101(void) +{ + + MCF_PSC0_PSCTB_8BIT = 'NEC '; +asm + { + // SELECT UPD720101 AD17 + MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(0),D0 + MOVE.L D0,MCF_PCI_PCICAR + LEA PCI_IO_OFFSET,A0 + MOVE.L (A0),D1 + move.l #0x33103500,d0 + cmp.l d0,d1 + beq nec_ok + } + MCF_PSC0_PSCTB_8BIT = 'NOT '; + goto nec_not_ok; +nec_ok: + asm + { + MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0 + MOVE.L D0,MCF_PCI_PCICAR + move.b #0x20,(a0) + } +nec_not_ok: + asm + { + MOVE.L #MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0 + MOVE.L D0,MCF_PCI_PCICAR + } + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/********************************************************************/ + /* TFP410 (vdi) einschalten /* +/********************************************************************/ + +void vdi_on(void) +{ + uint8 RBYT, DBYT; + int versuche, startzeit; + + + MCF_PSC0_PSCTB_8BIT = 'DVI '; + MCF_I2C_I2FDR = 0x34; // 100kHz standard + versuche = 0; +loop_i2c: + if (versuche++>10) goto next; + MCF_I2C_I2ICR = 0x0; + MCF_I2C_I2CR = 0x0; + MCF_I2C_I2CR = 0xA; + RBYT = MCF_I2C_I2DR; + MCF_I2C_I2SR = 0x0; + MCF_I2C_I2CR = 0x0; + MCF_I2C_I2ICR = 0x01; + + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7A; + warte_100us(); + if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2DR = 0x00; // SUB ADRESS 0 + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR |= 0x4; // repeat start + + MCF_I2C_I2DR = 0x7b; // beginn read + warte_100us(); + if (MCF_I2C_I2SR!=0xa6 | MCF_I2C_I2CR!=0xb0) goto loop_i2c; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR &= 0xef; // switch to rx + DBYT = MCF_I2C_I2DR; // dummy read + + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR |= 0x08; // txak=1 + + warte_100us(); + RBYT = MCF_I2C_I2DR; + + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR = 0x0; // stop + DBYT = MCF_I2C_I2DR; // dummy read + + if (RBYT!=0x4c) goto loop_i2c; + + +i2c_ok: + MCF_I2C_I2CR = 0x0; // stop + MCF_I2C_I2SR = 0x0; // clear sr + while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free + + MCF_I2C_I2CR = 0xb0; // on tx master + MCF_I2C_I2DR = 0x7A; + warte_50us(); + if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR = 0x0; // stop + MCF_I2C_I2SR = 0x0; // clear sr + + while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free + + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7A; + warte_50us(); + if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR |= 0x4; // repeat start + MCF_I2C_I2DR = 0x7b; // beginn read + warte_50us(); + if (MCF_I2C_I2SR!=0xa6 | MCF_I2C_I2CR!=0xb0) goto loop_i2c; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR &= 0xef; // switch to rx + + DBYT = MCF_I2C_I2DR; // dummy read + + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR |= 0x08; // txak=1 + + warte_50us(); + RBYT = MCF_I2C_I2DR; + + while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR = 0x0; // stop + DBYT = MCF_I2C_I2DR; // dummy read + + if (RBYT!=0xbf) goto loop_i2c; + + goto dvi_ok; +next: + MCF_I2C_I2CR = 0x0; // stop + MCF_PSC0_PSCTB_8BIT = 'NOT '; +dvi_ok: + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/********************************************************************/ + /* AC97 /* +/********************************************************************/ +void init_ac97(void) +{ +// PSC2: AC97 ---------- + int i,k,zm,x,va,vb,vc; + + MCF_PSC0_PSCTB_8BIT = 'AC97'; + MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 + | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK + | MCF_PAD_PAR_PSC2_PAR_TXD2 + | MCF_PAD_PAR_PSC2_PAR_RXD2; + MCF_PSC2_PSCMR1 = 0x0; + MCF_PSC2_PSCMR2 = 0x0; + MCF_PSC2_PSCIMR = 0x0300; + MCF_PSC2_PSCSICR = 0x03; //AC97 + MCF_PSC2_PSCRFCR = 0x0f000000; + MCF_PSC2_PSCTFCR = 0x0f000000; + MCF_PSC2_PSCRFAR = 0x00F0; + MCF_PSC2_PSCTFAR = 0x00F0; + + for ( zm = 0; zm<100000; zm++) // wiederholen bis synchron + { + MCF_PSC2_PSCCR = 0x20; + MCF_PSC2_PSCCR = 0x30; + MCF_PSC2_PSCCR = 0x40; + MCF_PSC2_PSCCR = 0x05; +// MASTER VOLUME -0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for ( i = 2; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // read register + MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume + for ( i = 2; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 + } + warte_50us(); + va = MCF_PSC2_PSCTB_AC97; + if ((va & 0x80000fff)==0x80000800) + { + vb = MCF_PSC2_PSCTB_AC97; + vc = MCF_PSC2_PSCTB_AC97; + if ((va & 0xE0000fff)==0xE0000800 & vb==0x02000000 & vc==0x00000000) + { + goto livo; + } + } + } + MCF_PSC0_PSCTB_8BIT = ' NOT'; +livo: +// AUX VOLUME ->-0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 + MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME + for ( i = 3; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + +// line in VOLUME +12dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for ( i = 2; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } +// cd in VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for ( i = 2; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } +// mono out VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for ( i = 3; i<13; i++ ) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF + MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data + +ac97_end: + MCF_PSC0_PSCTB_8BIT = ' OK!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; + +} +/********************************************************************/ + +void __initialize_hardware(void) +{ +_init_hardware: +asm +{ + // instruction cache on + move.l #0x000C8120,d0 + move.l d0,rt_cacr + movec d0,cacr + nop +} + init_gpio(); + init_seriel(); + init_slt(); + init_fbcs(); + init_ddram(); +// Ports nicht initialisieren wenn DIP Switch 6 = on +asm +{ + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + beq not_init_ports +} + init_PCI(); //pci braucht zeit + not_init_ports: + init_fpga(); + init_video_ddr(); + vdi_on(); +// Ports nicht initialisieren wenn DIP Switch 6 = on +asm +{ + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + beq not_init_ports2 +} +// video_1280_1024(); + test_upd720101(); +not_init_ports2: + init_ac97(); + +asm +{ +/*****************************************************/ +/* BaS kopieren +/*****************************************************/ + lea copy_start,a0 + lea BaS,a1 + sub.l a0,a1 + move.l #__Bas_base,a2 + move.l a2,a3 + add.l a1,a3 + lea copy_end,a4 +BaS_kopieren_loop: // immer 16 bytes + move.l (a0)+,(a2)+ + move.l (a0)+,(a2)+ + move.l (a0)+,(a2)+ + move.l (a0)+,(a2)+ + cmp.l a4,a0 + blt BaS_kopieren_loop +/*****************************************************/ + jmp (a3) + copy_start: +/********************************************************************/ +} +} + diff --git a/BaS_codewarrior/firebeeV1/sources/sysinit.h b/BaS_codewarrior/firebeeV1/sources/sysinit.h new file mode 100644 index 0000000..70bc6da --- /dev/null +++ b/BaS_codewarrior/firebeeV1/sources/sysinit.h @@ -0,0 +1,87 @@ +/* + * File: sysinit.h + * Purpose: COLDARI Power-on Reset configuration + * + * Notes: + * + */ + +#ifndef __SYSINIT_H__ +#define __SYSINIT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if ENABLE_UART_SUPPORT==1 + +/* + * System Bus Clock Info + */ +// 5475EVB has 133Mhz system clock +#define SYSTEM_CLOCK_KHZ 133000 /* system bus frequency in kHz */ + + +/*** + * Serial Port Info + * The baud rate to be : 19200 + * Data bits : 8 + * Parity : None + * Stop Bits : 1 + * Flow Control : None + */ +#define TERMINAL_PORT (0) /* PSC channel used as terminal */ +#define TERMINAL_BAUD kBaud19200 /* 115200 */ +#undef HARDWARE_FLOW_CONTROL /* Flow control ON or OFF */ +#endif + +/*** + * Board Memory map definitions from linker command files: + * __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker + * symbols must be defined in the linker command file. + */ +extern __declspec(system) uint8 __BOOT_FLASH[]; +extern __declspec(system) uint8 __BOOT_FLASH_SIZE[]; + +extern __declspec(system) uint8 __SDRAM[]; +extern __declspec(system) uint8 __SDRAM_SIZE[]; + + +#define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH +#define BOOT_FLASH_SIZE (uint32)__BOOT_FLASH_SIZE + +#define SDRAM_ADDRESS (uint32)__SDRAM +#define SDRAM_SIZE (uint32)__SDRAM_SIZE + + + + +/********************************************************************/ +/* __initialize_hardware Startup code routine + * + * __initialize_hardware is called by the startup code right after reset, + * with interrupt disabled and SP pre-set to a valid memory area. + * Here you should initialize memory and some peripherics; + * at this point global variables are not initialized yet. + * The startup code will initialize SP on return of this function. + */ +void __initialize_hardware(void); + +/********************************************************************/ +/* __initialize_system Startup code routine + * + * __initialize_system is called by the startup code when all languages + * specific initialization are done to allow additional hardware setup. + */ +void __initialize_system(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSINIT_H__ */ + + diff --git a/BaS_codewarrior/workspace.cww b/BaS_codewarrior/workspace.cww new file mode 100644 index 0000000..2d84375 --- /dev/null +++ b/BaS_codewarrior/workspace.cww @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> + + + + -1 + 0 + true + firebeeV1\firebeeV1.mcp + + 938 + 306 + + + 392 + 338 + + + 1 + 0 + 0 + 59420 + 1.000000 + 378 + + 0 + 0 + + + + + -1 + 1 + firebeeV1\sources\exceptions.s + + 8 + 34 + + + 549 + 895 + + + 0 + + + + + + + + + + + + + 1073741824 + 35 + + 60 + 205 + + + 582 + 392 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf + 2 + + + + 1073741824 + 35 + + 1586 + 31 + + + 484 + 907 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf + 4 + + + + 1073741824 + 35 + + 1185 + 39 + + + 481 + 225 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf + 5 + + + + 1073741824 + 35 + + 1100 + 691 + + + 481 + 225 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf + 3 + + + + 1073741824 + 35 + + 645 + 600 + + + 481 + 225 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf + 1 + + + + -2147483648 + 24 + + 13 + 33 + + + 591 + 742 + + + 0 + + + + + + + + + + + + + -2147483648 + 28 + + 652 + 33 + + + 518 + 519 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf + 0 + 373 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1073741824 + 28 + + 652 + 33 + + + 518 + 519 + + + 0 + + + + + + + + + + + GlobalSession, cpu68K, osCWDS + C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf + 0 + 373 + + + + + diff --git a/FPGA_quartus/Coldari1.qsf b/FPGA_quartus/Coldari1.qsf new file mode 100644 index 0000000..da581cf --- /dev/null +++ b/FPGA_quartus/Coldari1.qsf @@ -0,0 +1,44 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 222 10/21/2009 SJ Web Edition +# Date created = 12:11:46 March 06, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Coldari1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name DEVICE AUTO +set_global_assignment -name TOP_LEVEL_ENTITY Coldari1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46 MARCH 06, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 \ No newline at end of file diff --git a/FPGA_quartus/DSP/DSP.vhd b/FPGA_quartus/DSP/DSP.vhd new file mode 100644 index 0000000..26f8e2e --- /dev/null +++ b/FPGA_quartus/DSP/DSP.vhd @@ -0,0 +1,79 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:57 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY DSP IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nRSTO : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nSRCS : INOUT STD_LOGIC; + nSRBLE : OUT STD_LOGIC; + nSRBHE : OUT STD_LOGIC; + nSRWE : OUT STD_LOGIC; + nSROE : OUT STD_LOGIC; + DSP_INT : OUT STD_LOGIC; + DSP_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + IO : INOUT STD_LOGIC_VECTOR(17 downto 0); + SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END DSP; + + +-- Architecture Body + +ARCHITECTURE DSP_architecture OF DSP IS + + +BEGIN + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + DSP_INT <= '0'; + DSP_TA <= '0'; + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + + +END DSP_architecture; diff --git a/FPGA_quartus/DSP/DSP.vhd.bak b/FPGA_quartus/DSP/DSP.vhd.bak new file mode 100644 index 0000000..2d4811a --- /dev/null +++ b/FPGA_quartus/DSP/DSP.vhd.bak @@ -0,0 +1,79 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:57 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY DSP IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nRSTO : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nSRCS : OUT STD_LOGIC; + nSRBLE : OUT STD_LOGIC; + nSRBHE : OUT STD_LOGIC; + nSRWE : OUT STD_LOGIC; + nSROE : OUT STD_LOGIC; + DSP_INT : OUT STD_LOGIC; + DSP_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + IO : INOUT STD_LOGIC_VECTOR(17 downto 0); + SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END DSP; + + +-- Architecture Body + +ARCHITECTURE DSP_architecture OF DSP IS + + +BEGIN + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + DSP_INT <= '0'; + DSP_TA <= '0'; + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + + +END DSP_architecture; diff --git a/FPGA_quartus/DSP/dsp56k.zip b/FPGA_quartus/DSP/dsp56k.zip new file mode 100644 index 0000000000000000000000000000000000000000..6522299f5635ba5560150e498fbbdf0fde8328f5 GIT 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std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type +); +end entity; + + +architecture rtl of adgen_stage is + + signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0); + + +begin + + address_out_x <= address_out_x_int; + + address_generator_X: process(activate_adgen, instr_word, register_file, adgen_mode_a) is + variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable op1 : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable addr_mod : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0); + variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0); + variable bit_set : std_logic; + begin + r_reg_local := register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8)))); + n_reg_local := register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8)))); + m_reg_local := register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8)))); + + -- select the operands for the calculation + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => addr_mod := unsigned(- signed(n_reg_local)); + -- (Rn) + Nn + when POST_PLUS_N => addr_mod := n_reg_local; + -- (Rn)- + when POST_MIN_1 => addr_mod := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when NOP => addr_mod := (others => '0'); + -- (Rn + Nn) + when INDEXED_N => addr_mod := n_reg_local; + -- -(Rn) + when PRE_MIN_1 => addr_mod := (others => '1'); -- - 1 + -- absolute address (appended to instruction word) + when ABSOLUTE => addr_mod := (others => '0'); + when IMMEDIATE => addr_mod := (others => '0'); + end case; + + op1 := r_reg_local; + op2 := addr_mod; + -- linear addressing + if m_reg_local = 2**BW_ADDRESS-1 then + op1 := r_reg_local; + op2 := addr_mod; + -- bit reverse operation + elsif m_reg_local = 0 then + -- reverse the input to the adder bit wise + -- so we just need to use a single adder + for i in 0 to BW_ADDRESS-1 loop + op1(BW_ADDRESS - 1 - i) := r_reg_local(i); + op2(BW_ADDRESS - 1 - i) := addr_mod(i); + end loop; + -- modulo arithmetic + else + bit_set := '0'; + for i in BW_ADDRESS-1 downto 0 loop + if m_reg_local(i) = '1' then + bit_set := '1'; + end if; + if bit_set = '1' then + modulo_bitmask(i) := '0'; + else + modulo_bitmask(i) := '1'; + end if; + end loop; + end if; + + new_r_reg_interm := op1 + op2; + + new_r_reg := new_r_reg_interm; + -- linear addressing + if m_reg_local = 2**BW_ADDRESS-1 then + new_r_reg := new_r_reg_interm; + -- bit reverse operation + elsif m_reg_local = 0 then + for i in 0 to BW_ADDRESS-1 loop + new_r_reg(BW_ADDRESS - 1 - i) := new_r_reg_interm(i); + end loop; + else + + end if; + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + -- LUA instructions DO NOT UPDATE the source register!! + if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then + wr_R_port_A_valid <= '0'; + else + wr_R_port_A_valid <= '1'; + end if; + wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8)); + wr_R_port_A.reg_value <= new_r_reg; + + -- select the output of the AGU + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => address_out_x_int <= r_reg_local; + -- (Rn) + Nn + when POST_PLUS_N => address_out_x_int <= r_reg_local; + -- (Rn)- + when POST_MIN_1 => address_out_x_int <= r_reg_local; + -- (Rn)+ + when POST_PLUS_1 => address_out_x_int <= r_reg_local; + -- (Rn) + when NOP => address_out_x_int <= r_reg_local; + -- (Rn + Nn) + when INDEXED_N => address_out_x_int <= new_r_reg; + -- -(Rn) + when PRE_MIN_1 => address_out_x_int <= new_r_reg; + -- absolute address (appended to instruction word) + when ABSOLUTE => address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0)); + when IMMEDIATE => address_out_x_int <= r_reg_local; -- Done externally, value never used + end case; + -- LUA instructions only use the updated address! + if instr_array = INSTR_LUA then + address_out_x_int <= new_r_reg; + end if; + + end process address_generator_X; + + address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word, + register_file, adgen_mode_b, address_out_x_int) is + variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + begin + r_reg_local := register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + n_reg_local := register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + m_reg_local := register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + + -- select the operands for the calculation + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => op2 := n_reg_local; + -- (Rn)- + when POST_MIN_1 => op2 := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => op2 := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when others => op2 := (others => '0'); + end case; + + new_r_reg := r_reg_local + op2; + -- TODO: USE modifier register! + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + if adgen_mode_b = NOP then + wr_R_port_B_valid <= '0'; + else + wr_R_port_B_valid <= '1'; + end if; + wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13)); + wr_R_port_B.reg_value <= new_r_reg; + + -- the address for the y memory is calculated in the first AGU if the x memory is not accessed! + -- so use the other output as address output for the y memory! + -- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!) + if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then + address_out_y <= address_out_x_int; + -- in any other case use the locally computed value + else + -- select the output of the AGU + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => address_out_y <= r_reg_local; + -- (Rn)- + when POST_MIN_1 => address_out_y <= r_reg_local; + -- (Rn)+ + when POST_PLUS_1 => address_out_y <= r_reg_local; + -- (Rn) + when others => address_out_y <= r_reg_local; + end case; + end if; + end process address_generator_Y; + +end architecture; diff --git a/FPGA_quartus/DSP/src/constants_pkg.vhd b/FPGA_quartus/DSP/src/constants_pkg.vhd new file mode 100644 index 0000000..4b8122d --- /dev/null +++ b/FPGA_quartus/DSP/src/constants_pkg.vhd @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +package constants_pkg is + + ------------------------- + -- Flags in CCR register + ------------------------- + constant C_FLAG : natural := 0; + constant V_FLAG : natural := 1; + constant Z_FLAG : natural := 2; + constant N_FLAG : natural := 3; + constant U_FLAG : natural := 4; + constant E_FLAG : natural := 5; + constant L_FLAG : natural := 6; + constant S_FLAG : natural := 7; + + ------------------- + -- Pipeline stages + ------------------- + constant ST_FETCH : natural := 0; + constant ST_FETCH2 : natural := 1; + constant ST_DECODE : natural := 2; + constant ST_ADGEN : natural := 3; + constant ST_EXEC : natural := 4; + + ---------------------- + -- Activation signals + ---------------------- + constant ACT_ADGEN : natural := 0; -- Run the address generator + constant ACT_ALU : natural := 1; -- Activation of ALU results in modification of the status register + constant ACT_EXEC_BRA : natural := 2; -- Branch (in execute stage) + constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage) + constant ACT_EXEC_LOOP : natural := 4; -- Loop instruction (REP, DO) + constant ACT_X_MEM_RD : natural := 5; -- Init read from X memory + constant ACT_Y_MEM_RD : natural := 6; -- Init read from Y memory + constant ACT_P_MEM_RD : natural := 7; -- Init read from P memory + constant ACT_X_MEM_WR : natural := 8; -- Init write to X memory + constant ACT_Y_MEM_WR : natural := 9; -- Init write to Y memory + constant ACT_P_MEM_WR : natural := 10; -- Init write to P memory + constant ACT_REG_RD : natural := 11; -- Read from register (6 bit addressing) + constant ACT_REG_WR : natural := 12; -- Write to register (6 bit addressing) + constant ACT_IMM_8BIT : natural := 13; -- 8 bit immediate operand (in instruction word) + constant ACT_IMM_12BIT : natural := 14; -- 12 bit immediate operand (in instruction word) + constant ACT_IMM_LONG : natural := 15; -- 24 bit immediate operant (in optional instruction word) + constant ACT_X_BUS_RD : natural := 16; -- Read data via X-bus (from x0,x1,a,b) + constant ACT_X_BUS_WR : natural := 17; -- Write data via X-bus (to x0,x1,a,b) + constant ACT_Y_BUS_RD : natural := 18; -- Read data via Y-bus (from y0,y1,a,b) + constant ACT_Y_BUS_WR : natural := 19; -- Write data via Y-bus (to y0,y1,a,b) + constant ACT_L_BUS_RD : natural := 20; -- Read data via L-bus (from a10, b10,x,y,a,b,ab,ba) + constant ACT_L_BUS_WR : natural := 21; -- Write data via L-bus (to a10, b10,x,y,a,b,ab,ba) + constant ACT_BIT_MOD_WR : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG) + constant ACT_REG_WR_CC : natural := 23; -- Write to register file conditionally (Tcc) + constant ACT_ALU_WR_CC : natural := 24; -- Write ALU result conditionally (Tcc) + constant ACT_NORM : natural := 25; -- NORM instruction needs special handling + +end package constants_pkg; diff --git a/FPGA_quartus/DSP/src/decode_stage.vhd b/FPGA_quartus/DSP/src/decode_stage.vhd new file mode 100644 index 0000000..0c62149 --- /dev/null +++ b/FPGA_quartus/DSP/src/decode_stage.vhd @@ -0,0 +1,1221 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type +); +end entity; + + +architecture rtl of decode_stage is + + signal instr_array_int : instructions_type; +-- signal activate_pm_int : std_logic; + type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y); + -- SINGLE_X : MMMRRR + -- SINGLE_X_SHORT : MMRRR + -- DOUBLE_X_Y : mmrrMMRRR + signal adgen_bittype : adgen_bittype_type; + + signal ea_extension_available : std_logic; + + signal alu_tcc_decoded : std_logic; + signal alu_div_decoded : std_logic; + signal alu_norm_decoded : std_logic; + +begin + + + -- output the decoded instruction + instr_array <= instr_array_int; + + -- calculate whether this is a double word instruction + dble_word_instr <= '1' when ea_extension_available = '1' or + instr_array_int = INSTR_DO or + instr_array_int = INSTR_JCLR or + instr_array_int = INSTR_JSCLR or + instr_array_int = INSTR_JSET or + instr_array_int = INSTR_JSSET else + '0'; + + alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded, + alu_div_decoded, alu_norm_decoded) is + variable instr_word_var : std_logic_vector(23 downto 0); + begin + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + alu_ctrl.mul_op1 <= (others => '0'); + alu_ctrl.mul_op2 <= (others => '0'); + alu_ctrl.rotate <= '0'; + alu_ctrl.div_instr <= '0'; + alu_ctrl.norm_instr <= '0'; + alu_ctrl.shift_src <= '0'; + alu_ctrl.shift_src_sign <= (others => '0'); + alu_ctrl.shift_mode <= ZEROS; + alu_ctrl.add_src_stage_1 <= (others => '0'); + alu_ctrl.add_src_stage_2 <= (others => '0'); + alu_ctrl.add_src_sign <= (others => '0'); + alu_ctrl.logic_function <= (others => '0'); + alu_ctrl.word_24_update <= '0'; + alu_ctrl.rounding_used <= (others => '0'); + alu_ctrl.store_result <= '0'; + for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C) + alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH; + end loop; + alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations + + -- check wether instruction that allows parallel moves + -- has to be decoded, then it is an ALU operation in the 8 LSBs + -- Only exceptions are DIV, NORM, and Tcc + if instr_word_var(23 downto 20) /= "0000" then + -- ABS + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- source/dst are the same register + alu_ctrl.shift_src_sign <= "10"; -- the sign of the operand depends on the operand + -- negative operand will negate the content of the accu as + -- needed by the ABS instruction + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags but carry + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "10"; -- add carry to result of addition + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADD + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- AND / OR / EOR + if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and + instr_word_var(2 downto 0) = "010" or -- or + instr_word_var(2 downto 0) = "011") then -- eor + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not + alu_ctrl.word_24_update <= '1'; -- only accumulator bits 47 downto 24 affected? + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- ASL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ASR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags +-- alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; +-- alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CLR + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- CMP + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CMPM + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "111" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "10"; -- with the sign dependant sign (magnitude!) + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "10"; -- with sign dependant sign (magnitude!) + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- MPY, MPYR, MAC, MACR + if instr_word_var(7) = '1' then + case instr_word_var(6 downto 4) is + when "000" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0 + when "001" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0 + when "010" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0 + when "011" => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0 + when "100" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1 + when "101" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0 + when "110" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0 + when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1 + end case; + alu_ctrl.store_result <= '1'; -- store result in accu + alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder! + alu_ctrl.add_src_sign <= '0' & instr_word_var(2); -- select +/- + alu_ctrl.rounding_used <= '0' & instr_word_var(0); -- rounding is determined by that bit! + if instr_word_var(1) = '0' then -- MPY(R) + alu_ctrl.shift_mode <= ZEROS; + else -- MAC(R) + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + end if; + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NEG + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; +-- alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to +-- alu_ctrl.shift_src_sign <= "01"; -- with negative sign + -- Read Accu + alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register + alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NOT + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- select not operation + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- RND + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "01"; -- normal rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ROL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- ROR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- SBC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "11"; -- subtract carry + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUB + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- TFR + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then + -- do not read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- do not set any flag at all! + end if; + -- TST + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then + -- do not read accu + alu_ctrl.shift_mode <= NO_SHIFT; -- no shift + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.shift_src_sign <= "00"; -- sign unchanged + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '0'; -- do not store the result + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + end if; -- Parallel move ALU instructions + + -- Tcc + if alu_tcc_decoded = '1' then + -- Read source + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + -- The .store_result flag is generated in the execute stage + -- depending on the condition codes + -- do not set any flag at all! + end if; +--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--shift_src : std_logic; -- a,b +--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved +--shift_mode : alu_shift_mode; +--add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b +--add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved +--add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction! +--logic_function : std_logic_vector(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not +--word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? +--rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry +--store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator +--dst_accu : std_logic; -- 0: a, 1: b + -- DIV + if alu_div_decoded = '1' then + alu_ctrl.store_result <= '1'; -- do store the result + -- shifter operation + alu_ctrl.shift_mode <= SHIFT_LEFT; -- shift left + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.div_instr <= '1'; -- this is THE div instruction, special handling needed + -- source operand loading + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + alu_ctrl.add_src_sign <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] + -- if 1: positive, if 0: negative + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY; + end if; + -- NORM + if alu_norm_decoded = '1' then + -- set all alu-ctrl signals to ASL/ASR already here + -- depending on the condition code registers the flags + -- will be completed in the execute stage + alu_ctrl.norm_instr <= '1'; + -- Read accu + --alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + + end if; + end process; + + + instruction_decoder: process(instr_word, activate_dec) is + variable instr_word_var : std_logic_vector(23 downto 0); + procedure activate_AGU is + begin + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + end procedure activate_AGU; + begin + instr_array_int <= INSTR_NOP; + act_array <= (others => '0'); + adgen_bittype <= NOP; + reg_rd_addr <= (others => '0'); + reg_wr_addr <= (others => '0'); + x_bus_rd_addr <= (others => '0'); + x_bus_wr_addr <= (others => '0'); + y_bus_rd_addr <= (others => '0'); + y_bus_wr_addr <= (others => '0'); + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + + alu_tcc_decoded <= '0'; + alu_div_decoded <= '0'; + alu_norm_decoded <= '0'; + + -- in case the decoding is not activated we insert a nop + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + if instr_word_var(23 downto 16) = X"00" then + case instr_word_var(15 downto 0) is + when X"0000" => instr_array_int <= INSTR_NOP; + when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1'; + when X"0005" => instr_array_int <= INSTR_ILLEGAL; + when X"0006" => instr_array_int <= INSTR_SWI; + when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1'; + when X"0084" => instr_array_int <= INSTR_RESET; + when X"0086" => instr_array_int <= INSTR_WAIT; + when X"0087" => instr_array_int <= INSTR_STOP; + when X"008C" => instr_array_int <= INSTR_ENDDO; + act_array(ACT_EXEC_LOOP) <= '1'; + when others => + act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register + if instr_word_var(7 downto 2) = "101110" then + instr_array_int <= INSTR_ANDI; + elsif instr_word_var(7 downto 2) = "111110" then + instr_array_int <= INSTR_ORI; + end if; + end case; + end if; + --------------------------------------------------------- + -- DIV and NORM + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"01" then + -- DIV + if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then + alu_div_decoded <= '1'; + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- NORM + if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and + instr_word_var(2 downto 0) = "101" then + alu_norm_decoded <= '1'; + act_array(ACT_NORM) <= '1'; -- NORM instruction decoded, + -- special handling in exec-stage is caused + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + end if; + end if; + --------------------------------------------------------- + -- Tcc + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and + instr_word_var(2 downto 0) = "000" then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and + instr_word_var(7) = '0' then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + act_array(ACT_REG_WR_CC) <= '1'; + reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn + reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn + end if; + end if; + --------------------------------------------------------- + -- MOVEC and LUA instruction with registers + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"04" then + act_array(ACT_REG_WR) <= '1'; + -- LUA instruction + if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then + instr_array_int <= INSTR_LUA; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + -- MOVEC instruction (S1, D2) or (S2, D1) + if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_REG_RD) <= '1'; + -- Write D1 + if instr_word_var(15) = '1' then + reg_wr_addr <= instr_word_var(5 downto 0); + reg_rd_addr <= instr_word_var(13 downto 8); + -- Read S1 + else + reg_wr_addr <= instr_word_var(13 downto 8); + reg_rd_addr <= instr_word_var(5 downto 0); + end if; + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with memory access/absolute address + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and + instr_word_var(7) = '0' and instr_word_var(5) = '1' then + + instr_array_int <= INSTR_MOVEC; + -- read from memory, write to register + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + -- X Memory read? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- write to memory, read register + else + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + -- X Memory write? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with immediate + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + --------------------------------- + -- REP or DO loop? + --------------------------------- + if instr_word_var(23 downto 16) = X"06" then + -- Instruction encoding is the same for both except of this bit + if instr_word_var(5) = '1' then + instr_array_int <= INSTR_REP; + else + instr_array_int <= INSTR_DO; + end if; + act_array(ACT_EXEC_LOOP) <= '1'; + -- Init reading of loop counter from memory + if instr_word_var(15) = '0' and instr_word_var(7) = '0' then + -- X/Y: ea? + if instr_word_var(14) = '1' then + act_array(ACT_ADGEN) <= '1'; + end if; + -- X/Y: aa? + -- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not! + -- If not the absolute address stored in the instruction word is used. + ------- + -- only a single memory access is required + adgen_bittype <= SINGLE_X; + -- X/Y as source? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then + -- S (register as source) + reg_rd_addr <= instr_word_var(13 downto 8); + act_array(ACT_REG_RD) <= '1'; + -- #xxx ,12 bit immediate + elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then + act_array(ACT_IMM_12BIT) <= '1'; + end if; + end if; + -------------------------------- + -- MOVEM (Program memory move) + -------------------------------- + if instr_word_var(23 downto 16) = X"07" then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_RD) <= '1'; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_WR) <= '1'; + end if; + -- AGU needed? + if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -------------------------------- + -- MOVEP (Peripheral memory move) + -------------------------------- + if instr_word_var(23 downto 16) = "0000100-" then + -- TODO?? Why parallel moves in software model?? + case instr_word_var(15 downto 0) is +-- when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1'; + when others => + end case; + end if; + -- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR + if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then + + reg_rd_addr <= instr_word_var(13 downto 8); + reg_wr_addr <= instr_word_var(13 downto 8); + + if instr_word_var(16) = '0' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCLR; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BSET; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSET; + end if; + elsif instr_word_var(16) = '1' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCHG; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BTST; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JSCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSSET; + end if; + end if; + if instr_word_var(7) = '1' then + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + -- memory access? + if instr_word_var(15) = '0' then + -- X: + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_X_MEM_WR) <= '1'; + end if; + -- Y: + else + act_array(ACT_Y_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + end if; + + case instr_word_var(15 downto 14) is + -- X:/Y: aa + when "00" => + + -- X:/Y: ea + when "01" => + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + + -- X:/Y: pp + -- TODO! + when "10" => + + when others => -- "11" + if instr_word_var(7 downto 0) = "10000000" then + -- JMP/JSR ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JMP; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSR; + end if; + elsif instr_word_var(7 downto 4) = "1010" then + -- JCC/JSCC ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JCC; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSCC; + end if; + -- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D + else + act_array(ACT_REG_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_REG_WR) <= '1'; + end if; + end if; + end case; + end if; + -- JMP xxx (absoulute short) + if instr_word_var(23 downto 16) = X"0C" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JMP; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JSR xxx (absolute short) + if instr_word_var(23 downto 16) = X"0D" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JSR; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0E" then + instr_array_int <= INSTR_JCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + -- JSCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0F" then + instr_array_int <= INSTR_JSCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + ------------------------------------------------ + -- PARALLEL MOVE SECTION!! + ------------------------------------------------ + -- Here are the ALU operations that allow for parallel moves + if instr_word_var(23 downto 20) /= "0000" then + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- PM: I + if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(20 downto 16); + end if; + -- PM: R + if instr_word_var(23 downto 18) = "001000" then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(12 downto 8); + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(17 downto 13); + end if; + -- PM: U + if instr_word_var(23 downto 13) = "00100000010" then + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + end if; + -- PM: X or PM:Y + if instr_word_var(23 downto 22) = "01" and + -- Check whether L: type parallel move. If so do not enter this branch! + not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory read? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory write? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -- PM: X:R or R:Y (Class I) + if instr_word_var(23 downto 20) = "0001" then + adgen_bittype <= SINGLE_X; + -- X:R + if instr_word_var(14) = '0' then + x_bus_rd_addr <= instr_word_var(19 downto 18); + x_bus_wr_addr <= instr_word_var(19 downto 18); + y_bus_rd_addr <= '1' & instr_word_var(17); + y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs! + -- S2,D2 in any case! + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_X_BUS_RD) <= '1'; + end if; + -- R:Y + elsif instr_word_var(14) = '1' then + x_bus_rd_addr <= '1' & instr_word_var(19); + x_bus_wr_addr <= '0' & instr_word_var(18); + y_bus_rd_addr <= instr_word_var(17 downto 16); + y_bus_wr_addr <= instr_word_var(17 downto 16); + -- S1,D1 in any case! + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_Y_MEM_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_Y_MEM_WR) <= '1'; + act_array(ACT_Y_BUS_RD) <= '1'; + end if; + + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: X:R or R:Y (Class II) + if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then + act_array(ACT_REG_RD) <= '1'; + -- X:R + if instr_word_var(15) = '0' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory + x_bus_rd_addr <= "00"; -- read x0 + x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- R:Y + elsif instr_word_var(15) = '1' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory + y_bus_rd_addr <= "00"; -- read y0 + y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: L: + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then + -- Read S? + if instr_word_var(15) = '0' then + act_array(ACT_L_BUS_RD) <= '1'; + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_Y_MEM_WR) <= '1'; + else -- Write D + act_array(ACT_L_BUS_WR) <= '1'; + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + if instr_word_var(14) = '1' then + adgen_bittype <= SINGLE_X; + activate_AGU; + else + -- L:aa automatically performed in ADGEN stage + end if; + end if; + -- PM: X: Y: + if instr_word_var(23) = '1' then + adgen_bittype <= DOUBLE_X_Y; + -- No immediate value allowed, so activate in any case! + act_array(ACT_ADGEN) <= '1'; + -- S1, X: + if instr_word_var(15) = '0' then + act_array(ACT_X_BUS_RD) <= '1'; + x_bus_rd_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_WR) <= '1'; + -- X:, D1 + else + act_array(ACT_X_BUS_WR) <= '1'; + x_bus_wr_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_RD) <= '1'; + end if; + -- S2, Y: + if instr_word_var(22) = '0' then + act_array(ACT_Y_BUS_RD) <= '1'; + y_bus_rd_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_WR) <= '1'; + -- Y:, D2 + else + act_array(ACT_Y_BUS_WR) <= '1'; + y_bus_wr_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + end if; + end process; + + adgen_decoder: process(adgen_bittype, instr_word) is + begin + adgen_mode_a <= NOP; + adgen_mode_b <= NOP; + ea_extension_available <= '0'; + + case adgen_bittype is + when SINGLE_X => + case instr_word(13 downto 11) is + when "000" => adgen_mode_a <= POST_MIN_N; + when "001" => adgen_mode_a <= POST_PLUS_N; + when "010" => adgen_mode_a <= POST_MIN_1; + when "011" => adgen_mode_a <= POST_PLUS_1; + when "100" => adgen_mode_a <= NOP; + when "101" => adgen_mode_a <= INDEXED_N; + when "111" => adgen_mode_a <= PRE_MIN_1; + when "110" => + if instr_word(10 downto 8) = "000" then + adgen_mode_a <= ABSOLUTE; + ea_extension_available <= '1'; + elsif instr_word(10 downto 8) = "100" then + adgen_mode_a <= IMMEDIATE; + ea_extension_available <= '1'; + else + adgen_mode_a <= NOP; -- INVALID OPCODE! + end if; + when others => + end case; + when SINGLE_X_SHORT => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= POST_MIN_N; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + when DOUBLE_X_Y => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= NOP; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + case instr_word(21 downto 20) is + when "00" => adgen_mode_b <= NOP; + when "01" => adgen_mode_b <= POST_PLUS_N; + when "10" => adgen_mode_b <= POST_MIN_1; + when "11" => adgen_mode_b <= POST_PLUS_1; + when others => + end case; + when others => + end case; + end process adgen_decoder; + +end architecture rtl; + diff --git a/FPGA_quartus/DSP/src/exec_stage_alu.vhd b/FPGA_quartus/DSP/src/exec_stage_alu.vhd new file mode 100644 index 0000000..9f3c3b9 --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_alu.vhd @@ -0,0 +1,603 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + +architecture rtl of exec_stage_alu is + + signal alu_shifter_out : signed(55 downto 0); + signal alu_shifter_carry_out : std_logic; + signal alu_shifter_overflow_out : std_logic; + + signal alu_logic_conj : signed(55 downto 0); + signal alu_multiplier_out : signed(55 downto 0); + signal alu_src_op : signed(55 downto 0); + signal alu_add_result : signed(56 downto 0); + signal alu_add_carry_out : std_logic; + signal alu_post_adder_result : signed(56 downto 0); + + signal scaling_mode : std_logic_vector(1 downto 0); + + signal modified_accu_int : signed(55 downto 0); + + signal norm_instr_asl : std_logic; + signal norm_instr_asr : std_logic; + signal norm_instr_nop : std_logic; + signal norm_update_ccr : std_logic; + +begin + + + -- store calculated value? + modify_accu <= alu_ctrl.store_result; + modified_accu <= modified_accu_int; + -- for the norm instruction we first need to determine whether we have to + -- update the CCR register or not + modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else + norm_update_ccr; + dst_accu <= alu_ctrl.dst_accu; + + scaling_mode <= register_file.sr(11 downto 10); + + + calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out, + alu_post_adder_result, modified_accu_int, alu_add_carry_out) is + begin + -- by default do not modify the flags in the status register + modified_sr <= register_file.sr; + + -- Carry flag generation + ------------------------- + case alu_ctrl.ccr_flags_ctrl(C_FLAG) is + when CLEAR => modified_sr(C_FLAG) <= '0'; + when SET => modified_sr(C_FLAG) <= '1'; + when MODIFY => + -- the carry flag can stem from the shifter or from the post adder + -- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR) + -- take the carry flag from the shifter, else from the post adder + if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and + alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting? + modified_sr(C_FLAG) <= alu_shifter_carry_out; + elsif alu_ctrl.div_instr = '1' then + modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55)); + else +-- modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57)); + modified_sr(C_FLAG) <= alu_add_carry_out; + end if; + when others => -- Don't touch + end case; + + -- Overflow flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(V_FLAG) is + when CLEAR => modified_sr(V_FLAG) <= '0'; + when SET => modified_sr(V_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(V_FLAG) <= '1'; + else + modified_sr(V_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Zero flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is + when CLEAR => modified_sr(Z_FLAG) <= '0'; + when SET => modified_sr(Z_FLAG) <= '1'; + when MODIFY => + -- in case the result is zero set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or + (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto 0) = 0) then + modified_sr(Z_FLAG) <= '1'; + else + modified_sr(Z_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Negative flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(N_FLAG) is + when CLEAR => modified_sr(N_FLAG) <= '0'; + when SET => modified_sr(N_FLAG) <= '1'; + when MODIFY => + -- in case the result is negative set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if alu_ctrl.word_24_update = '1' then + modified_sr(N_FLAG) <= std_logic(modified_accu_int(47)); + else + modified_sr(N_FLAG) <= std_logic(modified_accu_int(55)); + end if; + when others => -- Don't touch + end case; + + -- Unnormalized flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(U_FLAG) is + when CLEAR => modified_sr(U_FLAG) <= '0'; + when SET => modified_sr(U_FLAG) <= '1'; + when MODIFY => + -- Set unnormalized bit according to the scaling mode + if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or + (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or + (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then + modified_sr(U_FLAG) <= '1'; + else + modified_sr(U_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Extension flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(E_FLAG) is + when CLEAR => modified_sr(E_FLAG) <= '0'; + when SET => modified_sr(E_FLAG) <= '1'; + when MODIFY => + -- Set extension flag by default + modified_sr(E_FLAG) <= '1'; + -- Clear extension flag according to the scaling mode + case scaling_mode is + when "00" => + if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "01" => + if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "10" => + if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when others => + modified_sr(E_FLAG) <= '0'; + end case; + when others => -- Don't touch + end case; + + -- Limit flag generation (equals overflow flag generaton!) + -- Clearing of the Limit flag has to be done by the user! + ----------------------------------------------------------- + case alu_ctrl.ccr_flags_ctrl(L_FLAG) is + when CLEAR => modified_sr(L_FLAG) <= '0'; + when SET => modified_sr(L_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(L_FLAG) <= '1'; + end if; + when others => -- Don't touch + end case; + + -- Scaling flag generation (DSP56002 and up) + -------------------------------------------- + -- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB + + end process; + + + src_operand_select: process(register_file, alu_ctrl) is + begin + -- decoding according similar to JJJ representation + case alu_ctrl.add_src_stage_1 is + when "000" => + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.a; + else + alu_src_op <= register_file.b; + end if; + when "001" => -- A,B or B,A + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.b; + else + alu_src_op <= register_file.a; + end if; + when "010" => -- X + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 0) <= register_file.x1 & register_file.x0; + when "011" => -- Y + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 0) <= register_file.y1 & register_file.y0; + when "100" => -- x0 + alu_src_op(55 downto 48) <= (others => register_file.x0(23)); + alu_src_op(47 downto 24) <= register_file.x0; + alu_src_op(23 downto 0) <= (others => '0'); + when "101" => -- y0 + alu_src_op(55 downto 48) <= (others => register_file.y0(23)); + alu_src_op(47 downto 24) <= register_file.y0; + alu_src_op(23 downto 0) <= (others => '0'); + when "110" => -- x1 + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 24) <= register_file.x1; + alu_src_op(23 downto 0) <= (others => '0'); + when "111" => -- y1 + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 24) <= register_file.y1; + alu_src_op(23 downto 0) <= (others => '0'); + when others => + end case; + end process; + + alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is + begin + alu_logic_conj <= alu_shifter_out; + case alu_ctrl.logic_function is + when "110" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24); + when "010" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or alu_src_op(47 downto 24); + when "011" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24); + when "111" => + alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24); + when others => + end case; + end process; + + alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is + variable add_src_op_1 : signed(56 downto 0); + variable add_src_op_2 : signed(56 downto 0); + variable carry_const : signed(56 downto 0); + variable alu_shifter_out_57 : signed(56 downto 0); + variable alu_add_result_58 : signed(57 downto 0); + variable alu_add_result_interm : signed(56 downto 0); + variable invert_carry_flag : std_logic; + begin + + -- by default do not invert the carry + invert_carry_flag := '0'; + + -- determine whether to use multiplier output, the operand defined above, or zeros! + -- resizing is done here already. Like that we can see whether an overflow + -- occurs due to negating the source operand + case alu_ctrl.add_src_stage_2 is + when "00" => add_src_op_1 := (others => '0'); + when "10" => add_src_op_1 := resize(alu_multiplier_out, 57); + when others => add_src_op_1 := resize(alu_src_op, 57); + end case; + + -- determine the sign for the 1st operand! + case alu_ctrl.add_src_sign is + -- normal operation + when "00" => add_src_op_1 := add_src_op_1; + -- negative sign + when "01" => add_src_op_1 := - add_src_op_1; + invert_carry_flag := not invert_carry_flag; + -- change according to sign + -- performs - | accu | for the CMPM instruction + when "10" => + -- we subtract in any case, so invert the carry! + invert_carry_flag := not invert_carry_flag; + if add_src_op_1(55) = '0' then + add_src_op_1 := - add_src_op_1; + else + add_src_op_1 := add_src_op_1; + end if; + -- div instruction! + -- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative + -- add_src_op_1 holds S[23] (sign extension!) + when others => + if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or + (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then + add_src_op_1 := add_src_op_1; + else + add_src_op_1 := - add_src_op_1; +-- invert_carry_flag := not invert_carry_flag; + end if; + end case; + + alu_shifter_out_57 := resize(alu_shifter_out, 57); + + -- determine the sign for the 2nd operand (coming from the shifter)! + case alu_ctrl.shift_src_sign is + -- negative sign + when "01" => + add_src_op_2 := - alu_shifter_out_57; + -- change according to sign + -- this allows to build the magnitude (ABS, CMPM) + when "10" => + if alu_shifter_out(55) = '1' then + add_src_op_2 := - alu_shifter_out_57; + else + add_src_op_2 := alu_shifter_out_57; + end if; + when others => + add_src_op_2 := alu_shifter_out_57; + end case; + + -- determine whether carry flag has to be added or subtracted + if alu_ctrl.rounding_used = "10" then + -- add carry flag + carry_const(0) := register_file.sr(C_FLAG); + elsif alu_ctrl.rounding_used = "11" then + -- subtract carry flag + carry_const := (others => register_file.sr(0)); -- carry flag + else + carry_const := (others => '0'); + end if; + + -- add the values and calculate the carry bit + alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + + ('0' & add_src_op_2(55 downto 0)) + + ('0' & carry_const(55 downto 0)); + + -- here pops the new carry out of the adder + if invert_carry_flag = '0' then + alu_add_carry_out <= alu_add_result_interm(56); + else + alu_add_carry_out <= not alu_add_result_interm(56); + end if; + + -- calculate the last bit (56), in order to test for overflow later on + alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0); +-- alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56); + alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) + xor carry_const(56) xor alu_add_result_interm(56); + + end process alu_adder; + + + -- Adder after the normal arithmetic adder + -- This adder is responsible for +-- -- 1) carry addition +-- -- 2) carry subtration + -- 3) convergent rounding + alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is + variable post_adder_constant : signed(56 downto 0); + variable testing_constant : signed(24 downto 0); + begin + -- by default add nothing + post_adder_constant := (others => '0'); + + case alu_ctrl.rounding_used is + -- rounding dependant on scaling bits + when "01" => + case scaling_mode is + -- no scaling + when "00" => testing_constant := alu_add_result(23 downto 0) & '0'; + -- scale down + when "01" => testing_constant := alu_add_result(24 downto 0); + -- scale up + when "10" => testing_constant := alu_add_result(22 downto 0) & "00"; + when others => + testing_constant := alu_add_result(23 downto 0) & '0'; + end case; + + -- Special case! + if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then + -- add depending on bit left to the rounding position + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := alu_add_result(24); + -- scale down + when "01" => post_adder_constant(24) := alu_add_result(25); + -- scale up + when "10" => post_adder_constant(22) := alu_add_result(23); + when others => + end case; + else -- testing_constant /= X"1000000" + -- add rounding constant depending on scaling mode + -- results in round up if MSB of testing constant is set, else nothing happens + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := '1'; + -- scale down + when "01" => post_adder_constant(24) := '1'; + -- scale up + when "10" => post_adder_constant(22) := '1'; + when others => + end case; + end if; + -- no rounding + when others => + post_adder_constant := (others => '0'); + + end case; + + -- Add the result of the first adder to the constant (e.g., carry flag) + alu_post_adder_result <= alu_add_result + post_adder_constant; + + -- When rounding is used set 24 LSBs to zero! + if alu_ctrl.rounding_used = "01" then + alu_post_adder_result(23 downto 0) <= (others => '0'); + end if; + end process; + + + + alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is + begin + if alu_ctrl.logic_function /= "000" then + modified_accu_int <= alu_logic_conj; + else + modified_accu_int <= alu_post_adder_result(55 downto 0); + end if; + end process; + + + -- contains the 24*24 bit fractional multiplier + alu_multiplier : process(register_file, alu_ctrl) is + variable src_op1: signed(23 downto 0); + variable src_op2: signed(23 downto 0); + variable mul_result_interm : signed(47 downto 0); + begin + -- select source operands for multiplication + case alu_ctrl.mul_op1 is + when "00" => src_op1 := register_file.x0; + when "01" => src_op1 := register_file.x1; + when "10" => src_op1 := register_file.y0; + when others => src_op1 := register_file.y1; + end case; + case alu_ctrl.mul_op2 is + when "00" => src_op2 := register_file.x0; + when "01" => src_op2 := register_file.x1; + when "10" => src_op2 := register_file.y0; + when others => src_op2 := register_file.y1; + end case; + + -- perform integer multiplication + mul_result_interm := src_op1 * src_op2; + + -- sign extension of result + alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47)); + -- convert from two's complement representation to fractional format + -- signed integer multiplication delivers twice the sign bit, but only one is needed for the + -- fractional multiplication, so remove one and append a zero to the result + alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0'; + + end process alu_multiplier; + + + -- contains the data shifter + alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is + variable src_accu : signed(55 downto 0); + variable shift_to_perform : alu_shift_mode; + begin + -- read source accumulator + if alu_ctrl.shift_src = '0' then + src_accu := register_file.a; + else + src_accu := register_file.b; + end if; + + alu_shifter_carry_out <= '0'; + alu_shifter_overflow_out <= '0'; + + -- NORM instruction determines the shift value just + -- in time, so overwrite the flag from the alu_ctrl + -- for this instruction by the calculated value + if alu_ctrl.norm_instr = '0' then + shift_to_perform := alu_ctrl.shift_mode; + else + if norm_instr_asl = '1' then + shift_to_perform := SHIFT_LEFT; + elsif norm_instr_asr = '1' then + shift_to_perform := SHIFT_RIGHT; + else + shift_to_perform := NO_SHIFT; + end if; + end if; + + case shift_to_perform is + when NO_SHIFT => + alu_shifter_out <= src_accu; + when SHIFT_LEFT => + -- ASL, ADDL, DIV? + if alu_ctrl.word_24_update = '0' then + -- special handling for div instruction required + if alu_ctrl.div_instr = '1' then + alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG); + else + alu_shifter_out <= src_accu(54 downto 0) & '0'; + end if; + alu_shifter_carry_out <= src_accu(55); + -- detect overflow that results from left shifting + -- Needed for ASL, ADDL, DIV instructions + if src_accu(55) /= src_accu(54) then + alu_shifter_overflow_out <= '1'; + end if; + -- LSL/ROL? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(47); + if alu_ctrl.rotate = '0' then -- LSL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0'; + else -- ROL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG); + end if; + end if; + when SHIFT_RIGHT => + -- ASR? + if alu_ctrl.word_24_update = '0' then + alu_shifter_out <= src_accu(55) & src_accu(55 downto 1); + alu_shifter_carry_out <= src_accu(0); + -- LSR/ROR? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(24); + if alu_ctrl.rotate = '0' then -- LSR + alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25); + else -- ROR + alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25); + end if; + end if; + when ZEROS => + alu_shifter_out <= (others => '0'); + end case; + end process alu_shifter; + + + -- Special handling for NORM instruction + -- Determine which case occurs (see User's Manual for more information) + norm_instr_logic: process(register_file, addr_r_in) is + begin + norm_instr_asl <= '0'; + norm_instr_asr <= '0'; + + -- Either left shift + if register_file.sr(E_FLAG) = '0' and + register_file.sr(U_FLAG) = '1' and + register_file.sr(Z_FLAG) = '0' then + norm_instr_asl <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in - 1; + -- Or right shift + elsif register_file.sr(E_FLAG) = '1' then + norm_instr_asr <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in + 1; + -- Or do nothing! + else + norm_update_ccr <= '0'; + addr_r_out <= addr_r_in; + end if; + end process; + +end architecture; diff --git a/FPGA_quartus/DSP/src/exec_stage_bit_modify.vhd b/FPGA_quartus/DSP/src/exec_stage_bit_modify.vhd new file mode 100644 index 0000000..68fecbb --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_bit_modify.vhd @@ -0,0 +1,79 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_bit_modify is + + signal operand_bit : std_logic; + signal src_operand_32 : std_logic_vector(31 downto 0); + +begin + + -- this is just a helper signal to prevent the simulator + -- to stop when accessing a bit > 23. + src_operand_32 <= "00000000" & src_operand; + -- read the bit we want to test (and modify) + operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0)))); + + -- modify the Carry flag only for the bit modify instructions! + modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0'; + modified_sr <= register_file.sr(15 downto 1) & operand_bit; + + bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is + variable new_bit : std_logic; + begin + -- do nothing by default! + dst_operand <= src_operand; + bit_cond_met <= '0'; + + -- determine which bit to write + if instr_array = INSTR_BCLR then + new_bit := '0'; + elsif instr_array = INSTR_BSET then + new_bit := '1'; + else -- BCHG + new_bit := not operand_bit; + end if; + + if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then + dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit; + end if; + + + -- check for the jump instructions whether condition is met or not! + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then + if operand_bit = '0' then + bit_cond_met <= '1'; + else + bit_cond_met <= '0'; + end if; + end if; + if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + if operand_bit = '0' then + bit_cond_met <= '0'; + else + bit_cond_met <= '1'; + end if; + end if; + + end process; + + +end architecture; diff --git a/FPGA_quartus/DSP/src/exec_stage_branch.vhd b/FPGA_quartus/DSP/src/exec_stage_branch.vhd new file mode 100644 index 0000000..9b07913 --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_branch.vhd @@ -0,0 +1,117 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_branch is + + signal branch_condition_met : std_logic; + signal modify_pc_int : std_logic; + +begin + + modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0'; + modify_pc <= modify_pc_int; + + calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met) + begin + branch_condition_met <= '0'; + + -- unconditional jumps + if instr_array = INSTR_JMP or + instr_array = INSTR_JSR or + instr_array = INSTR_RTI or + instr_array = INSTR_RTS then + -- jump always + branch_condition_met <= '1'; + end if; + -- then see whether the branch condition is satisfied + if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then + branch_condition_met <= cc_flag_set; + end if; + -- jmp that is executed according to a certain bit condition + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or + instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + branch_condition_met <= bit_cond_met; + end if; + end process calculate_branch_condition; + + + calculate_branch_target : process(instr_array, instr_word, jump_address) + begin + modified_pc <= jump_address; + + -- address calculation is the same for the following instructions + if instr_array = INSTR_JMP or + instr_array = INSTR_JCC or + instr_array = INSTR_JSCC or + instr_array = INSTR_JSR then + if instr_word(18) = '1' then + -- short jump address included in opcode (bits 11 downto 0) + modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0)); + elsif instr_word(18) = '0' then + -- effective address defined by opcode and coming from address generator unit + modified_pc <= jump_address; + end if; + end if; + + -- jump address contains the obligatory address of the second + -- instruction word + if instr_array = INSTR_JCLR or + instr_array = INSTR_JSET or + instr_array = INSTR_JSCLR or + instr_array = INSTR_JSSET then + modified_pc <= jump_address; + end if; + + -- target address is stored on the stack + if instr_array = INSTR_RTS or + instr_array = INSTR_RTI then + modified_pc <= unsigned(register_file.current_ssh); + end if; + end process calculate_branch_target; + + -- Subroutine functions need to store PC and SR on the stack + push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC or instr_array = INSTR_JSR or + instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0'; + push_stack.content <= PC_AND_SR; + -- pc is set externally! + push_stack.pc <= (others => '0'); + + -- RTI/RTS instructions need to read from the stack + pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0'; + + -- some instructions require to set the SR + calculate_status_register : process(instr_array) + begin + modify_sr <= '0'; + modified_sr <= (others => '0'); + if instr_array = INSTR_RTI then + modify_sr <= '1'; + modified_sr <= register_file.current_ssl; + end if; + end process calculate_status_register; + + +end architecture rtl; diff --git a/FPGA_quartus/DSP/src/exec_stage_cc_flag_calc.vhd b/FPGA_quartus/DSP/src/exec_stage_cc_flag_calc.vhd new file mode 100644 index 0000000..63a0b2c --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_cc_flag_calc.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic +); +end entity; + + +architecture rtl of exec_stage_cc_flag_calc is + + +begin + + calculate_cc_flag : process(instr_word, instr_array, register_file) + + variable cc_select : std_logic_vector(3 downto 0); + + procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is + variable c_flag : std_logic := register_file.ccr(0); + variable v_flag : std_logic := register_file.ccr(1); + variable z_flag : std_logic := register_file.ccr(2); + variable n_flag : std_logic := register_file.ccr(3); + variable u_flag : std_logic := register_file.ccr(4); + variable e_flag : std_logic := register_file.ccr(5); + variable l_flag : std_logic := register_file.ccr(6); + + begin + if (cc = "0000" and c_flag = '0') or -- CC: carry clear + (cc = "1000" and c_flag = '1') or -- CS: carry set + (cc = "0101" and e_flag = '0') or -- EC: extension clear + (cc = "1010" and z_flag = '1') or -- EQ: equal + (cc = "1101" and e_flag = '1') or -- ES: extension set + (cc = "0001" and (n_flag = v_flag)) or -- GE: greater than or equal + (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0') or -- GT: greater than + (cc = "0110" and l_flag = '0') or -- LC: limit clear + (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1') or -- LE: less or equal + (cc = "1110" and l_flag = '1') or -- LS: limit set + (cc = "1001" and (n_flag /= v_flag)) or -- LT: less than + (cc = "1011" and n_flag = '1') or -- MI: minus + (cc = "0010" and z_flag = '0') or -- NE: not equal + (cc = "1100" and (( not u_flag and not e_flag) or z_flag) = '1') or -- NR: normalized + (cc = "0011" and n_flag = '0') or -- PL: plus + (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0') -- NN: not normalized + then + cc_flag_set <= '1'; + end if; + end procedure; + + begin + + cc_flag_set <= '0'; + + -- Rip the flags we have to test for from the instruction word + if (instr_array = INSTR_JCC and instr_word(18) = '0') or + (instr_array = INSTR_JSCC) then + cc_select := instr_word(3 downto 0); + else + cc_select := instr_word(15 downto 12); + end if; + + calculate_cc_flag(cc_select); + + end process; + + +end architecture; diff --git a/FPGA_quartus/DSP/src/exec_stage_cr_mod.vhd b/FPGA_quartus/DSP/src/exec_stage_cr_mod.vhd new file mode 100644 index 0000000..c236db7 --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_cr_mod.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cr_mod is port ( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) +); +end exec_stage_cr_mod; + + +architecture rtl of exec_stage_cr_mod is + +begin + + process(activate_exec_cr_mod, instr_word, instr_array, register_file) is + variable imm8 : std_logic_vector(7 downto 0); + variable op8 : std_logic_vector(7 downto 0); + variable res8 : std_logic_vector(7 downto 0); + begin + modify_sr <= '0'; + modify_omr <= '0'; + modified_sr <= (others => '0'); + modified_omr <= (others => '0'); + + imm8 := instr_word(15 downto 8); + if instr_word(1 downto 0) = "00" then + -- read MR + op8 := register_file.mr; + elsif instr_word(1 downto 0) = "01" then + -- read CCR + op8 := register_file.ccr; + else -- instr_word(1 downto 0) = "10" + -- read OMR + op8 := register_file.omr; + end if; + + if instr_array = INSTR_ANDI then + res8 := imm8 and op8; + else -- instr_array = INSTR_ORI + res8 := imm8 or op8; + end if; + + -- only write the result when activated + if activate_exec_cr_mod = '1' then + if instr_word(1 downto 0) = "00" then + -- update MR + modify_sr <= '1'; + modified_sr <= res8 & register_file.ccr; + elsif instr_word(1 downto 0) = "01" then + -- update CCR + modify_sr <= '1'; + modified_sr <= register_file.mr & res8; + elsif instr_word(1 downto 0) = "10" then + -- update OMR + modify_omr <= '1'; + modified_omr <= res8; + end if; + end if; + end process; + +end architecture; diff --git a/FPGA_quartus/DSP/src/exec_stage_loops.vhd b/FPGA_quartus/DSP/src/exec_stage_loops.vhd new file mode 100644 index 0000000..cc32692 --- /dev/null +++ b/FPGA_quartus/DSP/src/exec_stage_loops.vhd @@ -0,0 +1,200 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_loop is + + signal rep_loop_polling : std_logic; + signal do_loop_polling : std_logic; + signal enddo_polling : std_logic; + signal lc_temp : unsigned(15 downto 0); + signal rf_lc_eq_1 : std_logic; + signal memory_stall_t : std_logic; + +begin + + modified_pc <= loop_start_address; + + + -- loop counter in register file equal to 1? + rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0'; + + process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo, + rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is + begin + stall_rep <= '0'; + stall_do <= '0'; + + modify_la <= '0'; + modify_lc <= '0'; + modify_pc <= '0'; + modify_sr <= '0'; + modified_la <= loop_address; + modified_lc <= loop_iterations; -- default + -- set the loop flag LF (bit 15) of Status register + modified_sr(15) <= '1'; + modified_sr(14 downto 0) <= register_file.sr(14 downto 0); + + push_stack.valid <= '0'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= LA_AND_LC; + + pop_stack.valid <= '0'; + decrement_lc <= '0'; + ------------------ + -- DO instruction + ------------------ + if activate_exec_loop = '1' and instr_array = INSTR_DO then + -- first instruction of the do loop instruction? + if do_loop_polling = '0' then + stall_do <= '1'; + modify_lc <= '1'; -- store the new loop counter + modify_la <= '1'; -- store the new loop address + push_stack.valid <= '1'; -- push LA and LC on the stack + push_stack.content <= LA_AND_LC; + else -- second clock cycle of the do loop instruction ? + push_stack.valid <= '1'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= PC_AND_SR; + -- set the PC to the first instruction of the loop + -- the already fetched instruction are flushed from the pipeline + -- this prevents problems, when the loop consists of only one or two instructions + modify_pc <= '1'; + -- set the loop flag + modify_sr <= '1'; + end if; + end if; + ----------------------------------------------- + -- ENDDO instruction / loop end in fetch stage + ----------------------------------------------- + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then + pop_stack.valid <= '1'; + if enddo_polling = '0' then + -- only restore the LF from the stack + modified_sr(15) <= register_file.current_ssl(15); + modify_sr <= '1'; + stall_do <= '1'; -- stall one clock cycle + else + -- restore loop counter and loop address in second clock cycle + modified_lc <= unsigned(register_file.current_ssl); + modify_lc <= '1'; + modified_la <= unsigned(register_file.current_ssh); + modify_la <= '1'; + end if; + end if; + ------------------- + -- REP instruction + ------------------- + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + stall_rep <= '1'; -- stall the fetch and decode stages + modify_lc <= '1'; -- store the loop counter + modified_lc <= loop_iterations - 1; + end if; + end if; + + -- keep processing the single instruction + if rep_loop_polling = '1' then + stall_rep <= '1'; + -- if the REP instruction cause a stall do not modify the lc! + if memory_stall_t = '0' then + if rf_lc_eq_1 = '0' then + decrement_lc <= '1'; + -- when the instruction to repeat caused a memory stall + -- do not continue! + else + -- finish the REP instruction by restoring the LC + stall_rep <= '0'; + modify_lc <= '1'; + modified_lc <= lc_temp; + end if; + end if; + end if; + end process; + + + -- process that allows to remember that we are processing a REP/DO instruction + -- even though the REP instruction is not available in the pipeline anymore + -- also store the old loop counter + process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + rep_loop_polling <= '0'; + do_loop_polling <= '0'; + enddo_polling <= '0'; + lc_temp <= (others => '0'); + memory_stall_t <= '0'; + else + memory_stall_t <= memory_stall; + + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + rep_loop_polling <= '1'; + lc_temp <= register_file.lc; + end if; + end if; + -- test whether the REP instruction has been executed + if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0' then + rep_loop_polling <= '0'; + end if; + + -- do loop execution takes two clock cycles + -- in the first clock cycle we store loop address and loop counter on the stack + -- in the second clock cycle we store programm counter and status register on the stack + if activate_exec_loop = '1' and instr_array = INSTR_DO then + do_loop_polling <= '1'; + end if; + -- clear the flag immediately again (only two cycles execution time!) + if do_loop_polling = '1' then + do_loop_polling <= '0'; + end if; + + -- ENDDO instructions take two clock cycles as well! + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then + enddo_polling <= '1'; + end if; + if enddo_polling = '1' then + enddo_polling <= '0'; + end if; + end if; + end if; + end process; + +end architecture; diff --git a/FPGA_quartus/DSP/src/fetch_stage.vhd b/FPGA_quartus/DSP/src/fetch_stage.vhd new file mode 100644 index 0000000..6b22f09 --- /dev/null +++ b/FPGA_quartus/DSP/src/fetch_stage.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +entity fetch_stage is port( + + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + +); +end fetch_stage; + + +architecture rtl of fetch_stage is + + +begin + + pc_calculation: process(pc_old, modify_pc, modified_pc, register_file) is + begin + decrement_lc <= '0'; + perform_enddo <= '0'; + + -- by default increment pc by one + pc_new <= pc_old + 1; + if modify_pc = '1' then + pc_new <= modified_pc; + end if; + -- Loop Flag set? + if register_file.sr(15) = '1' then + if register_file.la = pc_old then + -- Loop not finished? + -- => start from the beginning if necessary + if register_file.lc /= 1 then + -- if the last address was LA and the loop is not finished yet, we have to + -- read now from the beginning of the loop again + pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0)); + -- decrement loop counter + decrement_lc <= '1'; + else + -- loop done! + -- => tell the loop controller in the exec stage to perform the enddo operation + -- (without flushing of the pipeline!) + perform_enddo <= '1'; + end if; + end if; + end if; + end process pc_calculation; + +end architecture rtl; + diff --git a/FPGA_quartus/DSP/src/mem_control.vhd b/FPGA_quartus/DSP/src/mem_control.vhd new file mode 100644 index 0000000..091fcf0 --- /dev/null +++ b/FPGA_quartus/DSP/src/mem_control.vhd @@ -0,0 +1,1519 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + +entity mem_control is + generic( + mem_type : memory_type := P_MEM + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); +end entity mem_control; + + +architecture rtl of mem_control is + + signal int_mem_rd_addr : std_logic_vector(7 downto 0); + type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0); + signal int_mem : int_mem_type; + signal int_pmem : int_mem_type := ( +-- ABS begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200026", +--X"56F400", +--X"E00000", +--X"200026", +--X"56F400", +--X"000000", +--X"200026", +--X"52F400", +--X"000080", +--X"200026", +-- ABS end + +-- ADC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200039", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200039", +-- ADC end + +-- ADD begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200038", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200038", +-- ADD end + +-- ADDL begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20001A", +--X"56F400", +--X"0000AA", +--X"20001A", +--X"53F400", +--X"000080", +--X"20001A", +-- ADDL end + +-- ADDR begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20000A", +--X"56F400", +--X"0000AA", +--X"20000A", +--X"53F400", +--X"000080", +--X"20000A", +-- ADDR end + +-- AND begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"FFF000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +-- AND end + +-- EOR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005B", +--X"46F400", +--X"FFFFFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005B", +-- EOR end + +-- OR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005A", +--X"46F400", +--X"000000", +--X"57F400", +--X"000000", +--X"0000B9", +--X"20005A", +-- OR end + +-- NOT begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"7F00FF", +--X"0000B9", +--X"20001F", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20001F", +-- NOT end + +-- ASL begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20003A", +-- ASL end + +-- ASR begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20002A", +-- ASR end + +-- CLR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200013", +--X"56F400", +--X"E00000", +--X"0000B9", +--X"0001F9", +--X"200013", +-- CLR end + +-- CMP begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005D", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005D", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005D", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005D", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005D", +-- CMP end + +-- CMPM begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005F", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005F", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005F", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005F", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005F", +-- CMPM end + +-- DIV begin +--X"00FEB9", +--X"44F400", +--X"600000", +--X"56F400", +--X"200000", +--X"0618A0", +--X"018040", +--X"210E00", +-- DIV end + +-- LSL begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200033", +-- LSL end + +-- LSR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200023", +-- LSR end + +-- MPY begin +--X"0000B9", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D0", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D4", +-- MPY end + +-- MAC begin +--X"0000B9", +--X"200013", +--X"2A8000", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D6", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D6", +-- MAC end + +-- MACR begin +--X"0000B9", +--X"200013", +--X"2E1000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"56F400", +--X"100001", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"2E1000", +--X"50F400", +--X"800000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +-- MACR end + +-- MPYR begin +--X"0000B9", +--X"46F400", +--X"654321", +--X"200095", +-- MPYR end + +-- NEG begin +--X"0000B9", +--X"56F400", +--X"654321", +--X"200036", +--X"200013", +--X"52F400", +--X"000080", +--X"200036", +--X"56F400", +--X"800000", +--X"200036", +-- NEG end + +-- NORM begin +X"200013", +X"2C0100", +X"200003", +X"062FA0", +X"01DB15", +X"200013", +X"2EFF00", +X"2A8400", +X"200003", +X"062FA0", +X"01D915", +X"200013", +X"062FA0", +X"01DA15", +-- NORM end + +-- RND begin +--X"0000B9", +--X"54F400", +--X"123456", +--X"50F400", +--X"789ABC", +--X"200011", +--X"54F400", +--X"123456", +--X"50F400", +--X"800000", +--X"200011", +--X"54F400", +--X"123455", +--X"50F400", +--X"800000", +--X"200011", +-- RND end + +-- ROR begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200027", +-- ROR end + +-- ROL begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200037", +-- ROL end + + +-- SUB begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003C", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003C", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20007C", +-- SUB end + +-- SUBL begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20001E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20001E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20001E", +-- SUBL end + +-- SUBR begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20000E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20000E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20000E", +-- SUBR end + +-- SBC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003D", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003D", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20003D", +-- SBC end + +-- TCC begin +--X"311400", +--X"44F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"0000B9", +--X"038143", +--X"03014A", +--X"0004F9", +--X"03A143", +--X"03214A", +-- TCC end + +-- TFR begin +--X"56F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"21EE09", +--X"44F400", +--X"555555", +--X"47F400", +--X"AAAAAA", +--X"21C441", +--X"21E679", +-- TFR end + +-- TST begin +--X"20001B", +--X"20000B", +--X"0000B9", +--X"0001F9", +--X"53F400", +--X"000080", +--X"20000B", +--X"53F400", +--X"00007F", +--X"20000B", +-- TST end + + +--X"2AFF00", +--X"54F400", +--X"FFFFFF", +--X"50F400", +--X"FFFFF2", +--X"200026", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +--X"44F400", +--X"100010", +--X"45F400", +--X"100011", +--X"0B5880", +--X"000017", +--X"46F400", +--X"100026", +--X"47F400", +--X"100027", +--X"425800", +--X"435800", +--X"420A00", +--X"431F00", +--X"437000", +--X"0000A0", +--X"427000", +--X"00004F", +-- X"42F800", +-- X"43F800", +-- X"428A00", +-- X"439F00", +-- "001100000100100000000000", -- 0 move #72,r0 +-- "001110000000100000000000", -- 1 move #8,n0 +-- "000001010000000010100000", -- 2 move #0,m0 +-- "000001010001000010100001", -- 3 move #16,m1 +-- "000001101110000100100000", -- 4 rep m1 +-- "010001001100100000000000", -- 5 move x:(r0)+n0,x0 +-- "000000000000000000000000", -- 6 +-- "000000000000000000000000", -- 7 +-- "000000000000000000000000", -- 8 +-- "000000000000000000000000", -- 9 +-- "000000000000000000000000", -- 10 +-- "000000000000000000000000", -- 11 +-- "000000000000000000000000", -- 12 +-- "000000000000000000000000", -- 13 +-- "000000000000000000000000", -- 14 +-- "000000000000000000000000", -- 15 +-- "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 +-- "000000000000000000000000", -- 18 +-- "000000000000000000000000", -- 19 +-- "000010101101101010000000", -- 20 -- JMP (r2)+ +-- "000000000000000000000000", -- 20 +-- "000000000000000000000000", -- 21 +-- "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_xmem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000001100", -- 0 -- REP + "000000000000000000000101", -- 1 -- ORI #$0E, MR + "000000000000111011111010", -- 2 -- ORI #$0E, OMR + "000000000000100010111010", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000000", -- 4 + "000000000000000000000000", -- 5 + "000000000000000000000000", -- 6 + "000000000000000000000000", -- 7 + "000000000000000000000000", -- 8 + "000000000000000000000000", -- 9 + "000000000000000000000000", -- 10 + "000000000000000000000000", -- 11 + "000000000000000000000000", -- 12 + "000000000000000000000000", -- 13 + "000000000000000000000000", -- 14 + "000000000000000000000000", -- 15 + "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_ymem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000000001", -- 0 -- REP + "000000000000000000000010", -- 1 -- ORI #$0E, MR + "000000000000000000000011", -- 2 -- ORI #$0E, OMR + "000000000000000000000100", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000101", -- 4 + "000000000000000000000110", -- 5 + "000000000000000000000111", -- 6 + "000000000000000000001000", -- 7 + "000000000000000000001001", -- 8 + "000000000000000000001010", -- 9 + "000000000000000000001011", -- 10 + "000000000000000000001100", -- 11 + "000000000000000000001101", -- 12 + "000000000000000000001110", -- 13 + "000000000000000000001111", -- 14 + "000000000000000000010000", -- 15 + "000000000000000000010001", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + +begin + +-- int_mem <= int_pmem when mem_type = P_MEM else +-- int_xmem when mem_type = X_MEM else +-- int_ymem when mem_type = Y_MEM; + + wr_accomplished <= wr_en; + + PMEM_GEN: if mem_type = P_MEM generate + data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_pmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + XMEM_GEN: if mem_type = X_MEM generate + data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_xmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + YMEM_GEN: if mem_type = Y_MEM generate + data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_ymem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; +-- process(clk, rst) is +-- begin +-- if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else +-- int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); +-- data_out_valid <= rd_en; +-- if wr_en = '1' then +-- if mem_type = P_MEM then +-- int_pmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = X_MEM then +-- int_xmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = Y_MEM then +-- int_ymem(to_integer(wr_addr)) <= data_in; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; + +end architecture rtl; + diff --git a/FPGA_quartus/DSP/src/memory_management.vhd b/FPGA_quartus/DSP/src/memory_management.vhd new file mode 100644 index 0000000..6a25ac8 --- /dev/null +++ b/FPGA_quartus/DSP/src/memory_management.vhd @@ -0,0 +1,206 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out +); +end memory_management; + + +architecture rtl of memory_management is + + + component mem_control is + generic( + mem_type : memory_type + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); + end component mem_control; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + + signal pmem_rd_addr : unsigned(BW_ADDRESS-1 downto 0); + signal pmem_rd_en : std_logic; + + signal xmem_rd_en : std_logic; + signal xmem_data_out : std_logic_vector(23 downto 0); + signal xmem_data_out_valid : std_logic; + signal xmem_rd_polling : std_logic; + + signal ymem_rd_en : std_logic; + signal ymem_data_out : std_logic_vector(23 downto 0); + signal ymem_data_out_valid : std_logic; + signal ymem_rd_polling : std_logic; + + signal pmem_stall_buffer : std_logic_vector(23 downto 0); + signal pmem_stall_buffer_valid : std_logic; + signal xmem_stall_buffer : std_logic_vector(23 downto 0); + signal ymem_stall_buffer : std_logic_vector(23 downto 0); + + signal stall_flags_d : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + +begin + + -- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall + -- when the pipeline wakes up, this temporal result is inserted into the pipeline + stall_buffer: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + pmem_stall_buffer <= (others => '0'); + pmem_stall_buffer_valid <= '0'; + xmem_stall_buffer <= (others => '0'); + ymem_stall_buffer <= (others => '0'); + stall_flags_d <= (others => '0'); + else + stall_flags_d <= stall_flags; + if stall_flags(ST_FETCH2) = '1' and stall_flags_d(ST_FETCH2) = '0' then + if pmem_data_out_valid = '1' then + pmem_stall_buffer <= pmem_data_out; + pmem_stall_buffer_valid <= '1'; + end if; + end if; + if stall_flags(ST_FETCH2) = '0' and stall_flags_d(ST_FETCH2) = '1' then + pmem_stall_buffer_valid <= '0'; + end if; + + + end if; + end if; + end process stall_buffer; + + memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or + ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else + '0'; + + ------------------------------- + -- PMEM CONTROLLER + ------------------------------- + inst_pmem_ctrl : mem_control + generic map( + mem_type => P_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => pmem_ctrl_in.rd_addr, + rd_en => pmem_ctrl_in.rd_en, + data_out => pmem_data_out, + data_out_valid => pmem_data_out_valid, + wr_addr => pmem_ctrl_in.wr_addr, + wr_en => pmem_ctrl_in.wr_en, + data_in => pmem_ctrl_in.data_in + ); + + -- In case we wake up from a stall use the buffered value + pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FETCH2) = '0' and + stall_flags_d(ST_FETCH2) = '1' and + pmem_stall_buffer_valid = '1' else + pmem_data_out; + + pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FETCH2) = '0' and + stall_flags_d(ST_FETCH2) = '1' else + '0' when stall_flags(ST_FETCH2) = '1' else + pmem_data_out_valid; + + ------------------------------- + -- XMEM CONTROLLER + ------------------------------- + inst_xmem_ctrl : mem_control + generic map( + mem_type => X_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => xmem_ctrl_in.rd_addr, + rd_en => xmem_rd_en, + data_out => xmem_data_out, + data_out_valid => xmem_data_out_valid, + wr_addr => xmem_ctrl_in.wr_addr, + wr_en => xmem_ctrl_in.wr_en, + data_in => xmem_ctrl_in.data_in + ); + + xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0'; + + xmem_ctrl_out.data_out <= xmem_data_out; + xmem_ctrl_out.data_out_valid <= xmem_data_out_valid; + + ------------------------------- + -- YMEM CONTROLLER + ------------------------------- + inst_ymem_ctrl : mem_control + generic map( + mem_type => Y_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => ymem_ctrl_in.rd_addr, + rd_en => ymem_rd_en, + data_out => ymem_data_out, + data_out_valid => ymem_data_out_valid, + wr_addr => ymem_ctrl_in.wr_addr, + wr_en => ymem_ctrl_in.wr_en, + data_in => ymem_ctrl_in.data_in + ); + + ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0'; + + ymem_ctrl_out.data_out <= ymem_data_out; + ymem_ctrl_out.data_out_valid <= ymem_data_out_valid; + + mem_stall_control: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + xmem_rd_polling <= '0'; + ymem_rd_polling <= '0'; + else + if xmem_rd_en = '1' then + xmem_rd_polling <= '1'; + end if; + + if xmem_data_out_valid = '1' then + xmem_rd_polling <= '0'; + end if; + + if ymem_rd_en = '1' then + ymem_rd_polling <= '1'; + end if; + + if ymem_data_out_valid = '1' then + ymem_rd_polling <= '0'; + end if; + + end if; + end if; + end process; +end architecture; + diff --git a/FPGA_quartus/DSP/src/parameter_pkg.vhd b/FPGA_quartus/DSP/src/parameter_pkg.vhd new file mode 100644 index 0000000..9e3c301 --- /dev/null +++ b/FPGA_quartus/DSP/src/parameter_pkg.vhd @@ -0,0 +1,10 @@ + +package parameter_pkg is + + constant BW_ADDRESS : natural := 16; + + constant PIPELINE_DEPTH : natural := 5; + + constant NUM_ACT_SIGNALS : natural := 26; + +end package; diff --git a/FPGA_quartus/DSP/src/pipeline.vhd b/FPGA_quartus/DSP/src/pipeline.vhd new file mode 100644 index 0000000..5b5a98e --- /dev/null +++ b/FPGA_quartus/DSP/src/pipeline.vhd @@ -0,0 +1,968 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity pipeline is port ( + clk, rst : in std_logic; + register_file_out : out register_file_type + +); +end pipeline; + +-- TODOs: +-- External memory accesses +-- ROM tables +-- Reading from SSH flag has to modify stack pointer +-- Memory access (x,y,p) and talling accordingly +-- Address Generator: ring buffers are not yet supported + +-- List of BUGS: +-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!! +-- - SBC instruction has errorneous carry flag calculation + +-- List of probable issues: +-- - Reading from XMEM/YMEM with stalls probably results in corrupted data +-- - ENDDO instruction probably has to flush the pipeline afterwards +-- - Writing to memory occurs twice, when stalls occur + +-- Things to optimize: +-- - RTS/RTI could be executed in the ADGEN Stage already +-- - DO loops always flush the pipeline. This is necessary in case we have a very short loop. +-- The single instruction of the loop then has passed the fetch stage already without the branch + + +architecture rtl of pipeline is + + signal pipeline_regs : pipeline_type; + signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + + component fetch_stage is port( + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + ); + end component fetch_stage; + + signal pc_old, pc_new : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_modify_pc : std_logic; + signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_perform_enddo: std_logic; + signal fetch_decrement_lc: std_logic; + + + component decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type + ); + end component decode_stage; + + signal dec_activate : std_logic; + signal dec_instr_word : std_logic_vector(23 downto 0); + signal dec_dble_word_instr : std_logic; + signal dec_instr_array : instructions_type; + signal dec_act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + signal dec_reg_wr_addr : std_logic_vector(5 downto 0); + signal dec_reg_rd_addr : std_logic_vector(5 downto 0); + signal dec_x_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_x_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_l_bus_addr : std_logic_vector(2 downto 0); + signal dec_adgen_mode_a : adgen_mode_type; + signal dec_adgen_mode_b : adgen_mode_type; + signal dec_alu_ctrl : alu_ctrl_type; + + component adgen_stage is port( + activate_adgen : in std_logic; + activate_x_mem : in std_logic; + activate_y_mem : in std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type + ); + end component adgen_stage; + + signal adgen_activate : std_logic; + signal adgen_activate_x_mem : std_logic; + signal adgen_activate_y_mem : std_logic; + signal adgen_activate_l_mem : std_logic; + signal adgen_instr_word : std_logic_vector(23 downto 0); + signal adgen_instr_array : instructions_type; + signal adgen_optional_ea_word : std_logic_vector(23 downto 0); + signal adgen_register_file : register_file_type; + signal adgen_mode_a : adgen_mode_type; + signal adgen_mode_b : adgen_mode_type; + signal adgen_address_out_x : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_address_out_y : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_wr_R_port_A_valid : std_logic; + signal adgen_wr_R_port_A : addr_wr_port_type; + signal adgen_wr_R_port_B_valid : std_logic; + signal adgen_wr_R_port_B : addr_wr_port_type; + + component exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_bit_modify; + + signal exec_bit_modify_instr_word : std_logic_vector(23 downto 0); + signal exec_bit_modify_instr_array : instructions_type; + signal exec_bit_modify_src_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_dst_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_bit_cond_met : std_logic; + signal exec_bit_modify_modify_sr : std_logic; + signal exec_bit_modify_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_branch; + + signal exec_bra_activate : std_logic; + signal exec_bra_instr_word : std_logic_vector(23 downto 0); + signal exec_bra_instr_array : instructions_type; + signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_bit_cond_met : std_logic; + signal exec_bra_push_stack : push_stack_type; + signal exec_bra_pop_stack : pop_stack_type; + signal exec_bra_modify_pc : std_logic; + signal exec_bra_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_modify_sr : std_logic; + signal exec_bra_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_cr_mod is port( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) + ); + end component exec_stage_cr_mod; + + signal exec_cr_mod_activate : std_logic; + signal exec_cr_mod_instr_word : std_logic_vector(23 downto 0); + signal exec_cr_mod_instr_array : instructions_type; + signal exec_cr_mod_modify_sr : std_logic; + signal exec_cr_mod_modified_sr : std_logic_vector(15 downto 0); + signal exec_cr_mod_modify_omr : std_logic; + signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0); + + component exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_loop; + + signal exec_loop_activate : std_logic; + signal exec_loop_instr_word : std_logic_vector(23 downto 0); + signal exec_loop_instr_array : instructions_type; + signal exec_loop_iterations : unsigned(15 downto 0); + signal exec_loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_register_file : register_file_type; + signal exec_loop_push_stack : push_stack_type; + signal exec_loop_pop_stack : pop_stack_type; + signal exec_loop_stall_rep : std_logic; + signal exec_loop_stall_do : std_logic; + signal exec_loop_decrement_lc : std_logic; + signal exec_loop_modify_lc : std_logic; + signal exec_loop_modified_lc : unsigned(15 downto 0); + signal exec_loop_modify_la : std_logic; + signal exec_loop_modified_la : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_pc : std_logic; + signal exec_loop_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_sr : std_logic; + signal exec_loop_modified_sr : std_logic_vector(BW_ADDRESS-1 downto 0); + + component exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_alu; + + signal exec_alu_activate : std_logic; + signal exec_alu_instr_word : std_logic_vector(23 downto 0); + signal exec_alu_ctrl : alu_ctrl_type; + signal exec_alu_addr_r_in : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_addr_r_out : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_modify_accu : std_logic; + signal exec_alu_dst_accu : std_logic; + signal exec_alu_modified_accu : signed(55 downto 0); + signal exec_alu_modify_sr : std_logic; + signal exec_alu_modified_sr : std_logic_vector(15 downto 0); + + signal exec_imm_8bit : std_logic_vector(23 downto 0); + signal exec_imm_12bit : std_logic_vector(23 downto 0); + signal exec_src_operand : std_logic_vector(23 downto 0); + signal exec_dst_operand : std_logic_vector(23 downto 0); + + component exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic + ); + end component exec_stage_cc_flag_calc; + + signal exec_cc_flag_calc_instr_word : std_logic_vector(23 downto 0); + signal exec_cc_flag_calc_instr_array : instructions_type; + signal exec_cc_flag_set : std_logic; + + component reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + dec_lc : in std_logic; + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) + ); + end component reg_file; + + signal register_file : register_file_type; + signal rf_wr_R_port_A_valid : std_logic; + signal rf_wr_R_port_B_valid : std_logic; + signal rf_reg_wr_addr : std_logic_vector(5 downto 0); + signal rf_reg_wr_addr_valid : std_logic; + signal rf_reg_wr_data : std_logic_vector(23 downto 0); + signal rf_reg_rd_addr : std_logic_vector(5 downto 0); + signal rf_reg_rd_data : std_logic_vector(23 downto 0); + signal rf_X_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_data_out : std_logic_vector(23 downto 0); + signal rf_X_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_wr_valid : std_logic; + signal rf_X_bus_data_in : std_logic_vector(23 downto 0); + signal rf_Y_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_data_out : std_logic_vector(23 downto 0); + signal rf_Y_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_wr_valid : std_logic; + signal rf_Y_bus_data_in : std_logic_vector(23 downto 0); + signal rf_L_bus_rd_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_rd_valid : std_logic; + signal rf_L_bus_wr_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_wr_valid : std_logic; + signal push_stack : push_stack_type; + signal pop_stack : pop_stack_type; + signal rf_set_sr : std_logic; + signal rf_new_sr : std_logic_vector(15 downto 0); + signal rf_set_omr : std_logic; + signal rf_new_omr : std_logic_vector(7 downto 0); + signal rf_dec_lc : std_logic; + signal rf_set_lc : std_logic; + signal rf_new_lc : unsigned(15 downto 0); + signal rf_set_la : std_logic; + signal rf_new_la : unsigned(BW_ADDRESS-1 downto 0); + signal rf_alu_wr_valid : std_logic; + + component memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out + ); + end component memory_management; + + signal memory_stall : std_logic; + signal pmem_ctrl_in : mem_ctrl_type_in; + signal pmem_ctrl_out : mem_ctrl_type_out; + signal xmem_ctrl_in : mem_ctrl_type_in; + signal xmem_ctrl_out : mem_ctrl_type_out; + signal ymem_ctrl_in : mem_ctrl_type_in; + signal ymem_ctrl_out : mem_ctrl_type_out; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + signal xmem_data_out : std_logic_vector(23 downto 0); + signal xmem_data_out_valid : std_logic; + signal ymem_data_out : std_logic_vector(23 downto 0); + signal ymem_data_out_valid : std_logic; + +begin + register_file_out <= register_file; + + -- merge all stall sources + stall_flags(ST_FETCH) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_FETCH2) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_DECODE) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_ADGEN) <= exec_loop_stall_do; +-- stall_flags(ST_ADGEN) <= '1' when memory_stall = '1' or +-- exec_loop_stall_do = '1' else '0'; +-- stall_flags(ST_EXEC) <= '0'; + stall_flags(ST_EXEC) <= exec_loop_stall_do; +-- stall_flags(ST_EXEC) <= '1' when memory_stall = '1' or +-- exec_loop_stall_do = '1' else '0'; + + shift_pipeline: process(clk, rst) is + procedure flush_pipeline_stage(stage: natural) is + begin + pipeline_regs(stage).pc <= (others => '1'); + pipeline_regs(stage).instr_word <= (others => '0'); + pipeline_regs(stage).act_array <= (others => '0'); + pipeline_regs(stage).instr_array <= INSTR_NOP; + pipeline_regs(stage).dble_word_instr <= '0'; + pipeline_regs(stage).dec_activate <= '0'; + pipeline_regs(stage).adgen_mode_a <= NOP; + pipeline_regs(stage).adgen_mode_b <= NOP; + pipeline_regs(stage).reg_wr_addr <= (others => '0'); + pipeline_regs(stage).reg_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).y_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).y_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).l_bus_addr <= (others => '0'); + pipeline_regs(stage).adgen_address_x <= (others => '0'); + pipeline_regs(stage).adgen_address_y <= (others => '0'); + pipeline_regs(stage).RAM_out_x <= (others => '0'); + pipeline_regs(stage).RAM_out_y <= (others => '0'); + pipeline_regs(stage).alu_ctrl.store_result <= '0'; + end procedure flush_pipeline_stage; + begin + if rising_edge(clk) then + if rst = '1' then + for i in 0 to PIPELINE_DEPTH-1 loop + flush_pipeline_stage(i); + end loop; + else + -- shift the pipeline registers when no stall applies + for i in 1 to PIPELINE_DEPTH-1 loop + if stall_flags(i) = '0' then + -- do not copy the pipeline registers from a stalled pipeline stage + -- for REP we do not flush +-- if stall_flags(i-1) = '1' then + if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or + (i = ST_ADGEN and memory_stall = '1' and exec_loop_stall_rep = '1') then + flush_pipeline_stage(i); + else + pipeline_regs(i) <= pipeline_regs(i-1); + end if; + end if; + end loop; + -- FETCH Pipeline Registers + if stall_flags(ST_FETCH) = '0' then + pipeline_regs(ST_FETCH).pc <= pc_new; + pipeline_regs(ST_FETCH).dec_activate <= '1'; + end if; + + -- FETCH2 Pipeline Registers + if stall_flags(ST_FETCH2) = '0' then + -- Normal pipeline operation? + -- Buffering of RAM output when stalling is performed in the memory management + if pmem_data_out_valid = '1' then + pipeline_regs(ST_FETCH2).instr_word <= pmem_data_out; + end if; + end if; + + -- DECODE Pipeline registers + if stall_flags(ST_DECODE) = '0' then + pipeline_regs(ST_DECODE).act_array <= dec_act_array; + pipeline_regs(ST_DECODE).instr_array <= dec_instr_array; + pipeline_regs(ST_DECODE).dble_word_instr <= dec_dble_word_instr; + pipeline_regs(ST_DECODE).reg_wr_addr <= dec_reg_wr_addr; + pipeline_regs(ST_DECODE).reg_rd_addr <= dec_reg_rd_addr; + pipeline_regs(ST_DECODE).x_bus_wr_addr <= dec_x_bus_wr_addr; + pipeline_regs(ST_DECODE).x_bus_rd_addr <= dec_x_bus_rd_addr; + pipeline_regs(ST_DECODE).y_bus_wr_addr <= dec_y_bus_wr_addr; + pipeline_regs(ST_DECODE).y_bus_rd_addr <= dec_y_bus_rd_addr; + pipeline_regs(ST_DECODE).l_bus_addr <= dec_l_bus_addr; + pipeline_regs(ST_DECODE).adgen_mode_a <= dec_adgen_mode_a; + pipeline_regs(ST_DECODE).adgen_mode_b <= dec_adgen_mode_b; + pipeline_regs(ST_DECODE).alu_ctrl <= dec_alu_ctrl; + end if; + + -- ADGEN Pipeline registers + if stall_flags(ST_ADGEN) = '0' then + pipeline_regs(ST_ADGEN).adgen_address_x <= adgen_address_out_x; + pipeline_regs(ST_ADGEN).adgen_address_y <= adgen_address_out_y; + end if; + if xmem_data_out_valid = '1' then + pipeline_regs(ST_ADGEN).RAM_out_x <= xmem_data_out; + end if; + if ymem_data_out_valid = '1' then + pipeline_regs(ST_ADGEN).RAM_out_y <= ymem_data_out; + end if; + + -- EXEC Pipeline stuff + if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then + -- clear the following pipeline stages, + -- since we modified the pc. + -- Do not flush ST_FETCH - it will hold the correct pc. + flush_pipeline_stage(ST_FETCH2); + flush_pipeline_stage(ST_DECODE); + flush_pipeline_stage(ST_ADGEN); + end if; + end if; + end if; + end process shift_pipeline; + + ------------------------------- + -- FETCH STAGE INSTANTIATION + ------------------------------- + inst_fetch_stage: fetch_stage port map( + pc_old => pc_old, + pc_new => pc_new, + modify_pc => fetch_modify_pc, + modified_pc => fetch_modified_pc, + register_file => register_file, + decrement_lc => fetch_decrement_lc, + perform_enddo => fetch_perform_enddo + ); + + pc_old <= pipeline_regs(ST_FETCH).pc; + + fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0'; + fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else + exec_loop_modified_pc; + + ------------------------------- + -- DECODE STAGE INSTANTIATION + ------------------------------- + inst_decode_stage : decode_stage port map( + activate_dec => dec_activate, + instr_word => dec_instr_word, + dble_word_instr => dec_dble_word_instr, + instr_array => dec_instr_array, + act_array => dec_act_array, + reg_wr_addr => dec_reg_wr_addr, + reg_rd_addr => dec_reg_rd_addr, + x_bus_wr_addr => dec_x_bus_wr_addr, + x_bus_rd_addr => dec_x_bus_rd_addr, + y_bus_wr_addr => dec_y_bus_wr_addr, + y_bus_rd_addr => dec_y_bus_rd_addr, + l_bus_addr => dec_l_bus_addr, + adgen_mode_a => dec_adgen_mode_a, + adgen_mode_b => dec_adgen_mode_b, + alu_ctrl => dec_alu_ctrl + ); + + dec_instr_word <= pipeline_regs(ST_DECODE-1).instr_word; + -- do not decode, when we have no valid instruction. This can happen when + -- 1) the pipeline just started its operation + -- 2) the pipeline was flushed due to a jump + -- 3) we are processing a instruction that consists of two words + dec_activate <= '1' when pipeline_regs(ST_DECODE-1).dec_activate = '1' and pipeline_regs(ST_DECODE).dble_word_instr = '0' else '0'; + + ------------------------------- + -- AGU STAGE INSTANTIATION + ------------------------------- + inst_adgen_stage: adgen_stage port map( + activate_adgen => adgen_activate, + activate_x_mem => adgen_activate_x_mem, + activate_y_mem => adgen_activate_y_mem, + activate_l_mem => adgen_activate_l_mem, + instr_word => adgen_instr_word, + instr_array => adgen_instr_array, + optional_ea_word => adgen_optional_ea_word, + register_file => register_file, + adgen_mode_a => adgen_mode_a, + adgen_mode_b => adgen_mode_b, + address_out_x => adgen_address_out_x, + address_out_y => adgen_address_out_y, + wr_R_port_A_valid => adgen_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => adgen_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B + ); + + adgen_activate <= pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN); + adgen_activate_x_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_WR) = '1' else '0'; + adgen_activate_y_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_WR) = '1' else '0'; + adgen_activate_l_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_WR) = '1' else '0'; + adgen_instr_word <= pipeline_regs(ST_ADGEN-1).instr_word; + adgen_instr_array <= pipeline_regs(ST_ADGEN-1).instr_array; + adgen_optional_ea_word <= pipeline_regs(ST_ADGEN-2).instr_word; + adgen_mode_a <= pipeline_regs(ST_ADGEN-1).adgen_mode_a; + adgen_mode_b <= pipeline_regs(ST_ADGEN-1).adgen_mode_b; + + ------------------------------- + -- EXECUTE STAGE INSTANTIATIONS + ------------------------------- + inst_exec_stage_alu: exec_stage_alu port map( + alu_activate => exec_alu_activate, + instr_word => exec_alu_instr_word, + alu_ctrl => exec_alu_ctrl, + register_file => register_file, + addr_r_in => exec_alu_addr_r_in, + addr_r_out => exec_alu_addr_r_out, + modify_accu => exec_alu_modify_accu, + dst_accu => exec_alu_dst_accu, + modified_accu => exec_alu_modified_accu, + modify_sr => exec_alu_modify_sr, + modified_sr => exec_alu_modified_sr + ); + + exec_alu_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_ALU); + exec_alu_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_alu_ctrl <= pipeline_regs(ST_EXEC-1).alu_ctrl; + + exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0)); + + inst_exec_stage_bit_modify: exec_stage_bit_modify port map( + instr_word => exec_bit_modify_instr_word, + instr_array => exec_bit_modify_instr_array, + src_operand => exec_bit_modify_src_operand, + register_file => register_file, + dst_operand => exec_bit_modify_dst_operand, + bit_cond_met => exec_bit_modify_bit_cond_met, + modify_sr => exec_bit_modify_modify_sr, + modified_sr => exec_bit_modify_modified_sr + ); + + exec_bit_modify_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_bit_modify_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_bit_modify_src_operand <= exec_src_operand; + + -- Writing to the register file using the 6 bit addressing scheme + -- sources are: + -- 1) X-RAM output + -- 2) Y-RAM output + -- 3) register file itself + -- 4) short immediate value (8 bit stored in instruction word) + -- 5) long immediate value (from optional effective address extension) + -- 5) address generated by the address generation unit (LUA instr) + exec_src_operand <= pipeline_regs(ST_EXEC-1).RAM_out_x when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_y when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else + rf_reg_rd_data when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else + exec_imm_8bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_8BIT) = '1' else + exec_imm_12bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_12BIT) = '1' else + pipeline_regs(ST_EXEC-2).instr_word when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_LONG) = '1' else + std_logic_vector(resize(pipeline_regs(ST_EXEC-1).adgen_address_x, 24)); -- for LUA instr. + + -- Destination for the register file using the 6 bit addressing scheme. + -- Either read the bit modified version of the read value + -- or use the modified Rn in case of a NORM instruction +-- exec_dst_operand <= exec_bit_modify_dst_operand; + exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_EXEC-1).act_array(ACT_NORM) = '0' else + std_logic_vector(resize(exec_alu_addr_r_out,24)); + + -- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true + inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map( + instr_word => exec_cc_flag_calc_instr_word, + instr_array => exec_cc_flag_calc_instr_array, + register_file => register_file, + cc_flag_set => exec_cc_flag_set + ); + + exec_cc_flag_calc_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_cc_flag_calc_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + + + inst_exec_stage_branch : exec_stage_branch port map( + activate_exec_bra => exec_bra_activate, + instr_word => exec_bra_instr_word, + instr_array => exec_bra_instr_array, + register_file => register_file, + jump_address => exec_bra_jump_address, + bit_cond_met => exec_bra_bit_cond_met, + cc_flag_set => exec_cc_flag_set, + push_stack => exec_bra_push_stack, + pop_stack => exec_bra_pop_stack, + modify_pc => exec_bra_modify_pc, + modified_pc => exec_bra_modified_pc, + modify_sr => exec_bra_modify_sr, + modified_sr => exec_bra_modified_sr + ); + + exec_bra_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_BRA); + exec_bra_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_bra_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_bra_jump_address <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else + unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)); + exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met; + + inst_exec_stage_cr_mod : exec_stage_cr_mod port map( + activate_exec_cr_mod => exec_cr_mod_activate, + instr_word => exec_cr_mod_instr_word, + instr_array => exec_cr_mod_instr_array, + register_file => register_file, + modify_sr => exec_cr_mod_modify_sr, + modified_sr => exec_cr_mod_modified_sr, + modify_omr => exec_cr_mod_modify_omr, + modified_omr => exec_cr_mod_modified_omr + ); + + exec_cr_mod_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_CR_MOD); + exec_cr_mod_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_cr_mod_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + + inst_exec_stage_loop: exec_stage_loop port map( + clk => clk, + rst => rst, + activate_exec_loop => exec_loop_activate, + instr_word => exec_loop_instr_word, + instr_array => exec_loop_instr_array, + loop_iterations => exec_loop_iterations, + loop_address => exec_loop_address, + loop_start_address => exec_loop_start_address, + register_file => register_file, + fetch_perform_enddo=> fetch_perform_enddo, + memory_stall => memory_stall, + push_stack => exec_loop_push_stack, + pop_stack => exec_loop_pop_stack, + stall_rep => exec_loop_stall_rep, + stall_do => exec_loop_stall_do, + modify_lc => exec_loop_modify_lc, + decrement_lc => exec_loop_decrement_lc, + modified_lc => exec_loop_modified_lc, + modify_la => exec_loop_modify_la, + modified_la => exec_loop_modified_la, + modify_pc => exec_loop_modify_pc, + modified_pc => exec_loop_modified_pc, + modify_sr => exec_loop_modify_sr, + modified_sr => exec_loop_modified_sr + ); + + exec_loop_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_LOOP); + exec_loop_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_loop_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_loop_iterations <= unsigned(exec_src_operand(15 downto 0)); + -- from which source is our operand? + -- - XMEM + -- - YMEM + -- - Any register + -- - Immediate (from instruction word) +-- exec_src_operand <= unsigned(pipeline_regs(ST_EXEC-1).RAM_out_x(BW_ADDRESS-1 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else +-- unsigned(pipeline_regs(ST_EXEC-1).RAM_out_y(BW_ADDRESS-1 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else +-- unsigned(rf_reg_rd_data(15 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else +-- "00000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(15 downto 8)); + + -- Loop address is given by the second instruction word of the DO instruction. + -- This address is available one previous stage within the pipeline + exec_loop_address <= unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)) - 1; + -- one more stage before we find the programm counter of the first instruction to be executed in a DO loop + exec_loop_start_address <= unsigned(pipeline_regs(ST_EXEC-3).pc); + + -- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest) + exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else + pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + exec_imm_8bit(15 downto 8) <= (others => '0'); + exec_imm_8bit( 7 downto 0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else + pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + -- The 12 bit immediate stems from the instruction word + exec_imm_12bit(23 downto 12) <= (others => '0'); + exec_imm_12bit(11 downto 0) <= pipeline_regs(ST_EXEC-1).instr_word(3 downto 0) & pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + ----------------- + -- REGISTER FILE + ----------------- + inst_reg_file: reg_file port map( + clk => clk, + rst => rst, + register_file => register_file, + wr_R_port_A_valid => rf_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => rf_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B, + reg_wr_addr => rf_reg_wr_addr, + reg_wr_addr_valid => rf_reg_wr_addr_valid, + reg_wr_data => rf_reg_wr_data, + reg_rd_addr => rf_reg_rd_addr, + reg_rd_data => rf_reg_rd_data, + alu_wr_valid => rf_alu_wr_valid, + alu_wr_addr => exec_alu_dst_accu, + alu_wr_data => exec_alu_modified_accu, + X_bus_rd_addr => rf_X_bus_rd_addr, + X_bus_data_out => rf_X_bus_data_out, + X_bus_wr_addr => rf_X_bus_wr_addr , + X_bus_wr_valid => rf_X_bus_wr_valid, + X_bus_data_in => rf_X_bus_data_in , + Y_bus_rd_addr => rf_Y_bus_rd_addr , + Y_bus_data_out => rf_Y_bus_data_out, + Y_bus_wr_addr => rf_Y_bus_wr_addr , + Y_bus_wr_valid => rf_Y_bus_wr_valid, + Y_bus_data_in => rf_Y_bus_data_in , + L_bus_rd_addr => rf_L_bus_rd_addr , + L_bus_rd_valid => rf_L_bus_rd_valid, + L_bus_wr_addr => rf_L_bus_wr_addr , + L_bus_wr_valid => rf_L_bus_wr_valid, + push_stack => push_stack, + pop_stack => pop_stack, + set_sr => rf_set_sr, + new_sr => rf_new_sr, + set_omr => rf_set_omr, + new_omr => rf_new_omr, + set_la => rf_set_la, + new_la => rf_new_la, + dec_lc => rf_dec_lc, + set_lc => rf_set_lc, + new_lc => rf_new_lc + ); + + ----------------- + -- BUSES (X,Y,L) + ----------------- + rf_X_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_WR); + rf_X_bus_wr_addr <= pipeline_regs(ST_EXEC-1).x_bus_wr_addr; + rf_X_bus_rd_addr <= pipeline_regs(ST_EXEC-1).x_bus_rd_addr; + rf_X_bus_data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_x; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else + + rf_Y_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_WR); + rf_Y_bus_wr_addr <= pipeline_regs(ST_EXEC-1).y_bus_wr_addr; + rf_Y_bus_rd_addr <= pipeline_regs(ST_EXEC-1).y_bus_rd_addr; + rf_Y_bus_data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_y; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else + + rf_L_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_WR); + rf_L_bus_rd_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD); + rf_L_bus_wr_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- equal to bits in instruction word + rf_L_bus_rd_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- could be simplified by taking these bits.. + + -- writing to the R registers within the ADGEN stage has to be prevented when + -- 1) a jump is currently being executed (which is detected in the exec stage) + -- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling. + -- 3) a memory access results in a stall (e.g. caused by the instruction to REP) + rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADGEN) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_A_valid; + rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADGEN) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_B_valid; + + + rf_reg_wr_addr <= pipeline_regs(ST_EXEC-1).reg_wr_addr; + -- can be set due to + -- 1) normal write operation (e.g., move) + -- 2) conditional move (Tcc) + rf_reg_wr_addr_valid <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR) = '1' else + exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR_CC) = '1' else '0'; + rf_reg_wr_data <= exec_dst_operand; + + rf_reg_rd_addr <= pipeline_regs(ST_EXEC-1).reg_rd_addr; + + -- Writing from the ALU can depend on the condition code (Tcc) instruction + rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_ALU_WR_CC) = '1' else + exec_alu_modify_accu; + + push_stack.valid <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0'; + push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else + exec_loop_push_stack.content; + -- for jump to subroutine store the pc of the subsequent instruction + push_stack.pc <= pipeline_regs(ST_EXEC-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else + pipeline_regs(ST_EXEC-3).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '1' else + exec_loop_push_stack.pc when exec_loop_push_stack.valid = '1' else + (others => '0'); + + pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0'; + + rf_set_sr <= '1' when exec_bra_modify_sr = '1' or + exec_cr_mod_modify_sr = '1' or + exec_loop_modify_sr = '1' or + exec_alu_modify_sr = '1' or + exec_bit_modify_modify_sr = '1' else '0'; + rf_new_sr <= exec_bra_modified_sr when exec_bra_modify_sr = '1' else + exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else + exec_loop_modified_sr when exec_loop_modify_sr = '1' else + exec_alu_modified_sr when exec_alu_modify_sr = '1' else + exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else + + rf_set_omr <= exec_cr_mod_modify_omr; + rf_new_omr <= exec_cr_mod_modified_omr; + rf_set_lc <= exec_loop_modify_lc; + rf_new_lc <= exec_loop_modified_lc; + rf_set_la <= exec_loop_modify_la; + rf_new_la <= exec_loop_modified_la; + + rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0'; + + --------------------- + -- MEMORY MANAGEMENT + --------------------- + MMU_inst: memory_management port map ( + clk => clk, + rst => rst, + stall_flags => stall_flags, + memory_stall => memory_stall, + data_rom_enable => register_file.omr(2), + pmem_ctrl_in => pmem_ctrl_in, + pmem_ctrl_out => pmem_ctrl_out, + xmem_ctrl_in => xmem_ctrl_in, + xmem_ctrl_out => xmem_ctrl_out, + ymem_ctrl_in => ymem_ctrl_in, + ymem_ctrl_out => ymem_ctrl_out + ); + + ------------------ + -- Program Memory + ------------------ + pmem_ctrl_in.rd_addr <= pc_new; + pmem_ctrl_in.rd_en <= '1' when stall_flags(ST_FETCH) = '0' else '0'; + -- TODO: Writing to PMEM! + pmem_ctrl_in.wr_addr <= (others => '0'); + pmem_ctrl_in.wr_en <= '0'; + pmem_ctrl_in.data_in <= (others => '0'); + + pmem_data_out <= pmem_ctrl_out.data_out; + pmem_data_out_valid <= pmem_ctrl_out.data_out_valid; + + + ------------------ + -- X Memory + ------------------ + -- Either take the result of the AGU or use the short absolute value stored in the instruction word + xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8)); + xmem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + xmem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8)); + xmem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_WR) = '1' else '0'; + xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' or + pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + + xmem_data_out <= xmem_ctrl_out.data_out; + xmem_data_out_valid <= xmem_ctrl_out.data_out_valid; + + ------------------ + -- Y Memory + ------------------ + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8)); + ymem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_y when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8)); + ymem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_WR) = '1' else '0'; + ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' or + pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + + ymem_data_out <= ymem_ctrl_out.data_out; + ymem_data_out_valid <= ymem_ctrl_out.data_out_valid; + + +end architecture rtl; diff --git a/FPGA_quartus/DSP/src/reg_file.vhd b/FPGA_quartus/DSP/src/reg_file.vhd new file mode 100644 index 0000000..7f3244c --- /dev/null +++ b/FPGA_quartus/DSP/src/reg_file.vhd @@ -0,0 +1,679 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + dec_lc : in std_logic; + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) +); +end entity; + + +architecture rtl of reg_file is + + signal addr_r : addr_array; + signal addr_m : addr_array; + signal addr_n : addr_array; + + signal loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal loop_counter : unsigned(15 downto 0); + + -- condition code register + signal ccr : std_logic_vector(7 downto 0); + -- mode register + signal mr : std_logic_vector(7 downto 0); + -- status register = mode register + condition code register + signal sr : std_logic_vector(15 downto 0); + -- operation mode register + signal omr : std_logic_vector(7 downto 0); + + signal stack_pointer : unsigned(5 downto 0); + signal system_stack_ssh : stack_array_type; + signal system_stack_ssl : stack_array_type; + + signal x0 : signed(23 downto 0); + signal x1 : signed(23 downto 0); + signal y0 : signed(23 downto 0); + signal y1 : signed(23 downto 0); + + signal a0 : signed(23 downto 0); + signal a1 : signed(23 downto 0); + signal a2 : signed(7 downto 0); + + signal b0 : signed(23 downto 0); + signal b1 : signed(23 downto 0); + signal b2 : signed(7 downto 0); + + signal limited_a1 : signed(23 downto 0); + signal limited_b1 : signed(23 downto 0); + signal limited_a0 : signed(23 downto 0); + signal limited_b0 : signed(23 downto 0); + signal set_limiting_flag : std_logic; + signal X_bus_rd_limited_a : std_logic; + signal X_bus_rd_limited_b : std_logic; + signal Y_bus_rd_limited_a : std_logic; + signal Y_bus_rd_limited_b : std_logic; + signal reg_rd_limited_a : std_logic; + signal reg_rd_limited_b : std_logic; + signal rd_limited_a : std_logic; + signal rd_limited_b : std_logic; + +begin + + + + sr <= mr & ccr; + + register_file.addr_r <= addr_r; + register_file.addr_n <= addr_n; + register_file.addr_m <= addr_m; + register_file.lc <= loop_counter; + register_file.la <= loop_address; + register_file.ccr <= ccr; + register_file.mr <= mr; + register_file.sr <= sr; + register_file.omr <= omr; + register_file.stack_pointer <= stack_pointer; + register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0))); + register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0))); + register_file.a <= a2 & a1 & a0; + register_file.b <= b2 & b1 & b0; + register_file.x0 <= x0; + register_file.x1 <= x1; + register_file.y0 <= y0; + register_file.y1 <= y1; + + + global_register_file: process(clk) is + variable stack_pointer_plus_1 : unsigned(3 downto 0); + variable reg_addr : integer range 0 to 7; + begin + if rising_edge(clk) then + if rst = '1' then + addr_r <= (others => (others => '0')); + addr_n <= (others => (others => '0')); + addr_m <= (others => (others => '1')); + ccr <= (others => '0'); + mr <= (others => '0'); + omr <= (others => '0'); + system_stack_ssl <= (others => (others => '0')); + system_stack_ssh <= (others => (others => '0')); + stack_pointer <= (others => '0'); + loop_counter <= (others => '0'); + loop_address <= (others => '0'); + x0 <= (others => '0'); + x1 <= (others => '0'); + y0 <= (others => '0'); + y1 <= (others => '0'); + a0 <= (others => '0'); + a1 <= (others => '0'); + a2 <= (others => '0'); + b0 <= (others => '0'); + b1 <= (others => '0'); + b2 <= (others => '0'); + else + reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0))); + ----------------------------------------------------------------------- + -- General write port to register file using 6 bit addressing scheme + ----------------------------------------------------------------------- + if reg_wr_addr_valid = '1' then + case reg_wr_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_wr_addr(2 downto 0) is + when "100" => + x0 <= signed(reg_wr_data); + when "101" => + x1 <= signed(reg_wr_data); + when "110" => + y0 <= signed(reg_wr_data); + when "111" => + y1 <= signed(reg_wr_data); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_wr_addr(2 downto 0) is + when "000" => + a0 <= signed(reg_wr_data); + when "001" => + b0 <= signed(reg_wr_data); + when "010" => + a2 <= signed(reg_wr_data(7 downto 0)); + when "011" => + b2 <= signed(reg_wr_data(7 downto 0)); + when "100" => + a1 <= signed(reg_wr_data); + when "101" => + b1 <= signed(reg_wr_data); + when "110" => + a2 <= (others => reg_wr_data(23)); + a1 <= signed(reg_wr_data); + a0 <= (others => '0'); + when "111" => + b2 <= (others => reg_wr_data(23)); + b1 <= signed(reg_wr_data); + b0 <= (others => '0'); + when others => + end case; + + -- R0-R7 + when "010" => + addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- N0-N7 + when "011" => + addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- M0-M7 + when "100" => + addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + mr <= reg_wr_data(15 downto 8); + ccr <= reg_wr_data( 7 downto 0); + + -- OMR + when "010" => + omr <= reg_wr_data(7 downto 0); + + -- SP + when "011" => + stack_pointer <= unsigned(reg_wr_data(5 downto 0)); + + -- SSH + when "100" => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + + -- SSL + when "101" => + system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + + -- LA + when "110" => + loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- LC + when "111" => + loop_counter <= unsigned(reg_wr_data(15 downto 0)); + + when others => + end case; + when others => + end case; + end if; + + ---------------- + -- X BUS Write + ---------------- + if X_bus_wr_valid = '1' then + case X_bus_wr_addr is + when "00" => + x0 <= signed(X_bus_data_in); + when "01" => + x1 <= signed(X_bus_data_in); + when "10" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ---------------- + -- Y BUS Write + ---------------- + if Y_bus_wr_valid = '1' then + case Y_bus_wr_addr is + when "00" => + y0 <= signed(Y_bus_data_in); + when "01" => + y1 <= signed(Y_bus_data_in); + when "10" => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ------------------ + -- L BUS Write + ------------------ + if L_bus_wr_valid = '1' then + case L_bus_wr_addr is + -- A10 + when "000" => + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B10 + when "001" => + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- X + when "010" => + x1 <= signed(X_bus_data_in); + x0 <= signed(Y_bus_data_in); + -- Y + when "011" => + y1 <= signed(X_bus_data_in); + y0 <= signed(Y_bus_data_in); + -- A + when "100" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B + when "101" => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- AB + when "110" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + -- BA + when others => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + + --------------------- + -- STATUS REGISTERS + --------------------- + if set_sr = '1' then + ccr <= new_sr( 7 downto 0); + mr <= new_sr(15 downto 8); + end if; + if set_omr = '1' then + omr <= new_omr; + end if; + -- data limiter active? + -- listing this statement after the set_sr test results + -- in the correct behaviour for ALU operations with parallel move + if set_limiting_flag = '1' then + ccr(6) <= '1'; + end if; + + -------------------- + -- LOOP REGISTERS + -------------------- + if set_la = '1' then + loop_address <= new_la; + end if; + if set_lc = '1' then + loop_counter <= new_lc; + end if; + if dec_lc = '1' then + loop_counter <= loop_counter - 1; + end if; + + --------------------- + -- ADDRESS REGISTER + --------------------- + if wr_R_port_A_valid = '1' then + addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value; + end if; + if wr_R_port_B_valid = '1' then + addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value; + end if; + + ------------------------- + -- ALU ACCUMULATOR WRITE + ------------------------- + if alu_wr_valid = '1' then + if alu_wr_addr = '0' then + a2 <= alu_wr_data(55 downto 48); + a1 <= alu_wr_data(47 downto 24); + a0 <= alu_wr_data(23 downto 0); + else + b2 <= alu_wr_data(55 downto 48); + b1 <= alu_wr_data(47 downto 24); + b0 <= alu_wr_data(23 downto 0); + end if; + end if; + + --------------------- + -- STACK CONTROLLER + --------------------- + stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1; + if push_stack.valid = '1' then + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + case push_stack.content is + when PC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + + when PC_AND_SR => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR; + + when LA_AND_LC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter); + + end case; + end if; + + -- decrease stack pointer + if pop_stack.valid = '1' then + stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1; + -- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE) + if stack_pointer(3 downto 0) = "0000" then + stack_pointer(5) <= '1'; + stack_pointer(4) <= '1'; + end if; + end if; + end if; + end if; + end process; + + + x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,y1) is + begin + X_bus_rd_limited_a <= '0'; + X_bus_rd_limited_b <= '0'; + case X_bus_rd_addr is + when "00" => X_bus_data_out <= std_logic_vector(x0); + when "01" => X_bus_data_out <= std_logic_vector(x1); + when "10" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => X_bus_data_out <= std_logic_vector(a1); + when "001" => X_bus_data_out <= std_logic_vector(b1); + when "010" => X_bus_data_out <= std_logic_vector(x1); + when "011" => X_bus_data_out <= std_logic_vector(y1); + when "100" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when "101" => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + when "110" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + end if; + end process x_bus_rd_port; + + y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is + begin + Y_bus_rd_limited_a <= '0'; + Y_bus_rd_limited_b <= '0'; + case Y_bus_rd_addr is + when "00" => Y_bus_data_out <= std_logic_vector(y0); + when "01" => Y_bus_data_out <= std_logic_vector(y1); + when "10" => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => Y_bus_data_out <= std_logic_vector(a0); + when "001" => Y_bus_data_out <= std_logic_vector(b0); + when "010" => Y_bus_data_out <= std_logic_vector(x0); + when "011" => Y_bus_data_out <= std_logic_vector(y0); + when "100" => Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1'; + when "101" => Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1'; + when "110" => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + end case; + end if; + end process y_bus_rd_port; + + + reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2, + omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer, + loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is + variable reg_addr : integer range 0 to 7; + begin + reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0))); + reg_rd_data <= (others => '0'); + reg_rd_limited_a <= '0'; + reg_rd_limited_b <= '0'; + + case reg_rd_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_rd_addr(2 downto 0) is + when "100" => + reg_rd_data <= std_logic_vector(x0); + when "101" => + reg_rd_data <= std_logic_vector(x1); + when "110" => + reg_rd_data <= std_logic_vector(y0); + when "111" => + reg_rd_data <= std_logic_vector(y1); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_rd_addr(2 downto 0) is + when "000" => + reg_rd_data <= std_logic_vector(a0); + when "001" => + reg_rd_data <= std_logic_vector(b0); + when "010" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(a2); + when "011" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(b2); + when "100" => + reg_rd_data <= std_logic_vector(a1); + when "101" => + reg_rd_data <= std_logic_vector(b1); + when "110" => + reg_rd_data <= std_logic_vector(limited_a1); + reg_rd_limited_a <= '1'; + when "111" => + reg_rd_data <= std_logic_vector(limited_b1); + reg_rd_limited_b <= '1'; + when others => + end case; + + -- R0-R7 + when "010" => + reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24)); + + -- N0-N7 + when "011" => + reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24)); + + -- M0-M7 + when "100" => + reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + reg_rd_data(23 downto 16) <= (others => '0'); + reg_rd_data(15 downto 0) <= mr & ccr; + + -- OMR + when "010" => + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data( 7 downto 0) <= omr; + + -- SP + when "011" => + reg_rd_data(23 downto 6) <= (others => '0'); + reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer); + + -- SSH + when "100" => +-- TODO! +-- system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); +-- -- increase stack after writing +-- stack_pointer(3 downto 0) <= stack_pointer_plus_1; +-- -- test whether stack is full, if so set the stack error flag (SE) +-- if stack_pointer(3 downto 0) = "1111" then +-- stack_pointer(4) <= '1'; +-- end if; + + -- SSL + when "101" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer))); + + -- LA + when "110" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address); + + -- LC + when "111" => + reg_rd_data <= (others => '0'); + reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter); + + when others => + end case; + when others => + end case; + end process; + + rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0'; + rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0'; + + data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is + variable scaled_a : signed(55 downto 0); + variable scaled_b : signed(55 downto 0); + begin + + set_limiting_flag <= '0'; + ----------------- + -- DATA SCALING + ----------------- + -- test against scaling bits S1, S0 + case sr(11 downto 10) is + -- scale down (right shift) + when "01" => + scaled_a := a2(7) & a2 & a1 & a0(23 downto 1); + scaled_b := b2(7) & b2 & b1 & b0(23 downto 1); + -- scale up (arithmetic left shift) + when "10" => + scaled_a := a2(6 downto 0) & a1 & a0 & '0'; + scaled_b := b2(6 downto 0) & b1 & b0 & '0'; + -- "00" do not scale! + when others => + scaled_a := a2 & a1 & a0; + scaled_b := b2 & b1 & b0; + end case; + + -- only sign extension stored in a2? + -- Yes: No limiting needed! + if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then + limited_a1 <= scaled_a(47 downto 24); + limited_a0 <= scaled_a(23 downto 0); + else + -- positive value in a? + if scaled_a(55) = '0' then + limited_a1 <= X"7FFFFF"; + limited_a0 <= X"FFFFFF"; + -- negative value in a? + else + limited_a1 <= X"800000"; + limited_a0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_a = '1' then + set_limiting_flag <= '1'; + end if; + end if; + -- only sign extension stored in b2? + -- Yes: No limiting needed! + if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then + limited_b1 <= scaled_b(47 downto 24); + limited_b0 <= scaled_b(23 downto 0); + else + -- positive value in b? + if scaled_b(55) = '0' then + limited_b1 <= X"7FFFFF"; + limited_b0 <= X"FFFFFF"; + -- negative value in b? + else + limited_b1 <= X"800000"; + limited_b0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_b = '1' then + set_limiting_flag <= '1'; + end if; + end if; + + end process; + + +end architecture rtl; diff --git a/FPGA_quartus/DSP/src/types_pkg.vhd b/FPGA_quartus/DSP/src/types_pkg.vhd new file mode 100644 index 0000000..131f7fa --- /dev/null +++ b/FPGA_quartus/DSP/src/types_pkg.vhd @@ -0,0 +1,167 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; + + + +package types_pkg is + + -- the different addressing modes + type adgen_mode_type is (NOP, POST_MIN_N, POST_PLUS_N, POST_MIN_1, POST_PLUS_1, INDEXED_N, PRE_MIN_1, ABSOLUTE, IMMEDIATE); + ------------------------ + -- Decoded instructions + ------------------------ + type instructions_type is ( + INSTR_NOP , + INSTR_RTI , + INSTR_ILLEGAL , + INSTR_SWI , + INSTR_RTS , + INSTR_RESET , + INSTR_WAIT , + INSTR_STOP , + INSTR_ENDDO , + INSTR_ANDI , + INSTR_ORI , + INSTR_DIV , + INSTR_NORM , + INSTR_LUA , + INSTR_MOVEC , + INSTR_REP , + INSTR_DO , + INSTR_MOVEM , + INSTR_MOVEP , + INSTR_PM_MOVEM, + INSTR_BCLR , + INSTR_BSET , + INSTR_JCLR , + INSTR_JSET , + INSTR_JMP , + INSTR_JCC , + INSTR_BCHG , + INSTR_BTST , + INSTR_JSCLR , + INSTR_JSSET , + INSTR_JSR , + INSTR_JSCC ); + + type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0); + + type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS); + type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET); + type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag; + + type alu_ctrl_type is record + mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + shift_src : std_logic; -- a,b + shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + shift_mode : alu_shift_mode; + rotate : std_logic; -- 0: logical shift, 1: rotate shift + add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b + add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved + add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + logic_function : std_logic_vector(2 downto 0); -- 000: none, 001: and, 010: or, 011: eor, 100: not + word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? + rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry + store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator + dst_accu : std_logic; -- 0: a, 1: b + div_instr : std_logic; -- DIV instruction? Special ALU operations needed! + norm_instr : std_logic; -- NORM instruction? Special ALU operations needed! + ccr_flags_ctrl : alu_ccr_flag_array; + end record; + + type pipeline_signals is record + instr_word: std_logic_vector(23 downto 0); + pc : unsigned(BW_ADDRESS-1 downto 0); + dble_word_instr : std_logic; + instr_array : instructions_type; + act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + dec_activate : std_logic; + adgen_mode_a : adgen_mode_type; + adgen_mode_b : adgen_mode_type; + reg_wr_addr : std_logic_vector(5 downto 0); + reg_rd_addr : std_logic_vector(5 downto 0); + x_bus_rd_addr : std_logic_vector(1 downto 0); + x_bus_wr_addr : std_logic_vector(1 downto 0); + y_bus_rd_addr : std_logic_vector(1 downto 0); + y_bus_wr_addr : std_logic_vector(1 downto 0); + l_bus_addr : std_logic_vector(2 downto 0); + adgen_address_x : unsigned(BW_ADDRESS-1 downto 0); + adgen_address_y : unsigned(BW_ADDRESS-1 downto 0); + RAM_out_x : std_logic_vector(23 downto 0); + RAM_out_y : std_logic_vector(23 downto 0); + alu_ctrl : alu_ctrl_type; + end record; + + type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals; + + + type register_file_type is record + a : signed(55 downto 0); + b : signed(55 downto 0); + x0 : signed(23 downto 0); + x1 : signed(23 downto 0); + y0 : signed(23 downto 0); + y1 : signed(23 downto 0); + la : unsigned(BW_ADDRESS-1 downto 0); + lc : unsigned(15 downto 0); + addr_r : addr_array; + addr_n : addr_array; + addr_m : addr_array; + ccr : std_logic_vector(7 downto 0); + mr : std_logic_vector(7 downto 0); + sr : std_logic_vector(15 downto 0); + omr : std_logic_vector(7 downto 0); + stack_pointer : unsigned(5 downto 0); +-- system_stack_ssh : stack_array_type; +-- system_stack_ssl : stack_array_type; + current_ssh : std_logic_vector(BW_ADDRESS-1 downto 0); + current_ssl : std_logic_vector(BW_ADDRESS-1 downto 0); + + end record; + + type addr_wr_port_type is record +-- write_valid : std_logic; + reg_number : unsigned(2 downto 0); + reg_value : unsigned(15 downto 0); + end record; + + type mem_ctrl_type_in is record + rd_addr : unsigned(BW_ADDRESS-1 downto 0); + rd_en : std_logic; + wr_addr : unsigned(BW_ADDRESS-1 downto 0); + wr_en : std_logic; + data_in : std_logic_vector(23 downto 0); + end record; + + type mem_ctrl_type_out is record + data_out : std_logic_vector(23 downto 0); + data_out_valid : std_logic; + end record; + + type memory_type is (X_MEM, Y_MEM, P_MEM); + --------------- + -- STACK TYPES + --------------- + type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0); + + type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC); + + type push_stack_type is record + valid : std_logic; + pc : unsigned(BW_ADDRESS-1 downto 0); + content : push_stack_content_type; + end record; + +-- type pop_stack_content_type is (PC, PC_AND_SR, SR, LA_AND_LC); + +-- type pop_stack_type is std_logic; + type pop_stack_type is record + valid : std_logic; +-- content : pop_stack_content_type; + end record; + +end package types_pkg; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd new file mode 100644 index 0000000..b2b8dbb --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -0,0 +1,971 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:20 2009 + +library work; +use work.FalconIO_SDCard_IDE_CF_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +-- Entity Declaration + + +-- Entity Declaration + +ENTITY FalconIO_SDCard_IDE_CF IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + CLK2M : IN STD_LOGIC; + CLK500k : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + LP_BUSY : IN STD_LOGIC; + nACSI_DRQ : IN STD_LOGIC; + nACSI_INT : IN STD_LOGIC; + nSCSI_DRQ : IN STD_LOGIC; + nSCSI_MSG : IN STD_LOGIC; + MIDI_IN : IN STD_LOGIC; + RxD : IN STD_LOGIC; + CTS : IN STD_LOGIC; + RI : IN STD_LOGIC; + DCD : IN STD_LOGIC; + AMKB_RX : IN STD_LOGIC; + PIC_AMKB_RX : IN STD_LOGIC; + IDE_RDY : IN STD_LOGIC; + IDE_INT : IN STD_LOGIC; + WP_CS_CARD : IN STD_LOGIC; + nINDEX : IN STD_LOGIC; + TRACK00 : IN STD_LOGIC; + nRD_DATA : IN STD_LOGIC; + nDCHG : IN STD_LOGIC; + SD_DATA0 : IN STD_LOGIC; + SD_DATA1 : IN STD_LOGIC; + SD_DATA2 : IN STD_LOGIC; + SD_CARD_DEDECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + nDACK0 : IN STD_LOGIC; + nFB_WR : INOUT STD_LOGIC; + WP_CF_CARD : IN STD_LOGIC; + nWP : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + HD_DD : IN STD_LOGIC; + nSCSI_C_D : IN STD_LOGIC; + nSCSI_I_O : IN STD_LOGIC; + CLK2M4576 : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + VSYNC : IN STD_LOGIC; + HSYNC : IN STD_LOGIC; + DSP_INT : IN STD_LOGIC; + nBLANK : IN STD_LOGIC; + FDC_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); + nIDE_CS1 : OUT STD_LOGIC; + nIDE_CS0 : OUT STD_LOGIC; + LP_STR : OUT STD_LOGIC; + LP_DIR : OUT STD_LOGIC; + nACSI_ACK : OUT STD_LOGIC; + nACSI_RESET : OUT STD_LOGIC; + nACSI_CS : OUT STD_LOGIC; + ACSI_DIR : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + nSCSI_ACK : OUT STD_LOGIC; + nSCSI_ATN : OUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + YM_QA : OUT STD_LOGIC; + YM_QC : OUT STD_LOGIC; + YM_QB : OUT STD_LOGIC; + nSDSEL : OUT STD_LOGIC; + STEP : OUT STD_LOGIC; + MOT_ON : OUT STD_LOGIC; + nRP_LDS : OUT STD_LOGIC; + nRP_UDS : OUT STD_LOGIC; + nROM4 : OUT STD_LOGIC; + nROM3 : OUT STD_LOGIC; + nCF_CS1 : OUT STD_LOGIC; + nCF_CS0 : OUT STD_LOGIC; + nIDE_RD : INOUT STD_LOGIC; + nIDE_WR : INOUT STD_LOGIC; + AMKB_TX : OUT STD_LOGIC; + IDE_RES : OUT STD_LOGIC; + DTR : OUT STD_LOGIC; + RTS : OUT STD_LOGIC; + TxD : OUT STD_LOGIC; + MIDI_OLR : OUT STD_LOGIC; + MIDI_TLR : OUT STD_LOGIC; + nDREQ0 : OUT STD_LOGIC; + DSA_D : OUT STD_LOGIC; + nMFP_INT : OUT STD_LOGIC; + FALCON_IO_TA : OUT STD_LOGIC; + STEP_DIR : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC; + WR_GATE : OUT STD_LOGIC; + DMA_DRQ : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_PAR : INOUT STD_LOGIC; + nSCSI_SEL : INOUT STD_LOGIC; + nSCSI_BUSY : INOUT STD_LOGIC; + nSCSI_RST : INOUT STD_LOGIC; + SD_CD_DATA3 : INOUT STD_LOGIC; + SD_CDM_D1 : INOUT STD_LOGIC + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END FalconIO_SDCard_IDE_CF; + + +-- Architecture Body + +ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS +-- system +signal SYS_CLK : STD_LOGIC; +signal RESETn : STD_LOGIC; +signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS +signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS +signal BYT : STD_LOGIC; -- WENN BYT -> 1 +signal LONG : STD_LOGIC; -- WENN -> 1 +-- KEYBOARD MIDI +signal ACIA_CS_I : STD_LOGIC; +signal IRQ_KEYBDn : STD_LOGIC; +signal IRQ_MIDIn : STD_LOGIC; +signal KEYB_RxD : STD_LOGIC; +signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); +signal MIDI_OUT : STD_LOGIC; +signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); +signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); +-- MFP +signal MFP_CS : STD_LOGIC; +signal MFP_INTACK : STD_LOGIC; +signal LDS : STD_LOGIC; +signal DTACK_OUT_MFPn : STD_LOGIC; +signal IRQ_ACIAn : STD_LOGIC; +signal DINTn : STD_LOGIC; +signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); +signal TDO : STD_LOGIC; +-- SOUND +signal SNDCS : STD_LOGIC; +signal SNDCS_I : STD_LOGIC; +signal SNDIR_I : STD_LOGIC; +signal LP_DIR_X : STD_LOGIC; +signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); +signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); +-- DIV +signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE +signal ROM_CS : STD_LOGIC; +-- DMA UND FLOPPY +signal DMA_DATEN_CS : STD_LOGIC; +signal DMA_MODUS_CS : STD_LOGIC; +signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); +signal WDC_BSL_CS : STD_LOGIC; +signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal HD_DD_OUT : STD_LOGIC; +signal FDCS_In : STD_LOGIC; +signal CA0 : STD_LOGIC; +signal CA1 : STD_LOGIC; +signal CA2 : STD_LOGIC; +signal FDINT : STD_LOGIC; +signal FDRQ : STD_LOGIC; +signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_TOP_CS : STD_LOGIC; +signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_HIGH_CS : STD_LOGIC; +signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_MID_CS : STD_LOGIC; +signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_LOW_CS : STD_LOGIC; +signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_DIRM_CS : STD_LOGIC; +signal DMA_ADR_CS : STD_LOGIC; +signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); +signal DMA_DIR_OLD : STD_LOGIC; +signal DMA_BYT_CNT_CS : STD_LOGIC; +signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); +signal CLR_FIFO : STD_LOGIC; +signal DMA_DRQ_I : STD_LOGIC; +signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); +signal DMA_DRQQ : STD_LOGIC; +signal DMA_DRQ_Q : STD_LOGIC; +signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); +signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal RDF_RDE : STD_LOGIC; +signal RDF_WRE : STD_LOGIC; +signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal WRF_RDE : STD_LOGIC; +signal WRF_WRE : STD_LOGIC; +signal nFDC_WR : STD_LOGIC; +type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); +signal FCF_STATE : FCF_STATES; +signal NEXT_FCF_STATE : FCF_STATES; +signal DMA_REQ : STD_LOGIC; +signal FDC_CS : STD_LOGIC; +signal FCF_CS : STD_LOGIC; +signal FCF_APH : STD_LOGIC; +signal DMA_AZ_CS : STD_LOGIC; +signal DMA_ACTIV : STD_LOGIC; +signal DMA_ACTIV_NEW : STD_LOGIC; +signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); +-- SCSI +signal SCSI_CS : STD_LOGIC; +signal SCSI_CSn : STD_LOGIC; +signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal nSCSI_DACK : STD_LOGIC; +signal SCSI_DRQ : STD_LOGIC; +signal SCSI_INT : STD_LOGIC; +signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); +signal DB_EN : STD_LOGIC; +signal DBP_OUTn : STD_LOGIC; +signal DBP_EN : STD_LOGIC; +signal RST_OUTn : STD_LOGIC; +signal RST_EN : STD_LOGIC; +signal BSY_OUTn : STD_LOGIC; +signal BSY_EN : STD_LOGIC; +signal SEL_OUTn : STD_LOGIC; +signal SEL_EN : STD_LOGIC; +-- IDE +signal nnIDE_RES : STD_LOGIC; +signal IDE_CF_CS : STD_LOGIC; +signal IDE_CF_TA : STD_LOGIC; +signal NEXT_nIDE_RD : STD_LOGIC; +signal NEXT_nIDE_WR : STD_LOGIC; +type CMD_STATES is( IDLE, T1, T6, T7); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; + + +BEGIN +LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; +BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; +FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; +FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; + +FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; +SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE + '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; +nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; +nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; +nDREQ0 <= '0'; +---------------------------------------------------------------------------- +-- SD +---------------------------------------------------------------------------- +SD_CLK <= 'Z'; +SD_CD_DATA3 <= 'Z'; +SD_CDM_D1 <= 'Z'; +---------------------------------------------------------------------------- +-- IDE +---------------------------------------------------------------------------- +CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + begin + if nRSTO = '0' then + CMD_STATE <= IDLE; + elsif rising_edge(MAIN_CLK) then + CMD_STATE <= NEXT_CMD_STATE; -- go to next + nIDE_RD <= NEXT_nIDE_RD; -- go to next + nIDE_WR <= NEXT_nIDE_WR; -- go to next + else + CMD_STATE <= CMD_STATE; -- halten + nIDE_RD <= nIDE_RD; -- halten + nIDE_WR <= nIDE_WR; -- halten + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + begin + case CMD_STATE is + when IDLE => + IDE_CF_TA <= '0'; + if IDE_CF_CS = '1' then + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T1; + else + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end if; + when T1 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + when T6 => + IF IDE_RDY = '1' then + IDE_CF_TA <= '1'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= T7; + else + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + end if; + when T7 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end case; + end process CMD_DECODER; + +IDE_RES <= not nnIDE_RES and nRSTO; +IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 +nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F +nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F +nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F +nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F +----------------------------------------------------------------------------------------------------------------------------------------- +-- ACSI, SCSI UND FLOPPY WD1772 +------------------------------------------------------------------------------------------------------------------------------------------- +-- daten read fifo + RDF: dcfifo0 + port map( + aclr => CLR_FIFO, + data => RDF_DIN, + rdclk => MAIN_CLK, + rdreq => RDF_RDE, + wrclk => FDC_CLK, + wrreq => RDF_WRE, + q => RDF_DOUT, + wrusedw => RDF_AZ + ); +FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY +FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY +RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE +FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; +-- daten write fifo + WRF: dcfifo1 + port map( + aclr => CLR_FIFO, + data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + rdclk => FDC_CLK, + rdreq => WRF_RDE, + wrclk => MAIN_CLK, + wrreq => WRF_WRE, + q => WRF_DOUT, + rdusedw => WRF_AZ + ); +CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB +DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG +FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + begin + if nRSTO = '0' THEN + WRF_WRE <= '0'; + elsif rising_edge(MAIN_CLK) then + IF FCF_APH = '1' and nFB_WR = '0' then + WRF_WRE <= '1'; + else + WRF_WRE <= '0'; + end if; + else + WRF_WRE <= WRF_WRE; + end if; + END PROCESS; + +FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + begin + if nRSTO = '0' then + FCF_STATE <= FCF_IDLE; + DMA_ACTIV <= '0'; + elsif rising_edge(FDC_CLK) then + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + else + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + end if; + end process FCF_REG; + +FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + begin + if nRSTO = '0' then + FDC_OUT <= x"00"; + elsif rising_edge(FDC_CLK) and FDCS_In = '0' then + FDC_OUT <= CD_OUT_FDC; -- set + else + FDC_OUT <= FDC_OUT; -- halten + end if; + end process FDC_REG; + +DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; +FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; +SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + + FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + begin + case FCF_STATE is + when FCF_IDLE => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + DMA_ACTIV_NEW <= DMA_REQ; + NEXT_FCF_STATE <= FCF_T0; + else + DMA_ACTIV_NEW <= '0'; + NEXT_FCF_STATE <= FCF_IDLE; + end if; + when FCF_T0 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= DMA_REQ; + WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO + if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start + else + NEXT_FCF_STATE <= FCF_T1; + end if; + when FCF_T1 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T2; + when FCF_T2 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T3; + when FCF_T3 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T6; + when FCF_T6 => + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO + NEXT_FCF_STATE <= FCF_T7; + when FCF_T7 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= '0'; + if FDC_CS = '1' and DMA_REQ = '0' then + NEXT_FCF_STATE <= FCF_T7; + else + NEXT_FCF_STATE <= FCF_IDLE; + end if; + end case; + end process FCF_DECODER; + + I_FDC: WF1772IP_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + CSn => FDCS_In, + RWn => nFDC_WR, + A1 => CA2, + A0 => CA1, + DATA_IN => CD_IN_FDC, + DATA_OUT => CD_OUT_FDC, +-- DATA_EN => CD_EN_FDC, + RDn => nRD_DATA, + TR00n => TRACK00, + IPn => nINDEX, + WPRTn => nWP, + DDEn => '0', -- Fixed to MFM. + HDTYPE => HD_DD_OUT, + MO => MOT_ON, + WG => WR_GATE, + WD => WR_DATA, + STEP => STEP, + DIRC => STEP_DIR, + DRQ => DMA_DRQ_I, + INTRQ => FDINT + ); +DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 +DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 +WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 +HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); +nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; +CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); +CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); +CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); +FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else + SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +--- WDC BSL REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + WDC_BSL <= "00"; + elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + else + WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); + end if; + end if; + END PROCESS; +--- DMA MODUS REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + DMA_MODUS <= x"0000"; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); + else + DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); + end if; + IF FB_B1 = '1' THEN + DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); + else + DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); + end if; + else + DMA_MODUS <= DMA_MODUS; + end if; + END PROCESS; +-- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + begin + if nRSTO = '0' or CLR_FIFO = '1' THEN + DMA_BYT_CNT <= x"00000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; + DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); + DMA_BYT_CNT(8 downto 0) <= "000000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then + DMA_BYT_CNT <= FB_AD; + else + DMA_BYT_CNT <= DMA_BYT_CNT; + end if; + END PROCESS; +-------------------------------------------------------------------- +FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +DMA_STATUS(0) <= '1'; -- DMA OK +DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS +DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; +DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else + '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; +DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + process(FDC_CLK, nRSTO, DMA_DRQ_REG) + begin + if nRSTO = '0' THEN + DMA_DRQ_REG <= "00"; + elsif rising_edge(FDC_CLK) then + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + else + DMA_DRQ_REG <= DMA_DRQ_REG; + end if; + END PROCESS; +-- DMA ADRESSE ------------------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_TOP <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then + DMA_TOP <= FB_AD(31 downto 24); + else + DMA_TOP <= DMA_TOP; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_HIGH <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then + DMA_HIGH <= FB_AD(23 downto 16); + else + DMA_HIGH <= DMA_HIGH; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + begin + DMA_MID <= DMA_MID; + if nRSTO = '0' THEN + DMA_MID <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_MID_CS = '1' then + DMA_MID <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_MID <= FB_AD(15 downto 8); + end if; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + begin + DMA_LOW <= DMA_LOW; + if nRSTO = '0' THEN + DMA_LOW <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_LOW_CS = '1'then + DMA_LOW <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_LOW <= FB_AD(7 downto 0); + end if; + end if; + END PROCESS; +-------------------------------------------------------------------------------------------- +DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 +DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 +DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 +DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 +FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +-- DIRECTZUGRIFF +DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD +DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG +DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG +FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +-- DMA RW TOGGLE ------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + begin + if nRSTO = '0' THEN + DMA_DIR_OLD <= '0'; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + DMA_DIR_OLD <= DMA_MODUS(8); + else + DMA_DIR_OLD <= DMA_DIR_OLD; + end if; + END PROCESS; +CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; +-- SCSI ---------------------------------------------------------------------------------- + I_SCSI: WF5380_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + ADR => CA2 & CA1 & CA0, + DATA_IN => CD_IN_FDC, + DATA_OUT => SCSI_DOUT, + --DATA_EN : out bit; + -- Bus and DMA controls: + CSn => '1', --SCSI_CSn, ABGESCHALTET + RDn => (not nFDC_WR) or (not SCSI_CS), + WRn => nFDC_WR or (not SCSI_CS), + EOPn => '1', + DACKn => nSCSI_DACK, + DRQ => SCSI_DRQ, + INT => SCSI_INT, +-- READY => + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => SCSI_PAR, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, -- wenn 1 dann output + RST_INn => nSCSI_RST, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => nSCSI_BUSY, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => nSCSI_SEL, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => '1', + ACK_OUTn => nSCSI_ACK, +-- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => nSCSI_ATN, +-- ATN_EN => ATN_EN, + REQ_INn => nSCSI_DRQ, +-- REQ_OUTn => REQ_OUTn, +-- REQ_EN => REQ_EN, + IOn_IN => nSCSI_I_O, +-- IOn_OUT => IOn_OUT, +-- IO_EN => IO_EN, + CDn_IN => nSCSI_C_D, +-- CDn_OUT => CDn_OUT, +-- CD_EN => CD_EN, + MSG_INn => nSCSI_MSG +-- MSG_OUTn => MSG_OUTn, +-- MSG_EN => MSG_EN + ); +-- SCSI ACSI --------------------------------------------------------------- +SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; +SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET +SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; +nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; +nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; +nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; +ACSI_DIR <= '0'; +ACSI_D <= "ZZZZZZZZ"; +nACSI_CS <= '1'; +ACSI_A1 <= CA1; +nACSI_RESET <= nRSTO; +nACSI_ACK <= '1'; +---------------------------------------------------------------------------- +-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns +---------------------------------------------------------------------------- +ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 +nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; +nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; +---------------------------------------------------------------------------- +-- ACIA KEYBOARD +---------------------------------------------------------------------------- + I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => FB_ADR(2), + CS1 => '1', + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_I, +-- DATA_EN => DATA_EN_ACIA_I, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => KEYB_RxD, + + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_KEYBDn, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); +ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 +KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL +FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; +-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + process(CLK2M, AMKB_RX, AMKB_REG) + begin + if rising_edge(CLK2M) then + IF AMKB_RX = '0' THEN + IF AMKB_REG < 16 THEN + AMKB_REG <= "00000"; + ELSE + AMKB_REG <= AMKB_REG - 1; + END IF; + ELSE + IF AMKB_REG > 15 THEN + AMKB_REG <= "11111"; + ELSE + AMKB_REG <= AMKB_REG + 1; + END IF; + END IF; + ELSE + AMKB_REG <= AMKB_REG; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- ACIA MIDI +---------------------------------------------------------------------------- + I_ACIA_MIDI: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => '0', + CS1 => FB_ADR(2), + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_II, +-- DATA_EN => DATA_EN_ACIA_II, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_MIDIn, + TXDATA => MIDI_OUT + --RTSn => -- Not used. + ); +MIDI_TLR <= MIDI_OUT; +MIDI_OLR <= MIDI_OUT; +FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +---------------------------------------------------------------------------- +-- MFP +---------------------------------------------------------------------------- + I_MFP: WF68901IP_TOP_SOC + port map( + -- System control: + CLK => MAIN_CLK, + RESETn => nRSTO, + -- Asynchronous bus control: + DSn => not LDS, + CSn => not MFP_CS, + RWn => nFB_WR, + DTACKn => DTACK_OUT_MFPn, + -- Data and Adresses: + RS => FB_ADR(5 downto 1), + DATA_IN => FB_AD(23 downto 16), + DATA_OUT => DATA_OUT_MFP, +-- DATA_EN => DATA_EN_MFP, + GPIP_IN(7) => not DMA_DRQ_Q, + GPIP_IN(6) => not RI, + GPIP_IN(5) => DINTn, + GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(3) => DSP_INT, + GPIP_IN(2) => not CTS, + GPIP_IN(1) => not DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction input. + -- Interrupt control: + IACKn => not MFP_INTACK, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => nMFP_INT, + -- Timers and timer control: + XTAL1 => CLK2M4576, + TAI => '0', + TBI => nBLANK, + -- TAO =>, + -- TBO =>, + -- TCO =>, + TDO => TDO, + -- Serial I/O control: + RC => TDO, + TC => TDO, + SI => RxD, + SO => TxD + -- SO_EN => MFP_SO_EN + -- DMA control: + -- RRn =>, + -- TRn => + ); + +MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 +MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 +LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; +FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; +DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else + '0' when FDINT = '1' else + '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; +-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) + begin + if nRSTO = '0' THEN + IRQ_ACIAn <= '1'; + elsif rising_edge(MAIN_CLK) then + IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; + else + IRQ_ACIAn <= IRQ_ACIAn; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- Sound +---------------------------------------------------------------------------- + I_SOUND: WF2149IP_TOP_SOC + port map( + SYS_CLK => MAIN_CLK, + RESETn => nRSTO, + + WAV_CLK => CLK2M, + SELn => '1', + + BDIR => SNDIR_I, + BC2 => '1', + BC1 => SNDCS_I, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 downto 24), + DA_OUT => DA_OUT_X, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => nnIDE_RES, + IO_A_OUT(6) => LP_DIR_X, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, +-- IO_A_OUT(2) => FDD_D1SEL, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => nSDSEL, + -- IO_A_EN =>, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => LP_D_X, + -- IO_B_EN => IO_B_EN, + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + +SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 +SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; +SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; +FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; +LP_DIR <= LP_DIR_X; + +END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak new file mode 100644 index 0000000..a339eda --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak @@ -0,0 +1,971 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:20 2009 + +library work; +use work.FalconIO_SDCard_IDE_CF_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +-- Entity Declaration + + +-- Entity Declaration + +ENTITY FalconIO_SDCard_IDE_CF IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + CLK2M : IN STD_LOGIC; + CLK500k : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + LP_BUSY : IN STD_LOGIC; + nACSI_DRQ : IN STD_LOGIC; + nACSI_INT : IN STD_LOGIC; + nSCSI_DRQ : IN STD_LOGIC; + nSCSI_MSG : IN STD_LOGIC; + MIDI_IN : IN STD_LOGIC; + RxD : IN STD_LOGIC; + CTS : IN STD_LOGIC; + RI : IN STD_LOGIC; + DCD : IN STD_LOGIC; + AMKB_RX : IN STD_LOGIC; + PIC_AMKB_RX : IN STD_LOGIC; + IDE_RDY : IN STD_LOGIC; + IDE_INT : IN STD_LOGIC; + WP_CS_CARD : IN STD_LOGIC; + nINDEX : IN STD_LOGIC; + TRACK00 : IN STD_LOGIC; + nRD_DATA : IN STD_LOGIC; + nDCHG : IN STD_LOGIC; + SD_DATA0 : IN STD_LOGIC; + SD_DATA1 : IN STD_LOGIC; + SD_DATA2 : IN STD_LOGIC; + SD_CARD_DEDECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + nDACK0 : IN STD_LOGIC; + nFB_WR : INOUT STD_LOGIC; + WP_CF_CARD : IN STD_LOGIC; + nWP : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + HD_DD : IN STD_LOGIC; + nSCSI_C_D : IN STD_LOGIC; + nSCSI_I_O : IN STD_LOGIC; + CLK2M4576 : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + VSYNC : IN STD_LOGIC; + HSYNC : IN STD_LOGIC; + DSP_INT : IN STD_LOGIC; + nBLANK : IN STD_LOGIC; + FDC_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); + nIDE_CS1 : OUT STD_LOGIC; + nIDE_CS0 : OUT STD_LOGIC; + LP_STR : OUT STD_LOGIC; + LP_DIR : OUT STD_LOGIC; + nACSI_ACK : OUT STD_LOGIC; + nACSI_RESET : OUT STD_LOGIC; + nACSI_CS : OUT STD_LOGIC; + ACSI_DIR : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + nSCSI_ACK : OUT STD_LOGIC; + nSCSI_ATN : OUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + YM_QA : OUT STD_LOGIC; + YM_QC : OUT STD_LOGIC; + YM_QB : OUT STD_LOGIC; + nSDSEL : OUT STD_LOGIC; + STEP : OUT STD_LOGIC; + MOT_ON : OUT STD_LOGIC; + nRP_LDS : OUT STD_LOGIC; + nRP_UDS : OUT STD_LOGIC; + nROM4 : OUT STD_LOGIC; + nROM3 : OUT STD_LOGIC; + nCF_CS1 : OUT STD_LOGIC; + nCF_CS0 : OUT STD_LOGIC; + nIDE_RD : INOUT STD_LOGIC; + nIDE_WR : INOUT STD_LOGIC; + AMKB_TX : OUT STD_LOGIC; + IDE_RES : OUT STD_LOGIC; + DTR : OUT STD_LOGIC; + RTS : OUT STD_LOGIC; + TxD : OUT STD_LOGIC; + MIDI_OLR : OUT STD_LOGIC; + MIDI_TLR : OUT STD_LOGIC; + nDREQ0 : OUT STD_LOGIC; + DSA_D : OUT STD_LOGIC; + nMFP_INT : OUT STD_LOGIC; + FALCON_IO_TA : OUT STD_LOGIC; + STEP_DIR : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC; + WR_GATE : OUT STD_LOGIC; + DMA_DRQ : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_PAR : INOUT STD_LOGIC; + nSCSI_SEL : INOUT STD_LOGIC; + nSCSI_BUSY : INOUT STD_LOGIC; + nSCSI_RST : INOUT STD_LOGIC; + SD_CD_DATA3 : INOUT STD_LOGIC; + SD_CDM_D1 : INOUT STD_LOGIC + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END FalconIO_SDCard_IDE_CF; + + +-- Architecture Body + +ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS +-- system +signal SYS_CLK : STD_LOGIC; +signal RESETn : STD_LOGIC; +signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS +signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS +signal BYT : STD_LOGIC; -- WENN BYT -> 1 +signal LONG : STD_LOGIC; -- WENN -> 1 +-- KEYBOARD MIDI +signal ACIA_CS_I : STD_LOGIC; +signal IRQ_KEYBDn : STD_LOGIC; +signal IRQ_MIDIn : STD_LOGIC; +signal KEYB_RxD : STD_LOGIC; +signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); +signal MIDI_OUT : STD_LOGIC; +signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); +signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); +-- MFP +signal MFP_CS : STD_LOGIC; +signal MFP_INTACK : STD_LOGIC; +signal LDS : STD_LOGIC; +signal DTACK_OUT_MFPn : STD_LOGIC; +signal IRQ_ACIAn : STD_LOGIC; +signal DINTn : STD_LOGIC; +signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); +signal TDO : STD_LOGIC; +-- SOUND +signal SNDCS : STD_LOGIC; +signal SNDCS_I : STD_LOGIC; +signal SNDIR_I : STD_LOGIC; +signal LP_DIR_X : STD_LOGIC; +signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); +signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); +-- DIV +signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE +signal ROM_CS : STD_LOGIC; +-- DMA UND FLOPPY +signal DMA_DATEN_CS : STD_LOGIC; +signal DMA_MODUS_CS : STD_LOGIC; +signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); +signal WDC_BSL_CS : STD_LOGIC; +signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal HD_DD_OUT : STD_LOGIC; +signal FDCS_In : STD_LOGIC; +signal CA0 : STD_LOGIC; +signal CA1 : STD_LOGIC; +signal CA2 : STD_LOGIC; +signal FDINT : STD_LOGIC; +signal FDRQ : STD_LOGIC; +signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_TOP_CS : STD_LOGIC; +signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_HIGH_CS : STD_LOGIC; +signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_MID_CS : STD_LOGIC; +signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_LOW_CS : STD_LOGIC; +signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_DIRM_CS : STD_LOGIC; +signal DMA_ADR_CS : STD_LOGIC; +signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); +signal DMA_DIR_OLD : STD_LOGIC; +signal DMA_BYT_CNT_CS : STD_LOGIC; +signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); +signal CLR_FIFO : STD_LOGIC; +signal DMA_DRQ_I : STD_LOGIC; +signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); +signal DMA_DRQQ : STD_LOGIC; +signal DMA_DRQ_Q : STD_LOGIC; +signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); +signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal RDF_RDE : STD_LOGIC; +signal RDF_WRE : STD_LOGIC; +signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal WRF_RDE : STD_LOGIC; +signal WRF_WRE : STD_LOGIC; +signal nFDC_WR : STD_LOGIC; +type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); +signal FCF_STATE : FCF_STATES; +signal NEXT_FCF_STATE : FCF_STATES; +signal DMA_REQ : STD_LOGIC; +signal FDC_CS : STD_LOGIC; +signal FCF_CS : STD_LOGIC; +signal FCF_APH : STD_LOGIC; +signal DMA_AZ_CS : STD_LOGIC; +signal DMA_ACTIV : STD_LOGIC; +signal DMA_ACTIV_NEW : STD_LOGIC; +signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); +-- SCSI +signal SCSI_CS : STD_LOGIC; +signal SCSI_CSn : STD_LOGIC; +signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal nSCSI_DACK : STD_LOGIC; +signal SCSI_DRQ : STD_LOGIC; +signal SCSI_INT : STD_LOGIC; +signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); +signal DB_EN : STD_LOGIC; +signal DBP_OUTn : STD_LOGIC; +signal DBP_EN : STD_LOGIC; +signal RST_OUTn : STD_LOGIC; +signal RST_EN : STD_LOGIC; +signal BSY_OUTn : STD_LOGIC; +signal BSY_EN : STD_LOGIC; +signal SEL_OUTn : STD_LOGIC; +signal SEL_EN : STD_LOGIC; +-- IDE +signal nnIDE_RES : STD_LOGIC; +signal IDE_CF_CS : STD_LOGIC; +signal IDE_CF_TA : STD_LOGIC; +signal NEXT_nIDE_RD : STD_LOGIC; +signal NEXT_nIDE_WR : STD_LOGIC; +type CMD_STATES is( IDLE, T1, T6, T7); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; + + +BEGIN +LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; +BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; +FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; +FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; + +FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; +SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE + '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; +nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; +nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; +nDREQ0 <= '0'; +---------------------------------------------------------------------------- +-- SD +---------------------------------------------------------------------------- +SD_CLK <= 'Z'; +SD_CD_DATA3 <= 'Z'; +SD_CDM_D1 <= 'Z'; +---------------------------------------------------------------------------- +-- IDE +---------------------------------------------------------------------------- +CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + begin + if nRSTO = '0' then + CMD_STATE <= IDLE; + elsif rising_edge(MAIN_CLK) then + CMD_STATE <= NEXT_CMD_STATE; -- go to next + nIDE_RD <= NEXT_nIDE_RD; -- go to next + nIDE_WR <= NEXT_nIDE_WR; -- go to next + else + CMD_STATE <= CMD_STATE; -- halten + nIDE_RD <= nIDE_RD; -- halten + nIDE_WR <= nIDE_WR; -- halten + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + begin + case CMD_STATE is + when IDLE => + IDE_CF_TA <= '0'; + if IDE_CF_CS = '1' then + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T1; + else + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end if; + when T1 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + when T6 => + IF IDE_RDY = '1' then + IDE_CF_TA <= '1'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= T7; + else + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + end if; + when T7 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end case; + end process CMD_DECODER; + +IDE_RES <= not nnIDE_RES and nRSTO; +IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 +nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F +nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F +nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F +nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F +----------------------------------------------------------------------------------------------------------------------------------------- +-- ACSI, SCSI UND FLOPPY WD1772 +------------------------------------------------------------------------------------------------------------------------------------------- +-- daten read fifo + RDF: dcfifo0 + port map( + aclr => CLR_FIFO, + data => RDF_DIN, + rdclk => MAIN_CLK, + rdreq => RDF_RDE, + wrclk => FDC_CLK, + wrreq => RDF_WRE, + q => RDF_DOUT, + wrusedw => RDF_AZ + ); +FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY +FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY +RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE +FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; +-- daten write fifo + WRF: dcfifo1 + port map( + aclr => CLR_FIFO, + data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + rdclk => FDC_CLK, + rdreq => WRF_RDE, + wrclk => MAIN_CLK, + wrreq => WRF_WRE, + q => WRF_DOUT, + rdusedw => WRF_AZ + ); +CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB +DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG +FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + begin + if nRSTO = '0' THEN + WRF_WRE <= '0'; + elsif rising_edge(MAIN_CLK) then + IF FCF_APH = '1' and nFB_WR = '0' then + WRF_WRE <= '1'; + else + WRF_WRE <= '0'; + end if; + else + WRF_WRE <= WRF_WRE; + end if; + END PROCESS; + +FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + begin + if nRSTO = '0' then + FCF_STATE <= FCF_IDLE; + DMA_ACTIV <= '0'; + elsif rising_edge(FDC_CLK) then + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + else + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + end if; + end process FCF_REG; + +FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + begin + if nRSTO = '0' then + FDC_OUT <= x"00"; + elsif rising_edge(FDC_CLK) and FDCS_In = '0' then + FDC_OUT <= CD_OUT_FDC; -- set + else + FDC_OUT <= FDC_OUT; -- halten + end if; + end process FDC_REG; + +DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; +FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; +SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + + FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + begin + case FCF_STATE is + when FCF_IDLE => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + DMA_ACTIV_NEW <= DMA_REQ; + NEXT_FCF_STATE <= FCF_T0; + else + DMA_ACTIV_NEW <= '0'; + NEXT_FCF_STATE <= FCF_IDLE; + end if; + when FCF_T0 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= DMA_REQ; + WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO + if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start + else + NEXT_FCF_STATE <= FCF_T1; + end if; + when FCF_T1 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T2; + when FCF_T2 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T3; + when FCF_T3 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T6; + when FCF_T6 => + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO + NEXT_FCF_STATE <= FCF_T7; + when FCF_T7 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= '0'; + if FDC_CS = '1' and DMA_REQ = '0' then + NEXT_FCF_STATE <= FCF_T7; + else + NEXT_FCF_STATE <= FCF_IDLE; + end if; + end case; + end process FCF_DECODER; + + I_FDC: WF1772IP_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + CSn => FDCS_In, + RWn => nFDC_WR, + A1 => CA2, + A0 => CA1, + DATA_IN => CD_IN_FDC, + DATA_OUT => CD_OUT_FDC, +-- DATA_EN => CD_EN_FDC, + RDn => nRD_DATA, + TR00n => TRACK00, + IPn => nINDEX, + WPRTn => nWP, + DDEn => '0', -- Fixed to MFM. + HDTYPE => HD_DD_OUT, + MO => MOT_ON, + WG => WR_GATE, + WD => WR_DATA, + STEP => STEP, + DIRC => STEP_DIR, + DRQ => DMA_DRQ_I, + INTRQ => FDINT + ); +DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 +DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 +WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 +HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); +nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; +CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); +CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); +CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); +FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else + SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +--- WDC BSL REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + WDC_BSL <= "00"; + elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + else + WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); + end if; + end if; + END PROCESS; +--- DMA MODUS REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + DMA_MODUS <= x"0000"; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); + else + DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); + end if; + IF FB_B1 = '1' THEN + DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); + else + DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); + end if; + else + DMA_MODUS <= DMA_MODUS; + end if; + END PROCESS; +-- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + begin + if nRSTO = '0' or CLR_FIFO = '1' THEN + DMA_BYT_CNT <= x"00000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; + DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); + DMA_BYT_CNT(8 downto 0) <= "000000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then + DMA_BYT_CNT <= FB_AD; + else + DMA_BYT_CNT <= DMA_BYT_CNT; + end if; + END PROCESS; +-------------------------------------------------------------------- +FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +DMA_STATUS(0) <= '1'; -- DMA OK +DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS +DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; +DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else + '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; +DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + process(FDC_CLK, nRSTO, DMA_DRQ_REG) + begin + if nRSTO = '0' THEN + DMA_DRQ_REG <= "00"; + elsif rising_edge(FDC_CLK) then + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + else + DMA_DRQ_REG <= DMA_DRQ_REG; + end if; + END PROCESS; +-- DMA ADRESSE ------------------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_TOP <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then + DMA_TOP <= FB_AD(31 downto 24); + else + DMA_TOP <= DMA_TOP; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_HIGH <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then + DMA_HIGH <= FB_AD(23 downto 16); + else + DMA_HIGH <= DMA_HIGH; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + begin + DMA_MID <= DMA_MID; + if nRSTO = '0' THEN + DMA_MID <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_MID_CS = '1' then + DMA_MID <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_MID <= FB_AD(15 downto 8); + end if; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + begin + DMA_LOW <= DMA_LOW; + if nRSTO = '0' THEN + DMA_LOW <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_LOW_CS = '1'then + DMA_LOW <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_LOW <= FB_AD(7 downto 0); + end if; + end if; + END PROCESS; +-------------------------------------------------------------------------------------------- +DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 +DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 +DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 +DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 +FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +-- DIRECTZUGRIFF +DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD +DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG +DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG +FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +-- DMA RW TOGGLE ------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + begin + if nRSTO = '0' THEN + DMA_DIR_OLD <= '0'; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + DMA_DIR_OLD <= DMA_MODUS(8); + else + DMA_DIR_OLD <= DMA_DIR_OLD; + end if; + END PROCESS; +CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; +-- SCSI ---------------------------------------------------------------------------------- + I_SCSI: WF5380_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + ADR => CA2 & CA1 & CA0, + DATA_IN => CD_IN_FDC, + DATA_OUT => SCSI_DOUT, + --DATA_EN : out bit; + -- Bus and DMA controls: + CSn => '1', --SCSI_CSn, ABGESCHALTET + RDn => (not nFDC_WR) or (not SCSI_CS), + WRn => nFDC_WR or (not SCSI_CS), + EOPn => '1', + DACKn => nSCSI_DACK, + DRQ => SCSI_DRQ, + INT => SCSI_INT, +-- READY => + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => SCSI_PAR, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, -- wenn 1 dann output + RST_INn => nSCSI_RST, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => nSCSI_BUSY, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => nSCSI_SEL, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => '1', + ACK_OUTn => nSCSI_ACK, +-- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => nSCSI_ATN, +-- ATN_EN => ATN_EN, + REQ_INn => nSCSI_DRQ, +-- REQ_OUTn => REQ_OUTn, +-- REQ_EN => REQ_EN, + IOn_IN => nSCSI_I_O, +-- IOn_OUT => IOn_OUT, +-- IO_EN => IO_EN, + CDn_IN => nSCSI_C_D, +-- CDn_OUT => CDn_OUT, +-- CD_EN => CD_EN, + MSG_INn => nSCSI_MSG +-- MSG_OUTn => MSG_OUTn, +-- MSG_EN => MSG_EN + ); +-- SCSI ACSI --------------------------------------------------------------- +SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; +SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET +SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; +nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; +nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; +nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; +ACSI_DIR <= '0'; +ACSI_D <= "ZZZZZZZZ"; +nACSI_CS <= '1'; +ACSI_A1 <= CA1; +nACSI_RESET <= nRSTO; +nACSI_ACK <= '1'; +---------------------------------------------------------------------------- +-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns +---------------------------------------------------------------------------- +ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 +nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; +nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; +---------------------------------------------------------------------------- +-- ACIA KEYBOARD +---------------------------------------------------------------------------- + I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => FB_ADR(2), + CS1 => '1', + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_I, +-- DATA_EN => DATA_EN_ACIA_I, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => KEYB_RxD, + + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_KEYBDn, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); +ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 +KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL +FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; +-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + process(CLK2M, AMKB_RX, AMKB_REG) + begin + if rising_edge(CLK2M) then + IF AMKB_RX = '0' THEN + IF AMKB_REG < 16 THEN + AMKB_REG <= "00000"; + ELSE + AMKB_REG <= AMKB_REG - 1; + END IF; + ELSE + IF AMKB_REG > 15 THEN + AMKB_REG <= "11111"; + ELSE + AMKB_REG <= AMKB_REG + 1; + END IF; + END IF; + ELSE + AMKB_REG <= AMKB_REG; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- ACIA MIDI +---------------------------------------------------------------------------- + I_ACIA_MIDI: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => '0', + CS1 => FB_ADR(2), + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_II, +-- DATA_EN => DATA_EN_ACIA_II, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_MIDIn, + TXDATA => MIDI_OUT + --RTSn => -- Not used. + ); +MIDI_TLR <= MIDI_OUT; +MIDI_OLR <= MIDI_OUT; +FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +---------------------------------------------------------------------------- +-- MFP +---------------------------------------------------------------------------- + I_MFP: WF68901IP_TOP_SOC + port map( + -- System control: + CLK => MAIN_CLK, + RESETn => nRSTO, + -- Asynchronous bus control: + DSn => not LDS, + CSn => not MFP_CS, + RWn => nFB_WR, + DTACKn => DTACK_OUT_MFPn, + -- Data and Adresses: + RS => FB_ADR(5 downto 1), + DATA_IN => FB_AD(23 downto 16), + DATA_OUT => DATA_OUT_MFP, +-- DATA_EN => DATA_EN_MFP, + GPIP_IN(7) => not DMA_DRQ_Q, + GPIP_IN(6) => not RI, + GPIP_IN(5) => DINTn, + GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(3) => DSP_INT, + GPIP_IN(2) => not CTS, + GPIP_IN(1) => not DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction input. + -- Interrupt control: + IACKn => not MFP_INTACK, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => nMFP_INT, + -- Timers and timer control: + XTAL1 => CLK2M4576, + TAI => '0', + TBI => nBLANK, + -- TAO =>, + -- TBO =>, + -- TCO =>, + TDO => TDO, + -- Serial I/O control: + RC => TDO, + TC => TDO, + SI => RxD, + SO => TxD + -- SO_EN => MFP_SO_EN + -- DMA control: + -- RRn =>, + -- TRn => + ); + +MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 +MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 +LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; +FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; +DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else + '0' when FDINT = '1' else + '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1'; +-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) + begin + if nRSTO = '0' THEN + IRQ_ACIAn <= '1'; + elsif rising_edge(MAIN_CLK) then + IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; + else + IRQ_ACIAn <= IRQ_ACIAn; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- Sound +---------------------------------------------------------------------------- + I_SOUND: WF2149IP_TOP_SOC + port map( + SYS_CLK => MAIN_CLK, + RESETn => nRSTO, + + WAV_CLK => CLK2M, + SELn => '1', + + BDIR => SNDIR_I, + BC2 => '1', + BC1 => SNDCS_I, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 downto 24), + DA_OUT => DA_OUT_X, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => nnIDE_RES, + IO_A_OUT(6) => LP_DIR_X, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, +-- IO_A_OUT(2) => FDD_D1SEL, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => nSDSEL, + -- IO_A_EN =>, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => LP_D_X, + -- IO_B_EN => IO_B_EN, + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + +SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 +SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; +SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; +FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; +LP_DIR <= LP_DIR_X; + +END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd new file mode 100644 index 0000000..edef447 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd @@ -0,0 +1,406 @@ +---------------------------------------------------------------------- +---- ---- +---- Atari Coldfire IP Core ---- +---- ---- +---- This file is part of the Atari Coldfire project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- 1.0 Initial Release, 20090925. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package FalconIO_SDCard_IDE_CF_PKG is + component WF25915IP_TOP_V1_SOC -- GLUE. + port ( + -- Clock system: + GL_CLK : in std_logic; -- Originally 8MHz. + GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. + + -- Core address select: + GL_ROMSEL_FC_E0n : in std_logic; + EN_RAM_14MB : in std_logic; + -- Adress decoder outputs: + GL_ROM_6n : out std_logic; -- STE. + GL_ROM_5n : out std_logic; -- STE. + GL_ROM_4n : out std_logic; -- ST. + GL_ROM_3n : out std_logic; -- ST. + GL_ROM_2n : out std_logic; + GL_ROM_1n : out std_logic; + GL_ROM_0n : out std_logic; + + GL_ACIACS : out std_logic; + GL_MFPCSn : out std_logic; + GL_SNDCSn : out std_logic; + GL_FCSn : out std_logic; + + GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. + GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. + + GL_STE_RTCCSn : out std_logic; --STE only. + GL_STE_RTC_WRn : out std_logic; --STE only. + GL_STE_RTC_RDn : out std_logic; --STE only. + + -- 6800 peripheral control, + GL_VPAn : out std_logic; + GL_VMAn : in std_logic; + + GL_DMA_SYNC : in std_logic; + GL_DEVn : out std_logic; + GL_RAMn : out std_logic; + GL_DMAn : out std_logic; + + -- Interrupt system: + -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. + GL_AVECn : out std_logic; + GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. + GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. + GL_MFPINTn : in std_logic; -- ST. + GL_STE_EINT3n : in std_logic; --STE only. + GL_STE_EINT5n : in std_logic; --STE only. + GL_STE_EINT7n : in std_logic; --STE only. + GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. + GL_IACKn : out std_logic; -- ST. + GL_STE_IPL2n : out std_logic; --STE only. + GL_STE_IPL1n : out std_logic; --STE only. + GL_STE_IPL0n : out std_logic; --STE only. + + -- Video timing: + GL_BLANKn : out std_logic; + GL_DE : out std_logic; + GL_MULTISYNC : in std_logic_vector(3 downto 2); + GL_VIDEO_HIMODE : out std_logic; + GL_HSYNC_INn : in std_logic; + GL_HSYNC_OUTn : out std_logic; + GL_VSYNC_INn : in std_logic; + GL_VSYNC_OUTn : out std_logic; + GL_SYNC_OUT_EN : out std_logic; + + -- Bus arstd_logicration control: + GL_RDY_INn : in std_logic; + GL_RDY_OUTn : out std_logic; + GL_BRn : out std_logic; + GL_BGIn : in std_logic; + GL_BGOn : out std_logic; + GL_BGACK_INn : in std_logic; + GL_BGACK_OUTn : out std_logic; + + -- Adress and data bus: + GL_ADDRESS : in std_logic_vector(23 downto 1); + -- ST: put the data bus to 1 downto 0. + -- STE: put the data out bus to 15 downto 0. + GL_DATA_IN : in std_logic_vector(7 downto 0); + GL_DATA_OUT : out std_logic_vector(15 downto 0); + GL_DATA_EN : out std_logic; + + -- Asynchronous bus control: + GL_RWn_IN : in std_logic; + GL_RWn_OUT : out std_logic; + GL_AS_INn : in std_logic; + GL_AS_OUTn : out std_logic; + GL_UDS_INn : in std_logic; + GL_UDS_OUTn : out std_logic; + GL_LDS_INn : in std_logic; + GL_LDS_OUTn : out std_logic; + GL_DTACK_INn : in std_logic; + GL_DTACK_OUTn : out std_logic; + GL_CTRL_EN : out std_logic; + + -- System control: + GL_RESETn : in std_logic; + GL_BERRn : out std_logic; + + -- Processor function codes: + GL_FC : in std_logic_vector(2 downto 0); + + -- STE enhancements: + GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). + GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. + GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. + GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. + GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. + GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. + GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. + GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. + GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. + GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. + GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. + GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. + GL_STE_PENn : in std_logic; -- Input of the light pen. + GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. + GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. + ); + end component WF25915IP_TOP_V1_SOC; + + component WF5380_TOP_SOC + port ( + CLK : in std_logic; + RESETn : in std_logic; + ADR : in std_logic_vector(2 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + CSn : in std_logic; + RDn : in std_logic; + WRn : in std_logic; + EOPn : in std_logic; + DACKn : in std_logic; + DRQ : out std_logic; + INT : out std_logic; + READY : out std_logic; + DB_INn : in std_logic_vector(7 downto 0); + DB_OUTn : out std_logic_vector(7 downto 0); + DB_EN : out std_logic; + DBP_INn : in std_logic; + DBP_OUTn : out std_logic; + DBP_EN : out std_logic; + RST_INn : in std_logic; + RST_OUTn : out std_logic; + RST_EN : out std_logic; + BSY_INn : in std_logic; + BSY_OUTn : out std_logic; + BSY_EN : out std_logic; + SEL_INn : in std_logic; + SEL_OUTn : out std_logic; + SEL_EN : out std_logic; + ACK_INn : in std_logic; + ACK_OUTn : out std_logic; + ACK_EN : out std_logic; + ATN_INn : in std_logic; + ATN_OUTn : out std_logic; + ATN_EN : out std_logic; + REQ_INn : in std_logic; + REQ_OUTn : out std_logic; + REQ_EN : out std_logic; + IOn_IN : in std_logic; + IOn_OUT : out std_logic; + IO_EN : out std_logic; + CDn_IN : in std_logic; + CDn_OUT : out std_logic; + CD_EN : out std_logic; + MSG_INn : in std_logic; + MSG_OUTn : out std_logic; + MSG_EN : out std_logic + ); + end component WF5380_TOP_SOC; + + component WF1772IP_TOP_SOC -- FDC. + port ( + CLK : in std_logic; -- 16MHz clock! + RESETn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + A1, A0 : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + RDn : in std_logic; + TR00n : in std_logic; + IPn : in std_logic; + WPRTn : in std_logic; + DDEn : in std_logic; + HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. + MO : out std_logic; + WG : out std_logic; + WD : out std_logic; + STEP : out std_logic; + DIRC : out std_logic; + DRQ : out std_logic; + INTRQ : out std_logic + ); + end component WF1772IP_TOP_SOC; + + component WF68901IP_TOP_SOC -- MFP. + port ( -- System control: + CLK : in std_logic; + RESETn : in std_logic; + + -- Asynchronous bus control: + DSn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in std_logic_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + GPIP_IN : in std_logic_vector(7 downto 0); + GPIP_OUT : out std_logic_vector(7 downto 0); + GPIP_EN : out std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in std_logic; + IEIn : in std_logic; + IEOn : out std_logic; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. + TAI : in std_logic; + TBI : in std_logic; + TAO : out std_logic; + TBO : out std_logic; + TCO : out std_logic; + TDO : out std_logic; + + -- Serial I/O control: + RC : in std_logic; + TC : in std_logic; + SI : in std_logic; + SO : out std_logic; + SO_EN : out std_logic; + + -- DMA control: + RRn : out std_logic; + TRn : out std_logic + ); + end component WF68901IP_TOP_SOC; + + component WF2149IP_TOP_SOC -- Sound. + port( + + SYS_CLK : in std_logic; -- Read the inforation in the header! + RESETn : in std_logic; + + WAV_CLK : in std_logic; -- Read the inforation in the header! + SELn : in std_logic; + + BDIR : in std_logic; + BC2, BC1 : in std_logic; + + A9n, A8 : in std_logic; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out std_logic; + + IO_A_IN : in std_logic_vector(7 downto 0); + IO_A_OUT : out std_logic_vector(7 downto 0); + IO_A_EN : out std_logic; + IO_B_IN : in std_logic_vector(7 downto 0); + IO_B_OUT : out std_logic_vector(7 downto 0); + IO_B_EN : out std_logic; + + OUT_A : out std_logic; -- Analog (PWM) outputs. + OUT_B : out std_logic; + OUT_C : out std_logic + ); + end component WF2149IP_TOP_SOC; + + component WF6850IP_TOP_SOC -- ACIA. + port ( + CLK : in std_logic; + RESETn : in std_logic; + + CS2n, CS1, CS0 : in std_logic; + E : in std_logic; + RWn : in std_logic; + RS : in std_logic; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + + TXCLK : in std_logic; + RXCLK : in std_logic; + RXDATA : in std_logic; + CTSn : in std_logic; + DCDn : in std_logic; + + IRQn : out std_logic; + TXDATA : out std_logic; + RTSn : out std_logic + ); + end component WF6850IP_TOP_SOC; + + component WF_SD_CARD + port ( + RESETn : in std_logic; + CLK : in std_logic; + ACSI_A1 : in std_logic; + ACSI_CSn : in std_logic; + ACSI_ACKn : in std_logic; + ACSI_INTn : out std_logic; + ACSI_DRQn : out std_logic; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out std_logic; + MC_DO : in std_logic; + MC_PIO_DMAn : in std_logic; + MC_RWn : in std_logic; + MC_CLR_CMD : in std_logic; + MC_DONE : out std_logic; + MC_GOT_CMD : out std_logic; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out std_logic + ); + end component WF_SD_CARD; + + component dcfifo0 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + end component dcfifo0; + + component dcfifo1 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + end component; + + +end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak new file mode 100644 index 0000000..4f42cf2 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak @@ -0,0 +1,406 @@ +---------------------------------------------------------------------- +---- ---- +---- Atari Coldfire IP Core ---- +---- ---- +---- This file is part of the Atari Coldfire project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- 1.0 Initial Release, 20090925. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package FalconIO_SDCard_IDE_CF_PKG is + component WF25915IP_TOP_V1_SOC -- GLUE. + port ( + -- Clock system: + GL_CLK : in std_logic; -- Originally 8MHz. + GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. + + -- Core address select: + GL_ROMSEL_FC_E0n : in std_logic; + EN_RAM_14MB : in std_logic; + -- Adress decoder outputs: + GL_ROM_6n : out std_logic; -- STE. + GL_ROM_5n : out std_logic; -- STE. + GL_ROM_4n : out std_logic; -- ST. + GL_ROM_3n : out std_logic; -- ST. + GL_ROM_2n : out std_logic; + GL_ROM_1n : out std_logic; + GL_ROM_0n : out std_logic; + + GL_ACIACS : out std_logic; + GL_MFPCSn : out std_logic; + GL_SNDCSn : out std_logic; + GL_FCSn : out std_logic; + + GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. + GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. + + GL_STE_RTCCSn : out std_logic; --STE only. + GL_STE_RTC_WRn : out std_logic; --STE only. + GL_STE_RTC_RDn : out std_logic; --STE only. + + -- 6800 peripheral control, + GL_VPAn : out std_logic; + GL_VMAn : in std_logic; + + GL_DMA_SYNC : in std_logic; + GL_DEVn : out std_logic; + GL_RAMn : out std_logic; + GL_DMAn : out std_logic; + + -- Interrupt system: + -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. + GL_AVECn : out std_logic; + GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. + GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. + GL_MFPINTn : in std_logic; -- ST. + GL_STE_EINT3n : in std_logic; --STE only. + GL_STE_EINT5n : in std_logic; --STE only. + GL_STE_EINT7n : in std_logic; --STE only. + GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. + GL_IACKn : out std_logic; -- ST. + GL_STE_IPL2n : out std_logic; --STE only. + GL_STE_IPL1n : out std_logic; --STE only. + GL_STE_IPL0n : out std_logic; --STE only. + + -- Video timing: + GL_BLANKn : out std_logic; + GL_DE : out std_logic; + GL_MULTISYNC : in std_logic_vector(3 downto 2); + GL_VIDEO_HIMODE : out std_logic; + GL_HSYNC_INn : in std_logic; + GL_HSYNC_OUTn : out std_logic; + GL_VSYNC_INn : in std_logic; + GL_VSYNC_OUTn : out std_logic; + GL_SYNC_OUT_EN : out std_logic; + + -- Bus arstd_logicration control: + GL_RDY_INn : in std_logic; + GL_RDY_OUTn : out std_logic; + GL_BRn : out std_logic; + GL_BGIn : in std_logic; + GL_BGOn : out std_logic; + GL_BGACK_INn : in std_logic; + GL_BGACK_OUTn : out std_logic; + + -- Adress and data bus: + GL_ADDRESS : in std_logic_vector(23 downto 1); + -- ST: put the data bus to 1 downto 0. + -- STE: put the data out bus to 15 downto 0. + GL_DATA_IN : in std_logic_vector(7 downto 0); + GL_DATA_OUT : out std_logic_vector(15 downto 0); + GL_DATA_EN : out std_logic; + + -- Asynchronous bus control: + GL_RWn_IN : in std_logic; + GL_RWn_OUT : out std_logic; + GL_AS_INn : in std_logic; + GL_AS_OUTn : out std_logic; + GL_UDS_INn : in std_logic; + GL_UDS_OUTn : out std_logic; + GL_LDS_INn : in std_logic; + GL_LDS_OUTn : out std_logic; + GL_DTACK_INn : in std_logic; + GL_DTACK_OUTn : out std_logic; + GL_CTRL_EN : out std_logic; + + -- System control: + GL_RESETn : in std_logic; + GL_BERRn : out std_logic; + + -- Processor function codes: + GL_FC : in std_logic_vector(2 downto 0); + + -- STE enhancements: + GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). + GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. + GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. + GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. + GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. + GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. + GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. + GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. + GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. + GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. + GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. + GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. + GL_STE_PENn : in std_logic; -- Input of the light pen. + GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. + GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. + ); + end component WF25915IP_TOP_V1_SOC; + + component WF5380_TOP_SOC + port ( + CLK : in std_logic; + RESETn : in std_logic; + ADR : in std_logic_vector(2 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + CSn : in std_logic; + RDn : in std_logic; + WRn : in std_logic; + EOPn : in std_logic; + DACKn : in std_logic; + DRQ : out std_logic; + INT : out std_logic; + READY : out std_logic; + DB_INn : in std_logic_vector(7 downto 0); + DB_OUTn : out std_logic_vector(7 downto 0); + DB_EN : out std_logic; + DBP_INn : in std_logic; + DBP_OUTn : out std_logic; + DBP_EN : out std_logic; + RST_INn : in std_logic; + RST_OUTn : out std_logic; + RST_EN : out std_logic; + BSY_INn : in std_logic; + BSY_OUTn : out std_logic; + BSY_EN : out std_logic; + SEL_INn : in std_logic; + SEL_OUTn : out std_logic; + SEL_EN : out std_logic; + ACK_INn : in std_logic; + ACK_OUTn : out std_logic; + ACK_EN : out std_logic; + ATN_INn : in std_logic; + ATN_OUTn : out std_logic; + ATN_EN : out std_logic; + REQ_INn : in std_logic; + REQ_OUTn : out std_logic; + REQ_EN : out std_logic; + IOn_IN : in std_logic; + IOn_OUT : out std_logic; + IO_EN : out std_logic; + CDn_IN : in std_logic; + CDn_OUT : out std_logic; + CD_EN : out std_logic; + MSG_INn : in std_logic; + MSG_OUTn : out std_logic; + MSG_EN : out std_logic + ); + end component WF5380_TOP_SOC; + + component WF1772IP_TOP_SOC -- FDC. + port ( + CLK : in std_logic; -- 16MHz clock! + RESETn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + A1, A0 : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + RDn : in std_logic; + TR00n : in std_logic; + IPn : in std_logic; + WPRTn : in std_logic; + DDEn : in std_logic; + HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. + MO : out std_logic; + WG : out std_logic; + WD : out std_logic; + STEP : out std_logic; + DIRC : out std_logic; + DRQ : out std_logic; + INTRQ : out std_logic + ); + end component WF1772IP_TOP_SOC; + + component WF68901IP_TOP_SOC -- MFP. + port ( -- System control: + CLK : in std_logic; + RESETn : in std_logic; + + -- Asynchronous bus control: + DSn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in std_logic_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + GPIP_IN : in std_logic_vector(7 downto 0); + GPIP_OUT : out std_logic_vector(7 downto 0); + GPIP_EN : out std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in std_logic; + IEIn : in std_logic; + IEOn : out std_logic; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. + TAI : in std_logic; + TBI : in std_logic; + TAO : out std_logic; + TBO : out std_logic; + TCO : out std_logic; + TDO : out std_logic; + + -- Serial I/O control: + RC : in std_logic; + TC : in std_logic; + SI : in std_logic; + SO : out std_logic; + SO_EN : out std_logic; + + -- DMA control: + RRn : out std_logic; + TRn : out std_logic + ); + end component WF68901IP_TOP_SOC; + + component WF2149IP_TOP_SOC -- Sound. + port( + + SYS_CLK : in std_logic; -- Read the inforation in the header! + RESETn : in std_logic; + + WAV_CLK : in std_logic; -- Read the inforation in the header! + SELn : in std_logic; + + BDIR : in std_logic; + BC2, BC1 : in std_logic; + + A9n, A8 : in std_logic; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out std_logic; + + IO_A_IN : in std_logic_vector(7 downto 0); + IO_A_OUT : out std_logic_vector(7 downto 0); + IO_A_EN : out std_logic; + IO_B_IN : in std_logic_vector(7 downto 0); + IO_B_OUT : out std_logic_vector(7 downto 0); + IO_B_EN : out std_logic; + + OUT_A : out std_logic; -- Analog (PWM) outputs. + OUT_B : out std_logic; + OUT_C : out std_logic + ); + end component WF2149IP_TOP_SOC; + + component WF6850IP_TOP_SOC -- ACIA. + port ( + CLK : in std_logic; + RESETn : in std_logic; + + CS2n, CS1, CS0 : in std_logic; + E : in std_logic; + RWn : in std_logic; + RS : in std_logic; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + + TXCLK : in std_logic; + RXCLK : in std_logic; + RXDATA : in std_logic; + CTSn : in std_logic; + DCDn : in std_logic; + + IRQn : out std_logic; + TXDATA : out std_logic; + RTSn : out std_logic + ); + end component WF6850IP_TOP_SOC; + + component WF_SD_CARD + port ( + RESETn : in std_logic; + CLK : in std_logic; + ACSI_A1 : in std_logic; + ACSI_CSn : in std_logic; + ACSI_ACKn : in std_logic; + ACSI_INTn : out std_logic; + ACSI_DRQn : out std_logic; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out std_logic; + MC_DO : in std_logic; + MC_PIO_DMAn : in std_logic; + MC_RWn : in std_logic; + MC_CLR_CMD : in std_logic; + MC_DONE : out std_logic; + MC_GOT_CMD : out std_logic; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out std_logic + ); + end component WF_SD_CARD; + + component dcfifo0 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + end component dcfifo0; + + component dcfifo1 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + end component; + + +end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd new file mode 100644 index 0000000..4453332 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd @@ -0,0 +1,631 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the 5380's system controller. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_CONTROL is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; -- System reset. + + -- System controls: + BSY_INn : in bit; -- SCSI BSY_INn bit. + BSY_OUTn : out bit; -- SCSI BSY_INn bit. + DATA_EN : out bit; -- Enable the SCSI data lines. + SEL_INn : in bit; -- SCSI SEL_INn bit. + ARB_EN : in bit; -- Arbitration enable. + BSY_DISn : in bit; -- BSY monitoring enable. + RSTn : in bit; -- SCSI reset. + + ARB : out bit; -- Arbitration flag. + AIP : out bit; -- Arbitration in progress flag. + LA : out bit; -- Lost arbitration flag. + + ACK_INn : in bit; + ACK_OUTn : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + + DACKn : in bit; -- Data acknowledge. + READY : out bit; + DRQ : out bit; -- Data request. + + TARG : in bit; -- Target mode indicator. + BLK : in bit; -- Block mode indicator. + PINT_EN : in bit; -- Parity interrupt enable. + SPER : in bit; -- Parity error. + SER_ID : in bit; -- SER matches ODR bits. + RPI : in bit; -- Reset interrupts. + DMA_EN : in bit; -- DMA mode enable. + SDS : in bit; -- Start DMA send, write only. + SDT : in bit; -- Start DMA target receive, write only. + SDI : in bit; -- Start DMA initiator receive, write only. + EOP_EN : in bit; -- EOP interrupt enable. + EOPn : in bit; -- End of process indicator. + PHSM : in bit; -- Phase match flag. + + INT : out bit; -- Interrupt. + IDR_WR : out bit; -- Write input data register during DMA. + ODR_WR : out bit; -- Write output data register, during DMA. + CHK_PAR : out bit; -- Check Parity during DMA operation. + BSY_ERR : out bit; -- Busy monitoring error. + DMA_SND : out bit; -- Indicates direction of target DMA. + DMA_ACTIVE : out bit -- DMA is active. + ); +end entity WF5380_CONTROL; + +architecture BEHAVIOUR of WF5380_CONTROL is +type CTRL_STATES is (IDLE, WAIT_800ns, WAIT_2200ns, DMA_SEND, DMA_TARG_RCV, DMA_INIT_RCV); +type DMA_STATES is (IDLE, DMA_STEP_1, DMA_STEP_2, DMA_STEP_3, DMA_STEP_4); +signal CTRL_STATE : CTRL_STATES; +signal NEXT_CTRL_STATE : CTRL_STATES; +signal DMA_STATE : DMA_STATES; +signal NEXT_DMA_STATE : DMA_STATES; +signal BUS_FREE : bit; +signal DELAY_800ns : boolean; +signal DELAY_2200ns : boolean; +signal DMA_ACTIVE_I : bit; +signal EOP_In : bit; +begin + IN_BUFFER: process + -- This buffer shall prevent some signals against + -- setup hold effects and thus the state machine + -- against unpredictable behaviour. + begin + wait until CLK = '1' and CLK' event; + EOP_In <= EOPn; + end process IN_BUFFER; + + STATE_REGISTERS: process(RESETn, CLK) + -- This is the controller's state machine register. + variable BSY_LOCK : boolean; + begin + if RESETn = '0' then + CTRL_STATE <= IDLE; + DMA_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if RSTn = '0' then -- SCSI reset. + CTRL_STATE <= IDLE; + DMA_STATE <= IDLE; + else + CTRL_STATE <= NEXT_CTRL_STATE; + DMA_STATE <= NEXT_DMA_STATE; + end if; + -- + if DMA_EN = '0' then + DMA_STATE <= IDLE; + end if; + end if; + end process STATE_REGISTERS; + + CTRL_DECODER: process(CTRL_STATE, ARB_EN, BUS_FREE, DELAY_800ns, SEL_INn, DMA_ACTIVE_I, SDS, SDT, SDI) + -- This is the controller's state machine decoder. + variable BSY_LOCK : boolean; + begin + -- Defaults. + DMA_SND <= '0'; + -- + case CTRL_STATE is + when IDLE => + if ARB_EN = '1' and BUS_FREE = '1' then + NEXT_CTRL_STATE <= WAIT_800ns; + else + NEXT_CTRL_STATE <= IDLE; + end if; + when WAIT_800ns => + if DELAY_800ns = true then + NEXT_CTRL_STATE <= WAIT_2200ns; + else + NEXT_CTRL_STATE <= WAIT_800ns; + end if; + when WAIT_2200ns => + -- In this state the delay is provided by the + -- microprocessor and is at least 2.2us. The + -- delay is released by deasserting SELn. + if SEL_INn = '1' and SDS = '1' then + NEXT_CTRL_STATE <= DMA_SEND; + elsif SEL_INn = '1' and SDT = '1' then + NEXT_CTRL_STATE <= DMA_TARG_RCV; + elsif SEL_INn = '1' and SDI = '1' then + NEXT_CTRL_STATE <= DMA_INIT_RCV; + else + NEXT_CTRL_STATE <= WAIT_2200ns; + end if; + when DMA_SEND => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_SEND; + end if; + -- + DMA_SND <= '1'; + when DMA_TARG_RCV => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_TARG_RCV; + end if; + when DMA_INIT_RCV => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_INIT_RCV; + end if; + end case; + end process CTRL_DECODER; + + DMA_DECODER: process(CTRL_STATE, DMA_STATE, TARG, BLK, DACKn, REQ_INn, ACK_INn) + -- This is the DMA state machine decoder. + begin + -- Defaults: + IDR_WR <= '0'; + ODR_WR <= '0'; + CHK_PAR <= '0'; + -- + case DMA_STATE is + when IDLE => + if CTRL_STATE = DMA_SEND then + NEXT_DMA_STATE <= DMA_STEP_1; + elsif CTRL_STATE = DMA_INIT_RCV then + NEXT_DMA_STATE <= DMA_STEP_1; + elsif CTRL_STATE = DMA_TARG_RCV then + NEXT_DMA_STATE <= DMA_STEP_1; + else + NEXT_DMA_STATE <= IDLE; + end if; + when DMA_STEP_1 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted. + IDR_WR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted. + IDR_WR <= '1'; + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted. + IDR_WR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted. + IDR_WR <= '1'; + else + NEXT_DMA_STATE <= DMA_STEP_1; + end if; + when DMA_STEP_2 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted. + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted. + else + NEXT_DMA_STATE <= DMA_STEP_2; + end if; + when DMA_STEP_3 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted. + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + else + NEXT_DMA_STATE <= DMA_STEP_3; + end if; + when DMA_STEP_4 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + else + NEXT_DMA_STATE <= DMA_STEP_4; + end if; + end case; + end process DMA_DECODER; + + P_REQn: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the REQn output in target mode. + begin + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + REQ_OUTn <= '0'; + else + REQ_OUTn <= '1'; + end if; + end process P_REQn; + + P_ACKn: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the ACKn output in initiator mode. + begin + if DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then + ACK_OUTn <= '0'; + else + ACK_OUTn <= '1'; + end if; + end process P_ACKn; + + P_READY: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the READY output in initiator and target block mode. + begin + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + READY <= '1'; + else + READY <= '0'; + end if; + end process P_READY; + + P_DRQ: process(RESETn, CLK) + -- This flip flop controls the DRQ flag during all initiator and all target modes + -- for both block mode and non block mode operation. + variable LOCK : boolean; + begin + if RESETn = '0' then + DRQ <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- Initiator modes: + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and LOCK = false then + DRQ <= '1'; + LOCK := true; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + DRQ <= '1'; + LOCK := true; + -- Target modes: + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + DRQ <= '1'; + LOCK := true; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + DRQ <= '1'; + LOCK := true; + elsif DACKn = '0' and LOCK = false then + DRQ <= '0'; + elsif EOPn = '0' and DACKn = '0' then + DRQ <= '0'; + LOCK := false; + end if; + end if; + end process P_DRQ; + + P_BUSFREE: process(RESETn, CLK) + -- This is the logic for the bus free signal. + -- A bus free is valid if the BSY_INn signal is + -- at least 437.5ns inactive ans SEL_INn is inactive. + -- The delay are 7 clock cycles of 16MHz. + variable TMP : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + BUS_FREE <= '0'; + TMP := "000"; + elsif CLK = '1' and CLK' event then + if BSY_INn = '1' and TMP < x"111" then + TMP := TMP + '1'; + elsif BSY_INn = '0' then + TMP := "000"; + end if; + -- + if RSTn = '0' then -- SCSI reset. + BUS_FREE <= '0'; + elsif SEL_INn = '1' and TMP = "111" then + BUS_FREE <= '1'; + else + BUS_FREE <= '0'; + end if; + end if; + end process P_BUSFREE; + + DELAY_800: process(RESETn, CLK) + -- This is the delay of 812.5ns. + -- It is derived from 13 16MHz clock cycles. + variable TMP : std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + DELAY_800ns <= false; + TMP := x"0"; + elsif CLK = '1' and CLK' event then + if CTRL_STATE /= WAIT_800ns then + TMP := x"0"; + elsif TMP <= x"D" then + TMP := TMP + '1'; + end if; + -- + if TMP = x"D" then + DELAY_800ns <= true; + else + DELAY_800ns <= false; + end if; + end if; + end process DELAY_800; + + P_ARB: process(RESETn, CLK) + -- This flip flop controls the ARB flag read back + -- by the microcontroller. + begin + if RESETn = '0' then + ARB <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE /= WAIT_800ns and NEXT_CTRL_STATE = WAIT_800ns then + ARB <= '1'; + elsif ARB_EN = '0' then + ARB <= '0'; + end if; + end if; + end process P_ARB; + + P_AIP: process(RESETn, CLK) + -- This flip flop controls the AIP flag read back + -- by the microcontroller. + begin + if RESETn = '0' then + AIP <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + AIP <= '1'; + elsif ARB_EN = '0' then + AIP <= '0'; + end if; + end if; + end process P_AIP; + + P_BSY: process + -- This flip flop controls the BSYn output + -- to the SCSI bus. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + BSY_OUTn <= '1'; + elsif CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + BSY_OUTn <= '0'; + elsif ARB_EN = '0' then + BSY_OUTn <= '1'; + end if; + end process P_BSY; + + P_DATA_EN: process(RESETn, CLK) + -- This flip flop controls the data enable + -- of the SCSI bus. + begin + if RESETn = '0' then + DATA_EN <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + DATA_EN <= '1'; + elsif ARB_EN = '0' then + DATA_EN <= '0'; + end if; + end if; + end process P_DATA_EN; + + P_LA: process(RESETn, CLK) + -- This flip flop controls the LA + -- (lost arbitration) flag. + begin + if RESETn = '0' then + LA <= '0'; + elsif CLK = '1' and CLK' event then + if (CTRL_STATE = WAIT_800ns or CTRL_STATE = WAIT_2200ns) and SEL_INn = '0' then + LA <= '1'; + elsif ARB_EN = '0' then + LA <= '0'; + end if; + end if; + end process P_LA; + + P_DMA_ACTIVE: process(RESETn, CLK, DMA_ACTIVE_I) + -- This is the Flip Flop indicating if there is DMA + -- operation. + begin + if RESETn = '0' then + DMA_ACTIVE_I <= '0'; + elsif CLK = '1' and CLK' event then + if DMA_EN = '1' and SDS = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA send. + elsif DMA_EN = '1' and SDT = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA target receive. + elsif DMA_EN = '1' and SDI = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA initiator receive. + elsif DMA_EN = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via DMA flag in MR2. + elsif EOP_In = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via EOPn. + elsif PHSM = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via phase mismatch. + end if; + end if; + -- + DMA_ACTIVE <= DMA_ACTIVE_I; + end process P_DMA_ACTIVE; + + INTERRUPTS: process(RESETn, CLK) + -- This is the logic for all DP5380's interrupt sources. + -- A busy interrupt occurs if the BSY_INn signal is at + -- least 437.5ns inactive. The delay are 7 clock cycles + -- of 16MHz. This logic also provides the respective + -- error flags for the BSR. + variable TMP : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + INT <= '0'; + BSY_ERR <= '0'; + TMP := "000"; + elsif CLK = '1' and CLK' event then + if SPER = '1' and PINT_EN = '1' then + INT <= '1'; -- Parity interrupt. + elsif RPI = '0' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if EOP_In = '0' and CTRL_STATE = DMA_SEND then + BSY_ERR <= '1'; -- End of DMA error. + elsif EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then + BSY_ERR <= '1'; -- End of DMA error. + elsif EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then + BSY_ERR <= '1'; -- End of DMA error. + elsif DMA_EN = '0' then -- Reset error. + INT <= '0'; + end if; + -- + if EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_SEND then + INT <= '1'; -- End of DMA interrupt. + elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then + INT <= '1'; -- End of DMA interrupt. + elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then + INT <= '1'; -- End of DMA interrupt. + elsif DMA_EN = '0' then -- Reset interrupt. + INT <= '0'; + end if; + + -- + if PHSM = '0' then + INT <= '1'; -- Phase mismatch interrupt. + elsif DMA_EN = '0' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if SEL_INn = '0' and BSY_INn = '1' and SER_ID = '1' then + INT <= '1'; -- (Re)Selection interrupt. + elsif RPI = '1' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if BSY_INn = '1' and TMP < x"111" then + TMP := TMP + '1'; -- Bus settle delay. + elsif BSY_INn = '0' then + TMP := "000"; + end if; + -- + if BSY_DISn = '1' and BSY_INn = '1' and TMP = x"111" then + INT <= '1'; -- Busy monitoring interrupt. + BSY_ERR <= '1'; + elsif RPI = '1' then -- Reset interrupts. + INT <= '0'; + BSY_ERR <= '0'; + end if; + -- + end if; + end process INTERRUPTS; +end BEHAVIOUR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd new file mode 100644 index 0000000..57cf305 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd @@ -0,0 +1,139 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the package file of the ip core. ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. + +library ieee; +use ieee.std_logic_1164.all; + +package WF5380_PKG is + component WF5380_REGISTERS + port ( + CLK : in bit; + RESETn : in bit; + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + CSn : in bit; + RDn : in bit; + WRn : in bit; + RSTn : in bit; + RST : out bit; + ARB_EN : out bit; + DMA_ACTIVE : in bit; + DMA_EN : out bit; + BSY_DISn : out bit; + EOP_EN : out bit; + PINT_EN : out bit; + SPER : out bit; + TARG : out bit; + BLK : out bit; + DMA_DIS : in bit; + IDR_WR : in bit; + ODR_WR : in bit; + CHK_PAR : in bit; + AIP : in bit; + ARB : in bit; + LA : in bit; + CSD : in bit_vector(7 downto 0); + CSB : in bit_vector(7 downto 0); + BSR : in bit_vector(7 downto 0); + ODR_OUT : out bit_vector(7 downto 0); + ICR_OUT : out bit_vector(7 downto 0); + TCR_OUT : out bit_vector(3 downto 0); + SER_OUT : out bit_vector(7 downto 0); + SDS : out bit; + SDT : out bit; + SDI : out bit; + RPI : out bit + ); + end component; + + component WF5380_CONTROL + port ( + CLK : in bit; + RESETn : in bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + DATA_EN : out bit; + SEL_INn : in bit; + ARB_EN : in bit; + BSY_DISn : in bit; + RSTn : in bit; + ARB : out bit; + AIP : out bit; + LA : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + DACKn : in bit; + READY : out bit; + DRQ : out bit; + TARG : in bit; + BLK : in bit; + PINT_EN : in bit; + SPER : in bit; + SER_ID : in bit; + RPI : in bit; + DMA_EN : in bit; + SDS : in bit; + SDT : in bit; + SDI : in bit; + EOP_EN : in bit; + EOPn : in bit; + PHSM : in bit; + INT : out bit; + IDR_WR : out bit; + ODR_WR : out bit; + CHK_PAR : out bit; + BSY_ERR : out bit; + DMA_SND : out bit; + DMA_ACTIVE : out bit + ); + end component; +end WF5380_PKG; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd new file mode 100644 index 0000000..2c21c12 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd @@ -0,0 +1,265 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the 5380's register model. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Register description (for more information see the DP5380 ---- +---- data sheet: ---- +---- ODR (address 0) Output data register, write only. ---- +---- CSD (address 0) Current SCSI data, read only. ---- +---- ICR (address 1) Initiator command register, read/write. ---- +---- MR2 (address 2) Mode register 2, read/write. ---- +---- TCR (address 3) Target command register, read/write. ---- +---- SER (address 4) Select enable register, write only. ---- +---- CSB (address 4) Current SCSI bus status, read only. ---- +---- BSR (address 5) Start DMA send, write only. ---- +---- SDS (address 5) Bus and status, read only. ---- +---- SDT (address 6) Start DMA target receive, write only. ---- +---- IDR (address 6) Input data register, read only. ---- +---- SDI (address 7) Start DMA initiator recive, write only. ---- +---- RPI (address 7) Reset parity / interrupts, read only. ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_REGISTERS is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; -- System reset. + + -- Address and data: + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + + -- Core controls: + RSTn : in bit; -- SCSI reset. + RST : out bit; -- Programmed SCSI reset. + ARB_EN : out bit; -- Arbitration enable. + DMA_ACTIVE : in bit; -- DMA is running. + DMA_EN : out bit; -- DMA mode enable. + BSY_DISn : out bit; -- BSY monitoring enable. + EOP_EN : out bit; -- EOP interrupt enable. + PINT_EN : out bit; -- Parity interrupt enable. + SPER : out bit; -- Parity error. + TARG : out bit; -- Target mode. + BLK : out bit; -- Block DMA mode. + DMA_DIS : in bit; -- Reset the DMA_EN by this signal. + IDR_WR : in bit; -- Write input data register during DMA. + ODR_WR : in bit; -- Write output data register, during DMA. + CHK_PAR : in bit; -- Check Parity during DMA operation. + AIP : in bit; -- Arbitration in progress. + ARB : in bit; -- Arbitration. + LA : in bit; -- Lost arbitration. + + CSD : in bit_vector(7 downto 0); -- SCSI data. + CSB : in bit_vector(7 downto 0); -- Current SCSI bus status. + BSR : in bit_vector(7 downto 0); -- Bus and status. + + ODR_OUT : out bit_vector(7 downto 0); -- This is the ODR register. + ICR_OUT : out bit_vector(7 downto 0); -- This is the ICR register. + TCR_OUT : out bit_vector(3 downto 0); -- This is the TCR register. + SER_OUT : out bit_vector(7 downto 0); -- This is the SER register. + + SDS : out bit; -- Start DMA send, write only. + SDT : out bit; -- Start DMA target receive, write only. + SDI : out bit; -- Start DMA initiator receive, write only. + RPI : out bit + ); +end entity WF5380_REGISTERS; + +architecture BEHAVIOUR of WF5380_REGISTERS is +signal ICR : bit_vector(7 downto 0); -- Initiator command register, read/write. +signal IDR : bit_vector(7 downto 0); -- Input data register. +signal MR2 : bit_vector(7 downto 0); -- Mode register 2, read/write. +signal ODR : bit_vector(7 downto 0); -- Output data register, write only. +signal SER : bit_vector(7 downto 0); -- Select enable register, write only. +signal TCR : bit_vector(3 downto 0); -- Target command register, read/write. +begin + REGISTERS: process(RESETn, CLK) + -- This process reflects all registers in the 5380. + variable BSY_LOCK : boolean; + begin + if RESETn = '0' then + ODR <= (others => '0'); + ICR <= (others => '0'); + MR2 <= (others => '0'); + TCR <= (others => '0'); + SER <= (others => '0'); + BSY_LOCK := false; + elsif CLK = '1' and CLK' event then + if RSTn = '0' then -- SCSI reset. + ODR <= (others => '0'); + ICR(6 downto 0) <= (others => '0'); + MR2(7) <= '0'; + MR2(5 downto 0) <= (others => '0'); + TCR <= (others => '0'); + SER <= (others => '0'); + BSY_LOCK := false; + elsif ADR = "000" and CSn = '0' and WRn = '0' then + ODR <= DATA_IN; + elsif ADR = "001" and CSn = '0' and WRn = '0' then + ICR <= DATA_IN; + elsif ADR = "010" and CSn = '0' and WRn = '0' then + MR2 <= DATA_IN; + elsif ADR = "011" and CSn = '0' and WRn = '0' then + TCR <= DATA_IN(3 downto 0); + elsif ADR = "100" and CSn = '0' and WRn = '0' then + SER <= DATA_IN; + end if; + -- + if ODR_WR = '1' then + ODR <= DATA_IN; + end if; + -- + -- This reset function is edge triggered on the 'Monitor Busy' + -- MR2(2). + if MR2(2) = '1' and BSY_LOCK = false then + ICR(5 downto 0) <= "000000"; + BSY_LOCK := true; + elsif MR2(2) = '0' then + BSY_LOCK := false; + end if; + -- + if DMA_DIS = '1' then + MR2(1) <= '0'; + end if; + end if; + end process REGISTERS; + + IDR_REGISTER: process(RESETn, CLK) + begin + if RESETn = '0' then + IDR <= x"00"; + elsif CLK = '1' and CLK' event then + if RSTn = '0' or ICR(7) = '1' then + IDR <= x"00"; -- SCSI reset. + elsif IDR_WR = '1' then + IDR <= CSD; + end if; + end if; + end process IDR_REGISTER; + + PARITY: process(RESETn, CLK) + -- This is the parity generating logic with it's related + -- error generation. + variable PAR_VAR : bit; + variable LOCK : boolean; + begin + if RESETn = '0' then + SPER <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- Parity checked during 'Read from CSD' + -- (registered I/O and selection/reselection): + if ADR = "000" and CSn = '0' and RDn = '0' and LOCK = false then + for i in 1 to 7 loop + PAR_VAR := CSD(i) xor CSD(i-1); + end loop; + SPER <= not PAR_VAR; + LOCK := true; + end if; + -- + -- Parity checking during DMA operation: + if DMA_ACTIVE = '1' and CHK_PAR = '1' then + for i in 1 to 7 loop + PAR_VAR := IDR(i) xor IDR(i-1); + end loop; + SPER <= not PAR_VAR; + LOCK := true; + end if; + -- + -- Reset parity flag: + if MR2(5) <= '0' then -- MR2(5) = PCHK (disabled). + SPER <= '0'; + elsif ADR = "111" and CSn = '0' and RDn = '0' then -- Reset parity/interrupts. + SPER <= '0'; + LOCK := false; + end if; + end if; + end process PARITY; + + DATA_EN <= '1' when ADR < "101" and CSn = '0' and WRn = '0' else '0'; + + SDS <= '1' when ADR = "101" and CSn = '0' and WRn = '0' else '0'; + SDT <= '1' when ADR = "110" and CSn = '0' and WRn = '0' else '0'; + SDI <= '1' when ADR = "111" and CSn = '0' and WRn = '0' else '0'; + + ICR_OUT <= ICR; + TCR_OUT <= TCR; + SER_OUT <= SER; + ODR_OUT <= ODR; + + ARB_EN <= MR2(0); + DMA_EN <= MR2(1); + BSY_DISn <= MR2(2); + EOP_EN <= MR2(3); + PINT_EN <= MR2(4); + TARG <= MR2(6); + BLK <= MR2(7); + + RST <= ICR(7); + + -- Readback, unused bit positions are read back zero. + DATA_OUT <= CSD when ADR = "000" and CSn = '0' and RDn = '0' else -- Current SCSI data. + ICR(7) & AIP & LA & ICR(4 downto 0) when ADR = "001" and CSn = '0' and RDn = '0' else + MR2 when ADR = "010" and CSn = '0' and RDn = '0' else + x"0" & TCR when ADR = "011" and CSn = '0' and RDn = '0' else + CSB when ADR = "100" and CSn = '0' and RDn = '0' else -- Current SCSI bus status. + BSR when ADR = "101" and CSn = '0' and RDn = '0' else -- Bus and status. + IDR when ADR = "110" and CSn = '0' and RDn = '0' else x"00"; -- Input data register. + + RPI <= '1' when ADR = "111" and CSn = '0' and RDn = '0' else '0'; -- Reset parity/interrupts. +end BEHAVIOUR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd new file mode 100644 index 0000000..abc0400 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd @@ -0,0 +1,300 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- Some remarks to the required input clock: ---- +---- This core is provided for a 16MHz input clock. To use other ---- +---- frequencies, it is necessary to modify the following proces- ---- +---- ses in the control file section: ---- +---- P_BUSFREE, DELAY_800, INTERRUPTS. ---- +---- ---- +---- This file is the top level file without tree state buses for ---- +---- use in 'systems on chip' designs. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library work; +use work.wf5380_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_TOP_SOC is + port ( + -- System controls: + CLK : in bit; -- Use a 16MHz Clock. + RESETn : in bit; + + -- Address and data: + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + + -- SCSI bus: + DB_INn : in bit_vector(7 downto 0); + DB_OUTn : out bit_vector(7 downto 0); + DB_EN : out bit; + DBP_INn : in bit; + DBP_OUTn : out bit; + DBP_EN : out bit; + RST_INn : in bit; + RST_OUTn : out bit; + RST_EN : out bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + BSY_EN : out bit; + SEL_INn : in bit; + SEL_OUTn : out bit; + SEL_EN : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + ACK_EN : out bit; + ATN_INn : in bit; + ATN_OUTn : out bit; + ATN_EN : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + REQ_EN : out bit; + IOn_IN : in bit; + IOn_OUT : out bit; + IO_EN : out bit; + CDn_IN : in bit; + CDn_OUT : out bit; + CD_EN : out bit; + MSG_INn : in bit; + MSG_OUTn : out bit; + MSG_EN : out bit + ); +end entity WF5380_TOP_SOC; + +architecture STRUCTURE of WF5380_TOP_SOC is +signal ACK_OUT_CTRLn : bit; +signal AIP : bit; +signal ARB : bit; +signal ARB_EN : bit; +signal BLK : bit; +signal BSR : bit_vector(7 downto 0); +signal BSY_DISn : bit; +signal BSY_ERR : bit; +signal BSY_OUT_CTRLn : bit; +signal CHK_PAR : bit; +signal CSD : bit_vector(7 downto 0); +signal CSB : bit_vector(7 downto 0); +signal DATA_EN_CTRL : bit; +signal DB_EN_I : bit; +signal DMA_ACTIVE : bit; +signal DMA_EN : bit; +signal DMA_DIS : bit; +signal DMA_SND : bit; +signal DRQ_I : bit; +signal EDMA : bit; +signal EOP_EN : bit; +signal ICR : bit_vector(7 downto 0); +signal IDR_WR : bit; +signal INT_I : bit; +signal LA : bit; +signal ODR : bit_vector(7 downto 0); +signal ODR_WR : bit; +signal PCHK : bit; +signal PHSM : bit; +signal PINT_EN : bit; +signal REQ_OUT_CTRLn : bit; +signal RPI : bit; +signal RST : bit; +signal SDI : bit; +signal SDS : bit; +signal SDT : bit; +signal SER : bit_vector(7 downto 0); +signal SER_ID : bit; +signal SPER : bit; +signal TARG : bit; +signal TCR : bit_vector(3 downto 0); +begin + EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else + '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0'; + + PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA. + '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch. + + DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0'; + + SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0'; + + DRQ <= DRQ_I; + INT <= INT_I; + + -- Pay attention: the SCSI bus is driven with inverted signals. + ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode. + REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3); -- Valid in Target mode. + BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode. + '0' when ICR(3) = '1' else '1'; + ATN_OUTn <= not ICR(1); -- Valid in initiator mode. + SEL_OUTn <= not ICR(2); -- Valid in initiator mode. + IOn_OUT <= not TCR(0); -- Valid in Target mode. + CDn_OUT <= not TCR(1); -- Valid in Target mode. + MSG_OUTn <= not TCR(2); -- Valid in Target mode. + RST_OUTn <= not RST; + + DB_OUTn <= not ODR; + DBP_OUTn <= not SPER; + + CSD <= not DB_INn; + CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn; + BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn; + + -- Hi impedance control: + ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + IO_EN <= '1' when TARG = '1' else '0'; -- Target mode. + CD_EN <= '1' when TARG = '1' else '0'; -- Target mode. + MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode. + REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode. + RST_EN <= '1' when RST = '1' else '0'; -- Open drain control. + + -- Data enables: + DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arbitration. + '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode. + '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else + '1' when ICR(6) = '1' else '0'; -- Test mode enable. + + DB_EN <= DB_EN_I; + DBP_EN <= DB_EN_I; + + I_REGISTERS: WF5380_REGISTERS + port map( + CLK => CLK, + RESETn => RESETn, + ADR => ADR, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + CSn => CSn, + RDn => RDn, + WRn => WRn, + RSTn => RST_INn, + RST => RST, + ARB_EN => ARB_EN, + DMA_ACTIVE => DMA_ACTIVE, + DMA_EN => DMA_EN, + BSY_DISn => BSY_DISn, + EOP_EN => EOP_EN, + PINT_EN => PINT_EN, + SPER => SPER, + TARG => TARG, + BLK => BLK, + DMA_DIS => DMA_DIS, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + AIP => AIP, + ARB => ARB, + LA => LA, + CSD => CSD, + CSB => CSB, + BSR => BSR, + ODR_OUT => ODR, + ICR_OUT => ICR, + TCR_OUT => TCR, + SER_OUT => SER, + SDS => SDS, + SDT => SDT, + SDI => SDI, + RPI => RPI + ); + + I_CONTROL: WF5380_CONTROL + port map( + CLK => CLK, + RESETn => RESETn, + BSY_INn => BSY_INn, + BSY_OUTn => BSY_OUT_CTRLn, + DATA_EN => DATA_EN_CTRL, + SEL_INn => SEL_INn, + ARB_EN => ARB_EN, + BSY_DISn => BSY_DISn, + RSTn => RST_INn, + ARB => ARB, + AIP => AIP, + LA => LA, + ACK_INn => ACK_INn, + ACK_OUTn => ACK_OUT_CTRLn, + REQ_INn => REQ_INn, + REQ_OUTn => REQ_OUT_CTRLn, + DACKn => DACKn, + READY => READY, + DRQ => DRQ_I, + TARG => TARG, + BLK => BLK, + PINT_EN => PINT_EN, + SPER => SPER, + SER_ID => SER_ID, + RPI => RPI, + DMA_EN => DMA_EN, + SDS => SDS, + SDT => SDT, + SDI => SDI, + EOP_EN => EOP_EN, + EOPn => EOPn, + PHSM => PHSM, + INT => INT_I, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + BSY_ERR => BSY_ERR, + DMA_SND => DMA_SND, + DMA_ACTIVE => DMA_ACTIVE + ); +end STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd new file mode 100644 index 0000000..bfb31fb --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd @@ -0,0 +1,275 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the top level file with tree state buses. ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library work; +use work.wf5380_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_TOP is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; + + -- Address and data: + ADR : in std_logic_vector(2 downto 0); + DATA : inout std_logic_vector(7 downto 0); + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + + -- SCSI bus: + DBn : inout std_logic_vector(7 downto 0); + DBPn : inout std_logic; + RSTn : inout std_logic; + BSYn : inout std_logic; + SELn : inout std_logic; + ACKn : inout std_logic; + ATNn : inout std_logic; + REQn : inout std_logic; + IOn : inout std_logic; + CDn : inout std_logic; + MSGn : inout std_logic + ); +end entity WF5380_TOP; + +architecture STRUCTURE of WF5380_TOP is +component WF5380_TOP_SOC + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + DB_INn : in bit_vector(7 downto 0); + DB_OUTn : out bit_vector(7 downto 0); + DB_EN : out bit; + DBP_INn : in bit; + DBP_OUTn : out bit; + DBP_EN : out bit; + RST_INn : in bit; + RST_OUTn : out bit; + RST_EN : out bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + BSY_EN : out bit; + SEL_INn : in bit; + SEL_OUTn : out bit; + SEL_EN : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + ACK_EN : out bit; + ATN_INn : in bit; + ATN_OUTn : out bit; + ATN_EN : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + REQ_EN : out bit; + IOn_IN : in bit; + IOn_OUT : out bit; + IO_EN : out bit; + CDn_IN : in bit; + CDn_OUT : out bit; + CD_EN : out bit; + MSG_INn : in bit; + MSG_OUTn : out bit; + MSG_EN : out bit + ); +end component; +-- +signal ADR_IN : bit_vector(2 downto 0); +signal DATA_IN : bit_vector(7 downto 0); +signal DATA_OUT : bit_vector(7 downto 0); +signal DATA_EN : bit; +signal DB_INn : bit_vector(7 downto 0); +signal DB_OUTn : bit_vector(7 downto 0); +signal DB_EN : bit; +signal DBP_INn : bit; +signal DBP_OUTn : bit; +signal DBP_EN : bit; +signal RST_INn : bit; +signal RST_OUTn : bit; +signal RST_EN : bit; +signal BSY_INn : bit; +signal BSY_OUTn : bit; +signal BSY_EN : bit; +signal SEL_INn : bit; +signal SEL_OUTn : bit; +signal SEL_EN : bit; +signal ACK_INn : bit; +signal ACK_OUTn : bit; +signal ACK_EN : bit; +signal ATN_INn : bit; +signal ATN_OUTn : bit; +signal ATN_EN : bit; +signal REQ_INn : bit; +signal REQ_OUTn : bit; +signal REQ_EN : bit; +signal IOn_IN : bit; +signal IOn_OUT : bit; +signal IO_EN : bit; +signal CDn_IN : bit; +signal CDn_OUT : bit; +signal CD_EN : bit; +signal MSG_INn : bit; +signal MSG_OUTn : bit; +signal MSG_EN : bit; +begin + ADR_IN <= To_BitVector(ADR); + + DATA_IN <= To_BitVector(DATA); + DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z'); + + DB_INn <= To_BitVector(DBn); + DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z'); + + DBP_INn <= To_Bit(DBPn); + + RST_INn <= To_Bit(RSTn); + BSY_INn <= To_Bit(BSYn); + SEL_INn <= To_Bit(SELn); + ACK_INn <= To_Bit(ACKn); + ATN_INn <= To_Bit(ATNn); + REQ_INn <= To_Bit(REQn); + IOn_IN <= To_Bit(IOn); + CDn_IN <= To_Bit(CDn); + MSG_INn <= To_Bit(MSGn); + + DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else + '0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z'; + RSTn <= '1' when RST_OUTn = '1' and RST_EN = '1'else + '0' when RST_OUTn = '0' and RST_EN = '1' else 'Z'; + BSYn <= '1' when BSY_OUTn = '1' and BSY_EN = '1' else + '0' when BSY_OUTn = '0' and BSY_EN = '1' else 'Z'; + SELn <= '1' when SEL_OUTn = '1' and SEL_EN = '1' else + '0' when SEL_OUTn = '0' and SEL_EN = '1' else 'Z'; + ACKn <= '1' when ACK_OUTn = '1' and ACK_EN = '1' else + '0' when ACK_OUTn = '0' and ACK_EN = '1' else 'Z'; + ATNn <= '1' when ATN_OUTn = '1' and ATN_EN = '1' else + '0' when ATN_OUTn = '0' and ATN_EN = '1' else 'Z'; + REQn <= '1' when REQ_OUTn = '1' and REQ_EN = '1' else + '0' when REQ_OUTn = '0' and REQ_EN = '1' else 'Z'; + IOn <= '1' when IOn_OUT = '1' and IO_EN = '1' else + '0' when IOn_OUT = '0' and IO_EN = '1' else 'Z'; + CDn <= '1' when CDn_OUT = '1' and CD_EN = '1' else + '0' when CDn_OUT = '0' and CD_EN = '1' else 'Z'; + MSGn <= '1' when MSG_OUTn = '1' and MSG_EN = '1' else + '0' when MSG_OUTn = '0' and MSG_EN = '1' else 'Z'; + + I_5380: WF5380_TOP_SOC + port map( + CLK => CLK, + RESETn => RESETn, + ADR => ADR_IN, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + CSn => CSn, + RDn => RDn, + WRn => WRn, + EOPn => EOPn, + DACKn => DACKn, + DRQ => DRQ, + INT => INT, + READY => READY, + DB_INn => DB_INn, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => DBP_INn, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, + RST_INn => RST_INn, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => BSY_INn, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => SEL_INn, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => ACK_INn, + ACK_OUTn => ACK_OUTn, + ACK_EN => ACK_EN, + ATN_INn => ATN_INn, + ATN_OUTn => ATN_OUTn, + ATN_EN => ATN_EN, + REQ_INn => REQ_INn, + REQ_OUTn => REQ_OUTn, + REQ_EN => REQ_EN, + IOn_IN => IOn_IN, + IOn_OUT => IOn_OUT, + IO_EN => IO_EN, + CDn_IN => CDn_IN, + CDn_OUT => CDn_OUT, + CD_EN => CD_EN, + MSG_INn => MSG_INn, + MSG_OUTn => MSG_OUTn, + MSG_EN => MSG_EN + ); +end STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd new file mode 100644 index 0000000..10a86f9 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd @@ -0,0 +1,253 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- Address mark detector file. This part detects the address ---- +---- mark in the incoming data stream in FM and also in MFM mode ---- +---- and provides therewith synchronisation information for the ---- +---- control state machine and for the data separator in the ---- +---- transceiver unit. ---- +---- ---- +------------------------------- Some theory ------------------------------------- +---- Frequency modulation FM: ---- +---- The frequency modulation works as follows: ---- +---- 1. every first pulse of the clock and data line is a clock. ---- +---- 2. every second pulse is a data. ---- +---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ---- +---- 4. a logic 0 is represented by one clock pulse and no data pulse. ---- +---- 5. Hence there are a maximum of two pulses per data bit. ---- +---- 6. one clock and one data pulse come together in one bit cell. ---- +---- 7. the duration of a bit cell in FM is 4 microseconds. ---- +---- 8. an ID address mark is represented as data FE with clock C7. ---- +---- 9. a DATA address mark is represented as data FB with clock C7. ---- +---- Examples: ---- +---- Binary data 1 1 0 0 1 0 1 1 is represented in FM as follows: ---- +---- 1111101011101111 ---- +---- the FE data 1 1 1 1 1 1 1 0 is represented as follows: ---- +---- 1111111111111110 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101111110 this is the ID address mark. ---- +---- the FB data 1 1 1 1 1 0 1 1 is represented as follows: ---- +---- 1111111111101111 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101101111 this is the DATA address mark. ---- +---- the F8 data 1 1 1 1 1 0 0 0 is represented as follows: ---- +---- 1111111111101010 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101101010 this is the deleted DATA mark. ---- +---- ---- +---- ---- +---- Modified frequency modulation MFM: ---- +---- The modified frequency modulation works as follows: ---- +---- 1. every first pulse of the clock and data line is a clock. ---- +---- 2. every second pulse is a data. ---- +---- 3. a logic 1 is represented by no clock but a data pulse. ---- +---- 4. a logic 0 is represented by a clock pulse and no data pulse if ---- +---- following a 0. ---- +---- 5. a logic 0 is represented by no pulse if following a 1. ---- +---- 6. Hence there are a maximum of one pulse per data bit. ---- +---- 7. one clock and one data pulse form together one bit cell. ---- +---- 8. the duration of a bit cell in MFM is 2 microseconds. ---- +---- 9. an address mark sync is represented as data A1 with missing clock ---- +---- pulse between bit 4 and 5. ---- +---- Examples: ---- +---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows: ---- +---- 0101010101010100 this is the ID address mark. ---- +---- Binary data FB 1 1 1 1 1 0 1 1 is represented in MFM as follows: ---- +---- 0101010101000101 this is the DATA address mark. ---- +---- Binary data F8 1 1 1 1 1 0 0 0 is represented in MFM as follows: ---- +---- 0101010101001010 this is the deleted DATA address mark. ---- +---- the A1 data 1 0 1 0 0 0 0 1 is represented as follows: ---- +---- 0100010010101001 ---- +---- with the missing clock pulse between bits 4 and 5 there results: ---- +---- results: 0100010010001001 this is the address mark sync. ---- +---- ---- +---- Both MFM and FM are during read and write shifted with most significant ---- +---- bit (MSB) first. During the FM address marks are written without a ---- +---- SYNC pulse the MFM coded data requires a synchronisation (A1 with ---- +---- missing clock pulse because at the beginning of the data stream it is ---- +---- not defined wether a clock pulse or a data pulse appears first. In FM ---- +---- coding the first pulse is in any case a clock pulse. ---- +--------------------------------------------------------------------------------- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_AM_DETECTOR is + port( + -- System control + CLK : in bit; + RESETn : in bit; + + -- Controls: + DDEn : in bit; + + -- Serial data and clock: + DATA : in bit; + DATA_STRB : in bit; + + -- Address mark detector: + ID_AM : out bit; -- ID address mark strobe. + DATA_AM : out bit; -- Data address mark strobe. + DDATA_AM : out bit -- Deleted data address mark strobe. + ); +end WF1772IP_AM_DETECTOR; + +architecture BEHAVIOR of WF1772IP_AM_DETECTOR is +signal SHIFT : bit_vector(15 downto 0); +signal SYNC : boolean; +signal ID_AM_I : bit; +signal DATA_AM_I : bit; +signal DDATA_AM_I : bit; +begin + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT <= (others => '0'); + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + -- MSB first leads to a shift left operation. + SHIFT <= SHIFT(14 downto 0) & DATA; + elsif DDEn = '0' and SHIFT = "0100010010001001" then -- This is the synchronisation in MFM. + SHIFT <= (others => '0'); + end if; + end if; + end process SHIFTREG; + + MFM_SYNCLOCK: process(RESETn, CLK) + -- The SYNC pulse is generated in MFM mode only when the sync character + -- appears in the shift register (A1 sync mark, see file header). + -- After the sync character is detected, the sync time counter is loaded + -- with a value of 17. During counting the following 17 read clock pulses + -- down, the SYNC is true. After exactly 16 pulses the address mark is + -- detected if the pattern in the shift register fits one of the address + -- marks. The address mark pulses are valid for one read clock cycle until + -- SYNC goes low again. This mechanism is used to detect the correct address + -- marks in the MFM data stream during the type III read track command. + -- This is an improvement over the original WD1772 chip. + variable TMP : std_logic_vector(4 downto 0); + begin + if RESETn = '0' then + TMP := "00000"; + elsif CLK = '1' and CLK' event then + if SHIFT = "0100010010001001" and DDEn = '0' then + TMP := "10001"; -- Load sync time counter. + elsif DATA_STRB = '1' and TMP > "00000" then + TMP := TMP - '1'; + end if; + end if; + case TMP is + when "00000" => SYNC <= false; + when others => SYNC <= true; + end case; + end process MFM_SYNCLOCK; + + -- The addressmark is nominally valid for one data pulse cycle (1us, 2us, 4us). + -- The pulse is shorter due to the fact that the detected address marks change the + -- state of the control state machine and so clear the address mark shift register... + ID_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101111110" else + '1' when DDEn = '0' and SHIFT = "0101010101010100" and SYNC = true else '0'; + DATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101111" else + -- Normal data address mark... + '1' when DDEn = '0' and SHIFT = "0101010101000101" and SYNC = true else '0'; + DDATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101010" else + -- ... and deleted address mark in MFM mode: + '1' when DDEn = '0' and SHIFT = "0101010101001010" and SYNC = true else '0'; + + ADRMARK_STROBES: process(RESETn, CLK) + -- ... nevertheless The controller and the transceiver require ID address mark strobes + -- and DATA address mark strobes. Therefore this process provides these strobe + -- signals independant of any 'feedbacks' like pulse shortening by the controller + -- state machine itself. + variable ID_AM_LOCK, DATA_AM_LOCK, DDATA_AM_LOCK : boolean; + begin + if RESETn = '0' then + ID_AM_LOCK := false; + DATA_AM_LOCK := false; + ID_AM <= '0'; + DATA_AM <= '0'; + elsif CLK = '1' and CLK' event then + -- ID address mark: + if ID_AM_I = '1' and ID_AM_LOCK = false then + ID_AM <= '1'; + ID_AM_LOCK := true; + elsif ID_AM_I = '0' then + ID_AM <= '0'; + ID_AM_LOCK := false; + else + ID_AM <= '0'; + end if; + -- Data address mark: + if DATA_AM_I = '1' and DATA_AM_LOCK = false then + DATA_AM <= '1'; + DATA_AM_LOCK := true; + elsif DATA_AM_I = '0' then + DATA_AM <= '0'; + DATA_AM_LOCK := false; + else + DATA_AM <= '0'; + end if; + -- Deleted data address mark: + if DDATA_AM_I = '1' and DDATA_AM_LOCK = false then + DDATA_AM <= '1'; + DDATA_AM_LOCK := true; + elsif DDATA_AM_I = '0' then + DDATA_AM <= '0'; + DDATA_AM_LOCK := false; + else + DDATA_AM <= '0'; + end if; + end if; + end process ADRMARK_STROBES; +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd new file mode 100644 index 0000000..ce4c346 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd @@ -0,0 +1,1463 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is file the control unit providing all signals for the ---- +---- data processing units like registers, addressmark detector, ---- +---- data separator, CRC redundancy checker or transceiver. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma +-- Oksanen for the information. +-- Revision 2K8A 2008/02/26 WF +-- Fixed a bug in the 6ms delay. Thanks to Lyndon Amsdon. +-- Revision 2K8B 2008/12/24 WF +-- Bugfixes to avoid hanging state machine. +-- Changed DELAY_30MS to DELAY_15MS, which is the correct value. Thanks to L. Amsdon for the information. +-- Removed CRC_BUSY. +-- Fixed a bug in the Delay for the state T2_VERIFY_AM. +-- Revision 2K9A 2009/06/20 WF +-- Fix to provide correct LOST_DATA_TR00 flag during seek command. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_CONTROL is + port( + -- System control: + CLK : in bit; + RESETn : in bit; + + -- Chip control signals: + A1, A0 : in bit; + RWn : in bit; + CSn : in bit; + DDEn : in bit; + + -- Registers: + DR : in bit_vector(7 downto 0); -- Data register. + CMD : in std_logic_vector(7 downto 0); -- Command register. + DSR : in std_logic_vector(7 downto 0); -- Shift register. + TR : in std_logic_vector(7 downto 0); -- Track register. + SR : in std_logic_vector(7 downto 0); -- Sector register. + + -- Status flags: + MO : buffer bit; -- Motor on status flag. + WR_PR : out bit; -- Write protect status flag. + SPINUP_RECTYPE : out bit; -- Spin up / record type status flag. + SEEK_RNF : out bit; -- Seek error / record not found status flag. + CRC_ERRFLAG : out bit; -- CRC status flag. + LOST_DATA_TR00 : out bit; -- Status flag indicates lost data or track 00 position. + DRQ : out bit; -- Data request. + DRQ_IPn : out bit; -- Data request status flag. + BUSY : buffer bit; -- BUSY status flag. + + -- Address mark detector controls: + AM_2_DISK : out bit; -- Enables / disables the address mark detector. + ID_AM : in bit; -- Address mark of the ID field + DATA_AM : in bit; -- Address mark of the data field + DDATA_AM : in bit; -- Address mark of a deleted data field + + -- CRC unit controls: + CRC_ERR : in bit; -- CRC decoder's error. + CRC_PRES : out bit; -- Preset CRC during write operations. + + -- Track register controls: + TR_PRES : out bit; -- Set x"FF". + TR_CLR : out bit; -- Clear. + TR_INC : out bit; -- Increment. + TR_DEC : out bit; -- Decrement. + + -- Sector register control: + SR_LOAD : out bit; -- Load. + SR_INC : out bit; -- Increment. + -- The TRACK_NR is required during the type III command + -- 'Read Address'. TRACK_NR is the content of the TRACKMEM. + TRACK_NR : out std_logic_vector(7 downto 0); + + -- DATA register control: + DR_CLR : out bit; -- Clear. + DR_LOAD : out bit; -- LOAD. + + -- Shift register control: + SHFT_LOAD_ND : out bit; -- Load normal data. + SHFT_LOAD_SD : out bit; -- Load special data. + + -- Transceiver controls: + CRC_2_DISK : out bit; -- Cause the Transceiver to write out CRC data. + DSR_2_DISK : out bit; -- Cause the Transceiver to write normal data. + FF_2_DISK : out bit; -- Cause the Transceiver to write x"FF" bytes. + PRECOMP_EN : out bit; -- Enables the write precompensation. + + -- Miscellaneous Controls: + DATA_STRB : in bit; -- Data strobe (read and write operation) + WPRTn : in bit; -- Write protect flag + IPn : in bit; -- Index pulse flag + TRACK00n : in bit; -- Track zero flag + DISK_RWn : out bit; -- This signal reflects the data direction. + DIRC : out bit; -- Step direction control. + STEP : out bit; -- Step pulse. + WG : out bit; -- Write gate control. + INTRQ : out bit -- Interrupt request flag. + ); +end WF1772IP_CONTROL; + +architecture BEHAVIOR of WF1772IP_CONTROL is +-- The control state machine for the three command types I, II and III +-- (10 commands) has 73 states: +type CMD_STATES is( IDLE, INIT, SPINUP, DELAY_15MS, DECODE, T1_SEEK_RESTORE, T1_STEPPING, + T1_LOAD_SHFT, T1_COMP_TR_DSR, T1_CHECK_DIR, T1_HEAD_CTRL, T1_STEP, T1_TRAP, T1_STEP_DELAY, + T1_SPINDOWN, T1_SCAN_TRACK, T1_SCAN_CRC, T1_VERIFY_DELAY, T1_VERIFY_CRC, T2_RD_WR_SECT, + T2_INIT, T2_SCAN_TRACK, T2_SCAN_SECT, T2_SCAN_LEN, T2_VERIFY_CRC_1, T2_VERIFY_AM, T2_FIRSTBYTE, + T2_LOAD_DATA, T2_NEXTBYTE, T2_VERIFY_DRQ_1, T2_RDSTAT, T2_VERIFY_CRC_2, + T2_MULTISECT, T2_DELAY_B2, T2_SET_DRQ, T2_DELAY_B8, T2_VERIFY_DRQ_2, + T2_DELAY_B1, T2_CHECK_MODE, T2_DELAY_B11, T2_WR_LEADIN, T2_WR_AM, + T2_LOAD_SHFT, T2_WR_BYTE, T2_VERIFY_DRQ_3, T2_DATALOST, T2_WRSTAT, T2_WR_CRC, + T2_WR_FF, T3_WR, T3_DELAY_B3, T3_VERIFY_DRQ, T3_CHECK_INDEX_1, T3_LOAD_SHFT, + T3_WR_DATA, T3_CHECK_INDEX_2, T3_DATALOST, T3_RD_TRACK, T3_SHIFT, + T3_CHECK_INDEX_3, T3_DETECT_AM, T3_CHECK_BYTE, T3_CHECK_DR, T3_LOAD_DATA_1, + T3_SET_DRQ_1, T3_RD_ADR, T3_VERIFY_AM, T3_SHIFT_ADR, T3_LOAD_DATA_2, + T3_SET_DRQ_2, T3_CHECK_RD, T3_LOAD_SR, T3_VERIFY_CRC); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; +signal DATA_WR : boolean; +signal DATA_RD : boolean; +signal CMD_WR : boolean; +signal STAT_RD : boolean; +signal DELAY : boolean; +signal DRQ_I : bit; +signal INDEX_CNT : boolean; +signal DIR : bit; +signal INDEX_MARK : bit; +signal STEP_TRAP : boolean; +signal TYPE_IV_BREAK : boolean; +signal BYTE_RDY : boolean; +signal SECT_LEN : std_logic_vector(10 downto 0); +signal TRACKMEM : std_logic_vector(7 downto 0); +signal T3_TRADR : boolean; +signal T3_DATATYPE : bit_vector(7 downto 0); +begin + -- The Forced interrupt stops any command at the end of an internal micro instruction. + -- Forced interrupt waits until ALU operations in progress are complete (CRC calculations, + -- compares etc.). the TYPE_IV_BREAK controls this behavior. + TYPE_IV_BREAK <= true when CMD(7 downto 4) = x"D" and DELAY = true else false; + + CMD_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + CMD_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if TYPE_IV_BREAK = true then + CMD_STATE <= IDLE; -- Forced interrupt break. + else + CMD_STATE <= NEXT_CMD_STATE; -- Normal operation. + end if; + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, CMD, DSR, TR, SR, INDEX_CNT, IPn, INDEX_MARK, DELAY, DIR, MO, CMD_WR, DRQ_I, + DDEn, CRC_ERR, TRACK00n, STEP_TRAP, ID_AM, DATA_AM, DDATA_AM, WPRTn, SECT_LEN, BYTE_RDY, + T3_TRADR) + begin + case CMD_STATE is + -------------------------------------------------------------------- + ------------------ type1, -2, -3 command stuff --------------------- + -------------------------------------------------------------------- + when IDLE => + -- The write access to the command register indicates a new command. + -- Any command received (type1, -2 or -3 but not type4): + if CMD_WR = true and CMD /= x"FF" and CMD(7 downto 4) /= "1101" then + NEXT_CMD_STATE <= INIT; + else + NEXT_CMD_STATE <= IDLE; -- No CMD detected. + end if; + when INIT => + -- The process goes on when the CMD_WR flag is released. + if CMD_WR = false and CMD(3) = '0' and MO = '0' then + -- Do not enter the SPINUP sequence + -- when the motor is already on (MO = '1'). + NEXT_CMD_STATE <= SPINUP; + elsif CMD_WR = false then + -- Proceed with the DELAY_15MS when the motor was + -- already on or when the SPINUP sequence is + -- disabled (CMD(3) = '1'). + NEXT_CMD_STATE <= DELAY_15MS; + else + NEXT_CMD_STATE <= INIT; + end if; + when SPINUP => + if INDEX_CNT = true then -- proceed after 6 revolutions + NEXT_CMD_STATE <= DELAY_15MS; + else + NEXT_CMD_STATE <= SPINUP; + end if; + when DELAY_15MS => + if CMD(7) = '0' then -- No delay for type1 commands. + NEXT_CMD_STATE <= DECODE; + elsif CMD(7) = '1' and CMD(2) = '0' then -- Delay for type2 and -3 disabled. + NEXT_CMD_STATE <= DECODE; + elsif CMD(7) = '1' and CMD(2) = '1' and DELAY = true then -- Delay enabled by CMD(2). + NEXT_CMD_STATE <= DECODE; + else + NEXT_CMD_STATE <= DELAY_15MS; + end if; + when DECODE => + case CMD(7 downto 5) is + when "000" => -- 'restore', 'seek'. + NEXT_CMD_STATE <= T1_SEEK_RESTORE; + when "001" |"010" | "011" => -- 'step', 'step in', 'step out'. + NEXT_CMD_STATE <= T1_STEPPING; + when "100" | "101" => -- 'read sector', 'write sector' + NEXT_CMD_STATE <= T2_RD_WR_SECT; + when "110" => -- 'read address'. + -- "110" is also used by the 'force interrupt'. + -- There will result no wrong encoding because + -- the 'force intterrupt' is predecoded in IDLE. + NEXT_CMD_STATE <= T3_RD_ADR; + when "111" => -- 'read track', 'write track'. + case CMD(4) is + when '0' => NEXT_CMD_STATE <= T3_RD_TRACK; + when '1' => NEXT_CMD_STATE <= T3_WR; + when others => NEXT_CMD_STATE <= T3_WR; -- Dummy for U, X, Z, W, H, L, -. + end case; + when others => + -- The following NEXT_CMD_STATE is chosen to compile fine with + -- the Xilinx ISE not to produce a latch. + NEXT_CMD_STATE <= IDLE; -- Never true due to IDLE preselection. + end case; + -------------------------------------------------------------------- + ------------------ special type1 command stuff --------------------- + -------------------------------------------------------------------- + when T1_SEEK_RESTORE => + -- In this state, the data register and the track register are updated, if the + -- command is a RESTORE. The update is done further down with the track register + -- and the data register controls. + NEXT_CMD_STATE <= T1_LOAD_SHFT; + when T1_STEPPING => + if CMD(4) = '1' then -- '1' means update track register. + NEXT_CMD_STATE <= T1_CHECK_DIR; + else + NEXT_CMD_STATE <= T1_HEAD_CTRL; + end if; + when T1_LOAD_SHFT => + NEXT_CMD_STATE <= T1_COMP_TR_DSR; + when T1_COMP_TR_DSR => + if DSR = TR then + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + else + -- The direction control is done further down. + NEXT_CMD_STATE <= T1_CHECK_DIR; + end if; + when T1_CHECK_DIR => + -- Track register modifications are done in + -- statements further down. + -- The delay is to provide the timing of the WD1772 which is DIR to step = + -- 24us in MFM mode and 48us in FM mode. + if DELAY = true then + NEXT_CMD_STATE <= T1_HEAD_CTRL; + else + NEXT_CMD_STATE <= T1_CHECK_DIR; + end if; + when T1_HEAD_CTRL => + if TRACK00n = '0' and DIR = '0' then + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + else + NEXT_CMD_STATE <= T1_STEP; + end if; + when T1_STEP => + NEXT_CMD_STATE <= T1_TRAP; + when T1_TRAP => + if STEP_TRAP = true then + NEXT_CMD_STATE <= IDLE; -- Break due to seek error. + else + NEXT_CMD_STATE <= T1_STEP_DELAY; + end if; + when T1_STEP_DELAY => + -- The delay in here is according to the CMD(1 downto 0) as follows: + -- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms. + if DELAY = true then + case CMD(7 downto 5) is + when "001" | "010" | "011" => -- STEP - STEP IN - STEP OUT. + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + when others => -- Seek or restore command. + NEXT_CMD_STATE <= T1_LOAD_SHFT; + end case; + else + NEXT_CMD_STATE <= T1_STEP_DELAY; + end if; + when T1_VERIFY_DELAY => + if CMD(2) = '0' then -- No verify. + NEXT_CMD_STATE <= IDLE; + else + if DELAY = true then -- Wait, if verify is active. + NEXT_CMD_STATE <= T1_SPINDOWN; + else + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + end if; + end if; + when T1_SPINDOWN => -- Detect ID address mark in here. + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + elsif ID_AM = '1' then -- Addressmark found. + NEXT_CMD_STATE <= T1_SCAN_TRACK; + else + NEXT_CMD_STATE <= T1_SPINDOWN; + end if; + when T1_SCAN_TRACK => + if DELAY = true then + -- Track found if shift register (DSR) equals track register (TR). + if DSR = TR then + NEXT_CMD_STATE <= T1_SCAN_CRC; + else + NEXT_CMD_STATE <= T1_SPINDOWN; + end if; + else + NEXT_CMD_STATE <= T1_SCAN_TRACK; + end if; + when T1_SCAN_CRC => + -- Scan the rest of the data header for correct CRC generation (3 Bytes). + -- Sector number side select byte and data length byte. + if DELAY = true then + NEXT_CMD_STATE <= T1_VERIFY_CRC; + else + NEXT_CMD_STATE <= T1_SCAN_CRC; + end if; + when T1_VERIFY_CRC => + -- The CRC logic starts during T1_SPINDOWN (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= T1_SPINDOWN; -- CRC error. + else + NEXT_CMD_STATE <= IDLE; -- Operation finished. + end if; + else + NEXT_CMD_STATE <= T1_VERIFY_CRC; -- Wait until CRC logic is ready. + end if; + -------------------------------------------------------------------- + ------------------ special type2 command stuff --------------------- + -------------------------------------------------------------------- + when T2_RD_WR_SECT => + if CMD(7 downto 5) = "101" and WPRTn = '0' then + NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk. + else + NEXT_CMD_STATE <= T2_INIT; + end if; + when T2_INIT => + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + elsif ID_AM = '0' then + NEXT_CMD_STATE <= T2_INIT; -- Wait for address mark. + else -- INDEX_CNT = false and ID_AM = '1' -> ID address mark detected + NEXT_CMD_STATE <= T2_SCAN_TRACK; + end if; + when T2_SCAN_TRACK => + -- Track found if shift register (DSR) equals track register (TR). + if DELAY = true then + if DSR = TR then + NEXT_CMD_STATE <= T2_SCAN_SECT; + else + NEXT_CMD_STATE <= T2_INIT; + end if; + else + NEXT_CMD_STATE <= T2_SCAN_TRACK; + end if; + when T2_SCAN_SECT => + -- Sector found if shift register (DSR) equals sector register (SR). + if DELAY = true then + if DSR = SR then + NEXT_CMD_STATE <= T2_SCAN_LEN; + else + NEXT_CMD_STATE <= T2_INIT; + end if; + else + NEXT_CMD_STATE <= T2_SCAN_SECT; + end if; + when T2_SCAN_LEN => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_CRC_1; + else + NEXT_CMD_STATE <= T2_SCAN_LEN; + end if; + when T2_VERIFY_CRC_1 => + -- The CRC logic starts after T2_INIT (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= T2_INIT; -- CRC error. + elsif CRC_ERR = '0' and CMD(7 downto 5) = "101" then + NEXT_CMD_STATE <= T2_DELAY_B2; -- Comand is a write. + else -- Command is a read. + NEXT_CMD_STATE <= T2_VERIFY_AM; + end if; + else + NEXT_CMD_STATE <= T2_VERIFY_CRC_1; -- Wait until CRC logic is ready. + end if; + when T2_VERIFY_AM => + if DATA_AM = '1' or DDATA_AM = '1' then -- Data address mark detected, go on. + NEXT_CMD_STATE <= T2_FIRSTBYTE; + elsif DELAY = false then -- Stay in this state. + NEXT_CMD_STATE <= T2_VERIFY_AM; + else + NEXT_CMD_STATE <= T2_INIT; -- No addressmark detected. + end if; + when T2_FIRSTBYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_LOAD_DATA; + else + NEXT_CMD_STATE <= T2_FIRSTBYTE; + end if; + when T2_LOAD_DATA => + NEXT_CMD_STATE <= T2_NEXTBYTE; + when T2_NEXTBYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_1; + else + NEXT_CMD_STATE <= T2_NEXTBYTE; + end if; + when T2_VERIFY_DRQ_1 => + NEXT_CMD_STATE <= T2_RDSTAT; + when T2_RDSTAT => + if SECT_LEN = "00000000000" then + NEXT_CMD_STATE <= T2_VERIFY_CRC_2; + else + NEXT_CMD_STATE <= T2_LOAD_DATA; + end if; + when T2_VERIFY_CRC_2 => + -- The CRC logic starts after T2_VERIFY_AM (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= IDLE; -- Break due to CRC error. + else + NEXT_CMD_STATE <= T2_MULTISECT; + end if; + else + NEXT_CMD_STATE <= T2_VERIFY_CRC_2; -- Wait until CRC logic is ready. + end if; + when T2_MULTISECT => + if CMD(4) = '1' then + NEXT_CMD_STATE <= T2_RD_WR_SECT; + else + NEXT_CMD_STATE <= IDLE; -- Operation finished. + end if; + when T2_DELAY_B2 => + if DELAY = true then + NEXT_CMD_STATE <= T2_SET_DRQ; + else + NEXT_CMD_STATE <= T2_DELAY_B2; + end if; + when T2_SET_DRQ => + NEXT_CMD_STATE <= T2_DELAY_B8; + when T2_DELAY_B8 => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_2; + else + NEXT_CMD_STATE <= T2_DELAY_B8; + end if; + when T2_VERIFY_DRQ_2 => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T2_DELAY_B1; + else + NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host). + end if; + when T2_DELAY_B1 => + if DELAY = true then + NEXT_CMD_STATE <= T2_CHECK_MODE; + else + NEXT_CMD_STATE <= T2_DELAY_B1; + end if; + when T2_CHECK_MODE => + if DDEn = '1' then -- FM mode + NEXT_CMD_STATE <= T2_WR_LEADIN; + else + NEXT_CMD_STATE <= T2_DELAY_B11; + end if; + when T2_DELAY_B11 => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_LEADIN; + else + NEXT_CMD_STATE <= T2_DELAY_B11; + end if; + when T2_WR_LEADIN => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_AM; + else + NEXT_CMD_STATE <= T2_WR_LEADIN; + end if; + when T2_WR_AM => -- Write data address mark. + if DELAY = true then + NEXT_CMD_STATE <= T2_LOAD_SHFT; + else + NEXT_CMD_STATE <= T2_WR_AM; + end if; + when T2_LOAD_SHFT => + NEXT_CMD_STATE <= T2_WR_BYTE; + when T2_WR_BYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_3; + else + NEXT_CMD_STATE <= T2_WR_BYTE; + end if; + when T2_VERIFY_DRQ_3 => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T2_WRSTAT; + else + NEXT_CMD_STATE <= T2_DATALOST; + end if; + when T2_DATALOST => + if DELAY = true then + NEXT_CMD_STATE <= T2_WRSTAT; + else + NEXT_CMD_STATE <= T2_DATALOST; + end if; + when T2_WRSTAT => + if SECT_LEN = "00000000000" then + NEXT_CMD_STATE <= T2_WR_CRC; -- Write operation finished. + else + NEXT_CMD_STATE <= T2_LOAD_SHFT; + end if; + when T2_WR_CRC => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_FF; + else + NEXT_CMD_STATE <= T2_WR_CRC; + end if; + when T2_WR_FF => + if DELAY = true then + NEXT_CMD_STATE <= T2_MULTISECT; + else + NEXT_CMD_STATE <= T2_WR_FF; + end if; + -------------------------------------------------------------------- + ---------------- type3 write track command stuff ------------------- + -------------------------------------------------------------------- + when T3_WR => + if WPRTn = '0' then + NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk. + else + NEXT_CMD_STATE <= T3_DELAY_B3; + end if; + when T3_DELAY_B3 => + if DELAY = true then + NEXT_CMD_STATE <= T3_VERIFY_DRQ; + else + NEXT_CMD_STATE <= T3_DELAY_B3; + end if; + when T3_VERIFY_DRQ => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T3_CHECK_INDEX_1; + else + NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host). + end if; + when T3_CHECK_INDEX_1 => + if IPn = '0' then + NEXT_CMD_STATE <= T3_LOAD_SHFT; + else + NEXT_CMD_STATE <= T3_CHECK_INDEX_1; + end if; + when T3_LOAD_SHFT => + NEXT_CMD_STATE <= T3_WR_DATA; + when T3_WR_DATA => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_2; + else + NEXT_CMD_STATE <= T3_WR_DATA; + end if; + when T3_CHECK_INDEX_2 => + if INDEX_MARK = '1' then + NEXT_CMD_STATE <= IDLE; -- End of track reached. + elsif DRQ_I = '0' then -- New data has been loaded. + NEXT_CMD_STATE <= T3_LOAD_SHFT; -- Fetch new data. + else + NEXT_CMD_STATE <= T3_DATALOST; -- Fill in nullbyte. + end if; + when T3_DATALOST => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_2; + else + NEXT_CMD_STATE <= T3_DATALOST; + end if; + -------------------------------------------------------------------- + --------------- type3 read track command stuff -------------------- + -------------------------------------------------------------------- + when T3_RD_TRACK => + -- wait for index pulse: + if IPn = '0' then + NEXT_CMD_STATE <= T3_SHIFT; + else + NEXT_CMD_STATE <= T3_RD_TRACK; + end if; + when T3_SHIFT => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_3; + else + NEXT_CMD_STATE <= T3_SHIFT; + end if; + when T3_CHECK_INDEX_3 => + if INDEX_MARK = '1' then + NEXT_CMD_STATE <= IDLE; -- End of track reached. + else + NEXT_CMD_STATE <= T3_DETECT_AM; + end if; + when T3_DETECT_AM => -- Detect for ID address mark. + if ID_AM = '1' then + NEXT_CMD_STATE <= T3_CHECK_DR; + else + NEXT_CMD_STATE <= T3_CHECK_BYTE; + end if; + when T3_CHECK_BYTE => + if BYTE_RDY = true then + NEXT_CMD_STATE <= T3_CHECK_DR; + else + NEXT_CMD_STATE <= T3_SHIFT; + end if; + when T3_CHECK_DR => + NEXT_CMD_STATE <= T3_LOAD_DATA_1; + when T3_LOAD_DATA_1 => + NEXT_CMD_STATE <= T3_SET_DRQ_1; + when T3_SET_DRQ_1 => + NEXT_CMD_STATE <= T3_SHIFT; + -------------------------------------------------------------------- + ---------------- type3 read address command stuff ------------------ + -------------------------------------------------------------------- + when T3_RD_ADR => + -- check for 6 index holes + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + else + NEXT_CMD_STATE <= T3_VERIFY_AM; + end if; + when T3_VERIFY_AM => -- Check for existing ID address mark + if ID_AM = '1' then + NEXT_CMD_STATE <= T3_SHIFT_ADR; + else + NEXT_CMD_STATE <= T3_RD_ADR; + end if; + when T3_SHIFT_ADR => + if DELAY = true then + NEXT_CMD_STATE <= T3_LOAD_DATA_2; + else + NEXT_CMD_STATE <= T3_SHIFT_ADR; + end if; + when T3_LOAD_DATA_2 => + NEXT_CMD_STATE <= T3_SET_DRQ_2; + when T3_SET_DRQ_2 => + NEXT_CMD_STATE <= T3_CHECK_RD; + when T3_CHECK_RD => + if T3_TRADR = true then + NEXT_CMD_STATE <= T3_LOAD_SR; + else + NEXT_CMD_STATE <= T3_SHIFT_ADR; + end if; + when T3_LOAD_SR => + NEXT_CMD_STATE <= T3_VERIFY_CRC; + when T3_VERIFY_CRC => + -- The CRC logic starts during T3_VERIFY_AM (missing clock transitions). + if DELAY = true then + NEXT_CMD_STATE <= IDLE; -- Operation finished (with or without CRC error). + else + NEXT_CMD_STATE <= T3_VERIFY_CRC; -- Wait until CRC logic is ready. + end if; + end case; + end process CMD_DECODER; + + P_DELAY: process(RESETn, CLK, CMD_STATE, T3_DATATYPE, DDEn, CMD) + -- This process is responsible to control the DELAY signal in the different command + -- states of the main state machine. These states finish, if the signal DELAY is + -- asserted. The condition for asserted DELAY is the correct number of data strobes + -- which are supervised by the DATA_STRB inputs. + -- Another condition is a time delay required in the following states: + -- In DELAY_15MS there is a delay of 30ms. + -- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows: + -- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms. + -- In T1_VERIFY_DELAY there is a delay of 30ms. + variable DELCNT : std_logic_vector(19 downto 0); + begin + if RESETn = '0' then + DELCNT := (others => '0'); + elsif CLK = '1' and CLK' event then + -- Reset the delay right after it occurs: + if DELAY = true then + DELCNT := (others => '0'); + elsif DATA_AM = '1' or DDATA_AM = '1' then -- Reset in command state T2_VERIFY_AM. + DELCNT := (others => '0'); + else + case CMD_STATE is + -- Time delays work on CLK edges. + when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY => + DELCNT := DELCNT + '1'; + -- Bit count delays work on data strobes. + -- Read from disk operation: + when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT | + T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM | T2_FIRSTBYTE | + T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC => + if DATA_STRB = '1' then + DELCNT := DELCNT + '1'; + end if; + -- Write to disk operation: + when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN | + T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST | + T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST => + if DATA_STRB = '1' then + DELCNT := DELCNT + '1'; + end if; + when others => + DELCNT := (others => '0'); -- Clear the delay counter if not used. + end case; + end if; + end if; + + case CMD_STATE is + when DELAY_15MS | T1_VERIFY_DELAY => + case DELCNT is + --when x"75300" => DELAY <= true; -- 30ms + when x"3A980" => DELAY <= true; -- 15ms, thanks to L. Amsdon. + when others => DELAY <= false; + end case; + when T1_CHECK_DIR => + if DDEn = '1' and DELCNT = x"00300" then -- 48us in FM + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00180" then -- 24us in MFM. + DELAY <= true; + else + DELAY <= false; + end if; + when T1_STEP_DELAY => + if CMD(1 downto 0) = "11" and DELCNT >= x"0BB80" then -- 3ms + DELAY <= true; + elsif CMD(1 downto 0) = "10" and DELCNT >= x"07D00" then -- 2ms + DELAY <= true; + elsif CMD(1 downto 0) = "01" and DELCNT >= x"2EE00" then -- 12ms + DELAY <= true; + elsif CMD(1 downto 0) = "00" and DELCNT >= x"17700" then -- 6ms + DELAY <= true; + else + DELAY <= false; + end if; + when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE | + T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR => + case DELCNT is + when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times. + when others => DELAY <= false; + end case; + when T1_SCAN_CRC => + case DELCNT is + when x"00018" => DELAY <= true; -- Scan for 3 bytes. + when others => DELAY <= false; + end case; + when T2_WR_AM => + if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode). + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode). + DELAY <= true; + else + DELAY <= false; + end if; + when T2_VERIFY_AM => + if DDEn = '1' and DELCNT >= x"00148" then -- FM mode. + DELAY <= true; -- (11+6+1)+1 = 19 Byte Times, plus 10 Byte times uncertainty. + elsif DDEn = '0' and DELCNT >= x"00188" then -- MFM mode. + DELAY <= true; -- (22+12+3+1)+1 = 39 Byte Times, plus 10 Byte times uncertainty. + else + DELAY <= false; + end if; + when T2_WR_LEADIN => + if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode. + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode. + DELAY <= true; + else + DELAY <= false; + end if; + when T2_DELAY_B1 => + case DELCNT is + when x"00008" => DELAY <= true; -- Delay is 1 byte. + when others => DELAY <= false; + end case; + when T3_DELAY_B3 => + case DELCNT is + when x"00018" => DELAY <= true; -- Delay is 3 bytes. + when others => DELAY <= false; + end case; + when T2_DELAY_B8 => + case DELCNT is + when x"00040" => DELAY <= true; -- Delay is 8 bytes. + when others => DELAY <= false; + end case; + when T2_DELAY_B11 => + case DELCNT is + when x"00058" => DELAY <= true; -- Delay is 11 bytes. + when others => DELAY <= false; + end case; + when T2_VERIFY_CRC_2 => + -- In this state the original WD1772 state machine causes the CRC data to appear 1 byte + -- too early. The reason is the construction of the states T2_LOAD_DATA and T2_NEXTBYTE + -- where the length counter and the DRQ flag are serviced in T2_LOAD_DATA. Therefore the + -- delay is only 1 byte instead of 2. + case DELCNT is + when x"00008" => DELAY <= true; -- Scan for 2 bytes but wait only 1 byte. + when others => DELAY <= false; + end case; + when T1_VERIFY_CRC | T2_SCAN_SECT | T2_VERIFY_CRC_1 | T2_DELAY_B2 | T2_WR_CRC | T3_VERIFY_CRC => + case DELCNT is + when x"00010" => DELAY <= true; -- Scan for 2 bytes (e. g. side and sector in T2_SCAN_SECT). + when others => DELAY <= false; + end case; + when T3_WR_DATA => + if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits. + DELAY <= true; + elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits. + DELAY <= true; + else + DELAY <= false; + end if; + when T3_SHIFT => + case DELCNT is + when x"00001" => DELAY <= true; -- Scan just one data bit. + when others => DELAY <= false; + end case; + when others => + DELAY <= false; + end case; + end process P_DELAY; + + INDEX_COUNTER: process(RESETn, CLK, CMD_STATE) + -- This process is intended to control some command states via the index pulse behavior. + -- In the original WD177x there is foreseen a delay of several index pulses (about 1s). + -- It is achieved by counting the index pulses of the disk. This encounters problems, + -- if the disk is not inserted. For this reason there is additionally to the index counter + -- a timeout which is active if there are no index pulses. + variable CNT : std_logic_vector(3 downto 0); + variable TIMEOUT : std_logic_vector(27 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + CNT := x"0"; + TIMEOUT := (others => '0'); + LOCK := false; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + -- Be aware that there must sometimes checked several states for the presence of IPn! + when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | + T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM => + if IPn = '0' and LOCK = false then -- Count the index pulses. + CNT := CNT + '1'; + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + -- + if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s. + TIMEOUT := TIMEOUT + '1'; + end if; + when others => + CNT := x"0"; + TIMEOUT := (others => '0'); + end case; + end if; + -- + if CMD_STATE = SPINUP and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T1_SPINDOWN and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T2_INIT and (CNT = "101" or TIMEOUT = x"17FFFFF") then -- 5 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T3_RD_ADR and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + else + INDEX_CNT <= false; + end if; + end process INDEX_COUNTER; + + P_INDEX_MARK: process + -- This process controls the occurence of an index pulse during read track + -- and write track commands. The flag INDEX_MARK is cleared at the + -- beginning of these two commands during the first check for an index + -- pulse and is set right after the next index pulse occurs, which means + -- track processing has completed. + variable LOCK: boolean; + begin + wait until CLK = '1' and CLK' event; + if CMD_STATE = T3_RD_TRACK and IPn = '0' then + INDEX_MARK <= '0'; -- Reset the flag. + LOCK := true; + elsif CMD_STATE = T3_CHECK_INDEX_1 and IPn = '0' then + INDEX_MARK <= '0'; -- Reset the flag. + LOCK := true; + elsif IPn = '0' and LOCK = false then + INDEX_MARK <= '1'; -- Index pulse has passed. + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + end process P_INDEX_MARK; + + P_T3_DATATYPE: process(RESETn, CLK) + -- In type 3 write track command, it is necessary to store the information, which data + -- has to be written to disk (in command state T3_WR_DATA. This information is sampled + -- in the command state T3_LOAD_SHFT which preceeds the command state T3_WR_DATA. + begin + if RESETn = '0' then + T3_DATATYPE <= x"00"; + elsif CLK = '1' and CLK' event then + if CMD_STATE = T3_LOAD_SHFT then + T3_DATATYPE <= DR; + end if; + end if; + end process P_T3_DATATYPE; + + CNT_T3BYTES: process(RESETn, CLK, CMD_STATE) + -- This process counts the bytes read in the type III read address + -- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2, + -- T3_SET_DRQ_2 and T3_CHECK_RD. + variable CNT : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + CNT := "000"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T3_VERIFY_AM => + CNT := "000"; -- Clear the counter right befor the count operation. + when T3_SET_DRQ_2 => + CNT := CNT + '1'; -- Increment after each read cycle. + when others => + null; + end case; + end if; + case CNT is + when "100" => T3_TRADR <= true; + when others => T3_TRADR <= false; + end case; + end process CNT_T3BYTES; + + BYTEASMBLY: process(RESETn, CLK) + -- This process controls the condition in the CMD_STATE T3_CHECK_DR. + -- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted. + -- The count condition is entering the command state T3_CHECK_INDEX_3. The clear + -- condition is either the command state IDLE or the command state T3_CHECK_DR. + variable CNT : std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + CNT := x"0"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when IDLE => CNT := x"0"; + when T3_CHECK_INDEX_3 => CNT := CNT + '1'; + when T3_CHECK_DR => CNT := (others => '0'); + when others => null; + end case; + end if; + case CNT is + when x"8" => BYTE_RDY <= true; + when others => BYTE_RDY <= false; + end case; + end process BYTEASMBLY; + + P_DIR: process(RESETn, CLK, DIR) + -- This portion of code is responsible to control the right stepping + -- direction in type I commands. + begin + if RESETn = '0' then + DIR <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = DECODE and CMD(7 downto 5) = "010" then -- Step in. + DIR <= '1'; + elsif CMD_STATE = DECODE and CMD(7 downto 5) = "011" then -- Step out. + DIR <= '0'; + elsif CMD_STATE = T1_COMP_TR_DSR and DSR > TR then -- Seek. + DIR <= '1'; + elsif CMD_STATE = T1_COMP_TR_DSR and DSR < TR then -- Seek. + DIR <= '0'; + end if; + end if; + DIRC <= DIR; -- Copy signal to the output. + end process P_DIR; + + P_DRQ: process(RESETn, CLK, DRQ_I) + begin + if RESETn = '0' then + DRQ_I <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when INIT => + DRQ_I <= '0'; + when T2_LOAD_DATA | T2_SET_DRQ | T2_LOAD_SHFT => + DRQ_I <= '1'; + when T3_WR | T3_LOAD_SHFT | T3_SET_DRQ_1 | T3_SET_DRQ_2 => + DRQ_I <= '1'; + when others => + null; + end case; + -- The data request bit is also cleared by reading or writing the + -- data register (direct memory access operation). + if (DATA_RD = true or DATA_WR = true) then + DRQ_I <= '0'; + end if; + end if; + -- + DRQ <= DRQ_I; -- Copy to entity. + -- + end process P_DRQ; + + -- The DRQ_IPn detects the index pulse during type I commands and a forced interrupt or + -- DRQ during type II and III commands. + -- The index pulse flag is active high and can be used for the detection of an inserted disk. + DRQ_IPn <= not IPn when CMD(7) = '0' else + not IPn when CMD(7 downto 4) = x"D" and BUSY = '0' else DRQ_I; + + P_BUSY: process(RESETn, CLK) + begin + if RESETn = '0' then + BUSY <= '0'; + elsif CLK = '1' and CLK' event then + -- During forced interrupt, the busy flag is reset when the command + -- state machine enters the IDLE state. + if CMD_STATE = INIT then + BUSY <= '1'; -- set BUSY flag for all command types I ... III. + elsif CMD_STATE = IDLE then + BUSY <= '0'; -- Reset BUSY after entering IDLE in any case. + end if; + end if; + end process P_BUSY; + + P_SEEK_RNF: process(RESETn, CLK) + -- Seek error or record not found error flag. + begin + if RESETn = '0' then + SEEK_RNF <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT then + SEEK_RNF <= '0'; -- Clear the flag for all command types I ... III. + elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then + SEEK_RNF <= '1'; -- Seek error (SEEK). + elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Seek error (SEEK). + elsif CMD_STATE = T2_INIT and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Record not found (RNF). + elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Record not found (RNF). + end if; + end if; + end process P_SEEK_RNF; + + P_INTRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INTRQ <= '0'; + elsif CLK = '1' and CLK' event then + -- Interrupt reset conditions: + if STAT_RD = true and CMD /= x"D8" then + -- No clear during immediately forced interrupt. + INTRQ <= '0'; -- Clear the flag when status register is read. + elsif CMD_WR = true and CMD = x"D0" then + -- Clear with the next write access to the command register after the + -- forced interrupt x"D0" was written. + INTRQ <= '0'; + elsif CMD_STATE = INIT and CMD(7 downto 6) /= "11" then + INTRQ <= '0'; -- Clear the flag for type I and type II commands during start of execution. + -- Interrupt set conditions. + elsif CMD = x"D8" and CMD_STATE = IDLE then + INTRQ <= '1'; -- Force interrupt immediately (after the break took affect). + elsif CMD = x"D4" and IPn = '0' and CMD_STATE = IDLE then + INTRQ <= '1'; -- Force interrupt on next index pulse (after the break took affect). + elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then + INTRQ <= '1'; -- Indicate interrupt request due to seek error. + elsif CMD_STATE = T1_VERIFY_DELAY and CMD(2) = '0' then + INTRQ <= '1'; -- Indicate interrupt: command finished or interrupted. + elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request, reason: seek error. + elsif CMD_STATE = T1_VERIFY_CRC and CRC_ERR = '0' then + INTRQ <= '1'; -- Indicate interrupt request; command correct, no CRC error. + elsif CMD_STATE = T2_RD_WR_SECT and CMD(7 downto 5) = "101" and WPRTn = '0' then + INTRQ <= '1'; -- Indicate interrupt request because disk is write protected. + elsif CMD_STATE = T2_INIT and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request, reason: timeout. + elsif CMD_STATE = T2_VERIFY_CRC_2 and DELAY = true and CRC_ERR = '1' then + INTRQ <= '1'; -- Indicate interrupt request due to CRC error. + elsif CMD_STATE = T2_MULTISECT and CMD(4) = '0' then + INTRQ <= '1'; -- Indicate interrupt request, command correct finished. + elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: lost data. + elsif CMD_STATE = T3_WR and WPRTn = '0' then + INTRQ <= '1'; -- Indicate interrupt request, reason: disk is write protected. + elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then + INTRQ <= '1'; -- Indicate interrupt request due to lost data. + elsif CMD_STATE = T3_CHECK_INDEX_2 and INDEX_MARK = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly. + elsif CMD_STATE = T3_CHECK_INDEX_3 and INDEX_MARK = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly. + elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request because record was not found. + elsif CMD_STATE = T3_VERIFY_CRC then + INTRQ <= '1'; -- Indicate interrupt request; command finished with or without CRC error. + end if; + end if; + end process P_INTRQ; + + P_LOST_DATA_TR00: process(RESETn, CLK) + -- Logic for the status bit number 2: + -- The TRACK00 flag is used to detect wether a floppy disk drive + -- is connected or not. + begin + if RESETn = '0' then + LOST_DATA_TR00 <= '0'; + elsif CLK = '1' and CLK' event then + if CMD(7 downto 4) = x"D" and BUSY = '0' then -- Forced interrupt. + LOST_DATA_TR00 <= not TRACK00n; + elsif CMD_STATE = INIT then + LOST_DATA_TR00 <= '0'; + elsif CMD_STATE = T1_VERIFY_DELAY then + LOST_DATA_TR00 <= not TRACK00n; + elsif CMD_STATE = T2_VERIFY_DRQ_1 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T2_VERIFY_DRQ_3 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_DATALOST then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_CHECK_DR and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + end if; + end if; + end process P_LOST_DATA_TR00; + + MOTORSWITCH: process(RESETn, CLK) + variable INDEXCNT : std_logic_vector(3 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + MO <= '0'; + INDEXCNT := x"0"; + LOCK := false; + elsif CLK = '1' and CLK' event then + if CMD_STATE /= IDLE then + INDEXCNT := x"9"; -- Initialise the index counter. + LOCK := false; + elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then + INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state. + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + -- + if CMD_STATE = INIT and CMD_WR = false then + MO <= '1'; -- Start the motor for all command types I ... III in this state. + elsif INDEXCNT = x"0" then + MO <= '0'; -- The motor stops after 9 index pulses in idle state. + end if; + end if; + end process MOTORSWITCH; + + WRITE_PROTECT: process(RESETn, CLK) + begin + if RESETn = '0' then + WR_PR <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT and CMD(7) = '1' then + WR_PR <= '0'; -- Clear the flag for type II and type III commands. + elsif CMD_STATE = T2_RD_WR_SECT and WPRTn = '0' then + WR_PR <= '1'; + elsif CMD_STATE = T3_WR and WPRTn = '0' then + WR_PR <= '1'; + end if; + end if; + end process WRITE_PROTECT; + + RECTYPE_SPINUP: process(RESETn, CLK) + begin + if RESETn = '0' then + SPINUP_RECTYPE <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT then + SPINUP_RECTYPE <= '0'; -- Clear the flag for type II...III commands. + elsif CMD_STATE = SPINUP and CMD(7) = '0' and INDEX_CNT = true then + SPINUP_RECTYPE <= '1'; -- SPINUP SEQUENCE for type I commands has finished. + elsif CMD_STATE = T2_VERIFY_AM and (DATA_AM = '1' or DDATA_AM = '1') then + case DSR is + when x"F8" => SPINUP_RECTYPE <= '1'; -- Deleted data address mark. + when x"FB" => SPINUP_RECTYPE <= '0'; -- Normal data address mark. + when others => null; -- Forbidden, should never appear. + end case; + end if; + end if; + end process RECTYPE_SPINUP; + + WRITEGATE: process(RESETn, CLK) + begin + if RESETn = '0' then + WG <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T2_WR_LEADIN | T3_LOAD_SHFT => + WG <= '1'; + when T2_MULTISECT | IDLE => + WG <= '0'; + when others => + null; + end case; + end if; + end process WRITEGATE; + + RESTORE_TRAP: process(RESETn, CLK) + -- This process is responsible to supervise the RESTORE command. + -- If after 255 stepping pulses no TRACK00n was not detected, the + -- RESTORE command is terminated and the interrupt request and the + -- seek error are set. + variable STEP_CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + STEP_CNT := (others => '0'); + elsif CLK = '1' and CLK' event then + if CMD_STATE = IDLE then + STEP_CNT := x"00"; + elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command. + STEP_CNT := x"00"; + elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then + STEP_CNT := STEP_CNT + '1'; + end if; + end if; + -- + case STEP_CNT is + when x"FF" => STEP_TRAP <= true; + when others => STEP_TRAP <= false; + end case; + end process RESTORE_TRAP; + + STEPPULSE: process(RESETn, CLK) + -- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us. + -- in FM mode This process is responsible to provide the correct pulse lengths. + variable CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + CNT := (others => '0'); + elsif CLK = '1' and CLK' event then + if CMD_STATE = T1_STEP then + case DDEn is + when '1' => CNT := x"80"; --Start counter for FM step pulse. + when '0' => CNT := x"40"; --Start counter for MFM step pulse. + end case; + elsif CNT > x"00" then + CNT := CNT -1; -- Count 63 or 127 CLK cycles ... + end if; + case CNT is + when x"00" => STEP <= '0'; + when others => STEP <= '1'; --...result in 3.875us or 7.75us pulse. + end case; + end if; + end process STEPPULSE; + + TRACK_MEM: process(RESETn, CLK, TRACKMEM) + -- This process is necessary to store the actual track number in the + -- type III command 'read address' because the track number is written + -- to the sector register some byte times after the detection of the + -- track number from disk. + begin + if RESETn = '0' then + TRACKMEM <= x"00"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when IDLE => + TRACKMEM <= x"00"; -- Clear the Track memory. + when T3_LOAD_DATA_2 => + TRACKMEM <= DSR; -- Store the actual track number. + when others => + null; + end case; + end if; + TRACK_NR <= TRACKMEM; -- Output the TRACKMEM. + end process TRACK_MEM; + + SECT_LENGTH: process(RESETn, CLK, SECT_LEN) + -- This process supervises the read sector and write sector + -- commands. If the sector read or write are equal to the + -- sector length, the commands read sector and write sector + -- are ready. + begin + if RESETn = '0' then + SECT_LEN <= "00000000000"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T2_SCAN_LEN => + -- Bring in the correct sector length. + case DSR(1 downto 0) is + when "00" => SECT_LEN <= "00010000000"; -- 128 Byte per sector. + when "01" => SECT_LEN <= "00100000000"; -- 256 Byte per sector. + when "10" => SECT_LEN <= "01000000000"; -- 512 Byte per sector. + when "11" => SECT_LEN <= "10000000000"; -- 1024 Byte per sector. + when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -. + end case; + when T2_LOAD_DATA | T2_LOAD_SHFT => + SECT_LEN <= SECT_LEN - '1'; + when others => + null; + end case; + end if; + end process SECT_LENGTH; + + P_CRC_ERR: process(RESETn, CLK) + -- This code checks the CRC status in the right command states + -- and sets or resets the CRC error status flag. + begin + if RESETn = '0' then + CRC_ERRFLAG <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when INIT => + if CMD(7) = '0' then + CRC_ERRFLAG <= '0'; -- Reset for type I commands only. + end if; + when T1_VERIFY_CRC | T2_VERIFY_CRC_1 => + if CRC_ERR = '1' and DELAY = true then + CRC_ERRFLAG <= '1'; -- Set CRC error flag... + elsif CRC_ERR = '0' and DELAY = true then + CRC_ERRFLAG <= '0'; -- ... or reset CRC error flag. + end if; + when T2_VERIFY_CRC_2 | T3_VERIFY_CRC => + if CRC_ERR = '1' and DELAY = true then + -- Set CRC error flag but no reset in here. + -- The CRC is already reset by the previous checks. + CRC_ERRFLAG <= '1'; + end if; + when others => + null; + end case; + end if; + end process P_CRC_ERR; + + CMD_WR <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '0' else false; -- Command register write. + STAT_RD <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '1' else false; -- Status register read. + DATA_WR <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '0' else false; -- Data register write. + DATA_RD <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '1' else false; -- Data register read. + + -- Track register arithmetics controls: + TR_PRES <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command. + TR_CLR <= '1' when CMD_STATE = T1_HEAD_CTRL and TRACK00n = '0' and DIR = '0' else '0'; + TR_INC <= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '1' else '0'; + TR_DEC <= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '0' else '0'; + + -- Sector register arithmetics: + SR_INC <= '1' when CMD_STATE = T2_MULTISECT and CMD(4) = '1' else '0'; -- Multi sector enabled. + SR_LOAD <= '1' when CMD_STATE = T3_LOAD_SR else '0'; + + -- Data register arithmetics controls: + DR_CLR <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command. + DR_LOAD <= '1' when CMD_STATE = T2_LOAD_DATA else + '1' when CMD_STATE = T3_LOAD_DATA_1 else + '1' when CMD_STATE = T3_LOAD_DATA_2 else '0'; + + -- Shift register arithmetics controls: + -- During type I and type II commands all characters are allowed as data. + -- During the type III write track command, there are some special characters + -- which may not appear as normal data. See the register file for more information. + SHFT_LOAD_SD <= '1' when CMD_STATE = T3_LOAD_SHFT else '0'; -- Special data. + SHFT_LOAD_ND <= '1' when CMD_STATE = T1_LOAD_SHFT else + '1' when CMD_STATE = T2_LOAD_SHFT else '0'; -- Normal data. + + P_CRC_PRES: process(RESETn, CLK) + -- CRC preset during write sector and write track commands. + variable LOCK : boolean; + begin + if RESETn = '0' then + CRC_PRES <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- In write track command, the CRC is initialised at the beginning of the + -- first A1 data and released during shifting the CRC out. + if CMD_STATE = T2_WR_AM and LOCK = false then + CRC_PRES <= '1'; -- Write sector command. + LOCK := true; + elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F5" and LOCK = false then -- x"F5" means write A1. + CRC_PRES <= '1'; -- Write track command. + LOCK := true; + elsif CMD_STATE = T2_WR_CRC then + CRC_PRES <= '0'; -- Write sector command. + LOCK := false; + elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F7" then + CRC_PRES <= '0'; -- Write track command. + LOCK := false; + else + CRC_PRES <= '0'; + end if; + end if; + end process P_CRC_PRES; + + -- Write control signals: + AM_2_DISK <= '1' when CMD_STATE = T2_WR_AM else '0'; + FF_2_DISK <= '1' when CMD_STATE = T2_WR_FF else '0'; + DSR_2_DISK <= '1' when CMD_STATE = T2_WR_BYTE else + '1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE /= x"F7" else '0'; -- not during CRC. + CRC_2_DISK <= '1' when CMD_STATE = T2_WR_CRC else + '1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE = x"F7" else '0'; + + -- Write precompensation control: + PRECOMP_EN <= '1' when CMD(7 downto 4) = x"A" and CMD(1) = '0' else -- Write single sector. + '1' when CMD(7 downto 4) = x"B" and CMD(1) = '0' else -- Write multiple sector. + '1' when CMD(7 downto 4) = x"F" and CMD(1) = '0' else '0'; -- Write track. + + -- Disk data flow direction: + DISK_RWn <= -- Write sector command: + '0' when CMD_STATE = T2_WR_LEADIN else + '0' when CMD_STATE = T2_WR_AM else + '0' when CMD_STATE = T2_LOAD_SHFT else + '0' when CMD_STATE = T2_WR_BYTE else + '0' when CMD_STATE = T2_VERIFY_DRQ_3 else + '0' when CMD_STATE = T2_DATALOST else + '0' when CMD_STATE = T2_WRSTAT else + '0' when CMD_STATE = T2_WR_CRC else + '0' when CMD_STATE = T2_WR_FF else + -- Write track command: + '0' when CMD_STATE = T3_LOAD_SHFT else + '0' when CMD_STATE = T3_WR_DATA else + '0' when CMD_STATE = T3_CHECK_INDEX_2 else + '0' when CMD_STATE = T3_DATALOST else '1'; +end BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd new file mode 100644 index 0000000..54b2060 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd @@ -0,0 +1,162 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The CRC cyclic redundancy checker unit. Further description ---- +---- see below. ---- +---- ---- +---- Working principle of the CRC generator and verify unit: ---- +---- During read operation: ---- +---- The CRC generator is switched on via after the detection of ---- +---- the address ID of the data ID mark. The CRC generation last ---- +---- in case of the address ID until the lenght byte is read. ---- +---- In case of generation after the data address mark the CRC ---- +---- generator is activated until the last data byte is read. ---- +---- The number of data bytes to be read depends on the LENGHT ---- +---- information in the header file. After generation of the CRC ---- +---- the CRC_GEN is switched off and the VERIFY procedure begins ---- +---- by activating CRC_VERIFY. The previously generated CRC is ---- +---- then compared (serially) with the two consecutive read CRC ---- +---- bytes. The CRC error appeas, when the comparision fails. ---- +---- During write operation: ---- +---- The CRC generator is switched on via after the detection of ---- +---- the address ID of the data ID mark. The CRC generation last ---- +---- in case of the address ID until the lenght byte is read. ---- +---- In case of generation after the data address mark the CRC ---- +---- generator is activated until the last data byte is read. ---- +---- The number of data bytes to be read depends on the LENGHT ---- +---- information in the header file. After the generation of the ---- +---- two CRC bytes, the write out process begins by activating ---- +---- CRC_SHFTOUT. The CRC data appears in this case serially on ---- +---- the CRC_SDOUT. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CRC_SHIFT has now synchronous reset to meeet preset behaviour. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_CRC_LOGIC is + port( + -- System control + CLK : in bit; + RESETn : in bit; + DISK_RWn : in bit; + + -- Preset controls: + DDEn : in bit; + ID_AM : in bit; + DATA_AM : in Bit; + DDATA_AM : in Bit; + + -- CRC unit: + SD : in bit; -- Serial data input. + CRC_STRB : in bit; -- Data strobe. + CRC_2_DISK : in bit; -- Forces the unit to flush the CRC remainder. + CRC_PRES : in bit; -- Presets the CRC unit during write to disk. + CRC_SDOUT : out bit; -- Serial data output. + CRC_ERR : out bit -- Indicates CRC error. + ); +end WF1772IP_CRC_LOGIC; + +architecture BEHAVIOR of WF1772IP_CRC_LOGIC is +signal CRC_SHIFT : bit_vector(15 downto 0); +begin + P_CRC: process + -- The shift register is initialised with appropriate values in HD or DD mode. + -- In theory the shift register should be preset to ones. Due to a latency of one byte + -- in FM mode or 4 bytes in MFM mode it is necessary to preset the shift register with + -- the CRC values of this ID address mark, data address mark and the A1 sync bytes. The + -- latency is caused by the addressmark detector which needs one or 4 byte time(s) for + -- detection. The CRC unit therefore starts with every detection of an address mark and + -- ends if the CRC unit is flushed. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CRC_SHIFT <= (others => '1'); + elsif CRC_2_DISK = '1' then + if CRC_STRB = '1' then + CRC_SHIFT <= CRC_SHIFT(14 downto 0) & '0'; + end if; + elsif CRC_PRES = '1' then -- Preset during write sector or write track command. + CRC_SHIFT <= x"FFFF"; + elsif DDEn = '1' and ID_AM = '1' then -- DD mode and ID address mark detected. + CRC_SHIFT <= x"EF21"; -- The CRC-CCITT for data x"FE" is x"EF21" + elsif DDEn = '1' and DATA_AM = '1' then -- DD mode and data address mark detected. + CRC_SHIFT <= x"BF84"; -- The CRC-CCITT for data x"FB" is x"BF84" + elsif DDEn = '1' and DDATA_AM = '1' then -- DD mode and deleted data address mark detected. + CRC_SHIFT <= x"8FE7"; -- The CRC-CCITT for data x"F8" is x"8FE7" + elsif DDEn = '0' and ID_AM = '1' then -- HD mode and ID address mark detected. + CRC_SHIFT <= x"B230"; -- The CRC-CCITT for data x"A1A1A1FE" is x"B230" + elsif DDEn = '0' and DATA_AM = '1' then -- HD mode and data address mark detected. + CRC_SHIFT <= x"E295"; -- The CRC-CCITT for data x"A1A1A1FB" is x"E295" + elsif DDEn = '0' and DDATA_AM = '1' then -- HD mode and deleted data address mark detected. + CRC_SHIFT <= x"D2F6"; -- The CRC-CCITT for data x"A1A1A1F8" is x"D2F6" + elsif CRC_STRB = '1' then + -- CRC-CCITT (xFFFF): + -- the polynomial is G(x) = x^16 + x^12 + x^5 + 1 + -- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC + -- verification. In this operating condition the ID or the data field is compared + -- against the CRC checksum. if there are no errors, the shift register's value is + -- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the + -- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the + -- ID or data field. + CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) & + CRC_SHIFT(10 downto 5) & (CRC_SHIFT(15) xor CRC_SHIFT(4) xor SD) & + CRC_SHIFT(3 downto 0) & (CRC_SHIFT(15) xor SD); + end if; + end process P_CRC; + + CRC_SDOUT <= CRC_SHIFT(15); + CRC_ERR <= '0' when CRC_SHIFT = x"0000" else '1'; +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd new file mode 100644 index 0000000..95ce08c --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd @@ -0,0 +1,426 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The digital PLL is responsible to detect the incoming serial ---- +---- data stream and provide a system clock synchronous signal ---- +---- containing the data and clock information. ---- +---- To understand how the code works in detail refer to the free ---- +---- US patent no. 4,780,844. ---- +---- ---- +---- Attention: The settings for TOP and BOTTOM, which control ---- +---- the PLL frequency and for PHASE_CORR which control the PLL ---- +---- phase are rather critical for a good read condition! To test ---- +---- the PLL in the WD1772 compatible core do the following: ---- +---- Sample on an oscilloscope on one channel the falling edge of ---- +---- the RDn pulse and on the other channel the PLL_DSTRB. The ---- +---- RDn must be located exactly between the PLL_DSTRB pulses. ---- +---- Otherwise, the parameters TOP, BOTTOM and PHASE_CORR have to ---- +---- be optimized. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to lack of FM +-- drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/12/24 WF +-- Improvement of the INPORT process. +-- Bugfix of the FREQ_AMOUNT counter: now stops if its value is zero. +-- Several changes concerning the PLL parameters to improve the +-- stability of the PLL. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_DIGITAL_PLL is + generic( + -- The valid range of the period counter of the PLL is given by the TOP and BOTTOM + -- limits. The counter range is therefore BOTTOM <= counter value <= TOP. + -- The generic PHASE_CORR is responsible fo the center setting of PLL_DSTRB concerning + -- the RDn period. + -- The nominal frequency setting is 128. So it is recommended to use TOP and BOTTOM + -- settings symmetrically around 128. If TOP = BOTTOM = 128, the frequency control + -- is disabled. TOP + PHASE_CORR may not exceed a value of 255. BOTTOM - PHASE_CORR + -- may not drop below zero. + TOP : integer range 0 to 255 := 152; -- +18.0% + BOTTOM : integer range 0 to 255 := 104; -- -18.0% + PHASE_CORR : integer range 0 to 128 := 75 + ); + port( + -- System control + CLK : in bit; -- 16MHz clock. + RESETn : in bit; + + -- Controls + DDEn : in bit; -- Double density enable. + HDTYPE : in bit; -- This control is '1' when HD disks are inserted. + DISK_RWn : in bit; -- Read write control. + + -- Data and clock lines + RDn : in bit; -- Read signal from the disk. + PLL_D : out bit; -- Synchronous read signal. + PLL_DSTRB : out bit -- Read strobe. + ); +end WF1772IP_DIGITAL_PLL; + +architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is +signal RD_In : bit; +signal UP, DOWN : bit; +signal PHASE_DECREASE : bit; +signal PHASE_INCREASE : bit; +signal HI_STOP, LOW_STOP : bit; +signal PER_CNT : std_logic_vector(7 downto 0); +signal ADDER_IN : std_logic_vector(7 downto 0); +signal ADDER_MSBs : bit_vector(2 downto 0); +signal RD_PULSE : bit; +signal ROLL_OVER : bit; +signal HISTORY_REG : bit_vector(1 downto 0); +signal ERROR_HISTORY : integer range 0 to 2; +begin + INPORT: process + -- This process is necessary due to the poor quality of the rising + -- edge of RDn. Let it work on the negative clock edge. + begin + wait until CLK = '0' and CLK' event; + RD_In <= RDn; + end process INPORT; + + EDGEDETECT: process(RESETn, CLK) + -- This process forms a falling edge detector for the incoming + -- data read port. The output (RD_PULSE) goes high for exactly + -- one clock period after the RDn is low and the positive + -- clock edge is detected. + variable LOCK : boolean; + begin + if RESETn = '0' then + RD_PULSE <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if DISK_RWn = '0' then -- Disable detector in write mode. + RD_PULSE <= '0'; + elsif RD_In = '0' and LOCK = false then + RD_PULSE <= '1'; -- READ_PULSE is inverted against RDn + LOCK := true; + elsif RD_In = '1' then + LOCK := false; + RD_PULSE <= '0'; + else + RD_PULSE <= '0'; + end if; + end if; + end process EDGEDETECT; + + PERIOD_CNT: process(RESETn, CLK) + -- This process provides the nominal variable added to the adder. To achieve a good + -- settling time of the PLL in all cases, the period counter is controlled via the DDEn + -- and HDTYPE flags respective to its added value. Be aware, that in case of adding "10" + -- or "11", the TOP value may be exceeded or the period counter may drop below the BOTTOM + -- value. The higher the value added, the faster will be the settling time of phase locked + -- loop . + begin + if RESETn = '0' then + PER_CNT <= "10000000"; -- Initial value is 128. + elsif CLK = '1' and CLK' event then + if UP = '1' then + PER_CNT <= PER_CNT + '1'; + elsif DOWN = '1' then + PER_CNT <= PER_CNT - '1'; + end if; + end if; + end process PERIOD_CNT; + + HI_STOP <= '1' when PER_CNT >= TOP else '0'; + LOW_STOP <= '1' when PER_CNT <= BOTTOM else '0'; + + ADDER_IN <= -- This DISK_RWn = '0' implementation keeps the last phase information + -- of the PLL in read from disk mode. It should be a good solution concer- + -- ning alternative read write cycles. + "10000000" when DISK_RWn = '0' else -- Nominal value for write to disk. + PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags. + PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds. + PER_CNT; -- No phase correction; + + ADDER: process(RESETn, CLK, DDEn, HDTYPE) + -- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock. + -- The offset (LSBs) of the adder input is chosen to be conform with the required + -- rollover period in the different DDEn and HDTYPE modi as follows: + -- With a nominal adder input term of 128: + -- The adder rolls over every 4us for DDEn = 1 and HDTYPE = 0. + -- The adder rolls over every 2us for DDEn = 1 and HDTYPE = 1. + -- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0. + -- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1. + -- The given times are the half of a data period time in MFM or FM. + variable ADDER_DATA : std_logic_vector(12 downto 0); + begin + if RESETn = '0' then + ADDER_DATA := (others => '0'); + elsif CLK = '1' and CLK' event then + ADDER_DATA := ADDER_DATA + ADDER_IN; + end if; + -- + case DDEn & HDTYPE is + when "01" => -- MFM mode using HD disks, results in 1us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8)); + when "00" => -- MFM mode using DD disks, results in 2us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9)); + when "11" => -- FM mode using HD disks, results in 2us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9)); + when "10" => -- FM mode using DD disks, results in 4us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10)); + end case; + end process ADDER; + + ROLLOVER: process(RESETn, CLK) + -- This process forms a falling edge detector for the detection + -- of the adder's rollover time. The output goes low for exactly + -- one clock period after the rollover is detected and the positive + -- clock edge appears. + variable LOCK : boolean; + begin + if RESETn = '0' then + ROLL_OVER <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if ADDER_MSBs /= "111" and LOCK = false then + ROLL_OVER <= '1'; + LOCK := true; + elsif ADDER_MSBs = "111" then + LOCK := false; + ROLL_OVER <= '0'; + else + ROLL_OVER <= '0'; + end if; + end if; + end process ROLLOVER; + PLL_DSTRB <= ROLL_OVER; + + DATA_FLIP_FLOP: process(RESETn, CLK, RD_PULSE) + -- This flip-flop is responsible for 'catching' the read pulses of the + -- serial data input. + begin + if RESETn = '0' then + PLL_D <= '0'; -- Asynchronous reset. + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then + PLL_D <= '1'; -- Read pulse detected. + elsif ROLL_OVER = '1' then + PLL_D <= '0'; + end if; + end if; + end process DATA_FLIP_FLOP; + + WIN_HISTORY: process(RESETn, CLK) + begin + if RESETn = '0' then + HISTORY_REG <= "00"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then + HISTORY_REG <= ADDER_MSBs(2) & HISTORY_REG(1); + end if; + end if; + end process WIN_HISTORY; + + -- Error history: + -- This signal indicates the number of consequtive levels of the adder's + -- MSB and the history register as shown in the following table. The default + -- setting of 0 was added to compile with the Xilinx ISE. + ERROR_HISTORY <= 2 when ADDER_MSBs(2) = '0' and HISTORY_REG = "00" else -- Speed strongly up. + 1 when ADDER_MSBs(2) = '0' and HISTORY_REG = "01" else -- Speed up. + 0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "10" else -- o.k. + 0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "11" else -- Now adjusted. + 0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "00" else -- Now adjusted. + 0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "01" else -- o.k. + 1 when ADDER_MSBs(2) = '1' and HISTORY_REG = "10" else -- Slow down. + 2 when ADDER_MSBs(2) = '1' and HISTORY_REG = "11" else 0; -- Slow strongly down. + + FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP) + -- The frequency decoder controls the period of the data inspection window respective to the + -- ERROR_HISTORY for the 11 bit adder is as follows: + -- ERROR_HISTORY = 0: + -- -> no correction necessary <- + -- ERROR_HISTORY = 1: + -- MSBs input: 7 6 5 4 3 2 1 0 + -- Correction output: -3 -2 -1 0 0 +1 +2 +3 + -- ERROR_HISTORY = 2: + -- MSBs input: 7 6 5 4 3 2 1 0 + -- Correction output: -4 -3 -2 -1 +1 +2 +3 +4 + -- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation + -- of the adder (0 is up). + variable FREQ_AMOUNT: std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + FREQ_AMOUNT := "0000"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then -- Load the frequency amount register. + case ERROR_HISTORY is + when 2 => + case ADDER_MSBs is + when "000" => FREQ_AMOUNT := "0100"; + when "001" => FREQ_AMOUNT := "0011"; + when "010" => FREQ_AMOUNT := "0010"; + when "011" => FREQ_AMOUNT := "0001"; + when "100" => FREQ_AMOUNT := "1001"; + when "101" => FREQ_AMOUNT := "1010"; + when "110" => FREQ_AMOUNT := "1011"; + when "111" => FREQ_AMOUNT := "1100"; + end case; + when 1 => + case ADDER_MSBs is + when "000" => FREQ_AMOUNT := "0011"; + when "001" => FREQ_AMOUNT := "0010"; + when "010" => FREQ_AMOUNT := "0001"; + when "011" => FREQ_AMOUNT := "0000"; + when "100" => FREQ_AMOUNT := "1000"; + when "101" => FREQ_AMOUNT := "1001"; + when "110" => FREQ_AMOUNT := "1010"; + when "111" => FREQ_AMOUNT := "1011"; + end case; + when others => + FREQ_AMOUNT := "0000"; + end case; + elsif FREQ_AMOUNT(2 downto 0) > "000" then + FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register. + end if; + end if; + -- + if FREQ_AMOUNT(3) = '0' and FREQ_AMOUNT(2 downto 0) /= "000" and HI_STOP = '0' then + -- FREQ_AMOUNT(3) = '0' means Frequency is too low. Count up when counter is not at HI_STOP. + UP <= '1'; + DOWN <= '0'; + elsif FREQ_AMOUNT(3) = '1' and FREQ_AMOUNT (2 downto 0) /= "000" and LOW_STOP = '0' then + -- FREQ_AMOUNT(3) = '1' means Frequency is too high. Count down when counter is not at LOW_STOP. + UP <= '0'; + DOWN <= '1'; + else + UP <= '0'; + DOWN <= '0'; + end if; + end process FREQUENCY_DECODER; + + PHASE_DECODER: process(RESETn, CLK) + -- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit + -- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a + -- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of + -- PHASE_AMOUNT). + -- This implementation gives the freedom to adjust the phase amount individually for every mode + -- depending on DDEn and HDTYPE. + variable PHASE_AMOUNT: std_logic_vector(5 downto 0); + begin + if RESETn = '0' then + PHASE_AMOUNT := "000000"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' and DDEn = '1' and HDTYPE = '0' then -- FM mode, single density. + case ADDER_MSBs is -- Multiplier: 4. + when "000" => PHASE_AMOUNT := "010000"; + when "001" => PHASE_AMOUNT := "001101"; + when "010" => PHASE_AMOUNT := "001000"; + when "011" => PHASE_AMOUNT := "000100"; + when "100" => PHASE_AMOUNT := "100100"; + when "101" => PHASE_AMOUNT := "101000"; + when "110" => PHASE_AMOUNT := "101100"; + when "111" => PHASE_AMOUNT := "110000"; + end case; + elsif RD_PULSE = '1' and DDEn = '1' and HDTYPE = '1' then -- FM mode, double density + case ADDER_MSBs is -- Multiplier: 2. + when "000" => PHASE_AMOUNT := "001000"; + when "001" => PHASE_AMOUNT := "000110"; + when "010" => PHASE_AMOUNT := "000100"; + when "011" => PHASE_AMOUNT := "000010"; + when "100" => PHASE_AMOUNT := "100010"; + when "101" => PHASE_AMOUNT := "100100"; + when "110" => PHASE_AMOUNT := "100110"; + when "111" => PHASE_AMOUNT := "101000"; + end case; + elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '0' then -- MFM mode, single density + case ADDER_MSBs is -- Multiplier: 2. + when "000" => PHASE_AMOUNT := "000110"; + when "001" => PHASE_AMOUNT := "000100"; + when "010" => PHASE_AMOUNT := "000011"; + when "011" => PHASE_AMOUNT := "000010"; + when "100" => PHASE_AMOUNT := "100010"; + when "101" => PHASE_AMOUNT := "100011"; + when "110" => PHASE_AMOUNT := "100100"; + when "111" => PHASE_AMOUNT := "100110"; + end case; + elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '1' then -- MFM mode, double density. + case ADDER_MSBs is -- Multiplier: 1. + when "000" => PHASE_AMOUNT := "000100"; + when "001" => PHASE_AMOUNT := "000011"; + when "010" => PHASE_AMOUNT := "000010"; + when "011" => PHASE_AMOUNT := "000001"; + when "100" => PHASE_AMOUNT := "100001"; + when "101" => PHASE_AMOUNT := "100010"; + when "110" => PHASE_AMOUNT := "100011"; + when "111" => PHASE_AMOUNT := "100100"; + end case; + else -- Modify phase amount register: + if PHASE_AMOUNT(4 downto 0) > x"0" then + PHASE_AMOUNT := PHASE_AMOUNT - 1; + end if; + end if; + end if; + -- + if PHASE_AMOUNT(5) = '0' and PHASE_AMOUNT(4 downto 0) > x"0" then + -- PHASE_AMOUNT(5) = '0' means, that the phase leeds. + PHASE_INCREASE <= '1'; -- Speed phase up, accelerate next rollover. + PHASE_DECREASE <= '0'; + elsif PHASE_AMOUNT(5) = '1' and PHASE_AMOUNT(4 downto 0) > x"0" then + -- PHASE_AMOUNT(5) = '1' means, that the phase lags. + PHASE_INCREASE <= '0'; + PHASE_DECREASE <= '1'; -- Speed phase down, delay of next rollover. + else + PHASE_INCREASE <= '0'; + PHASE_DECREASE <= '0'; + end if; + end process PHASE_DECODER; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd new file mode 100644 index 0000000..b365b3d --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd @@ -0,0 +1,232 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Removed CRC_BUSY. + + +library ieee; +use ieee.std_logic_1164.all; + +package WF1772IP_PKG is +-- component declarations: +component WF1772IP_AM_DETECTOR + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + DATA : in bit; + DATA_STRB : in bit; + ID_AM : out bit; + DATA_AM : out bit; + DDATA_AM : out bit + ); +end component; + +component WF1772IP_CONTROL + port( + CLK : in bit; + RESETn : in bit; + A1, A0 : in bit; + RWn : in bit; + CSn : in bit; + DDEn : in bit; + DR : in bit_vector(7 downto 0); + CMD : in std_logic_vector(7 downto 0); + DSR : in std_logic_vector(7 downto 0); + TR : in std_logic_vector(7 downto 0); + SR : in std_logic_vector(7 downto 0); + MO : out bit; + WR_PR : out bit; + SPINUP_RECTYPE : out bit; + SEEK_RNF : out bit; + CRC_ERRFLAG : out bit; + LOST_DATA_TR00 : out bit; + DRQ : out bit; + DRQ_IPn : out bit; + BUSY : out bit; + AM_2_DISK : out bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + CRC_ERR : in bit; + CRC_PRES : out bit; + TR_PRES : out bit; + TR_CLR : out bit; + TR_INC : out bit; + TR_DEC : out bit; + SR_LOAD : out bit; + SR_INC : out bit; + TRACK_NR : out std_logic_vector(7 downto 0); + DR_CLR : out bit; + DR_LOAD : out bit; + SHFT_LOAD_SD : out bit; + SHFT_LOAD_ND : out bit; + CRC_2_DISK : out bit; + DSR_2_DISK : out bit; + FF_2_DISK : out bit; + PRECOMP_EN : out bit; + DATA_STRB : in bit; + DISK_RWn : out bit; + WPRTn : in bit; + TRACK00n : in bit; + IPn : in bit; + DIRC : out bit; + STEP : out bit; + WG : out bit; + INTRQ : out bit + ); +end component; + +component WF1772IP_CRC_LOGIC + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + DISK_RWn : in bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + SD : in bit; + CRC_STRB : in bit; + CRC_2_DISK : in bit; + CRC_PRES : in bit; + CRC_SDOUT : out bit; + CRC_ERR : out bit + ); +end component; + +component WF1772IP_DIGITAL_PLL + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + HDTYPE : in bit; + DISK_RWn : in bit; + RDn : in bit; + PLL_D : out bit; + PLL_DSTRB : out bit + ); +end component; + +component WF1772IP_REGISTERS + port( + CLK : in bit; + RESETn : in bit; + CSn : in bit; + ADR : in bit_vector(1 downto 0); + RWn : in bit; + DATA_IN : in std_logic_vector (7 downto 0); + DATA_OUT : out std_logic_vector (7 downto 0); + DATA_EN : out bit; + CMD : out std_logic_vector(7 downto 0); + SR : out std_logic_vector(7 downto 0); + TR : out std_logic_vector(7 downto 0); + DSR : out std_logic_vector(7 downto 0); + DR : out bit_vector(7 downto 0); + SD_R : in bit; + DATA_STRB : in bit; + DR_CLR : in bit; + DR_LOAD : in bit; + TR_PRES : in bit; + TR_CLR : in bit; + TR_INC : in bit; + TR_DEC : in bit; + TRACK_NR : in std_logic_vector(7 downto 0); + SR_LOAD : in bit; + SR_INC : in bit; + SHFT_LOAD_SD : in bit; + SHFT_LOAD_ND : in bit; + MOTOR_ON : in bit; + WRITE_PROTECT : in bit; + SPINUP_RECTYPE : in bit; + SEEK_RNF : in bit; + CRC_ERRFLAG : in bit; + LOST_DATA_TR00 : in bit; + DRQ : in bit; + DRQ_IPn : in bit; + BUSY : in bit; + DDEn : in bit + ); +end component; + +component WF1772IP_TRANSCEIVER + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + HDTYPE : in bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + SHFT_LOAD_SD : in bit; + DR : in bit_vector(7 downto 0); + PRECOMP_EN : in bit; + AM_TYPE : in bit; + AM_2_DISK : in bit; + CRC_2_DISK : in bit; + DSR_2_DISK : in bit; + FF_2_DISK : in bit; + SR_SDOUT : in std_logic; + CRC_SDOUT : in bit; + WRn : out bit; + PLL_DSTRB : in bit; + PLL_D : in bit; + WDATA : out bit; + DATA_STRB : out bit; + SD_R : out bit + ); +end component; +end WF1772IP_PKG; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd new file mode 100644 index 0000000..7556fe5 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd @@ -0,0 +1,264 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This file models all the five WD1772 registers: DATA-, ---- +---- COMMAND-, SECTOR-, TRACK- and STATUS register as also the ---- +---- shift register. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_REGISTERS is + port( + -- System control: + CLK : in bit; + RESETn : in bit; + + -- Bus interface: + CSn : in bit; + ADR : in bit_vector(1 downto 0); + RWn : in bit; + DATA_IN : in std_logic_vector (7 downto 0); + DATA_OUT : out std_logic_vector (7 downto 0); + DATA_EN : out bit; + + -- FDC data: + CMD : out std_logic_vector(7 downto 0); -- Command register. + SR : out std_logic_vector(7 downto 0); -- Sector register. + TR : out std_logic_vector(7 downto 0); -- Track register. + DSR : out std_logic_vector(7 downto 0); -- Data shift register. + DR : out bit_vector(7 downto 0); -- Data register. + + -- Serial data and clock strobes (in and out): + DATA_STRB : in bit; -- Strobe for the incoming data. + SD_R : in bit; -- Serial data input. + + -- DATA register control: + DR_CLR : in bit; -- Clear. + DR_LOAD : in bit; -- LOAD. + + -- Track register controls: + TR_PRES : in bit; -- Set x"FF". + TR_CLR : in bit; -- Clear. + TR_INC : in bit; -- Increment. + TR_DEC : in bit; -- Decrement. + + -- Sector register control: + TRACK_NR : in std_logic_vector(7 downto 0); + SR_LOAD : in bit; -- Load. + SR_INC : in bit; -- Increment. + + -- Shift register control: + SHFT_LOAD_SD : in bit; + SHFT_LOAD_ND : in bit; + + -- Status register stuff + MOTOR_ON : in bit; + WRITE_PROTECT : in bit; + SPINUP_RECTYPE : in bit; -- Disk is on speed / data mark status. + SEEK_RNF : in bit; -- Seek error / record not found status flag. + CRC_ERRFLAG : in bit; -- CRC status flag. + LOST_DATA_TR00 : in bit; + DRQ : in bit; + DRQ_IPn : in bit; + BUSY : in bit; + + -- Others: + DDEn : in bit + ); +end WF1772IP_REGISTERS; + +architecture BEHAVIOR of WF1772IP_REGISTERS is +-- Remark: In the original data sheet 'WD17X-00' there is the following statement: +-- "After any register is written to, the same register cannot be read from until +-- 16us in MFM or 32us in FMMM have elapsed." If this is a hint for a hardware read +-- lock ... this lock is not implemented in this code. +signal SHIFT_REG : std_logic_vector(7 downto 0); +signal DATA_REG : std_logic_vector(7 downto 0); +signal COMMAND_REG : std_logic_vector(7 downto 0); +signal SECTOR_REG : std_logic_vector(7 downto 0); +signal TRACK_REG : std_logic_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal SD_R_I : std_logic; +begin + -- Type conversion To_Std_Logic: + SD_R_I <= '1' when SD_R = '1' else '0'; + + P_SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if SHFT_LOAD_ND = '1' then + SHIFT_REG <= DATA_REG; -- Load data register stuff. + elsif SHFT_LOAD_SD = '1' and DDEn = '1' then + SHIFT_REG <= DATA_REG; -- Normal data in FM mode. + elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode: + case DATA_REG is + when x"F5" => SHIFT_REG <= x"A1"; -- Special character. + when x"F6" => SHIFT_REG <= x"C2"; -- Special character. + when others => SHIFT_REG <= DATA_REG; -- Normal MFM data. + end case; + elsif DATA_STRB = '1' then -- Shift left during read from disk or write to disk. + SHIFT_REG <= SHIFT_REG(6 downto 0) & SD_R_I; -- for write operation SD_R_I is a dummy. + end if; + end if; + end process P_SHIFTREG; + DSR <= SHIFT_REG; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "11" and RWn = '0' then + DATA_REG <= DATA_IN; -- Write bus data to register + elsif DR_LOAD = '1' and DRQ = '0' then + DATA_REG <= SHIFT_REG; -- Correct data loaded to shift register. + elsif DR_LOAD = '1' and DRQ = '1' then + DATA_REG <= x"00"; -- Dummy byte due to lost data loaded to shift register. + elsif DR_CLR = '1' then + DATA_REG <= (others => '0'); + end if; + end if; + end process DATAREG; + -- Data register buffered for further data processing. + DR <= To_BitVector(DATA_REG); + + SECTORREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SECTOR_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "10" and RWn = '0' and BUSY = '0' then + SECTOR_REG <= DATA_IN; -- Write to register when device is not busy. + elsif SR_LOAD = '1' then + -- Load the track number to the sector register in the type III command + -- 'Read Address'. + SECTOR_REG <= TRACK_NR; + elsif SR_INC = '1' then + SECTOR_REG <= SECTOR_REG + '1'; + end if; + end if; + end process SECTORREG; + SR <= SECTOR_REG; + + TRACKREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TRACK_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "01" and RWn = '0' and BUSY = '0' then + TRACK_REG <= DATA_IN; -- Write to register when device is busy. + elsif TR_PRES = '1' then + TRACK_REG <= (others => '1'); -- Preset the track register. + elsif TR_CLR = '1' then + TRACK_REG <= (others => '0'); -- Reset the track register. + elsif TR_INC = '1' then + TRACK_REG <= TRACK_REG + '1'; -- Increment register contents. + elsif TR_DEC = '1' then + TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents. + end if; + end if; + end process TRACKREG; + TR <= TRACK_REG; + + COMMANDREG: process(RESETn, CLK) + -- The command register is write only. + begin + if RESETn = '0' then + COMMAND_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "00" and RWn = '0' and BUSY = '0' then + COMMAND_REG <= DATA_IN; -- Write to register when device is not busy. + -- Write 'force interrupt' to register even when device is busy: + elsif CSn = '0' and ADR = "00" and RWn = '0' and DATA_IN(7 downto 4) = x"D" then + COMMAND_REG <= DATA_IN; + end if; + end if; + end process COMMANDREG; + CMD <= COMMAND_REG; + + STATUSREG: process(RESETn, CLK) + -- The status register is read only to the data bus. + begin + -- Status register wiring: + if RESETn = '0' then + STATUS_REG <= x"00"; + elsif CLK = '1' and CLK' event then + STATUS_REG(7) <= MOTOR_ON; + STATUS_REG(6) <= WRITE_PROTECT; + STATUS_REG(5) <= SPINUP_RECTYPE; + STATUS_REG(4) <= SEEK_RNF; + STATUS_REG(3) <= CRC_ERRFLAG; + STATUS_REG(2) <= LOST_DATA_TR00; + STATUS_REG(1) <= DRQ_IPn; + STATUS_REG(0) <= BUSY; + end if; + end process STATUSREG; + -- Read from track, sector or data register: + -- The register data after writing to the track register is valid at least + -- after 32us in FM mode and after 16us in MFM mode. + -- Read from status register. This register is read only: + -- Be aware, that the status register data bits 7 to 1 after writing + -- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and + -- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode. + DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else + SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else + DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else + To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0'); + DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0'; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd new file mode 100644 index 0000000..71ef3f3 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd @@ -0,0 +1,154 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is the top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - Test of the FM portion of the code (if there is any need). ---- +---- - Test of the read track command. ---- +---- - Test of the read address command. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to the lack +-- of FM drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma +-- Oksanen for the information. +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. + +library work; +use work.WF1772IP_PKG.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TOP is + port ( + CLK : in bit; -- 16MHz clock! + MRn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA : inout std_logic_vector(7 downto 0); + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks. + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end entity WF1772IP_TOP; + +architecture STRUCTURE of WF1772IP_TOP is +component WF1772IP_TOP_SOC + port ( + CLK : in bit; + RESETn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end component; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +begin + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + + I_1772: WF1772IP_TOP_SOC + port map( + CLK => CLK, + RESETn => MRn, + CSn => CSn, + RWn => RWn, + A1 => A1, + A0 => A0, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + RDn => RDn, + TR00n => TR00n, + IPn => IPn, + WPRTn => WPRTn, + DDEn => DDEn, + HDTYPE => HDTYPE, + MO => MO, + WG => WG, + WD => WD, + STEP => STEP, + DIRC => DIRC, + DRQ => DRQ, + INTRQ => INTRQ + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd new file mode 100644 index 0000000..9cfd111 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd @@ -0,0 +1,333 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - Test of the FM portion of the code (if there is any need). ---- +---- - Test of the read track command. ---- +---- - Test of the read address command. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to the lack +-- of FM drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma Oksanen for the information. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/12/24 WF +-- Bugfixes in the controller due to hanging state machine. +-- Removed CRC_BUSY. +-- + +library work; +use work.WF1772IP_PKG.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TOP_SOC is + port ( + CLK : in bit; -- 16MHz clock! + RESETn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks. + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end entity WF1772IP_TOP_SOC; + +architecture STRUCTURE of WF1772IP_TOP_SOC is +signal DATA_OUT_REG : std_logic_vector(7 downto 0); +signal DATA_EN_REG : bit; +signal CMD_I : std_logic_vector(7 downto 0); +signal DR_I : bit_vector(7 downto 0); +signal DSR_I : std_logic_vector(7 downto 0); +signal TR_I : std_logic_vector(7 downto 0); +signal SR_I : std_logic_vector(7 downto 0); +signal ID_AM_I : bit; +signal DATA_AM_I : bit; +signal DDATA_AM_I : bit; +signal AM_TYPE_I : bit; +signal AM_2_DISK_I : bit; +signal DATA_STRB_I : bit; +signal BUSY_I : bit; +signal DRQ_I : bit; +signal DRQ_IPn_I : bit; +signal LD_TR00_I : bit; +signal SP_RT_I : bit; +signal SEEK_RNF_I : bit; +signal WR_PR_I : bit; +signal MO_I : bit; +signal PLL_DSTRB_I : bit; +signal PLL_D_I : bit; +signal CRC_SD_I : bit; +signal CRC_ERR_I : bit; +signal CRC_PRES_I : bit; +signal CRC_ERRFLAG_I : bit; +signal SD_R_I : bit; +signal CRC_SDOUT_I : bit; +signal SHFT_LOAD_SD_I : bit; +signal SHFT_LOAD_ND_I : bit; +signal WR_In : bit; +signal TR_PRES_I : bit; +signal TR_CLR_I : bit; +signal TR_INC_I : bit; +signal TR_DEC_I : bit; +signal SR_LOAD_I : bit; +signal SR_INC_I : bit; +signal DR_CLR_I : bit; +signal DR_LOAD_I : bit; +signal TRACK_NR_I : std_logic_vector(7 downto 0); +signal CRC_2_DISK_I : bit; +signal DSR_2_DISK_I : bit; +signal FF_2_DISK_I : bit; +signal PRECOMP_EN_I : bit; +signal DISK_RWn_I : bit; +signal WDATA_I : bit; +begin + -- Three state data bus: + DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0'); + DATA_EN <= DATA_EN_REG; + + -- Some signals copied to the outputs: + WD <= not WR_In; + MO <= MO_I; + DRQ <= DRQ_I; + + -- Write deleted data address mark in MFM mode in 'Write Sector' command in + -- case of asserted command bit 0. + AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1'; + + -- The CRC unit is used during read from disk and write to disk. + -- This is the data multiplexer for the data stream to encode. + CRC_SD_I <= SD_R_I when DISK_RWn_I = '1' else WDATA_I; + + I_CONTROL: WF1772IP_CONTROL + port map( + CLK => CLK, + RESETn => RESETn, + A1 => A0, + A0 => A1, + RWn => RWn, + CSn => CSn, + DDEn => DDEn, + DR => DR_I, + CMD => CMD_I, + DSR => DSR_I, + TR => TR_I, + SR => SR_I, + MO => MO_I, + WR_PR => WR_PR_I, + SPINUP_RECTYPE => SP_RT_I, + SEEK_RNF => SEEK_RNF_I, + CRC_ERRFLAG => CRC_ERRFLAG_I, + LOST_DATA_TR00 => LD_TR00_I, + DRQ => DRQ_I, + DRQ_IPn => DRQ_IPn_I, + BUSY => BUSY_I, + AM_2_DISK => AM_2_DISK_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + CRC_ERR => CRC_ERR_I, + CRC_PRES => CRC_PRES_I, + TR_PRES => TR_PRES_I, + TR_CLR => TR_CLR_I, + TR_INC => TR_INC_I, + TR_DEC => TR_DEC_I, + SR_LOAD => SR_LOAD_I, + SR_INC => SR_INC_I, + TRACK_NR => TRACK_NR_I, + DR_CLR => DR_CLR_I, + DR_LOAD => DR_LOAD_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + SHFT_LOAD_ND => SHFT_LOAD_ND_I, + CRC_2_DISK => CRC_2_DISK_I, + DSR_2_DISK => DSR_2_DISK_I, + FF_2_DISK => FF_2_DISK_I, + PRECOMP_EN => PRECOMP_EN_I, + DATA_STRB => DATA_STRB_I, + DISK_RWn => DISK_RWn_I, + WPRTn => WPRTn, + TRACK00n => TR00n, + IPn => IPn, + DIRC => DIRC, + STEP => STEP, + WG => WG, + INTRQ => INTRQ + ); + + I_REGISTERS: WF1772IP_REGISTERS + port map( + CLK => CLK, + RESETn => RESETn, + CSn => CSn, + ADR(1) => A1, + ADR(0) => A0, + RWn => RWn, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT_REG, + DATA_EN => DATA_EN_REG, + CMD => CMD_I, + TR => TR_I, + SR => SR_I, + DSR => DSR_I, + DR => DR_I, + SD_R => SD_R_I, + DATA_STRB => DATA_STRB_I, + DR_CLR => DR_CLR_I, + DR_LOAD => DR_LOAD_I, + TR_PRES => TR_PRES_I, + TR_CLR => TR_CLR_I, + TR_INC => TR_INC_I, + TR_DEC => TR_DEC_I, + TRACK_NR => TRACK_NR_I, + SR_LOAD => SR_LOAD_I, + SR_INC => SR_INC_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + SHFT_LOAD_ND => SHFT_LOAD_ND_I, + MOTOR_ON => MO_I, + WRITE_PROTECT => WR_PR_I, + SPINUP_RECTYPE => SP_RT_I, + SEEK_RNF => SEEK_RNF_I, + CRC_ERRFLAG => CRC_ERRFLAG_I, + LOST_DATA_TR00 => LD_TR00_I, + DRQ => DRQ_I, + DRQ_IPn => DRQ_IPn_I, + BUSY => BUSY_I, + DDEn => DDEn + ); + + I_DIGITAL_PLL: WF1772IP_DIGITAL_PLL + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + HDTYPE => HDTYPE, + DISK_RWn => DISK_RWn_I, + RDn => RDn, + PLL_D => PLL_D_I, + PLL_DSTRB => PLL_DSTRB_I + ); + + I_AM_DETECTOR: WF1772IP_AM_DETECTOR + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + DATA => PLL_D_I, + DATA_STRB => PLL_DSTRB_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I + ); + + I_CRC_LOGIC: WF1772IP_CRC_LOGIC + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + DISK_RWn => DISK_RWn_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + SD => CRC_SD_I, + CRC_STRB => DATA_STRB_I, + CRC_2_DISK => CRC_2_DISK_I, + CRC_PRES => CRC_PRES_I, + CRC_SDOUT => CRC_SDOUT_I, + CRC_ERR => CRC_ERR_I + ); + + I_TRANSCEIVER: WF1772IP_TRANSCEIVER + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + HDTYPE => HDTYPE, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + DR => DR_I, + PRECOMP_EN => PRECOMP_EN_I, + AM_TYPE => AM_TYPE_I, + AM_2_DISK => AM_2_DISK_I, + CRC_2_DISK => CRC_2_DISK_I, + DSR_2_DISK => DSR_2_DISK_I, + FF_2_DISK => FF_2_DISK_I, + SR_SDOUT => DSR_I(7), + CRC_SDOUT => CRC_SDOUT_I, + WRn => WR_In, + WDATA => WDATA_I, + PLL_DSTRB => PLL_DSTRB_I, + PLL_D => PLL_D_I, + DATA_STRB => DATA_STRB_I, + SD_R => SD_R_I + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd new file mode 100644 index 0000000..c836716 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd @@ -0,0 +1,517 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The transceiver unit contains on the one hand the receiver ---- +---- part which strips off the clock signal from the data stream ---- +---- and on the other hand the transmitter unit which provides in ---- +---- the different modes (FM and MFM) all functions which are ---- +---- necessary to send data, CRC bytes, 'FF', '00' or the address ---- +---- marks. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- MFM_In and MASK_SHFT have now synchronous reset to meet preset requirement. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TRANSCEIVER is + port( + -- System control + CLK : in bit; -- must be 16MHz + RESETn : in bit; + + -- Data and Control: + HDTYPE : in bit; -- Floppy type HD or DD. + DDEn : in bit; -- Double density select (FM or MFM). + ID_AM : in bit; -- ID addressmark strobe. + DATA_AM : in Bit; -- Data addressmark strobe. + DDATA_AM : in Bit; -- Deleted data addressmark strobe. + SHFT_LOAD_SD : in bit; -- Indication for shift register load time. + DR : in bit_vector(7 downto 0); -- Content of the data register. + + -- Data strobes: + PLL_DSTRB : in bit; -- Clock strobe for RD serial data input. + DATA_STRB : buffer bit; + + -- Data strobe and data for the CRC during write operation: + WDATA : buffer bit; + + -- Encoder (logic to disk): + PRECOMP_EN : in bit; -- control signal for MFM write precompensation. + AM_TYPE : in bit; -- Write deleted address mark in MFM mode when 0. + AM_2_DISK : in bit; + DSR_2_DISK : in bit; + FF_2_DISK : in bit; + CRC_2_DISK : in bit; + SR_SDOUT : in std_logic; -- encoder's data input from the shift register (serial). + CRC_SDOUT : in bit; -- encoder's data input from the CRC unit (serial). + WRn : out bit; -- write output for the MFM drive containing clock and data. + + -- Decoder (disk to logic): + PLL_D : in bit; -- Serial data input. + SD_R : out bit -- Serial (decoded) data output. + ); +end WF1772IP_TRANSCEIVER; + +architecture BEHAVIOR of WF1772IP_TRANSCEIVER is +type MFM_STATES is (A_00, B_01, C_10); +type PRECOMP_VALUES is (EARLY, NOMINAL, LATE); +type DEC_STATES is (CLK_PHASE, DATA_PHASE); + +signal MFM_STATE : MFM_STATES; +signal NEXT_MFM_STATE : MFM_STATES; +signal PRECOMP : PRECOMP_VALUES; +signal DEC_STATE : DEC_STATES; +signal NEXT_DEC_STATE : DEC_STATES; + +signal FM_In : bit; + +signal CLKMASK : bit; -- Control for suppression of FM clock transitions. + +signal MFM_10_STRB : bit; +signal MFM_01_STRB : bit; + +signal WR_CNT : std_logic_vector(3 downto 0); +signal MFM_In : bit; + +signal AM_SHFT : bit_vector(31 downto 0); + +begin + -- ####################### encoder stuff ########################### + ADRMARK: process(RESETn, CLK) + -- This process provides the address mark data for both FM and MFM in + -- write to disk mode. In FM only one byte is written where in MFM + -- 3 sync bytes x"A1" and one data address mark is written. + -- In this process only the data address mark is provided. The only way + -- writing the ID address mark is the write track command. + begin + if RESETn = '0' then + AM_SHFT <= (others => '0'); + elsif CLK = '1' and CLK' event then + if AM_2_DISK = '1' and DATA_STRB = '1' then + AM_SHFT <= AM_SHFT (30 downto 0) & '0'; -- Shift out. + elsif AM_2_DISK = '0' and DDEn = '1' and AM_TYPE = '0' then -- FM mode. + AM_SHFT <= x"F8000000"; -- Load deleted FM address mark. + elsif AM_2_DISK = '0' and DDEn = '1' and AM_TYPE = '1' then -- FM mode. + AM_SHFT <= x"FB000000"; -- Load normal FM address mark. + elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '0' then -- MFM mode deleted data mark. + AM_SHFT <= x"A1A1A1F8"; -- Load MFM syncs and address mark. + elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '1' then -- Default: MFM mode normal data mark. + AM_SHFT <= x"A1A1A1FB"; -- Load MFM syncs and address mark. + end if; + end if; + end process ADRMARK; + + -- Input multiplexer: + WDATA <= AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data. + To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data. + CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data. + '1' when FF_2_DISK = '1' else '0'; -- Write zeros is default. + + -- Output multiplexer: + WRn <= '0' when FM_In = '0' and DDEn = '1' else -- FM portion. + '0' when MFM_In = '0' and DDEn = '0' else '1'; -- MFM portion and default. + + CLK_MASK: process(CLK) + -- This part of software controls the suppression of the clock pulses + -- during transmission of several FM special characters. During writing + -- 'normal' data to the disk, only 8 mask bits of the shift register are + -- used. During writing MFM sync and address mark bits, the register is + -- used with 32 mask bits. + variable MASK_SHFT : bit_vector(23 downto 0); + variable LOCK : boolean; + begin + if CLK = '1' and CLK' event then + if RESETn = '0' then + MASK_SHFT := (others => '1'); + LOCK := false; + -- Load the mask shift register just in time when the shift register is + -- loaded with valid data from the data register. + elsif SHFT_LOAD_SD = '1' and DDEn = '1' then -- FM mode. + case DR is + when x"F8" | x"F9" | x"FA" | x"FB" | x"FE" => MASK_SHFT := x"C7FFFF"; + when x"FC" => MASK_SHFT := x"D7FFFF"; + when x"F5" | x"F6" => MASK_SHFT := (others => '0'); -- Not allowed. + when others => MASK_SHFT := x"FFFFFF"; -- Normal data. + end case; + elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode. + case DR is + when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5. + when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4. + when others => MASK_SHFT := x"FFFFFF"; -- Normal data. + end case; + elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode. + MASK_SHFT := x"C7FFFF"; -- Load just once per AM_2_DISK rising edge. + LOCK := true; + elsif AM_2_DISK = '1' and DDEn = '0' and LOCK = false then -- MFM mode. + MASK_SHFT := x"FBFBFB"; -- Three syncs with suppressed clock pulse then transparent mask. + LOCK := true; + elsif DATA_STRB = '1' then -- shift as long as transmission is active + -- The Shift register is shifted left. After shifting the clockmasks out it is + -- transparent due to the '1's filled up from the left. + MASK_SHFT := MASK_SHFT(22 downto 0) & '1'; -- Shift left. + elsif AM_2_DISK = '0' then + LOCK := false; -- Release the lock after address mark has been written. + end if; + end if; + CLKMASK <= MASK_SHFT(23); + end process CLK_MASK; + + FM_ENCODER: process (RESETn, DATA_STRB, CLK) + -- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles + -- per FM bit. + -- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles + -- per FM bit. + -- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies. + -- This process provides the FM encoded signal. The first pulse is in any case the clock + -- pulse and the second pulse is due to data. The FM encoding is very simple and therefore + -- self explaining. + variable CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + FM_In <= '1'; + CNT := x"00"; + elsif CLK = '1' and CLK' event then + -- In case of HD type floppies the counter reaches a value of b"0100000" + -- In case of DD type floppies the counter reaches a value of b"1000000" + if DATA_STRB = '1' then + CNT := x"00"; + else + CNT := CNT + '1'; + end if; + -- The flux reversal pulses are centered between the DATA_STRB pulses. + -- In detail: the clock pulse appears in the middle of the first half + -- of the DATA_STRB period and the data pulse appears in the middle of + -- the second half. + case HDTYPE is + when '0' => -- DD type floppies: + if CNT > "00010101" and CNT <= "00101011" then + FM_In <= not CLKMASK; -- FM clock. + elsif CNT > "01010101" and CNT <= "01101011" then + FM_In <= not WDATA; -- FM data. + else + FM_In <= '1'; + end if; + when '1' => -- HD type floppies: + if CNT > "00001010" and CNT <= "00010110" then + FM_In <= not CLKMASK; -- FM clock. + elsif CNT > "00101010" and CNT <= "00110110" then + FM_In <= not WDATA; -- FM data. + else + FM_In <= '1'; + end if; + end case; + end if; + end process FM_ENCODER; + + MFM_ENCODE_REG: process(RESETn, CLK) + -- This process is the first portion of the more complicated MFM encoder. It can be interpreted + -- as a Moore machine. This part is the current state register. + begin + if RESETn = '0' then + MFM_STATE <= A_00; + elsif CLK = '1' and CLK' event then + MFM_STATE <= NEXT_MFM_STATE; + end if; + end process MFM_ENCODE_REG; + + MFM_ENCODE_LOGIC: process(MFM_STATE, WDATA, DATA_STRB) + -- Rules for Encoding: + -- transitions are never located at the mid point of a 'zero'. + -- transistions are always located at the mid point of a '1'. + -- no transitions at the borders of a '1'. + -- transitions appear between two adjacent 'zeros'. + -- states are as follows: + -- A_00: idle state, no transition. + -- B_01: transistion between the MFM clock edges. + -- C_10: transition on the leading MFM clock edges. + -- The timing of the MFM output is done in the process MFM_WR_OUT. + begin + case MFM_STATE is + when A_00 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= C_10; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= A_00; -- Stay, if there is no strobe. + end if; + when C_10 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= C_10; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= C_10; -- Stay, if there is no strobe. + end if; + when B_01 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= A_00; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= B_01; -- Stay, if there is no strobe. + end if; + end case; + end process MFM_ENCODE_LOGIC; + + MFM_PRECOMPENSATION: process(RESETn, CLK) + -- The write pattern is adjusted in the MFM write timing process as follows: + -- after DATA_STRB (the duty cycle of this strobe is exactly one CLK) the + -- incoming data is bufferd in WRITEPATTERN. After the following DATA_STRB + -- the WDATA is shifted through WRITEPATTERN. After further DATA_STRBs the + -- WRITEPATTERN consists of previous, current and next WDATA like this: + -- WRITEPATTERN(3) is the second previous WDATA. + -- WRITEPATTERN(2) is the previous WDATA. + -- WRITEPATTERN(1) is the current WDATA to be sent. + -- WRITEPATTERN(0) is the next WDATA to be sent. + variable WRITEPATTERN : bit_vector(3 downto 0); + begin + if RESETn = '0' then + PRECOMP <= NOMINAL; + WRITEPATTERN := "0000"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + WRITEPATTERN := WRITEPATTERN(2 downto 0) & WDATA; -- shift left + end if; + if PRECOMP_EN = '0' then + PRECOMP <= NOMINAL; -- no precompensation + else + case WRITEPATTERN is + when "1110" | "0110" => PRECOMP <= EARLY; + when "1011" | "0011" => PRECOMP <= LATE; + when "0001" => PRECOMP <= EARLY; + when "1000" => PRECOMP <= LATE; + when others => PRECOMP <= NOMINAL; + end case; + end if; + end if; + end process MFM_PRECOMPENSATION; + + MFM_STROBES: process (RESETn, DATA_STRB, CLK) + -- For the MFM frequency is 250 kBps for DD type floppies, there are 64 + -- 16 MHz clock cycles per MFM bit and for HD type floppies, which have + -- 500 kBps there are 32 16MHz clock pulses for one MFM bit. + -- The MFM state machine (Moore) switches on the DATA_STRB. + -- During one cycle there are the two further strobes MFM_10_STRB and + -- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT. + -- The strobes are centered in the middle of the first half and in the + -- middle of the second half of the DATA_STRB cycle. + variable CNT : std_logic_vector(5 downto 0); + begin + if RESETn = '0' then + CNT := "000000"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + CNT := (others => '0'); + else + CNT := CNT + '1'; + end if; + if HDTYPE = '1' then + case CNT is + -- encoder timing for MFM and HD type floppies. + when "000100" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half. + when "010100" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half. + when others => MFM_10_STRB <= '0'; MFM_01_STRB <= '0'; + end case; + else + case CNT is + -- encoder timing for MFM and DD type floppies. + when "001010" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half. + when "101000" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half. + when others => MFM_10_STRB <= '0'; MFM_01_STRB <= '0'; + end case; + end if; + end if; + end process MFM_STROBES; + + -- MFM_WR_TIMING generates the timing for the write pulses which are + -- required by a MFM device like floppy disk drive. The pulse timing + -- meets the timing of the MFM data with pulse width of 700ns +/- 100ns + -- depending on write precompensation. + -- The original WD1772 (CLK = 8MHz) data timing was as follows: + -- The output is asserted as long as CNT is active; in detail + -- this are 4,5; 5,5 or 6,5 CLK cycles depending on the write + -- precompensation. + -- The new design which works with a 16MHz clock requires the following + -- timing: 9; 11 or 13 CLK cycles depending on the writeprecompensation + -- for DD floppies and 5; 6 or 7 CLK cycles depending on the write + -- precompensation for HD floppies. + -- To meet the timing requirements of half clocks + -- the WRn is controlled by the following three processes where the one + -- syncs on the positive clock edge and the other on the negative. + -- For more information on the WTn timing see the datasheet of the + -- WD177x floppy disc controller. + + MFM_WR_TIMING: process(RESETn, CLK) + variable CLKMASK_MFM : bit; + begin + if RESETn = '0' then + WR_CNT <= x"F"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + -- The CLKMASK_MFM is synchronised to DATA_STRB. This brings one strobe latency. + -- The timing in connection with the data is correct because the MFM encoder state machine + -- causes the data to be 1 DATA_STRB late too. + CLKMASK_MFM := CLKMASK; + end if; + if MFM_STATE = C_10 and MFM_10_STRB = '1' and CLKMASK_MFM = '1' then + WR_CNT <= x"0"; + elsif MFM_STATE = B_01 and MFM_01_STRB = '1' then + WR_CNT <= x"0"; + elsif WR_CNT < x"F" then + WR_CNT <= WR_CNT + '1'; + end if; + end if; + end process MFM_WR_TIMING; + + MFM_WR_OUT: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + MFM_In <= '1'; + else + case HDTYPE is + when '1' => -- HD type. + if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"9" then + MFM_In <= '0'; -- 9,0 clock cycles for WRn --> early timing + elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"8" then + MFM_In <= '0'; -- 8,0 clock cycles for WRn --> nominal timing + elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"7" then + MFM_In <= '0'; -- 7,0 clock cycles for WRn --> late timing + else + MFM_In <= '1'; + end if; + when '0' => -- DD type. + if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"D" then + MFM_In <= '0'; -- 13,0 clock cycles for WRn --> early timing + elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"B" then + MFM_In <= '0'; -- 11,0 clock cycles for WRn --> nominal timing + elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"9" then + MFM_In <= '0'; -- 9,0 clock cycles for WRn --> late timing + else + MFM_In <= '1'; + end if; + end case; + end if; + end process MFM_WR_OUT; + + -- ####################### Decoder stuff ########################### + -- The decoding of the serial FM or MFM encoded data stream + -- is done in the following two processes (Moore machine). + -- The decoder works in principle like a simple toggle Flip-Flop. + -- It is important to synchronise it in a way, that the clock + -- pulses are separated from the data pulses. The principle + -- works for both FM and MFM data due to the digital phase + -- locked loop, which delivers the serial data and the clock + -- strobe. In general this decoder can be understood as the + -- data separator where the digital phase locked loop provides + -- the FM or the MFM decoding. The data separation lives from + -- the fact, that FM and also MFM encoded signals consist of a + -- mixture of alternating data and clock pulses. + -- FM works as follows: + -- every first pulse of the FM signal is a clock pulse and every + -- second pulse is a logic '1' of the data. A missing second + -- pulse represents a logic '0' of the data. + -- MFM works as follows: + -- every first pulse of the MFM signal is a clock pulse. The coding + -- principle causes clock pulses to be absent in some conditions. + -- Every second pulse is a logic '1' of the data. A missing second + -- pulse represents a logic '0' of the data. + -- So FM and MFM compared, the data is represented directly by the + -- second pulses and the data separator has to look only for these. + -- The missing MFM clock pulses do not cause a problem because the + -- digital PLL used in conjunction with this data separator fills + -- up the clock pulses and delivers a PLL_DSTRB containing aequidistant + -- clock strobes and data strobes. + + DEC_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + DEC_STATE <= CLK_PHASE; + elsif CLK = '1' and CLK' event then + DEC_STATE <= NEXT_DEC_STATE; + end if; + end process DEC_REG; + + DEC_LOGIC: process(DEC_STATE, ID_AM, DATA_AM, DDATA_AM, PLL_DSTRB, PLL_D) + begin + case DEC_STATE is + when CLK_PHASE => + if PLL_DSTRB = '1' then + NEXT_DEC_STATE <= DATA_PHASE; + else + NEXT_DEC_STATE <= CLK_PHASE; + end if; + DATA_STRB <= '0'; -- Inactive during clock pulse time. + SD_R <= '0'; -- Inactive during clock pulse time. + when DATA_PHASE => + if ID_AM = '1' or DATA_AM = '1' or DDATA_AM = '1' then + -- Here the state machine is synchronised + -- to separate data and clock pulses correctly. + NEXT_DEC_STATE <= CLK_PHASE; + elsif PLL_DSTRB = '1' then + NEXT_DEC_STATE <= CLK_PHASE; + else + NEXT_DEC_STATE <= DATA_PHASE; + end if; + -- During the data phase valid data appears at SD. + -- The data is valid during DATA_STRB. + DATA_STRB <= PLL_DSTRB; + SD_R <= PLL_D; + end case; + end process DEC_LOGIC; +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd new file mode 100644 index 0000000..7660aa2 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd @@ -0,0 +1,141 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This are the SUSKA MFP IP core's general purpose I/Os. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_GPIO is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Timer controls: + AER_4 : out bit; + AER_3 : out bit; + + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_OUT_EN : buffer bit_vector(7 downto 0); + GP_INT : out bit_vector(7 downto 0) + ); +end entity WF68901IP_GPIO; + +architecture BEHAVIOR of WF68901IP_GPIO is +signal GPDR : bit_vector(7 downto 0); +signal DDR : bit_vector(7 downto 0); +signal AER : bit_vector(7 downto 0); +signal GPDR_I : bit_vector(7 downto 0); +begin + -- These two bits control the timers A and B pulse width operation and the + -- timers A and B event count operation. + AER_4 <= AER(4); + AER_3 <= AER(3); + -- This statement provides 8 XOR units setting the desired interrupt polarity. + -- While the level control is done here, the edge triggering is provided by + -- the interrupt control hardware. The level control is individually for each + -- GPIP port pin. The interrupt edge trigger unit must operate in any case on + -- the low to high transistion of the respective port pin. + GP_INT <= AER xnor GPIP_IN; + + GPIO_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + GPDR <= (others => '0'); + DDR <= (others => '0'); + AER <= (others => '0'); + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "00000" => GPDR <= DATA_IN; + when "00001" => AER <= DATA_IN; + when "00010" => DDR <= DATA_IN; + when others => null; + end case; + end if; + end if; + end process GPIO_REGISTERS; + GPIP_OUT <= GPDR; -- Port outputs. + GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP. + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0'; + DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else + AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else + GPDR_I when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00000" else (others => '0'); + + P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR) + -- Read back control: Read the port pins, if the data direction is configured as input. + -- Read the respective GPDR register bit, if the data direction is configured as output. + begin + for i in 7 downto 0 loop + if GPIP_OUT_EN(i) = '1' then -- Port is configured output. + GPDR_I(i) <= GPDR(i); + else + GPDR_I(i) <= GPIP_IN(i); -- Port is configured input. + end if; + end loop; + end process P_GPDR; +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd new file mode 100644 index 0000000..91417f8 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd @@ -0,0 +1,391 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core interrupt logic file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/06/03 WF +-- Fixed Pending register logic. +-- Revision 2K9A 2009/06/20 WF +-- Fixed interrupt polarity for TA_I and TB_I. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_INTERRUPTS is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + + -- Interrupt sources: + GP_INT : in bit_vector(7 downto 0); + + AER_4 : in bit; + AER_3 : in bit; + TAI : in bit; + TBI : in bit; + TA_PWM : in bit; + TB_PWM : in bit; + TIMER_A_INT : in bit; + TIMER_B_INT : in bit; + TIMER_C_INT : in bit; + TIMER_D_INT : in bit; + + RCV_ERR : in bit; + TRM_ERR : in bit; + RCV_BUF_F : in bit; + TRM_BUF_E : in bit + ); +end entity WF68901IP_INTERRUPTS; + +architecture BEHAVIOR of WF68901IP_INTERRUPTS is +-- Interrupt state machine: +type INT_STATES is (SCAN, REQUEST, VECTOR_OUT); +signal INT_STATE : INT_STATES; +-- The registers: +signal IERA : bit_vector(7 downto 0); +signal IERB : bit_vector(7 downto 0); +signal IPRA : bit_vector(7 downto 0); +signal IPRB : bit_vector(7 downto 0); +signal ISRA : bit_vector(7 downto 0); +signal ISRB : bit_vector(7 downto 0); +signal IMRA : bit_vector(7 downto 0); +signal IMRB : bit_vector(7 downto 0); +signal VR : bit_vector(7 downto 3); +-- Interconnect: +signal VECT_NUMBER : bit_vector(7 downto 0); +signal INT_SRC : bit_vector(15 downto 0); +signal INT_SRC_EDGE : bit_vector(15 downto 0); +signal INT_ENA : bit_vector(15 downto 0); +signal INT_MASK : bit_vector(15 downto 0); +signal INT_PENDING : bit_vector(15 downto 0); +signal INT_SERVICE : bit_vector(15 downto 0); +signal INT_PASS : bit_vector(15 downto 0); +signal INT_OUT : bit_vector(15 downto 0); +signal GP_INT_4 : bit; +signal GP_INT_3 : bit; +begin + -- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin. + -- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated + -- to timer A and timer B. + -- The xor logic provides polarity control for the interrupt transition. Be aware, + -- that the PWM signals cause an interrupt on the opposite transition like the + -- respective GPIP port pins (with the same AER settings). + --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4; + --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3; + GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct. + GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3; + + + -- Interrupt source priority sorted (15 = highest): + INT_SRC <= GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & + GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0); + + INT_ENA <= IERA & IERB; + INT_MASK <= IMRA & IMRB; + INT_PENDING <= IPRA & IPRB; + INT_SERVICE <= ISRA & ISRB; + INT_OUT <= INT_PENDING and INT_MASK; -- Masking: + + -- Enable the daisy chain, if there is no pending interrupt and + -- the interrupt state machine is not in service. + IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1'; + + -- Interrupt request: + IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1'; + + EDGE_ENA: process(RESETn, CLK) + -- These are the 16 edge detectors of the 16 interrupt input sources. This + -- process also provides the disabling or enabling via the IERA and IERB registers. + variable LOCK : bit_vector(15 downto 0); + begin + if RESETn = '0' then + INT_SRC_EDGE <= x"0000"; + LOCK := x"0000"; + elsif CLK = '1' and CLK' event then + for i in 15 downto 0 loop + if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then + LOCK(i) := '1'; + INT_SRC_EDGE(i) <= '1'; + elsif INT_SRC(i) = '0' then + LOCK(i) := '0'; + INT_SRC_EDGE(i) <= '0'; + else + INT_SRC_EDGE(i) <= '0'; + end if; + end loop; + end if; + end process EDGE_ENA; + + INT_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + IERA <= (others => '0'); + IERB <= (others => '0'); + IPRA <= (others => '0'); + IPRB <= (others => '0'); + ISRA <= (others => '0'); + ISRB <= (others => '0'); + IMRA <= (others => '0'); + IMRB <= (others => '0'); + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "00011" => IERA <= DATA_IN; -- Enable A. + when "00100" => IERB <= DATA_IN; -- Enable B. + when "00101" => + -- Only a '0' can be written to the pending register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + IPRA(i) <= '0'; -- Pending A. + end if; + end loop; + when "00110" => + -- Only a '0' can be written to the pending register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + IPRB(i) <= '0'; -- Pending B. + end if; + end loop; + when "00111" => + -- Only a '0' can be written to the in service register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + ISRA(i) <= '0'; -- In Service A. + end if; + end loop; + when "01000" => + -- Only a '0' can be written to the in service register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + ISRB(i) <= '0'; -- In Service B. + end if; + end loop; + when "01001" => IMRA <= DATA_IN; -- Mask A. + when "01010" => IMRB <= DATA_IN; -- Mask B. + when "01011" => VR <= DATA_IN(7 downto 3); -- Vector register. + when others => null; + end case; + end if; + + -- Pending register: + -- set and clear bit logic. + for i in 15 downto 8 loop + if INT_SRC_EDGE(i) = '1' then + IPRA(i-8) <= '1'; + elsif INT_ENA(i) = '0' then + IPRA(i-8) <= '0'; -- Clear by disabling the channel. + elsif INT_PASS(i) = '1' then + IPRA(i-8) <= '0'; -- Clear by passing the interrupt. + end if; + end loop; + for i in 7 downto 0 loop + if INT_SRC_EDGE(i) = '1' then + IPRB(i) <= '1'; + elsif INT_ENA(i) = '0' then + IPRB(i) <= '0'; -- Clear by disabling the channel. + elsif INT_PASS(i) = '1' then + IPRB(i) <= '0'; -- Clear by passing the interrupt. + end if; + end loop; + + -- In-Service register: + -- Set bit logic, VR(3) is the service register enable. + for i in 15 downto 8 loop + if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then + ISRA(i-8) <= '1'; + end if; + end loop; + for i in 7 downto 0 loop + if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then + ISRB(i) <= '1'; + end if; + end loop; + end if; + end process INT_REGISTERS; + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else '1' when INT_STATE = VECTOR_OUT else '0'; + + DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else + IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else + IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else + IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else + ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else + ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else + IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else + IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else + VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else + VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00"; + + P_INT_STATE : process(RESETn, CLK) + begin + if RESETn = '0' then + INT_STATE <= SCAN; + elsif CLK = '1' and CLK' event then + case INT_STATE is + when SCAN => + INT_PASS <= x"0000"; + -- Automatic End of Interrupt mode. Service register disabled. + -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized + -- vector number (VR(7 downto 4) = x"0"). + if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then + INT_STATE <= REQUEST; -- Non masked interrupt is pending. + -- The following 16 are the Software end of interrupt mode. Service register enabled. + -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized + -- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized. + elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then + if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then + INT_STATE <= REQUEST; + elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then + INT_STATE <= REQUEST; + elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then + INT_STATE <= REQUEST; + elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then + INT_STATE <= REQUEST; + else + INT_STATE <= SCAN; -- Wait for interrupt. + end if; + else + INT_STATE <= SCAN; + end if; + when REQUEST => + if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode. + INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending. + if INT_OUT(15) = '1' then + INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7. + elsif INT_OUT(14) = '1' then + INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6. + elsif INT_OUT(13) = '1' then + INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A. + elsif INT_OUT(12) = '1' then + INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full. + elsif INT_OUT(11) = '1' then + INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error. + elsif INT_OUT(10) = '1' then + INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty. + elsif INT_OUT(9) = '1' then + INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error. + elsif INT_OUT(8) = '1' then + INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B. + elsif INT_OUT(7) = '1' then + INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5. + elsif INT_OUT(6) = '1' then + INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4. + elsif INT_OUT(5) = '1' then + INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C. + elsif INT_OUT(4) = '1' then + INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D. + elsif INT_OUT(3) = '1' then + INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3. + elsif INT_OUT(2) = '1' then + INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2. + elsif INT_OUT(1) = '1' then + INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1. + elsif INT_OUT(0) = '1' then + INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0. + end if; + -- Polled interrupt mode: End of interrupt by writing to the pending registers. + elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then + INT_STATE <= SCAN; + else + INT_STATE <= REQUEST; -- Wait. + end if; + when VECTOR_OUT => + INT_PASS <= x"0000"; + if DSn = '1' or IACKn = '1' then + INT_STATE <= SCAN; -- Finished. + else + INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector. + end if; + end case; + end if; + end process P_INT_STATE; +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd new file mode 100644 index 0000000..73c0cdc --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd @@ -0,0 +1,263 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package WF68901IP_PKG is +component WF68901IP_USART_TOP + port ( CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + RX_ERR_INT : out bit; + RX_BUFF_INT : out bit; + TX_ERR_INT : out bit; + TX_BUFF_INT : out bit; + RRn : out bit; + TRn : out bit + ); +end component; + +component WF68901IP_USART_CTRL + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + RX_SAMPLE : in bit; + RX_DATA : in bit_vector(7 downto 0); + TX_DATA : out bit_vector(7 downto 0); + SCR_OUT : out bit_vector(7 downto 0); + BF : in bit; + BE : in bit; + FE : in bit; + OE : in bit; + UE : in bit; + PE : in bit; + M_CIP : in bit; + FS_B : in bit; + TX_END : in bit; + CL : out bit_vector(1 downto 0); + ST : out bit_vector(1 downto 0); + FS_CLR : out bit; + RSR_READ : out bit; + TSR_READ : out bit; + UDR_READ : out bit; + UDR_WRITE : out bit; + LOOPBACK : out bit; + SDOUT_EN : out bit; + SD_LEVEL : out bit; + CLK_MODE : out bit; + RE : out bit; + TE : out bit; + P_ENA : out bit; + P_EOn : out bit; + SS : out bit; + BR : out bit + ); +end component; + +component WF68901IP_USART_TX + port ( + CLK : in bit; + RESETn : in bit; + SCR : in bit_vector(7 downto 0); + TX_DATA : in bit_vector(7 downto 0); + SDATA_OUT : out bit; + TXCLK : in bit; + CL : in bit_vector(1 downto 0); + ST : in bit_vector(1 downto 0); + TE : in bit; + BR : in bit; + P_ENA : in bit; + P_EOn : in bit; + UDR_WRITE : in bit; + TSR_READ : in bit; + CLK_MODE : in bit; + TX_END : out bit; + UE : out bit; + BE : out bit + ); +end component; + +component WF68901IP_USART_RX + port ( + CLK : in bit; + RESETn : in bit; + SCR : in bit_vector(7 downto 0); + RX_SAMPLE : out bit; + RX_DATA : out bit_vector(7 downto 0); + RXCLK : in bit; + SDATA_IN : in bit; + CL : in bit_vector(1 downto 0); + ST : in bit_vector(1 downto 0); + P_ENA : in bit; + P_EOn : in bit; + CLK_MODE : in bit; + RE : in bit; + FS_CLR : in bit; + SS : in bit; + RSR_READ : in bit; + UDR_READ : in bit; + M_CIP : out bit; + FS_B : out bit; + BF : out bit; + OE : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF68901IP_INTERRUPTS + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + GP_INT : in bit_vector(7 downto 0); + AER_4 : in bit; + AER_3 : in bit; + TAI : in bit; + TBI : in bit; + TA_PWM : in bit; + TB_PWM : in bit; + TIMER_A_INT : in bit; + TIMER_B_INT : in bit; + TIMER_C_INT : in bit; + TIMER_D_INT : in bit; + RCV_ERR : in bit; + TRM_ERR : in bit; + RCV_BUF_F : in bit; + TRM_BUF_E : in bit + ); +end component; + +component WF68901IP_GPIO + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + AER_4 : out bit; + AER_3 : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_OUT_EN : out bit_vector(7 downto 0); + GP_INT : out bit_vector(7 downto 0) + ); +end component; + +component WF68901IP_TIMERS + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + XTAL1 : in bit; + TAI : in bit; + TBI : in bit; + AER_4 : in bit; + AER_3 : in bit; + TA_PWM : out bit; + TB_PWM : out bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + TIMER_A_INT : out bit; + TIMER_B_INT : out bit; + TIMER_C_INT : out bit; + TIMER_D_INT : out bit + ); +end component; + +end WF68901IP_PKG; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd new file mode 100644 index 0000000..b339af5 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd @@ -0,0 +1,533 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core timers logic file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8A 2008/02/29 WF +-- Fixed a serious prescaler bug. +-- Revision 2K9A 20090620 WF +-- Introduced timer readback registers. +-- TIMER_x_INT is now a strobe. +-- Minor improvements. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TIMERS is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + AER_4 : in bit; + AER_3 : in bit; + TA_PWM : out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic). + TB_PWM : out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic). + TAO : buffer bit; + TBO : buffer bit; + TCO : buffer bit; + TDO : buffer bit; + TIMER_A_INT : out bit; + TIMER_B_INT : out bit; + TIMER_C_INT : out bit; + TIMER_D_INT : out bit + ); +end entity WF68901IP_TIMERS; + +architecture BEHAVIOR of WF68901IP_TIMERS is +signal XTAL1_S : bit; +signal XTAL_STRB : bit; +signal TACR : bit_vector(4 downto 0); -- Timer A control register. +signal TBCR : bit_vector(4 downto 0); -- Timer B control register. +signal TCDCR : bit_vector(5 downto 0); -- Timer C and D control register. +signal TADR : bit_vector(7 downto 0); -- Timer A data register. +signal TBDR : bit_vector(7 downto 0); -- Timer B data register. +signal TCDR : bit_vector(7 downto 0); -- Timer C data register. +signal TDDR : bit_vector(7 downto 0); -- Timer D data register. +signal TIMER_A : std_logic_vector(7 downto 0); -- Timer A count register. +signal TIMER_B : std_logic_vector(7 downto 0); -- Timer B count register. +signal TIMER_C : std_logic_vector(7 downto 0); -- Timer C count register. +signal TIMER_D : std_logic_vector(7 downto 0); -- Timer D count register. +signal TIMER_R_A : bit_vector(7 downto 0); -- Timer A readback register. +signal TIMER_R_B : bit_vector(7 downto 0); -- Timer B readback register. +signal TIMER_R_C : bit_vector(7 downto 0); -- Timer C readback register. +signal TIMER_R_D : bit_vector(7 downto 0); -- Timer D readback register. +signal A_CNTSTRB : bit; +signal B_CNTSTRB : bit; +signal C_CNTSTRB : bit; +signal D_CNTSTRB : bit; +signal TAI_I : bit; +signal TBI_I : bit; +signal TAI_STRB : bit; -- Strobe for the event counter mode. +signal TBI_STRB : bit; -- Strobe for the event counter mode. +signal TAO_I : bit; -- Timer A output signal. +signal TBO_I : bit; -- Timer A output signal. +begin + SYNC: process + -- This process provides a 'clean' XTAL1. + -- Without this sync, the edge detector for + -- XTAL_STRB does not work properly. + begin + wait until CLK = '1' and CLK' event; + XTAL1_S <= XTAL1; + -- Polarity control for the event counter and the PWM mode: + TAI_I <= TAI xnor AER_4; + TBI_I <= TBI xnor AER_3; + end process SYNC; + + -- Output enables for timer A and timer B: + -- The outputs are held low for asserted reset flags in the control registers TACR + -- and TBCR but also during a write operation to these registers. + TAO <= '0' when TACR(4) = '1' else + '0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01100" else TAO_I; + TBO <= '0' when TBCR(4) = '1' else + '0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01101" else TBO_I; + + -- Control outputs for the PWM modi of the timers A and B. These + -- controls are used in the interrupt logic to select the interrupt + -- sources GPIP4 or TAI repective GPIP3 or TBI. + TA_PWM <= '1' when TACR(3 downto 0) > x"8" else '0'; + TB_PWM <= '1' when TBCR(3 downto 0) > x"8" else '0'; + + TIMER_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + TACR <= (others => '0'); + TBCR <= (others => '0'); + TCDCR <= (others => '0'); + -- TADR <= Do not clear during reset! + -- TBDR <= Do not clear during reset! + -- TCDR <= Do not clear during reset! + -- TDDR <= Do not clear during reset! + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "01100" => TACR <= DATA_IN(4 downto 0); + when "01101" => TBCR <= DATA_IN(4 downto 0); + when "01110" => TCDCR <= DATA_IN(6 downto 4) & DATA_IN(2 downto 0); + when "01111" => TADR <= DATA_IN; + when "10000" => TBDR <= DATA_IN; + when "10001" => TCDR <= DATA_IN; + when "10010" => TDDR <= DATA_IN; + when others => null; + end case; + end if; + end if; + end process TIMER_REGISTERS; + + TIMER_READBACK : process(RESETn, CLK) + -- This process provides the readback information for the + -- timers A to D. The information read is the information + -- last clocked into the timer read register when the DSn + -- pin had last gone high prior to the current read cycle. + variable READ_A : boolean; + variable READ_B : boolean; + variable READ_C : boolean; + variable READ_D : boolean; + begin + if RESETn = '0' then + TIMER_R_A <= x"00"; + TIMER_R_B <= x"00"; + TIMER_R_C <= x"00"; + TIMER_R_D <= x"00"; + elsif CLK = '1' and CLK' event then + if DSn = '0' and RS = "01111" then + READ_A := true; + elsif DSn = '0' and RS = "10000" then + READ_B := true; + elsif DSn = '0' and RS = "10001" then + READ_C := true; + elsif DSn = '0' and RS = "10010" then + READ_D := true; + elsif DSn = '1' and READ_A = true then + TIMER_R_A <= To_BitVector(TIMER_A); + READ_A := false; + elsif DSn = '1' and READ_B = true then + TIMER_R_B <= To_BitVector(TIMER_B); + READ_B := false; + elsif DSn = '1' and READ_C = true then + TIMER_R_C <= To_BitVector(TIMER_C); + READ_C := false; + elsif DSn = '1' and READ_D = true then + TIMER_R_D <= To_BitVector(TIMER_D); + READ_D := false; + end if; + end if; + end process TIMER_READBACK; + + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "01011" and RS <= "10010" else '0'; + DATA_OUT <= "000" & TACR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01100" else + "000" & TBCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01101" else + '0' & TCDCR(5 downto 3) & '0' & TCDCR(2 downto 0) when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01110" else + TIMER_R_A when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01111" else + TIMER_R_B when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10000" else + TIMER_R_C when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10001" else + TIMER_R_D when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10010" else (others => '0'); + + XTAL_STROBE: process(RESETn, CLK) + -- This process provides a strobe with 1 clock cycle + -- (CLK) length after every rising edge of XTAL1. + variable LOCK : boolean; + begin + if RESETn = '0' then + XTAL_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if XTAL1_S = '1' and LOCK = false then + XTAL_STRB <= '1'; + LOCK := true; + elsif XTAL1_S = '0' then + XTAL_STRB <= '0'; + LOCK := false; + else + XTAL_STRB <= '0'; + end if; + end if; + end process XTAL_STROBE; + + TAI_STROBE: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + TAI_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if TAI_I = '1' and XTAL_STRB = '1' and LOCK = false then + LOCK := true; + TAI_STRB <= '1'; + elsif TAI_I = '0' then + LOCK := false; + TAI_STRB <= '0'; + else + TAI_STRB <= '0'; + end if; + end if; + end process TAI_STROBE; + + TBI_STROBE: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + TBI_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if TBI_I = '1' and XTAL_STRB = '1' and LOCK = false then + LOCK := true; + TBI_STRB <= '1'; + elsif TBI_I = '0' then + LOCK := false; + TBI_STRB <= '0'; + else + TBI_STRB <= '0'; + end if; + end if; + end process TBI_STROBE; + + PRESCALE_A: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + A_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TACR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode. + end case; + A_CNTSTRB <= '1'; + end if; + end process PRESCALE_A; + + PRESCALE_B: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + B_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TBCR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode. + end case; + B_CNTSTRB <= '1'; + end if; + end process PRESCALE_B; + + PRESCALE_C: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + C_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TCDCR(5 downto 3) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped. + end case; + C_CNTSTRB <= '1'; + end if; + end process PRESCALE_C; + + PRESCALE_D: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + D_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TCDCR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped. + end case; + D_CNTSTRB <= '1'; + end if; + end process PRESCALE_D; + + TIMERA: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TAO_I <= '0'; + TIMER_A_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_A_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_A <= To_StdLogicVector(DATA_IN); + else + case TACR(3 downto 0) is + when x"0" => -- Timer is off. + TAO_I <= '0'; + when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode. + if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + when x"8" => -- Event count operation. + if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode. + if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERA; + + TIMERB: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TBO_I <= '0'; + TIMER_B_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_B_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_B <= To_StdLogicVector(DATA_IN); + else + case TBCR(3 downto 0) is + when x"0" => -- Timer is off. + TBO_I <= '0'; + when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode. + if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + when x"8" => -- Event count operation. + if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode. + if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERB; + + TIMERC: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TCO <= '0'; + TIMER_C_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_C_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_C <= To_StdLogicVector(DATA_IN); + else + case TCDCR(5 downto 3) is + when "000" => -- Timer is off. + TCO <= '0'; + when others => -- Delay counter mode. + if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count. + TIMER_C <= TIMER_C - '1'; + elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload. + TIMER_C <= To_StdLogicVector(TCDR); + TCO <= not TCO; -- Toggle the timer C output pin. + TIMER_C_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERC; + + TIMERD: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TDO <= '0'; + TIMER_D_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_D_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_D <= To_StdLogicVector(DATA_IN); + else + case TCDCR(2 downto 0) is + when "000" => -- Timer is off. + TDO <= '0'; + when others => -- Delay counter mode. + if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count. + TIMER_D <= TIMER_D - '1'; + elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload. + TIMER_D <= To_StdLogicVector(TDDR); + TDO <= not TDO; -- Toggle the timer D output pin. + TIMER_D_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd new file mode 100644 index 0000000..783ba56 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd @@ -0,0 +1,213 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TOP is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA : inout std_logic_vector(7 downto 0); + GPIP : inout std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + + -- Serial I/O control: + RC : in bit; + TC : in bit; + SI : in bit; + SO : out std_logic; + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_TOP; + +architecture STRUCTURE of WF68901IP_TOP is +component WF68901IP_TOP_SOC + port(CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_EN : out bit_vector(7 downto 0); + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + XTAL1 : in bit; + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + RRn : out bit; + TRn : out bit + ); +end component; +-- +signal DTACK_In : bit; +signal IRQ_In : bit; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +signal GPIP_IN : bit_vector(7 downto 0); +signal GPIP_OUT : bit_vector(7 downto 0); +signal GPIP_EN : bit_vector(7 downto 0); +signal SO_I : bit; +signal SO_EN : bit; +begin + DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain. + IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + + GPIP_IN <= To_BitVector(GPIP); + + P_GPIP_OUT: process(GPIP_OUT, GPIP_EN) + begin + for i in 7 downto 0 loop + if GPIP_EN(i) = '1' then + case GPIP_OUT(i) is + when '0' => GPIP(i) <= '0'; + when others => GPIP(i) <= '1'; + end case; + else + GPIP(i) <= 'Z'; + end if; + end loop; + end process P_GPIP_OUT; + + SO <= '0' when SO_I = '0' and SO_EN = '1' else + '1' when SO_I = '1' and SO_EN = '1' else 'Z'; + + I_MFP: WF68901IP_TOP_SOC + port map(CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + DTACKn => DTACK_In, + RS => RS, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + GPIP_IN => GPIP_IN, + GPIP_OUT => GPIP_OUT, + GPIP_EN => GPIP_EN, + IACKn => IACKn, + IEIn => IEIn, + IEOn => IEOn, + IRQn => IRQ_In, + XTAL1 => XTAL1, + TAI => TAI, + TBI => TBI, + TAO => TAO, + TBO => TBO, + TCO => TCO, + TDO => TDO, + RC => RC, + TC => TC, + SI => SI, + SO => SO_I, + SO_EN => SO_EN, + RRn => RRn, + TRn => TRn + ); +end architecture STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd new file mode 100644 index 0000000..1e559d9 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd @@ -0,0 +1,309 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- DTACK_OUTn has now synchronous reset to meet preset requirement. +-- +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TOP_SOC is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_EN : out bit_vector(7 downto 0); + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + + -- Serial I/O control: + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_TOP_SOC; + +architecture STRUCTURE of WF68901IP_TOP_SOC is +signal DATA_IN_I : bit_vector(7 downto 0); +signal DTACK_In : bit; +signal DTACK_LOCK : boolean; +signal DTACK_OUTn : bit; +signal RX_ERR_INT_I : bit; +signal TX_ERR_INT_I : bit; +signal RX_BUFF_INT_I : bit; +signal TX_BUFF_INT_I : bit; +signal DATA_OUT_USART_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_USART_I : bit; +signal DATA_OUT_INT_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_INT_I : bit; +signal DATA_OUT_GPIO_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_GPIO_I : bit; +signal DATA_OUT_TIMERS_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_TIMERS_I : bit; +signal SO_I : bit; +signal SO_EN_I : bit; +signal GPIP_IN_I : bit_vector(7 downto 0); +signal GPIP_OUT_I : bit_vector(7 downto 0); +signal GPIP_EN_I : bit_vector(7 downto 0); +signal GP_INT_I : bit_vector(7 downto 0); +signal TIMER_A_INT_I : bit; +signal TIMER_B_INT_I : bit; +signal TIMER_C_INT_I : bit; +signal TIMER_D_INT_I : bit; +signal IRQ_In : bit; +signal AER_4_I : bit; +signal AER_3_I : bit; +signal TA_PWM_I : bit; +signal TB_PWM_I : bit; +begin + -- Interrupt request (open drain): + IRQn <= IRQ_In; + + -- Serial data output: + SO <= SO_I; + SO_EN <= SO_EN_I and RESETn; + + -- General purpose port: + GPIP_IN_I <= GPIP_IN; + GPIP_OUT <= GPIP_OUT_I; + GPIP_EN <= GPIP_EN_I; + + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I; + -- Output data multiplexer: + DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else + To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else + To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else + To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1'); + + -- Data acknowledge handshake is provided by the following statement and the consecutive two + -- processes. For more information refer to the M68000 family reference manual. + DTACK_In <= '0' when CSn = '0' and DSn = '0' and RS <= "10111" else -- Read and write operation. + '0' when IACKn = '0' and DSn = '0' and IEIn = '0' else '1'; -- Interrupt vector data acknowledge. + + P_DTACK_LOCK: process + -- This process releases a data acknowledge detect, one rising clock + -- edge after the DTACK_In occured. This is necessary to ensure write + -- data to registers for there is one rising clock edge required. + begin + wait until CLK = '1' and CLK' event; + if DTACK_In = '0' then + DTACK_LOCK <= false; + else + DTACK_LOCK <= true; + end if; + end process P_DTACK_LOCK; + + DTACK_OUT: process + -- The DTACKn port pin is released on the falling clock edge after the data + -- acknowledge detect (DTACK_LOCK) is asserted. The DTACKn is deasserted + -- immediately when there is no further register access DTACK_In = '1'; + begin + wait until CLK = '0' and CLK' event; + if RESETn = '0' then + DTACK_OUTn <= '1'; + elsif DTACK_In = '1' then + DTACK_OUTn <= '1'; + elsif DTACK_LOCK = false then + DTACK_OUTn <= '0'; + end if; + end process DTACK_OUT; + DTACKn <= '0' when DTACK_OUTn = '0' else '1'; + + I_USART: WF68901IP_USART_TOP + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_USART_I, + DATA_OUT_EN => DATA_OUT_EN_USART_I, + RC => RC, + TC => TC, + SI => SI, + SO => SO_I, + SO_EN => SO_EN_I, + RX_ERR_INT => RX_ERR_INT_I, + RX_BUFF_INT => RX_BUFF_INT_I, + TX_ERR_INT => TX_ERR_INT_I, + TX_BUFF_INT => TX_BUFF_INT_I, + RRn => RRn, + TRn => TRn + ); + + I_INTERRUPTS: WF68901IP_INTERRUPTS + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_INT_I, + DATA_OUT_EN => DATA_OUT_EN_INT_I, + IACKn => IACKn, + IEIn => IEIn, + IEOn => IEOn, + IRQn => IRQ_In, + GP_INT => GP_INT_I, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + TAI => TAI, + TBI => TBI, + TA_PWM => TA_PWM_I, + TB_PWM => TB_PWM_I, + TIMER_A_INT => TIMER_A_INT_I, + TIMER_B_INT => TIMER_B_INT_I, + TIMER_C_INT => TIMER_C_INT_I, + TIMER_D_INT => TIMER_D_INT_I, + RCV_ERR => RX_ERR_INT_I, + TRM_ERR => TX_ERR_INT_I, + RCV_BUF_F => RX_BUFF_INT_I, + TRM_BUF_E => TX_BUFF_INT_I + ); + + I_GPIO: WF68901IP_GPIO + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_GPIO_I, + DATA_OUT_EN => DATA_OUT_EN_GPIO_I, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + GPIP_IN => GPIP_IN_I, + GPIP_OUT => GPIP_OUT_I, + GPIP_OUT_EN => GPIP_EN_I, + GP_INT => GP_INT_I + ); + + I_TIMERS: WF68901IP_TIMERS + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_TIMERS_I, + DATA_OUT_EN => DATA_OUT_EN_TIMERS_I, + XTAL1 => XTAL1, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + TAI => TAI, + TBI => TBI, + TAO => TAO, + TBO => TBO, + TCO => TCO, + TDO => TDO, + TA_PWM => TA_PWM_I, + TB_PWM => TB_PWM_I, + TIMER_A_INT => TIMER_A_INT_I, + TIMER_B_INT => TIMER_B_INT_I, + TIMER_C_INT => TIMER_C_INT_I, + TIMER_D_INT => TIMER_D_INT_I + ); +end architecture STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd new file mode 100644 index 0000000..8e7c3cc --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd @@ -0,0 +1,191 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART control file. ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_CTRL is + port ( + -- System Control: + CLK : in bit; + RESETn : in bit; + + -- Bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- USART data register + RX_SAMPLE : in bit; + RX_DATA : in bit_vector(7 downto 0); + TX_DATA : out bit_vector(7 downto 0); + SCR_OUT : out bit_vector(7 downto 0); + + -- USART control inputs: + BF : in bit; + BE : in bit; + FE : in bit; + OE : in bit; + UE : in bit; + PE : in bit; + M_CIP : in bit; + FS_B : in bit; + TX_END : in bit; + + -- USART control outputs: + CL : out bit_vector(1 downto 0); + ST : out bit_vector(1 downto 0); + FS_CLR : out bit; + UDR_WRITE : out bit; + UDR_READ : out bit; + RSR_READ : out bit; + TSR_READ : out bit; + LOOPBACK : out bit; + SDOUT_EN : out bit; + SD_LEVEL : out bit; + CLK_MODE : out bit; + RE : out bit; + TE : out bit; + P_ENA : out bit; + P_EOn : out bit; + SS : out bit; + BR : out bit + ); +end entity WF68901IP_USART_CTRL; + +architecture BEHAVIOR of WF68901IP_USART_CTRL is +signal SCR : bit_vector(7 downto 0); -- Synchronous data register. +signal UCR : bit_vector(7 downto 1); -- USART control register. +signal RSR : bit_vector(7 downto 0); -- Receiver status register. +signal TSR : bit_vector(7 downto 0); -- Transmitter status register. +signal UDR : bit_vector(7 downto 0); -- USART data register. +begin + USART_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + SCR <= (others => '0'); + UCR <= (others => '0'); + RSR <= (others => '0'); + -- TSR and UDR are not cleared during an asserted RESETn + elsif CLK = '1' and CLK' event then + -- Loading via receiver shift register + -- has priority over data buss access: + if RX_SAMPLE = '1' then + UDR <= RX_DATA; + elsif CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "10011" => SCR <= DATA_IN; + when "10100" => UCR <= DATA_IN(7 downto 1); + when "10101" => RSR(1 downto 0) <= DATA_IN(1 downto 0); -- Only the two LSB are read/write. + when "10110" => TSR(5) <= DATA_IN(5); TSR(3 downto 0) <= DATA_IN(3 downto 0); + when "10111" => UDR <= DATA_IN; + when others => null; + end case; + end if; + RSR(7 downto 2) <= BF & OE & PE & FE & FS_B & M_CIP; + TSR(7 downto 6) <= BE & UE; + TSR(4) <= TX_END; + TX_DATA <= UDR; + end if; + end process USART_REGISTERS; + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS >= "10011" and RS <= "10111" else '0'; + DATA_OUT <= SCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10011" else + UCR & '0' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10100" else + RSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else + TSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else + UDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else x"00"; + + UDR_WRITE <= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10111" else '0'; + UDR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else '0'; + RSR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else '0'; + TSR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else '0'; + FS_CLR <= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10011" else '0'; + + RE <= '1' when RSR(0) = '1' else -- Receiver enable. + '1' when TSR(5) = '1' and TX_END = '1' else '0'; -- Auto Turnaround. + SS <= RSR(1); -- Synchronous strip enable. + BR <= TSR(3); -- Send break. + TE <= TSR(0); -- Transmitter enable. + + SCR_OUT <= SCR; + + CLK_MODE <= UCR(7); -- Clock mode. + CL <= UCR(6 downto 5); -- Character length. + ST <= UCR(4 downto 3); -- Start/Stop configuration. + P_ENA <= UCR(2); -- Parity enable. + P_EOn <= UCR(1); -- Even or odd parity. + + SOUT_CONFIG: process + begin + wait until CLK = '1' and CLK' event; + -- Do not change the output configuration until the transmitter is disabled and + -- current character has been transmitted (TX_END = '1'). + if TX_END = '1' then + case TSR(2 downto 1) is + when "00" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '0'; + when "01" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '1'; + when "10" => LOOPBACK <= '0'; SD_LEVEL <= '1'; SDOUT_EN <= '1'; + when "11" => LOOPBACK <= '1'; SD_LEVEL <= '1'; SDOUT_EN <= '1'; + end case; + end if; + end process SOUT_CONFIG; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd new file mode 100644 index 0000000..eb00a11 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd @@ -0,0 +1,590 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART receiver file. ---- +---- ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- Process P_STARTBIT has now synchronous reset to meet preset requirement. +-- Process P_SAMPLE has now synchronous reset to meet preset requirement. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_RX is + port ( + CLK : in bit; + RESETn : in bit; + + SCR : in bit_vector(7 downto 0); -- Synchronous character. + RX_SAMPLE : buffer bit; -- Flag indicating valid shift register data. + RX_DATA : out bit_vector(7 downto 0); -- Received data. + + RXCLK : in bit; -- Receiver clock. + SDATA_IN : in bit; -- Serial data input. + + CL : in bit_vector(1 downto 0); -- Character length. + ST : in bit_vector(1 downto 0); -- Start and stop bit configuration. + P_ENA : in bit; -- Parity enable. + P_EOn : in bit; -- Even or odd parity. + CLK_MODE : in bit; -- Clock mode configuration bit. + RE : in bit; -- Receiver enable. + FS_CLR : in bit; -- Clear the Found/Search flag for resynchronisation purpose. + SS : in bit; -- Synchronous strip enable. + UDR_READ : in bit; -- Flag indicating reading the data register. + RSR_READ : in bit; -- Flag indicating reading the receiver status register. + + M_CIP : out bit; -- Match/Character in progress. + FS_B : buffer bit; -- Find/Search or Break detect flag. + BF : out bit; -- Buffer full. + OE : out bit; -- Overrun error. + PE : out bit; -- Parity error. + FE : out bit -- Framing error. + ); +end entity WF68901IP_USART_RX; + +architecture BEHAVIOR of WF68901IP_USART_RX is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal SDATA_DIV16 : bit; +signal SDATA_IN_I : bit; +signal SDATA_EDGE : bit; +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal CLK_2_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +signal BREAK : boolean; +signal RDRF : bit; +signal STARTBIT : boolean; +begin + BF <= RDRF; -- Buffer full = Receiver Data Register Full. + RX_SAMPLE <= '1' when RCV_STATE = SYNC and ST /= "00" else -- Asynchronous mode: + -- Synchronous modes: + '1' when RCV_STATE = SYNC and ST = "00" and SS = '0' else + '1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0'; + + -- Data multiplexer for the received data: + RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits. + "00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits. + '0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits. + SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits. + + P_SAMPLE: process + -- This process provides the 'valid transition logic' of the originally MC68901. For further + -- details see the 'M68000 FAMILY REFERENCE MANUAL'. + variable LOW_FLT : std_logic_vector(1 downto 0); + variable HI_FLT : std_logic_vector(1 downto 0); + variable CLK_LOCK : boolean; + variable EDGE_LOCK : boolean; + variable TIMER : std_logic_vector(2 downto 0); + variable TIMER_LOCK : boolean; + variable NEW_SDATA : bit; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' or RE = '0' then + -- The reset condition assumes the SDATA_IN logic high. Otherwise + -- one not valid SDATA_EDGE pulse occurs during system startup. + CLK_LOCK := true; + EDGE_LOCK := true; + HI_FLT := "11"; + LOW_FLT := "11"; + SDATA_EDGE <= '0'; + NEW_SDATA := '1'; + -- Positive or negative edge detector for the incoming data. + -- Any transition must be valid for at least three receiver clock + -- cycles. The TIMER locking inhibits detecting four receiver + -- clock cycles after a valid transition. + elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then + CLK_LOCK := true; + EDGE_LOCK := false; + HI_FLT := "00"; + LOW_FLT := LOW_FLT - '1'; + elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then + CLK_LOCK := true; + EDGE_LOCK := false; + LOW_FLT := "11"; + HI_FLT := HI_FLT + '1'; + elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then + EDGE_LOCK := true; + SDATA_EDGE <= '1'; -- Falling edge detected. + NEW_SDATA := '0'; + elsif RXCLK = '1' and EDGE_LOCK = false and HI_FLT = "11" then + EDGE_LOCK := true; + SDATA_EDGE <= '1'; -- Rising edge detected. + NEW_SDATA := '1'; + elsif RXCLK = '1' and CLK_LOCK = false then + CLK_LOCK := true; + SDATA_EDGE <= '0'; + elsif RXCLK = '0' then + CLK_LOCK := false; + end if; + -- + if RESETn = '0' or RE = '0' then + -- The reset condition assumes the SDATA_IN logic high. Otherwise + -- one not valid SDATA_EDGE pulse occurs during system startup. + TIMER := "111"; + TIMER_LOCK := true; + SDATA_DIV16 <= '1'; + -- The timer controls the SDATA in a way, that after a detected valid + -- Transistion, the serial data is sampled on the 8th receiver clock + -- edge after the initial valid transition occured. + elsif RXCLK = '1' and SDATA_EDGE = '1' and TIMER_LOCK = false then + TIMER_LOCK := true; + TIMER := "000"; -- Resynchronisation. + elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then + TIMER_LOCK := true; + SDATA_DIV16 <= NEW_SDATA; -- Scan the new data. + TIMER := TIMER + '1'; -- Timing is active. + elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then + TIMER_LOCK := true; + TIMER := TIMER + '1'; -- Timing is active. + elsif RXCLK = '0' then + TIMER_LOCK := false; + end if; + end process P_SAMPLE; + + P_START_BIT: process(CLK) + -- This is the valid start bit logic of the original MC68901 multi function + -- port's USART receiver. + variable TMP : std_logic_vector(2 downto 0); + variable LOCK : boolean; + begin + if CLK = '1' and CLK' event then + if RESETn = '0' then + TMP := "000"; + LOCK := true; + elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled. + TMP := "000"; + LOCK := true; + elsif SDATA_EDGE = '1' then + TMP := "000"; -- (Re)-Initialize. + LOCK := false; -- Start counting. + elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then + LOCK := true; + TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid. + elsif RXCLK = '0' then + LOCK := false; + end if; + end if; + + case TMP is + when "111" => STARTBIT <= true; + when others => STARTBIT <= false; + end case; + end process P_START_BIT; + + SDATA_IN_I <= SDATA_IN when CLK_MODE = '0' else -- Clock div by 1 mode. + SDATA_IN when ST = "00" else SDATA_DIV16; -- Synchronous mode. + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(4 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CLK_MODE = '0' then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode. + elsif SDATA_EDGE = '1' then +CLK_DIVCNT := "01100"; -- Div by 16 mode. + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + else + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_LOCK := true; + if CLK_DIVCNT = "01000" then + -- This strobe is asserted at half of the clock cycle. + -- It is used for the stop bit timing. + CLK_2_STRB <= '1'; + end if; + elsif CLK_DIVCNT = "00000" then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + end if; + end if; + end process CLKDIV; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if RE = '0' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= SDATA_IN_I & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_M_CIP: process(RESETn, CLK) + -- In Synchronous mode this flag indicates wether a synchronous character M_CIP = '1' + -- or another character (M_CIP = '0') is transferred to the receive buffer. + -- In asynchronous mode the flag indicates sampling condition. + begin + if RESETn = '0' then + M_CIP <= '0'; + elsif CLK = '0' and CLK' event then + if RE = '0' then + M_CIP <= '0'; + elsif ST = "00" then -- Synchronous mode. + if RCV_STATE = SYNC and SHIFT_REG = SCR and RDRF = '0' then + M_CIP <= '1'; -- SCR transferred. + elsif RCV_STATE = SYNC and RDRF = '0' then + M_CIP <= '0'; -- No SCR transferred. + end if; + else -- Asynchronous mode. + case RCV_STATE is + when SAMPLE | PARITY | STOP1 | STOP2 => M_CIP <= '1'; -- Sampling. + when others => M_CIP <= '0'; -- No Sampling. + end case; + end if; + end if; + end process P_M_CIP; + + BREAK_DETECT: process(RESETn, CLK) + -- A break condition occurs, if there is no STOP1 bit and the + -- shift register contains zero data. + begin + if RESETn = '0' then + BREAK <= false; + elsif CLK = '1' and CLK' event then + if RE = '0' then + BREAK <= false; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then + BREAK <= true; -- Break detected (empty shift register and no stop bit). + elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then + BREAK <= false; -- UPDATE. + elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + BREAK <= false; -- UPDATE, but framing error. + end if; + end if; + end if; + end process BREAK_DETECT; + + P_FS_B: process(RESETn, CLK) + -- In the synchronous mode, this process provides the flag detecting the synchronous + -- character. In the asynchronous mode, the flag indicates a break condition. + variable FS_B_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + FS_B <= '0'; + FIRST_READ := false; + FS_B_I := '0'; + elsif CLK = '0' and CLK' event then + if RE = '0' then + FS_B <= '0'; + FS_B_I := '0'; + else + if ST = "00" then -- Synchronous operation. + if FS_CLR = '1' then + FS_B <= '0'; -- Clear during writing to the SCR. + elsif SHIFT_REG = SCR then + FS_B <= '1'; -- SCR detected. + end if; + else -- Asynchronous operation. + if RX_SAMPLE = '1' and BREAK = true then -- Break condition detected. + FS_B_I := '1'; -- Update. + elsif RX_SAMPLE = '1' then -- No break condition. + FS_B_I := '0'; -- Update. + elsif RSR_READ = '1' and FS_B_I = '1' then + -- If a break condition was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the break flag is reset + -- and the break condition disappears after a second read + -- (in time) of the receiver status register. + if FIRST_READ = false then + FS_B <= '1'; + FIRST_READ := true; + else + FS_B <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end if; + end if; + end process P_FS_B; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode. + BITCNT <= BITCNT + '1'; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode. + BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1'). + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + BUFFER_FULL: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + RDRF <= '0'; + elsif RX_SAMPLE = '1' then + RDRF <= '1'; -- Data register is full until now! + elsif UDR_READ = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process BUFFER_FULL; + + OVERRUN: process(RESETn, CLK) + variable OE_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OE_I := '0'; + OE <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if RESETn = '0' then + OE_I := '0'; + OE <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = SYNC and BREAK = false then + -- Overrun appears if RDRF is '1' in this state and there + -- is no break condition. + OE_I := RDRF; + end if; + if RSR_READ = '1' and OE_I = '1' then + -- if an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OE_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OE <= '1'; + FIRST_READ := true; + else + OE <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable P_ERR : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + PE <= '0'; + elsif RX_SAMPLE = '1' then + PE <= P_ERR; -- Update on load shift register to data register. + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + P_ERR := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if P_ENA = '1' and P_EOn = '1' then -- Even parity. + P_ERR := PAR_TMP xor SDATA_IN_I; + elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity. + P_ERR := not PAR_TMP xor SDATA_IN_I; + elsif P_ENA = '0' then -- No parity. + P_ERR := '0'; + end if; + end if; + end if; + end if; + end process PARITY_TEST; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + FE_I := '1'; + elsif RCV_STATE = STOP2 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if RE = '0' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, SDATA_IN_I, BITCNT, CLK_STRB, STARTBIT, + CLK_2_STRB, ST, CLK_MODE, CL, P_ENA, SHIFT_REG) + begin + case RCV_STATE is + when IDLE => + if ST = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode. + elsif SDATA_IN_I = '0' and CLK_MODE = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif STARTBIT = true and CLK_MODE = '1' then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + -- This state delays the sample process by one CLK_STRB pulse + -- to eliminate the start bit. + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SAMPLE; + else + RCV_NEXT_STATE <= WAIT_START; + end if; + when SAMPLE => + if CLK_STRB = '1' then + if CL = "11" and BITCNT < "100" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits. + elsif CL = "10" and BITCNT < "101" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits. + elsif CL = "01" and BITCNT < "110" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif CL = "00" and BITCNT < "111" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits). + RCV_NEXT_STATE <= IDLE; -- No parity check enabled. + elsif P_ENA = '0' then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + if ST = "00" then -- Synchronous mode (no stop bits). + RCV_NEXT_STATE <= IDLE; + else + RCV_NEXT_STATE <= STOP1; + end if; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data. + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif ST = "11" or ST = "10" then + RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_2_STRB = '1' and ST = "10" then + RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected. + elsif CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; -- Two stop bits selected. + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd new file mode 100644 index 0000000..fd06bf1 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd @@ -0,0 +1,238 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core USART top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_TOP is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Serial I/O control: + RC : in bit; -- Receiver clock. + TC : in bit; -- Transmitter clock. + SI : in bit; -- Serial input. + SO : out bit; -- Serial output. + SO_EN : out bit; -- Serial output enable. + + -- Interrupt channels: + RX_ERR_INT : out bit; -- Receiver errors. + RX_BUFF_INT : out bit; -- Receiver buffer full. + TX_ERR_INT : out bit; -- Transmitter errors. + TX_BUFF_INT : out bit; -- Transmitter buffer empty. + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_USART_TOP; + +architecture STRUCTURE of WF68901IP_USART_TOP is + signal BF_I : bit; + signal BE_I : bit; + signal FE_I : bit; + signal OE_I : bit; + signal UE_I : bit; + signal PE_I : bit; + signal LOOPBACK_I : bit; + signal SD_LEVEL_I : bit; + signal SDATA_IN_I : bit; + signal SDATA_OUT_I : bit; + signal RXCLK_I : bit; + signal CLK_MODE_I : bit; + signal SCR_I : bit_vector(7 downto 0); + signal RX_SAMPLE_I : bit; + signal RX_DATA_I : bit_vector(7 downto 0); + signal TX_DATA_I : bit_vector(7 downto 0); + signal CL_I : bit_vector(1 downto 0); + signal ST_I : bit_vector(1 downto 0); + signal P_ENA_I : bit; + signal P_EOn_I : bit; + signal RE_I : bit; + signal TE_I : bit; + signal FS_CLR_I : bit; + signal SS_I : bit; + signal M_CIP_I : bit; + signal FS_B_I : bit; + signal BR_I : bit; + signal UDR_READ_I : bit; + signal UDR_WRITE_I : bit; + signal RSR_READ_I : bit; + signal TSR_READ_I : bit; + signal TX_END_I : bit; +begin + SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I; + -- Loopback mode: + SDATA_IN_I <= SDATA_OUT_I when LOOPBACK_I = '1' and TE_I = '1' else -- Loopback, transmitter enabled. + '1' when LOOPBACK_I = '1' and TE_I = '0' else SI; -- Loopback, transmitter disabled. + + RXCLK_I <= TC when LOOPBACK_I = '1' else RC; + RRn <= '0' when BF_I = '1' and PE_I = '0' and FE_I = '0' else '1'; + TRn <= not BE_I; + + -- Interrupt sources: + RX_ERR_INT <= OE_I or PE_I or FE_I or FS_B_I; + RX_BUFF_INT <= BF_I; + TX_ERR_INT <= UE_I or TX_END_I; + TX_BUFF_INT <= BE_I; + + I_USART_CTRL: WF68901IP_USART_CTRL + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_OUT_EN => DATA_OUT_EN, + LOOPBACK => LOOPBACK_I, + SDOUT_EN => SO_EN, + SD_LEVEL => SD_LEVEL_I, + CLK_MODE => CLK_MODE_I, + RE => RE_I, + TE => TE_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + BF => BF_I, + BE => BE_I, + FE => FE_I, + OE => OE_I, + UE => UE_I, + PE => PE_I, + M_CIP => M_CIP_I, + FS_B => FS_B_I, + SCR_OUT => SCR_I, + TX_DATA => TX_DATA_I, + RX_SAMPLE => RX_SAMPLE_I, + RX_DATA => RX_DATA_I, + SS => SS_I, + BR => BR_I, + CL => CL_I, + ST => ST_I, + FS_CLR => FS_CLR_I, + UDR_READ => UDR_READ_I, + UDR_WRITE => UDR_WRITE_I, + RSR_READ => RSR_READ_I, + TSR_READ => TSR_READ_I, + TX_END => TX_END_I + ); + + I_USART_RECEIVE: WF68901IP_USART_RX + port map ( + CLK => CLK, + RESETn => RESETn, + SCR => SCR_I, + RX_SAMPLE => RX_SAMPLE_I, + RX_DATA => RX_DATA_I, + CL => CL_I, + ST => ST_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + CLK_MODE => CLK_MODE_I, + RE => RE_I, + FS_CLR => FS_CLR_I, + SS => SS_I, + RXCLK => RXCLK_I, + SDATA_IN => SDATA_IN_I, + RSR_READ => RSR_READ_I, + UDR_READ => UDR_READ_I, + M_CIP => M_CIP_I, + FS_B => FS_B_I, + BF => BF_I, + OE => OE_I, + PE => PE_I, + FE => FE_I + ); + + I_USART_TRANSMIT: WF68901IP_USART_TX + port map ( + CLK => CLK, + RESETn => RESETn, + SCR => SCR_I, + TX_DATA => TX_DATA_I, + SDATA_OUT => SDATA_OUT_I, + TXCLK => TC, + CL => CL_I, + ST => ST_I, + TE => TE_I, + BR => BR_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + UDR_WRITE => UDR_WRITE_I, + TSR_READ => TSR_READ_I, + CLK_MODE => CLK_MODE_I, + TX_END => TX_END_I, + UE => UE_I, + BE => BE_I + ); +end architecture STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd new file mode 100644 index 0000000..8de27f3 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd @@ -0,0 +1,387 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART transmitter file. ---- +---- ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- TDRE has now synchronous reset to meet preset requirement. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_TX is + port ( + CLK : in bit; + RESETn : in bit; + + SCR : in bit_vector(7 downto 0); -- Synchronous character. + TX_DATA : in bit_vector(7 downto 0); -- Normal data. + + SDATA_OUT : out bit; -- Serial data output. + TXCLK : in bit; -- Transmitter clock. + + CL : in bit_vector(1 downto 0); -- Character length. + ST : in bit_vector(1 downto 0); -- Start and stop bit configuration. + TE : in bit; -- Transmitter enable. + BR : in bit; -- BREAK character send enable (all '0' without stop bit). + P_ENA : in bit; -- Parity enable. + P_EOn : in bit; -- Even or odd parity. + UDR_WRITE : in bit; -- Flag indicating writing the data register. + TSR_READ : in bit; -- Flag indicating reading the transmitter status register. + CLK_MODE : in bit; -- Transmitter clock mode. + + TX_END : out bit; -- End of transmission flag. + UE : out bit; -- Underrun Flag. + BE : out bit -- Buffer empty flag. + ); +end entity WF68901IP_USART_TX; + +architecture BEHAVIOR of WF68901IP_USART_TX is +type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal CLK_2_STRB : bit; +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +signal TDRE : bit; +signal BREAK : bit; +begin + BE <= TDRE; -- Buffer empty flag. + + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + SDATA_OUT <= '0' when BREAK = '1' else + '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + P_BREAK : process(RESETn, CLK) + -- This process is responsible to control the BREAK signal. After the break request + -- is asserted via BR, the break character will be sent after the current transmission has + -- finished. The BREAK character is sent until the BR is disabled. + variable LOCK : boolean; + begin + if RESETn = '0' then + BREAK <= '0'; + elsif CLK = '1' and CLK' event then + -- Break is only available in the asynchronous mode (ST /= "00"). + -- The LOCK mechanism is reponsible for sending the BREAK character just once. + if TE = '1' and BR = '1' and ST /= "00" and TR_STATE = IDLE and LOCK = false then + BREAK <= '1'; -- Break for the case that there is no current transmission. + LOCK := true; + elsif BR = '1' and ST /= "00" and TR_STATE = STOP1 then + BREAK <= '0'; -- Break character sent. + elsif BR = '0' then + BREAK <= '0'; + LOCK := false; + else + BREAK <= '0'; + end if; + end if; + end process P_BREAK; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(4 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CLK_MODE = '0' then -- Divider off. + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode. + elsif TR_STATE = IDLE then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_LOCK := true; + if CLK_DIVCNT = "01000" then + -- This strobe is asserted at half of the clock cycle. + -- It is used for the stop bit timing. + CLK_2_STRB <= '1'; + end if; + elsif CLK_DIVCNT = "00000" then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + end if; + end if; + end process CLKDIV; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if TR_STATE = LOAD_SHFT and TDRE = '1' then -- Lost data ... + case ST is + when "00" => -- Synchronous mode. + SHIFT_REG <= SCR; -- Send the synchronous character. + when others => -- Asynchronous mode. + SHIFT_REG <= x"5A"; -- Load the shift register with a mark (underrun). + end case; + elsif TR_STATE = LOAD_SHFT then + -- Load 'normal' data if there is no break condition: + case CL is + when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits. + when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits. + when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits. + when "00" => SHIFT_REG <= TX_DATA; -- 8 databits. + end case; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + BUFFER_EMPTY: process + -- Transmit data register empty flag. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + TDRE <= '1'; + elsif TE = '0' then + TDRE <= '1'; + elsif TR_STATE = START and BREAK = '0' then + -- Data has been loaded to the shift register, + -- thus data register is free again. + -- If the BREAK flag is enabled, the BE flag + -- respective TDRE flag cannot be set. + TDRE <= '1'; + elsif UDR_WRITE = '1' then + TDRE <= '0'; + end if; + end process BUFFER_EMPTY; + + UNDERRUN: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + UE <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if TE = '0' then + UE <= '0'; + LOCK := false; + elsif CLK_STRB = '1' and TR_STATE = START then + -- Underrun appears if TDRE is '0' at the end of this state. + UE <= TDRE; -- Never true for enabled BREAK flag. See alos process BUFFER_EMPTY. + LOCK := true; + elsif CLK_STRB = '1' then + LOCK := false; -- Disables clearing UE one transmit clock cycle. + elsif TSR_READ = '1' and LOCK = false then + UE <= '0'; + end if; + end if; + end process UNDERRUN; + + P_TX_END: process(RESETn, CLK) + begin + if RESETn = '0' then + TX_END <= '0'; + elsif CLK = '1' and CLK' event then + if TE = '1' then -- Transmitter enabled. + TX_END <= '0'; + elsif TE = '0' and TR_STATE = IDLE then + TX_END <= '1'; + end if; + end if; + end process P_TX_END; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if P_ENA = '1' and P_EOn = '1' then -- Even parity. + PARITY_I <= PAR_TMP; + elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity. + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + TR_STATE <= TR_NEXT_STATE; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, CLK_2_STRB, BITCNT, TDRE, BREAK, TE, ST, P_ENA, CL, BR) + begin + case TR_STATE is + when IDLE => + -- This IDLE state is just one clock cycle and is required to give the + -- break process time to set the BREAK flag. + TR_NEXT_STATE <= CHECK_BREAK; + when CHECK_BREAK => + if BREAK = '1' then -- Send break character. + -- Do not load any data to the shift register, go directly + -- to the START state. + TR_NEXT_STATE <= START; + -- Start enabled transmitter, if the data register is not empty. + -- Do not send any further data for the case of an asserted BR flag. + elsif TE = '1' and TDRE = '0' and BR = '0' then + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; -- Go back, scan for BREAK. + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => -- Send the start bit. + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "100" and CL = "11" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits. + elsif BITCNT < "101" and CL = "10" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits. + elsif BITCNT < "110" and CL = "01" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and CL = "00" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif P_ENA = '0' and BREAK = '1' then + TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits. + elsif P_ENA = '0' and ST = "00" then + TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled. + elsif P_ENA = '0' then + TR_NEXT_STATE <= STOP1; -- Asynchronous mode, no parity check enabled. + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if ST = "00" then -- Synchronous mode (no stop bits). + TR_NEXT_STATE <= IDLE; + elsif BREAK = '1' then -- No stop bits during break condition. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (ST = "11" or ST = "10") then + TR_NEXT_STATE <= STOP2; -- More than one stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_2_STRB = '1' and ST = "10" then + TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- Two stop bits detected. + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd new file mode 100644 index 0000000..685fc02 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd @@ -0,0 +1,228 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 1.0 2007/01/05 WF +-- Initial Release. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D : inout std_logic_vector(7 downto 0); + + -- Microcontroller interface: + MC_D : inout std_logic_vector(7 downto 0); + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => 'Z'); + ACSI_D <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => 'Z'); + ACSI_INTn <= INT_REG; + ACSI_DRQn <= DRQ_REG; + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then + if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd new file mode 100644 index 0000000..b1dfe91 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd @@ -0,0 +1,240 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K7A 2007/01/05 WF +-- Initial Release. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out bit; + + -- Microcontroller interface: + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); + MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; + ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); +--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; +ACSI_D_EN <= '0'; -- Disabled. +--ACSI_INTn <= INT_REG; +ACSI_INTn <= '1'; -- Disabled. +--ACSI_DRQn <= DRQ_REG; +ACSI_DRQn <= '1'; -- Disabled. + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then +-- ?? ACSI_CSn doppelt! +if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak new file mode 100644 index 0000000..0200dea --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak @@ -0,0 +1,239 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K7A 2007/01/05 WF +-- Initial Release. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out bit; + + -- Microcontroller interface: + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); + MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; + ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); +-- ???: +--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; +ACSI_D_EN <= '0'; + ACSI_INTn <= INT_REG; + ACSI_DRQn <= DRQ_REG; + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then +-- ?? ACSI_CSn doppelt! +--if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd new file mode 100644 index 0000000..9d048de --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -0,0 +1,84 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package WF2149IP_PKG is +type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); + +component WF2149IP_WAVE + port( + RESETn : in bit; + SYS_CLK : in bit; + + WAV_STRB : in bit; + + ADR : in bit_vector(3 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + BUSCYCLE : in BUSCYCLES; + CTRL_REG : in bit_vector(5 downto 0); + + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end component; +end WF2149IP_PKG; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd new file mode 100644 index 0000000..3f5024a --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd @@ -0,0 +1,170 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- This IP core of the sound generator differs slightly from ---- +---- the original. Firstly it is a synchronous design without any ---- +---- latches (like assumed in the original chip). This required ---- +---- the introduction of a system adequate clock. In detail this ---- +---- SYS_CLK should on the one hand be fast enough to meet the ---- +---- timing requirements of the system's bus cycle and should one ---- +---- the other hand drive the PWM modules correctly. To meet both ---- +---- a SYS_CLK of 16MHz or above is recommended. ---- +---- Secondly, the original chip has an implemented DA converter. ---- +---- This feature is not possible in today's FPGAs. Therefore the ---- +---- converter is replaced by pulse width modulators. This solu- ---- +---- tion is very simple in comparison to other approaches like ---- +---- external DA converters with wave tables etc. The soltution ---- +---- with the pulse width modulators is probably not as accurate ---- +---- DAs with wavetables. For a detailed descrition of the hard- ---- +---- ware PWM filter look at the end of the wave file, where the ---- +---- pulse width modulators can be found. ---- +---- For a proper operation it is required, that the wave clock ---- +---- is lower than the system clock. A good choice is for example ---- +---- 2MHz for the wave clock and 16MHz for the system clock. ---- +---- ---- +---- Main module file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_TOP is + port( + + SYS_CLK : in bit; -- Read the inforation in the header! + RESETn : in bit; + + WAV_CLK : in bit; -- Read the inforation in the header! + SELn : in bit; + + BDIR : in bit; + BC2, BC1 : in bit; + + A9n, A8 : in bit; + DA : inout std_logic_vector(7 downto 0); + + IO_A : inout std_logic_vector(7 downto 0); + IO_B : inout std_logic_vector(7 downto 0); + + OUT_A : out bit; -- Analog (PWM) outputs. + OUT_B : out bit; + OUT_C : out bit + ); +end WF2149IP_TOP; + +architecture STRUCTURE of WF2149IP_TOP is +component WF2149IP_TOP_SOC + port( + SYS_CLK : in bit; + RESETn : in bit; + WAV_CLK : in bit; + SELn : in bit; + BDIR : in bit; + BC2, BC1 : in bit; + A9n, A8 : in bit; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out bit; + IO_A_IN : in bit_vector(7 downto 0); + IO_A_OUT : out bit_vector(7 downto 0); + IO_A_EN : out bit; + IO_B_IN : in bit_vector(7 downto 0); + IO_B_OUT : out bit_vector(7 downto 0); + IO_B_EN : out bit; + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end component; +-- +signal DA_OUT : std_logic_vector(7 downto 0); +signal DA_EN : bit; +signal IO_A_IN : bit_vector(7 downto 0); +signal IO_A_OUT : bit_vector(7 downto 0); +signal IO_A_EN : bit; +signal IO_B_IN : bit_vector(7 downto 0); +signal IO_B_OUT : bit_vector(7 downto 0); +signal IO_B_EN : bit; +begin + IO_A_IN <= To_BitVector(IO_A); + IO_B_IN <= To_BitVector(IO_B); + + IO_A <= To_StdLogicVector(IO_A_OUT) when IO_A_EN = '1' else (others => 'Z'); + IO_B <= To_StdLogicVector(IO_B_OUT) when IO_B_EN = '1' else (others => 'Z'); + + DA <= DA_OUT when DA_EN = '1' else (others => 'Z'); + + I_SOUND: WF2149IP_TOP_SOC + port map(SYS_CLK => SYS_CLK, + RESETn => RESETn, + WAV_CLK => WAV_CLK, + SELn => SELn, + BDIR => BDIR, + BC2 => BC2, + BC1 => BC1, + A9n => A9n, + A8 => A8, + DA_IN => DA, + DA_OUT => DA_OUT, + DA_EN => DA_EN, + IO_A_IN => IO_A_IN, + IO_A_OUT => IO_A_OUT, + IO_A_EN => IO_A_EN, + IO_B_IN => IO_B_IN, + IO_B_OUT => IO_B_OUT, + IO_B_EN => IO_B_EN, + OUT_A => OUT_A, + OUT_B => OUT_B, + OUT_C => OUT_C + ); +end STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd new file mode 100644 index 0000000..77ea5ef --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -0,0 +1,229 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- This IP core of the sound generator differs slightly from ---- +---- the original. Firstly it is a synchronous design without any ---- +---- latches (like assumed in the original chip). This required ---- +---- the introduction of a system adequate clock. In detail this ---- +---- SYS_CLK should on the one hand be fast enough to meet the ---- +---- timing requirements of the system's bus cycle and should one ---- +---- the other hand drive the PWM modules correctly. To meet both ---- +---- a SYS_CLK of 16MHz or above is recommended. ---- +---- Secondly, the original chip has an implemented DA converter. ---- +---- This feature is not possible in today's FPGAs. Therefore the ---- +---- converter is replaced by pulse width modulators. This solu- ---- +---- tion is very simple in comparison to other approaches like ---- +---- external DA converters with wave tables etc. The soltution ---- +---- with the pulse width modulators is probably not as accurate ---- +---- DAs with wavetables. For a detailed descrition of the hard- ---- +---- ware PWM filter look at the end of the wave file, where the ---- +---- pulse width modulators can be found. ---- +---- For a proper operation it is required, that the wave clock ---- +---- is lower than the system clock. A good choice is for example ---- +---- 2MHz for the wave clock and 16MHz for the system clock. ---- +---- ---- +---- Main module file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_TOP_SOC is + port( + + SYS_CLK : in bit; -- Read the inforation in the header! + RESETn : in bit; + + WAV_CLK : in bit; -- Read the inforation in the header! + SELn : in bit; + + BDIR : in bit; + BC2, BC1 : in bit; + + A9n, A8 : in bit; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out bit; + + IO_A_IN : in bit_vector(7 downto 0); + IO_A_OUT : out bit_vector(7 downto 0); + IO_A_EN : out bit; + IO_B_IN : in bit_vector(7 downto 0); + IO_B_OUT : out bit_vector(7 downto 0); + IO_B_EN : out bit; + + OUT_A : out bit; -- Analog (PWM) outputs. + OUT_B : out bit; + OUT_C : out bit + ); +end WF2149IP_TOP_SOC; + +architecture STRUCTURE of WF2149IP_TOP_SOC is +signal BUSCYCLE : BUSCYCLES; +signal DATA_OUT_I : std_logic_vector(7 downto 0); +signal DATA_EN_I : bit; +signal WAV_STRB : bit; +signal ADR_I : bit_vector(3 downto 0); +signal CTRL_REG : bit_vector(7 downto 0); +signal PORT_A : bit_vector(7 downto 0); +signal PORT_B : bit_vector(7 downto 0); +begin + P_WAVSTRB: process(RESETn, SYS_CLK) + variable LOCK : boolean; + variable TMP : bit; + begin + if RESETn = '0' then + LOCK := false; + TMP := '0'; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_CLK = '1' and LOCK = false then + LOCK := true; + TMP := not TMP; -- Divider by 2. + case SELn is + when '1' => WAV_STRB <= '1'; + when others => WAV_STRB <= TMP; + end case; + elsif WAV_CLK = '0' then + LOCK := false; + WAV_STRB <= '0'; + else + WAV_STRB <= '0'; + end if; + end if; + end process P_WAVSTRB; + + with BDIR & BC2 & BC1 select + BUSCYCLE <= INACTIVE when "000" | "010" | "101", + ADDRESS when "001" | "100" | "111", + R_READ when "011", + R_WRITE when "110"; + + ADDRESSLATCH: process(RESETn, SYS_CLK) + -- This process is responsible to store the desired register + -- address. The default (after reset) is channel A fine tone + -- adjustment. + begin + if RESETn = '0' then + ADR_I <= (others => '0'); + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then + ADR_I <= To_BitVector(DA_IN(3 downto 0)); + end if; + end if; + end process ADDRESSLATCH; + + P_CTRL_REG: process(RESETn, SYS_CLK) + -- THIS is the Control register for the mixer and for the I/O ports. + begin + if RESETn = '0' then + CTRL_REG <= x"00"; + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = R_WRITE and ADR_I = x"7" then + CTRL_REG <= To_BitVector(DA_IN); + end if; + end if; + end process P_CTRL_REG; + + DIG_PORTS: process(RESETn, SYS_CLK) + begin + if RESETn = '0' then + PORT_A <= x"00"; + PORT_B <= x"00"; + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = R_WRITE and ADR_I = x"E" then + PORT_A <= To_BitVector(DA_IN); + elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then + PORT_B <= To_BitVector(DA_IN); + end if; + end if; + end process DIG_PORTS; + -- Set port direction to input or to output: + IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0'; + IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0'; + IO_A_OUT <= PORT_A; + IO_B_OUT <= PORT_B; + + I_PSG_WAVE: WF2149IP_WAVE + port map( + RESETn => RESETn, + SYS_CLK => SYS_CLK, + + WAV_STRB => WAV_STRB, + + ADR => ADR_I, + DATA_IN => DA_IN, + DATA_OUT => DATA_OUT_I, + DATA_EN => DATA_EN_I, + + BUSCYCLE => BUSCYCLE, + CTRL_REG => CTRL_REG(5 downto 0), + + OUT_A => OUT_A, + OUT_B => OUT_B, + OUT_C => OUT_C + ); + + -- Read the ports and registers: + DA_EN <= '1' when DATA_EN_I = '1' else + '1' when BUSCYCLE = R_READ and ADR_I = x"7" else + '1' when BUSCYCLE = R_READ and ADR_I = x"E" else + '1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0'; + + DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff. + To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else + To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else + To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0'); + +end STRUCTURE; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd new file mode 100644 index 0000000..d829f9b --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -0,0 +1,533 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- ---- +---- Waveform generator. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- NOISE_OUT has now synchronous reset to meet preset requirement. +-- Fixed a bug in the envelope generator. Thanks to Lyndon Amsdon finding it. +-- Correction of the schematic given in the end of this file. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_WAVE is + port( + RESETn : in bit; + SYS_CLK : in bit; + + WAV_STRB : in bit; + + ADR : in bit_vector(3 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + BUSCYCLE : in BUSCYCLES; + CTRL_REG : in bit_vector(5 downto 0); + + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end entity WF2149IP_WAVE; + +architecture BEHAVIOR of WF2149IP_WAVE is +signal FREQUENCY_A : std_logic_vector(11 downto 0); +signal FREQUENCY_B : std_logic_vector(11 downto 0); +signal FREQUENCY_C : std_logic_vector(11 downto 0); +signal NOISE_FREQ : std_logic_vector(4 downto 0); +signal LEVEL_A : std_logic_vector(4 downto 0); +signal LEVEL_B : std_logic_vector(4 downto 0); +signal LEVEL_C : std_logic_vector(4 downto 0); +signal ENV_FREQ : std_logic_vector(15 downto 0); +signal ENV_SHAPE : std_logic_vector(3 downto 0); +signal ENV_RESET : boolean; +signal ENV_STRB : bit; +signal OSC_A_OUT : bit; +signal OSC_B_OUT : bit; +signal OSC_C_OUT : bit; +signal NOISE_OUT : bit; +signal AUDIO_A : bit; +signal AUDIO_B : bit; +signal AUDIO_C : bit; +signal VOL_ENV : std_logic_vector(4 downto 0); +signal AMPLITUDE_A : std_logic_vector(4 downto 0); +signal AMPLITUDE_B : std_logic_vector(4 downto 0); +signal AMPLITUDE_C : std_logic_vector(4 downto 0); +signal VOLUME_A : std_logic_vector(7 downto 0); +signal VOLUME_B : std_logic_vector(7 downto 0); +signal VOLUME_C : std_logic_vector(7 downto 0); +signal PWM_RAMP : std_logic_vector(7 downto 0); +begin + REGISTERS: process(RESETn, SYS_CLK) + -- This process is responsible for initialisation + -- and write access to the configuration registers. + begin + if RESETn = '0' then + FREQUENCY_A <= x"000"; + FREQUENCY_B <= x"000"; + FREQUENCY_C <= x"000"; + NOISE_FREQ <= "00000"; + LEVEL_A <= "00000"; + LEVEL_B <= "00000"; + LEVEL_C <= "00000"; + ENV_FREQ <= (others => '0'); + ENV_SHAPE <= "0000"; + elsif SYS_CLK = '1' and SYS_CLK' event then + ENV_RESET <= false; -- Initialize signal. + if BUSCYCLE = R_WRITE then + case ADR is + when x"0" => FREQUENCY_A(7 downto 0) <= DATA_IN; + when x"1" => FREQUENCY_A(11 downto 8) <= DATA_IN(3 downto 0); + when x"2" => FREQUENCY_B(7 downto 0) <= DATA_IN; + when x"3" => FREQUENCY_B(11 downto 8) <= DATA_IN(3 downto 0); + when x"4" => FREQUENCY_C(7 downto 0) <= DATA_IN; + when x"5" => FREQUENCY_C(11 downto 8) <= DATA_IN(3 downto 0); + when x"6" => NOISE_FREQ <= DATA_IN(4 downto 0); + when x"8" => LEVEL_A <= DATA_IN(4 downto 0); + when x"9" => LEVEL_B <= DATA_IN(4 downto 0); + when x"A" => LEVEL_C <= DATA_IN(4 downto 0); + when x"B" => ENV_FREQ(7 downto 0) <= DATA_IN; + when x"C" => ENV_FREQ(15 downto 8) <= DATA_IN; + ENV_RESET <= true; -- Initialize the envelope generator. + when x"D" => ENV_SHAPE <= DATA_IN(3 downto 0); + when others => null; + end case; + end if; + end if; + end process REGISTERS; + + -- Read back the configuration registers: + DATA_OUT <= FREQUENCY_A(7 downto 0) when BUSCYCLE = R_READ and ADR = x"0" else + "0000" & FREQUENCY_A(11 downto 8) when BUSCYCLE = R_READ and ADR = x"1" else + FREQUENCY_B(7 downto 0) when BUSCYCLE = R_READ and ADR = x"2" else + "0000" & FREQUENCY_B(11 downto 8) when BUSCYCLE = R_READ and ADR = x"3" else + FREQUENCY_C(7 downto 0) when BUSCYCLE = R_READ and ADR = x"4" else + "0000" & FREQUENCY_C(11 downto 8) when BUSCYCLE = R_READ and ADR = x"5" else + "000" & NOISE_FREQ when BUSCYCLE = R_READ and ADR = x"6" else + "000" & LEVEL_A when BUSCYCLE = R_READ and ADR = x"8" else + "000" & LEVEL_B when BUSCYCLE = R_READ and ADR = x"9" else + "000" & LEVEL_C when BUSCYCLE = R_READ and ADR = x"A" else + ENV_FREQ(7 downto 0) when BUSCYCLE = R_READ and ADR = x"B" else + ENV_FREQ(15 downto 8) when BUSCYCLE = R_READ and ADR = x"C" else + x"0" & ENV_SHAPE when BUSCYCLE = R_READ and ADR = x"D" else (others => '0'); + DATA_EN <= '1' when BUSCYCLE = R_READ and ADR >= x"0" and ADR <= x"6" else + '1' when BUSCYCLE = R_READ and ADR >= x"8" and ADR <= x"D" else '0'; + + MUSICGENERATOR: process(RESETn, SYS_CLK) + variable CLK_DIV : std_logic_vector(2 downto 0); + variable CNT_CH_A : std_logic_vector(11 downto 0); + variable CNT_CH_B : std_logic_vector(11 downto 0); + variable CNT_CH_C : std_logic_vector(11 downto 0); + begin + if RESETn = '0' then + CLK_DIV := "000"; + CNT_CH_A := (others => '0'); + CNT_CH_B := (others => '0'); + CNT_CH_C := (others => '0'); + OSC_A_OUT <= '0'; + OSC_B_OUT <= '0'; + OSC_C_OUT <= '0'; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_STRB = '1' then + -- Divider by 8 for the oscillators brings in connection + -- with the toggle flip flops CH_x_OUT the required divider + -- ratio of 16. + CLK_DIV := CLK_DIV + '1'; + + if CLK_DIV = "000" then + if FREQUENCY_A = x"000" then + CNT_CH_A := (others => '0'); + OSC_A_OUT <= '0'; + elsif CNT_CH_A = x"000" then + CNT_CH_A := FREQUENCY_A - '1' ; + OSC_A_OUT <= not OSC_A_OUT; + else + CNT_CH_A := CNT_CH_A - '1'; + end if; + + if FREQUENCY_B = x"000" then + CNT_CH_B := (others => '0'); + OSC_B_OUT <= '0'; + elsif CNT_CH_B = x"000" then + CNT_CH_B := FREQUENCY_B - '1' ; + OSC_B_OUT <= not OSC_B_OUT; + else + CNT_CH_B := CNT_CH_B - '1'; + end if; + + if FREQUENCY_C = x"000" then + CNT_CH_C := (others => '0'); + OSC_C_OUT <= '0'; + elsif CNT_CH_C = x"000" then + CNT_CH_C := FREQUENCY_C - '1' ; + OSC_C_OUT <= not OSC_C_OUT; + else + CNT_CH_C := CNT_CH_C - '1'; + end if; + end if; + end if; + end if; + end process MUSICGENERATOR; + + NOISEGENERATOR: process + -- The noise shift polynomial is taken from a template of Kazuhiro TSUJIKAWA's + -- (ESE Artists' factory) approach for a 2149 equivalent. But the implementation + -- is done in another way. + -- LFSR (linear feedback shift register polynomial: f(x) = x^17 + x^14 + 1. + variable CLK_DIV : std_logic_vector(3 downto 0); + variable CNT_NOISE : std_logic_vector(4 downto 0); + variable N_SHFT : std_logic_vector(16 downto 0); + begin + wait until SYS_CLK = '1' and SYS_CLK' event; + if RESETn = '0' then + CLK_DIV := x"0"; + CNT_NOISE := (others => '1'); -- Preset the polynomial shift register. + NOISE_OUT <= '1'; + elsif WAV_STRB = '1' then + -- Divider by 16 for the noise generator. + CLK_DIV := CLK_DIV + '1'; + if CLK_DIV = x"0" then + -- Noise frequency counter. + if NOISE_FREQ = "00000" then + CNT_NOISE := (others => '0'); + elsif CNT_NOISE = "00000" then + CNT_NOISE := NOISE_FREQ - '1' ; + N_SHFT := N_SHFT(15 downto 14) & not(N_SHFT(16) xor N_SHFT(13)) & + N_SHFT(12 downto 0) & not N_SHFT(16); + else + CNT_NOISE := CNT_NOISE - '1'; + end if; + end if; + end if; + NOISE_OUT <= To_Bit(N_SHFT(16)); + end process NOISEGENERATOR; + + ENVELOPE_PERIOD: process(RESETn, SYS_CLK) + -- The envelope period is controlled by the Envelope Frequency and the divider ratio which is + -- 256/32 = 8. For further information see the original data sheet. + variable ENV_CLK : std_logic_vector(18 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + ENV_STRB <= '0'; + ENV_CLK := (others => '0'); + LOCK := false; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_STRB = '1' and LOCK = false then + LOCK := true; + if ENV_FREQ = x"0000" then + ENV_STRB <= '0'; + elsif ENV_CLK = x"0000" & "000" then + ENV_CLK := (ENV_FREQ & "111") - '1' ; + ENV_STRB <= '1'; + else + ENV_CLK := ENV_CLK - '1'; + ENV_STRB <= '0'; + end if; + elsif WAV_STRB = '0' then + LOCK := false; + ENV_STRB <= '0'; + else + ENV_STRB <= '0'; + end if; + end if; + end process ENVELOPE_PERIOD; + + ENVELOPE: process(RESETn, SYS_CLK) + -- Envelope shapes: + -- case ENV_SHAPE: + -- + -- 0 0 x x \___ + -- + -- 0 1 x x /|___ + -- + -- 1 0 0 0 _|\|\|\|\| + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \| + -- + -- 1 1 0 0 /|/|/|/| + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /|___ + -- + variable ENV_STOP : boolean; + variable ENV_UP_DNn : bit; + begin + if RESETn = '0' then + VOL_ENV <= (others => '0'); + ENV_UP_DNn := '0'; + ENV_STOP := false; + elsif SYS_CLK = '1' and SYS_CLK' event then + if ENV_RESET = true then + ENV_STOP := false; + case ENV_SHAPE is + when "1011" | "1010" | "1001" | "1000" | "0011" | "0010" | "0001" | "0000" => + VOL_ENV <= "11111"; -- Start on top. + ENV_UP_DNn := '0'; + when others => + VOL_ENV <= "00000"; -- Start at bottom. + ENV_UP_DNn := '1'; + end case; + elsif ENV_STRB = '1' then + case ENV_SHAPE is + when "1001" | "0011" | "0010" | "0001" | "0000" => + if VOL_ENV > "00000" then + VOL_ENV <= VOL_ENV - '1'; + end if; + when "1111" | "0111" | "0110" | "0101" | "0100" => + if VOL_ENV < "11111" and ENV_STOP = false then + VOL_ENV <= VOL_ENV + '1'; + else + VOL_ENV <= "00000"; + ENV_STOP := true; + end if; + when "1000" => + VOL_ENV <= VOL_ENV - '1'; + when "1110" | "1010" => + if ENV_UP_DNn = '0' then + VOL_ENV <= VOL_ENV - '1'; + else + VOL_ENV <= VOL_ENV + '1'; + end if; + -- + if VOL_ENV = "00001" then + ENV_UP_DNn := '1'; + elsif VOL_ENV = "11110" then + ENV_UP_DNn := '0'; + end if; + when "1011" => + if VOL_ENV > "00000" and ENV_STOP = false then + VOL_ENV <= VOL_ENV - '1'; + else + VOL_ENV <= "11111"; + ENV_STOP := true; + end if; + when "1100" => + VOL_ENV <= VOL_ENV + '1'; + when "1101" => + if VOL_ENV < "11111" then + VOL_ENV <= VOL_ENV + '1'; + end if; + when others => null; -- Covers U, X, Z, W, H, L, -. + end case; + end if; + end if; + end process ENVELOPE; + + --MIXER: + -- The mixer controls are dependant on the mixer settings and the output of the + -- audio data for all three channels. The noise generator and the square wave + -- generators A, B and C are mixed together by a simple boolean OR. + AUDIO_A <= (OSC_A_OUT and not CTRL_REG(0)) or (NOISE_OUT and not CTRL_REG(3)); + AUDIO_B <= (OSC_B_OUT and not CTRL_REG(1)) or (NOISE_OUT and not CTRL_REG(4)); + AUDIO_C <= (OSC_C_OUT and not CTRL_REG(2)) or (NOISE_OUT and not CTRL_REG(5)); + + --LEVEL (e.g. volume control): + -- The linear amplitude for the DA converters of channel A, B or C are fixed + -- (LEVEL(3 downto 0)) or delivered by the envelope generator. + -- The following behavior is taken from the 2149 IP core of Mike J (www.fpgaarcade.com): + -- "make sure level 31 (env) = level 15 (tone)" + -- Thus there is a resulting & '1' modeling if LEVEL amplitudes are selected. + AMPLITUDE_A <= LEVEL_A(3 downto 0) & '1' when LEVEL_A(4) = '0' and AUDIO_A = '1' else + VOL_ENV when LEVEL_A(4) = '1' and AUDIO_A = '1' else "00000"; + AMPLITUDE_B <= LEVEL_B(3 downto 0) & '1' when LEVEL_B(4) = '0' and AUDIO_B = '1' else + VOL_ENV when LEVEL_B(4) = '1' and AUDIO_B = '1' else "00000"; + AMPLITUDE_C <= LEVEL_C(3 downto 0) & '1' when LEVEL_C(4) = '0' and AUDIO_C = '1' else + VOL_ENV when LEVEL_C(4) = '1' and AUDIO_C = '1' else "00000"; + + -- The values for the logarithmic DA converter volume controls are taken from the linear + -- mixer of Mike J's 2149 IP core (www.fpgaarcade.com). + with AMPLITUDE_A select + VOLUME_A <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + with AMPLITUDE_B select + VOLUME_B <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + with AMPLITUDE_C select + VOLUME_C <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + DA_CONVERSION: process + -- The DA conversion for the three analog outputs is originally performed by a built in DA converter. + -- For this is not possible in current FPGA designs, the converter is replaced by three PWM units + -- operating at a frequency which is 100 times higher than the highest noise or music frequency which + -- is 2MHz/16 = 125kHz. So the PWM frequency requires about 12.5MHz or more. The design is done for + -- a PWM frequency of 16MHz). + begin + wait until SYS_CLK = '1' and SYS_CLK' event; + PWM_RAMP <= PWM_RAMP + '1'; + end process DA_CONVERSION; + OUT_A <= '0' when VOLUME_A = x"00" else '1' when PWM_RAMP < VOLUME_A else '0'; + OUT_B <= '0' when VOLUME_B = x"00" else '1' when PWM_RAMP < VOLUME_B else '0'; + OUT_C <= '0' when VOLUME_C = x"00" else '1' when PWM_RAMP < VOLUME_C else '0'; + -- + -- To obtain proper analog output it is necessary to install analog RC filters to the pulse width + -- outputs. An example is given for the direct wiring of the three analog outputs and for a system + -- clock frequency of 16MHz. The output circuitry looks in this case as follows: + -- + -- OUT_A ---------|1kOhm|-----------| |\ e.g. LM741 + -- |----------------------|+\ || + -- OUT_B ---------|1kOhm|-----------| | OP------||--- Analog Signal + -- | |-----|-/ | || + -- OUT_C ---------|1kOhm|-----------| | |/ | 4u7 + -- | |__________| + -- | + -- --- 10nF. + -- --- + -- | + -- | + -- --- + -- WF. +end architecture BEHAVIOR; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd new file mode 100644 index 0000000..e60cc43 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd @@ -0,0 +1,244 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CTRL_REG has now synchronous reset to meet preset requirements. +-- Process P_DCD has now synchronous reset to meet preset requirements. +-- IRQ_In has now synchronous reset to meet preset requirement. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_CTRL_STATUS is + port ( + CLK : in bit; + RESETn : in bit; + + CS : in bit_vector(2 downto 0); -- Active if "011". + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Status register stuff: + RDRF : in bit; -- Receive data register full. + TDRE : in bit; -- Transmit data register empty. + DCDn : in bit; -- Data carrier detect. + CTSn : in bit; -- Clear to send. + FE : in bit; -- Framing error. + OVR : in bit; -- Overrun error. + PE : in bit; -- Parity error. + + -- Control register stuff: + MCLR : buffer bit; -- Master clear (high active). + RTSn : out bit; -- Request to send. + CDS : out bit_vector(1 downto 0); -- Clock control. + WS : out bit_vector(2 downto 0); -- Word select. + TC : out bit_vector(1 downto 0); -- Transmit control. + IRQn : out bit -- Interrupt request. + ); +end entity WF6850IP_CTRL_STATUS; + +architecture BEHAVIOR of WF6850IP_CTRL_STATUS is +signal CTRL_REG : bit_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal RIE : bit; +signal IRQ_I : bit; +signal CTS_In : bit; +signal DCD_In : bit; +signal DCD_FLAGn : bit; +begin + P_SAMPLE: process + begin + wait until CLK = '0' and CLK' event; + CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. + DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. + end process P_SAMPLE; + + STATUS_REG(7) <= IRQ_I; + STATUS_REG(6) <= PE; + STATUS_REG(5) <= OVR; + STATUS_REG(4) <= FE; + STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. + STATUS_REG(2) <= DCD_FLAGn; + STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. + STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. + + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + + MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; + RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; + + CDS <= CTRL_REG(1 downto 0); + WS <= CTRL_REG(4 downto 2); + TC <= CTRL_REG(6 downto 5); + RIE <= CTRL_REG(7); + + P_IRQ: process + variable DCD_OVR_LOCK : boolean; + variable DCD_LOCK : boolean; + variable DCD_TRANS : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_OVR_LOCK := false; + IRQn <= '1'; + IRQ_I <= '0'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + DCD_OVR_LOCK := false; -- Enable reset by reading the status. + end if; + + -- Clear interrupts when disabled. + if CTRL_REG(7) = '0' then + IRQn <= '1'; + IRQ_I <= '0'; + elsif CTRL_REG(6 downto 5) /= "01" then + IRQn <= '1'; + IRQ_I <= '0'; + end if; + + -- Transmitter interrupt: + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by writing to the transmit data register. + end if; + + -- Receiver interrupts: + if RDRF = '1' and RIE = '1' and DCD_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by reading the receive data register. + end if; + + if OVR = '1' and RIE = '1' then + IRQn <= '0'; + IRQ_I <= '1'; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + end if; + + if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then + IRQn <= '0'; + IRQ_I <= '1'; + -- DCD_TRANS is used to detect a low to high transition of DCDn. + DCD_TRANS := true; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + elsif DCD_In = '0' then + DCD_TRANS := false; + end if; + + -- The reset of the IRQ status flag: + -- Clear by writing to the transmit data register. + -- Clear by reading the receive data register. + if CS = "011" and RS = '1' and E = '1' then + IRQ_I <= '0'; + end if; + end process P_IRQ; + + CONTROL: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CTRL_REG <= "01000000"; + elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + CTRL_REG <= DATA_IN; + end if; + end process CONTROL; + + P_DCD: process + -- This process is some kind of tricky. Refer to the MC6850 data + -- sheet for more information. + variable READ_LOCK : boolean; + variable DCD_RELEASE : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_FLAGn <= '0'; -- This interrupt source must initialise low. + READ_LOCK := true; + DCD_RELEASE := false; + elsif MCLR = '1' then + DCD_FLAGn <= DCD_In; + READ_LOCK := true; + elsif DCD_In = '1' then + DCD_FLAGn <= '1'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + -- Clear if receiver status register read access. + -- After data register has ben read and READ_LOCK again. + DCD_RELEASE := true; + READ_LOCK := true; + DCD_FLAGn <= DCD_In; + elsif DCD_In = '0' and DCD_RELEASE = true then + DCD_FLAGn <= '0'; + DCD_RELEASE := false; + end if; + end process P_DCD; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak new file mode 100644 index 0000000..a0ea9e4 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak @@ -0,0 +1,244 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CTRL_REG has now synchronous reset to meet preset requirements. +-- Process P_DCD has now synchronous reset to meet preset requirements. +-- IRQ_In has now synchronous reset to meet preset requirement. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_CTRL_STATUS is + port ( + CLK : in bit; + RESETn : in bit; + + CS : in bit_vector(2 downto 0); -- Active if "011". + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Status register stuff: + RDRF : in bit; -- Receive data register full. + TDRE : in bit; -- Transmit data register empty. + DCDn : in bit; -- Data carrier detect. + CTSn : in bit; -- Clear to send. + FE : in bit; -- Framing error. + OVR : in bit; -- Overrun error. + PE : in bit; -- Parity error. + + -- Control register stuff: + MCLR : buffer bit; -- Master clear (high active). + RTSn : out bit; -- Request to send. + CDS : out bit_vector(1 downto 0); -- Clock control. + WS : out bit_vector(2 downto 0); -- Word select. + TC : out bit_vector(1 downto 0); -- Transmit control. + IRQn : out bit -- Interrupt request. + ); +end entity WF6850IP_CTRL_STATUS; + +architecture BEHAVIOR of WF6850IP_CTRL_STATUS is +signal CTRL_REG : bit_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal RIE : bit; +signal IRQ_I : bit; +signal CTS_In : bit; +signal DCD_In : bit; +signal DCD_FLAGn : bit; +begin + P_SAMPLE: process + begin + wait until CLK = '0' and CLK' event; + CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. + DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. + end process P_SAMPLE; + + STATUS_REG(7) <= IRQ_I; + STATUS_REG(6) <= PE; + STATUS_REG(5) <= OVR; + STATUS_REG(4) <= FE; + STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. + STATUS_REG(2) <= DCD_FLAGn; + STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. + STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. + + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + + MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; + RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; + + CDS <= CTRL_REG(1 downto 0); + WS <= CTRL_REG(4 downto 2); + TC <= CTRL_REG(6 downto 5); + RIE <= CTRL_REG(7); + + P_IRQ: process + variable DCD_OVR_LOCK : boolean; + variable DCD_LOCK : boolean; + variable DCD_TRANS : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_OVR_LOCK := false; + IRQn <= '1'; + IRQ_I <= '0'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + DCD_OVR_LOCK := false; -- Enable reset by reading the status. + end if; + +-- Clear interrupts when disabled. +if CTRL_REG(7) = '0' then + IRQn <= '1'; + IRQ_I <= '0'; +elsif CTRL_REG(6 downto 5) /= "01" then + IRQn <= '1'; + IRQ_I <= '0'; +end if; + + -- Transmitter interrupt: + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by writing to the transmit data register. + end if; + + -- Receiver interrupts: + if RDRF = '1' and RIE = '1' and DCD_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by reading the receive data register. + end if; + + if OVR = '1' and RIE = '1' then + IRQn <= '0'; + IRQ_I <= '1'; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + end if; + + if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then + IRQn <= '0'; + IRQ_I <= '1'; + -- DCD_TRANS is used to detect a low to high transition of DCDn. + DCD_TRANS := true; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + elsif DCD_In = '0' then + DCD_TRANS := false; + end if; + + -- The reset of the IRQ status flag: + -- Clear by writing to the transmit data register. + -- Clear by reading the receive data register. + if CS = "011" and RS = '1' and E = '1' then + IRQ_I <= '0'; + end if; + end process P_IRQ; + + CONTROL: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CTRL_REG <= "01000000"; + elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + CTRL_REG <= DATA_IN; + end if; + end process CONTROL; + + P_DCD: process + -- This process is some kind of tricky. Refer to the MC6850 data + -- sheet for more information. + variable READ_LOCK : boolean; + variable DCD_RELEASE : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_FLAGn <= '0'; -- This interrupt source must initialise low. + READ_LOCK := true; + DCD_RELEASE := false; + elsif MCLR = '1' then + DCD_FLAGn <= DCD_In; + READ_LOCK := true; + elsif DCD_In = '1' then + DCD_FLAGn <= '1'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + -- Clear if receiver status register read access. + -- After data register has ben read and READ_LOCK again. + DCD_RELEASE := true; + READ_LOCK := true; + DCD_FLAGn <= DCD_In; + elsif DCD_In = '0' and DCD_RELEASE = true then + DCD_FLAGn <= '0'; + DCD_RELEASE := false; + end if; + end process P_DCD; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd new file mode 100644 index 0000000..755e018 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd @@ -0,0 +1,415 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's receiver unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_RECEIVE is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + RXCLK : in bit; + RXDATA : in bit; + + RDRF : buffer bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end entity WF6850IP_RECEIVE; + +architecture BEHAVIOR of WF6850IP_RECEIVE is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal RXDATA_I : bit; +signal RXDATA_S : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +begin + P_SAMPLE: process + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + variable FLT_TMP : integer range 0 to 2; + begin + wait until CLK = '1' and CLK' event; + -- + RXDATA_I <= RXDATA; + -- + if RXDATA_I = '1' and FLT_TMP < 2 then + FLT_TMP := FLT_TMP + 1; + elsif RXDATA_I = '1' then + RXDATA_S <= '1'; + elsif RXDATA_I = '0' and FLT_TMP > 0 then + FLT_TMP := FLT_TMP - 1; + elsif RXDATA_I = '0' then + RXDATA_S <= '0'; + end if; + end process P_SAMPLE; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif RCV_STATE = IDLE then + -- Preset the CLKDIV with the start delays. + if CDS = "01" then + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + elsif CDS = "10" then + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + end if; + CLK_STRB <= '0'; + else + if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + end if; + end if; + end process DATAREG; + DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP2 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + OVERRUN: process(RESETn, CLK) + variable OVR_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = STOP1 then + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + end if; + if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OVR <= '1'; + FIRST_READ := true; + else + OVR <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable PE_I : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + PE <= '0'; + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + else -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + end if; + end if; + end if; + -- Transmit the parity flag together with the data + -- In other words: no parity to the status register + -- when RDRF inhibits the data transfer to the + -- receiver data register. + if RCV_STATE = SYNC and RDRF = '0' then + PE <= PE_I; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + PE <= '0'; -- Clear when reading the data register. + end if; + end if; + end process PARITY_TEST; + + P_RDRF: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RDRF <= '0'; + elsif RCV_STATE = SYNC then + RDRF <= '1'; -- Data register is full until now! + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process P_RDRF; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + begin + case RCV_STATE is + when IDLE => + if RXDATA_S = '0' and CDS = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif RXDATA_S = '0' and CDS = "01" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + elsif RXDATA_S = '0' and CDS = "10" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. + else + RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. + end if; + else + RCV_NEXT_STATE <= WAIT_START; -- Stay. + end if; + when SAMPLE => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif WS = "100" or WS = "101" then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= STOP1; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif WS = "000" or WS = "001" or WS = "100" then + RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak new file mode 100644 index 0000000..e8c82b2 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak @@ -0,0 +1,415 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's receiver unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_RECEIVE is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + RXCLK : in bit; + RXDATA : in bit; + + RDRF : buffer bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end entity WF6850IP_RECEIVE; + +architecture BEHAVIOR of WF6850IP_RECEIVE is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal RXDATA_I : bit; +signal RXDATA_S : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +begin + P_SAMPLE: process + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + variable FLT_TMP : integer range 0 to 2; + begin + wait until CLK = '1' and CLK' event; + -- + RXDATA_I <= RXDATA; + -- + if RXDATA_I = '1' and FLT_TMP < 2 then + FLT_TMP := FLT_TMP + 1; + elsif RXDATA_I = '1' then + RXDATA_S <= '1'; + elsif RXDATA_I = '0' and FLT_TMP > 0 then + FLT_TMP := FLT_TMP - 1; + elsif RXDATA_I = '0' then + RXDATA_S <= '0'; + end if; + end process P_SAMPLE; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif RCV_STATE = IDLE then + -- Preset the CLKDIV with the start delays. + if CDS = "01" then + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + elsif CDS = "10" then + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + end if; + CLK_STRB <= '0'; + else + if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + end if; + end if; + end process DATAREG; +--DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); +--DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; +DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0'); +DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0'; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP2 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + OVERRUN: process(RESETn, CLK) + variable OVR_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = STOP1 then + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + end if; + if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OVR <= '1'; + FIRST_READ := true; + else + OVR <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable PE_I : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + PE <= '0'; + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + else -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + end if; + end if; + end if; + -- Transmit the parity flag together with the data + -- In other words: no parity to the status register + -- when RDRF inhibits the data transfer to the + -- receiver data register. + if RCV_STATE = SYNC and RDRF = '0' then + PE <= PE_I; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + PE <= '0'; -- Clear when reading the data register. + end if; + end if; + end process PARITY_TEST; + + P_RDRF: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RDRF <= '0'; + elsif RCV_STATE = SYNC then + RDRF <= '1'; -- Data register is full until now! + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process P_RDRF; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + begin + case RCV_STATE is + when IDLE => + if RXDATA_S = '0' and CDS = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif RXDATA_S = '0' and CDS = "01" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + elsif RXDATA_S = '0' and CDS = "10" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. + else + RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. + end if; + else + RCV_NEXT_STATE <= WAIT_START; -- Stay. + end if; + when SAMPLE => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif WS = "100" or WS = "101" then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= STOP1; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif WS = "000" or WS = "001" or WS = "100" then + RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd new file mode 100644 index 0000000..60a7885 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd @@ -0,0 +1,135 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA : inout std_logic_vector(7 downto 0); + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out std_logic; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP; + +architecture STRUCTURE of WF6850IP_TOP is +component WF6850IP_TOP_SOC + port ( + CLK : in bit; + RESETn : in bit; + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end component; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +signal IRQ_In : bit; +begin + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + + I_UART: WF6850IP_TOP_SOC + port map(CLK => CLK, + RESETn => RESETn, + CS2n => CS2n, + CS1 => CS1, + CS0 => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + TXCLK => TXCLK, + RXCLK => RXCLK, + RXDATA => RXDATA, + CTSn => CTSn, + DCDn => DCDn, + IRQn => IRQ_In, + TXDATA => TXDATA, + RTSn => RTSn + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd new file mode 100644 index 0000000..cbca6bd --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -0,0 +1,255 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP_SOC is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP_SOC; + +architecture STRUCTURE of WF6850IP_TOP_SOC is +component WF6850IP_CTRL_STATUS + port ( + CLK : in bit; + RESETn : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + RDRF : in bit; + TDRE : in bit; + DCDn : in bit; + CTSn : in bit; + FE : in bit; + OVR : in bit; + PE : in bit; + MCLR : out bit; + RTSn : out bit; + CDS : out bit_vector(1 downto 0); + WS : out bit_vector(2 downto 0); + TC : out bit_vector(1 downto 0); + IRQn : out bit + ); +end component; + +component WF6850IP_RECEIVE + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + RXCLK : in bit; + RXDATA : in bit; + RDRF : out bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF6850IP_TRANSMIT + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + CTSn : in bit; + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + TXCLK : in bit; + TDRE : out bit; + TXDATA : out bit + ); +end component; +signal DATA_IN_I : bit_vector(7 downto 0); +signal DATA_RX : bit_vector(7 downto 0); +signal DATA_RX_EN : bit; +signal DATA_CTRL : bit_vector(7 downto 0); +signal DATA_CTRL_EN : bit; +signal RDRF_I : bit; +signal TDRE_I : bit; +signal FE_I : bit; +signal OVR_I : bit; +signal PE_I : bit; +signal MCLR_I : bit; +signal CDS_I : bit_vector(1 downto 0); +signal WS_I : bit_vector(2 downto 0); +signal TC_I : bit_vector(1 downto 0); +signal IRQ_In : bit; +begin + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; + DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else + To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); + + IRQn <= '0' when IRQ_In = '0' else '1'; + + I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS + port map( + CLK => CLK, + RESETn => RESETn, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_CTRL, + DATA_EN => DATA_CTRL_EN, + RDRF => RDRF_I, + TDRE => TDRE_I, + DCDn => DCDn, + CTSn => CTSn, + FE => FE_I, + OVR => OVR_I, + PE => PE_I, + MCLR => MCLR_I, + RTSn => RTSn, + CDS => CDS_I, + WS => WS_I, + TC => TC_I, + IRQn => IRQ_In + ); + + I_UART_RECEIVE: WF6850IP_RECEIVE + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_OUT => DATA_RX, + DATA_EN => DATA_RX_EN, + WS => WS_I, + CDS => CDS_I, + RXCLK => RXCLK, + RXDATA => RXDATA, + RDRF => RDRF_I, + OVR => OVR_I, + PE => PE_I, + FE => FE_I + ); + + I_UART_TRANSMIT: WF6850IP_TRANSMIT + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + CTSn => CTSn, + TC => TC_I, + WS => WS_I, + CDS => CDS_I, + TDRE => TDRE_I, + TXCLK => TXCLK, + TXDATA => TXDATA + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak new file mode 100644 index 0000000..6f80a67 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak @@ -0,0 +1,252 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP_SOC is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP_SOC; + +architecture STRUCTURE of WF6850IP_TOP_SOC is +component WF6850IP_CTRL_STATUS + port ( + CLK : in bit; + RESETn : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + RDRF : in bit; + TDRE : in bit; + DCDn : in bit; + CTSn : in bit; + FE : in bit; + OVR : in bit; + PE : in bit; + MCLR : out bit; + RTSn : out bit; + CDS : out bit_vector(1 downto 0); + WS : out bit_vector(2 downto 0); + TC : out bit_vector(1 downto 0); + IRQn : out bit + ); +end component; + +component WF6850IP_RECEIVE + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + RXCLK : in bit; + RXDATA : in bit; + RDRF : out bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF6850IP_TRANSMIT + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + CTSn : in bit; + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + TXCLK : in bit; + TDRE : out bit; + TXDATA : out bit + ); +end component; +signal DATA_IN_I : bit_vector(7 downto 0); +signal DATA_RX : bit_vector(7 downto 0); +signal DATA_RX_EN : bit; +signal DATA_CTRL : bit_vector(7 downto 0); +signal DATA_CTRL_EN : bit; +signal RDRF_I : bit; +signal TDRE_I : bit; +signal FE_I : bit; +signal OVR_I : bit; +signal PE_I : bit; +signal MCLR_I : bit; +signal CDS_I : bit_vector(1 downto 0); +signal WS_I : bit_vector(2 downto 0); +signal TC_I : bit_vector(1 downto 0); +signal IRQ_In : bit; +begin + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; + DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else + To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); + + IRQn <= '0' when IRQ_In = '0' else '1'; + + I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS + port map( + CLK => CLK, + RESETn => RESETn, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_CTRL, + DATA_EN => DATA_CTRL_EN, + RDRF => RDRF_I, + TDRE => TDRE_I, + DCDn => DCDn, + CTSn => CTSn, + FE => FE_I, + OVR => OVR_I, + PE => PE_I, + MCLR => MCLR_I, + RTSn => RTSn, + CDS => CDS_I, + WS => WS_I, + TC => TC_I, + IRQn => IRQ_In + ); + + I_UART_RECEIVE: WF6850IP_RECEIVE + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_OUT => DATA_RX, + DATA_EN => DATA_RX_EN, + WS => WS_I, + CDS => CDS_I, + RXCLK => RXCLK, + RXDATA => RXDATA, + RDRF => RDRF_I, + OVR => OVR_I, + PE => PE_I, + FE => FE_I + ); + + I_UART_TRANSMIT: WF6850IP_TRANSMIT + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + CTSn => CTSn, + TC => TC_I, + WS => WS_I, + CDS => CDS_I, + TDRE => TDRE_I, + TXCLK => TXCLK, + TXDATA => TXDATA + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd new file mode 100644 index 0000000..c8ae6fc --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd @@ -0,0 +1,339 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's transmitter unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/11/01 WF +-- Fixed the T_DRE process concerning the TDRE <= '1' setting. +-- Thanks to Lyndon Amsdon finding the bug. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TRANSMIT is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + + CTSn : in bit; + + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + TXCLK : in bit; + + TDRE : buffer bit; + TXDATA : out bit + ); +end entity WF6850IP_TRANSMIT; + +architecture BEHAVIOR of WF6850IP_TRANSMIT is +type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +begin + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + TXDATA <= '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- divider off + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif TR_STATE = IDLE then + -- preset the CLKDIV with the start delays + if CDS = "01" then + CLK_DIVCNT := "0010000"; -- div by 16 mode + elsif CDS = "10" then + CLK_DIVCNT := "1000000"; -- div by 64 mode + end if; + CLK_STRB <= '0'; + else + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. + elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= DATA_IN; -- 8 bit data mode. + end if; + end if; + end process DATAREG; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif TR_STATE = LOAD_SHFT and TDRE = '0' then + -- If during LOAD_SHIFT the transmitter data register + -- is empty (TDRE = '1') the shift register will not + -- be loaded. When additionally TC = "11", the break + -- character (zero data and no stop bits) is sent. + SHIFT_REG <= DATA_REG; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + P_TDRE: process(RESETn, CLK) + -- Transmit data register empty flag. + variable LOCK : boolean; + begin + if RESETn = '0' then + TDRE <= '1'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TDRE <= '1'; + elsif TR_NEXT_STATE = START and TR_STATE /= START then + -- Data has been loaded to shift register, thus data register is free again. + -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once + -- entering the state now. + TDRE <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then + LOCK := true; + elsif E = '0' and LOCK = true then + -- This construction clears TDRE after the falling edge of E + -- and after the transmit data register has been written to. + TDRE <= '0'; + LOCK := false; + end if; + end if; + end process P_TDRE; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PARITY_I <= PAR_TMP; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity for WS = "100" and WS = "101". + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TR_STATE <= IDLE; + else + TR_STATE <= TR_NEXT_STATE; + end if; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) + begin + case TR_STATE is + when IDLE => + if TDRE = '1' and TC = "11" then + TR_NEXT_STATE <= LOAD_SHFT; + elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif WS = "100" or WS = "101" then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then + TR_NEXT_STATE <= STOP2; -- Two stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak new file mode 100644 index 0000000..bcff094 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak @@ -0,0 +1,339 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's transmitter unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/11/01 WF +-- Fixed the T_DRE process concerning the TDRE <= '1' setting. +-- Thanks to Lyndon Amsdon finding the bug. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TRANSMIT is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + + CTSn : in bit; + + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + TXCLK : in bit; + + TDRE : buffer bit; + TXDATA : out bit + ); +end entity WF6850IP_TRANSMIT; + +architecture BEHAVIOR of WF6850IP_TRANSMIT is +type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +begin + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + TXDATA <= '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- divider off + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif TR_STATE = IDLE then + -- preset the CLKDIV with the start delays + if CDS = "01" then + CLK_DIVCNT := "0010000"; -- div by 16 mode + elsif CDS = "10" then + CLK_DIVCNT := "1000000"; -- div by 64 mode + end if; + CLK_STRB <= '0'; + else + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. + elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= DATA_IN; -- 8 bit data mode. + end if; + end if; + end process DATAREG; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif TR_STATE = LOAD_SHFT and TDRE = '0' then + -- If during LOAD_SHIFT the transmitter data register + -- is empty (TDRE = '1') the shift register will not + -- be loaded. When additionally TC = "11", the break + -- character (zero data and no stop bits) is sent. + SHIFT_REG <= DATA_REG; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + P_TDRE: process(RESETn, CLK) + -- Transmit data register empty flag. + variable LOCK : boolean; + begin + if RESETn = '0' then + TDRE <= '1'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TDRE <= '1'; + elsif TR_NEXT_STATE = START and TR_STATE /= START then + -- Data has been loaded to shift register, thus data register is free again. + -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once + -- entering the state now. + TDRE <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then + LOCK := true; + elsif E = '0' and LOCK = true and CS /= "011" then + -- This construction clears TDRE after the falling edge of E + -- and after the transmit data register has been written to. + TDRE <= '0'; + LOCK := false; + end if; + end if; + end process P_TDRE; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PARITY_I <= PAR_TMP; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity for WS = "100" and WS = "101". + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TR_STATE <= IDLE; + else + TR_STATE <= TR_NEXT_STATE; + end if; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) + begin + case TR_STATE is + when IDLE => + if TDRE = '1' and TC = "11" then + TR_NEXT_STATE <= LOAD_SHFT; + elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif WS = "100" or WS = "101" then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then + TR_NEXT_STATE <= STOP2; -- Two stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.bsf b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.bsf new file mode 100644 index 0000000..f4d66a5 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.bsf @@ -0,0 +1,95 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) + (text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (drawing + (text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.cmp b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.cmp new file mode 100644 index 0000000..1f8ad52 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.cmp @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component dcfifo0 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.qip b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.qip new file mode 100644 index 0000000..a22ffe4 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"] diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd new file mode 100644 index 0000000..9db22fa --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo0.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +END dcfifo0; + + +ARCHITECTURE SYN OF dcfifo0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(9 DOWNTO 0); + q <= sub_wire1(31 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 1024, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 8, + lpm_widthu => 10, + lpm_widthu_r => 8, + lpm_width_r => 32, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "1024" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "32" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0] +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak new file mode 100644 index 0000000..c3ca670 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo0.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END dcfifo0; + + +ARCHITECTURE SYN OF dcfifo0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(4 DOWNTO 0); + q <= sub_wire1(15 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 32, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 8, + lpm_widthu => 5, + lpm_widthu_r => 4, + lpm_width_r => 16, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "32" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "16" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0] +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.bsf b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.bsf new file mode 100644 index 0000000..7a4a386 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.bsf @@ -0,0 +1,95 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 96) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) + (text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 3)) + ) + (drawing + (text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.cmp b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.cmp new file mode 100644 index 0000000..a1b8d55 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.cmp @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component dcfifo1 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.qip b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.qip new file mode 100644 index 0000000..bf1428c --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"] diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd new file mode 100644 index 0000000..d05dd0a --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo1.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo1 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +END dcfifo1; + + +ARCHITECTURE SYN OF dcfifo1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + rdusedw <= sub_wire1(9 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 256, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 32, + lpm_widthu => 8, + lpm_widthu_r => 10, + lpm_width_r => 8, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + q => sub_wire0, + rdusedw => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "256" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "32" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0] +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak new file mode 100644 index 0000000..e7c6ae6 --- /dev/null +++ b/FPGA_quartus/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo1.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo1 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END dcfifo1; + + +ARCHITECTURE SYN OF dcfifo1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(3 DOWNTO 0); + q <= sub_wire1(7 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 16, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 16, + lpm_widthu => 4, + lpm_widthu_r => 5, + lpm_width_r => 8, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "16" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "16" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0] +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf b/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf new file mode 100644 index 0000000..a455469 --- /dev/null +++ b/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf @@ -0,0 +1,478 @@ +TITLE "INTERRUPT HANDLER UND C1287"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_LONG.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + + +-- Parameters Statement (optional) + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + + +-- Subdesign Section + +SUBDESIGN interrupt_handler +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; + ANZAHL_TAGE_DES_MONATS[7..0]:NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; + +BEGIN +-- BYT SELECT + FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR[].CLK = MAIN_CLK; + INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 + INT_CTR[] = FB_AD[]; + INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; + INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; + INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; + INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA[].CLK = MAIN_CLK; + INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 + INT_ENA[] = FB_AD[]; + INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; + INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; + INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; + INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR[].CLK = MAIN_CLK; + INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 + INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; + INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; + INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; + INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT LATCH REGISTER READ ONLY + INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 +-- INTERRUPT + !nIRQ2 = HSYNC & INT_ENA[26]; + !nIRQ3 = INT_CTR0 & INT_ENA[27]; + !nIRQ4 = VSYNC & INT_ENA[28]; + nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ6 = !nMFP_INT & INT_ENA[30]; + !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; + +PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME + # FB_ADR[19..4]==H"F920" -- PADDLE + # FB_ADR[19..4]==H"F921" -- PADDLE + # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR + # FB_ADR[19..4]==H"F890" -- DMA SOUND + # FB_ADR[19..4]==H"F891" -- DMA SOUND + # FB_ADR[19..4]==H"F892"); -- DMA SOUND +-- IF VIDEO ADR CHANGE +TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 + +-- INTERRUPT LATCH + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; + INT_LATCH1.CLK = E0_INT & INT_ENA[1]; + INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; + INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; + INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; + INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; + INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; + INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; + INT_LATCH8.CLK = VSYNC & INT_ENA[8]; + INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + +-- INTERRUPT CLEAR + INT_LATCH[].CLRN = !INT_CLEAR[]; + +-- INT_IN + INT_IN0 = PIC_INT; + INT_IN1 = E0_INT; + INT_IN2 = DVI_INT; + INT_IN3 = !nPCI_INTA; + INT_IN4 = !nPCI_INTB; + INT_IN5 = !nPCI_INTC; + INT_IN6 = !nPCI_INTD; + INT_IN7 = DSP_INT; + INT_IN8 = VSYNC; + INT_IN9 = HSYNC; + INT_IN[25..10] = H"0"; + INT_IN26 = HSYNC; + INT_IN27 = INT_CTR0; + INT_IN28 = VSYNC; + INT_IN29 = INT_LATCH[]!=H"00000000"; + INT_IN30 = !nMFP_INT; + INT_IN31 = DMA_DRQ; +--*************************************************************************************** +-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF[].CLK = MAIN_CLK; + ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 + ACP_CONF[] = FB_AD[]; + ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; + ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; + ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; + ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; +--*************************************************************************************** + +-------------------------------------------------------------- +-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR +---------------------------------------------------------- + RTC_ADR[].CLK = MAIN_CLK; + RTC_ADR[] = FB_AD[21..16]; + UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 + UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 + RTC_ADR[].ENA = UHR_AS & !nFB_WR; + WERTE[][].CLK = MAIN_CLK; + WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[7..0][1] = FB_AD[23..16]; + WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[7..0][3] = FB_AD[23..16]; + WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[7..0][5] = FB_AD[23..16]; + WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[7..0][10] = FB_AD[23..16]; + WERTE[7..0][11] = FB_AD[23..16]; + WERTE[7..0][12] = FB_AD[23..16]; + WERTE[7..0][13] = FB_AD[23..16]; + WERTE[7..0][14] = FB_AD[23..16]; + WERTE[7..0][15] = FB_AD[23..16]; + WERTE[7..0][16] = FB_AD[23..16]; + WERTE[7..0][17] = FB_AD[23..16]; + WERTE[7..0][18] = FB_AD[23..16]; + WERTE[7..0][19] = FB_AD[23..16]; + WERTE[7..0][20] = FB_AD[23..16]; + WERTE[7..0][21] = FB_AD[23..16]; + WERTE[7..0][22] = FB_AD[23..16]; + WERTE[7..0][23] = FB_AD[23..16]; + WERTE[7..0][24] = FB_AD[23..16]; + WERTE[7..0][25] = FB_AD[23..16]; + WERTE[7..0][26] = FB_AD[23..16]; + WERTE[7..0][27] = FB_AD[23..16]; + WERTE[7..0][28] = FB_AD[23..16]; + WERTE[7..0][29] = FB_AD[23..16]; + WERTE[7..0][30] = FB_AD[23..16]; + WERTE[7..0][31] = FB_AD[23..16]; + WERTE[7..0][32] = FB_AD[23..16]; + WERTE[7..0][33] = FB_AD[23..16]; + WERTE[7..0][34] = FB_AD[23..16]; + WERTE[7..0][35] = FB_AD[23..16]; + WERTE[7..0][36] = FB_AD[23..16]; + WERTE[7..0][37] = FB_AD[23..16]; + WERTE[7..0][38] = FB_AD[23..16]; + WERTE[7..0][39] = FB_AD[23..16]; + WERTE[7..0][40] = FB_AD[23..16]; + WERTE[7..0][41] = FB_AD[23..16]; + WERTE[7..0][42] = FB_AD[23..16]; + WERTE[7..0][43] = FB_AD[23..16]; + WERTE[7..0][44] = FB_AD[23..16]; + WERTE[7..0][45] = FB_AD[23..16]; + WERTE[7..0][46] = FB_AD[23..16]; + WERTE[7..0][47] = FB_AD[23..16]; + WERTE[7..0][48] = FB_AD[23..16]; + WERTE[7..0][49] = FB_AD[23..16]; + WERTE[7..0][50] = FB_AD[23..16]; + WERTE[7..0][51] = FB_AD[23..16]; + WERTE[7..0][52] = FB_AD[23..16]; + WERTE[7..0][53] = FB_AD[23..16]; + WERTE[7..0][54] = FB_AD[23..16]; + WERTE[7..0][55] = FB_AD[23..16]; + WERTE[7..0][56] = FB_AD[23..16]; + WERTE[7..0][57] = FB_AD[23..16]; + WERTE[7..0][58] = FB_AD[23..16]; + WERTE[7..0][59] = FB_AD[23..16]; + WERTE[7..0][60] = FB_AD[23..16]; + WERTE[7..0][61] = FB_AD[23..16]; + WERTE[7..0][62] = FB_AD[23..16]; + WERTE[7..0][63] = FB_AD[23..16]; + WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; + WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; + WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; + WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; + WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; + WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; + WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; + WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; + WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; + WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; + WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; + WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; + WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; + WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; + WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; + WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; + WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; + WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; + WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; + WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; + WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; + WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; + WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; + WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; + WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; + WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; + WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; + WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; + WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; + WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; + WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; + WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; + WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; + WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; + WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; + WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; + WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; + WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; + WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; + WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; + WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; + WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; + WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; + WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; + WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; + WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; + WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; + WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; + WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; + WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; + WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; + WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; + WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; + WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; + WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; + WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; + WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; + PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; + PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; + WERTE[6][10].CLRN = GND; -- KEIN UIP + UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF + WERTE[2][11] = VCC; -- IMMER BINARY + WERTE[1][11] = VCC; -- IMMER 24H FORMAT + WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR + WERTE[7][13] = VCC; -- IMMER RICHTIG +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL + WERTE[0][13] = SOMMERZEIT; + WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); + WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN[].CLK = MAIN_CLK; + ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; + ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; +-- SEKUNDEN + INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); +-- MINUTEN + INC_MIN = INC_SEC & WERTE[][0]==59; -- + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- +-- STUNDEN + INC_STD = INC_MIN & WERTE[][2]==59; + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT +-- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); + ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) + # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) + # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 + # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- +-- MONATE + INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); +-- JAHR + INC_JAHR = INC_MONAT & WERTE[][8]==12; -- + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); +-- TRISTATE OUTPUT + + FB_AD[31..24] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[31..24] + # INT_ENA_CS & INT_ENA[31..24] + # INT_LATCH_CS & INT_LATCH[31..24] + # INT_CLEAR_CS & INT_IN[31..24] + # ACP_CONF_CS & ACP_CONF[31..24] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[23..16] = lpm_bustri_BYT( + WERTE[][0] & RTC_ADR[]==0 & UHR_DS + # WERTE[][1] & RTC_ADR[]==1 & UHR_DS + # WERTE[][2] & RTC_ADR[]==2 & UHR_DS + # WERTE[][3] & RTC_ADR[]==3 & UHR_DS + # WERTE[][4] & RTC_ADR[]==4 & UHR_DS + # WERTE[][5] & RTC_ADR[]==5 & UHR_DS + # WERTE[][6] & RTC_ADR[]==6 & UHR_DS + # WERTE[][7] & RTC_ADR[]==7 & UHR_DS + # WERTE[][8] & RTC_ADR[]==8 & UHR_DS + # WERTE[][9] & RTC_ADR[]==9 & UHR_DS + # WERTE[][10] & RTC_ADR[]==10 & UHR_DS + # WERTE[][11] & RTC_ADR[]==11 & UHR_DS + # WERTE[][12] & RTC_ADR[]==12 & UHR_DS + # WERTE[][13] & RTC_ADR[]==13 & UHR_DS + # WERTE[][14] & RTC_ADR[]==14 & UHR_DS + # WERTE[][15] & RTC_ADR[]==15 & UHR_DS + # WERTE[][16] & RTC_ADR[]==16 & UHR_DS + # WERTE[][17] & RTC_ADR[]==17 & UHR_DS + # WERTE[][18] & RTC_ADR[]==18 & UHR_DS + # WERTE[][19] & RTC_ADR[]==19 & UHR_DS + # WERTE[][20] & RTC_ADR[]==20 & UHR_DS + # WERTE[][21] & RTC_ADR[]==21 & UHR_DS + # WERTE[][22] & RTC_ADR[]==22 & UHR_DS + # WERTE[][23] & RTC_ADR[]==23 & UHR_DS + # WERTE[][24] & RTC_ADR[]==24 & UHR_DS + # WERTE[][25] & RTC_ADR[]==25 & UHR_DS + # WERTE[][26] & RTC_ADR[]==26 & UHR_DS + # WERTE[][27] & RTC_ADR[]==27 & UHR_DS + # WERTE[][28] & RTC_ADR[]==28 & UHR_DS + # WERTE[][29] & RTC_ADR[]==29 & UHR_DS + # WERTE[][30] & RTC_ADR[]==30 & UHR_DS + # WERTE[][31] & RTC_ADR[]==31 & UHR_DS + # WERTE[][32] & RTC_ADR[]==32 & UHR_DS + # WERTE[][33] & RTC_ADR[]==33 & UHR_DS + # WERTE[][34] & RTC_ADR[]==34 & UHR_DS + # WERTE[][35] & RTC_ADR[]==35 & UHR_DS + # WERTE[][36] & RTC_ADR[]==36 & UHR_DS + # WERTE[][37] & RTC_ADR[]==37 & UHR_DS + # WERTE[][38] & RTC_ADR[]==38 & UHR_DS + # WERTE[][39] & RTC_ADR[]==39 & UHR_DS + # WERTE[][40] & RTC_ADR[]==40 & UHR_DS + # WERTE[][41] & RTC_ADR[]==41 & UHR_DS + # WERTE[][42] & RTC_ADR[]==42 & UHR_DS + # WERTE[][43] & RTC_ADR[]==43 & UHR_DS + # WERTE[][44] & RTC_ADR[]==44 & UHR_DS + # WERTE[][45] & RTC_ADR[]==45 & UHR_DS + # WERTE[][46] & RTC_ADR[]==46 & UHR_DS + # WERTE[][47] & RTC_ADR[]==47 & UHR_DS + # WERTE[][48] & RTC_ADR[]==48 & UHR_DS + # WERTE[][49] & RTC_ADR[]==49 & UHR_DS + # WERTE[][50] & RTC_ADR[]==50 & UHR_DS + # WERTE[][51] & RTC_ADR[]==51 & UHR_DS + # WERTE[][52] & RTC_ADR[]==52 & UHR_DS + # WERTE[][53] & RTC_ADR[]==53 & UHR_DS + # WERTE[][54] & RTC_ADR[]==54 & UHR_DS + # WERTE[][55] & RTC_ADR[]==55 & UHR_DS + # WERTE[][56] & RTC_ADR[]==56 & UHR_DS + # WERTE[][57] & RTC_ADR[]==57 & UHR_DS + # WERTE[][58] & RTC_ADR[]==58 & UHR_DS + # WERTE[][59] & RTC_ADR[]==59 & UHR_DS + # WERTE[][60] & RTC_ADR[]==60 & UHR_DS + # WERTE[][61] & RTC_ADR[]==61 & UHR_DS + # WERTE[][62] & RTC_ADR[]==62 & UHR_DS + # WERTE[][63] & RTC_ADR[]==63 & UHR_DS + # (0,RTC_ADR[]) & UHR_AS + # INT_CTR_CS & INT_CTR[23..16] + # INT_ENA_CS & INT_ENA[23..16] + # INT_LATCH_CS & INT_LATCH[23..16] + # INT_CLEAR_CS & INT_IN[23..16] + # ACP_CONF_CS & ACP_CONF[23..16] + ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[15..8] + # INT_ENA_CS & INT_ENA[15..8] + # INT_LATCH_CS & INT_LATCH[15..8] + # INT_CLEAR_CS & INT_IN[15..8] + # ACP_CONF_CS & ACP_CONF[15..8] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[7..0] + # INT_ENA_CS & INT_ENA[7..0] + # INT_LATCH_CS & INT_LATCH[7..0] + # INT_CLEAR_CS & INT_IN[7..0] + # ACP_CONF_CS & ACP_CONF[7..0] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + + INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; +END; + + diff --git a/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf.bak new file mode 100644 index 0000000..e3e49eb --- /dev/null +++ b/FPGA_quartus/Interrupt_Handler/interrupt_handler.tdf.bak @@ -0,0 +1,478 @@ +TITLE "INTERRUPT HANDLER UND C1287"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_LONG.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + + +-- Parameters Statement (optional) + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + + +-- Subdesign Section + +SUBDESIGN interrupt_handler +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; + ANZAHL_TAGE_DES_MONATS[7..0]:NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; + +BEGIN +-- BYT SELECT + FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR[].CLK = MAIN_CLK; + INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 + INT_CTR[] = FB_AD[]; + INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; + INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; + INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; + INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA[].CLK = MAIN_CLK; + INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 + INT_ENA[] = FB_AD[]; + INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; + INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; + INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; + INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR[].CLK = MAIN_CLK; + INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 + INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; + INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; + INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; + INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT LATCH REGISTER READ ONLY + INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 +-- INTERRUPT + !nIRQ2 = HSYNC & INT_ENA[26]; + !nIRQ3 = INT_CTR0 & INT_ENA[27]; + !nIRQ4 = VSYNC & INT_ENA[28]; + nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ6 = !nMFP_INT & INT_ENA[30]; + !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; + +PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME + # FB_ADR[19..4]==H"F920" -- PADDLE + # FB_ADR[19..4]==H"F921" -- PADDLE + # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR + # FB_ADR[19..4]==H"F890" -- DMA SOUND + # FB_ADR[19..4]==H"F891" -- DMA SOUND + # FB_ADR[19..4]==H"F892"); -- DMA SOUND +-- IF VIDEO ADR CHANGE +TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2 + +-- INTERRUPT LATCH + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; + INT_LATCH1.CLK = E0_INT & INT_ENA[1]; + INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; + INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; + INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; + INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; + INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; + INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; + INT_LATCH8.CLK = VSYNC & INT_ENA[8]; + INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + +-- INTERRUPT CLEAR + INT_LATCH[].CLRN = !INT_CLEAR[]; + +-- INT_IN + INT_IN0 = PIC_INT; + INT_IN1 = E0_INT; + INT_IN2 = DVI_INT; + INT_IN3 = !nPCI_INTA; + INT_IN4 = !nPCI_INTB; + INT_IN5 = !nPCI_INTC; + INT_IN6 = !nPCI_INTD; + INT_IN7 = DSP_INT; + INT_IN8 = VSYNC; + INT_IN9 = HSYNC; + INT_IN[25..10] = H"0"; + INT_IN26 = HSYNC; + INT_IN27 = INT_CTR0; + INT_IN28 = VSYNC; + INT_IN29 = INT_LATCH[]!=H"00000000"; + INT_IN30 = !nMFP_INT; + INT_IN31 = DMA_DRQ; +--*************************************************************************************** +-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF[].CLK = MAIN_CLK; + ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 + ACP_CONF[] = FB_AD[]; + ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; + ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; + ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; + ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; +--*************************************************************************************** + +-------------------------------------------------------------- +-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR +---------------------------------------------------------- + RTC_ADR[].CLK = MAIN_CLK; + RTC_ADR[] = FB_AD[21..16]; + UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 + UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 + RTC_ADR[].ENA = UHR_AS & !nFB_WR; + WERTE[][].CLK = MAIN_CLK; + WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[7..0][1] = FB_AD[23..16]; + WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[7..0][3] = FB_AD[23..16]; + WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[7..0][5] = FB_AD[23..16]; + WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[7..0][10] = FB_AD[23..16]; + WERTE[7..0][11] = FB_AD[23..16]; + WERTE[7..0][12] = FB_AD[23..16]; + WERTE[7..0][13] = FB_AD[23..16]; + WERTE[7..0][14] = FB_AD[23..16]; + WERTE[7..0][15] = FB_AD[23..16]; + WERTE[7..0][16] = FB_AD[23..16]; + WERTE[7..0][17] = FB_AD[23..16]; + WERTE[7..0][18] = FB_AD[23..16]; + WERTE[7..0][19] = FB_AD[23..16]; + WERTE[7..0][20] = FB_AD[23..16]; + WERTE[7..0][21] = FB_AD[23..16]; + WERTE[7..0][22] = FB_AD[23..16]; + WERTE[7..0][23] = FB_AD[23..16]; + WERTE[7..0][24] = FB_AD[23..16]; + WERTE[7..0][25] = FB_AD[23..16]; + WERTE[7..0][26] = FB_AD[23..16]; + WERTE[7..0][27] = FB_AD[23..16]; + WERTE[7..0][28] = FB_AD[23..16]; + WERTE[7..0][29] = FB_AD[23..16]; + WERTE[7..0][30] = FB_AD[23..16]; + WERTE[7..0][31] = FB_AD[23..16]; + WERTE[7..0][32] = FB_AD[23..16]; + WERTE[7..0][33] = FB_AD[23..16]; + WERTE[7..0][34] = FB_AD[23..16]; + WERTE[7..0][35] = FB_AD[23..16]; + WERTE[7..0][36] = FB_AD[23..16]; + WERTE[7..0][37] = FB_AD[23..16]; + WERTE[7..0][38] = FB_AD[23..16]; + WERTE[7..0][39] = FB_AD[23..16]; + WERTE[7..0][40] = FB_AD[23..16]; + WERTE[7..0][41] = FB_AD[23..16]; + WERTE[7..0][42] = FB_AD[23..16]; + WERTE[7..0][43] = FB_AD[23..16]; + WERTE[7..0][44] = FB_AD[23..16]; + WERTE[7..0][45] = FB_AD[23..16]; + WERTE[7..0][46] = FB_AD[23..16]; + WERTE[7..0][47] = FB_AD[23..16]; + WERTE[7..0][48] = FB_AD[23..16]; + WERTE[7..0][49] = FB_AD[23..16]; + WERTE[7..0][50] = FB_AD[23..16]; + WERTE[7..0][51] = FB_AD[23..16]; + WERTE[7..0][52] = FB_AD[23..16]; + WERTE[7..0][53] = FB_AD[23..16]; + WERTE[7..0][54] = FB_AD[23..16]; + WERTE[7..0][55] = FB_AD[23..16]; + WERTE[7..0][56] = FB_AD[23..16]; + WERTE[7..0][57] = FB_AD[23..16]; + WERTE[7..0][58] = FB_AD[23..16]; + WERTE[7..0][59] = FB_AD[23..16]; + WERTE[7..0][60] = FB_AD[23..16]; + WERTE[7..0][61] = FB_AD[23..16]; + WERTE[7..0][62] = FB_AD[23..16]; + WERTE[7..0][63] = FB_AD[23..16]; + WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; + WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; + WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; + WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; + WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; + WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; + WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; + WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; + WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; + WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; + WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; + WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; + WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; + WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; + WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; + WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; + WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; + WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; + WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; + WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; + WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; + WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; + WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; + WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; + WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; + WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; + WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; + WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; + WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; + WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; + WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; + WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; + WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; + WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; + WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; + WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; + WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; + WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; + WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; + WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; + WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; + WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; + WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; + WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; + WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; + WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; + WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; + WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; + WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; + WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; + WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; + WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; + WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; + WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; + WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; + WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; + WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; + PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; + PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; + WERTE[6][10].CLRN = GND; -- KEIN UIP + UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF + WERTE[2][11] = VCC; -- IMMER BINARY + WERTE[1][11] = VCC; -- IMMER 24H FORMAT + WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR + WERTE[7][13] = VCC; -- IMMER RICHTIG +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL + WERTE[0][13] = SOMMERZEIT; + WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); + WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN[].CLK = MAIN_CLK; + ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; + ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; +-- SEKUNDEN + INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); +-- MINUTEN + INC_MIN = INC_SEC & WERTE[][0]==59; -- + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- +-- STUNDEN + INC_STD = INC_MIN & WERTE[][2]==59; + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT +-- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); + ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) + # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) + # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 + # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- +-- MONATE + INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); +-- JAHR + INC_JAHR = INC_MONAT & WERTE[][8]==12; -- + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); +-- TRISTATE OUTPUT + + FB_AD[31..24] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[31..24] + # INT_ENA_CS & INT_ENA[31..24] + # INT_LATCH_CS & INT_LATCH[31..24] + # INT_CLEAR_CS & INT_IN[31..24] + # ACP_CONF_CS & ACP_CONF[31..24] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[23..16] = lpm_bustri_BYT( + WERTE[][0] & RTC_ADR[]==0 & UHR_DS + # WERTE[][1] & RTC_ADR[]==1 & UHR_DS + # WERTE[][2] & RTC_ADR[]==2 & UHR_DS + # WERTE[][3] & RTC_ADR[]==3 & UHR_DS + # WERTE[][4] & RTC_ADR[]==4 & UHR_DS + # WERTE[][5] & RTC_ADR[]==5 & UHR_DS + # WERTE[][6] & RTC_ADR[]==6 & UHR_DS + # WERTE[][7] & RTC_ADR[]==7 & UHR_DS + # WERTE[][8] & RTC_ADR[]==8 & UHR_DS + # WERTE[][9] & RTC_ADR[]==9 & UHR_DS + # WERTE[][10] & RTC_ADR[]==10 & UHR_DS + # WERTE[][11] & RTC_ADR[]==11 & UHR_DS + # WERTE[][12] & RTC_ADR[]==12 & UHR_DS + # WERTE[][13] & RTC_ADR[]==13 & UHR_DS + # WERTE[][14] & RTC_ADR[]==14 & UHR_DS + # WERTE[][15] & RTC_ADR[]==15 & UHR_DS + # WERTE[][16] & RTC_ADR[]==16 & UHR_DS + # WERTE[][17] & RTC_ADR[]==17 & UHR_DS + # WERTE[][18] & RTC_ADR[]==18 & UHR_DS + # WERTE[][19] & RTC_ADR[]==19 & UHR_DS + # WERTE[][20] & RTC_ADR[]==20 & UHR_DS + # WERTE[][21] & RTC_ADR[]==21 & UHR_DS + # WERTE[][22] & RTC_ADR[]==22 & UHR_DS + # WERTE[][23] & RTC_ADR[]==23 & UHR_DS + # WERTE[][24] & RTC_ADR[]==24 & UHR_DS + # WERTE[][25] & RTC_ADR[]==25 & UHR_DS + # WERTE[][26] & RTC_ADR[]==26 & UHR_DS + # WERTE[][27] & RTC_ADR[]==27 & UHR_DS + # WERTE[][28] & RTC_ADR[]==28 & UHR_DS + # WERTE[][29] & RTC_ADR[]==29 & UHR_DS + # WERTE[][30] & RTC_ADR[]==30 & UHR_DS + # WERTE[][31] & RTC_ADR[]==31 & UHR_DS + # WERTE[][32] & RTC_ADR[]==32 & UHR_DS + # WERTE[][33] & RTC_ADR[]==33 & UHR_DS + # WERTE[][34] & RTC_ADR[]==34 & UHR_DS + # WERTE[][35] & RTC_ADR[]==35 & UHR_DS + # WERTE[][36] & RTC_ADR[]==36 & UHR_DS + # WERTE[][37] & RTC_ADR[]==37 & UHR_DS + # WERTE[][38] & RTC_ADR[]==38 & UHR_DS + # WERTE[][39] & RTC_ADR[]==39 & UHR_DS + # WERTE[][40] & RTC_ADR[]==40 & UHR_DS + # WERTE[][41] & RTC_ADR[]==41 & UHR_DS + # WERTE[][42] & RTC_ADR[]==42 & UHR_DS + # WERTE[][43] & RTC_ADR[]==43 & UHR_DS + # WERTE[][44] & RTC_ADR[]==44 & UHR_DS + # WERTE[][45] & RTC_ADR[]==45 & UHR_DS + # WERTE[][46] & RTC_ADR[]==46 & UHR_DS + # WERTE[][47] & RTC_ADR[]==47 & UHR_DS + # WERTE[][48] & RTC_ADR[]==48 & UHR_DS + # WERTE[][49] & RTC_ADR[]==49 & UHR_DS + # WERTE[][50] & RTC_ADR[]==50 & UHR_DS + # WERTE[][51] & RTC_ADR[]==51 & UHR_DS + # WERTE[][52] & RTC_ADR[]==52 & UHR_DS + # WERTE[][53] & RTC_ADR[]==53 & UHR_DS + # WERTE[][54] & RTC_ADR[]==54 & UHR_DS + # WERTE[][55] & RTC_ADR[]==55 & UHR_DS + # WERTE[][56] & RTC_ADR[]==56 & UHR_DS + # WERTE[][57] & RTC_ADR[]==57 & UHR_DS + # WERTE[][58] & RTC_ADR[]==58 & UHR_DS + # WERTE[][59] & RTC_ADR[]==59 & UHR_DS + # WERTE[][60] & RTC_ADR[]==60 & UHR_DS + # WERTE[][61] & RTC_ADR[]==61 & UHR_DS + # WERTE[][62] & RTC_ADR[]==62 & UHR_DS + # WERTE[][63] & RTC_ADR[]==63 & UHR_DS + # (0,RTC_ADR[]) & UHR_AS + # INT_CTR_CS & INT_CTR[23..16] + # INT_ENA_CS & INT_ENA[23..16] + # INT_LATCH_CS & INT_LATCH[23..16] + # INT_CLEAR_CS & INT_IN[23..16] + # ACP_CONF_CS & ACP_CONF[23..16] + ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[15..8] + # INT_ENA_CS & INT_ENA[15..8] + # INT_LATCH_CS & INT_LATCH[15..8] + # INT_CLEAR_CS & INT_IN[15..8] + # ACP_CONF_CS & ACP_CONF[15..8] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[7..0] + # INT_ENA_CS & INT_ENA[7..0] + # INT_LATCH_CS & INT_LATCH[7..0] + # INT_CLEAR_CS & INT_IN[7..0] + # ACP_CONF_CS & ACP_CONF[7..0] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + + INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; +END; + + diff --git a/FPGA_quartus/UNUSED b/FPGA_quartus/UNUSED new file mode 100644 index 0000000..3a7d9e6 --- /dev/null +++ b/FPGA_quartus/UNUSED @@ -0,0 +1,27 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=3; +DEPTH=16; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 00 : 7; + 01 : 6; + 02 : 5; + 03 : 4; + 04 : 3; + 05 : 2; + 06 : 1; + 07 : 0; + 08 : 7; + 09 : 6; + 0a : 5; + 0b : 4; + 0c : 3; + 0d : 2; + 0e : 1; + 0f : 0; +END; diff --git a/FPGA_quartus/Video/BLITTER/BLITTER.vhd b/FPGA_quartus/Video/BLITTER/BLITTER.vhd new file mode 100644 index 0000000..e09ed0b --- /dev/null +++ b/FPGA_quartus/Video/BLITTER/BLITTER.vhd @@ -0,0 +1,75 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Fri Oct 16 15:40:59 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY BLITTER IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END BLITTER; + + +-- Architecture Body + +ARCHITECTURE BLITTER_architecture OF BLITTER IS + + +BEGIN + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + BLITTER_ADR <= x"76543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + +END BLITTER_architecture; diff --git a/FPGA_quartus/Video/BLITTER/BLITTER.vhd.bak b/FPGA_quartus/Video/BLITTER/BLITTER.vhd.bak new file mode 100644 index 0000000..f674080 --- /dev/null +++ b/FPGA_quartus/Video/BLITTER/BLITTER.vhd.bak @@ -0,0 +1,75 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Fri Oct 16 15:40:59 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY BLITTER IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END BLITTER; + + +-- Architecture Body + +ARCHITECTURE BLITTER_architecture OF BLITTER IS + + +BEGIN + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + BLITTER_ADR <= x"FEDCBA9876543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + +END BLITTER_architecture; diff --git a/FPGA_quartus/Video/DDR_CTR.tdf b/FPGA_quartus/Video/DDR_CTR.tdf new file mode 100644 index 0000000..d5b5ec2 --- /dev/null +++ b/FPGA_quartus/Video/DDR_CTR.tdf @@ -0,0 +1,659 @@ +TITLE "DDR_CTR"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + +-- FIFO WATER MARK +CONSTANT FIFO_LWM = 0; +CONSTANT FIFO_MWM = 200; +CONSTANT FIFO_HWM = 500; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + DDRCLK0 : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + BA[1..0] : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + DS_T4R,DS_T5R, -- READ CPU UND BLITTER, + DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER + DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO + DS_CB6, DS_CB8, -- CLOSE FIFO BANK + DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA_P[12..0] :DFF; + BA_P[1..0] :DFF; + VA_S[12..0] :DFF; + BA_S[1..0] :DFF; + MCS[1..0] :DFF; + CPU_DDR_SYNC :DFF; + DDR_SEL :NODE; + DDR_CS :DFFE; + DDR_CONFIG :NODE; + SR_DDR_WR :DFF; + SR_DDRWR_D_SEL :DFF; + SR_VDMP[7..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA[1..0] :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + CPU_AC :DFF; + BUS_CYC :DFF; + BUS_CYC_END :NODE; + BLITTER_REQ :DFF; + BLITTER_AC :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA[1..0] :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_REQ :DFF; + FIFO_AC :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA[1..0] :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_ACTIVE :NODE; + CLR_FIFO_SYNC :DFF; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + SR_FIFO_WRE :DFF; + FIFO_BANK_OK :DFF; + FIFO_BANK_NOT_OK :NODE; + DDR_REFRESH_ON :NODE; + DDR_REFRESH_CNT[10..0] :DFF; + DDR_REFRESH_REQ :DFF; + DDR_REFRESH_SIG[3..0] :DFFE; + REFRESH_TIME :DFF; + VIDEO_BASE_L_D[7..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[2..0] :DFFE; + VIDEO_ADR_CNT[22..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[22..0] :NODE; + VIDEO_ACT_ADR[26..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0 -- ADR==0 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + FB_LE0 = !nFB_WR; + IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + IF DDR_CS THEN + FB_LE0 = !nFB_WR; + VIDEO_DDR_TA = VCC; + IF LINE THEN + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_REGDDR = FR_S1; + ELSE + BUS_CYC_END = VCC; + FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_REGDDR = FR_WAIT; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + IF DDR_CS THEN + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S2; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S2 => + IF DDR_CS THEN + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN + FB_REGDDR = FR_S2; + ELSE + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S3; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S3 => + IF DDR_CS THEN + FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + VIDEO_DDR_TA = VCC; + BUS_CYC_END = VCC; + FB_REGDDR = FR_WAIT; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + DDR_REFRESH_ON = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + FIFO_ACTIVE = VIDEO_RAM_CTR8; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA[] = FB_ADR[13..12]; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + SR_DDR_WR.CLK = DDRCLK0; + SR_DDRWR_D_SEL.CLK = DDRCLK0; + SR_VDMP[7..0].CLK = DDRCLK0; + SR_FIFO_WRE.CLK = DDRCLK0; + CPU_AC.CLK = DDRCLK0; + FIFO_AC.CLK = DDRCLK0; + BLITTER_AC.CLK = DDRCLK0; + DDRWR_D_SEL1 = BLITTER_AC; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; + DDR_CS.CLK = MAIN_CLK; + DDR_CS.ENA = FB_ALE; + DDR_CS = DDR_SEL; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + CPU_REQ.CLK = DDR_SYNC_66M; + CPU_REQ = CPU_SIG + # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG + BUS_CYC.CLK = DDRCLK0; + BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS[].CLK = DDRCLK0; + MCS0 = MAIN_CLK; + MCS1 = MCS0; + CPU_DDR_SYNC.CLK = DDRCLK0; + CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN + --------------------------------------------------- + VA_S[].CLK = DDRCLK0; + BA_S[].CLK = DDRCLK0; + VA[] = VA_S[]; + BA[] = BA_S[]; + VA_P[].CLK = DDRCLK0; + BA_P[].CLK = DDRCLK0; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF DDR_REFRESH_REQ THEN + DDR_SM = DS_R2; + ELSE + IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? + IF DDR_CONFIG THEN -- JA + DDR_SM = DS_C2; + ELSE + IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE + VA_S[] = CPU_ROW_ADR[]; + BA_S[] = CPU_BA[]; + CPU_AC = VCC; + BUS_CYC = VCC; + DDR_SM = DS_T2B; + ELSE + IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT + VA_P[] = FIFO_ROW_ADR[]; + BA_P[] = FIFO_BA[]; + FIFO_AC = VCC; -- VORBESETZEN + ELSE + VA_P[] = BLITTER_ROW_ADR[]; + BA_P[] = BLITTER_BA[]; + BLITTER_AC = VCC; -- VORBESETZEN + END IF; + DDR_SM = DS_T2A; + END IF; + END IF; + ELSE + DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN + END IF; + END IF; + + WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF DDR_SEL & (nFB_WR # !LINE) THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + ELSE + VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; + VA[] = VA_P[]; + BA[] = BA_P[]; + VA_S[10] = !(FIFO_AC & FIFO_REQ); + FIFO_BANK_OK = FIFO_AC & FIFO_REQ; + FIFO_AC = FIFO_AC & FIFO_REQ; + BLITTER_AC = BLITTER_AC & BLITTER_REQ; + END IF; + DDR_SM = DS_T3; + + WHEN DS_T2B => + VRAS = VCC; + FIFO_BANK_NOT_OK = VCC; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + DDR_SM = DS_T3; + + WHEN DS_T3 => + CPU_AC = CPU_AC; + FIFO_AC = FIFO_AC; + BLITTER_AC = BLITTER_AC; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN + DDR_SM = DS_T4W; + ELSE + IF CPU_AC THEN -- CPU? + VA_S[9..0] = CPU_COL_ADR[]; + BA_S[] = CPU_BA[]; + DDR_SM = DS_T4R; + ELSE + IF FIFO_AC THEN -- FIFO? + VA_S[9..0] = FIFO_COL_ADR[]; + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T4F; + ELSE + IF BLITTER_AC THEN + VA_S[9..0] = BLITTER_COL_ADR[]; + BA_S[] = BLITTER_BA[]; + DDR_SM = DS_T4R; + ELSE + DDR_SM = DS_N8; + END IF; + END IF; + END IF; + END IF; +-- READ + WHEN DS_T4R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN + DDR_SM = DS_T5R; + + WHEN DS_T5R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- MANUEL PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- WRITE + WHEN DS_T4W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + DDR_SM = DS_T5W; + + WHEN DS_T5W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VA_S[9..0] = CPU_AC & CPU_COL_ADR[] + # BLITTER_AC & BLITTER_COL_ADR[]; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + BA_S[] = CPU_AC & CPU_BA[] + # BLITTER_AC & BLITTER_BA[]; + SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE + SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE + DDR_SM = DS_T6W; + + WHEN DS_T6W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + VWE = VCC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV + DDR_SM = DS_T7W; + + WHEN DS_T7W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + DDR_SM = DS_T8W; + + WHEN DS_T8W => + DDR_SM = DS_T9W; + + WHEN DS_T9W => + IF FIFO_REQ & FIFO_BANK_OK THEN + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- FIFO READ + WHEN DS_T4F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T5F; + + WHEN DS_T5F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN + END IF; + + WHEN DS_T6F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + + WHEN DS_T7F => + IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T8F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + END IF; + END IF; + + WHEN DS_T8F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + IF FIFO_MW[] + ELSE + DDR_SM = DS_T9F; + END IF; + + WHEN DS_T9F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_P[9..0] = FIFO_COL_ADR[]+4; + VA_P[10] = GND; -- NON AUTO PRECHARGE + BA_P[] = FIFO_BA[]; + DDR_SM = DS_T10F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + END IF; + + WHEN DS_T10F => + IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK + DDR_SM = DS_T3; + ELSE + VCAS = VCC; + VA[] = VA_P[]; + BA[] = BA_P[]; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + END IF; + +-- CONFIG CYCLUS + WHEN DS_C2 => + DDR_SM = DS_C3; + WHEN DS_C3 => + BUS_CYC = CPU_REQ; + DDR_SM = DS_C4; + WHEN DS_C4 => + IF CPU_REQ THEN + DDR_SM = DS_C5; + ELSE + DDR_SM = DS_T1; + END IF; + WHEN DS_C5 => + DDR_SM = DS_C6; + WHEN DS_C6 => + VA_S[] = FB_AD[12..0]; + BA_S[] = FB_AD[14..13]; + DDR_SM = DS_C7; + WHEN DS_C7 => + VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + DDR_SM = DS_N8; +-- CLOSE FIFO BANK + WHEN DS_CB6 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_N7; + WHEN DS_CB8 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_T1; +-- REFRESH 70NS = 10 ZYCLEN + WHEN DS_R2 => + IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + VRAS = VCC; -- ALLE BANKS SCHLIESSEN + VWE = VCC; + VA[10] = VCC; + FIFO_BANK_NOT_OK = VCC; + DDR_SM = DS_R4; + ELSE + VCAS = VCC; + VRAS = VCC; + DDR_SM = DS_R3; + END IF; + WHEN DS_R3 => + DDR_SM = DS_R4; + WHEN DS_R4 => + DDR_SM = DS_R5; + WHEN DS_R5 => + DDR_SM = DS_R6; + WHEN DS_R6 => + DDR_SM = DS_N5; +-- LEERSCHLAUFE + WHEN DS_N5 => + DDR_SM = DS_N6; + WHEN DS_N6 => + DDR_SM = DS_N7; + WHEN DS_N7 => + DDR_SM = DS_N8; + WHEN DS_N8 => + DDR_SM = DS_T1; + END CASE; + +--------------------------------------------------------------- +-- BLITTER ---------------------- +----------------------------------------- + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; + BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; + BLITTER_BA1 = BLITTER_ADR13; + BLITTER_BA0 = BLITTER_ADR12; + BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- +-------------------------------------------------------- + FIFO_REQ.CLK = DDRCLK0; + FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS +----------------------------------------------------------------------------------------- + DDR_REFRESH_CNT[].CLK = CLK33M; + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + REFRESH_TIME.CLK = DDRCLK0; + REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC + DDR_REFRESH_SIG[].CLK = DDRCLK0; + DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT + DDR_REFRESH_REQ.CLK = DDRCLK0; + DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[26..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & VIDEO_BASE_L_D[] + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] + # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] + # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); +END; + diff --git a/FPGA_quartus/Video/DDR_CTR.tdf.bak b/FPGA_quartus/Video/DDR_CTR.tdf.bak new file mode 100644 index 0000000..ead66e8 --- /dev/null +++ b/FPGA_quartus/Video/DDR_CTR.tdf.bak @@ -0,0 +1,660 @@ +TITLE "DDR_CTR"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + +-- FIFO WATER MARK +CONSTANT FIFO_LWM = 0; +CONSTANT FIFO_MWM = 200; +CONSTANT FIFO_HWM = 500; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + DDRCLK0 : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + CLEAR_FIFO_CNT : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + BA[1..0] : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + DS_T4R,DS_T5R, -- READ CPU UND BLITTER, + DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER + DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO + DS_CB6, DS_CB8, -- CLOSE FIFO BANK + DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA_P[12..0] :DFF; + BA_P[1..0] :DFF; + VA_S[12..0] :DFF; + BA_S[1..0] :DFF; + MCS[1..0] :DFF; + CPU_DDR_SYNC :DFF; + DDR_SEL :NODE; + DDR_CS :DFFE; + DDR_CONFIG :NODE; + SR_DDR_WR :DFF; + SR_DDRWR_D_SEL :DFF; + SR_VDMP[7..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA[1..0] :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + CPU_AC :DFF; + BUS_CYC :DFF; + BUS_CYC_END :NODE; + BLITTER_REQ :DFF; + BLITTER_AC :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA[1..0] :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_REQ :DFF; + FIFO_AC :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA[1..0] :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_ACTIVE :NODE; + CLR_FIFO_SYNC :DFF; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + SR_FIFO_WRE :DFF; + FIFO_BANK_OK :DFF; + FIFO_BANK_NOT_OK :NODE; + DDR_REFRESH_ON :NODE; + DDR_REFRESH_CNT[10..0] :DFF; + DDR_REFRESH_REQ :DFF; + DDR_REFRESH_SIG[3..0] :DFFE; + REFRESH_TIME :DFF; + VIDEO_BASE_L_D[7..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[2..0] :DFFE; + VIDEO_ADR_CNT[22..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[22..0] :NODE; + VIDEO_ACT_ADR[26..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0 -- ADR==0 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + FB_LE0 = !nFB_WR; + IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + IF DDR_CS THEN + FB_LE0 = !nFB_WR; + VIDEO_DDR_TA = VCC; + IF LINE THEN + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_REGDDR = FR_S1; + ELSE + BUS_CYC_END = VCC; + FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_REGDDR = FR_WAIT; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + IF DDR_CS THEN + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S2; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S2 => + IF DDR_CS THEN + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN + FB_REGDDR = FR_S2; + ELSE + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S3; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S3 => + IF DDR_CS THEN + FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + VIDEO_DDR_TA = VCC; + BUS_CYC_END = VCC; + FB_REGDDR = FR_WAIT; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + DDR_REFRESH_ON = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + FIFO_ACTIVE = VIDEO_RAM_CTR8; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA[] = FB_ADR[13..12]; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + SR_DDR_WR.CLK = DDRCLK0; + SR_DDRWR_D_SEL.CLK = DDRCLK0; + SR_VDMP[7..0].CLK = DDRCLK0; + SR_FIFO_WRE.CLK = DDRCLK0; + CPU_AC.CLK = DDRCLK0; + FIFO_AC.CLK = DDRCLK0; + BLITTER_AC.CLK = DDRCLK0; + DDRWR_D_SEL1 = BLITTER_AC; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; + DDR_CS.CLK = MAIN_CLK; + DDR_CS.ENA = FB_ALE; + DDR_CS = DDR_SEL; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + CPU_REQ.CLK = DDR_SYNC_66M; + CPU_REQ = CPU_SIG + # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG + BUS_CYC.CLK = DDRCLK0; + BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS[].CLK = DDRCLK0; + MCS0 = MAIN_CLK; + MCS1 = MCS0; + CPU_DDR_SYNC.CLK = DDRCLK0; + CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN + --------------------------------------------------- + VA_S[].CLK = DDRCLK0; + BA_S[].CLK = DDRCLK0; + VA[] = VA_S[]; + BA[] = BA_S[]; + VA_P[].CLK = DDRCLK0; + BA_P[].CLK = DDRCLK0; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF DDR_REFRESH_REQ THEN + DDR_SM = DS_R2; + ELSE + IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? + IF DDR_CONFIG THEN -- JA + DDR_SM = DS_C2; + ELSE + IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE + VA_S[] = CPU_ROW_ADR[]; + BA_S[] = CPU_BA[]; + CPU_AC = VCC; + BUS_CYC = VCC; + DDR_SM = DS_T2B; + ELSE + IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT + VA_P[] = FIFO_ROW_ADR[]; + BA_P[] = FIFO_BA[]; + FIFO_AC = VCC; -- VORBESETZEN + ELSE + VA_P[] = BLITTER_ROW_ADR[]; + BA_P[] = BLITTER_BA[]; + BLITTER_AC = VCC; -- VORBESETZEN + END IF; + DDR_SM = DS_T2A; + END IF; + END IF; + ELSE + DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN + END IF; + END IF; + + WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF DDR_SEL & (nFB_WR # !LINE) THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + ELSE + VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; + VA[] = VA_P[]; + BA[] = BA_P[]; + VA_S[10] = !(FIFO_AC & FIFO_REQ); + FIFO_BANK_OK = FIFO_AC & FIFO_REQ; + FIFO_AC = FIFO_AC & FIFO_REQ; + BLITTER_AC = BLITTER_AC & BLITTER_REQ; + END IF; + DDR_SM = DS_T3; + + WHEN DS_T2B => + VRAS = VCC; + FIFO_BANK_NOT_OK = VCC; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + DDR_SM = DS_T3; + + WHEN DS_T3 => + CPU_AC = CPU_AC; + FIFO_AC = FIFO_AC; + BLITTER_AC = BLITTER_AC; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN + DDR_SM = DS_T4W; + ELSE + IF CPU_AC THEN -- CPU? + VA_S[9..0] = CPU_COL_ADR[]; + BA_S[] = CPU_BA[]; + DDR_SM = DS_T4R; + ELSE + IF FIFO_AC THEN -- FIFO? + VA_S[9..0] = FIFO_COL_ADR[]; + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T4F; + ELSE + IF BLITTER_AC THEN + VA_S[9..0] = BLITTER_COL_ADR[]; + BA_S[] = BLITTER_BA[]; + DDR_SM = DS_T4R; + ELSE + DDR_SM = DS_N8; + END IF; + END IF; + END IF; + END IF; +-- READ + WHEN DS_T4R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN + DDR_SM = DS_T5R; + + WHEN DS_T5R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- MANUEL PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- WRITE + WHEN DS_T4W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + DDR_SM = DS_T5W; + + WHEN DS_T5W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VA_S[9..0] = CPU_AC & CPU_COL_ADR[] + # BLITTER_AC & BLITTER_COL_ADR[]; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + BA_S[] = CPU_AC & CPU_BA[] + # BLITTER_AC & BLITTER_BA[]; + SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE + SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE + DDR_SM = DS_T6W; + + WHEN DS_T6W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + VWE = VCC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV + DDR_SM = DS_T7W; + + WHEN DS_T7W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + DDR_SM = DS_T8W; + + WHEN DS_T8W => + DDR_SM = DS_T9W; + + WHEN DS_T9W => + IF FIFO_REQ & FIFO_BANK_OK THEN + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- FIFO READ + WHEN DS_T4F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T5F; + + WHEN DS_T5F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN + END IF; + + WHEN DS_T6F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + + WHEN DS_T7F => + IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T8F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + END IF; + END IF; + + WHEN DS_T8F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + IF FIFO_MW[] + ELSE + DDR_SM = DS_T9F; + END IF; + + WHEN DS_T9F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_P[9..0] = FIFO_COL_ADR[]+4; + VA_P[10] = GND; -- NON AUTO PRECHARGE + BA_P[] = FIFO_BA[]; + DDR_SM = DS_T10F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + END IF; + + WHEN DS_T10F => + IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK + DDR_SM = DS_T3; + ELSE + VCAS = VCC; + VA[] = VA_P[]; + BA[] = BA_P[]; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + END IF; + +-- CONFIG CYCLUS + WHEN DS_C2 => + DDR_SM = DS_C3; + WHEN DS_C3 => + BUS_CYC = CPU_REQ; + DDR_SM = DS_C4; + WHEN DS_C4 => + IF CPU_REQ THEN + DDR_SM = DS_C5; + ELSE + DDR_SM = DS_T1; + END IF; + WHEN DS_C5 => + DDR_SM = DS_C6; + WHEN DS_C6 => + VA_S[] = FB_AD[12..0]; + BA_S[] = FB_AD[14..13]; + DDR_SM = DS_C7; + WHEN DS_C7 => + VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + DDR_SM = DS_N8; +-- CLOSE FIFO BANK + WHEN DS_CB6 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_N7; + WHEN DS_CB8 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_T1; +-- REFRESH 70NS = 10 ZYCLEN + WHEN DS_R2 => + IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + VRAS = VCC; -- ALLE BANKS SCHLIESSEN + VWE = VCC; + VA[10] = VCC; + FIFO_BANK_NOT_OK = VCC; + DDR_SM = DS_R4; + ELSE + VCAS = VCC; + VRAS = VCC; + DDR_SM = DS_R3; + END IF; + WHEN DS_R3 => + DDR_SM = DS_R4; + WHEN DS_R4 => + DDR_SM = DS_R5; + WHEN DS_R5 => + DDR_SM = DS_R6; + WHEN DS_R6 => + DDR_SM = DS_N5; +-- LEERSCHLAUFE + WHEN DS_N5 => + DDR_SM = DS_N6; + WHEN DS_N6 => + DDR_SM = DS_N7; + WHEN DS_N7 => + DDR_SM = DS_N8; + WHEN DS_N8 => + DDR_SM = DS_T1; + END CASE; + +--------------------------------------------------------------- +-- BLITTER ---------------------- +----------------------------------------- + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; + BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; + BLITTER_BA1 = BLITTER_ADR13; + BLITTER_BA0 = BLITTER_ADR12; + BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- +-------------------------------------------------------- + FIFO_REQ.CLK = DDRCLK0; + FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS +----------------------------------------------------------------------------------------- + DDR_REFRESH_CNT[].CLK = CLK33M; + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + REFRESH_TIME.CLK = DDRCLK0; + REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC + DDR_REFRESH_SIG[].CLK = DDRCLK0; + DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT + DDR_REFRESH_REQ.CLK = DDRCLK0; + DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[26..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & VIDEO_BASE_L_D[] + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] + # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] + # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); +END; + diff --git a/FPGA_quartus/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_quartus/Video/DDR_CTR_BLITTER.tdf.bak new file mode 100644 index 0000000..03052b4 --- /dev/null +++ b/FPGA_quartus/Video/DDR_CTR_BLITTER.tdf.bak @@ -0,0 +1,352 @@ +TITLE "DDR_CTR_BLITTER"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR_BLITTER +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FIFO_FULL : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + VSYNC : INPUT; + BLITTER_ON : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + VDVZ[127..0] : INPUT; + DDRCLK[3..0] : INPUT; + BA0 : OUTPUT; + BA1 : OUTPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FIFO_WRE : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + START_CYC_RDWR : OUTPUT; + DDR_WR : OUTPUT; + CLEAR_FIFO_CNT : OUTPUT; + BLITTER_RUN : OUTPUT; + BLITTER_DOUT[127..0] : OUTPUT; + BLITTER_LE[3..0] : OUTPUT; + BLITTER_RDE : OUTPUT; + DDRWR_D_SEL[1..0] : OUTPUT; + VDMP[7..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS); + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA[12..0] :NODE; + BA0 :NODE; + BA1 :NODE; + DDR_WR :DFF; + DDR_SEL :NODE; + DDR_CONFIG :NODE; + DDRWR_D_SEL[1..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA0 :NODE; + CPU_BA1 :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + BLITTER_SIG :NODE; + BLITTER_REQ :DFF; + BLITTER_RUN :DFF; + BLITTER_WR :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA0 :NODE; + BLITTER_BA1 :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_SIG :NODE; + FIFO_REQ :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA0 :NODE; + FIFO_BA1 :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_WRE :DFF; + FIFO_ACTIVE :NODE; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + DDR_REFRESH_ON :NODE; + VIDEO_BASE_L_D[3..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[7..0] :DFFE; + VIDEO_ADR_CNT[27..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[27..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0; -- ADR==0 + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + IF DDR_SEL THEN + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_LE0 = !nFB_WR; + IF LINE THEN + FB_REGDDR = FR_S1; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + FB_REGDDR = FR_S2; + WHEN FR_S2 => + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + FB_REGDDR = FR_S3; + WHEN FR_S3 => + FB_VDOE3 = !nFB_OE & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + FB_REGDDR = FR_WAIT; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + FIFO_ACTIVE = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + DDR_REFRESH_ON = VIDEO_RAM_CTR4; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA1 = FB_ADR13; + CPU_BA0 = FB_ADR12; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + DDR_WR.CLK = DDRCLK0; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..29]==B"011"; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS + # FR_S0 & !nFB_WR -- WRITE SPÄTER AUCH CONFIG + # FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE + CPU_REQ = CPU_SIG; + CPU_REQ.CLK = DDR_SYNC_66M; + DDR_D_SEL[].CLK = DDRCLK3; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF MAIN_CLK THEN + DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4) + DDR_SM = DS_T2; + ELSE + DDR_SM = DS_LS; -- SYNCHRONISIEREN + END IF; + WHEN DS_T2 => + IF !DDR_CONFIG THEN + VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON; + VA[] = CPU_SIG & CPU_ROW_ADR[] + # BLITTER_SIG & BLITTER_ROW_ADR[] + # FIFO_SIG & FIFO_ROW_ADR[]; + BA0 = CPU_SIG & CPU_BA0 + # BLITTER_SIG & BLITTER_BA0 + # FIFO_SIG & FIFO_BA0; + BA1 = CPU_SIG & CPU_BA1 + # BLITTER_SIG & BLITTER_BA1 + # FIFO_SIG & FIFO_BA1; + VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS + BLITTER_REQ = BLITTER_SIG; + FIFO_REQ = FIFO_SIG; + END IF; + IF MAIN_CLK THEN + DDR_SM = DS_T3; + ELSE + DDR_SM = DS_LS; + END IF; + WHEN DS_T3 => + IF DDR_CONFIG & CPU_REQ THEN + VRAS = FB_AD18; + VCAS = FB_AD17; + VWE = FB_AD16; + BA1 = FB_AD14; + BA0 = FB_AD13; + VA[] = FB_AD[12..0]; + END IF; + IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN + DDR_SM = DS_LS; + ELSE + BLITTER_REQ = BLITTER_SIG; + FIFO_REQ = FIFO_SIG; + DDR_SM = DS_T4; + END IF; + WHEN DS_T4 => + FIFO_REQ = FIFO_SIG; + VCAS = VCC; + VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; + VA[9..0] = CPU_REQ & CPU_COL_ADR[] + # BLITTER_REQ & BLITTER_COL_ADR[] + # FIFO_REQ & FIFO_COL_ADR[]; + VA10 = VCC; -- AUTO PRECHARGE + BA0 = CPU_REQ & CPU_BA0 + # BLITTER_REQ & BLITTER_BA0 + # FIFO_REQ & FIFO_BA0; + BA1 = CPU_REQ & CPU_BA1 + # BLITTER_REQ & BLITTER_BA1 + # FIFO_REQ & FIFO_BA1; + DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; + FIFO_REQ = FIFO_SIG; + IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? + DDR_SM = DS_T5; -- JA-> + ELSE + DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN + END IF; + WHEN DS_T5 => + FIFO_REQ = FIFO_SIG; + DDR_SM = DS_T6; + WHEN DS_T6 => + IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ + VRAS = VCC; + VA[] = CPU_ROW_ADR[]; + BA1 = CPU_BA1; + BA0 = CPU_BA0; + DDR_SM = DS_T3; + ELSE + FIFO_REQ = FIFO_SIG; + VCAS = VCC; + VA[9..0] = FIFO_COL_ADR[]; + VA10 = VCC; -- AUTO PRECHARGE + BA0 = FIFO_BA0; + BA1 = FIFO_BA1; + FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133 + IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? + DDR_SM = DS_T5; -- JA-> + ELSE + DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN + END IF; + END IF; + WHEN DS_LS => + IF !MAIN_CLK THEN -- LEERSTATE UND SYNC + DDR_SM = DS_T1; + ELSE + DDR_SM = DS_LS; + END IF; + END CASE; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- + FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG; + FIFO_REQ.CLK = DDR_SYNC_66M; + FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12]; + FIFO_BA1 = VIDEO_ADR_CNT11; + FIFO_BA0 = VIDEO_ADR_CNT10; + FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0]; + -- ZÄHLER RÜCKSETZEN WENN VSYNC ---------------- + CLEAR_FIFO_CNT.CLK = DDRCLK0; + CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE; + STOP.CLK = DDRCLK0; + STOP = VSYNC # CLEAR_FIFO_CNT; + VIDEO_ADR_CNT[].CLK = DDRCLK0; + VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET + # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS + VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE; + FIFO_WRE.CLK = DDRCLK0; +--------------------------------------------------------------- +-- BLITTER BUS IST 128 BIT BREIT ------ + BLITTER_SIG = GND & !CPU_SIG; + BLITTER_REQ.CLK = DDR_SYNC_66M; + BLITTER_RUN.CLK = DDRCLK0; + BLITTER_RUN = GND; + BLITTER_WR.CLK = DDRCLK0; + BLITTER_WR = GND; + DDRWR_D_SEL1 = BLITTER_WR; + BLITTER_ROW_ADR[] = H"0"; + BLITTER_BA1 = GND; + BLITTER_BA0 = GND; + BLITTER_COL_ADR[] = H"0"; + BLITTER_DOUT[] = H"0"; + BLITTER_LE[] = H"0"; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[31..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & VIDEO_BASE_X_D[] + # VIDEO_CNT_H & VIDEO_ADR_CNT[27..20] + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000") + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000") + # VIDEO_CNT_M & VIDEO_ADR_CNT[11..4] + # VIDEO_CNT_H & VIDEO_ADR_CNT[19..12] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); + + VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[]; + VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[]; + VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[]; + VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[]; +END; + diff --git a/FPGA_quartus/Video/UNUSED b/FPGA_quartus/Video/UNUSED new file mode 100644 index 0000000..12f424b --- /dev/null +++ b/FPGA_quartus/Video/UNUSED @@ -0,0 +1,267 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=6; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 0F; + 001 : 0E; + 002 : 0D; + 003 : 0C; + 004 : 0B; + 005 : 0A; + 006 : 09; + 007 : 08; + 008 : 07; + 009 : 06; + 00a : 05; + 00b : 04; + 00c : 03; + 00d : 02; + 00e : 01; + 00f : 00; + 010 : 0F; + 011 : 0E; + 012 : 0D; + 013 : 0C; + 014 : 0B; + 015 : 0A; + 016 : 09; + 017 : 08; + 018 : 07; + 019 : 06; + 01a : 05; + 01b : 04; + 01c : 03; + 01d : 02; + 01e : 01; + 01f : 00; + 020 : 0F; + 021 : 0E; + 022 : 0D; + 023 : 0C; + 024 : 0B; + 025 : 0A; + 026 : 09; + 027 : 08; + 028 : 07; + 029 : 06; + 02a : 05; + 02b : 04; + 02c : 03; + 02d : 02; + 02e : 01; + 02f : 00; + 030 : 0F; + 031 : 0E; + 032 : 0D; + 033 : 0C; + 034 : 0B; + 035 : 0A; + 036 : 09; + 037 : 08; + 038 : 07; + 039 : 06; + 03a : 05; + 03b : 04; + 03c : 03; + 03d : 02; + 03e : 01; + 03f : 00; + 040 : 0F; + 041 : 0E; + 042 : 0D; + 043 : 0C; + 044 : 0B; + 045 : 0A; + 046 : 09; + 047 : 08; + 048 : 07; + 049 : 06; + 04a : 05; + 04b : 04; + 04c : 03; + 04d : 02; + 04e : 01; + 04f : 00; + 050 : 0F; + 051 : 0E; + 052 : 0D; + 053 : 0C; + 054 : 0B; + 055 : 0A; + 056 : 09; + 057 : 08; + 058 : 07; + 059 : 06; + 05a : 05; + 05b : 04; + 05c : 03; + 05d : 02; + 05e : 01; + 05f : 00; + 060 : 0F; + 061 : 0E; + 062 : 0D; + 063 : 0C; + 064 : 0B; + 065 : 0A; + 066 : 09; + 067 : 08; + 068 : 07; + 069 : 06; + 06a : 05; + 06b : 04; + 06c : 03; + 06d : 02; + 06e : 01; + 06f : 00; + 070 : 0F; + 071 : 0E; + 072 : 0D; + 073 : 0C; + 074 : 0B; + 075 : 0A; + 076 : 09; + 077 : 08; + 078 : 07; + 079 : 06; + 07a : 05; + 07b : 04; + 07c : 03; + 07d : 02; + 07e : 01; + 07f : 00; + 080 : 0F; + 081 : 0E; + 082 : 0D; + 083 : 0C; + 084 : 0B; + 085 : 0A; + 086 : 09; + 087 : 08; + 088 : 07; + 089 : 06; + 08a : 05; + 08b : 04; + 08c : 03; + 08d : 02; + 08e : 01; + 08f : 00; + 090 : 0F; + 091 : 0E; + 092 : 0D; + 093 : 0C; + 094 : 0B; + 095 : 0A; + 096 : 09; + 097 : 08; + 098 : 07; + 099 : 06; + 09a : 05; + 09b : 04; + 09c : 03; + 09d : 02; + 09e : 01; + 09f : 00; + 0a0 : 0F; + 0a1 : 0E; + 0a2 : 0D; + 0a3 : 0C; + 0a4 : 0B; + 0a5 : 0A; + 0a6 : 09; + 0a7 : 08; + 0a8 : 07; + 0a9 : 06; + 0aa : 05; + 0ab : 04; + 0ac : 03; + 0ad : 02; + 0ae : 01; + 0af : 00; + 0b0 : 0F; + 0b1 : 0E; + 0b2 : 0D; + 0b3 : 0C; + 0b4 : 0B; + 0b5 : 0A; + 0b6 : 09; + 0b7 : 08; + 0b8 : 07; + 0b9 : 06; + 0ba : 05; + 0bb : 04; + 0bc : 03; + 0bd : 02; + 0be : 01; + 0bf : 00; + 0c0 : 0F; + 0c1 : 0E; + 0c2 : 0D; + 0c3 : 0C; + 0c4 : 0B; + 0c5 : 0A; + 0c6 : 09; + 0c7 : 08; + 0c8 : 07; + 0c9 : 06; + 0ca : 05; + 0cb : 04; + 0cc : 03; + 0cd : 02; + 0ce : 01; + 0cf : 00; + 0d0 : 0F; + 0d1 : 0E; + 0d2 : 0D; + 0d3 : 0C; + 0d4 : 0B; + 0d5 : 0A; + 0d6 : 09; + 0d7 : 08; + 0d8 : 07; + 0d9 : 06; + 0da : 05; + 0db : 04; + 0dc : 03; + 0dd : 02; + 0de : 01; + 0df : 00; + 0e0 : 0F; + 0e1 : 0E; + 0e2 : 0D; + 0e3 : 0C; + 0e4 : 0B; + 0e5 : 0A; + 0e6 : 09; + 0e7 : 08; + 0e8 : 07; + 0e9 : 06; + 0ea : 05; + 0eb : 04; + 0ec : 03; + 0ed : 02; + 0ee : 01; + 0ef : 00; + 0f0 : 0F; + 0f1 : 0E; + 0f2 : 0D; + 0f3 : 0C; + 0f4 : 0B; + 0f5 : 0A; + 0f6 : 09; + 0f7 : 08; + 0f8 : 07; + 0f9 : 06; + 0fa : 05; + 0fb : 04; + 0fc : 03; + 0fd : 02; + 0fe : 01; + 0ff : 00; +END; diff --git a/FPGA_quartus/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_quartus/Video/VIDEO_MOD_MUX_CLUTCTR.tdf new file mode 100644 index 0000000..2c9adcc --- /dev/null +++ b/FPGA_quartus/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -0,0 +1,675 @@ +TITLE "VIDEO MODUSE UND CLUT CONTROL"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_WORD.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN VIDEO_MOD_MUX_CLUTCTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + nRSTO : INPUT; + MAIN_CLK : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_WR : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nFB_BURST : INPUT; + FB_ADR[31..0] : INPUT; + CLK33M : INPUT; + CLK25M : INPUT; + BLITTER_RUN : INPUT; + CLK_VIDEO : INPUT; + VR_D[8..0] : INPUT; + VR_BUSY : INPUT; + COLOR8 : OUTPUT; + ACP_CLUT_RD : OUTPUT; + COLOR1 : OUTPUT; + FALCON_CLUT_RDH : OUTPUT; + FALCON_CLUT_RDL : OUTPUT; + FALCON_CLUT_WR[3..0] : OUTPUT; + ST_CLUT_RD : OUTPUT; + ST_CLUT_WR[1..0] : OUTPUT; + CLUT_MUX_ADR[3..0] : OUTPUT; + HSYNC : OUTPUT; + VSYNC : OUTPUT; + nBLANK : OUTPUT; + nSYNC : OUTPUT; + nPD_VGA : OUTPUT; + FIFO_RDE : OUTPUT; + COLOR2 : OUTPUT; + COLOR4 : OUTPUT; + PIXEL_CLK : OUTPUT; + CLUT_OFF[3..0] : OUTPUT; + BLITTER_ON : OUTPUT; + VIDEO_RAM_CTR[15..0] : OUTPUT; + VIDEO_MOD_TA : OUTPUT; + CCR[23..0] : OUTPUT; + CCSEL[2..0] : OUTPUT; + ACP_CLUT_WR[3..0] : OUTPUT; + INTER_ZEI : OUTPUT; + DOP_FIFO_CLR : OUTPUT; + VIDEO_RECONFIG : OUTPUT; + VR_WR : OUTPUT; + VR_RD : OUTPUT; + CLR_FIFO : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + CLK17M :DFF; + CLK13M :DFF; + ACP_CLUT_CS :NODE; + ACP_CLUT :NODE; + VIDEO_PLL_CONFIG_CS :NODE; + VR_WR :DFF; + VR_DOUT[8..0] :DFFE; + VR_FRQ[7..0] :DFFE; + VIDEO_PLL_RECONFIG_CS :NODE; + VIDEO_RECONFIG :DFF; + FALCON_CLUT_CS :NODE; + FALCON_CLUT :NODE; + ST_CLUT_CS :NODE; + ST_CLUT :NODE; + FB_B[3..0] :NODE; + FB_16B[1..0] :NODE; + ST_SHIFT_MODE[1..0] :DFFE; + ST_SHIFT_MODE_CS :NODE; + FALCON_SHIFT_MODE[10..0] :DFFE; + FALCON_SHIFT_MODE_CS :NODE; + CLUT_MUX_ADR[3..0] :DFF; + CLUT_MUX_AV[1..0][3..0] :DFF; + ACP_VCTR_CS :NODE; + ACP_VCTR[31..0] :DFFE; + CCR_CS :NODE; + CCR[23..0] :DFFE; + ACP_VIDEO_ON :NODE; + SYS_CTR[6..0] :DFFE; + SYS_CTR_CS :NODE; + VDL_LOF[15..0] :DFFE; + VDL_LOF_CS :NODE; + VDL_LWD[15..0] :DFFE; + VDL_LWD_CS :NODE; +-- DIV. CONTROL REGISTER + CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + HSYNC :DFF; + HSYNC_I[7..0] :DFF; + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSYNC_START :DFF; + LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + VSYNC :DFF; + VSYNC_START :DFFE; + VSYNC_I[2..0] :DFFE; + nBLANK :DFF; + DISP_ON :DFF; + DPO_ZL :DFFE; + DPO_ON :DFF; + DPO_OFF :DFF; + VDTRON :DFF; + VDO_ZL :DFFE; + VDO_ON :DFF; + VDO_OFF :DFF; + VHCNT[11..0] :DFF; + SUB_PIXEL_CNT[6..0] :DFFE; + VVCNT[10..0] :DFFE; + VERZ[2..0][9..0] :DFF; + RAND[6..0] :DFF; + RAND_ON :NODE; + FIFO_RDE :DFF; + CLR_FIFO :DFFE; + START_ZEILE :DFFE; + SYNC_PIX :DFF; + SYNC_PIX1 :DFF; + SYNC_PIX2 :DFF; + CCSEL[2..0] :DFF; + COLOR16 :NODE; + COLOR24 :NODE; +-- ATARI RESOLUTION + ATARI_SYNC :NODE; + ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 + ATARI_HH_CS :NODE; + ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 + ATARI_VH_CS :NODE; + ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 + ATARI_HL_CS :NODE; + ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 + ATARI_VL_CS :NODE; +-- HORIZONTAL + RAND_LINKS[11..0] :NODE; + HDIS_START[11..0] :NODE; + HDIS_END[11..0] :NODE; + RAND_RECHTS[11..0] :NODE; + HS_START[11..0] :NODE; + H_TOTAL[11..0] :NODE; + HDIS_LEN[11..0] :NODE; + MULF[5..0] :NODE; + VDL_HHT[11..0] :DFFE; + VDL_HHT_CS :NODE; + VDL_HBE[11..0] :DFFE; + VDL_HBE_CS :NODE; + VDL_HDB[11..0] :DFFE; + VDL_HDB_CS :NODE; + VDL_HDE[11..0] :DFFE; + VDL_HDE_CS :NODE; + VDL_HBB[11..0] :DFFE; + VDL_HBB_CS :NODE; + VDL_HSS[11..0] :DFFE; + VDL_HSS_CS :NODE; +-- VERTIKAL + RAND_OBEN[10..0] :NODE; + VDIS_START[10..0] :NODE; + VDIS_END[10..0] :NODE; + RAND_UNTEN[10..0] :NODE; + VS_START[10..0] :NODE; + V_TOTAL[10..0] :NODE; + FALCON_VIDEO :NODE; + ST_VIDEO :NODE; + INTER_ZEI :DFF; + DOP_ZEI :DFF; + DOP_FIFO_CLR :DFF; + + VDL_VBE[10..0] :DFFE; + VDL_VBE_CS :NODE; + VDL_VDB[10..0] :DFFE; + VDL_VDB_CS :NODE; + VDL_VDE[10..0] :DFFE; + VDL_VDE_CS :NODE; + VDL_VBB[10..0] :DFFE; + VDL_VBB_CS :NODE; + VDL_VSS[10..0] :DFFE; + VDL_VSS_CS :NODE; + VDL_VFT[10..0] :DFFE; + VDL_VFT_CS :NODE; + VDL_VCT[8..0] :DFFE; + VDL_VCT_CS :NODE; + VDL_VMD[3..0] :DFFE; + VDL_VMD_CS :NODE; + +BEGIN +-- BYT SELECT 32 BIT + FB_B0 = FB_ADR[1..0]==0; -- ADR==0 + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- BYT SELECT 16 BIT + FB_16B0 = FB_ADR[0]==0; -- ADR==0 + FB_16B1 = FB_ADR[0]==1 -- ADR==1 + # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT +-- ACP CLUT -- + ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 + ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; + ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; + CLUT_TA.CLK = MAIN_CLK; + CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; +--FALCON CLUT -- + FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 + FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD + FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD + FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; + FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; +-- ST CLUT -- + ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 + ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; + ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; +-- ST SHIFT MODE + ST_SHIFT_MODE[].CLK = MAIN_CLK; + ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 + ST_SHIFT_MODE[] = FB_AD[25..24]; + ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; + COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN + COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN +-- FALCON SHIFT MODE + FALCON_SHIFT_MODE[].CLK = MAIN_CLK; + FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 + FALCON_SHIFT_MODE[] = FB_AD[26..16]; + FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; + FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; +-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + ACP_VCTR[].CLK = MAIN_CLK; + ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 + ACP_VCTR[31..8] = FB_AD[31..8]; + ACP_VCTR[5..0] = FB_AD[5..0]; + ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; + ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; + ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; + ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; + ACP_VIDEO_ON = ACP_VCTR0; + nPD_VGA = ACP_VCTR1; + -- ATARI MODUS + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + -- HORIZONTAL TIMING 640x480 + ATARI_HH[].CLK = MAIN_CLK; + ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 + ATARI_HH[] = FB_AD[]; + ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; + ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; + ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; + ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 640x480 + ATARI_VH[].CLK = MAIN_CLK; + ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 + ATARI_VH[] = FB_AD[]; + ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; + ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; + ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; + ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; + -- HORIZONTAL TIMING 320x240 + ATARI_HL[].CLK = MAIN_CLK; + ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 + ATARI_HL[] = FB_AD[]; + ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; + ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; + ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; + ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 320x240 + ATARI_VL[].CLK = MAIN_CLK; + ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 + ATARI_VL[] = FB_AD[]; + ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; + ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; + ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; + ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; +-- VIDEO PLL CONFIG + VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VR_WR.CLK = MAIN_CLK; + VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; + VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; + VR_DOUT[].ENA = !VR_BUSY; + VR_DOUT[] = VR_D[]; + VR_FRQ[].CLK = MAIN_CLK; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[] = FB_AD[23..16]; +-- VIDEO PLL RECONFIG + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_RECONFIG.CLK = MAIN_CLK; + VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; +------------------------------------------------------------------------------------------------------------------------ + VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; +-------------- COLOR MODE IM ACP SETZEN + COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; + ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; + FALCON_VIDEO = ACP_VCTR7; + FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; + ST_VIDEO = ACP_VCTR6; + ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; + CCSEL[].CLK = PIXEL_CLK; + CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION + # B"001" & FALCON_CLUT + # B"100" & ACP_CLUT + # B"101" & COLOR16 + # B"110" & COLOR24 + # B"111" & RAND_ON; +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + CCR[].CLK = MAIN_CLK; + CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + CCR[] = FB_AD[23..0]; + CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; + CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; + CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; +--SYS CTR + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + SYS_CTR[].CLK = MAIN_CLK; + SYS_CTR[6..0] = FB_AD[22..16]; + SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; + BLITTER_ON = !SYS_CTR3; +--VDL_LOF + VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 + VDL_LOF[].CLK = MAIN_CLK; + VDL_LOF[] = FB_AD[31..16]; + VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; + VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; +--VDL_LWD + VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + VDL_LWD[].CLK = MAIN_CLK; + VDL_LWD[] = FB_AD[31..16]; + VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; + VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; +-- HORIZONTAL +-- VDL_HHT + VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + VDL_HHT[].CLK = MAIN_CLK; + VDL_HHT[] = FB_AD[27..16]; + VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; + VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; +-- VDL_HBE + VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + VDL_HBE[].CLK = MAIN_CLK; + VDL_HBE[] = FB_AD[27..16]; + VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; + VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; +-- VDL_HDB + VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + VDL_HDB[].CLK = MAIN_CLK; + VDL_HDB[] = FB_AD[27..16]; + VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; + VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; +-- VDL_HDE + VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + VDL_HDE[].CLK = MAIN_CLK; + VDL_HDE[] = FB_AD[27..16]; + VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; + VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; +-- VDL_HBB + VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + VDL_HBB[].CLK = MAIN_CLK; + VDL_HBB[] = FB_AD[27..16]; + VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; + VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; +-- VDL_HSS + VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 + VDL_HSS[].CLK = MAIN_CLK; + VDL_HSS[] = FB_AD[27..16]; + VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; + VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; +-- VERTIKAL +-- VDL_VBE + VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 + VDL_VBE[].CLK = MAIN_CLK; + VDL_VBE[] = FB_AD[26..16]; + VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; + VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; +-- VDL_VDB + VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 + VDL_VDB[].CLK = MAIN_CLK; + VDL_VDB[] = FB_AD[26..16]; + VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; + VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; +-- VDL_VDE + VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 + VDL_VDE[].CLK = MAIN_CLK; + VDL_VDE[] = FB_AD[26..16]; + VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; + VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; +-- VDL_VBB + VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 + VDL_VBB[].CLK = MAIN_CLK; + VDL_VBB[] = FB_AD[26..16]; + VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; + VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; +-- VDL_VSS + VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 + VDL_VSS[].CLK = MAIN_CLK; + VDL_VSS[] = FB_AD[26..16]; + VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; + VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; +-- VDL_VFT + VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 + VDL_VFT[].CLK = MAIN_CLK; + VDL_VFT[] = FB_AD[26..16]; + VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; + VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; +-- VDL_VCT + VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 + VDL_VCT[].CLK = MAIN_CLK; + VDL_VCT[] = FB_AD[24..16]; + VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; + VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; +-- VDL_VMD + VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 + VDL_VMD[].CLK = MAIN_CLK; + VDL_VMD[] = FB_AD[19..16]; + VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; +--- REGISTER OUT + FB_AD[31..16] = lpm_bustri_WORD( + ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) + # VDL_LOF_CS & VDL_LOF[] + # VDL_LWD_CS & VDL_LWD[] + # VDL_HBE_CS & (0,VDL_HBE[]) + # VDL_HDB_CS & (0,VDL_HDB[]) + # VDL_HDE_CS & (0,VDL_HDE[]) + # VDL_HBB_CS & (0,VDL_HBB[]) + # VDL_HSS_CS & (0,VDL_HSS[]) + # VDL_HHT_CS & (0,VDL_HHT[]) + # VDL_VBE_CS & (0,VDL_VBE[]) + # VDL_VDB_CS & (0,VDL_VDB[]) + # VDL_VDE_CS & (0,VDL_VDE[]) + # VDL_VBB_CS & (0,VDL_VBB[]) + # VDL_VSS_CS & (0,VDL_VSS[]) + # VDL_VFT_CS & (0,VDL_VFT[]) + # VDL_VCT_CS & (0,VDL_VCT[]) + # VDL_VMD_CS & (0,VDL_VMD[]) + # ACP_VCTR_CS & ACP_VCTR[31..16] + # ATARI_HH_CS & ATARI_HH[31..16] + # ATARI_VH_CS & ATARI_VH[31..16] + # ATARI_HL_CS & ATARI_HL[31..16] + # ATARI_VL_CS & ATARI_VL[31..16] + # CCR_CS & (0,CCR[23..16]) + # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + + FB_AD[15..0] = lpm_bustri_WORD( + ACP_VCTR_CS & ACP_VCTR[15..0] + # ATARI_HH_CS & ATARI_HH[15..0] + # ATARI_VH_CS & ATARI_VH[15..0] + # ATARI_HL_CS & ATARI_HL[15..0] + # ATARI_VL_CS & ATARI_VL[15..0] + # CCR_CS & CCR[15..0] + ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M.CLK = CLK33M; + CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; + CLK13M = !CLK13M; + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; +-------------------------------------------------------------- +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +---------------------------------------------------------------- + HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + + MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VDL_VMD2 + # 16 & ST_VIDEO & VDL_VMD2 + # 32 & ST_VIDEO & !VDL_VMD2; + + + HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN + # 640 & !VDL_VMD2; + +-- DOPPELZEILENMODUS + DOP_ZEI.CLK = MAIN_CLK; + DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; + INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + + RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON + # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- + HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON + # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- + RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON + # HDIS_END[]+1 & !ACP_VIDEO_ON; -- + HS_START[] = VDL_HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON + # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VS_START[] = VDL_VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; +-- ZÄHLER + LAST.CLK = PIXEL_CLK; + LAST = VHCNT[]==(H_TOTAL[]-2); + VHCNT[].CLK = PIXEL_CLK; + VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; + VVCNT[].ENA = LAST; + VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); +-- DISPLAY ON OFF + DPO_ZL.CLK = PIXEL_CLK; + DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[]6/2 WORD RESP LONG ONLY + VR_WR.CLK = MAIN_CLK; + VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; + VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; + VR_DOUT[].ENA = !VR_BUSY; + VR_DOUT[] = VR_D[]; + VR_FRQ[].CLK = MAIN_CLK; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[] = FB_AD[23..16]; +-- VIDEO PLL RECONFIG + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_RECONFIG.CLK = MAIN_CLK; + VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; +------------------------------------------------------------------------------------------------------------------------ + VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; +-------------- COLOR MODE IM ACP SETZEN + COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; + ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; + FALCON_VIDEO = ACP_VCTR7; + FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; + ST_VIDEO = ACP_VCTR6; + ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; + CCSEL[].CLK = PIXEL_CLK; + CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION + # B"001" & FALCON_CLUT + # B"100" & ACP_CLUT + # B"101" & COLOR16 + # B"110" & COLOR24 + # B"111" & RAND_ON; +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + CCR[].CLK = MAIN_CLK; + CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + CCR[] = FB_AD[23..0]; + CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; + CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; + CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; +--SYS CTR + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + SYS_CTR[].CLK = MAIN_CLK; + SYS_CTR[6..0] = FB_AD[22..16]; + SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; + BLITTER_ON = !SYS_CTR3; +--VDL_LOF + VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 + VDL_LOF[].CLK = MAIN_CLK; + VDL_LOF[] = FB_AD[31..16]; + VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; + VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; +--VDL_LWD + VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + VDL_LWD[].CLK = MAIN_CLK; + VDL_LWD[] = FB_AD[31..16]; + VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; + VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; +-- HORIZONTAL +-- VDL_HHT + VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + VDL_HHT[].CLK = MAIN_CLK; + VDL_HHT[] = FB_AD[27..16]; + VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; + VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; +-- VDL_HBE + VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + VDL_HBE[].CLK = MAIN_CLK; + VDL_HBE[] = FB_AD[27..16]; + VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; + VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; +-- VDL_HDB + VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + VDL_HDB[].CLK = MAIN_CLK; + VDL_HDB[] = FB_AD[27..16]; + VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; + VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; +-- VDL_HDE + VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + VDL_HDE[].CLK = MAIN_CLK; + VDL_HDE[] = FB_AD[27..16]; + VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; + VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; +-- VDL_HBB + VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + VDL_HBB[].CLK = MAIN_CLK; + VDL_HBB[] = FB_AD[27..16]; + VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; + VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; +-- VDL_HSS + VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 + VDL_HSS[].CLK = MAIN_CLK; + VDL_HSS[] = FB_AD[27..16]; + VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; + VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; +-- VERTIKAL +-- VDL_VBE + VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 + VDL_VBE[].CLK = MAIN_CLK; + VDL_VBE[] = FB_AD[26..16]; + VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; + VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; +-- VDL_VDB + VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 + VDL_VDB[].CLK = MAIN_CLK; + VDL_VDB[] = FB_AD[26..16]; + VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; + VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; +-- VDL_VDE + VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 + VDL_VDE[].CLK = MAIN_CLK; + VDL_VDE[] = FB_AD[26..16]; + VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; + VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; +-- VDL_VBB + VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 + VDL_VBB[].CLK = MAIN_CLK; + VDL_VBB[] = FB_AD[26..16]; + VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; + VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; +-- VDL_VSS + VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 + VDL_VSS[].CLK = MAIN_CLK; + VDL_VSS[] = FB_AD[26..16]; + VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; + VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; +-- VDL_VFT + VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 + VDL_VFT[].CLK = MAIN_CLK; + VDL_VFT[] = FB_AD[26..16]; + VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; + VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; +-- VDL_VCT + VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 + VDL_VCT[].CLK = MAIN_CLK; + VDL_VCT[] = FB_AD[24..16]; + VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; + VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; +-- VDL_VMD + VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 + VDL_VMD[].CLK = MAIN_CLK; + VDL_VMD[] = FB_AD[19..16]; + VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; +--- REGISTER OUT + FB_AD[31..16] = lpm_bustri_WORD( + ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) + # VDL_LOF_CS & VDL_LOF[] + # VDL_LWD_CS & VDL_LWD[] + # VDL_HBE_CS & (0,VDL_HBE[]) + # VDL_HDB_CS & (0,VDL_HDB[]) + # VDL_HDE_CS & (0,VDL_HDE[]) + # VDL_HBB_CS & (0,VDL_HBB[]) + # VDL_HSS_CS & (0,VDL_HSS[]) + # VDL_HHT_CS & (0,VDL_HHT[]) + # VDL_VBE_CS & (0,VDL_VBE[]) + # VDL_VDB_CS & (0,VDL_VDB[]) + # VDL_VDE_CS & (0,VDL_VDE[]) + # VDL_VBB_CS & (0,VDL_VBB[]) + # VDL_VSS_CS & (0,VDL_VSS[]) + # VDL_VFT_CS & (0,VDL_VFT[]) + # VDL_VCT_CS & (0,VDL_VCT[]) + # VDL_VMD_CS & (0,VDL_VMD[]) + # ACP_VCTR_CS & ACP_VCTR[31..16] + # ATARI_HH_CS & ATARI_HH[31..16] + # ATARI_VH_CS & ATARI_VH[31..16] + # ATARI_HL_CS & ATARI_HL[31..16] + # ATARI_VL_CS & ATARI_VL[31..16] + # CCR_CS & (0,CCR[23..16]) + # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + + FB_AD[15..0] = lpm_bustri_WORD( + ACP_VCTR_CS & ACP_VCTR[15..0] + # ATARI_HH_CS & ATARI_HH[15..0] + # ATARI_VH_CS & ATARI_VH[15..0] + # ATARI_HL_CS & ATARI_HL[15..0] + # ATARI_VL_CS & ATARI_VL[15..0] + # CCR_CS & CCR[15..0] + ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M.CLK = CLK33M; + CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; + CLK13M = !CLK13M; + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; +-------------------------------------------------------------- +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +---------------------------------------------------------------- + HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + + MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VDL_VMD2 + # 16 & ST_VIDEO & VDL_VMD2 + # 32 & ST_VIDEO & !VDL_VMD2; + + + HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN + # 640 & !VDL_VMD2; + +-- DOPPELZEILENMODUS + DOP_ZEI.CLK = MAIN_CLK; + DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; + INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + + RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON + # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- + HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON + # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- + RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON + # HDIS_END[]+1 & !ACP_VIDEO_ON; -- + HS_START[] = VDL_HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON + # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VS_START[] = VDL_VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; +-- ZÄHLER + LAST.CLK = PIXEL_CLK; + LAST = VHCNT[]==(H_TOTAL[]-2); + VHCNT[].CLK = PIXEL_CLK; + VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; + VVCNT[].ENA = LAST; + VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); +-- DISPLAY ON OFF + DPO_ZL.CLK = PIXEL_CLK; + DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] + + + + + + + + + + + + + + + diff --git a/FPGA_quartus/Video/altddio_bidir0.qip b/FPGA_quartus/Video/altddio_bidir0.qip new file mode 100644 index 0000000..3339057 --- /dev/null +++ b/FPGA_quartus/Video/altddio_bidir0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] diff --git a/FPGA_quartus/Video/altddio_bidir0.vhd b/FPGA_quartus/Video/altddio_bidir0.vhd new file mode 100644 index 0000000..a0ae0e0 --- /dev/null +++ b/FPGA_quartus/Video/altddio_bidir0.vhd @@ -0,0 +1,172 @@ +-- megafunction wizard: %ALTDDIO_BIDIR% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_bidir + +-- ============================================================ +-- File Name: altddio_bidir0.vhd +-- Megafunction Name(s): +-- altddio_bidir +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_bidir0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + oe : IN STD_LOGIC := '1'; + outclock : IN STD_LOGIC ; + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END altddio_bidir0; + + +ARCHITECTURE SYN OF altddio_bidir0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT altddio_bidir + GENERIC ( + extend_oe_disable : STRING; + implement_input_in_lcell : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + outclock : IN STD_LOGIC ; + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + oe : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout_h <= sub_wire0(31 DOWNTO 0); + combout <= sub_wire1(31 DOWNTO 0); + dataout_l <= sub_wire2(31 DOWNTO 0); + + altddio_bidir_component : altddio_bidir + GENERIC MAP ( + extend_oe_disable => "UNUSED", + implement_input_in_lcell => "ON", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_bidir", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 32 + ) + PORT MAP ( + outclock => outclock, + inclock => inclock, + oe => oe, + datain_h => datain_h, + datain_l => datain_l, + dataout_h => sub_wire0, + combout => sub_wire1, + dataout_l => sub_wire2, + padio => padio + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "1" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0] +-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0] +-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0] +-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0] +-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0] +-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock +-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0] +-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0 +-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0 +-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0 +-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0 +-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/Video/altddio_out0.bsf b/FPGA_quartus/Video/altddio_out0.bsf new file mode 100644 index 0000000..6554c2f --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8))) + (text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8))) + (text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "high" (rect 92 84 109 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/altddio_out0.cmp b/FPGA_quartus/Video/altddio_out0.cmp new file mode 100644 index 0000000..df70a5a --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out0 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/altddio_out0.inc b/FPGA_quartus/Video/altddio_out0.inc new file mode 100644 index 0000000..f534925 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out0 +( + datain_h[3..0], + datain_l[3..0], + outclock +) + +RETURNS ( + dataout[3..0] +); diff --git a/FPGA_quartus/Video/altddio_out0.ppf b/FPGA_quartus/Video/altddio_out0.ppf new file mode 100644 index 0000000..3f3cfb5 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_quartus/Video/altddio_out0.qip b/FPGA_quartus/Video/altddio_out0.qip new file mode 100644 index 0000000..8193856 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] diff --git a/FPGA_quartus/Video/altddio_out0.vhd b/FPGA_quartus/Video/altddio_out0.vhd new file mode 100644 index 0000000..f129798 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out0.vhd @@ -0,0 +1,136 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out0.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END altddio_out0; + + +ARCHITECTURE SYN OF altddio_out0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(3 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "ON", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "ON", + width => 4 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "4" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0] +-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0] +-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0 +-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0 +-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/Video/altddio_out1.bsf b/FPGA_quartus/Video/altddio_out1.bsf new file mode 100644 index 0000000..8289852 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/altddio_out1.cmp b/FPGA_quartus/Video/altddio_out1.cmp new file mode 100644 index 0000000..cdb7766 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out1 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/altddio_out1.inc b/FPGA_quartus/Video/altddio_out1.inc new file mode 100644 index 0000000..4d50b26 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out1 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_quartus/Video/altddio_out1.ppf b/FPGA_quartus/Video/altddio_out1.ppf new file mode 100644 index 0000000..9772cd3 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_quartus/Video/altddio_out1.qip b/FPGA_quartus/Video/altddio_out1.qip new file mode 100644 index 0000000..606e0b7 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"] diff --git a/FPGA_quartus/Video/altddio_out1.vhd b/FPGA_quartus/Video/altddio_out1.vhd new file mode 100644 index 0000000..cb76474 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out1.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out1.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out1 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out1; + + +ARCHITECTURE SYN OF altddio_out1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/Video/altddio_out2.bsf b/FPGA_quartus/Video/altddio_out2.bsf new file mode 100644 index 0000000..ff039ee --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8))) + (text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8))) + (text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/altddio_out2.cmp b/FPGA_quartus/Video/altddio_out2.cmp new file mode 100644 index 0000000..ad8aa55 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out2 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/altddio_out2.inc b/FPGA_quartus/Video/altddio_out2.inc new file mode 100644 index 0000000..2257c30 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out2 +( + datain_h[23..0], + datain_l[23..0], + outclock +) + +RETURNS ( + dataout[23..0] +); diff --git a/FPGA_quartus/Video/altddio_out2.ppf b/FPGA_quartus/Video/altddio_out2.ppf new file mode 100644 index 0000000..93df472 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_quartus/Video/altddio_out2.qip b/FPGA_quartus/Video/altddio_out2.qip new file mode 100644 index 0000000..d72d5ce --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] diff --git a/FPGA_quartus/Video/altddio_out2.vhd b/FPGA_quartus/Video/altddio_out2.vhd new file mode 100644 index 0000000..30a8586 --- /dev/null +++ b/FPGA_quartus/Video/altddio_out2.vhd @@ -0,0 +1,136 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out2.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out2 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END altddio_out2; + + +ARCHITECTURE SYN OF altddio_out2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(23 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 24 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0] +-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0] +-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0 +-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0 +-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/Video/altdpram0.bsf b/FPGA_quartus/Video/altdpram0.bsf new file mode 100644 index 0000000..e0d3ce3 --- /dev/null +++ b/FPGA_quartus/Video/altdpram0.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 112 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 112 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 112 128)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 176 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8))) + (line (pt 0 176)(pt 181 176)(line_width 1)) + ) + (port + (pt 256 32) + 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132)(line_width 1)) + (line (pt 120 128)(pt 128 128)(line_width 1)) + (line (pt 92 36)(pt 92 161)(line_width 1)) + (line (pt 176 36)(pt 176 161)(line_width 1)) + (line (pt 104 100)(pt 104 177)(line_width 1)) + (line (pt 181 100)(pt 181 177)(line_width 1)) + (line (pt 184 27)(pt 192 27)(line_width 1)) + (line (pt 192 27)(pt 192 39)(line_width 1)) + (line (pt 192 39)(pt 184 39)(line_width 1)) + (line (pt 184 39)(pt 184 27)(line_width 1)) + (line (pt 184 34)(pt 186 36)(line_width 1)) + (line (pt 186 36)(pt 184 38)(line_width 1)) + (line (pt 176 36)(pt 184 36)(line_width 1)) + (line (pt 168 32)(pt 184 32)(line_width 3)) + (line (pt 184 91)(pt 192 91)(line_width 1)) + (line (pt 192 91)(pt 192 103)(line_width 1)) + (line (pt 192 103)(pt 184 103)(line_width 1)) + (line (pt 184 103)(pt 184 91)(line_width 1)) + (line (pt 184 98)(pt 186 100)(line_width 1)) + (line (pt 186 100)(pt 184 102)(line_width 1)) + (line (pt 181 100)(pt 184 100)(line_width 1)) + (line (pt 168 96)(pt 184 96)(line_width 3)) + ) +) diff --git a/FPGA_quartus/Video/altdpram0.cmp b/FPGA_quartus/Video/altdpram0.cmp new file mode 100644 index 0000000..566f5cd --- /dev/null +++ b/FPGA_quartus/Video/altdpram0.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram0 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/altdpram0.inc b/FPGA_quartus/Video/altdpram0.inc new file mode 100644 index 0000000..828067d --- /dev/null +++ b/FPGA_quartus/Video/altdpram0.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram0 +( + address_a[3..0], + address_b[3..0], + clock_a, + clock_b, + data_a[2..0], + data_b[2..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[2..0], + q_b[2..0] +); diff --git a/FPGA_quartus/Video/altdpram0.qip b/FPGA_quartus/Video/altdpram0.qip new file mode 100644 index 0000000..e4d02ab --- /dev/null +++ b/FPGA_quartus/Video/altdpram0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"] diff --git a/FPGA_quartus/Video/altdpram0.vhd b/FPGA_quartus/Video/altdpram0.vhd new file mode 100644 index 0000000..c883f02 --- /dev/null +++ b/FPGA_quartus/Video/altdpram0.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram0.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram0 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +END altdpram0; + + +ARCHITECTURE SYN OF altdpram0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(2 DOWNTO 0); + q_b <= sub_wire1(2 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 16, + numwords_b => 16, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 4, + widthad_b => 4, + width_a => 3, + width_b => 3, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0] +-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0] +-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0] +-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0] +-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0 +-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0 +-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0 +-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0 +-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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Sample behavioral waveforms for design file altdpram0.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_quartus/Video/altdpram1.bsf b/FPGA_quartus/Video/altdpram1.bsf new file mode 100644 index 0000000..d75db28 --- /dev/null +++ b/FPGA_quartus/Video/altdpram1.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 112 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 112 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 112 128)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 176 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8))) + (line (pt 0 176)(pt 181 176)(line_width 1)) + ) + (port + (pt 256 32) + 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+ ) +) diff --git a/FPGA_quartus/Video/altdpram1.cmp b/FPGA_quartus/Video/altdpram1.cmp new file mode 100644 index 0000000..a482250 --- /dev/null +++ b/FPGA_quartus/Video/altdpram1.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram1 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/altdpram1.inc b/FPGA_quartus/Video/altdpram1.inc new file mode 100644 index 0000000..4a7924e --- /dev/null +++ b/FPGA_quartus/Video/altdpram1.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram1 +( + address_a[7..0], + address_b[7..0], + clock_a, + clock_b, + data_a[5..0], + data_b[5..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[5..0], + q_b[5..0] +); diff --git a/FPGA_quartus/Video/altdpram1.qip b/FPGA_quartus/Video/altdpram1.qip new file mode 100644 index 0000000..cdd178f --- /dev/null +++ b/FPGA_quartus/Video/altdpram1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"] diff --git a/FPGA_quartus/Video/altdpram1.vhd b/FPGA_quartus/Video/altdpram1.vhd new file mode 100644 index 0000000..b2e0435 --- /dev/null +++ b/FPGA_quartus/Video/altdpram1.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram1.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram1 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +END altdpram1; + + +ARCHITECTURE SYN OF altdpram1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(5 DOWNTO 0); + q_b <= sub_wire1(5 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 256, + numwords_b => 256, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 8, + widthad_b => 8, + width_a => 6, + width_b => 6, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0] +-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0] +-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0] +-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0] +-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0 +-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0 +-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0 +-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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zpZhYz=TR0wc$OwW%DTrC2%p^WMhL$K0@hac&wNnx2q1hy1*_Yg57M4r2*y&0pC8T| zAbjYzjp@Zxl>eTV|L3)g7P>gTi!Gm`$08ed zw)&84@$|jebc8g)k?OBMJV$Es=Kd17h9H|MiDMcp8o#Oke)tT9w>WWMS-Lsl@m49r zCJT0Qu+{Bj7te(>`;7YL(a$s$SvF%mu><+BX|C6py);*a%=sdt2fb7`X`5KN?668| z7d$ODhIy#0p9 + +Sample Waveforms for altdpram1.vhd + + +

Sample behavioral waveforms for design file altdpram1.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_quartus/Video/altdpram2.bsf b/FPGA_quartus/Video/altdpram2.bsf new file mode 100644 index 0000000..75c64aa --- /dev/null +++ b/FPGA_quartus/Video/altdpram2.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 112 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 112 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 112 128)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 176 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8))) + (line (pt 0 176)(pt 181 176)(line_width 1)) + ) + (port + (pt 256 32) + (output) + (text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8))) + (line (pt 256 32)(pt 192 32)(line_width 3)) + ) + (port + (pt 256 96) + (output) + (text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8))) + (line (pt 256 96)(pt 192 96)(line_width 3)) + ) + (drawing + (text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical)) + (text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical)) + (text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" )) + (line (pt 128 24)(pt 168 24)(line_width 1)) + (line (pt 168 24)(pt 168 144)(line_width 1)) + (line (pt 168 144)(pt 128 144)(line_width 1)) + (line (pt 128 144)(pt 128 24)(line_width 1)) + (line (pt 112 27)(pt 120 27)(line_width 1)) + (line (pt 120 27)(pt 120 39)(line_width 1)) + (line (pt 120 39)(pt 112 39)(line_width 1)) + (line (pt 112 39)(pt 112 27)(line_width 1)) + (line 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132)(line_width 1)) + (line (pt 120 128)(pt 128 128)(line_width 1)) + (line (pt 92 36)(pt 92 161)(line_width 1)) + (line (pt 176 36)(pt 176 161)(line_width 1)) + (line (pt 104 100)(pt 104 177)(line_width 1)) + (line (pt 181 100)(pt 181 177)(line_width 1)) + (line (pt 184 27)(pt 192 27)(line_width 1)) + (line (pt 192 27)(pt 192 39)(line_width 1)) + (line (pt 192 39)(pt 184 39)(line_width 1)) + (line (pt 184 39)(pt 184 27)(line_width 1)) + (line (pt 184 34)(pt 186 36)(line_width 1)) + (line (pt 186 36)(pt 184 38)(line_width 1)) + (line (pt 176 36)(pt 184 36)(line_width 1)) + (line (pt 168 32)(pt 184 32)(line_width 3)) + (line (pt 184 91)(pt 192 91)(line_width 1)) + (line (pt 192 91)(pt 192 103)(line_width 1)) + (line (pt 192 103)(pt 184 103)(line_width 1)) + (line (pt 184 103)(pt 184 91)(line_width 1)) + (line (pt 184 98)(pt 186 100)(line_width 1)) + (line (pt 186 100)(pt 184 102)(line_width 1)) + (line (pt 181 100)(pt 184 100)(line_width 1)) + (line (pt 168 96)(pt 184 96)(line_width 3)) + ) +) diff --git a/FPGA_quartus/Video/altdpram2.cmp b/FPGA_quartus/Video/altdpram2.cmp new file mode 100644 index 0000000..4895f04 --- /dev/null +++ b/FPGA_quartus/Video/altdpram2.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram2 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/altdpram2.inc b/FPGA_quartus/Video/altdpram2.inc new file mode 100644 index 0000000..1909de8 --- /dev/null +++ b/FPGA_quartus/Video/altdpram2.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram2 +( + address_a[7..0], + address_b[7..0], + clock_a, + clock_b, + data_a[7..0], + data_b[7..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[7..0], + q_b[7..0] +); diff --git a/FPGA_quartus/Video/altdpram2.qip b/FPGA_quartus/Video/altdpram2.qip new file mode 100644 index 0000000..f84925c --- /dev/null +++ b/FPGA_quartus/Video/altdpram2.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"] diff --git a/FPGA_quartus/Video/altdpram2.vhd b/FPGA_quartus/Video/altdpram2.vhd new file mode 100644 index 0000000..238e6f3 --- /dev/null +++ b/FPGA_quartus/Video/altdpram2.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram2.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram2 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END altdpram2; + + +ARCHITECTURE SYN OF altdpram2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(7 DOWNTO 0); + q_b <= sub_wire1(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 256, + numwords_b => 256, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 8, + widthad_b => 8, + width_a => 8, + width_b => 8, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0] +-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] +-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] +-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] +-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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Sample behavioral waveforms for design file altdpram2.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_quartus/Video/lpm_bustri0.bsf b/FPGA_quartus/Video/lpm_bustri0.bsf new file mode 100644 index 0000000..f65e217 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri0.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "32" (rect 61 25 71 37)(font "Arial" )) + (text "32" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri0.cmp b/FPGA_quartus/Video/lpm_bustri0.cmp new file mode 100644 index 0000000..9426443 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri0.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri0 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri0.inc b/FPGA_quartus/Video/lpm_bustri0.inc new file mode 100644 index 0000000..1b15c22 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri0.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri0 +( + data[31..0], + enabledt +) + +RETURNS ( + tridata[31..0] +); diff --git a/FPGA_quartus/Video/lpm_bustri0.qip b/FPGA_quartus/Video/lpm_bustri0.qip new file mode 100644 index 0000000..c70041d --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri0.vhd b/FPGA_quartus/Video/lpm_bustri0.vhd new file mode 100644 index 0000000..494b3c2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri0.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri0.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri0 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_bustri0; + + +ARCHITECTURE SYN OF lpm_bustri0 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 32 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0] +-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri1.bsf b/FPGA_quartus/Video/lpm_bustri1.bsf new file mode 100644 index 0000000..058fffb --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "3" (rect 63 25 68 37)(font "Arial" )) + (text "3" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri1.cmp b/FPGA_quartus/Video/lpm_bustri1.cmp new file mode 100644 index 0000000..48a33f0 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri1 + PORT + ( + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri1.qip b/FPGA_quartus/Video/lpm_bustri1.qip new file mode 100644 index 0000000..fd76bb2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri1.vhd b/FPGA_quartus/Video/lpm_bustri1.vhd new file mode 100644 index 0000000..47db597 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri1.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri1.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri1 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +END lpm_bustri1; + + +ARCHITECTURE SYN OF lpm_bustri1 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 3 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "3" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3" +-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0] +-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0 +-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri2.bsf b/FPGA_quartus/Video/lpm_bustri2.bsf new file mode 100644 index 0000000..36a4813 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "18" (rect 61 25 71 37)(font "Arial" )) + (text "18" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri2.cmp b/FPGA_quartus/Video/lpm_bustri2.cmp new file mode 100644 index 0000000..e45fbdd --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri2 + PORT + ( + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri2.qip b/FPGA_quartus/Video/lpm_bustri2.qip new file mode 100644 index 0000000..676e430 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri2.vhd b/FPGA_quartus/Video/lpm_bustri2.vhd new file mode 100644 index 0000000..0966743 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri2.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri2.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri2 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END lpm_bustri2; + + +ARCHITECTURE SYN OF lpm_bustri2 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 18 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "18" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0] +-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0 +-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri3.bsf b/FPGA_quartus/Video/lpm_bustri3.bsf new file mode 100644 index 0000000..2dde401 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "6" (rect 63 25 68 37)(font "Arial" )) + (text "6" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri3.cmp b/FPGA_quartus/Video/lpm_bustri3.cmp new file mode 100644 index 0000000..f3836e3 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri3 + PORT + ( + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri3.qip b/FPGA_quartus/Video/lpm_bustri3.qip new file mode 100644 index 0000000..8c41556 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri3.vhd b/FPGA_quartus/Video/lpm_bustri3.vhd new file mode 100644 index 0000000..2344712 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri3.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri3.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri3 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +END lpm_bustri3; + + +ARCHITECTURE SYN OF lpm_bustri3 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 6 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "6" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6" +-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0] +-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0 +-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri4.bsf b/FPGA_quartus/Video/lpm_bustri4.bsf new file mode 100644 index 0000000..cd9edcc --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "5" (rect 63 25 68 37)(font "Arial" )) + (text "5" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri4.cmp b/FPGA_quartus/Video/lpm_bustri4.cmp new file mode 100644 index 0000000..37bee59 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri4 + PORT + ( + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri4.qip b/FPGA_quartus/Video/lpm_bustri4.qip new file mode 100644 index 0000000..39eb21d --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri4.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri4.vhd b/FPGA_quartus/Video/lpm_bustri4.vhd new file mode 100644 index 0000000..5bb209b --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri4.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri4.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri4 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_bustri4; + + +ARCHITECTURE SYN OF lpm_bustri4 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 5 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0] +-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0 +-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri5.bsf b/FPGA_quartus/Video/lpm_bustri5.bsf new file mode 100644 index 0000000..1d9b178 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "8" (rect 63 25 68 37)(font "Arial" )) + (text "8" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri5.cmp b/FPGA_quartus/Video/lpm_bustri5.cmp new file mode 100644 index 0000000..5c719c7 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri5 + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri5.inc b/FPGA_quartus/Video/lpm_bustri5.inc new file mode 100644 index 0000000..fdb4877 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri5 +( + data[7..0], + enabledt +) + +RETURNS ( + tridata[7..0] +); diff --git a/FPGA_quartus/Video/lpm_bustri5.qip b/FPGA_quartus/Video/lpm_bustri5.qip new file mode 100644 index 0000000..daa3efa --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri5.vhd b/FPGA_quartus/Video/lpm_bustri5.vhd new file mode 100644 index 0000000..e1973b4 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri5.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri5.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri5 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_bustri5; + + +ARCHITECTURE SYN OF lpm_bustri5 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 8 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0] +-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri6.bsf b/FPGA_quartus/Video/lpm_bustri6.bsf new file mode 100644 index 0000000..4c9344e --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri6.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "24" (rect 61 25 71 37)(font "Arial" )) + (text "24" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri6.cmp b/FPGA_quartus/Video/lpm_bustri6.cmp new file mode 100644 index 0000000..67529c9 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri6.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri6 + PORT + ( + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri6.qip b/FPGA_quartus/Video/lpm_bustri6.qip new file mode 100644 index 0000000..6b9f1df --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri6.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri6.vhd b/FPGA_quartus/Video/lpm_bustri6.vhd new file mode 100644 index 0000000..45f409f --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri6.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri6.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri6 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_bustri6; + + +ARCHITECTURE SYN OF lpm_bustri6 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 24 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0] +-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0 +-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_bustri7.bsf b/FPGA_quartus/Video/lpm_bustri7.bsf new file mode 100644 index 0000000..399a828 --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri7.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "4" (rect 63 25 68 37)(font "Arial" )) + (text "4" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_bustri7.cmp b/FPGA_quartus/Video/lpm_bustri7.cmp new file mode 100644 index 0000000..2d5983d --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri7.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri7 + PORT + ( + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_bustri7.qip b/FPGA_quartus/Video/lpm_bustri7.qip new file mode 100644 index 0000000..f32324c --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri7.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"] diff --git a/FPGA_quartus/Video/lpm_bustri7.vhd b/FPGA_quartus/Video/lpm_bustri7.vhd new file mode 100644 index 0000000..4bf883d --- /dev/null +++ b/FPGA_quartus/Video/lpm_bustri7.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri7.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri7 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END lpm_bustri7; + + +ARCHITECTURE SYN OF lpm_bustri7 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 4 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0] +-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0 +-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_compare1.bsf b/FPGA_quartus/Video/lpm_compare1.bsf new file mode 100644 index 0000000..9ec3796 --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1.bsf @@ -0,0 +1,54 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 128 96) + (text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 128 56) + (output) + (text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8))) + (line (pt 128 56)(pt 112 56)(line_width 1)) + ) + (drawing + (text "unsigned compare" (rect 36 17 112 29)(font "Arial" )) + (line (pt 16 16)(pt 112 16)(line_width 1)) + (line (pt 112 16)(pt 112 80)(line_width 1)) + (line (pt 112 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_compare1.cmp b/FPGA_quartus/Video/lpm_compare1.cmp new file mode 100644 index 0000000..9bab50e --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_compare1 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_compare1.inc b/FPGA_quartus/Video/lpm_compare1.inc new file mode 100644 index 0000000..bde0ab9 --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_compare1 +( + dataa[10..0], + datab[10..0] +) + +RETURNS ( + AgB +); diff --git a/FPGA_quartus/Video/lpm_compare1.qip b/FPGA_quartus/Video/lpm_compare1.qip new file mode 100644 index 0000000..ea93f3c --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"] diff --git a/FPGA_quartus/Video/lpm_compare1.vhd b/FPGA_quartus/Video/lpm_compare1.vhd new file mode 100644 index 0000000..a85e3b2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_COMPARE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_compare + +-- ============================================================ +-- File Name: lpm_compare1.vhd +-- Megafunction Name(s): +-- lpm_compare +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_compare1 IS + PORT + ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); +END lpm_compare1; + + +ARCHITECTURE SYN OF lpm_compare1 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_compare + GENERIC ( + lpm_representation : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + AgB <= sub_wire0; + + lpm_compare_component : lpm_compare + GENERIC MAP ( + lpm_representation => "UNSIGNED", + lpm_type => "LPM_COMPARE", + lpm_width => 11 + ) + PORT MAP ( + dataa => dataa, + datab => datab, + AgB => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AeqB NUMERIC "0" +-- Retrieval info: PRIVATE: AgeB NUMERIC "0" +-- Retrieval info: PRIVATE: AgtB NUMERIC "1" +-- Retrieval info: PRIVATE: AleB NUMERIC "0" +-- Retrieval info: PRIVATE: AltB NUMERIC "0" +-- Retrieval info: PRIVATE: AneB NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +-- Retrieval info: PRIVATE: Latency NUMERIC "0" +-- Retrieval info: PRIVATE: PortBValue NUMERIC "0" +-- Retrieval info: PRIVATE: Radix NUMERIC "10" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: clken NUMERIC "0" +-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "11" +-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11" +-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB +-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0] +-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0] +-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0 +-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0 +-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE +-- Retrieval info: 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zfvXy|@(n5Dc;Wg3=%qa1lvltYf%`D{CmSeFga(d=4@QZxo}=Qy_xAZW2YPRx|GdE7 z+vmM~evSK&W$YM56RL~I7mPL{N8r>dNh}w&JKXW}F03Aapw4ibIAyT?>($61k?04~ zI3X3+vj(&UULAZzCcn~$CWPb8{`;236W?y?k8)mSP*V!#=j<4&y{*d!x+PTgn{;bC zs-w!W;K_myZFTETPbZSiwoZ(Eyyld3w&3y$MP9i66_QIC>DjQtoe3Q69uOQ7%wYlt vAo&Z$6#<1~#YdBktnd0+9AG^!oKS0e^VsMLG5LRnLw*S?^E3LuZw&ku=0&5V literal 0 HcmV?d00001 diff --git a/FPGA_quartus/Video/lpm_compare1_waveforms.html b/FPGA_quartus/Video/lpm_compare1_waveforms.html new file mode 100644 index 0000000..e8242d9 --- /dev/null +++ b/FPGA_quartus/Video/lpm_compare1_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for lpm_compare1.vhd + + +

Sample behavioral waveforms for design file lpm_compare1.vhd

+

The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator.

+
+

Fig. 1 : Wave showing comparator operation.

+

+

+ + diff --git a/FPGA_quartus/Video/lpm_constant0.bsf b/FPGA_quartus/Video/lpm_constant0.bsf new file mode 100644 index 0000000..684bbae --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant0.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "5" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_constant0.cmp b/FPGA_quartus/Video/lpm_constant0.cmp new file mode 100644 index 0000000..7143429 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant0.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant0 + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_constant0.qip b/FPGA_quartus/Video/lpm_constant0.qip new file mode 100644 index 0000000..bb19c49 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"] diff --git a/FPGA_quartus/Video/lpm_constant0.vhd b/FPGA_quartus/Video/lpm_constant0.vhd new file mode 100644 index 0000000..63631cc --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant0.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant0.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant0 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_constant0; + + +ARCHITECTURE SYN OF lpm_constant0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(4 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 5 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0] +-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_constant1.bsf b/FPGA_quartus/Video/lpm_constant1.bsf new file mode 100644 index 0000000..01fdb2b --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant1.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "2" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_constant1.cmp b/FPGA_quartus/Video/lpm_constant1.cmp new file mode 100644 index 0000000..a7e275c --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant1.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant1 + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_constant1.inc b/FPGA_quartus/Video/lpm_constant1.inc new file mode 100644 index 0000000..9b556e7 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant1.inc @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_constant1 +( + +) + +RETURNS ( + result[1..0] +); diff --git a/FPGA_quartus/Video/lpm_constant1.qip b/FPGA_quartus/Video/lpm_constant1.qip new file mode 100644 index 0000000..2bc12e7 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"] diff --git a/FPGA_quartus/Video/lpm_constant1.vhd b/FPGA_quartus/Video/lpm_constant1.vhd new file mode 100644 index 0000000..afa67ba --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant1.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant1.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant1 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END lpm_constant1; + + +ARCHITECTURE SYN OF lpm_constant1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(1 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 2 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0] +-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_constant2.bsf b/FPGA_quartus/Video/lpm_constant2.bsf new file mode 100644 index 0000000..a4b7697 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant2.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "8" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_constant2.cmp b/FPGA_quartus/Video/lpm_constant2.cmp new file mode 100644 index 0000000..63cc406 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant2.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant2 + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_constant2.qip b/FPGA_quartus/Video/lpm_constant2.qip new file mode 100644 index 0000000..ad38485 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"] diff --git a/FPGA_quartus/Video/lpm_constant2.vhd b/FPGA_quartus/Video/lpm_constant2.vhd new file mode 100644 index 0000000..f25e68f --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant2.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant2.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant2 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_constant2; + + +ARCHITECTURE SYN OF lpm_constant2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(7 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 8 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_constant3.bsf b/FPGA_quartus/Video/lpm_constant3.bsf new file mode 100644 index 0000000..7616869 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant3.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "7" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_constant3.cmp b/FPGA_quartus/Video/lpm_constant3.cmp new file mode 100644 index 0000000..0e2f877 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant3.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant3 + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_constant3.qip b/FPGA_quartus/Video/lpm_constant3.qip new file mode 100644 index 0000000..615a781 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"] diff --git a/FPGA_quartus/Video/lpm_constant3.vhd b/FPGA_quartus/Video/lpm_constant3.vhd new file mode 100644 index 0000000..5d47d8e --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant3.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant3.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant3 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_constant3; + + +ARCHITECTURE SYN OF lpm_constant3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(6 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 7 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_constant4.bsf b/FPGA_quartus/Video/lpm_constant4.bsf new file mode 100644 index 0000000..181c667 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant4.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "2040" (rect 60 18 80 30)(font "Arial" )) + (text "11" (rect 85 25 95 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 80 28)(pt 88 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_constant4.cmp b/FPGA_quartus/Video/lpm_constant4.cmp new file mode 100644 index 0000000..fd7f4cd --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant4.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant4 + PORT + ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_constant4.inc b/FPGA_quartus/Video/lpm_constant4.inc new file mode 100644 index 0000000..a913739 --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant4.inc @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_constant4 +( + +) + +RETURNS ( + result[10..0] +); diff --git a/FPGA_quartus/Video/lpm_constant4.qip b/FPGA_quartus/Video/lpm_constant4.qip new file mode 100644 index 0000000..44fa63f --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.cmp"] diff --git a/FPGA_quartus/Video/lpm_constant4.vhd b/FPGA_quartus/Video/lpm_constant4.vhd new file mode 100644 index 0000000..e0fc73d --- /dev/null +++ b/FPGA_quartus/Video/lpm_constant4.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant4.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant4 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); +END lpm_constant4; + + +ARCHITECTURE SYN OF lpm_constant4 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (10 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(10 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 2040, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 11 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "10" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "2040" +-- Retrieval info: PRIVATE: nBit NUMERIC "11" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2040" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11" +-- Retrieval info: USED_PORT: result 0 0 11 0 OUTPUT NODEFVAL result[10..0] +-- Retrieval info: CONNECT: result 0 0 11 0 @result 0 0 11 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff0.bsf b/FPGA_quartus/Video/lpm_ff0.bsf new file mode 100644 index 0000000..6675606 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff0.bsf @@ -0,0 +1,63 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 96) + (text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 144 56) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8))) + (line (pt 144 56)(pt 128 56)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 80)(line_width 1)) + (line (pt 128 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff0.cmp b/FPGA_quartus/Video/lpm_ff0.cmp new file mode 100644 index 0000000..0d8e769 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff0 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff0.qip b/FPGA_quartus/Video/lpm_ff0.qip new file mode 100644 index 0000000..d33c680 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff0.vhd b/FPGA_quartus/Video/lpm_ff0.vhd new file mode 100644 index 0000000..4c17d8f --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff0.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff0.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff0 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_ff0; + + +ARCHITECTURE SYN OF lpm_ff0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enable : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 32 + ) + PORT MAP ( + enable => enable, + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff1.bsf b/FPGA_quartus/Video/lpm_ff1.bsf new file mode 100644 index 0000000..947a023 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff1.cmp b/FPGA_quartus/Video/lpm_ff1.cmp new file mode 100644 index 0000000..4b25f14 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff1 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff1.qip b/FPGA_quartus/Video/lpm_ff1.qip new file mode 100644 index 0000000..94b30af --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff1.vhd b/FPGA_quartus/Video/lpm_ff1.vhd new file mode 100644 index 0000000..da02a15 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff1.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff1.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff1 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_ff1; + + +ARCHITECTURE SYN OF lpm_ff1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 32 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff2.bsf b/FPGA_quartus/Video/lpm_ff2.bsf new file mode 100644 index 0000000..b52c75b --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff2.cmp b/FPGA_quartus/Video/lpm_ff2.cmp new file mode 100644 index 0000000..6b5b979 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff2 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff2.qip b/FPGA_quartus/Video/lpm_ff2.qip new file mode 100644 index 0000000..9c46273 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff2.vhd b/FPGA_quartus/Video/lpm_ff2.vhd new file mode 100644 index 0000000..27b4c3a --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff2.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff2.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff2 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_ff2; + + +ARCHITECTURE SYN OF lpm_ff2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 128 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff3.bsf b/FPGA_quartus/Video/lpm_ff3.bsf new file mode 100644 index 0000000..51248ea --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff3.cmp b/FPGA_quartus/Video/lpm_ff3.cmp new file mode 100644 index 0000000..b3b5513 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff3 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff3.qip b/FPGA_quartus/Video/lpm_ff3.qip new file mode 100644 index 0000000..98d1312 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff3.vhd b/FPGA_quartus/Video/lpm_ff3.vhd new file mode 100644 index 0000000..a86b4ee --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff3.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff3.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff3 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_ff3; + + +ARCHITECTURE SYN OF lpm_ff3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(23 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 24 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0] +-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL q[23..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0 +-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff4.bsf b/FPGA_quartus/Video/lpm_ff4.bsf new file mode 100644 index 0000000..be432cb --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff4.cmp b/FPGA_quartus/Video/lpm_ff4.cmp new file mode 100644 index 0000000..f3a15e2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff4 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff4.inc b/FPGA_quartus/Video/lpm_ff4.inc new file mode 100644 index 0000000..ea243d6 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff4.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff4 +( + clock, + data[15..0] +) + +RETURNS ( + q[15..0] +); diff --git a/FPGA_quartus/Video/lpm_ff4.qip b/FPGA_quartus/Video/lpm_ff4.qip new file mode 100644 index 0000000..f5a0a35 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff4.vhd b/FPGA_quartus/Video/lpm_ff4.vhd new file mode 100644 index 0000000..a738a64 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff4.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff4.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff4 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_ff4; + + +ARCHITECTURE SYN OF lpm_ff4 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(15 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 16 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff5.bsf b/FPGA_quartus/Video/lpm_ff5.bsf new file mode 100644 index 0000000..a69af6e --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff5.cmp b/FPGA_quartus/Video/lpm_ff5.cmp new file mode 100644 index 0000000..6ad77c9 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff5 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff5.inc b/FPGA_quartus/Video/lpm_ff5.inc new file mode 100644 index 0000000..f65f941 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff5 +( + clock, + data[7..0] +) + +RETURNS ( + q[7..0] +); diff --git a/FPGA_quartus/Video/lpm_ff5.qip b/FPGA_quartus/Video/lpm_ff5.qip new file mode 100644 index 0000000..0d13267 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff5.vhd b/FPGA_quartus/Video/lpm_ff5.vhd new file mode 100644 index 0000000..96063a2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff5.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff5.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff5 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_ff5; + + +ARCHITECTURE SYN OF lpm_ff5 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 8 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_ff6.bsf b/FPGA_quartus/Video/lpm_ff6.bsf new file mode 100644 index 0000000..73a2df0 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff6.bsf @@ -0,0 +1,63 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 96) + (text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 144 56) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8))) + (line (pt 144 56)(pt 128 56)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 80)(line_width 1)) + (line (pt 128 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_ff6.cmp b/FPGA_quartus/Video/lpm_ff6.cmp new file mode 100644 index 0000000..50df3ad --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff6.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff6 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_ff6.inc b/FPGA_quartus/Video/lpm_ff6.inc new file mode 100644 index 0000000..c8a5a36 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff6.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff6 +( + clock, + data[127..0], + enable +) + +RETURNS ( + q[127..0] +); diff --git a/FPGA_quartus/Video/lpm_ff6.qip b/FPGA_quartus/Video/lpm_ff6.qip new file mode 100644 index 0000000..08e02f0 --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.cmp"] diff --git a/FPGA_quartus/Video/lpm_ff6.vhd b/FPGA_quartus/Video/lpm_ff6.vhd new file mode 100644 index 0000000..5cc384d --- /dev/null +++ b/FPGA_quartus/Video/lpm_ff6.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff6.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff6 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_ff6; + + +ARCHITECTURE SYN OF lpm_ff6 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enable : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 128 + ) + PORT MAP ( + enable => enable, + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_fifoDZ.bsf b/FPGA_quartus/Video/lpm_fifoDZ.bsf new file mode 100644 index 0000000..1e24640 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifoDZ.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 125 31 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (text "(ack)" (rect 51 67 76 81)(font "Arial" )) + (text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 128)(line_width 1)) + (line (pt 144 128)(pt 16 128)(line_width 1)) + (line (pt 16 128)(pt 16 16)(line_width 1)) + (line (pt 16 108)(pt 144 108)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_fifoDZ.cmp b/FPGA_quartus/Video/lpm_fifoDZ.cmp new file mode 100644 index 0000000..153e7c2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifoDZ.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_fifoDZ + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_fifoDZ.qip b/FPGA_quartus/Video/lpm_fifoDZ.qip new file mode 100644 index 0000000..5444627 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifoDZ.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"] diff --git a/FPGA_quartus/Video/lpm_fifoDZ.vhd b/FPGA_quartus/Video/lpm_fifoDZ.vhd new file mode 100644 index 0000000..95486bb --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifoDZ.vhd @@ -0,0 +1,178 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: scfifo + +-- ============================================================ +-- File Name: lpm_fifoDZ.vhd +-- Megafunction Name(s): +-- scfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY lpm_fifoDZ IS + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_fifoDZ; + + +ARCHITECTURE SYN OF lpm_fifodz IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + rdreq : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone III", + lpm_numwords => 128, + lpm_showahead => "ON", + lpm_type => "scfifo", + lpm_width => 128, + lpm_widthu => 7, + overflow_checking => "OFF", + underflow_checking => "OFF", + use_eab => "ON" + ) + PORT MAP ( + rdreq => rdreq, + aclr => aclr, + clock => clock, + wrreq => wrreq, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "128" +-- Retrieval info: PRIVATE: Empty NUMERIC "0" +-- Retrieval info: PRIVATE: Full NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: Optimize NUMERIC "2" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: UsedW NUMERIC "0" +-- Retrieval info: PRIVATE: Width NUMERIC "128" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "128" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE +-- Retrieval info: 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y)%>aEo}GoW0SyZTGqu#@w$prn)1gamo!{PbIi?$A@>Q7a|G)m*bFli4iT?yQZa#(p literal 0 HcmV?d00001 diff --git a/FPGA_quartus/Video/lpm_fifoDZ_waveforms.html b/FPGA_quartus/Video/lpm_fifoDZ_waveforms.html new file mode 100644 index 0000000..467441f --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifoDZ_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for "lpm_fifoDZ.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifoDZ.vhd"

+

The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_quartus/Video/lpm_fifo_dc0.bsf b/FPGA_quartus/Video/lpm_fifo_dc0.bsf new file mode 100644 index 0000000..61b485b --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifo_dc0.bsf @@ -0,0 +1,102 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) + (text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (drawing + (text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_fifo_dc0.cmp b/FPGA_quartus/Video/lpm_fifo_dc0.cmp new file mode 100644 index 0000000..08f6114 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifo_dc0.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_fifo_dc0 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_fifo_dc0.inc b/FPGA_quartus/Video/lpm_fifo_dc0.inc new file mode 100644 index 0000000..d29fb88 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifo_dc0.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_fifo_dc0 +( + aclr, + data[127..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[127..0], + rdempty, + wrusedw[8..0] +); diff --git a/FPGA_quartus/Video/lpm_fifo_dc0.qip b/FPGA_quartus/Video/lpm_fifo_dc0.qip new file mode 100644 index 0000000..e883724 --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifo_dc0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.cmp"] diff --git a/FPGA_quartus/Video/lpm_fifo_dc0.vhd b/FPGA_quartus/Video/lpm_fifo_dc0.vhd new file mode 100644 index 0000000..8646d9c --- /dev/null +++ b/FPGA_quartus/Video/lpm_fifo_dc0.vhd @@ -0,0 +1,203 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo + +-- ============================================================ +-- File Name: lpm_fifo_dc0.vhd +-- Megafunction Name(s): +-- dcfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY lpm_fifo_dc0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); +END lpm_fifo_dc0; + + +ARCHITECTURE SYN OF lpm_fifo_dc0 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT dcfifo + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdempty : OUT STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + rdempty <= sub_wire0; + wrusedw <= sub_wire1(8 DOWNTO 0); + q <= sub_wire2(127 DOWNTO 0); + + dcfifo_component : dcfifo + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 512, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 128, + lpm_widthu => 9, + overflow_checking => "OFF", + rdsync_delaypipe => 6, + underflow_checking => "OFF", + use_eab => "ON", + write_aclr_synch => "ON", + wrsync_delaypipe => 6 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + rdempty => sub_wire0, + wrusedw => sub_wire1, + q => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "512" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "128" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "128" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "6" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0] +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL 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Sample behavioral waveforms for design file lpm_fifo_dc0.vhd

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The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd. The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

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Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_quartus/Video/lpm_latch1.bsf b/FPGA_quartus/Video/lpm_latch1.bsf new file mode 100644 index 0000000..7197b2f --- /dev/null +++ b/FPGA_quartus/Video/lpm_latch1.bsf @@ -0,0 +1,53 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 80) + (text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) + (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 64)(line_width 1)) + (line (pt 144 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_latch1.cmp b/FPGA_quartus/Video/lpm_latch1.cmp new file mode 100644 index 0000000..ac4b322 --- /dev/null +++ b/FPGA_quartus/Video/lpm_latch1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_latch1 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_latch1.qip b/FPGA_quartus/Video/lpm_latch1.qip new file mode 100644 index 0000000..bc53d50 --- /dev/null +++ b/FPGA_quartus/Video/lpm_latch1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.cmp"] diff --git a/FPGA_quartus/Video/lpm_latch1.vhd b/FPGA_quartus/Video/lpm_latch1.vhd new file mode 100644 index 0000000..0afc209 --- /dev/null +++ b/FPGA_quartus/Video/lpm_latch1.vhd @@ -0,0 +1,110 @@ +-- megafunction wizard: %LPM_LATCH% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_latch + +-- ============================================================ +-- File Name: lpm_latch1.vhd +-- Megafunction Name(s): +-- lpm_latch +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_latch1 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_latch1; + + +ARCHITECTURE SYN OF lpm_latch1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_latch + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_latch_component : lpm_latch + GENERIC MAP ( + lpm_type => "LPM_LATCH", + lpm_width => 32 + ) + PORT MAP ( + data => data, + gate => gate, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: aset NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux0.bsf b/FPGA_quartus/Video/lpm_mux0.bsf new file mode 100644 index 0000000..ce1e27e --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux0.bsf @@ -0,0 +1,83 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 128) + (text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 1)) + ) + (port + (pt 80 128) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8))) + (line (pt 80 128)(pt 80 116)(line_width 3)) + ) + (port + (pt 152 72) + (output) + (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8))) + (line (pt 152 72)(pt 88 72)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 120)(line_width 1)) + (line (pt 88 32)(pt 88 112)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 120)(pt 88 112)(line_width 1)) + (line (pt 72 98)(pt 78 104)(line_width 1)) + (line (pt 78 104)(pt 72 110)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux0.cmp b/FPGA_quartus/Video/lpm_mux0.cmp new file mode 100644 index 0000000..7b6c18f --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux0.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux0 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux0.inc b/FPGA_quartus/Video/lpm_mux0.inc new file mode 100644 index 0000000..b0bc2be --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux0.inc @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux0 +( + clock, + data0x[31..0], + data1x[31..0], + data2x[31..0], + data3x[31..0], + sel[1..0] +) + +RETURNS ( + result[31..0] +); diff --git a/FPGA_quartus/Video/lpm_mux0.qip b/FPGA_quartus/Video/lpm_mux0.qip new file mode 100644 index 0000000..5e8e2b6 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux0.vhd b/FPGA_quartus/Video/lpm_mux0.vhd new file mode 100644 index 0000000..9d641a4 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux0.vhd @@ -0,0 +1,251 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux0.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux0 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_mux0; + + +ARCHITECTURE SYN OF lpm_mux0 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(31 DOWNTO 0); + sub_wire4 <= data1x(31 DOWNTO 0); + sub_wire3 <= data2x(31 DOWNTO 0); + result <= sub_wire0(31 DOWNTO 0); + sub_wire1 <= data3x(31 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 32, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0] +-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0] +-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0] +-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0] +-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux1.bsf b/FPGA_quartus/Video/lpm_mux1.bsf new file mode 100644 index 0000000..24ee953 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux1.bsf @@ -0,0 +1,111 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux1.cmp b/FPGA_quartus/Video/lpm_mux1.cmp new file mode 100644 index 0000000..cfc222a --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux1.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux1 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux1.inc b/FPGA_quartus/Video/lpm_mux1.inc new file mode 100644 index 0000000..e2f94a4 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux1.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux1 +( + clock, + data0x[15..0], + data1x[15..0], + data2x[15..0], + data3x[15..0], + data4x[15..0], + data5x[15..0], + data6x[15..0], + data7x[15..0], + sel[2..0] +) + +RETURNS ( + result[15..0] +); diff --git a/FPGA_quartus/Video/lpm_mux1.qip b/FPGA_quartus/Video/lpm_mux1.qip new file mode 100644 index 0000000..8a445b2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux1.vhd b/FPGA_quartus/Video/lpm_mux1.vhd new file mode 100644 index 0000000..a9ad991 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux1.vhd @@ -0,0 +1,271 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux1.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux1 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_mux1; + + +ARCHITECTURE SYN OF lpm_mux1 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(15 DOWNTO 0); + sub_wire8 <= data1x(15 DOWNTO 0); + sub_wire7 <= data2x(15 DOWNTO 0); + sub_wire6 <= data3x(15 DOWNTO 0); + sub_wire5 <= data4x(15 DOWNTO 0); + sub_wire4 <= data5x(15 DOWNTO 0); + sub_wire3 <= data6x(15 DOWNTO 0); + result <= sub_wire0(15 DOWNTO 0); + sub_wire1 <= data7x(15 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 16, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0] +-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0] +-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0] +-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0] +-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0] +-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0] +-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0] +-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0] +-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux2.bsf b/FPGA_quartus/Video/lpm_mux2.bsf new file mode 100644 index 0000000..b37c425 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux2.bsf @@ -0,0 +1,167 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 320) + (text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 304 25 316)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 72 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 72 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 72 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 72 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 72 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 72 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 72 280)(line_width 3)) + ) + (port + (pt 0 296) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 72 296)(line_width 1)) + ) + (port + (pt 80 320) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8))) + (line (pt 80 320)(pt 80 308)(line_width 3)) + ) + (port + (pt 144 168) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8))) + (line (pt 144 168)(pt 88 168)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 312)(line_width 1)) + (line (pt 88 32)(pt 88 304)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 312)(pt 88 304)(line_width 1)) + (line (pt 72 290)(pt 78 296)(line_width 1)) + (line (pt 78 296)(pt 72 302)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux2.cmp b/FPGA_quartus/Video/lpm_mux2.cmp new file mode 100644 index 0000000..d94260c --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux2.cmp @@ -0,0 +1,39 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux2 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux2.inc b/FPGA_quartus/Video/lpm_mux2.inc new file mode 100644 index 0000000..2334c7e --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux2.inc @@ -0,0 +1,40 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux2 +( + clock, + data0x[7..0], + data10x[7..0], + data11x[7..0], + data12x[7..0], + data13x[7..0], + data14x[7..0], + data15x[7..0], + data1x[7..0], + data2x[7..0], + data3x[7..0], + data4x[7..0], + data5x[7..0], + data6x[7..0], + data7x[7..0], + data8x[7..0], + data9x[7..0], + sel[3..0] +) + +RETURNS ( + result[7..0] +); diff --git a/FPGA_quartus/Video/lpm_mux2.qip b/FPGA_quartus/Video/lpm_mux2.qip new file mode 100644 index 0000000..7b5db74 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux2.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux2.vhd b/FPGA_quartus/Video/lpm_mux2.vhd new file mode 100644 index 0000000..cfece2e --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux2.vhd @@ -0,0 +1,311 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux2.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux2 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_mux2; + + +ARCHITECTURE SYN OF lpm_mux2 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(7 DOWNTO 0); + sub_wire16 <= data1x(7 DOWNTO 0); + sub_wire15 <= data2x(7 DOWNTO 0); + sub_wire14 <= data3x(7 DOWNTO 0); + sub_wire13 <= data4x(7 DOWNTO 0); + sub_wire12 <= data5x(7 DOWNTO 0); + sub_wire11 <= data6x(7 DOWNTO 0); + sub_wire10 <= data7x(7 DOWNTO 0); + sub_wire9 <= data8x(7 DOWNTO 0); + sub_wire8 <= data9x(7 DOWNTO 0); + sub_wire7 <= data10x(7 DOWNTO 0); + sub_wire6 <= data11x(7 DOWNTO 0); + sub_wire5 <= data12x(7 DOWNTO 0); + sub_wire4 <= data13x(7 DOWNTO 0); + sub_wire3 <= data14x(7 DOWNTO 0); + result <= sub_wire0(7 DOWNTO 0); + sub_wire1 <= data15x(7 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 8, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0] +-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0] +-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0] +-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0] +-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0] +-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0] +-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0] +-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0] +-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0] +-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0] +-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0] +-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0] +-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0] +-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0] +-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0] +-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0] +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux3.bsf b/FPGA_quartus/Video/lpm_mux3.bsf new file mode 100644 index 0000000..c389543 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux3.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 80) + (text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 32 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 32 56)(line_width 1)) + ) + (port + (pt 40 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8))) + (line (pt 40 80)(pt 40 68)(line_width 1)) + ) + (port + (pt 80 48) + (output) + (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "result" (rect 50 35 75 48)(font "Arial" (font_size 8))) + (line (pt 80 48)(pt 48 48)(line_width 1)) + ) + (drawing + (line (pt 32 24)(pt 32 72)(line_width 1)) + (line (pt 48 32)(pt 48 64)(line_width 1)) + (line (pt 32 24)(pt 48 32)(line_width 1)) + (line (pt 32 72)(pt 48 64)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux3.cmp b/FPGA_quartus/Video/lpm_mux3.cmp new file mode 100644 index 0000000..48f730d --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux3.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux3 + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux3.qip b/FPGA_quartus/Video/lpm_mux3.qip new file mode 100644 index 0000000..ca1e672 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux3.vhd b/FPGA_quartus/Video/lpm_mux3.vhd new file mode 100644 index 0000000..b975686 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux3.vhd @@ -0,0 +1,115 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux3.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux3 IS + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +END lpm_mux3; + + +ARCHITECTURE SYN OF lpm_mux3 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + +BEGIN + sub_wire6 <= data0; + sub_wire1 <= sub_wire0(0); + result <= sub_wire1; + sub_wire2 <= sel; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= data1; + sub_wire5(1, 0) <= sub_wire4; + sub_wire5(0, 0) <= sub_wire6; + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 1, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire3, + data => sub_wire5, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0 +-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1 +-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 +-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 +-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux4.bsf b/FPGA_quartus/Video/lpm_mux4.bsf new file mode 100644 index 0000000..a1c9ca0 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux4.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 136 80) + (text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 72 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8))) + (line (pt 72 80)(pt 72 68)(line_width 1)) + ) + (port + (pt 136 48) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8))) + (line (pt 136 48)(pt 80 48)(line_width 3)) + ) + (drawing + (line (pt 64 24)(pt 64 72)(line_width 1)) + (line (pt 80 32)(pt 80 64)(line_width 1)) + (line (pt 64 24)(pt 80 32)(line_width 1)) + (line (pt 64 72)(pt 80 64)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux4.cmp b/FPGA_quartus/Video/lpm_mux4.cmp new file mode 100644 index 0000000..05e7a07 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux4.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux4 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux4.qip b/FPGA_quartus/Video/lpm_mux4.qip new file mode 100644 index 0000000..7712e39 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux4.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux4.vhd b/FPGA_quartus/Video/lpm_mux4.vhd new file mode 100644 index 0000000..854a491 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux4.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux4.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux4 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_mux4; + + +ARCHITECTURE SYN OF lpm_mux4 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (6 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(6 DOWNTO 0); + result <= sub_wire0(6 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(6 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 7, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0] +-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0] +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux5.bsf b/FPGA_quartus/Video/lpm_mux5.bsf new file mode 100644 index 0000000..e63ce50 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux5.bsf @@ -0,0 +1,74 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 112) + (text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 80 112) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8))) + (line (pt 80 112)(pt 80 100)(line_width 3)) + ) + (port + (pt 152 64) + (output) + (text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8))) + (line (pt 152 64)(pt 88 64)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 104)(line_width 1)) + (line (pt 88 32)(pt 88 96)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 104)(pt 88 96)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux5.cmp b/FPGA_quartus/Video/lpm_mux5.cmp new file mode 100644 index 0000000..efc712a --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux5.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux5 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux5.inc b/FPGA_quartus/Video/lpm_mux5.inc new file mode 100644 index 0000000..a063f55 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux5.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux5 +( + data0x[63..0], + data1x[63..0], + data2x[63..0], + data3x[63..0], + sel[1..0] +) + +RETURNS ( + result[63..0] +); diff --git a/FPGA_quartus/Video/lpm_mux5.qip b/FPGA_quartus/Video/lpm_mux5.qip new file mode 100644 index 0000000..08b2e74 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux5.vhd b/FPGA_quartus/Video/lpm_mux5.vhd new file mode 100644 index 0000000..1d35347 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux5.vhd @@ -0,0 +1,373 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux5.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux5 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +END lpm_mux5; + + +ARCHITECTURE SYN OF lpm_mux5 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (63 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(63 DOWNTO 0); + sub_wire4 <= data1x(63 DOWNTO 0); + sub_wire3 <= data2x(63 DOWNTO 0); + result <= sub_wire0(63 DOWNTO 0); + sub_wire1 <= data3x(63 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(3, 32) <= sub_wire1(32); + sub_wire2(3, 33) <= sub_wire1(33); + sub_wire2(3, 34) <= sub_wire1(34); + sub_wire2(3, 35) <= sub_wire1(35); + sub_wire2(3, 36) <= sub_wire1(36); + sub_wire2(3, 37) <= sub_wire1(37); + sub_wire2(3, 38) <= sub_wire1(38); + sub_wire2(3, 39) <= sub_wire1(39); + sub_wire2(3, 40) <= sub_wire1(40); + sub_wire2(3, 41) <= sub_wire1(41); + sub_wire2(3, 42) <= sub_wire1(42); + sub_wire2(3, 43) <= sub_wire1(43); + sub_wire2(3, 44) <= sub_wire1(44); + sub_wire2(3, 45) <= sub_wire1(45); + sub_wire2(3, 46) <= sub_wire1(46); + sub_wire2(3, 47) <= sub_wire1(47); + sub_wire2(3, 48) <= sub_wire1(48); + sub_wire2(3, 49) <= sub_wire1(49); + sub_wire2(3, 50) <= sub_wire1(50); + sub_wire2(3, 51) <= sub_wire1(51); + sub_wire2(3, 52) <= sub_wire1(52); + sub_wire2(3, 53) <= sub_wire1(53); + sub_wire2(3, 54) <= sub_wire1(54); + sub_wire2(3, 55) <= sub_wire1(55); + sub_wire2(3, 56) <= sub_wire1(56); + sub_wire2(3, 57) <= sub_wire1(57); + sub_wire2(3, 58) <= sub_wire1(58); + sub_wire2(3, 59) <= sub_wire1(59); + sub_wire2(3, 60) <= sub_wire1(60); + sub_wire2(3, 61) <= sub_wire1(61); + sub_wire2(3, 62) <= sub_wire1(62); + sub_wire2(3, 63) <= sub_wire1(63); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(2, 32) <= sub_wire3(32); + sub_wire2(2, 33) <= sub_wire3(33); + sub_wire2(2, 34) <= sub_wire3(34); + sub_wire2(2, 35) <= sub_wire3(35); + sub_wire2(2, 36) <= sub_wire3(36); + sub_wire2(2, 37) <= sub_wire3(37); + sub_wire2(2, 38) <= sub_wire3(38); + sub_wire2(2, 39) <= sub_wire3(39); + sub_wire2(2, 40) <= sub_wire3(40); + sub_wire2(2, 41) <= sub_wire3(41); + sub_wire2(2, 42) <= sub_wire3(42); + sub_wire2(2, 43) <= sub_wire3(43); + sub_wire2(2, 44) <= sub_wire3(44); + sub_wire2(2, 45) <= sub_wire3(45); + sub_wire2(2, 46) <= sub_wire3(46); + sub_wire2(2, 47) <= sub_wire3(47); + sub_wire2(2, 48) <= sub_wire3(48); + sub_wire2(2, 49) <= sub_wire3(49); + sub_wire2(2, 50) <= sub_wire3(50); + sub_wire2(2, 51) <= sub_wire3(51); + sub_wire2(2, 52) <= sub_wire3(52); + sub_wire2(2, 53) <= sub_wire3(53); + sub_wire2(2, 54) <= sub_wire3(54); + sub_wire2(2, 55) <= sub_wire3(55); + sub_wire2(2, 56) <= sub_wire3(56); + sub_wire2(2, 57) <= sub_wire3(57); + sub_wire2(2, 58) <= sub_wire3(58); + sub_wire2(2, 59) <= sub_wire3(59); + sub_wire2(2, 60) <= sub_wire3(60); + sub_wire2(2, 61) <= sub_wire3(61); + sub_wire2(2, 62) <= sub_wire3(62); + sub_wire2(2, 63) <= sub_wire3(63); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(1, 32) <= sub_wire4(32); + sub_wire2(1, 33) <= sub_wire4(33); + sub_wire2(1, 34) <= sub_wire4(34); + sub_wire2(1, 35) <= sub_wire4(35); + sub_wire2(1, 36) <= sub_wire4(36); + sub_wire2(1, 37) <= sub_wire4(37); + sub_wire2(1, 38) <= sub_wire4(38); + sub_wire2(1, 39) <= sub_wire4(39); + sub_wire2(1, 40) <= sub_wire4(40); + sub_wire2(1, 41) <= sub_wire4(41); + sub_wire2(1, 42) <= sub_wire4(42); + sub_wire2(1, 43) <= sub_wire4(43); + sub_wire2(1, 44) <= sub_wire4(44); + sub_wire2(1, 45) <= sub_wire4(45); + sub_wire2(1, 46) <= sub_wire4(46); + sub_wire2(1, 47) <= sub_wire4(47); + sub_wire2(1, 48) <= sub_wire4(48); + sub_wire2(1, 49) <= sub_wire4(49); + sub_wire2(1, 50) <= sub_wire4(50); + sub_wire2(1, 51) <= sub_wire4(51); + sub_wire2(1, 52) <= sub_wire4(52); + sub_wire2(1, 53) <= sub_wire4(53); + sub_wire2(1, 54) <= sub_wire4(54); + sub_wire2(1, 55) <= sub_wire4(55); + sub_wire2(1, 56) <= sub_wire4(56); + sub_wire2(1, 57) <= sub_wire4(57); + sub_wire2(1, 58) <= sub_wire4(58); + sub_wire2(1, 59) <= sub_wire4(59); + sub_wire2(1, 60) <= sub_wire4(60); + sub_wire2(1, 61) <= sub_wire4(61); + sub_wire2(1, 62) <= sub_wire4(62); + sub_wire2(1, 63) <= sub_wire4(63); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + sub_wire2(0, 32) <= sub_wire5(32); + sub_wire2(0, 33) <= sub_wire5(33); + sub_wire2(0, 34) <= sub_wire5(34); + sub_wire2(0, 35) <= sub_wire5(35); + sub_wire2(0, 36) <= sub_wire5(36); + sub_wire2(0, 37) <= sub_wire5(37); + sub_wire2(0, 38) <= sub_wire5(38); + sub_wire2(0, 39) <= sub_wire5(39); + sub_wire2(0, 40) <= sub_wire5(40); + sub_wire2(0, 41) <= sub_wire5(41); + sub_wire2(0, 42) <= sub_wire5(42); + sub_wire2(0, 43) <= sub_wire5(43); + sub_wire2(0, 44) <= sub_wire5(44); + sub_wire2(0, 45) <= sub_wire5(45); + sub_wire2(0, 46) <= sub_wire5(46); + sub_wire2(0, 47) <= sub_wire5(47); + sub_wire2(0, 48) <= sub_wire5(48); + sub_wire2(0, 49) <= sub_wire5(49); + sub_wire2(0, 50) <= sub_wire5(50); + sub_wire2(0, 51) <= sub_wire5(51); + sub_wire2(0, 52) <= sub_wire5(52); + sub_wire2(0, 53) <= sub_wire5(53); + sub_wire2(0, 54) <= sub_wire5(54); + sub_wire2(0, 55) <= sub_wire5(55); + sub_wire2(0, 56) <= sub_wire5(56); + sub_wire2(0, 57) <= sub_wire5(57); + sub_wire2(0, 58) <= sub_wire5(58); + sub_wire2(0, 59) <= sub_wire5(59); + sub_wire2(0, 60) <= sub_wire5(60); + sub_wire2(0, 61) <= sub_wire5(61); + sub_wire2(0, 62) <= sub_wire5(62); + sub_wire2(0, 63) <= sub_wire5(63); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 64, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0] +-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0] +-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0] +-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0] +-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_mux6.bsf b/FPGA_quartus/Video/lpm_mux6.bsf new file mode 100644 index 0000000..2196842 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux6.bsf @@ -0,0 +1,111 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_mux6.cmp b/FPGA_quartus/Video/lpm_mux6.cmp new file mode 100644 index 0000000..543da1f --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux6.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux6 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_mux6.inc b/FPGA_quartus/Video/lpm_mux6.inc new file mode 100644 index 0000000..3cf223d --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux6.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux6 +( + clock, + data0x[23..0], + data1x[23..0], + data2x[23..0], + data3x[23..0], + data4x[23..0], + data5x[23..0], + data6x[23..0], + data7x[23..0], + sel[2..0] +) + +RETURNS ( + result[23..0] +); diff --git a/FPGA_quartus/Video/lpm_mux6.qip b/FPGA_quartus/Video/lpm_mux6.qip new file mode 100644 index 0000000..051a945 --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"] diff --git a/FPGA_quartus/Video/lpm_mux6.vhd b/FPGA_quartus/Video/lpm_mux6.vhd new file mode 100644 index 0000000..42d5aae --- /dev/null +++ b/FPGA_quartus/Video/lpm_mux6.vhd @@ -0,0 +1,335 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux6.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux6 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_mux6; + + +ARCHITECTURE SYN OF lpm_mux6 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (23 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(23 DOWNTO 0); + sub_wire8 <= data1x(23 DOWNTO 0); + sub_wire7 <= data2x(23 DOWNTO 0); + sub_wire6 <= data3x(23 DOWNTO 0); + sub_wire5 <= data4x(23 DOWNTO 0); + sub_wire4 <= data5x(23 DOWNTO 0); + sub_wire3 <= data6x(23 DOWNTO 0); + result <= sub_wire0(23 DOWNTO 0); + sub_wire1 <= data7x(23 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(7, 16) <= sub_wire1(16); + sub_wire2(7, 17) <= sub_wire1(17); + sub_wire2(7, 18) <= sub_wire1(18); + sub_wire2(7, 19) <= sub_wire1(19); + sub_wire2(7, 20) <= sub_wire1(20); + sub_wire2(7, 21) <= sub_wire1(21); + sub_wire2(7, 22) <= sub_wire1(22); + sub_wire2(7, 23) <= sub_wire1(23); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(6, 16) <= sub_wire3(16); + sub_wire2(6, 17) <= sub_wire3(17); + sub_wire2(6, 18) <= sub_wire3(18); + sub_wire2(6, 19) <= sub_wire3(19); + sub_wire2(6, 20) <= sub_wire3(20); + sub_wire2(6, 21) <= sub_wire3(21); + sub_wire2(6, 22) <= sub_wire3(22); + sub_wire2(6, 23) <= sub_wire3(23); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(5, 16) <= sub_wire4(16); + sub_wire2(5, 17) <= sub_wire4(17); + sub_wire2(5, 18) <= sub_wire4(18); + sub_wire2(5, 19) <= sub_wire4(19); + sub_wire2(5, 20) <= sub_wire4(20); + sub_wire2(5, 21) <= sub_wire4(21); + sub_wire2(5, 22) <= sub_wire4(22); + sub_wire2(5, 23) <= sub_wire4(23); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(4, 16) <= sub_wire5(16); + sub_wire2(4, 17) <= sub_wire5(17); + sub_wire2(4, 18) <= sub_wire5(18); + sub_wire2(4, 19) <= sub_wire5(19); + sub_wire2(4, 20) <= sub_wire5(20); + sub_wire2(4, 21) <= sub_wire5(21); + sub_wire2(4, 22) <= sub_wire5(22); + sub_wire2(4, 23) <= sub_wire5(23); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(3, 16) <= sub_wire6(16); + sub_wire2(3, 17) <= sub_wire6(17); + sub_wire2(3, 18) <= sub_wire6(18); + sub_wire2(3, 19) <= sub_wire6(19); + sub_wire2(3, 20) <= sub_wire6(20); + sub_wire2(3, 21) <= sub_wire6(21); + sub_wire2(3, 22) <= sub_wire6(22); + sub_wire2(3, 23) <= sub_wire6(23); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(2, 16) <= sub_wire7(16); + sub_wire2(2, 17) <= sub_wire7(17); + sub_wire2(2, 18) <= sub_wire7(18); + sub_wire2(2, 19) <= sub_wire7(19); + sub_wire2(2, 20) <= sub_wire7(20); + sub_wire2(2, 21) <= sub_wire7(21); + sub_wire2(2, 22) <= sub_wire7(22); + sub_wire2(2, 23) <= sub_wire7(23); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(1, 16) <= sub_wire8(16); + sub_wire2(1, 17) <= sub_wire8(17); + sub_wire2(1, 18) <= sub_wire8(18); + sub_wire2(1, 19) <= sub_wire8(19); + sub_wire2(1, 20) <= sub_wire8(20); + sub_wire2(1, 21) <= sub_wire8(21); + sub_wire2(1, 22) <= sub_wire8(22); + sub_wire2(1, 23) <= sub_wire8(23); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + sub_wire2(0, 16) <= sub_wire9(16); + sub_wire2(0, 17) <= sub_wire9(17); + sub_wire2(0, 18) <= sub_wire9(18); + sub_wire2(0, 19) <= sub_wire9(19); + sub_wire2(0, 20) <= sub_wire9(20); + sub_wire2(0, 21) <= sub_wire9(21); + sub_wire2(0, 22) <= sub_wire9(22); + sub_wire2(0, 23) <= sub_wire9(23); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 24, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0] +-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0] +-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0] +-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0] +-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0] +-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0] +-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0] +-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0] +-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_muxDZ.bsf b/FPGA_quartus/Video/lpm_muxDZ.bsf new file mode 100644 index 0000000..f4f1c7d --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ.bsf @@ -0,0 +1,76 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 112) + (text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 1)) + ) + (port + (pt 0 88) + (input) + (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 1)) + ) + (port + (pt 88 112) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8))) + (line (pt 88 112)(pt 88 100)(line_width 1)) + ) + (port + (pt 168 64) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8))) + (line (pt 168 64)(pt 96 64)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 104)(line_width 1)) + (line (pt 96 32)(pt 96 96)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 104)(pt 96 96)(line_width 1)) + (line (pt 80 66)(pt 86 72)(line_width 1)) + (line (pt 86 72)(pt 80 78)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_muxDZ.cmp b/FPGA_quartus/Video/lpm_muxDZ.cmp new file mode 100644 index 0000000..f177216 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxDZ + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_muxDZ.qip b/FPGA_quartus/Video/lpm_muxDZ.qip new file mode 100644 index 0000000..34ffc75 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"] diff --git a/FPGA_quartus/Video/lpm_muxDZ.vhd b/FPGA_quartus/Video/lpm_muxDZ.vhd new file mode 100644 index 0000000..e9bd32e --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ.vhd @@ -0,0 +1,377 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxDZ.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxDZ IS + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxDZ; + + +ARCHITECTURE SYN OF lpm_muxdz IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(127 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(1, 7) <= sub_wire3(7); + sub_wire4(1, 8) <= sub_wire3(8); + sub_wire4(1, 9) <= sub_wire3(9); + sub_wire4(1, 10) <= sub_wire3(10); + sub_wire4(1, 11) <= sub_wire3(11); + sub_wire4(1, 12) <= sub_wire3(12); + sub_wire4(1, 13) <= sub_wire3(13); + sub_wire4(1, 14) <= sub_wire3(14); + sub_wire4(1, 15) <= sub_wire3(15); + sub_wire4(1, 16) <= sub_wire3(16); + sub_wire4(1, 17) <= sub_wire3(17); + sub_wire4(1, 18) <= sub_wire3(18); + sub_wire4(1, 19) <= sub_wire3(19); + sub_wire4(1, 20) <= sub_wire3(20); + sub_wire4(1, 21) <= sub_wire3(21); + sub_wire4(1, 22) <= sub_wire3(22); + sub_wire4(1, 23) <= sub_wire3(23); + sub_wire4(1, 24) <= sub_wire3(24); + sub_wire4(1, 25) <= sub_wire3(25); + sub_wire4(1, 26) <= sub_wire3(26); + sub_wire4(1, 27) <= sub_wire3(27); + sub_wire4(1, 28) <= sub_wire3(28); + sub_wire4(1, 29) <= sub_wire3(29); + sub_wire4(1, 30) <= sub_wire3(30); + sub_wire4(1, 31) <= sub_wire3(31); + sub_wire4(1, 32) <= sub_wire3(32); + sub_wire4(1, 33) <= sub_wire3(33); + sub_wire4(1, 34) <= sub_wire3(34); + sub_wire4(1, 35) <= sub_wire3(35); + sub_wire4(1, 36) <= sub_wire3(36); + sub_wire4(1, 37) <= sub_wire3(37); + sub_wire4(1, 38) <= sub_wire3(38); + sub_wire4(1, 39) <= sub_wire3(39); + sub_wire4(1, 40) <= sub_wire3(40); + sub_wire4(1, 41) <= sub_wire3(41); + sub_wire4(1, 42) <= sub_wire3(42); + sub_wire4(1, 43) <= sub_wire3(43); + sub_wire4(1, 44) <= sub_wire3(44); + sub_wire4(1, 45) <= sub_wire3(45); + sub_wire4(1, 46) <= sub_wire3(46); + sub_wire4(1, 47) <= sub_wire3(47); + sub_wire4(1, 48) <= sub_wire3(48); + sub_wire4(1, 49) <= sub_wire3(49); + sub_wire4(1, 50) <= sub_wire3(50); + sub_wire4(1, 51) <= sub_wire3(51); + sub_wire4(1, 52) <= sub_wire3(52); + sub_wire4(1, 53) <= sub_wire3(53); + sub_wire4(1, 54) <= sub_wire3(54); + sub_wire4(1, 55) <= sub_wire3(55); + sub_wire4(1, 56) <= sub_wire3(56); + sub_wire4(1, 57) <= sub_wire3(57); + sub_wire4(1, 58) <= sub_wire3(58); + sub_wire4(1, 59) <= sub_wire3(59); + sub_wire4(1, 60) <= sub_wire3(60); + sub_wire4(1, 61) <= sub_wire3(61); + sub_wire4(1, 62) <= sub_wire3(62); + sub_wire4(1, 63) <= sub_wire3(63); + sub_wire4(1, 64) <= sub_wire3(64); + sub_wire4(1, 65) <= sub_wire3(65); + sub_wire4(1, 66) <= sub_wire3(66); + sub_wire4(1, 67) <= sub_wire3(67); + sub_wire4(1, 68) <= sub_wire3(68); + sub_wire4(1, 69) <= sub_wire3(69); + sub_wire4(1, 70) <= sub_wire3(70); + sub_wire4(1, 71) <= sub_wire3(71); + sub_wire4(1, 72) <= sub_wire3(72); + sub_wire4(1, 73) <= sub_wire3(73); + sub_wire4(1, 74) <= sub_wire3(74); + sub_wire4(1, 75) <= sub_wire3(75); + sub_wire4(1, 76) <= sub_wire3(76); + sub_wire4(1, 77) <= sub_wire3(77); + sub_wire4(1, 78) <= sub_wire3(78); + sub_wire4(1, 79) <= sub_wire3(79); + sub_wire4(1, 80) <= sub_wire3(80); + sub_wire4(1, 81) <= sub_wire3(81); + sub_wire4(1, 82) <= sub_wire3(82); + sub_wire4(1, 83) <= sub_wire3(83); + sub_wire4(1, 84) <= sub_wire3(84); + sub_wire4(1, 85) <= sub_wire3(85); + sub_wire4(1, 86) <= sub_wire3(86); + sub_wire4(1, 87) <= sub_wire3(87); + sub_wire4(1, 88) <= sub_wire3(88); + sub_wire4(1, 89) <= sub_wire3(89); + sub_wire4(1, 90) <= sub_wire3(90); + sub_wire4(1, 91) <= sub_wire3(91); + sub_wire4(1, 92) <= sub_wire3(92); + sub_wire4(1, 93) <= sub_wire3(93); + sub_wire4(1, 94) <= sub_wire3(94); + sub_wire4(1, 95) <= sub_wire3(95); + sub_wire4(1, 96) <= sub_wire3(96); + sub_wire4(1, 97) <= sub_wire3(97); + sub_wire4(1, 98) <= sub_wire3(98); + sub_wire4(1, 99) <= sub_wire3(99); + sub_wire4(1, 100) <= sub_wire3(100); + sub_wire4(1, 101) <= sub_wire3(101); + sub_wire4(1, 102) <= sub_wire3(102); + sub_wire4(1, 103) <= sub_wire3(103); + sub_wire4(1, 104) <= sub_wire3(104); + sub_wire4(1, 105) <= sub_wire3(105); + sub_wire4(1, 106) <= sub_wire3(106); + sub_wire4(1, 107) <= sub_wire3(107); + sub_wire4(1, 108) <= sub_wire3(108); + sub_wire4(1, 109) <= sub_wire3(109); + sub_wire4(1, 110) <= sub_wire3(110); + sub_wire4(1, 111) <= sub_wire3(111); + sub_wire4(1, 112) <= sub_wire3(112); + sub_wire4(1, 113) <= sub_wire3(113); + sub_wire4(1, 114) <= sub_wire3(114); + sub_wire4(1, 115) <= sub_wire3(115); + sub_wire4(1, 116) <= sub_wire3(116); + sub_wire4(1, 117) <= sub_wire3(117); + sub_wire4(1, 118) <= sub_wire3(118); + sub_wire4(1, 119) <= sub_wire3(119); + sub_wire4(1, 120) <= sub_wire3(120); + sub_wire4(1, 121) <= sub_wire3(121); + sub_wire4(1, 122) <= sub_wire3(122); + sub_wire4(1, 123) <= sub_wire3(123); + sub_wire4(1, 124) <= sub_wire3(124); + sub_wire4(1, 125) <= sub_wire3(125); + sub_wire4(1, 126) <= sub_wire3(126); + sub_wire4(1, 127) <= sub_wire3(127); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + sub_wire4(0, 7) <= sub_wire5(7); + sub_wire4(0, 8) <= sub_wire5(8); + sub_wire4(0, 9) <= sub_wire5(9); + sub_wire4(0, 10) <= sub_wire5(10); + sub_wire4(0, 11) <= sub_wire5(11); + sub_wire4(0, 12) <= sub_wire5(12); + sub_wire4(0, 13) <= sub_wire5(13); + sub_wire4(0, 14) <= sub_wire5(14); + sub_wire4(0, 15) <= sub_wire5(15); + sub_wire4(0, 16) <= sub_wire5(16); + sub_wire4(0, 17) <= sub_wire5(17); + sub_wire4(0, 18) <= sub_wire5(18); + sub_wire4(0, 19) <= sub_wire5(19); + sub_wire4(0, 20) <= sub_wire5(20); + sub_wire4(0, 21) <= sub_wire5(21); + sub_wire4(0, 22) <= sub_wire5(22); + sub_wire4(0, 23) <= sub_wire5(23); + sub_wire4(0, 24) <= sub_wire5(24); + sub_wire4(0, 25) <= sub_wire5(25); + sub_wire4(0, 26) <= sub_wire5(26); + sub_wire4(0, 27) <= sub_wire5(27); + sub_wire4(0, 28) <= sub_wire5(28); + sub_wire4(0, 29) <= sub_wire5(29); + sub_wire4(0, 30) <= sub_wire5(30); + sub_wire4(0, 31) <= sub_wire5(31); + sub_wire4(0, 32) <= sub_wire5(32); + sub_wire4(0, 33) <= sub_wire5(33); + sub_wire4(0, 34) <= sub_wire5(34); + sub_wire4(0, 35) <= sub_wire5(35); + sub_wire4(0, 36) <= sub_wire5(36); + sub_wire4(0, 37) <= sub_wire5(37); + sub_wire4(0, 38) <= sub_wire5(38); + sub_wire4(0, 39) <= sub_wire5(39); + sub_wire4(0, 40) <= sub_wire5(40); + sub_wire4(0, 41) <= sub_wire5(41); + sub_wire4(0, 42) <= sub_wire5(42); + sub_wire4(0, 43) <= sub_wire5(43); + sub_wire4(0, 44) <= sub_wire5(44); + sub_wire4(0, 45) <= sub_wire5(45); + sub_wire4(0, 46) <= sub_wire5(46); + sub_wire4(0, 47) <= sub_wire5(47); + sub_wire4(0, 48) <= sub_wire5(48); + sub_wire4(0, 49) <= sub_wire5(49); + sub_wire4(0, 50) <= sub_wire5(50); + sub_wire4(0, 51) <= sub_wire5(51); + sub_wire4(0, 52) <= sub_wire5(52); + sub_wire4(0, 53) <= sub_wire5(53); + sub_wire4(0, 54) <= sub_wire5(54); + sub_wire4(0, 55) <= sub_wire5(55); + sub_wire4(0, 56) <= sub_wire5(56); + sub_wire4(0, 57) <= sub_wire5(57); + sub_wire4(0, 58) <= sub_wire5(58); + sub_wire4(0, 59) <= sub_wire5(59); + sub_wire4(0, 60) <= sub_wire5(60); + sub_wire4(0, 61) <= sub_wire5(61); + sub_wire4(0, 62) <= sub_wire5(62); + sub_wire4(0, 63) <= sub_wire5(63); + sub_wire4(0, 64) <= sub_wire5(64); + sub_wire4(0, 65) <= sub_wire5(65); + sub_wire4(0, 66) <= sub_wire5(66); + sub_wire4(0, 67) <= sub_wire5(67); + sub_wire4(0, 68) <= sub_wire5(68); + sub_wire4(0, 69) <= sub_wire5(69); + sub_wire4(0, 70) <= sub_wire5(70); + sub_wire4(0, 71) <= sub_wire5(71); + sub_wire4(0, 72) <= sub_wire5(72); + sub_wire4(0, 73) <= sub_wire5(73); + sub_wire4(0, 74) <= sub_wire5(74); + sub_wire4(0, 75) <= sub_wire5(75); + sub_wire4(0, 76) <= sub_wire5(76); + sub_wire4(0, 77) <= sub_wire5(77); + sub_wire4(0, 78) <= sub_wire5(78); + sub_wire4(0, 79) <= sub_wire5(79); + sub_wire4(0, 80) <= sub_wire5(80); + sub_wire4(0, 81) <= sub_wire5(81); + sub_wire4(0, 82) <= sub_wire5(82); + sub_wire4(0, 83) <= sub_wire5(83); + sub_wire4(0, 84) <= sub_wire5(84); + sub_wire4(0, 85) <= sub_wire5(85); + sub_wire4(0, 86) <= sub_wire5(86); + sub_wire4(0, 87) <= sub_wire5(87); + sub_wire4(0, 88) <= sub_wire5(88); + sub_wire4(0, 89) <= sub_wire5(89); + sub_wire4(0, 90) <= sub_wire5(90); + sub_wire4(0, 91) <= sub_wire5(91); + sub_wire4(0, 92) <= sub_wire5(92); + sub_wire4(0, 93) <= sub_wire5(93); + sub_wire4(0, 94) <= sub_wire5(94); + sub_wire4(0, 95) <= sub_wire5(95); + sub_wire4(0, 96) <= sub_wire5(96); + sub_wire4(0, 97) <= sub_wire5(97); + sub_wire4(0, 98) <= sub_wire5(98); + sub_wire4(0, 99) <= sub_wire5(99); + sub_wire4(0, 100) <= sub_wire5(100); + sub_wire4(0, 101) <= sub_wire5(101); + sub_wire4(0, 102) <= sub_wire5(102); + sub_wire4(0, 103) <= sub_wire5(103); + sub_wire4(0, 104) <= sub_wire5(104); + sub_wire4(0, 105) <= sub_wire5(105); + sub_wire4(0, 106) <= sub_wire5(106); + sub_wire4(0, 107) <= sub_wire5(107); + sub_wire4(0, 108) <= sub_wire5(108); + sub_wire4(0, 109) <= sub_wire5(109); + sub_wire4(0, 110) <= sub_wire5(110); + sub_wire4(0, 111) <= sub_wire5(111); + sub_wire4(0, 112) <= sub_wire5(112); + sub_wire4(0, 113) <= sub_wire5(113); + sub_wire4(0, 114) <= sub_wire5(114); + sub_wire4(0, 115) <= sub_wire5(115); + sub_wire4(0, 116) <= sub_wire5(116); + sub_wire4(0, 117) <= sub_wire5(117); + sub_wire4(0, 118) <= sub_wire5(118); + sub_wire4(0, 119) <= sub_wire5(119); + sub_wire4(0, 120) <= sub_wire5(120); + sub_wire4(0, 121) <= sub_wire5(121); + sub_wire4(0, 122) <= sub_wire5(122); + sub_wire4(0, 123) <= sub_wire5(123); + sub_wire4(0, 124) <= sub_wire5(124); + sub_wire4(0, 125) <= sub_wire5(125); + sub_wire4(0, 126) <= sub_wire5(126); + sub_wire4(0, 127) <= sub_wire5(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 1, + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + clken => clken, + clock => clock, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_muxDZ2.bsf b/FPGA_quartus/Video/lpm_muxDZ2.bsf new file mode 100644 index 0000000..b7e3184 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ2.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 80) + (text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 40 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 40 56)(line_width 1)) + ) + (port + (pt 48 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8))) + (line (pt 48 80)(pt 48 68)(line_width 1)) + ) + (port + (pt 96 48) + (output) + (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "result" (rect 66 35 91 48)(font "Arial" (font_size 8))) + (line (pt 96 48)(pt 56 48)(line_width 1)) + ) + (drawing + (line (pt 40 24)(pt 40 72)(line_width 1)) + (line (pt 56 32)(pt 56 64)(line_width 1)) + (line (pt 40 24)(pt 56 32)(line_width 1)) + (line (pt 40 72)(pt 56 64)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_muxDZ2.cmp b/FPGA_quartus/Video/lpm_muxDZ2.cmp new file mode 100644 index 0000000..725acf4 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ2.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxDZ2 + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_muxDZ2.qip b/FPGA_quartus/Video/lpm_muxDZ2.qip new file mode 100644 index 0000000..8203bc6 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.cmp"] diff --git a/FPGA_quartus/Video/lpm_muxDZ2.vhd b/FPGA_quartus/Video/lpm_muxDZ2.vhd new file mode 100644 index 0000000..42e0c81 --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxDZ2.vhd @@ -0,0 +1,115 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxDZ2.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxDZ2 IS + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +END lpm_muxDZ2; + + +ARCHITECTURE SYN OF lpm_muxdz2 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + +BEGIN + sub_wire6 <= data0; + sub_wire1 <= sub_wire0(0); + result <= sub_wire1; + sub_wire2 <= sel; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= data1; + sub_wire5(1, 0) <= sub_wire4; + sub_wire5(0, 0) <= sub_wire6; + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 1, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire3, + data => sub_wire5, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0 +-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1 +-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 +-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 +-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_muxVDM.bsf b/FPGA_quartus/Video/lpm_muxVDM.bsf new file mode 100644 index 0000000..42d235c --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxVDM.bsf @@ -0,0 +1,158 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 304) + (text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 25 300)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 80 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 80 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 80 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 80 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 80 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 80 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 80 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 80 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 80 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 80 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 80 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 80 280)(line_width 3)) + ) + (port + (pt 88 304) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8))) + (line (pt 88 304)(pt 88 292)(line_width 3)) + ) + (port + (pt 168 160) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8))) + (line (pt 168 160)(pt 96 160)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 296)(line_width 1)) + (line (pt 96 32)(pt 96 288)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 296)(pt 96 288)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_muxVDM.cmp b/FPGA_quartus/Video/lpm_muxVDM.cmp new file mode 100644 index 0000000..867776d --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxVDM.cmp @@ -0,0 +1,38 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxVDM + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_muxVDM.qip b/FPGA_quartus/Video/lpm_muxVDM.qip new file mode 100644 index 0000000..08a824e --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxVDM.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"] diff --git a/FPGA_quartus/Video/lpm_muxVDM.vhd b/FPGA_quartus/Video/lpm_muxVDM.vhd new file mode 100644 index 0000000..662c8be --- /dev/null +++ b/FPGA_quartus/Video/lpm_muxVDM.vhd @@ -0,0 +1,2225 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxVDM.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxVDM IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxVDM; + + +ARCHITECTURE SYN OF lpm_muxvdm IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(127 DOWNTO 0); + sub_wire16 <= data1x(127 DOWNTO 0); + sub_wire15 <= data2x(127 DOWNTO 0); + sub_wire14 <= data3x(127 DOWNTO 0); + sub_wire13 <= data4x(127 DOWNTO 0); + sub_wire12 <= data5x(127 DOWNTO 0); + sub_wire11 <= data6x(127 DOWNTO 0); + sub_wire10 <= data7x(127 DOWNTO 0); + sub_wire9 <= data8x(127 DOWNTO 0); + sub_wire8 <= data9x(127 DOWNTO 0); + sub_wire7 <= data10x(127 DOWNTO 0); + sub_wire6 <= data11x(127 DOWNTO 0); + sub_wire5 <= data12x(127 DOWNTO 0); + sub_wire4 <= data13x(127 DOWNTO 0); + sub_wire3 <= data14x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= data15x(127 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(15, 8) <= sub_wire1(8); + sub_wire2(15, 9) <= sub_wire1(9); + sub_wire2(15, 10) <= sub_wire1(10); + sub_wire2(15, 11) <= sub_wire1(11); + sub_wire2(15, 12) <= sub_wire1(12); + sub_wire2(15, 13) <= sub_wire1(13); + sub_wire2(15, 14) <= sub_wire1(14); + sub_wire2(15, 15) <= sub_wire1(15); + sub_wire2(15, 16) <= sub_wire1(16); + sub_wire2(15, 17) <= sub_wire1(17); + sub_wire2(15, 18) <= sub_wire1(18); + sub_wire2(15, 19) <= sub_wire1(19); + sub_wire2(15, 20) <= sub_wire1(20); + sub_wire2(15, 21) <= sub_wire1(21); + sub_wire2(15, 22) <= sub_wire1(22); + sub_wire2(15, 23) <= sub_wire1(23); + sub_wire2(15, 24) <= sub_wire1(24); + sub_wire2(15, 25) <= sub_wire1(25); + sub_wire2(15, 26) <= sub_wire1(26); + sub_wire2(15, 27) <= sub_wire1(27); + sub_wire2(15, 28) <= sub_wire1(28); + sub_wire2(15, 29) <= sub_wire1(29); + sub_wire2(15, 30) <= sub_wire1(30); + sub_wire2(15, 31) <= sub_wire1(31); + sub_wire2(15, 32) <= sub_wire1(32); + sub_wire2(15, 33) <= sub_wire1(33); + sub_wire2(15, 34) <= sub_wire1(34); + sub_wire2(15, 35) <= sub_wire1(35); + sub_wire2(15, 36) <= sub_wire1(36); + sub_wire2(15, 37) <= sub_wire1(37); + sub_wire2(15, 38) <= sub_wire1(38); + sub_wire2(15, 39) <= sub_wire1(39); + sub_wire2(15, 40) <= sub_wire1(40); + sub_wire2(15, 41) <= sub_wire1(41); + sub_wire2(15, 42) <= sub_wire1(42); + sub_wire2(15, 43) <= sub_wire1(43); + sub_wire2(15, 44) <= sub_wire1(44); + sub_wire2(15, 45) <= sub_wire1(45); + sub_wire2(15, 46) <= sub_wire1(46); + sub_wire2(15, 47) <= sub_wire1(47); + sub_wire2(15, 48) <= sub_wire1(48); + sub_wire2(15, 49) <= sub_wire1(49); + sub_wire2(15, 50) <= sub_wire1(50); + sub_wire2(15, 51) <= sub_wire1(51); + sub_wire2(15, 52) <= sub_wire1(52); + sub_wire2(15, 53) <= sub_wire1(53); + sub_wire2(15, 54) <= sub_wire1(54); + sub_wire2(15, 55) <= sub_wire1(55); + sub_wire2(15, 56) <= sub_wire1(56); + sub_wire2(15, 57) <= sub_wire1(57); + sub_wire2(15, 58) <= sub_wire1(58); + sub_wire2(15, 59) <= sub_wire1(59); + sub_wire2(15, 60) <= sub_wire1(60); + sub_wire2(15, 61) <= sub_wire1(61); + sub_wire2(15, 62) <= sub_wire1(62); + sub_wire2(15, 63) <= sub_wire1(63); + sub_wire2(15, 64) <= sub_wire1(64); + sub_wire2(15, 65) <= sub_wire1(65); + sub_wire2(15, 66) <= sub_wire1(66); + sub_wire2(15, 67) <= sub_wire1(67); + sub_wire2(15, 68) <= sub_wire1(68); + sub_wire2(15, 69) <= sub_wire1(69); + sub_wire2(15, 70) <= sub_wire1(70); + sub_wire2(15, 71) <= sub_wire1(71); + sub_wire2(15, 72) <= sub_wire1(72); + sub_wire2(15, 73) <= sub_wire1(73); + sub_wire2(15, 74) <= sub_wire1(74); + sub_wire2(15, 75) <= sub_wire1(75); + sub_wire2(15, 76) <= sub_wire1(76); + sub_wire2(15, 77) <= sub_wire1(77); + sub_wire2(15, 78) <= sub_wire1(78); + sub_wire2(15, 79) <= sub_wire1(79); + sub_wire2(15, 80) <= sub_wire1(80); + sub_wire2(15, 81) <= sub_wire1(81); + sub_wire2(15, 82) <= sub_wire1(82); + sub_wire2(15, 83) <= sub_wire1(83); + sub_wire2(15, 84) <= sub_wire1(84); + sub_wire2(15, 85) <= sub_wire1(85); + sub_wire2(15, 86) <= sub_wire1(86); + sub_wire2(15, 87) <= sub_wire1(87); + sub_wire2(15, 88) <= sub_wire1(88); + sub_wire2(15, 89) <= sub_wire1(89); + sub_wire2(15, 90) <= sub_wire1(90); + sub_wire2(15, 91) <= sub_wire1(91); + sub_wire2(15, 92) <= sub_wire1(92); + sub_wire2(15, 93) <= sub_wire1(93); + sub_wire2(15, 94) <= sub_wire1(94); + sub_wire2(15, 95) <= sub_wire1(95); + sub_wire2(15, 96) <= sub_wire1(96); + sub_wire2(15, 97) <= sub_wire1(97); + sub_wire2(15, 98) <= sub_wire1(98); + sub_wire2(15, 99) <= sub_wire1(99); + sub_wire2(15, 100) <= sub_wire1(100); + sub_wire2(15, 101) <= sub_wire1(101); + sub_wire2(15, 102) <= sub_wire1(102); + sub_wire2(15, 103) <= sub_wire1(103); + sub_wire2(15, 104) <= sub_wire1(104); + sub_wire2(15, 105) <= sub_wire1(105); + sub_wire2(15, 106) <= sub_wire1(106); + sub_wire2(15, 107) <= sub_wire1(107); + sub_wire2(15, 108) <= sub_wire1(108); + sub_wire2(15, 109) <= sub_wire1(109); + sub_wire2(15, 110) <= sub_wire1(110); + sub_wire2(15, 111) <= sub_wire1(111); + sub_wire2(15, 112) <= sub_wire1(112); + sub_wire2(15, 113) <= sub_wire1(113); + sub_wire2(15, 114) <= sub_wire1(114); + sub_wire2(15, 115) <= sub_wire1(115); + sub_wire2(15, 116) <= sub_wire1(116); + sub_wire2(15, 117) <= sub_wire1(117); + sub_wire2(15, 118) <= sub_wire1(118); + sub_wire2(15, 119) <= sub_wire1(119); + sub_wire2(15, 120) <= sub_wire1(120); + sub_wire2(15, 121) <= sub_wire1(121); + sub_wire2(15, 122) <= sub_wire1(122); + sub_wire2(15, 123) <= sub_wire1(123); + sub_wire2(15, 124) <= sub_wire1(124); + sub_wire2(15, 125) <= sub_wire1(125); + sub_wire2(15, 126) <= sub_wire1(126); + sub_wire2(15, 127) <= sub_wire1(127); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(14, 8) <= sub_wire3(8); + sub_wire2(14, 9) <= sub_wire3(9); + sub_wire2(14, 10) <= sub_wire3(10); + sub_wire2(14, 11) <= sub_wire3(11); + sub_wire2(14, 12) <= sub_wire3(12); + sub_wire2(14, 13) <= sub_wire3(13); + sub_wire2(14, 14) <= sub_wire3(14); + sub_wire2(14, 15) <= sub_wire3(15); + sub_wire2(14, 16) <= sub_wire3(16); + sub_wire2(14, 17) <= sub_wire3(17); + sub_wire2(14, 18) <= sub_wire3(18); + sub_wire2(14, 19) <= sub_wire3(19); + sub_wire2(14, 20) <= sub_wire3(20); + sub_wire2(14, 21) <= sub_wire3(21); + sub_wire2(14, 22) <= sub_wire3(22); + sub_wire2(14, 23) <= sub_wire3(23); + sub_wire2(14, 24) <= sub_wire3(24); + sub_wire2(14, 25) <= sub_wire3(25); + sub_wire2(14, 26) <= sub_wire3(26); + sub_wire2(14, 27) <= sub_wire3(27); + sub_wire2(14, 28) <= sub_wire3(28); + sub_wire2(14, 29) <= sub_wire3(29); + sub_wire2(14, 30) <= sub_wire3(30); + sub_wire2(14, 31) <= sub_wire3(31); + sub_wire2(14, 32) <= sub_wire3(32); + sub_wire2(14, 33) <= sub_wire3(33); + sub_wire2(14, 34) <= sub_wire3(34); + sub_wire2(14, 35) <= sub_wire3(35); + sub_wire2(14, 36) <= sub_wire3(36); + sub_wire2(14, 37) <= sub_wire3(37); + sub_wire2(14, 38) <= sub_wire3(38); + sub_wire2(14, 39) <= sub_wire3(39); + sub_wire2(14, 40) <= sub_wire3(40); + sub_wire2(14, 41) <= sub_wire3(41); + sub_wire2(14, 42) <= sub_wire3(42); + sub_wire2(14, 43) <= sub_wire3(43); + sub_wire2(14, 44) <= sub_wire3(44); + sub_wire2(14, 45) <= sub_wire3(45); + sub_wire2(14, 46) <= sub_wire3(46); + sub_wire2(14, 47) <= sub_wire3(47); + sub_wire2(14, 48) <= sub_wire3(48); + sub_wire2(14, 49) <= sub_wire3(49); + sub_wire2(14, 50) <= sub_wire3(50); + sub_wire2(14, 51) <= sub_wire3(51); + sub_wire2(14, 52) <= sub_wire3(52); + sub_wire2(14, 53) <= sub_wire3(53); + sub_wire2(14, 54) <= sub_wire3(54); + sub_wire2(14, 55) <= sub_wire3(55); + sub_wire2(14, 56) <= sub_wire3(56); + sub_wire2(14, 57) <= sub_wire3(57); + sub_wire2(14, 58) <= sub_wire3(58); + sub_wire2(14, 59) <= sub_wire3(59); + sub_wire2(14, 60) <= sub_wire3(60); + sub_wire2(14, 61) <= sub_wire3(61); + sub_wire2(14, 62) <= sub_wire3(62); + sub_wire2(14, 63) <= sub_wire3(63); + sub_wire2(14, 64) <= sub_wire3(64); + sub_wire2(14, 65) <= sub_wire3(65); + sub_wire2(14, 66) <= sub_wire3(66); + sub_wire2(14, 67) <= sub_wire3(67); + sub_wire2(14, 68) <= sub_wire3(68); + sub_wire2(14, 69) <= sub_wire3(69); + sub_wire2(14, 70) <= sub_wire3(70); + sub_wire2(14, 71) <= sub_wire3(71); + sub_wire2(14, 72) <= sub_wire3(72); + sub_wire2(14, 73) <= sub_wire3(73); + sub_wire2(14, 74) <= sub_wire3(74); + sub_wire2(14, 75) <= sub_wire3(75); + sub_wire2(14, 76) <= sub_wire3(76); + sub_wire2(14, 77) <= sub_wire3(77); + sub_wire2(14, 78) <= sub_wire3(78); + sub_wire2(14, 79) <= sub_wire3(79); + sub_wire2(14, 80) <= sub_wire3(80); + sub_wire2(14, 81) <= sub_wire3(81); + sub_wire2(14, 82) <= sub_wire3(82); + sub_wire2(14, 83) <= sub_wire3(83); + sub_wire2(14, 84) <= sub_wire3(84); + sub_wire2(14, 85) <= sub_wire3(85); + sub_wire2(14, 86) <= sub_wire3(86); + sub_wire2(14, 87) <= sub_wire3(87); + sub_wire2(14, 88) <= sub_wire3(88); + sub_wire2(14, 89) <= sub_wire3(89); + sub_wire2(14, 90) <= sub_wire3(90); + sub_wire2(14, 91) <= sub_wire3(91); + sub_wire2(14, 92) <= sub_wire3(92); + sub_wire2(14, 93) <= sub_wire3(93); + sub_wire2(14, 94) <= sub_wire3(94); + sub_wire2(14, 95) <= sub_wire3(95); + sub_wire2(14, 96) <= sub_wire3(96); + sub_wire2(14, 97) <= sub_wire3(97); + sub_wire2(14, 98) <= sub_wire3(98); + sub_wire2(14, 99) <= sub_wire3(99); + sub_wire2(14, 100) <= sub_wire3(100); + sub_wire2(14, 101) <= sub_wire3(101); + sub_wire2(14, 102) <= sub_wire3(102); + sub_wire2(14, 103) <= sub_wire3(103); + sub_wire2(14, 104) <= sub_wire3(104); + sub_wire2(14, 105) <= sub_wire3(105); + sub_wire2(14, 106) <= sub_wire3(106); + sub_wire2(14, 107) <= sub_wire3(107); + sub_wire2(14, 108) <= sub_wire3(108); + sub_wire2(14, 109) <= sub_wire3(109); + sub_wire2(14, 110) <= sub_wire3(110); + sub_wire2(14, 111) <= sub_wire3(111); + sub_wire2(14, 112) <= sub_wire3(112); + sub_wire2(14, 113) <= sub_wire3(113); + sub_wire2(14, 114) <= sub_wire3(114); + sub_wire2(14, 115) <= sub_wire3(115); + sub_wire2(14, 116) <= sub_wire3(116); + sub_wire2(14, 117) <= sub_wire3(117); + sub_wire2(14, 118) <= sub_wire3(118); + sub_wire2(14, 119) <= sub_wire3(119); + sub_wire2(14, 120) <= sub_wire3(120); + sub_wire2(14, 121) <= sub_wire3(121); + sub_wire2(14, 122) <= sub_wire3(122); + sub_wire2(14, 123) <= sub_wire3(123); + sub_wire2(14, 124) <= sub_wire3(124); + sub_wire2(14, 125) <= sub_wire3(125); + sub_wire2(14, 126) <= sub_wire3(126); + sub_wire2(14, 127) <= sub_wire3(127); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(13, 8) <= sub_wire4(8); + sub_wire2(13, 9) <= sub_wire4(9); + sub_wire2(13, 10) <= sub_wire4(10); + sub_wire2(13, 11) <= sub_wire4(11); + sub_wire2(13, 12) <= sub_wire4(12); + sub_wire2(13, 13) <= sub_wire4(13); + sub_wire2(13, 14) <= sub_wire4(14); + sub_wire2(13, 15) <= sub_wire4(15); + sub_wire2(13, 16) <= sub_wire4(16); + sub_wire2(13, 17) <= sub_wire4(17); + sub_wire2(13, 18) <= sub_wire4(18); + sub_wire2(13, 19) <= sub_wire4(19); + sub_wire2(13, 20) <= sub_wire4(20); + sub_wire2(13, 21) <= sub_wire4(21); + sub_wire2(13, 22) <= sub_wire4(22); + sub_wire2(13, 23) <= sub_wire4(23); + sub_wire2(13, 24) <= sub_wire4(24); + sub_wire2(13, 25) <= sub_wire4(25); + sub_wire2(13, 26) <= sub_wire4(26); + sub_wire2(13, 27) <= sub_wire4(27); + sub_wire2(13, 28) <= sub_wire4(28); + sub_wire2(13, 29) <= sub_wire4(29); + sub_wire2(13, 30) <= sub_wire4(30); + sub_wire2(13, 31) <= sub_wire4(31); + sub_wire2(13, 32) <= sub_wire4(32); + sub_wire2(13, 33) <= sub_wire4(33); + sub_wire2(13, 34) <= sub_wire4(34); + sub_wire2(13, 35) <= sub_wire4(35); + sub_wire2(13, 36) <= sub_wire4(36); + sub_wire2(13, 37) <= sub_wire4(37); + sub_wire2(13, 38) <= sub_wire4(38); + sub_wire2(13, 39) <= sub_wire4(39); + sub_wire2(13, 40) <= sub_wire4(40); + sub_wire2(13, 41) <= sub_wire4(41); + sub_wire2(13, 42) <= sub_wire4(42); + sub_wire2(13, 43) <= sub_wire4(43); + sub_wire2(13, 44) <= sub_wire4(44); + sub_wire2(13, 45) <= sub_wire4(45); + sub_wire2(13, 46) <= sub_wire4(46); + sub_wire2(13, 47) <= sub_wire4(47); + sub_wire2(13, 48) <= sub_wire4(48); + sub_wire2(13, 49) <= sub_wire4(49); + sub_wire2(13, 50) <= sub_wire4(50); + sub_wire2(13, 51) <= sub_wire4(51); + sub_wire2(13, 52) <= sub_wire4(52); + sub_wire2(13, 53) <= sub_wire4(53); + sub_wire2(13, 54) <= sub_wire4(54); + sub_wire2(13, 55) <= sub_wire4(55); + sub_wire2(13, 56) <= sub_wire4(56); + sub_wire2(13, 57) <= sub_wire4(57); + sub_wire2(13, 58) <= sub_wire4(58); + sub_wire2(13, 59) <= sub_wire4(59); + sub_wire2(13, 60) <= sub_wire4(60); + sub_wire2(13, 61) <= sub_wire4(61); + sub_wire2(13, 62) <= sub_wire4(62); + sub_wire2(13, 63) <= sub_wire4(63); + sub_wire2(13, 64) <= sub_wire4(64); + sub_wire2(13, 65) <= sub_wire4(65); + sub_wire2(13, 66) <= sub_wire4(66); + sub_wire2(13, 67) <= sub_wire4(67); + sub_wire2(13, 68) <= sub_wire4(68); + sub_wire2(13, 69) <= sub_wire4(69); + sub_wire2(13, 70) <= sub_wire4(70); + sub_wire2(13, 71) <= sub_wire4(71); + sub_wire2(13, 72) <= sub_wire4(72); + sub_wire2(13, 73) <= sub_wire4(73); + sub_wire2(13, 74) <= sub_wire4(74); + sub_wire2(13, 75) <= sub_wire4(75); + sub_wire2(13, 76) <= sub_wire4(76); + sub_wire2(13, 77) <= sub_wire4(77); + sub_wire2(13, 78) <= sub_wire4(78); + sub_wire2(13, 79) <= sub_wire4(79); + sub_wire2(13, 80) <= sub_wire4(80); + sub_wire2(13, 81) <= sub_wire4(81); + sub_wire2(13, 82) <= sub_wire4(82); + sub_wire2(13, 83) <= sub_wire4(83); + sub_wire2(13, 84) <= sub_wire4(84); + sub_wire2(13, 85) <= sub_wire4(85); + sub_wire2(13, 86) <= sub_wire4(86); + sub_wire2(13, 87) <= sub_wire4(87); + sub_wire2(13, 88) <= sub_wire4(88); + sub_wire2(13, 89) <= sub_wire4(89); + sub_wire2(13, 90) <= sub_wire4(90); + sub_wire2(13, 91) <= sub_wire4(91); + sub_wire2(13, 92) <= sub_wire4(92); + sub_wire2(13, 93) <= sub_wire4(93); + sub_wire2(13, 94) <= sub_wire4(94); + sub_wire2(13, 95) <= sub_wire4(95); + sub_wire2(13, 96) <= sub_wire4(96); + sub_wire2(13, 97) <= sub_wire4(97); + sub_wire2(13, 98) <= sub_wire4(98); + sub_wire2(13, 99) <= sub_wire4(99); + sub_wire2(13, 100) <= sub_wire4(100); + sub_wire2(13, 101) <= sub_wire4(101); + sub_wire2(13, 102) <= sub_wire4(102); + sub_wire2(13, 103) <= sub_wire4(103); + sub_wire2(13, 104) <= sub_wire4(104); + sub_wire2(13, 105) <= sub_wire4(105); + sub_wire2(13, 106) <= sub_wire4(106); + sub_wire2(13, 107) <= sub_wire4(107); + sub_wire2(13, 108) <= sub_wire4(108); + sub_wire2(13, 109) <= sub_wire4(109); + sub_wire2(13, 110) <= sub_wire4(110); + sub_wire2(13, 111) <= sub_wire4(111); + sub_wire2(13, 112) <= sub_wire4(112); + sub_wire2(13, 113) <= sub_wire4(113); + sub_wire2(13, 114) <= sub_wire4(114); + sub_wire2(13, 115) <= sub_wire4(115); + sub_wire2(13, 116) <= sub_wire4(116); + sub_wire2(13, 117) <= sub_wire4(117); + sub_wire2(13, 118) <= sub_wire4(118); + sub_wire2(13, 119) <= sub_wire4(119); + sub_wire2(13, 120) <= sub_wire4(120); + sub_wire2(13, 121) <= sub_wire4(121); + sub_wire2(13, 122) <= sub_wire4(122); + sub_wire2(13, 123) <= sub_wire4(123); + sub_wire2(13, 124) <= sub_wire4(124); + sub_wire2(13, 125) <= sub_wire4(125); + sub_wire2(13, 126) <= sub_wire4(126); + sub_wire2(13, 127) <= sub_wire4(127); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(12, 8) <= sub_wire5(8); + sub_wire2(12, 9) <= sub_wire5(9); + sub_wire2(12, 10) <= sub_wire5(10); + sub_wire2(12, 11) <= sub_wire5(11); + sub_wire2(12, 12) <= sub_wire5(12); + sub_wire2(12, 13) <= sub_wire5(13); + sub_wire2(12, 14) <= sub_wire5(14); + sub_wire2(12, 15) <= sub_wire5(15); + sub_wire2(12, 16) <= sub_wire5(16); + sub_wire2(12, 17) <= sub_wire5(17); + sub_wire2(12, 18) <= sub_wire5(18); + sub_wire2(12, 19) <= sub_wire5(19); + sub_wire2(12, 20) <= sub_wire5(20); + sub_wire2(12, 21) <= sub_wire5(21); + sub_wire2(12, 22) <= sub_wire5(22); + sub_wire2(12, 23) <= sub_wire5(23); + sub_wire2(12, 24) <= sub_wire5(24); + sub_wire2(12, 25) <= sub_wire5(25); + sub_wire2(12, 26) <= sub_wire5(26); + sub_wire2(12, 27) <= sub_wire5(27); + sub_wire2(12, 28) <= sub_wire5(28); + sub_wire2(12, 29) <= sub_wire5(29); + sub_wire2(12, 30) <= sub_wire5(30); + sub_wire2(12, 31) <= sub_wire5(31); + sub_wire2(12, 32) <= sub_wire5(32); + sub_wire2(12, 33) <= sub_wire5(33); + sub_wire2(12, 34) <= sub_wire5(34); + sub_wire2(12, 35) <= sub_wire5(35); + sub_wire2(12, 36) <= sub_wire5(36); + sub_wire2(12, 37) <= sub_wire5(37); + sub_wire2(12, 38) <= sub_wire5(38); + sub_wire2(12, 39) <= sub_wire5(39); + sub_wire2(12, 40) <= sub_wire5(40); + sub_wire2(12, 41) <= sub_wire5(41); + sub_wire2(12, 42) <= sub_wire5(42); + sub_wire2(12, 43) <= sub_wire5(43); + sub_wire2(12, 44) <= sub_wire5(44); + sub_wire2(12, 45) <= sub_wire5(45); + sub_wire2(12, 46) <= sub_wire5(46); + sub_wire2(12, 47) <= sub_wire5(47); + sub_wire2(12, 48) <= sub_wire5(48); + sub_wire2(12, 49) <= sub_wire5(49); + sub_wire2(12, 50) <= sub_wire5(50); + sub_wire2(12, 51) <= sub_wire5(51); + sub_wire2(12, 52) <= sub_wire5(52); + sub_wire2(12, 53) <= sub_wire5(53); + sub_wire2(12, 54) <= sub_wire5(54); + sub_wire2(12, 55) <= sub_wire5(55); + sub_wire2(12, 56) <= sub_wire5(56); + sub_wire2(12, 57) <= sub_wire5(57); + sub_wire2(12, 58) <= sub_wire5(58); + sub_wire2(12, 59) <= sub_wire5(59); + sub_wire2(12, 60) <= sub_wire5(60); + sub_wire2(12, 61) <= sub_wire5(61); + sub_wire2(12, 62) <= sub_wire5(62); + sub_wire2(12, 63) <= sub_wire5(63); + sub_wire2(12, 64) <= sub_wire5(64); + sub_wire2(12, 65) <= sub_wire5(65); + sub_wire2(12, 66) <= sub_wire5(66); + sub_wire2(12, 67) <= sub_wire5(67); + sub_wire2(12, 68) <= sub_wire5(68); + sub_wire2(12, 69) <= sub_wire5(69); + sub_wire2(12, 70) <= sub_wire5(70); + sub_wire2(12, 71) <= sub_wire5(71); + sub_wire2(12, 72) <= sub_wire5(72); + sub_wire2(12, 73) <= sub_wire5(73); + sub_wire2(12, 74) <= sub_wire5(74); + sub_wire2(12, 75) <= sub_wire5(75); + sub_wire2(12, 76) <= sub_wire5(76); + sub_wire2(12, 77) <= sub_wire5(77); + sub_wire2(12, 78) <= sub_wire5(78); + sub_wire2(12, 79) <= sub_wire5(79); + sub_wire2(12, 80) <= sub_wire5(80); + sub_wire2(12, 81) <= sub_wire5(81); + sub_wire2(12, 82) <= sub_wire5(82); + sub_wire2(12, 83) <= sub_wire5(83); + sub_wire2(12, 84) <= sub_wire5(84); + sub_wire2(12, 85) <= sub_wire5(85); + sub_wire2(12, 86) <= sub_wire5(86); + sub_wire2(12, 87) <= sub_wire5(87); + sub_wire2(12, 88) <= sub_wire5(88); + sub_wire2(12, 89) <= sub_wire5(89); + sub_wire2(12, 90) <= sub_wire5(90); + sub_wire2(12, 91) <= sub_wire5(91); + sub_wire2(12, 92) <= sub_wire5(92); + sub_wire2(12, 93) <= sub_wire5(93); + sub_wire2(12, 94) <= sub_wire5(94); + sub_wire2(12, 95) <= sub_wire5(95); + sub_wire2(12, 96) <= sub_wire5(96); + sub_wire2(12, 97) <= sub_wire5(97); + sub_wire2(12, 98) <= sub_wire5(98); + sub_wire2(12, 99) <= sub_wire5(99); + sub_wire2(12, 100) <= sub_wire5(100); + sub_wire2(12, 101) <= sub_wire5(101); + sub_wire2(12, 102) <= sub_wire5(102); + sub_wire2(12, 103) <= sub_wire5(103); + sub_wire2(12, 104) <= sub_wire5(104); + sub_wire2(12, 105) <= sub_wire5(105); + sub_wire2(12, 106) <= sub_wire5(106); + sub_wire2(12, 107) <= sub_wire5(107); + sub_wire2(12, 108) <= sub_wire5(108); + sub_wire2(12, 109) <= sub_wire5(109); + sub_wire2(12, 110) <= sub_wire5(110); + sub_wire2(12, 111) <= sub_wire5(111); + sub_wire2(12, 112) <= sub_wire5(112); + sub_wire2(12, 113) <= sub_wire5(113); + sub_wire2(12, 114) <= sub_wire5(114); + sub_wire2(12, 115) <= sub_wire5(115); + sub_wire2(12, 116) <= sub_wire5(116); + sub_wire2(12, 117) <= sub_wire5(117); + sub_wire2(12, 118) <= sub_wire5(118); + sub_wire2(12, 119) <= sub_wire5(119); + sub_wire2(12, 120) <= sub_wire5(120); + sub_wire2(12, 121) <= sub_wire5(121); + sub_wire2(12, 122) <= sub_wire5(122); + sub_wire2(12, 123) <= sub_wire5(123); + sub_wire2(12, 124) <= sub_wire5(124); + sub_wire2(12, 125) <= sub_wire5(125); + sub_wire2(12, 126) <= sub_wire5(126); + sub_wire2(12, 127) <= sub_wire5(127); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(11, 8) <= sub_wire6(8); + sub_wire2(11, 9) <= sub_wire6(9); + sub_wire2(11, 10) <= sub_wire6(10); + sub_wire2(11, 11) <= sub_wire6(11); + sub_wire2(11, 12) <= sub_wire6(12); + sub_wire2(11, 13) <= sub_wire6(13); + sub_wire2(11, 14) <= sub_wire6(14); + sub_wire2(11, 15) <= sub_wire6(15); + sub_wire2(11, 16) <= sub_wire6(16); + sub_wire2(11, 17) <= sub_wire6(17); + sub_wire2(11, 18) <= sub_wire6(18); + sub_wire2(11, 19) <= sub_wire6(19); + sub_wire2(11, 20) <= sub_wire6(20); + sub_wire2(11, 21) <= sub_wire6(21); + sub_wire2(11, 22) <= sub_wire6(22); + sub_wire2(11, 23) <= sub_wire6(23); + sub_wire2(11, 24) <= sub_wire6(24); + sub_wire2(11, 25) <= sub_wire6(25); + sub_wire2(11, 26) <= sub_wire6(26); + sub_wire2(11, 27) <= sub_wire6(27); + sub_wire2(11, 28) <= sub_wire6(28); + sub_wire2(11, 29) <= sub_wire6(29); + sub_wire2(11, 30) <= sub_wire6(30); + sub_wire2(11, 31) <= sub_wire6(31); + sub_wire2(11, 32) <= sub_wire6(32); + sub_wire2(11, 33) <= sub_wire6(33); + sub_wire2(11, 34) <= sub_wire6(34); + sub_wire2(11, 35) <= sub_wire6(35); + sub_wire2(11, 36) <= sub_wire6(36); + sub_wire2(11, 37) <= sub_wire6(37); + sub_wire2(11, 38) <= sub_wire6(38); + sub_wire2(11, 39) <= sub_wire6(39); + sub_wire2(11, 40) <= sub_wire6(40); + sub_wire2(11, 41) <= sub_wire6(41); + sub_wire2(11, 42) <= sub_wire6(42); + sub_wire2(11, 43) <= sub_wire6(43); + sub_wire2(11, 44) <= sub_wire6(44); + sub_wire2(11, 45) <= sub_wire6(45); + sub_wire2(11, 46) <= sub_wire6(46); + sub_wire2(11, 47) <= sub_wire6(47); + sub_wire2(11, 48) <= sub_wire6(48); + sub_wire2(11, 49) <= sub_wire6(49); + sub_wire2(11, 50) <= sub_wire6(50); + sub_wire2(11, 51) <= sub_wire6(51); + sub_wire2(11, 52) <= sub_wire6(52); + sub_wire2(11, 53) <= sub_wire6(53); + sub_wire2(11, 54) <= sub_wire6(54); + sub_wire2(11, 55) <= sub_wire6(55); + sub_wire2(11, 56) <= sub_wire6(56); + sub_wire2(11, 57) <= sub_wire6(57); + sub_wire2(11, 58) <= sub_wire6(58); + sub_wire2(11, 59) <= sub_wire6(59); + sub_wire2(11, 60) <= sub_wire6(60); + sub_wire2(11, 61) <= sub_wire6(61); + sub_wire2(11, 62) <= sub_wire6(62); + sub_wire2(11, 63) <= sub_wire6(63); + sub_wire2(11, 64) <= sub_wire6(64); + sub_wire2(11, 65) <= sub_wire6(65); + sub_wire2(11, 66) <= sub_wire6(66); + sub_wire2(11, 67) <= sub_wire6(67); + sub_wire2(11, 68) <= sub_wire6(68); + sub_wire2(11, 69) <= sub_wire6(69); + sub_wire2(11, 70) <= sub_wire6(70); + sub_wire2(11, 71) <= sub_wire6(71); + sub_wire2(11, 72) <= sub_wire6(72); + sub_wire2(11, 73) <= sub_wire6(73); + sub_wire2(11, 74) <= sub_wire6(74); + sub_wire2(11, 75) <= sub_wire6(75); + sub_wire2(11, 76) <= sub_wire6(76); + sub_wire2(11, 77) <= sub_wire6(77); + sub_wire2(11, 78) <= sub_wire6(78); + sub_wire2(11, 79) <= sub_wire6(79); + sub_wire2(11, 80) <= sub_wire6(80); + sub_wire2(11, 81) <= sub_wire6(81); + sub_wire2(11, 82) <= sub_wire6(82); + sub_wire2(11, 83) <= sub_wire6(83); + sub_wire2(11, 84) <= sub_wire6(84); + sub_wire2(11, 85) <= sub_wire6(85); + sub_wire2(11, 86) <= sub_wire6(86); + sub_wire2(11, 87) <= sub_wire6(87); + sub_wire2(11, 88) <= sub_wire6(88); + sub_wire2(11, 89) <= sub_wire6(89); + sub_wire2(11, 90) <= sub_wire6(90); + sub_wire2(11, 91) <= sub_wire6(91); + sub_wire2(11, 92) <= sub_wire6(92); + sub_wire2(11, 93) <= sub_wire6(93); + sub_wire2(11, 94) <= sub_wire6(94); + sub_wire2(11, 95) <= sub_wire6(95); + sub_wire2(11, 96) <= sub_wire6(96); + sub_wire2(11, 97) <= sub_wire6(97); + sub_wire2(11, 98) <= sub_wire6(98); + sub_wire2(11, 99) <= sub_wire6(99); + sub_wire2(11, 100) <= sub_wire6(100); + sub_wire2(11, 101) <= sub_wire6(101); + sub_wire2(11, 102) <= sub_wire6(102); + sub_wire2(11, 103) <= sub_wire6(103); + sub_wire2(11, 104) <= sub_wire6(104); + sub_wire2(11, 105) <= sub_wire6(105); + sub_wire2(11, 106) <= sub_wire6(106); + sub_wire2(11, 107) <= sub_wire6(107); + sub_wire2(11, 108) <= sub_wire6(108); + sub_wire2(11, 109) <= sub_wire6(109); + sub_wire2(11, 110) <= sub_wire6(110); + sub_wire2(11, 111) <= sub_wire6(111); + sub_wire2(11, 112) <= sub_wire6(112); + sub_wire2(11, 113) <= sub_wire6(113); + sub_wire2(11, 114) <= sub_wire6(114); + sub_wire2(11, 115) <= sub_wire6(115); + sub_wire2(11, 116) <= sub_wire6(116); + sub_wire2(11, 117) <= sub_wire6(117); + sub_wire2(11, 118) <= sub_wire6(118); + sub_wire2(11, 119) <= sub_wire6(119); + sub_wire2(11, 120) <= sub_wire6(120); + sub_wire2(11, 121) <= sub_wire6(121); + sub_wire2(11, 122) <= sub_wire6(122); + sub_wire2(11, 123) <= sub_wire6(123); + sub_wire2(11, 124) <= sub_wire6(124); + sub_wire2(11, 125) <= sub_wire6(125); + sub_wire2(11, 126) <= sub_wire6(126); + sub_wire2(11, 127) <= sub_wire6(127); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(10, 8) <= sub_wire7(8); + sub_wire2(10, 9) <= sub_wire7(9); + sub_wire2(10, 10) <= sub_wire7(10); + sub_wire2(10, 11) <= sub_wire7(11); + sub_wire2(10, 12) <= sub_wire7(12); + sub_wire2(10, 13) <= sub_wire7(13); + sub_wire2(10, 14) <= sub_wire7(14); + sub_wire2(10, 15) <= sub_wire7(15); + sub_wire2(10, 16) <= sub_wire7(16); + sub_wire2(10, 17) <= sub_wire7(17); + sub_wire2(10, 18) <= sub_wire7(18); + sub_wire2(10, 19) <= sub_wire7(19); + sub_wire2(10, 20) <= sub_wire7(20); + sub_wire2(10, 21) <= sub_wire7(21); + sub_wire2(10, 22) <= sub_wire7(22); + sub_wire2(10, 23) <= sub_wire7(23); + sub_wire2(10, 24) <= sub_wire7(24); + sub_wire2(10, 25) <= sub_wire7(25); + sub_wire2(10, 26) <= sub_wire7(26); + sub_wire2(10, 27) <= sub_wire7(27); + sub_wire2(10, 28) <= sub_wire7(28); + sub_wire2(10, 29) <= sub_wire7(29); + sub_wire2(10, 30) <= sub_wire7(30); + sub_wire2(10, 31) <= sub_wire7(31); + sub_wire2(10, 32) <= sub_wire7(32); + sub_wire2(10, 33) <= sub_wire7(33); + sub_wire2(10, 34) <= sub_wire7(34); + sub_wire2(10, 35) <= sub_wire7(35); + sub_wire2(10, 36) <= sub_wire7(36); + sub_wire2(10, 37) <= sub_wire7(37); + sub_wire2(10, 38) <= sub_wire7(38); + sub_wire2(10, 39) <= sub_wire7(39); + sub_wire2(10, 40) <= sub_wire7(40); + sub_wire2(10, 41) <= sub_wire7(41); + sub_wire2(10, 42) <= sub_wire7(42); + sub_wire2(10, 43) <= sub_wire7(43); + sub_wire2(10, 44) <= sub_wire7(44); + sub_wire2(10, 45) <= sub_wire7(45); + sub_wire2(10, 46) <= sub_wire7(46); + sub_wire2(10, 47) <= sub_wire7(47); + sub_wire2(10, 48) <= sub_wire7(48); + sub_wire2(10, 49) <= sub_wire7(49); + sub_wire2(10, 50) <= sub_wire7(50); + sub_wire2(10, 51) <= sub_wire7(51); + sub_wire2(10, 52) <= sub_wire7(52); + sub_wire2(10, 53) <= sub_wire7(53); + sub_wire2(10, 54) <= sub_wire7(54); + sub_wire2(10, 55) <= sub_wire7(55); + sub_wire2(10, 56) <= sub_wire7(56); + sub_wire2(10, 57) <= sub_wire7(57); + sub_wire2(10, 58) <= sub_wire7(58); + sub_wire2(10, 59) <= sub_wire7(59); + sub_wire2(10, 60) <= sub_wire7(60); + sub_wire2(10, 61) <= sub_wire7(61); + sub_wire2(10, 62) <= sub_wire7(62); + sub_wire2(10, 63) <= sub_wire7(63); + sub_wire2(10, 64) <= sub_wire7(64); + sub_wire2(10, 65) <= sub_wire7(65); + sub_wire2(10, 66) <= sub_wire7(66); + sub_wire2(10, 67) <= sub_wire7(67); + sub_wire2(10, 68) <= sub_wire7(68); + sub_wire2(10, 69) <= sub_wire7(69); + sub_wire2(10, 70) <= sub_wire7(70); + sub_wire2(10, 71) <= sub_wire7(71); + sub_wire2(10, 72) <= sub_wire7(72); + sub_wire2(10, 73) <= sub_wire7(73); + sub_wire2(10, 74) <= sub_wire7(74); + sub_wire2(10, 75) <= sub_wire7(75); + sub_wire2(10, 76) <= sub_wire7(76); + sub_wire2(10, 77) <= sub_wire7(77); + sub_wire2(10, 78) <= sub_wire7(78); + sub_wire2(10, 79) <= sub_wire7(79); + sub_wire2(10, 80) <= sub_wire7(80); + sub_wire2(10, 81) <= sub_wire7(81); + sub_wire2(10, 82) <= sub_wire7(82); + sub_wire2(10, 83) <= sub_wire7(83); + sub_wire2(10, 84) <= sub_wire7(84); + sub_wire2(10, 85) <= sub_wire7(85); + sub_wire2(10, 86) <= sub_wire7(86); + sub_wire2(10, 87) <= sub_wire7(87); + sub_wire2(10, 88) <= sub_wire7(88); + sub_wire2(10, 89) <= sub_wire7(89); + sub_wire2(10, 90) <= sub_wire7(90); + sub_wire2(10, 91) <= sub_wire7(91); + sub_wire2(10, 92) <= sub_wire7(92); + sub_wire2(10, 93) <= sub_wire7(93); + sub_wire2(10, 94) <= sub_wire7(94); + sub_wire2(10, 95) <= sub_wire7(95); + sub_wire2(10, 96) <= sub_wire7(96); + sub_wire2(10, 97) <= sub_wire7(97); + sub_wire2(10, 98) <= sub_wire7(98); + sub_wire2(10, 99) <= sub_wire7(99); + sub_wire2(10, 100) <= sub_wire7(100); + sub_wire2(10, 101) <= sub_wire7(101); + sub_wire2(10, 102) <= sub_wire7(102); + sub_wire2(10, 103) <= sub_wire7(103); + sub_wire2(10, 104) <= sub_wire7(104); + sub_wire2(10, 105) <= sub_wire7(105); + sub_wire2(10, 106) <= sub_wire7(106); + sub_wire2(10, 107) <= sub_wire7(107); + sub_wire2(10, 108) <= sub_wire7(108); + sub_wire2(10, 109) <= sub_wire7(109); + sub_wire2(10, 110) <= sub_wire7(110); + sub_wire2(10, 111) <= sub_wire7(111); + sub_wire2(10, 112) <= sub_wire7(112); + sub_wire2(10, 113) <= sub_wire7(113); + sub_wire2(10, 114) <= sub_wire7(114); + sub_wire2(10, 115) <= sub_wire7(115); + sub_wire2(10, 116) <= sub_wire7(116); + sub_wire2(10, 117) <= sub_wire7(117); + sub_wire2(10, 118) <= sub_wire7(118); + sub_wire2(10, 119) <= sub_wire7(119); + sub_wire2(10, 120) <= sub_wire7(120); + sub_wire2(10, 121) <= sub_wire7(121); + sub_wire2(10, 122) <= sub_wire7(122); + sub_wire2(10, 123) <= sub_wire7(123); + sub_wire2(10, 124) <= sub_wire7(124); + sub_wire2(10, 125) <= sub_wire7(125); + sub_wire2(10, 126) <= sub_wire7(126); + sub_wire2(10, 127) <= sub_wire7(127); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(9, 8) <= sub_wire8(8); + sub_wire2(9, 9) <= sub_wire8(9); + sub_wire2(9, 10) <= sub_wire8(10); + sub_wire2(9, 11) <= sub_wire8(11); + sub_wire2(9, 12) <= sub_wire8(12); + sub_wire2(9, 13) <= sub_wire8(13); + sub_wire2(9, 14) <= sub_wire8(14); + sub_wire2(9, 15) <= sub_wire8(15); + sub_wire2(9, 16) <= sub_wire8(16); + sub_wire2(9, 17) <= sub_wire8(17); + sub_wire2(9, 18) <= sub_wire8(18); + sub_wire2(9, 19) <= sub_wire8(19); + sub_wire2(9, 20) <= sub_wire8(20); + sub_wire2(9, 21) <= sub_wire8(21); + sub_wire2(9, 22) <= sub_wire8(22); + sub_wire2(9, 23) <= sub_wire8(23); + sub_wire2(9, 24) <= sub_wire8(24); + sub_wire2(9, 25) <= sub_wire8(25); + sub_wire2(9, 26) <= sub_wire8(26); + sub_wire2(9, 27) <= sub_wire8(27); + sub_wire2(9, 28) <= sub_wire8(28); + sub_wire2(9, 29) <= sub_wire8(29); + sub_wire2(9, 30) <= sub_wire8(30); + sub_wire2(9, 31) <= sub_wire8(31); + sub_wire2(9, 32) <= sub_wire8(32); + sub_wire2(9, 33) <= sub_wire8(33); + sub_wire2(9, 34) <= sub_wire8(34); + sub_wire2(9, 35) <= sub_wire8(35); + sub_wire2(9, 36) <= sub_wire8(36); + sub_wire2(9, 37) <= sub_wire8(37); + sub_wire2(9, 38) <= sub_wire8(38); + sub_wire2(9, 39) <= sub_wire8(39); + sub_wire2(9, 40) <= sub_wire8(40); + sub_wire2(9, 41) <= sub_wire8(41); + sub_wire2(9, 42) <= sub_wire8(42); + sub_wire2(9, 43) <= sub_wire8(43); + sub_wire2(9, 44) <= sub_wire8(44); + sub_wire2(9, 45) <= sub_wire8(45); + sub_wire2(9, 46) <= sub_wire8(46); + sub_wire2(9, 47) <= sub_wire8(47); + sub_wire2(9, 48) <= sub_wire8(48); + sub_wire2(9, 49) <= sub_wire8(49); + sub_wire2(9, 50) <= sub_wire8(50); + sub_wire2(9, 51) <= sub_wire8(51); + sub_wire2(9, 52) <= sub_wire8(52); + sub_wire2(9, 53) <= sub_wire8(53); + sub_wire2(9, 54) <= sub_wire8(54); + sub_wire2(9, 55) <= sub_wire8(55); + sub_wire2(9, 56) <= sub_wire8(56); + sub_wire2(9, 57) <= sub_wire8(57); + sub_wire2(9, 58) <= sub_wire8(58); + sub_wire2(9, 59) <= sub_wire8(59); + sub_wire2(9, 60) <= sub_wire8(60); + sub_wire2(9, 61) <= sub_wire8(61); + sub_wire2(9, 62) <= sub_wire8(62); + sub_wire2(9, 63) <= sub_wire8(63); + sub_wire2(9, 64) <= sub_wire8(64); + sub_wire2(9, 65) <= sub_wire8(65); + sub_wire2(9, 66) <= sub_wire8(66); + sub_wire2(9, 67) <= sub_wire8(67); + sub_wire2(9, 68) <= sub_wire8(68); + sub_wire2(9, 69) <= sub_wire8(69); + sub_wire2(9, 70) <= sub_wire8(70); + sub_wire2(9, 71) <= sub_wire8(71); + sub_wire2(9, 72) <= sub_wire8(72); + sub_wire2(9, 73) <= sub_wire8(73); + sub_wire2(9, 74) <= sub_wire8(74); + sub_wire2(9, 75) <= sub_wire8(75); + sub_wire2(9, 76) <= sub_wire8(76); + sub_wire2(9, 77) <= sub_wire8(77); + sub_wire2(9, 78) <= sub_wire8(78); + sub_wire2(9, 79) <= sub_wire8(79); + sub_wire2(9, 80) <= sub_wire8(80); + sub_wire2(9, 81) <= sub_wire8(81); + sub_wire2(9, 82) <= sub_wire8(82); + sub_wire2(9, 83) <= sub_wire8(83); + sub_wire2(9, 84) <= sub_wire8(84); + sub_wire2(9, 85) <= sub_wire8(85); + sub_wire2(9, 86) <= sub_wire8(86); + sub_wire2(9, 87) <= sub_wire8(87); + sub_wire2(9, 88) <= sub_wire8(88); + sub_wire2(9, 89) <= sub_wire8(89); + sub_wire2(9, 90) <= sub_wire8(90); + sub_wire2(9, 91) <= sub_wire8(91); + sub_wire2(9, 92) <= sub_wire8(92); + sub_wire2(9, 93) <= sub_wire8(93); + sub_wire2(9, 94) <= sub_wire8(94); + sub_wire2(9, 95) <= sub_wire8(95); + sub_wire2(9, 96) <= sub_wire8(96); + sub_wire2(9, 97) <= sub_wire8(97); + sub_wire2(9, 98) <= sub_wire8(98); + sub_wire2(9, 99) <= sub_wire8(99); + sub_wire2(9, 100) <= sub_wire8(100); + sub_wire2(9, 101) <= sub_wire8(101); + sub_wire2(9, 102) <= sub_wire8(102); + sub_wire2(9, 103) <= sub_wire8(103); + sub_wire2(9, 104) <= sub_wire8(104); + sub_wire2(9, 105) <= sub_wire8(105); + sub_wire2(9, 106) <= sub_wire8(106); + sub_wire2(9, 107) <= sub_wire8(107); + sub_wire2(9, 108) <= sub_wire8(108); + sub_wire2(9, 109) <= sub_wire8(109); + sub_wire2(9, 110) <= sub_wire8(110); + sub_wire2(9, 111) <= sub_wire8(111); + sub_wire2(9, 112) <= sub_wire8(112); + sub_wire2(9, 113) <= sub_wire8(113); + sub_wire2(9, 114) <= sub_wire8(114); + sub_wire2(9, 115) <= sub_wire8(115); + sub_wire2(9, 116) <= sub_wire8(116); + sub_wire2(9, 117) <= sub_wire8(117); + sub_wire2(9, 118) <= sub_wire8(118); + sub_wire2(9, 119) <= sub_wire8(119); + sub_wire2(9, 120) <= sub_wire8(120); + sub_wire2(9, 121) <= sub_wire8(121); + sub_wire2(9, 122) <= sub_wire8(122); + sub_wire2(9, 123) <= sub_wire8(123); + sub_wire2(9, 124) <= sub_wire8(124); + sub_wire2(9, 125) <= sub_wire8(125); + sub_wire2(9, 126) <= sub_wire8(126); + sub_wire2(9, 127) <= sub_wire8(127); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(8, 8) <= sub_wire9(8); + sub_wire2(8, 9) <= sub_wire9(9); + sub_wire2(8, 10) <= sub_wire9(10); + sub_wire2(8, 11) <= sub_wire9(11); + sub_wire2(8, 12) <= sub_wire9(12); + sub_wire2(8, 13) <= sub_wire9(13); + sub_wire2(8, 14) <= sub_wire9(14); + sub_wire2(8, 15) <= sub_wire9(15); + sub_wire2(8, 16) <= sub_wire9(16); + sub_wire2(8, 17) <= sub_wire9(17); + sub_wire2(8, 18) <= sub_wire9(18); + sub_wire2(8, 19) <= sub_wire9(19); + sub_wire2(8, 20) <= sub_wire9(20); + sub_wire2(8, 21) <= sub_wire9(21); + sub_wire2(8, 22) <= sub_wire9(22); + sub_wire2(8, 23) <= sub_wire9(23); + sub_wire2(8, 24) <= sub_wire9(24); + sub_wire2(8, 25) <= sub_wire9(25); + sub_wire2(8, 26) <= sub_wire9(26); + sub_wire2(8, 27) <= sub_wire9(27); + sub_wire2(8, 28) <= sub_wire9(28); + sub_wire2(8, 29) <= sub_wire9(29); + sub_wire2(8, 30) <= sub_wire9(30); + sub_wire2(8, 31) <= sub_wire9(31); + sub_wire2(8, 32) <= sub_wire9(32); + sub_wire2(8, 33) <= sub_wire9(33); + sub_wire2(8, 34) <= sub_wire9(34); + sub_wire2(8, 35) <= sub_wire9(35); + sub_wire2(8, 36) <= sub_wire9(36); + sub_wire2(8, 37) <= sub_wire9(37); + sub_wire2(8, 38) <= sub_wire9(38); + sub_wire2(8, 39) <= sub_wire9(39); + sub_wire2(8, 40) <= sub_wire9(40); + sub_wire2(8, 41) <= sub_wire9(41); + sub_wire2(8, 42) <= sub_wire9(42); + sub_wire2(8, 43) <= sub_wire9(43); + sub_wire2(8, 44) <= sub_wire9(44); + sub_wire2(8, 45) <= sub_wire9(45); + sub_wire2(8, 46) <= sub_wire9(46); + sub_wire2(8, 47) <= sub_wire9(47); + sub_wire2(8, 48) <= sub_wire9(48); + sub_wire2(8, 49) <= sub_wire9(49); + sub_wire2(8, 50) <= sub_wire9(50); + sub_wire2(8, 51) <= sub_wire9(51); + sub_wire2(8, 52) <= sub_wire9(52); + sub_wire2(8, 53) <= sub_wire9(53); + sub_wire2(8, 54) <= sub_wire9(54); + sub_wire2(8, 55) <= sub_wire9(55); + sub_wire2(8, 56) <= sub_wire9(56); + sub_wire2(8, 57) <= sub_wire9(57); + sub_wire2(8, 58) <= sub_wire9(58); + sub_wire2(8, 59) <= sub_wire9(59); + sub_wire2(8, 60) <= sub_wire9(60); + sub_wire2(8, 61) <= sub_wire9(61); + sub_wire2(8, 62) <= sub_wire9(62); + sub_wire2(8, 63) <= sub_wire9(63); + sub_wire2(8, 64) <= sub_wire9(64); + sub_wire2(8, 65) <= sub_wire9(65); + sub_wire2(8, 66) <= sub_wire9(66); + sub_wire2(8, 67) <= sub_wire9(67); + sub_wire2(8, 68) <= sub_wire9(68); + sub_wire2(8, 69) <= sub_wire9(69); + sub_wire2(8, 70) <= sub_wire9(70); + sub_wire2(8, 71) <= sub_wire9(71); + sub_wire2(8, 72) <= sub_wire9(72); + sub_wire2(8, 73) <= sub_wire9(73); + sub_wire2(8, 74) <= sub_wire9(74); + sub_wire2(8, 75) <= sub_wire9(75); + sub_wire2(8, 76) <= sub_wire9(76); + sub_wire2(8, 77) <= sub_wire9(77); + sub_wire2(8, 78) <= sub_wire9(78); + sub_wire2(8, 79) <= sub_wire9(79); + sub_wire2(8, 80) <= sub_wire9(80); + sub_wire2(8, 81) <= sub_wire9(81); + sub_wire2(8, 82) <= sub_wire9(82); + sub_wire2(8, 83) <= sub_wire9(83); + sub_wire2(8, 84) <= sub_wire9(84); + sub_wire2(8, 85) <= sub_wire9(85); + sub_wire2(8, 86) <= sub_wire9(86); + sub_wire2(8, 87) <= sub_wire9(87); + sub_wire2(8, 88) <= sub_wire9(88); + sub_wire2(8, 89) <= sub_wire9(89); + sub_wire2(8, 90) <= sub_wire9(90); + sub_wire2(8, 91) <= sub_wire9(91); + sub_wire2(8, 92) <= sub_wire9(92); + sub_wire2(8, 93) <= sub_wire9(93); + sub_wire2(8, 94) <= sub_wire9(94); + sub_wire2(8, 95) <= sub_wire9(95); + sub_wire2(8, 96) <= sub_wire9(96); + sub_wire2(8, 97) <= sub_wire9(97); + sub_wire2(8, 98) <= sub_wire9(98); + sub_wire2(8, 99) <= sub_wire9(99); + sub_wire2(8, 100) <= sub_wire9(100); + sub_wire2(8, 101) <= sub_wire9(101); + sub_wire2(8, 102) <= sub_wire9(102); + sub_wire2(8, 103) <= sub_wire9(103); + sub_wire2(8, 104) <= sub_wire9(104); + sub_wire2(8, 105) <= sub_wire9(105); + sub_wire2(8, 106) <= sub_wire9(106); + sub_wire2(8, 107) <= sub_wire9(107); + sub_wire2(8, 108) <= sub_wire9(108); + sub_wire2(8, 109) <= sub_wire9(109); + sub_wire2(8, 110) <= sub_wire9(110); + sub_wire2(8, 111) <= sub_wire9(111); + sub_wire2(8, 112) <= sub_wire9(112); + sub_wire2(8, 113) <= sub_wire9(113); + sub_wire2(8, 114) <= sub_wire9(114); + sub_wire2(8, 115) <= sub_wire9(115); + sub_wire2(8, 116) <= sub_wire9(116); + sub_wire2(8, 117) <= sub_wire9(117); + sub_wire2(8, 118) <= sub_wire9(118); + sub_wire2(8, 119) <= sub_wire9(119); + sub_wire2(8, 120) <= sub_wire9(120); + sub_wire2(8, 121) <= sub_wire9(121); + sub_wire2(8, 122) <= sub_wire9(122); + sub_wire2(8, 123) <= sub_wire9(123); + sub_wire2(8, 124) <= sub_wire9(124); + sub_wire2(8, 125) <= sub_wire9(125); + sub_wire2(8, 126) <= sub_wire9(126); + sub_wire2(8, 127) <= sub_wire9(127); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(7, 8) <= sub_wire10(8); + sub_wire2(7, 9) <= sub_wire10(9); + sub_wire2(7, 10) <= sub_wire10(10); + sub_wire2(7, 11) <= sub_wire10(11); + sub_wire2(7, 12) <= sub_wire10(12); + sub_wire2(7, 13) <= sub_wire10(13); + sub_wire2(7, 14) <= sub_wire10(14); + sub_wire2(7, 15) <= sub_wire10(15); + sub_wire2(7, 16) <= sub_wire10(16); + sub_wire2(7, 17) <= sub_wire10(17); + sub_wire2(7, 18) <= sub_wire10(18); + sub_wire2(7, 19) <= sub_wire10(19); + sub_wire2(7, 20) <= sub_wire10(20); + sub_wire2(7, 21) <= sub_wire10(21); + sub_wire2(7, 22) <= sub_wire10(22); + sub_wire2(7, 23) <= sub_wire10(23); + sub_wire2(7, 24) <= sub_wire10(24); + sub_wire2(7, 25) <= sub_wire10(25); + sub_wire2(7, 26) <= sub_wire10(26); + sub_wire2(7, 27) <= sub_wire10(27); + sub_wire2(7, 28) <= sub_wire10(28); + sub_wire2(7, 29) <= sub_wire10(29); + sub_wire2(7, 30) <= sub_wire10(30); + sub_wire2(7, 31) <= sub_wire10(31); + sub_wire2(7, 32) <= sub_wire10(32); + sub_wire2(7, 33) <= sub_wire10(33); + sub_wire2(7, 34) <= sub_wire10(34); + sub_wire2(7, 35) <= sub_wire10(35); + sub_wire2(7, 36) <= sub_wire10(36); + sub_wire2(7, 37) <= sub_wire10(37); + sub_wire2(7, 38) <= sub_wire10(38); + sub_wire2(7, 39) <= sub_wire10(39); + sub_wire2(7, 40) <= sub_wire10(40); + sub_wire2(7, 41) <= sub_wire10(41); + sub_wire2(7, 42) <= sub_wire10(42); + sub_wire2(7, 43) <= sub_wire10(43); + sub_wire2(7, 44) <= sub_wire10(44); + sub_wire2(7, 45) <= sub_wire10(45); + sub_wire2(7, 46) <= sub_wire10(46); + sub_wire2(7, 47) <= sub_wire10(47); + sub_wire2(7, 48) <= sub_wire10(48); + sub_wire2(7, 49) <= sub_wire10(49); + sub_wire2(7, 50) <= sub_wire10(50); + sub_wire2(7, 51) <= sub_wire10(51); + sub_wire2(7, 52) <= sub_wire10(52); + sub_wire2(7, 53) <= sub_wire10(53); + sub_wire2(7, 54) <= sub_wire10(54); + sub_wire2(7, 55) <= sub_wire10(55); + sub_wire2(7, 56) <= sub_wire10(56); + sub_wire2(7, 57) <= sub_wire10(57); + sub_wire2(7, 58) <= sub_wire10(58); + sub_wire2(7, 59) <= sub_wire10(59); + sub_wire2(7, 60) <= sub_wire10(60); + sub_wire2(7, 61) <= sub_wire10(61); + sub_wire2(7, 62) <= sub_wire10(62); + sub_wire2(7, 63) <= sub_wire10(63); + sub_wire2(7, 64) <= sub_wire10(64); + sub_wire2(7, 65) <= sub_wire10(65); + sub_wire2(7, 66) <= sub_wire10(66); + sub_wire2(7, 67) <= sub_wire10(67); + sub_wire2(7, 68) <= sub_wire10(68); + sub_wire2(7, 69) <= sub_wire10(69); + sub_wire2(7, 70) <= sub_wire10(70); + sub_wire2(7, 71) <= sub_wire10(71); + sub_wire2(7, 72) <= sub_wire10(72); + sub_wire2(7, 73) <= sub_wire10(73); + sub_wire2(7, 74) <= sub_wire10(74); + sub_wire2(7, 75) <= sub_wire10(75); + sub_wire2(7, 76) <= sub_wire10(76); + sub_wire2(7, 77) <= sub_wire10(77); + sub_wire2(7, 78) <= sub_wire10(78); + sub_wire2(7, 79) <= sub_wire10(79); + sub_wire2(7, 80) <= sub_wire10(80); + sub_wire2(7, 81) <= sub_wire10(81); + sub_wire2(7, 82) <= sub_wire10(82); + sub_wire2(7, 83) <= sub_wire10(83); + sub_wire2(7, 84) <= sub_wire10(84); + sub_wire2(7, 85) <= sub_wire10(85); + sub_wire2(7, 86) <= sub_wire10(86); + sub_wire2(7, 87) <= sub_wire10(87); + sub_wire2(7, 88) <= sub_wire10(88); + sub_wire2(7, 89) <= sub_wire10(89); + sub_wire2(7, 90) <= sub_wire10(90); + sub_wire2(7, 91) <= sub_wire10(91); + sub_wire2(7, 92) <= sub_wire10(92); + sub_wire2(7, 93) <= sub_wire10(93); + sub_wire2(7, 94) <= sub_wire10(94); + sub_wire2(7, 95) <= sub_wire10(95); + sub_wire2(7, 96) <= sub_wire10(96); + sub_wire2(7, 97) <= sub_wire10(97); + sub_wire2(7, 98) <= sub_wire10(98); + sub_wire2(7, 99) <= sub_wire10(99); + sub_wire2(7, 100) <= sub_wire10(100); + sub_wire2(7, 101) <= sub_wire10(101); + sub_wire2(7, 102) <= sub_wire10(102); + sub_wire2(7, 103) <= sub_wire10(103); + sub_wire2(7, 104) <= sub_wire10(104); + sub_wire2(7, 105) <= sub_wire10(105); + sub_wire2(7, 106) <= sub_wire10(106); + sub_wire2(7, 107) <= sub_wire10(107); + sub_wire2(7, 108) <= sub_wire10(108); + sub_wire2(7, 109) <= sub_wire10(109); + sub_wire2(7, 110) <= sub_wire10(110); + sub_wire2(7, 111) <= sub_wire10(111); + sub_wire2(7, 112) <= sub_wire10(112); + sub_wire2(7, 113) <= sub_wire10(113); + sub_wire2(7, 114) <= sub_wire10(114); + sub_wire2(7, 115) <= sub_wire10(115); + sub_wire2(7, 116) <= sub_wire10(116); + sub_wire2(7, 117) <= sub_wire10(117); + sub_wire2(7, 118) <= sub_wire10(118); + sub_wire2(7, 119) <= sub_wire10(119); + sub_wire2(7, 120) <= sub_wire10(120); + sub_wire2(7, 121) <= sub_wire10(121); + sub_wire2(7, 122) <= sub_wire10(122); + sub_wire2(7, 123) <= sub_wire10(123); + sub_wire2(7, 124) <= sub_wire10(124); + sub_wire2(7, 125) <= sub_wire10(125); + sub_wire2(7, 126) <= sub_wire10(126); + sub_wire2(7, 127) <= sub_wire10(127); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(6, 8) <= sub_wire11(8); + sub_wire2(6, 9) <= sub_wire11(9); + sub_wire2(6, 10) <= sub_wire11(10); + sub_wire2(6, 11) <= sub_wire11(11); + sub_wire2(6, 12) <= sub_wire11(12); + sub_wire2(6, 13) <= sub_wire11(13); + sub_wire2(6, 14) <= sub_wire11(14); + sub_wire2(6, 15) <= sub_wire11(15); + sub_wire2(6, 16) <= sub_wire11(16); + sub_wire2(6, 17) <= sub_wire11(17); + sub_wire2(6, 18) <= sub_wire11(18); + sub_wire2(6, 19) <= sub_wire11(19); + sub_wire2(6, 20) <= sub_wire11(20); + sub_wire2(6, 21) <= sub_wire11(21); + sub_wire2(6, 22) <= sub_wire11(22); + sub_wire2(6, 23) <= sub_wire11(23); + sub_wire2(6, 24) <= sub_wire11(24); + sub_wire2(6, 25) <= sub_wire11(25); + sub_wire2(6, 26) <= sub_wire11(26); + sub_wire2(6, 27) <= sub_wire11(27); + sub_wire2(6, 28) <= sub_wire11(28); + sub_wire2(6, 29) <= sub_wire11(29); + sub_wire2(6, 30) <= sub_wire11(30); + sub_wire2(6, 31) <= sub_wire11(31); + sub_wire2(6, 32) <= sub_wire11(32); + sub_wire2(6, 33) <= sub_wire11(33); + sub_wire2(6, 34) <= sub_wire11(34); + sub_wire2(6, 35) <= sub_wire11(35); + sub_wire2(6, 36) <= sub_wire11(36); + sub_wire2(6, 37) <= sub_wire11(37); + sub_wire2(6, 38) <= sub_wire11(38); + sub_wire2(6, 39) <= sub_wire11(39); + sub_wire2(6, 40) <= sub_wire11(40); + sub_wire2(6, 41) <= sub_wire11(41); + sub_wire2(6, 42) <= sub_wire11(42); + sub_wire2(6, 43) <= sub_wire11(43); + sub_wire2(6, 44) <= sub_wire11(44); + sub_wire2(6, 45) <= sub_wire11(45); + sub_wire2(6, 46) <= sub_wire11(46); + sub_wire2(6, 47) <= sub_wire11(47); + sub_wire2(6, 48) <= sub_wire11(48); + sub_wire2(6, 49) <= sub_wire11(49); + sub_wire2(6, 50) <= sub_wire11(50); + sub_wire2(6, 51) <= sub_wire11(51); + sub_wire2(6, 52) <= sub_wire11(52); + sub_wire2(6, 53) <= sub_wire11(53); + sub_wire2(6, 54) <= sub_wire11(54); + sub_wire2(6, 55) <= sub_wire11(55); + sub_wire2(6, 56) <= sub_wire11(56); + sub_wire2(6, 57) <= sub_wire11(57); + sub_wire2(6, 58) <= sub_wire11(58); + sub_wire2(6, 59) <= sub_wire11(59); + sub_wire2(6, 60) <= sub_wire11(60); + sub_wire2(6, 61) <= sub_wire11(61); + sub_wire2(6, 62) <= sub_wire11(62); + sub_wire2(6, 63) <= sub_wire11(63); + sub_wire2(6, 64) <= sub_wire11(64); + sub_wire2(6, 65) <= sub_wire11(65); + sub_wire2(6, 66) <= sub_wire11(66); + sub_wire2(6, 67) <= sub_wire11(67); + sub_wire2(6, 68) <= sub_wire11(68); + sub_wire2(6, 69) <= sub_wire11(69); + sub_wire2(6, 70) <= sub_wire11(70); + sub_wire2(6, 71) <= sub_wire11(71); + sub_wire2(6, 72) <= sub_wire11(72); + sub_wire2(6, 73) <= sub_wire11(73); + sub_wire2(6, 74) <= sub_wire11(74); + sub_wire2(6, 75) <= sub_wire11(75); + sub_wire2(6, 76) <= sub_wire11(76); + sub_wire2(6, 77) <= sub_wire11(77); + sub_wire2(6, 78) <= sub_wire11(78); + sub_wire2(6, 79) <= sub_wire11(79); + sub_wire2(6, 80) <= sub_wire11(80); + sub_wire2(6, 81) <= sub_wire11(81); + sub_wire2(6, 82) <= sub_wire11(82); + sub_wire2(6, 83) <= sub_wire11(83); + sub_wire2(6, 84) <= sub_wire11(84); + sub_wire2(6, 85) <= sub_wire11(85); + sub_wire2(6, 86) <= sub_wire11(86); + sub_wire2(6, 87) <= sub_wire11(87); + sub_wire2(6, 88) <= sub_wire11(88); + sub_wire2(6, 89) <= sub_wire11(89); + sub_wire2(6, 90) <= sub_wire11(90); + sub_wire2(6, 91) <= sub_wire11(91); + sub_wire2(6, 92) <= sub_wire11(92); + sub_wire2(6, 93) <= sub_wire11(93); + sub_wire2(6, 94) <= sub_wire11(94); + sub_wire2(6, 95) <= sub_wire11(95); + sub_wire2(6, 96) <= sub_wire11(96); + sub_wire2(6, 97) <= sub_wire11(97); + sub_wire2(6, 98) <= sub_wire11(98); + sub_wire2(6, 99) <= sub_wire11(99); + sub_wire2(6, 100) <= sub_wire11(100); + sub_wire2(6, 101) <= sub_wire11(101); + sub_wire2(6, 102) <= sub_wire11(102); + sub_wire2(6, 103) <= sub_wire11(103); + sub_wire2(6, 104) <= sub_wire11(104); + sub_wire2(6, 105) <= sub_wire11(105); + sub_wire2(6, 106) <= sub_wire11(106); + sub_wire2(6, 107) <= sub_wire11(107); + sub_wire2(6, 108) <= sub_wire11(108); + sub_wire2(6, 109) <= sub_wire11(109); + sub_wire2(6, 110) <= sub_wire11(110); + sub_wire2(6, 111) <= sub_wire11(111); + sub_wire2(6, 112) <= sub_wire11(112); + sub_wire2(6, 113) <= sub_wire11(113); + sub_wire2(6, 114) <= sub_wire11(114); + sub_wire2(6, 115) <= sub_wire11(115); + sub_wire2(6, 116) <= sub_wire11(116); + sub_wire2(6, 117) <= sub_wire11(117); + sub_wire2(6, 118) <= sub_wire11(118); + sub_wire2(6, 119) <= sub_wire11(119); + sub_wire2(6, 120) <= sub_wire11(120); + sub_wire2(6, 121) <= sub_wire11(121); + sub_wire2(6, 122) <= sub_wire11(122); + sub_wire2(6, 123) <= sub_wire11(123); + sub_wire2(6, 124) <= sub_wire11(124); + sub_wire2(6, 125) <= sub_wire11(125); + sub_wire2(6, 126) <= sub_wire11(126); + sub_wire2(6, 127) <= sub_wire11(127); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(5, 8) <= sub_wire12(8); + sub_wire2(5, 9) <= sub_wire12(9); + sub_wire2(5, 10) <= sub_wire12(10); + sub_wire2(5, 11) <= sub_wire12(11); + sub_wire2(5, 12) <= sub_wire12(12); + sub_wire2(5, 13) <= sub_wire12(13); + sub_wire2(5, 14) <= sub_wire12(14); + sub_wire2(5, 15) <= sub_wire12(15); + sub_wire2(5, 16) <= sub_wire12(16); + sub_wire2(5, 17) <= sub_wire12(17); + sub_wire2(5, 18) <= sub_wire12(18); + sub_wire2(5, 19) <= sub_wire12(19); + sub_wire2(5, 20) <= sub_wire12(20); + sub_wire2(5, 21) <= sub_wire12(21); + sub_wire2(5, 22) <= sub_wire12(22); + sub_wire2(5, 23) <= sub_wire12(23); + sub_wire2(5, 24) <= sub_wire12(24); + sub_wire2(5, 25) <= sub_wire12(25); + sub_wire2(5, 26) <= sub_wire12(26); + sub_wire2(5, 27) <= sub_wire12(27); + sub_wire2(5, 28) <= sub_wire12(28); + sub_wire2(5, 29) <= sub_wire12(29); + sub_wire2(5, 30) <= sub_wire12(30); + sub_wire2(5, 31) <= sub_wire12(31); + sub_wire2(5, 32) <= sub_wire12(32); + sub_wire2(5, 33) <= sub_wire12(33); + sub_wire2(5, 34) <= sub_wire12(34); + sub_wire2(5, 35) <= sub_wire12(35); + sub_wire2(5, 36) <= sub_wire12(36); + sub_wire2(5, 37) <= sub_wire12(37); + sub_wire2(5, 38) <= sub_wire12(38); + sub_wire2(5, 39) <= sub_wire12(39); + sub_wire2(5, 40) <= sub_wire12(40); + sub_wire2(5, 41) <= sub_wire12(41); + sub_wire2(5, 42) <= sub_wire12(42); + sub_wire2(5, 43) <= sub_wire12(43); + sub_wire2(5, 44) <= sub_wire12(44); + sub_wire2(5, 45) <= sub_wire12(45); + sub_wire2(5, 46) <= sub_wire12(46); + sub_wire2(5, 47) <= sub_wire12(47); + sub_wire2(5, 48) <= sub_wire12(48); + sub_wire2(5, 49) <= sub_wire12(49); + sub_wire2(5, 50) <= sub_wire12(50); + sub_wire2(5, 51) <= sub_wire12(51); + sub_wire2(5, 52) <= sub_wire12(52); + sub_wire2(5, 53) <= sub_wire12(53); + sub_wire2(5, 54) <= sub_wire12(54); + sub_wire2(5, 55) <= sub_wire12(55); + sub_wire2(5, 56) <= sub_wire12(56); + sub_wire2(5, 57) <= sub_wire12(57); + sub_wire2(5, 58) <= sub_wire12(58); + sub_wire2(5, 59) <= sub_wire12(59); + sub_wire2(5, 60) <= sub_wire12(60); + sub_wire2(5, 61) <= sub_wire12(61); + sub_wire2(5, 62) <= sub_wire12(62); + sub_wire2(5, 63) <= sub_wire12(63); + sub_wire2(5, 64) <= sub_wire12(64); + sub_wire2(5, 65) <= sub_wire12(65); + sub_wire2(5, 66) <= sub_wire12(66); + sub_wire2(5, 67) <= sub_wire12(67); + sub_wire2(5, 68) <= sub_wire12(68); + sub_wire2(5, 69) <= sub_wire12(69); + sub_wire2(5, 70) <= sub_wire12(70); + sub_wire2(5, 71) <= sub_wire12(71); + sub_wire2(5, 72) <= sub_wire12(72); + sub_wire2(5, 73) <= sub_wire12(73); + sub_wire2(5, 74) <= sub_wire12(74); + sub_wire2(5, 75) <= sub_wire12(75); + sub_wire2(5, 76) <= sub_wire12(76); + sub_wire2(5, 77) <= sub_wire12(77); + sub_wire2(5, 78) <= sub_wire12(78); + sub_wire2(5, 79) <= sub_wire12(79); + sub_wire2(5, 80) <= sub_wire12(80); + sub_wire2(5, 81) <= sub_wire12(81); + sub_wire2(5, 82) <= sub_wire12(82); + sub_wire2(5, 83) <= sub_wire12(83); + sub_wire2(5, 84) <= sub_wire12(84); + sub_wire2(5, 85) <= sub_wire12(85); + sub_wire2(5, 86) <= sub_wire12(86); + sub_wire2(5, 87) <= sub_wire12(87); + sub_wire2(5, 88) <= sub_wire12(88); + sub_wire2(5, 89) <= sub_wire12(89); + sub_wire2(5, 90) <= sub_wire12(90); + sub_wire2(5, 91) <= sub_wire12(91); + sub_wire2(5, 92) <= sub_wire12(92); + sub_wire2(5, 93) <= sub_wire12(93); + sub_wire2(5, 94) <= sub_wire12(94); + sub_wire2(5, 95) <= sub_wire12(95); + sub_wire2(5, 96) <= sub_wire12(96); + sub_wire2(5, 97) <= sub_wire12(97); + sub_wire2(5, 98) <= sub_wire12(98); + sub_wire2(5, 99) <= sub_wire12(99); + sub_wire2(5, 100) <= sub_wire12(100); + sub_wire2(5, 101) <= sub_wire12(101); + sub_wire2(5, 102) <= sub_wire12(102); + sub_wire2(5, 103) <= sub_wire12(103); + sub_wire2(5, 104) <= sub_wire12(104); + sub_wire2(5, 105) <= sub_wire12(105); + sub_wire2(5, 106) <= sub_wire12(106); + sub_wire2(5, 107) <= sub_wire12(107); + sub_wire2(5, 108) <= sub_wire12(108); + sub_wire2(5, 109) <= sub_wire12(109); + sub_wire2(5, 110) <= sub_wire12(110); + sub_wire2(5, 111) <= sub_wire12(111); + sub_wire2(5, 112) <= sub_wire12(112); + sub_wire2(5, 113) <= sub_wire12(113); + sub_wire2(5, 114) <= sub_wire12(114); + sub_wire2(5, 115) <= sub_wire12(115); + sub_wire2(5, 116) <= sub_wire12(116); + sub_wire2(5, 117) <= sub_wire12(117); + sub_wire2(5, 118) <= sub_wire12(118); + sub_wire2(5, 119) <= sub_wire12(119); + sub_wire2(5, 120) <= sub_wire12(120); + sub_wire2(5, 121) <= sub_wire12(121); + sub_wire2(5, 122) <= sub_wire12(122); + sub_wire2(5, 123) <= sub_wire12(123); + sub_wire2(5, 124) <= sub_wire12(124); + sub_wire2(5, 125) <= sub_wire12(125); + sub_wire2(5, 126) <= sub_wire12(126); + sub_wire2(5, 127) <= sub_wire12(127); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(4, 8) <= sub_wire13(8); + sub_wire2(4, 9) <= sub_wire13(9); + sub_wire2(4, 10) <= sub_wire13(10); + sub_wire2(4, 11) <= sub_wire13(11); + sub_wire2(4, 12) <= sub_wire13(12); + sub_wire2(4, 13) <= sub_wire13(13); + sub_wire2(4, 14) <= sub_wire13(14); + sub_wire2(4, 15) <= sub_wire13(15); + sub_wire2(4, 16) <= sub_wire13(16); + sub_wire2(4, 17) <= sub_wire13(17); + sub_wire2(4, 18) <= sub_wire13(18); + sub_wire2(4, 19) <= sub_wire13(19); + sub_wire2(4, 20) <= sub_wire13(20); + sub_wire2(4, 21) <= sub_wire13(21); + sub_wire2(4, 22) <= sub_wire13(22); + sub_wire2(4, 23) <= sub_wire13(23); + sub_wire2(4, 24) <= sub_wire13(24); + sub_wire2(4, 25) <= sub_wire13(25); + sub_wire2(4, 26) <= sub_wire13(26); + sub_wire2(4, 27) <= sub_wire13(27); + sub_wire2(4, 28) <= sub_wire13(28); + sub_wire2(4, 29) <= sub_wire13(29); + sub_wire2(4, 30) <= sub_wire13(30); + sub_wire2(4, 31) <= sub_wire13(31); + sub_wire2(4, 32) <= sub_wire13(32); + sub_wire2(4, 33) <= sub_wire13(33); + sub_wire2(4, 34) <= sub_wire13(34); + sub_wire2(4, 35) <= sub_wire13(35); + sub_wire2(4, 36) <= sub_wire13(36); + sub_wire2(4, 37) <= sub_wire13(37); + sub_wire2(4, 38) <= sub_wire13(38); + sub_wire2(4, 39) <= sub_wire13(39); + sub_wire2(4, 40) <= sub_wire13(40); + sub_wire2(4, 41) <= sub_wire13(41); + sub_wire2(4, 42) <= sub_wire13(42); + sub_wire2(4, 43) <= sub_wire13(43); + sub_wire2(4, 44) <= sub_wire13(44); + sub_wire2(4, 45) <= sub_wire13(45); + sub_wire2(4, 46) <= sub_wire13(46); + sub_wire2(4, 47) <= sub_wire13(47); + sub_wire2(4, 48) <= sub_wire13(48); + sub_wire2(4, 49) <= sub_wire13(49); + sub_wire2(4, 50) <= sub_wire13(50); + sub_wire2(4, 51) <= sub_wire13(51); + sub_wire2(4, 52) <= sub_wire13(52); + sub_wire2(4, 53) <= sub_wire13(53); + sub_wire2(4, 54) <= sub_wire13(54); + sub_wire2(4, 55) <= sub_wire13(55); + sub_wire2(4, 56) <= sub_wire13(56); + sub_wire2(4, 57) <= sub_wire13(57); + sub_wire2(4, 58) <= sub_wire13(58); + sub_wire2(4, 59) <= sub_wire13(59); + sub_wire2(4, 60) <= sub_wire13(60); + sub_wire2(4, 61) <= sub_wire13(61); + sub_wire2(4, 62) <= sub_wire13(62); + sub_wire2(4, 63) <= sub_wire13(63); + sub_wire2(4, 64) <= sub_wire13(64); + sub_wire2(4, 65) <= sub_wire13(65); + sub_wire2(4, 66) <= sub_wire13(66); + sub_wire2(4, 67) <= sub_wire13(67); + sub_wire2(4, 68) <= sub_wire13(68); + sub_wire2(4, 69) <= sub_wire13(69); + sub_wire2(4, 70) <= sub_wire13(70); + sub_wire2(4, 71) <= sub_wire13(71); + sub_wire2(4, 72) <= sub_wire13(72); + sub_wire2(4, 73) <= sub_wire13(73); + sub_wire2(4, 74) <= sub_wire13(74); + sub_wire2(4, 75) <= sub_wire13(75); + sub_wire2(4, 76) <= sub_wire13(76); + sub_wire2(4, 77) <= sub_wire13(77); + sub_wire2(4, 78) <= sub_wire13(78); + sub_wire2(4, 79) <= sub_wire13(79); + sub_wire2(4, 80) <= sub_wire13(80); + sub_wire2(4, 81) <= sub_wire13(81); + sub_wire2(4, 82) <= sub_wire13(82); + sub_wire2(4, 83) <= sub_wire13(83); + sub_wire2(4, 84) <= sub_wire13(84); + sub_wire2(4, 85) <= sub_wire13(85); + sub_wire2(4, 86) <= sub_wire13(86); + sub_wire2(4, 87) <= sub_wire13(87); + sub_wire2(4, 88) <= sub_wire13(88); + sub_wire2(4, 89) <= sub_wire13(89); + sub_wire2(4, 90) <= sub_wire13(90); + sub_wire2(4, 91) <= sub_wire13(91); + sub_wire2(4, 92) <= sub_wire13(92); + sub_wire2(4, 93) <= sub_wire13(93); + sub_wire2(4, 94) <= sub_wire13(94); + sub_wire2(4, 95) <= sub_wire13(95); + sub_wire2(4, 96) <= sub_wire13(96); + sub_wire2(4, 97) <= sub_wire13(97); + sub_wire2(4, 98) <= sub_wire13(98); + sub_wire2(4, 99) <= sub_wire13(99); + sub_wire2(4, 100) <= sub_wire13(100); + sub_wire2(4, 101) <= sub_wire13(101); + sub_wire2(4, 102) <= sub_wire13(102); + sub_wire2(4, 103) <= sub_wire13(103); + sub_wire2(4, 104) <= sub_wire13(104); + sub_wire2(4, 105) <= sub_wire13(105); + sub_wire2(4, 106) <= sub_wire13(106); + sub_wire2(4, 107) <= sub_wire13(107); + sub_wire2(4, 108) <= sub_wire13(108); + sub_wire2(4, 109) <= sub_wire13(109); + sub_wire2(4, 110) <= sub_wire13(110); + sub_wire2(4, 111) <= sub_wire13(111); + sub_wire2(4, 112) <= sub_wire13(112); + sub_wire2(4, 113) <= sub_wire13(113); + sub_wire2(4, 114) <= sub_wire13(114); + sub_wire2(4, 115) <= sub_wire13(115); + sub_wire2(4, 116) <= sub_wire13(116); + sub_wire2(4, 117) <= sub_wire13(117); + sub_wire2(4, 118) <= sub_wire13(118); + sub_wire2(4, 119) <= sub_wire13(119); + sub_wire2(4, 120) <= sub_wire13(120); + sub_wire2(4, 121) <= sub_wire13(121); + sub_wire2(4, 122) <= sub_wire13(122); + sub_wire2(4, 123) <= sub_wire13(123); + sub_wire2(4, 124) <= sub_wire13(124); + sub_wire2(4, 125) <= sub_wire13(125); + sub_wire2(4, 126) <= sub_wire13(126); + sub_wire2(4, 127) <= sub_wire13(127); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(3, 8) <= sub_wire14(8); + sub_wire2(3, 9) <= sub_wire14(9); + sub_wire2(3, 10) <= sub_wire14(10); + sub_wire2(3, 11) <= sub_wire14(11); + sub_wire2(3, 12) <= sub_wire14(12); + sub_wire2(3, 13) <= sub_wire14(13); + sub_wire2(3, 14) <= sub_wire14(14); + sub_wire2(3, 15) <= sub_wire14(15); + sub_wire2(3, 16) <= sub_wire14(16); + sub_wire2(3, 17) <= sub_wire14(17); + sub_wire2(3, 18) <= sub_wire14(18); + sub_wire2(3, 19) <= sub_wire14(19); + sub_wire2(3, 20) <= sub_wire14(20); + sub_wire2(3, 21) <= sub_wire14(21); + sub_wire2(3, 22) <= sub_wire14(22); + sub_wire2(3, 23) <= sub_wire14(23); + sub_wire2(3, 24) <= sub_wire14(24); + sub_wire2(3, 25) <= sub_wire14(25); + sub_wire2(3, 26) <= sub_wire14(26); + sub_wire2(3, 27) <= sub_wire14(27); + sub_wire2(3, 28) <= sub_wire14(28); + sub_wire2(3, 29) <= sub_wire14(29); + sub_wire2(3, 30) <= sub_wire14(30); + sub_wire2(3, 31) <= sub_wire14(31); + sub_wire2(3, 32) <= sub_wire14(32); + sub_wire2(3, 33) <= sub_wire14(33); + sub_wire2(3, 34) <= sub_wire14(34); + sub_wire2(3, 35) <= sub_wire14(35); + sub_wire2(3, 36) <= sub_wire14(36); + sub_wire2(3, 37) <= sub_wire14(37); + sub_wire2(3, 38) <= sub_wire14(38); + sub_wire2(3, 39) <= sub_wire14(39); + sub_wire2(3, 40) <= sub_wire14(40); + sub_wire2(3, 41) <= sub_wire14(41); + sub_wire2(3, 42) <= sub_wire14(42); + sub_wire2(3, 43) <= sub_wire14(43); + sub_wire2(3, 44) <= sub_wire14(44); + sub_wire2(3, 45) <= sub_wire14(45); + sub_wire2(3, 46) <= sub_wire14(46); + sub_wire2(3, 47) <= sub_wire14(47); + sub_wire2(3, 48) <= sub_wire14(48); + sub_wire2(3, 49) <= sub_wire14(49); + sub_wire2(3, 50) <= sub_wire14(50); + sub_wire2(3, 51) <= sub_wire14(51); + sub_wire2(3, 52) <= sub_wire14(52); + sub_wire2(3, 53) <= sub_wire14(53); + sub_wire2(3, 54) <= sub_wire14(54); + sub_wire2(3, 55) <= sub_wire14(55); + sub_wire2(3, 56) <= sub_wire14(56); + sub_wire2(3, 57) <= sub_wire14(57); + sub_wire2(3, 58) <= sub_wire14(58); + sub_wire2(3, 59) <= sub_wire14(59); + sub_wire2(3, 60) <= sub_wire14(60); + sub_wire2(3, 61) <= sub_wire14(61); + sub_wire2(3, 62) <= sub_wire14(62); + sub_wire2(3, 63) <= sub_wire14(63); + sub_wire2(3, 64) <= sub_wire14(64); + sub_wire2(3, 65) <= sub_wire14(65); + sub_wire2(3, 66) <= sub_wire14(66); + sub_wire2(3, 67) <= sub_wire14(67); + sub_wire2(3, 68) <= sub_wire14(68); + sub_wire2(3, 69) <= sub_wire14(69); + sub_wire2(3, 70) <= sub_wire14(70); + sub_wire2(3, 71) <= sub_wire14(71); + sub_wire2(3, 72) <= sub_wire14(72); + sub_wire2(3, 73) <= sub_wire14(73); + sub_wire2(3, 74) <= sub_wire14(74); + sub_wire2(3, 75) <= sub_wire14(75); + sub_wire2(3, 76) <= sub_wire14(76); + sub_wire2(3, 77) <= sub_wire14(77); + sub_wire2(3, 78) <= sub_wire14(78); + sub_wire2(3, 79) <= sub_wire14(79); + sub_wire2(3, 80) <= sub_wire14(80); + sub_wire2(3, 81) <= sub_wire14(81); + sub_wire2(3, 82) <= sub_wire14(82); + sub_wire2(3, 83) <= sub_wire14(83); + sub_wire2(3, 84) <= sub_wire14(84); + sub_wire2(3, 85) <= sub_wire14(85); + sub_wire2(3, 86) <= sub_wire14(86); + sub_wire2(3, 87) <= sub_wire14(87); + sub_wire2(3, 88) <= sub_wire14(88); + sub_wire2(3, 89) <= sub_wire14(89); + sub_wire2(3, 90) <= sub_wire14(90); + sub_wire2(3, 91) <= sub_wire14(91); + sub_wire2(3, 92) <= sub_wire14(92); + sub_wire2(3, 93) <= sub_wire14(93); + sub_wire2(3, 94) <= sub_wire14(94); + sub_wire2(3, 95) <= sub_wire14(95); + sub_wire2(3, 96) <= sub_wire14(96); + sub_wire2(3, 97) <= sub_wire14(97); + sub_wire2(3, 98) <= sub_wire14(98); + sub_wire2(3, 99) <= sub_wire14(99); + sub_wire2(3, 100) <= sub_wire14(100); + sub_wire2(3, 101) <= sub_wire14(101); + sub_wire2(3, 102) <= sub_wire14(102); + sub_wire2(3, 103) <= sub_wire14(103); + sub_wire2(3, 104) <= sub_wire14(104); + sub_wire2(3, 105) <= sub_wire14(105); + sub_wire2(3, 106) <= sub_wire14(106); + sub_wire2(3, 107) <= sub_wire14(107); + sub_wire2(3, 108) <= sub_wire14(108); + sub_wire2(3, 109) <= sub_wire14(109); + sub_wire2(3, 110) <= sub_wire14(110); + sub_wire2(3, 111) <= sub_wire14(111); + sub_wire2(3, 112) <= sub_wire14(112); + sub_wire2(3, 113) <= sub_wire14(113); + sub_wire2(3, 114) <= sub_wire14(114); + sub_wire2(3, 115) <= sub_wire14(115); + sub_wire2(3, 116) <= sub_wire14(116); + sub_wire2(3, 117) <= sub_wire14(117); + sub_wire2(3, 118) <= sub_wire14(118); + sub_wire2(3, 119) <= sub_wire14(119); + sub_wire2(3, 120) <= sub_wire14(120); + sub_wire2(3, 121) <= sub_wire14(121); + sub_wire2(3, 122) <= sub_wire14(122); + sub_wire2(3, 123) <= sub_wire14(123); + sub_wire2(3, 124) <= sub_wire14(124); + sub_wire2(3, 125) <= sub_wire14(125); + sub_wire2(3, 126) <= sub_wire14(126); + sub_wire2(3, 127) <= sub_wire14(127); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(2, 8) <= sub_wire15(8); + sub_wire2(2, 9) <= sub_wire15(9); + sub_wire2(2, 10) <= sub_wire15(10); + sub_wire2(2, 11) <= sub_wire15(11); + sub_wire2(2, 12) <= sub_wire15(12); + sub_wire2(2, 13) <= sub_wire15(13); + sub_wire2(2, 14) <= sub_wire15(14); + sub_wire2(2, 15) <= sub_wire15(15); + sub_wire2(2, 16) <= sub_wire15(16); + sub_wire2(2, 17) <= sub_wire15(17); + sub_wire2(2, 18) <= sub_wire15(18); + sub_wire2(2, 19) <= sub_wire15(19); + sub_wire2(2, 20) <= sub_wire15(20); + sub_wire2(2, 21) <= sub_wire15(21); + sub_wire2(2, 22) <= sub_wire15(22); + sub_wire2(2, 23) <= sub_wire15(23); + sub_wire2(2, 24) <= sub_wire15(24); + sub_wire2(2, 25) <= sub_wire15(25); + sub_wire2(2, 26) <= sub_wire15(26); + sub_wire2(2, 27) <= sub_wire15(27); + sub_wire2(2, 28) <= sub_wire15(28); + sub_wire2(2, 29) <= sub_wire15(29); + sub_wire2(2, 30) <= sub_wire15(30); + sub_wire2(2, 31) <= sub_wire15(31); + sub_wire2(2, 32) <= sub_wire15(32); + sub_wire2(2, 33) <= sub_wire15(33); + sub_wire2(2, 34) <= sub_wire15(34); + sub_wire2(2, 35) <= sub_wire15(35); + sub_wire2(2, 36) <= sub_wire15(36); + sub_wire2(2, 37) <= sub_wire15(37); + sub_wire2(2, 38) <= sub_wire15(38); + sub_wire2(2, 39) <= sub_wire15(39); + sub_wire2(2, 40) <= sub_wire15(40); + sub_wire2(2, 41) <= sub_wire15(41); + sub_wire2(2, 42) <= sub_wire15(42); + sub_wire2(2, 43) <= sub_wire15(43); + sub_wire2(2, 44) <= sub_wire15(44); + sub_wire2(2, 45) <= sub_wire15(45); + sub_wire2(2, 46) <= sub_wire15(46); + sub_wire2(2, 47) <= sub_wire15(47); + sub_wire2(2, 48) <= sub_wire15(48); + sub_wire2(2, 49) <= sub_wire15(49); + sub_wire2(2, 50) <= sub_wire15(50); + sub_wire2(2, 51) <= sub_wire15(51); + sub_wire2(2, 52) <= sub_wire15(52); + sub_wire2(2, 53) <= sub_wire15(53); + sub_wire2(2, 54) <= sub_wire15(54); + sub_wire2(2, 55) <= sub_wire15(55); + sub_wire2(2, 56) <= sub_wire15(56); + sub_wire2(2, 57) <= sub_wire15(57); + sub_wire2(2, 58) <= sub_wire15(58); + sub_wire2(2, 59) <= sub_wire15(59); + sub_wire2(2, 60) <= sub_wire15(60); + sub_wire2(2, 61) <= sub_wire15(61); + sub_wire2(2, 62) <= sub_wire15(62); + sub_wire2(2, 63) <= sub_wire15(63); + sub_wire2(2, 64) <= sub_wire15(64); + sub_wire2(2, 65) <= sub_wire15(65); + sub_wire2(2, 66) <= sub_wire15(66); + sub_wire2(2, 67) <= sub_wire15(67); + sub_wire2(2, 68) <= sub_wire15(68); + sub_wire2(2, 69) <= sub_wire15(69); + sub_wire2(2, 70) <= sub_wire15(70); + sub_wire2(2, 71) <= sub_wire15(71); + sub_wire2(2, 72) <= sub_wire15(72); + sub_wire2(2, 73) <= sub_wire15(73); + sub_wire2(2, 74) <= sub_wire15(74); + sub_wire2(2, 75) <= sub_wire15(75); + sub_wire2(2, 76) <= sub_wire15(76); + sub_wire2(2, 77) <= sub_wire15(77); + sub_wire2(2, 78) <= sub_wire15(78); + sub_wire2(2, 79) <= sub_wire15(79); + sub_wire2(2, 80) <= sub_wire15(80); + sub_wire2(2, 81) <= sub_wire15(81); + sub_wire2(2, 82) <= sub_wire15(82); + sub_wire2(2, 83) <= sub_wire15(83); + sub_wire2(2, 84) <= sub_wire15(84); + sub_wire2(2, 85) <= sub_wire15(85); + sub_wire2(2, 86) <= sub_wire15(86); + sub_wire2(2, 87) <= sub_wire15(87); + sub_wire2(2, 88) <= sub_wire15(88); + sub_wire2(2, 89) <= sub_wire15(89); + sub_wire2(2, 90) <= sub_wire15(90); + sub_wire2(2, 91) <= sub_wire15(91); + sub_wire2(2, 92) <= sub_wire15(92); + sub_wire2(2, 93) <= sub_wire15(93); + sub_wire2(2, 94) <= sub_wire15(94); + sub_wire2(2, 95) <= sub_wire15(95); + sub_wire2(2, 96) <= sub_wire15(96); + sub_wire2(2, 97) <= sub_wire15(97); + sub_wire2(2, 98) <= sub_wire15(98); + sub_wire2(2, 99) <= sub_wire15(99); + sub_wire2(2, 100) <= sub_wire15(100); + sub_wire2(2, 101) <= sub_wire15(101); + sub_wire2(2, 102) <= sub_wire15(102); + sub_wire2(2, 103) <= sub_wire15(103); + sub_wire2(2, 104) <= sub_wire15(104); + sub_wire2(2, 105) <= sub_wire15(105); + sub_wire2(2, 106) <= sub_wire15(106); + sub_wire2(2, 107) <= sub_wire15(107); + sub_wire2(2, 108) <= sub_wire15(108); + sub_wire2(2, 109) <= sub_wire15(109); + sub_wire2(2, 110) <= sub_wire15(110); + sub_wire2(2, 111) <= sub_wire15(111); + sub_wire2(2, 112) <= sub_wire15(112); + sub_wire2(2, 113) <= sub_wire15(113); + sub_wire2(2, 114) <= sub_wire15(114); + sub_wire2(2, 115) <= sub_wire15(115); + sub_wire2(2, 116) <= sub_wire15(116); + sub_wire2(2, 117) <= sub_wire15(117); + sub_wire2(2, 118) <= sub_wire15(118); + sub_wire2(2, 119) <= sub_wire15(119); + sub_wire2(2, 120) <= sub_wire15(120); + sub_wire2(2, 121) <= sub_wire15(121); + sub_wire2(2, 122) <= sub_wire15(122); + sub_wire2(2, 123) <= sub_wire15(123); + sub_wire2(2, 124) <= sub_wire15(124); + sub_wire2(2, 125) <= sub_wire15(125); + sub_wire2(2, 126) <= sub_wire15(126); + sub_wire2(2, 127) <= sub_wire15(127); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(1, 8) <= sub_wire16(8); + sub_wire2(1, 9) <= sub_wire16(9); + sub_wire2(1, 10) <= sub_wire16(10); + sub_wire2(1, 11) <= sub_wire16(11); + sub_wire2(1, 12) <= sub_wire16(12); + sub_wire2(1, 13) <= sub_wire16(13); + sub_wire2(1, 14) <= sub_wire16(14); + sub_wire2(1, 15) <= sub_wire16(15); + sub_wire2(1, 16) <= sub_wire16(16); + sub_wire2(1, 17) <= sub_wire16(17); + sub_wire2(1, 18) <= sub_wire16(18); + sub_wire2(1, 19) <= sub_wire16(19); + sub_wire2(1, 20) <= sub_wire16(20); + sub_wire2(1, 21) <= sub_wire16(21); + sub_wire2(1, 22) <= sub_wire16(22); + sub_wire2(1, 23) <= sub_wire16(23); + sub_wire2(1, 24) <= sub_wire16(24); + sub_wire2(1, 25) <= sub_wire16(25); + sub_wire2(1, 26) <= sub_wire16(26); + sub_wire2(1, 27) <= sub_wire16(27); + sub_wire2(1, 28) <= sub_wire16(28); + sub_wire2(1, 29) <= sub_wire16(29); + sub_wire2(1, 30) <= sub_wire16(30); + sub_wire2(1, 31) <= sub_wire16(31); + sub_wire2(1, 32) <= sub_wire16(32); + sub_wire2(1, 33) <= sub_wire16(33); + sub_wire2(1, 34) <= sub_wire16(34); + sub_wire2(1, 35) <= sub_wire16(35); + sub_wire2(1, 36) <= sub_wire16(36); + sub_wire2(1, 37) <= sub_wire16(37); + sub_wire2(1, 38) <= sub_wire16(38); + sub_wire2(1, 39) <= sub_wire16(39); + sub_wire2(1, 40) <= sub_wire16(40); + sub_wire2(1, 41) <= sub_wire16(41); + sub_wire2(1, 42) <= sub_wire16(42); + sub_wire2(1, 43) <= sub_wire16(43); + sub_wire2(1, 44) <= sub_wire16(44); + sub_wire2(1, 45) <= sub_wire16(45); + sub_wire2(1, 46) <= sub_wire16(46); + sub_wire2(1, 47) <= sub_wire16(47); + sub_wire2(1, 48) <= sub_wire16(48); + sub_wire2(1, 49) <= sub_wire16(49); + sub_wire2(1, 50) <= sub_wire16(50); + sub_wire2(1, 51) <= sub_wire16(51); + sub_wire2(1, 52) <= sub_wire16(52); + sub_wire2(1, 53) <= sub_wire16(53); + sub_wire2(1, 54) <= sub_wire16(54); + sub_wire2(1, 55) <= sub_wire16(55); + sub_wire2(1, 56) <= sub_wire16(56); + sub_wire2(1, 57) <= sub_wire16(57); + sub_wire2(1, 58) <= sub_wire16(58); + sub_wire2(1, 59) <= sub_wire16(59); + sub_wire2(1, 60) <= sub_wire16(60); + sub_wire2(1, 61) <= sub_wire16(61); + sub_wire2(1, 62) <= sub_wire16(62); + sub_wire2(1, 63) <= sub_wire16(63); + sub_wire2(1, 64) <= sub_wire16(64); + sub_wire2(1, 65) <= sub_wire16(65); + sub_wire2(1, 66) <= sub_wire16(66); + sub_wire2(1, 67) <= sub_wire16(67); + sub_wire2(1, 68) <= sub_wire16(68); + sub_wire2(1, 69) <= sub_wire16(69); + sub_wire2(1, 70) <= sub_wire16(70); + sub_wire2(1, 71) <= sub_wire16(71); + sub_wire2(1, 72) <= sub_wire16(72); + sub_wire2(1, 73) <= sub_wire16(73); + sub_wire2(1, 74) <= sub_wire16(74); + sub_wire2(1, 75) <= sub_wire16(75); + sub_wire2(1, 76) <= sub_wire16(76); + sub_wire2(1, 77) <= sub_wire16(77); + sub_wire2(1, 78) <= sub_wire16(78); + sub_wire2(1, 79) <= sub_wire16(79); + sub_wire2(1, 80) <= sub_wire16(80); + sub_wire2(1, 81) <= sub_wire16(81); + sub_wire2(1, 82) <= sub_wire16(82); + sub_wire2(1, 83) <= sub_wire16(83); + sub_wire2(1, 84) <= sub_wire16(84); + sub_wire2(1, 85) <= sub_wire16(85); + sub_wire2(1, 86) <= sub_wire16(86); + sub_wire2(1, 87) <= sub_wire16(87); + sub_wire2(1, 88) <= sub_wire16(88); + sub_wire2(1, 89) <= sub_wire16(89); + sub_wire2(1, 90) <= sub_wire16(90); + sub_wire2(1, 91) <= sub_wire16(91); + sub_wire2(1, 92) <= sub_wire16(92); + sub_wire2(1, 93) <= sub_wire16(93); + sub_wire2(1, 94) <= sub_wire16(94); + sub_wire2(1, 95) <= sub_wire16(95); + sub_wire2(1, 96) <= sub_wire16(96); + sub_wire2(1, 97) <= sub_wire16(97); + sub_wire2(1, 98) <= sub_wire16(98); + sub_wire2(1, 99) <= sub_wire16(99); + sub_wire2(1, 100) <= sub_wire16(100); + sub_wire2(1, 101) <= sub_wire16(101); + sub_wire2(1, 102) <= sub_wire16(102); + sub_wire2(1, 103) <= sub_wire16(103); + sub_wire2(1, 104) <= sub_wire16(104); + sub_wire2(1, 105) <= sub_wire16(105); + sub_wire2(1, 106) <= sub_wire16(106); + sub_wire2(1, 107) <= sub_wire16(107); + sub_wire2(1, 108) <= sub_wire16(108); + sub_wire2(1, 109) <= sub_wire16(109); + sub_wire2(1, 110) <= sub_wire16(110); + sub_wire2(1, 111) <= sub_wire16(111); + sub_wire2(1, 112) <= sub_wire16(112); + sub_wire2(1, 113) <= sub_wire16(113); + sub_wire2(1, 114) <= sub_wire16(114); + sub_wire2(1, 115) <= sub_wire16(115); + sub_wire2(1, 116) <= sub_wire16(116); + sub_wire2(1, 117) <= sub_wire16(117); + sub_wire2(1, 118) <= sub_wire16(118); + sub_wire2(1, 119) <= sub_wire16(119); + sub_wire2(1, 120) <= sub_wire16(120); + sub_wire2(1, 121) <= sub_wire16(121); + sub_wire2(1, 122) <= sub_wire16(122); + sub_wire2(1, 123) <= sub_wire16(123); + sub_wire2(1, 124) <= sub_wire16(124); + sub_wire2(1, 125) <= sub_wire16(125); + sub_wire2(1, 126) <= sub_wire16(126); + sub_wire2(1, 127) <= sub_wire16(127); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + sub_wire2(0, 8) <= sub_wire17(8); + sub_wire2(0, 9) <= sub_wire17(9); + sub_wire2(0, 10) <= sub_wire17(10); + sub_wire2(0, 11) <= sub_wire17(11); + sub_wire2(0, 12) <= sub_wire17(12); + sub_wire2(0, 13) <= sub_wire17(13); + sub_wire2(0, 14) <= sub_wire17(14); + sub_wire2(0, 15) <= sub_wire17(15); + sub_wire2(0, 16) <= sub_wire17(16); + sub_wire2(0, 17) <= sub_wire17(17); + sub_wire2(0, 18) <= sub_wire17(18); + sub_wire2(0, 19) <= sub_wire17(19); + sub_wire2(0, 20) <= sub_wire17(20); + sub_wire2(0, 21) <= sub_wire17(21); + sub_wire2(0, 22) <= sub_wire17(22); + sub_wire2(0, 23) <= sub_wire17(23); + sub_wire2(0, 24) <= sub_wire17(24); + sub_wire2(0, 25) <= sub_wire17(25); + sub_wire2(0, 26) <= sub_wire17(26); + sub_wire2(0, 27) <= sub_wire17(27); + sub_wire2(0, 28) <= sub_wire17(28); + sub_wire2(0, 29) <= sub_wire17(29); + sub_wire2(0, 30) <= sub_wire17(30); + sub_wire2(0, 31) <= sub_wire17(31); + sub_wire2(0, 32) <= sub_wire17(32); + sub_wire2(0, 33) <= sub_wire17(33); + sub_wire2(0, 34) <= sub_wire17(34); + sub_wire2(0, 35) <= sub_wire17(35); + sub_wire2(0, 36) <= sub_wire17(36); + sub_wire2(0, 37) <= sub_wire17(37); + sub_wire2(0, 38) <= sub_wire17(38); + sub_wire2(0, 39) <= sub_wire17(39); + sub_wire2(0, 40) <= sub_wire17(40); + sub_wire2(0, 41) <= sub_wire17(41); + sub_wire2(0, 42) <= sub_wire17(42); + sub_wire2(0, 43) <= sub_wire17(43); + sub_wire2(0, 44) <= sub_wire17(44); + sub_wire2(0, 45) <= sub_wire17(45); + sub_wire2(0, 46) <= sub_wire17(46); + sub_wire2(0, 47) <= sub_wire17(47); + sub_wire2(0, 48) <= sub_wire17(48); + sub_wire2(0, 49) <= sub_wire17(49); + sub_wire2(0, 50) <= sub_wire17(50); + sub_wire2(0, 51) <= sub_wire17(51); + sub_wire2(0, 52) <= sub_wire17(52); + sub_wire2(0, 53) <= sub_wire17(53); + sub_wire2(0, 54) <= sub_wire17(54); + sub_wire2(0, 55) <= sub_wire17(55); + sub_wire2(0, 56) <= sub_wire17(56); + sub_wire2(0, 57) <= sub_wire17(57); + sub_wire2(0, 58) <= sub_wire17(58); + sub_wire2(0, 59) <= sub_wire17(59); + sub_wire2(0, 60) <= sub_wire17(60); + sub_wire2(0, 61) <= sub_wire17(61); + sub_wire2(0, 62) <= sub_wire17(62); + sub_wire2(0, 63) <= sub_wire17(63); + sub_wire2(0, 64) <= sub_wire17(64); + sub_wire2(0, 65) <= sub_wire17(65); + sub_wire2(0, 66) <= sub_wire17(66); + sub_wire2(0, 67) <= sub_wire17(67); + sub_wire2(0, 68) <= sub_wire17(68); + sub_wire2(0, 69) <= sub_wire17(69); + sub_wire2(0, 70) <= sub_wire17(70); + sub_wire2(0, 71) <= sub_wire17(71); + sub_wire2(0, 72) <= sub_wire17(72); + sub_wire2(0, 73) <= sub_wire17(73); + sub_wire2(0, 74) <= sub_wire17(74); + sub_wire2(0, 75) <= sub_wire17(75); + sub_wire2(0, 76) <= sub_wire17(76); + sub_wire2(0, 77) <= sub_wire17(77); + sub_wire2(0, 78) <= sub_wire17(78); + sub_wire2(0, 79) <= sub_wire17(79); + sub_wire2(0, 80) <= sub_wire17(80); + sub_wire2(0, 81) <= sub_wire17(81); + sub_wire2(0, 82) <= sub_wire17(82); + sub_wire2(0, 83) <= sub_wire17(83); + sub_wire2(0, 84) <= sub_wire17(84); + sub_wire2(0, 85) <= sub_wire17(85); + sub_wire2(0, 86) <= sub_wire17(86); + sub_wire2(0, 87) <= sub_wire17(87); + sub_wire2(0, 88) <= sub_wire17(88); + sub_wire2(0, 89) <= sub_wire17(89); + sub_wire2(0, 90) <= sub_wire17(90); + sub_wire2(0, 91) <= sub_wire17(91); + sub_wire2(0, 92) <= sub_wire17(92); + sub_wire2(0, 93) <= sub_wire17(93); + sub_wire2(0, 94) <= sub_wire17(94); + sub_wire2(0, 95) <= sub_wire17(95); + sub_wire2(0, 96) <= sub_wire17(96); + sub_wire2(0, 97) <= sub_wire17(97); + sub_wire2(0, 98) <= sub_wire17(98); + sub_wire2(0, 99) <= sub_wire17(99); + sub_wire2(0, 100) <= sub_wire17(100); + sub_wire2(0, 101) <= sub_wire17(101); + sub_wire2(0, 102) <= sub_wire17(102); + sub_wire2(0, 103) <= sub_wire17(103); + sub_wire2(0, 104) <= sub_wire17(104); + sub_wire2(0, 105) <= sub_wire17(105); + sub_wire2(0, 106) <= sub_wire17(106); + sub_wire2(0, 107) <= sub_wire17(107); + sub_wire2(0, 108) <= sub_wire17(108); + sub_wire2(0, 109) <= sub_wire17(109); + sub_wire2(0, 110) <= sub_wire17(110); + sub_wire2(0, 111) <= sub_wire17(111); + sub_wire2(0, 112) <= sub_wire17(112); + sub_wire2(0, 113) <= sub_wire17(113); + sub_wire2(0, 114) <= sub_wire17(114); + sub_wire2(0, 115) <= sub_wire17(115); + sub_wire2(0, 116) <= sub_wire17(116); + sub_wire2(0, 117) <= sub_wire17(117); + sub_wire2(0, 118) <= sub_wire17(118); + sub_wire2(0, 119) <= sub_wire17(119); + sub_wire2(0, 120) <= sub_wire17(120); + sub_wire2(0, 121) <= sub_wire17(121); + sub_wire2(0, 122) <= sub_wire17(122); + sub_wire2(0, 123) <= sub_wire17(123); + sub_wire2(0, 124) <= sub_wire17(124); + sub_wire2(0, 125) <= sub_wire17(125); + sub_wire2(0, 126) <= sub_wire17(126); + sub_wire2(0, 127) <= sub_wire17(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0] +-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0] +-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0] +-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0] +-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0] +-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0] +-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0] +-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0] +-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0] +-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0] +-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0] +-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0] +-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg0.bsf b/FPGA_quartus/Video/lpm_shiftreg0.bsf new file mode 100644 index 0000000..fb70a4b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg0.bsf @@ -0,0 +1,70 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 128) + (text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "load" (rect 0 0 23 14)(font "Arial" (font_size 8))) + (text "load" (rect 20 26 41 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 144 72) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8))) + (line (pt 144 72)(pt 128 72)(line_width 1)) + ) + (drawing + (text "left shift" (rect 92 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 112)(line_width 1)) + (line (pt 128 112)(pt 16 112)(line_width 1)) + (line (pt 16 112)(pt 16 16)(line_width 1)) + (line (pt 16 74)(pt 22 80)(line_width 1)) + (line (pt 22 80)(pt 16 86)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg0.cmp b/FPGA_quartus/Video/lpm_shiftreg0.cmp new file mode 100644 index 0000000..c0613d5 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg0.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg0 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg0.inc b/FPGA_quartus/Video/lpm_shiftreg0.inc new file mode 100644 index 0000000..1c0c4a2 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg0.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg0 +( + clock, + data[15..0], + load, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_quartus/Video/lpm_shiftreg0.qip b/FPGA_quartus/Video/lpm_shiftreg0.qip new file mode 100644 index 0000000..a233319 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg0.vhd b/FPGA_quartus/Video/lpm_shiftreg0.vhd new file mode 100644 index 0000000..6e5d954 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg0.vhd @@ -0,0 +1,135 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg0.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg0 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg0; + + +ARCHITECTURE SYN OF lpm_shiftreg0 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + load : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "LEFT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 16 + ) + PORT MAP ( + load => load, + clock => clock, + data => data, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "1" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "1" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg1.bsf b/FPGA_quartus/Video/lpm_shiftreg1.bsf new file mode 100644 index 0000000..aa20405 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "left shift" (rect 92 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg1.cmp b/FPGA_quartus/Video/lpm_shiftreg1.cmp new file mode 100644 index 0000000..1a7ae1c --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg1 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg1.qip b/FPGA_quartus/Video/lpm_shiftreg1.qip new file mode 100644 index 0000000..8a8e8a5 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg1.vhd b/FPGA_quartus/Video/lpm_shiftreg1.vhd new file mode 100644 index 0000000..781fe1b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg1.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg1.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg1 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END lpm_shiftreg1; + + +ARCHITECTURE SYN OF lpm_shiftreg1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(1 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "LEFT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 2 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "1" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg2.bsf b/FPGA_quartus/Video/lpm_shiftreg2.bsf new file mode 100644 index 0000000..0caa084 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg2.cmp b/FPGA_quartus/Video/lpm_shiftreg2.cmp new file mode 100644 index 0000000..e7c1030 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg2 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg2.qip b/FPGA_quartus/Video/lpm_shiftreg2.qip new file mode 100644 index 0000000..3c5305b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg2.vhd b/FPGA_quartus/Video/lpm_shiftreg2.vhd new file mode 100644 index 0000000..ca02c26 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg2.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg2.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg2 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg2; + + +ARCHITECTURE SYN OF lpm_shiftreg2 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 4 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg3.bsf b/FPGA_quartus/Video/lpm_shiftreg3.bsf new file mode 100644 index 0000000..d18b388 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg3.cmp b/FPGA_quartus/Video/lpm_shiftreg3.cmp new file mode 100644 index 0000000..4cc6db7 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg3 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg3.inc b/FPGA_quartus/Video/lpm_shiftreg3.inc new file mode 100644 index 0000000..4f70ce5 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg3.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg3 +( + clock, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_quartus/Video/lpm_shiftreg3.qip b/FPGA_quartus/Video/lpm_shiftreg3.qip new file mode 100644 index 0000000..783fdea --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg3.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg3.vhd b/FPGA_quartus/Video/lpm_shiftreg3.vhd new file mode 100644 index 0000000..b87c221 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg3.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg3.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg3 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg3; + + +ARCHITECTURE SYN OF lpm_shiftreg3 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 2 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg4.bsf b/FPGA_quartus/Video/lpm_shiftreg4.bsf new file mode 100644 index 0000000..658958d --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg4.cmp b/FPGA_quartus/Video/lpm_shiftreg4.cmp new file mode 100644 index 0000000..83fb9e5 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg4 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg4.inc b/FPGA_quartus/Video/lpm_shiftreg4.inc new file mode 100644 index 0000000..322863a --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg4.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg4 +( + clock, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_quartus/Video/lpm_shiftreg4.qip b/FPGA_quartus/Video/lpm_shiftreg4.qip new file mode 100644 index 0000000..363cd59 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg4.vhd b/FPGA_quartus/Video/lpm_shiftreg4.vhd new file mode 100644 index 0000000..3d8f5d1 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg4.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg4.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg4 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg4; + + +ARCHITECTURE SYN OF lpm_shiftreg4 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg5.bsf b/FPGA_quartus/Video/lpm_shiftreg5.bsf new file mode 100644 index 0000000..a528c96 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg5.cmp b/FPGA_quartus/Video/lpm_shiftreg5.cmp new file mode 100644 index 0000000..638f12e --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg5 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg5.inc b/FPGA_quartus/Video/lpm_shiftreg5.inc new file mode 100644 index 0000000..431ed2c --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg5 +( + clock, + shiftin +) + +RETURNS ( + q[4..0] +); diff --git a/FPGA_quartus/Video/lpm_shiftreg5.qip b/FPGA_quartus/Video/lpm_shiftreg5.qip new file mode 100644 index 0000000..9b71f4b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg5.vhd b/FPGA_quartus/Video/lpm_shiftreg5.vhd new file mode 100644 index 0000000..71a1232 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg5.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg5.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg5 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_shiftreg5; + + +ARCHITECTURE SYN OF lpm_shiftreg5 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(4 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/Video/lpm_shiftreg6.bsf b/FPGA_quartus/Video/lpm_shiftreg6.bsf new file mode 100644 index 0000000..aa0296b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg6.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/Video/lpm_shiftreg6.cmp b/FPGA_quartus/Video/lpm_shiftreg6.cmp new file mode 100644 index 0000000..c9f7a9b --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg6.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg6 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/Video/lpm_shiftreg6.inc b/FPGA_quartus/Video/lpm_shiftreg6.inc new file mode 100644 index 0000000..7767c57 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg6.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg6 +( + clock, + shiftin +) + +RETURNS ( + q[4..0] +); diff --git a/FPGA_quartus/Video/lpm_shiftreg6.qip b/FPGA_quartus/Video/lpm_shiftreg6.qip new file mode 100644 index 0000000..adb4909 --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"] diff --git a/FPGA_quartus/Video/lpm_shiftreg6.vhd b/FPGA_quartus/Video/lpm_shiftreg6.vhd new file mode 100644 index 0000000..773243e --- /dev/null +++ b/FPGA_quartus/Video/lpm_shiftreg6.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg6.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg6 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_shiftreg6; + + +ARCHITECTURE SYN OF lpm_shiftreg6 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(4 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/altddio_out0.bsf b/FPGA_quartus/altddio_out0.bsf new file mode 100644 index 0000000..9889d79 --- /dev/null +++ b/FPGA_quartus/altddio_out0.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altddio_out0.cmp b/FPGA_quartus/altddio_out0.cmp new file mode 100644 index 0000000..6e98c39 --- /dev/null +++ b/FPGA_quartus/altddio_out0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out0 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altddio_out0.inc b/FPGA_quartus/altddio_out0.inc new file mode 100644 index 0000000..030b327 --- /dev/null +++ b/FPGA_quartus/altddio_out0.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out0 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_quartus/altddio_out0.ppf b/FPGA_quartus/altddio_out0.ppf new file mode 100644 index 0000000..4379977 --- /dev/null +++ b/FPGA_quartus/altddio_out0.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_quartus/altddio_out0.qip b/FPGA_quartus/altddio_out0.qip new file mode 100644 index 0000000..8193856 --- /dev/null +++ b/FPGA_quartus/altddio_out0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] diff --git a/FPGA_quartus/altddio_out0.vhd b/FPGA_quartus/altddio_out0.vhd new file mode 100644 index 0000000..ea6d708 --- /dev/null +++ b/FPGA_quartus/altddio_out0.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out0.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out0 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out0; + + +ARCHITECTURE SYN OF altddio_out0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altddio_out3.bsf b/FPGA_quartus/altddio_out3.bsf new file mode 100644 index 0000000..ba8c153 --- /dev/null +++ b/FPGA_quartus/altddio_out3.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altddio_out3.cmp b/FPGA_quartus/altddio_out3.cmp new file mode 100644 index 0000000..ce5862c --- /dev/null +++ b/FPGA_quartus/altddio_out3.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out3 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altddio_out3.inc b/FPGA_quartus/altddio_out3.inc new file mode 100644 index 0000000..f6b4097 --- /dev/null +++ b/FPGA_quartus/altddio_out3.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out3 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_quartus/altddio_out3.ppf b/FPGA_quartus/altddio_out3.ppf new file mode 100644 index 0000000..e914df8 --- /dev/null +++ b/FPGA_quartus/altddio_out3.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_quartus/altddio_out3.qip b/FPGA_quartus/altddio_out3.qip new file mode 100644 index 0000000..8f94ee3 --- /dev/null +++ b/FPGA_quartus/altddio_out3.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] diff --git a/FPGA_quartus/altddio_out3.vhd b/FPGA_quartus/altddio_out3.vhd new file mode 100644 index 0000000..e55160f --- /dev/null +++ b/FPGA_quartus/altddio_out3.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out3.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out3 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out3; + + +ARCHITECTURE SYN OF altddio_out3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll0.bsf b/FPGA_quartus/altpll0.bsf new file mode 100644 index 0000000..b9a2853 --- /dev/null +++ b/FPGA_quartus/altpll0.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 280 248) + (text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 280 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8))) + (line (pt 280 72)(pt 248 72)(line_width 1)) + ) + (port + (pt 280 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8))) + (line (pt 280 96)(pt 248 96)(line_width 1)) + ) + (port + (pt 280 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8))) + (line (pt 280 120)(pt 248 120)(line_width 1)) + ) + (port + (pt 280 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8))) + (line (pt 280 144)(pt 248 144)(line_width 1)) + ) + (port + (pt 280 168) + (output) + (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8))) + (line (pt 280 168)(pt 248 168)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 205 230 253 244)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 90 111 114 125)(font "Arial" )) + (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) + (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "16/11" (rect 89 129 116 143)(font "Arial" )) + (text "0.00" (rect 136 129 157 143)(font "Arial" )) + (text "50.00" (rect 178 129 205 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "50/11" (rect 89 147 116 161)(font "Arial" )) + (text "0.00" (rect 136 147 157 161)(font "Arial" )) + (text "50.00" (rect 178 147 205 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "40/11" (rect 89 165 116 179)(font "Arial" )) + (text "0.00" (rect 136 165 157 179)(font "Arial" )) + (text "50.00" (rect 178 165 205 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "109/33" (rect 85 183 118 197)(font "Arial" )) + (text "0.00" (rect 136 183 157 197)(font "Arial" )) + (text "50.00" (rect 178 183 205 197)(font "Arial" )) + (text "c4" (rect 63 201 75 215)(font "Arial" )) + (text "109/39" (rect 85 201 118 215)(font "Arial" )) + (text "0.00" (rect 136 201 157 215)(font "Arial" )) + (text "50.00" (rect 178 201 205 215)(font "Arial" )) + (line (pt 0 0)(pt 281 0)(line_width 1)) + (line (pt 281 0)(pt 281 249)(line_width 1)) + (line (pt 0 249)(pt 281 249)(line_width 1)) + (line (pt 0 0)(pt 0 249)(line_width 1)) + (line (pt 56 108)(pt 215 108)(line_width 1)) + (line (pt 56 125)(pt 215 125)(line_width 1)) + (line (pt 56 143)(pt 215 143)(line_width 1)) + (line (pt 56 161)(pt 215 161)(line_width 1)) + (line (pt 56 179)(pt 215 179)(line_width 1)) + (line (pt 56 197)(pt 215 197)(line_width 1)) + (line (pt 56 215)(pt 215 215)(line_width 1)) + (line (pt 56 108)(pt 56 215)(line_width 1)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 125 108)(pt 125 215)(line_width 3)) + (line (pt 170 108)(pt 170 215)(line_width 3)) + (line (pt 214 108)(pt 214 215)(line_width 1)) + (line (pt 48 56)(pt 248 56)(line_width 1)) + (line (pt 248 56)(pt 248 232)(line_width 1)) + (line (pt 48 232)(pt 248 232)(line_width 1)) + (line (pt 48 56)(pt 48 232)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll0.cmp b/FPGA_quartus/altpll0.cmp new file mode 100644 index 0000000..5097275 --- /dev/null +++ b/FPGA_quartus/altpll0.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll0 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll0.inc b/FPGA_quartus/altpll0.inc new file mode 100644 index 0000000..933af49 --- /dev/null +++ b/FPGA_quartus/altpll0.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll0 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/FPGA_quartus/altpll0.ppf b/FPGA_quartus/altpll0.ppf new file mode 100644 index 0000000..521a742 --- /dev/null +++ b/FPGA_quartus/altpll0.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FPGA_quartus/altpll0.qip b/FPGA_quartus/altpll0.qip new file mode 100644 index 0000000..1b4cd11 --- /dev/null +++ b/FPGA_quartus/altpll0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"] diff --git a/FPGA_quartus/altpll0.vhd b/FPGA_quartus/altpll0.vhd new file mode 100644 index 0000000..b035bf5 --- /dev/null +++ b/FPGA_quartus/altpll0.vhd @@ -0,0 +1,477 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll0.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll0 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll0; + + +ARCHITECTURE SYN OF altpll0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 11, + clk0_duty_cycle => 50, + clk0_multiply_by => 16, + clk0_phase_shift => "0", + clk1_divide_by => 11, + clk1_duty_cycle => 50, + clk1_multiply_by => 50, + clk1_phase_shift => "0", + clk2_divide_by => 11, + clk2_duty_cycle => 50, + clk2_multiply_by => 40, + clk2_phase_shift => "0", + clk3_divide_by => 33, + clk3_duty_cycle => 50, + clk3_multiply_by => 109, + clk3_phase_shift => "0", + clk4_divide_by => 39, + clk4_duty_cycle => 50, + clk4_multiply_by => 109, + clk4_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll0_waveforms.html b/FPGA_quartus/altpll0_waveforms.html new file mode 100644 index 0000000..80e236a --- /dev/null +++ b/FPGA_quartus/altpll0_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll0.vhd" + + +

Sample behavioral waveforms for design file "altpll0.vhd"

+

+

+ + diff --git a/FPGA_quartus/altpll1.bsf b/FPGA_quartus/altpll1.bsf new file mode 100644 index 0000000..d1e4a9e --- /dev/null +++ b/FPGA_quartus/altpll1.bsf @@ -0,0 +1,100 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 328 216) + (text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 197 31 212)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 328 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8))) + (line (pt 328 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 328 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8))) + (line (pt 328 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 328 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8))) + (line (pt 328 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 328 144) + (output) + (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) + (text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8))) + (line (pt 328 144)(pt 272 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 253 198 301 212)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 90 111 114 125)(font "Arial" )) + (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) + (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "1/66" (rect 92 129 113 143)(font "Arial" )) + (text "0.00" (rect 136 129 157 143)(font "Arial" )) + (text "50.00" (rect 178 129 205 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "67/900" (rect 85 147 118 161)(font "Arial" )) + (text "0.00" (rect 136 147 157 161)(font "Arial" )) + (text "50.00" (rect 178 147 205 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "67/90" (rect 89 165 116 179)(font "Arial" )) + (text "0.00" (rect 136 165 157 179)(font "Arial" )) + (text "50.00" (rect 178 165 205 179)(font "Arial" )) + (line (pt 0 0)(pt 329 0)(line_width 1)) + (line (pt 329 0)(pt 329 217)(line_width 1)) + (line (pt 0 217)(pt 329 217)(line_width 1)) + (line (pt 0 0)(pt 0 217)(line_width 1)) + (line (pt 56 108)(pt 215 108)(line_width 1)) + (line (pt 56 125)(pt 215 125)(line_width 1)) + (line (pt 56 143)(pt 215 143)(line_width 1)) + (line (pt 56 161)(pt 215 161)(line_width 1)) + (line (pt 56 179)(pt 215 179)(line_width 1)) + (line (pt 56 108)(pt 56 179)(line_width 1)) + (line (pt 82 108)(pt 82 179)(line_width 3)) + (line (pt 125 108)(pt 125 179)(line_width 3)) + (line (pt 170 108)(pt 170 179)(line_width 3)) + (line (pt 214 108)(pt 214 179)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 200)(line_width 1)) + (line (pt 48 200)(pt 272 200)(line_width 1)) + (line (pt 48 56)(pt 48 200)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll1.cmp b/FPGA_quartus/altpll1.cmp new file mode 100644 index 0000000..300576d --- /dev/null +++ b/FPGA_quartus/altpll1.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll1 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll1.inc b/FPGA_quartus/altpll1.inc new file mode 100644 index 0000000..0923ad2 --- /dev/null +++ b/FPGA_quartus/altpll1.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll1 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + locked +); diff --git a/FPGA_quartus/altpll1.ppf b/FPGA_quartus/altpll1.ppf new file mode 100644 index 0000000..0f38a28 --- /dev/null +++ b/FPGA_quartus/altpll1.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_quartus/altpll1.qip b/FPGA_quartus/altpll1.qip new file mode 100644 index 0000000..ec03f05 --- /dev/null +++ b/FPGA_quartus/altpll1.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] diff --git a/FPGA_quartus/altpll1.vhd b/FPGA_quartus/altpll1.vhd new file mode 100644 index 0000000..ab9bfaf --- /dev/null +++ b/FPGA_quartus/altpll1.vhd @@ -0,0 +1,423 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll1.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll1 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END altpll1; + + +ARCHITECTURE SYN OF altpll1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + locked <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 66, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 900, + clk1_duty_cycle => 50, + clk1_multiply_by => 67, + clk1_phase_shift => "0", + clk2_divide_by => 90, + clk2_duty_cycle => 50, + clk2_multiply_by => 67, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire4 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll1_waveforms.html b/FPGA_quartus/altpll1_waveforms.html new file mode 100644 index 0000000..1382a12 --- /dev/null +++ b/FPGA_quartus/altpll1_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll1.vhd" + + +

Sample behavioral waveforms for design file "altpll1.vhd"

+

+

+ + diff --git a/FPGA_quartus/altpll2.bsf b/FPGA_quartus/altpll2.bsf new file mode 100644 index 0000000..79679d7 --- /dev/null +++ b/FPGA_quartus/altpll2.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 304 248) + (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 304 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 304 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 304 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 304 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)(line_width 1)) + ) + (port + (pt 304 168) + (output) + (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8))) + (line (pt 304 168)(pt 272 168)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 229 230 277 244)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 85 111 109 125)(font "Arial" )) + (text "Ph (dg)" (rect 119 111 154 125)(font "Arial" )) + (text "DC (%)" (rect 164 111 199 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "4/1" (rect 91 129 106 143)(font "Arial" )) + (text "240.00" (rect 120 129 153 143)(font "Arial" )) + (text "50.00" (rect 169 129 196 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "4/1" (rect 91 147 106 161)(font "Arial" )) + (text "0.00" (rect 127 147 148 161)(font "Arial" )) + (text "50.00" (rect 169 147 196 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "4/1" (rect 91 165 106 179)(font "Arial" )) + (text "180.00" (rect 120 165 153 179)(font "Arial" )) + (text "50.00" (rect 169 165 196 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "4/1" (rect 91 183 106 197)(font "Arial" )) + (text "105.00" (rect 120 183 153 197)(font "Arial" )) + (text "50.00" (rect 169 183 196 197)(font "Arial" )) + (text "c4" (rect 63 201 75 215)(font "Arial" )) + (text "2/1" (rect 91 201 106 215)(font "Arial" )) + (text "270.00" (rect 120 201 153 215)(font "Arial" )) + (text "50.00" (rect 169 201 196 215)(font "Arial" )) + (line (pt 0 0)(pt 305 0)(line_width 1)) + (line (pt 305 0)(pt 305 249)(line_width 1)) + (line (pt 0 249)(pt 305 249)(line_width 1)) + (line (pt 0 0)(pt 0 249)(line_width 1)) + (line (pt 56 108)(pt 206 108)(line_width 1)) + (line (pt 56 125)(pt 206 125)(line_width 1)) + (line (pt 56 143)(pt 206 143)(line_width 1)) + (line (pt 56 161)(pt 206 161)(line_width 1)) + (line (pt 56 179)(pt 206 179)(line_width 1)) + (line (pt 56 197)(pt 206 197)(line_width 1)) + (line (pt 56 215)(pt 206 215)(line_width 1)) + (line (pt 56 108)(pt 56 215)(line_width 1)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 116 108)(pt 116 215)(line_width 3)) + (line (pt 161 108)(pt 161 215)(line_width 3)) + (line (pt 205 108)(pt 205 215)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 232)(line_width 1)) + (line (pt 48 232)(pt 272 232)(line_width 1)) + (line (pt 48 56)(pt 48 232)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll2.cmp b/FPGA_quartus/altpll2.cmp new file mode 100644 index 0000000..c6fe758 --- /dev/null +++ b/FPGA_quartus/altpll2.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll2 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll2.inc b/FPGA_quartus/altpll2.inc new file mode 100644 index 0000000..e75913b --- /dev/null +++ b/FPGA_quartus/altpll2.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll2 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/FPGA_quartus/altpll2.ppf b/FPGA_quartus/altpll2.ppf new file mode 100644 index 0000000..b1c71cc --- /dev/null +++ b/FPGA_quartus/altpll2.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FPGA_quartus/altpll2.qip b/FPGA_quartus/altpll2.qip new file mode 100644 index 0000000..74cc641 --- /dev/null +++ b/FPGA_quartus/altpll2.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] diff --git a/FPGA_quartus/altpll2.vhd b/FPGA_quartus/altpll2.vhd new file mode 100644 index 0000000..2c55f08 --- /dev/null +++ b/FPGA_quartus/altpll2.vhd @@ -0,0 +1,477 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll2.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll2 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll2; + + +ARCHITECTURE SYN OF altpll2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "5051", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 1, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "3788", + clk3_divide_by => 1, + clk3_duty_cycle => 50, + clk3_multiply_by => 4, + clk3_phase_shift => "2210", + clk4_divide_by => 1, + clk4_duty_cycle => 50, + clk4_multiply_by => 2, + clk4_phase_shift => "11364", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll2_waveforms.html b/FPGA_quartus/altpll2_waveforms.html new file mode 100644 index 0000000..1932527 --- /dev/null +++ b/FPGA_quartus/altpll2_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll2.vhd" + + +

Sample behavioral waveforms for design file "altpll2.vhd"

+

+

+ + diff --git a/FPGA_quartus/altpll3.bsf b/FPGA_quartus/altpll3.bsf new file mode 100644 index 0000000..da30b0c --- /dev/null +++ b/FPGA_quartus/altpll3.bsf @@ -0,0 +1,105 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 304 232) + (text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 213 31 228)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 304 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 304 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 304 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 304 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 229 214 277 228)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 86 111 110 125)(font "Arial" )) + (text "Ph (dg)" (rect 121 111 156 125)(font "Arial" )) + (text "DC (%)" (rect 166 111 201 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "2/33" (rect 88 129 109 143)(font "Arial" )) + (text "0.00" (rect 129 129 150 143)(font "Arial" )) + (text "50.00" (rect 171 129 198 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "16/33" (rect 85 147 112 161)(font "Arial" )) + (text "0.00" (rect 129 147 150 161)(font "Arial" )) + (text "50.00" (rect 171 147 198 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "25/33" (rect 85 165 112 179)(font "Arial" )) + (text "0.00" (rect 129 165 150 179)(font "Arial" )) + (text "50.00" (rect 171 165 198 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "16/11" (rect 85 183 112 197)(font "Arial" )) + (text "0.00" (rect 129 183 150 197)(font "Arial" )) + (text "50.00" (rect 171 183 198 197)(font "Arial" )) + (line (pt 0 0)(pt 305 0)(line_width 1)) + (line (pt 305 0)(pt 305 233)(line_width 1)) + (line (pt 0 233)(pt 305 233)(line_width 1)) + (line (pt 0 0)(pt 0 233)(line_width 1)) + (line (pt 56 108)(pt 208 108)(line_width 1)) + (line (pt 56 125)(pt 208 125)(line_width 1)) + (line (pt 56 143)(pt 208 143)(line_width 1)) + (line (pt 56 161)(pt 208 161)(line_width 1)) + (line (pt 56 179)(pt 208 179)(line_width 1)) + (line (pt 56 197)(pt 208 197)(line_width 1)) + (line (pt 56 108)(pt 56 197)(line_width 1)) + (line (pt 82 108)(pt 82 197)(line_width 3)) + (line (pt 118 108)(pt 118 197)(line_width 3)) + (line (pt 163 108)(pt 163 197)(line_width 3)) + (line (pt 207 108)(pt 207 197)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 216)(line_width 1)) + (line (pt 48 216)(pt 272 216)(line_width 1)) + (line (pt 48 56)(pt 48 216)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll3.cmp b/FPGA_quartus/altpll3.cmp new file mode 100644 index 0000000..44b3f2e --- /dev/null +++ b/FPGA_quartus/altpll3.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll3 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll3.inc b/FPGA_quartus/altpll3.inc new file mode 100644 index 0000000..160ecad --- /dev/null +++ b/FPGA_quartus/altpll3.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll3 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3 +); diff --git a/FPGA_quartus/altpll3.ppf b/FPGA_quartus/altpll3.ppf new file mode 100644 index 0000000..2a7b695 --- /dev/null +++ b/FPGA_quartus/altpll3.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_quartus/altpll3.qip b/FPGA_quartus/altpll3.qip new file mode 100644 index 0000000..8dd2955 --- /dev/null +++ b/FPGA_quartus/altpll3.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] diff --git a/FPGA_quartus/altpll3.vhd b/FPGA_quartus/altpll3.vhd new file mode 100644 index 0000000..6ead1f5 --- /dev/null +++ b/FPGA_quartus/altpll3.vhd @@ -0,0 +1,445 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll3.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll3 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END altpll3; + + +ARCHITECTURE SYN OF altpll3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 33, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 33, + clk1_duty_cycle => 50, + clk1_multiply_by => 16, + clk1_phase_shift => "0", + clk2_divide_by => 33, + clk2_duty_cycle => 50, + clk2_multiply_by => 25, + clk2_phase_shift => "0", + clk3_divide_by => 11, + clk3_duty_cycle => 50, + clk3_multiply_by => 16, + clk3_phase_shift => "0", + compensate_clock => "CLK1", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll3_waveforms.html b/FPGA_quartus/altpll3_waveforms.html new file mode 100644 index 0000000..3f6367c --- /dev/null +++ b/FPGA_quartus/altpll3_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll3.vhd" + + +

Sample behavioral waveforms for design file "altpll3.vhd"

+

+

+ + diff --git a/FPGA_quartus/altpll4.bsf b/FPGA_quartus/altpll4.bsf new file mode 100644 index 0000000..e071d43 --- /dev/null +++ b/FPGA_quartus/altpll4.bsf @@ -0,0 +1,125 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 376 232) + (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 213 31 228)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 88 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) + (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 88 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 88 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 88 144)(line_width 1)) + ) + (port + (pt 0 168) + (input) + (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 88 168)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 88 192)(line_width 1)) + ) + (port + (pt 376 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) + (line (pt 376 72)(pt 288 72)(line_width 1)) + ) + (port + (pt 376 96) + (output) + (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) + (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) + (line (pt 376 96)(pt 288 96)(line_width 1)) + ) + (port + (pt 376 120) + (output) + (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) + (line (pt 376 120)(pt 288 120)(line_width 1)) + ) + (port + (pt 376 144) + (output) + (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) + (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) + (line (pt 376 144)(pt 288 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) + (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) + (text "Clk " (rect 99 167 116 181)(font "Arial" )) + (text "Ratio" (rect 125 167 149 181)(font "Arial" )) + (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) + (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) + (text "c0" (rect 103 185 115 199)(font "Arial" )) + (text "2/1" (rect 131 185 146 199)(font "Arial" )) + (text "0.00" (rect 167 185 188 199)(font "Arial" )) + (text "50.00" (rect 209 185 236 199)(font "Arial" )) + (line (pt 0 0)(pt 377 0)(line_width 1)) + (line (pt 377 0)(pt 377 233)(line_width 1)) + (line (pt 0 233)(pt 377 233)(line_width 1)) + (line (pt 0 0)(pt 0 233)(line_width 1)) + (line (pt 96 164)(pt 246 164)(line_width 1)) + (line (pt 96 181)(pt 246 181)(line_width 1)) + (line (pt 96 199)(pt 246 199)(line_width 1)) + (line (pt 96 164)(pt 96 199)(line_width 1)) + (line (pt 122 164)(pt 122 199)(line_width 3)) + (line (pt 156 164)(pt 156 199)(line_width 3)) + (line (pt 201 164)(pt 201 199)(line_width 3)) + (line (pt 245 164)(pt 245 199)(line_width 1)) + (line (pt 88 56)(pt 288 56)(line_width 1)) + (line (pt 288 56)(pt 288 216)(line_width 1)) + (line (pt 88 216)(pt 288 216)(line_width 1)) + (line (pt 88 56)(pt 88 216)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll4.cmp b/FPGA_quartus/altpll4.cmp new file mode 100644 index 0000000..83b3c1e --- /dev/null +++ b/FPGA_quartus/altpll4.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll4 + PORT + ( + areset : IN STD_LOGIC := '0'; + configupdate : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + scanclk : IN STD_LOGIC := '1'; + scanclkena : IN STD_LOGIC := '0'; + scandata : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ; + scandataout : OUT STD_LOGIC ; + scandone : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll4.inc b/FPGA_quartus/altpll4.inc new file mode 100644 index 0000000..39f54c9 --- /dev/null +++ b/FPGA_quartus/altpll4.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll4 +( + areset, + configupdate, + inclk0, + scanclk, + scanclkena, + scandata +) + +RETURNS ( + c0, + locked, + scandataout, + scandone +); diff --git a/FPGA_quartus/altpll4.mif b/FPGA_quartus/altpll4.mif new file mode 100644 index 0000000..e50eda2 --- /dev/null +++ b/FPGA_quartus/altpll4.mif @@ -0,0 +1,174 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- MIF file representing initial state of PLL Scan Chain +-- Device Family: Cyclone III +-- Device Part: - +-- Device Speed Grade: 8 +-- PLL Scan Chain: Fast PLL (144 bits) +-- File Name: C:\FireBee\FPGA\altpll4.mif +-- Generated: Mon Dec 06 01:47:24 2010 + +WIDTH=1; +DEPTH=144; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 0; -- Reserved Bits = 0 (1 bit(s)) + 1 : 0; -- Reserved Bits = 0 (1 bit(s)) + 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) + 3 : 0; + 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) + 5 : 1; + 6 : 0; + 7 : 1; + 8 : 1; + 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) + 10 : 0; -- Reserved Bits = 0 (5 bit(s)) + 11 : 0; + 12 : 0; + 13 : 0; + 14 : 0; + 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) + 16 : 0; + 17 : 1; + 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) + 19 : 0; -- N counter: High Count = 0 (8 bit(s)) + 20 : 0; + 21 : 0; + 22 : 0; + 23 : 0; + 24 : 0; + 25 : 0; + 26 : 0; + 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) + 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) + 29 : 0; + 30 : 0; + 31 : 0; + 32 : 0; + 33 : 0; + 34 : 0; + 35 : 0; + 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) + 37 : 0; -- M counter: High Count = 6 (8 bit(s)) + 38 : 0; + 39 : 0; + 40 : 0; + 41 : 0; + 42 : 1; + 43 : 1; + 44 : 0; + 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 6 (8 bit(s)) + 47 : 0; + 48 : 0; + 49 : 0; + 50 : 0; + 51 : 1; + 52 : 1; + 53 : 0; + 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) + 55 : 0; -- clk0 counter: High Count = 3 (8 bit(s)) + 56 : 0; + 57 : 0; + 58 : 0; + 59 : 0; + 60 : 0; + 61 : 1; + 62 : 1; + 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s)) + 65 : 0; + 66 : 0; + 67 : 0; + 68 : 0; + 69 : 0; + 70 : 1; + 71 : 1; + 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 74 : 0; + 75 : 0; + 76 : 0; + 77 : 0; + 78 : 0; + 79 : 0; + 80 : 0; + 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 83 : 0; + 84 : 0; + 85 : 0; + 86 : 0; + 87 : 0; + 88 : 0; + 89 : 0; + 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) + 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) + 92 : 0; + 93 : 0; + 94 : 0; + 95 : 0; + 96 : 0; + 97 : 0; + 98 : 0; + 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) + 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) + 101 : 0; + 102 : 0; + 103 : 0; + 104 : 0; + 105 : 0; + 106 : 0; + 107 : 0; + 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) + 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) + 110 : 0; + 111 : 0; + 112 : 0; + 113 : 0; + 114 : 0; + 115 : 0; + 116 : 0; + 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) + 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) + 119 : 0; + 120 : 0; + 121 : 0; + 122 : 0; + 123 : 0; + 124 : 0; + 125 : 0; + 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) + 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) + 128 : 0; + 129 : 0; + 130 : 0; + 131 : 0; + 132 : 0; + 133 : 0; + 134 : 0; + 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) + 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) + 137 : 0; + 138 : 0; + 139 : 0; + 140 : 0; + 141 : 0; + 142 : 0; + 143 : 0; +END; diff --git a/FPGA_quartus/altpll4.ppf b/FPGA_quartus/altpll4.ppf new file mode 100644 index 0000000..541ce91 --- /dev/null +++ b/FPGA_quartus/altpll4.ppf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/FPGA_quartus/altpll4.qip b/FPGA_quartus/altpll4.qip new file mode 100644 index 0000000..f44acdc --- /dev/null +++ b/FPGA_quartus/altpll4.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] diff --git a/FPGA_quartus/altpll4.tdf b/FPGA_quartus/altpll4.tdf new file mode 100644 index 0000000..3ec77d4 --- /dev/null +++ b/FPGA_quartus/altpll4.tdf @@ -0,0 +1,298 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll4.tdf +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + +INCLUDE "altpll.inc"; + + + +SUBDESIGN altpll4 +( + areset : INPUT = GND; + configupdate : INPUT = GND; + inclk0 : INPUT = GND; + scanclk : INPUT = VCC; + scanclkena : INPUT = GND; + scandata : INPUT = GND; + c0 : OUTPUT; + locked : OUTPUT; + scandataout : OUTPUT; + scandone : OUTPUT; +) + +VARIABLE + + altpll_component : altpll WITH ( + BANDWIDTH_TYPE = "AUTO", + CLK0_DIVIDE_BY = 1, + CLK0_DUTY_CYCLE = 50, + CLK0_MULTIPLY_BY = 2, + CLK0_PHASE_SHIFT = "0", + COMPENSATE_CLOCK = "CLK0", + INCLK0_INPUT_FREQUENCY = 20833, + INTENDED_DEVICE_FAMILY = "Cyclone III", + LPM_TYPE = "altpll", + OPERATION_MODE = "NORMAL", + PLL_TYPE = "AUTO", + PORT_ACTIVECLOCK = "PORT_UNUSED", + PORT_ARESET = "PORT_USED", + PORT_CLKBAD0 = "PORT_UNUSED", + PORT_CLKBAD1 = "PORT_UNUSED", + PORT_CLKLOSS = "PORT_UNUSED", + PORT_CLKSWITCH = "PORT_UNUSED", + PORT_CONFIGUPDATE = "PORT_USED", + PORT_FBIN = "PORT_UNUSED", + PORT_INCLK0 = "PORT_USED", + PORT_INCLK1 = "PORT_UNUSED", + PORT_LOCKED = "PORT_USED", + PORT_PFDENA = "PORT_UNUSED", + PORT_PHASECOUNTERSELECT = "PORT_UNUSED", + PORT_PHASEDONE = "PORT_UNUSED", + PORT_PHASESTEP = "PORT_UNUSED", + PORT_PHASEUPDOWN = "PORT_UNUSED", + PORT_PLLENA = "PORT_UNUSED", + PORT_SCANACLR = "PORT_UNUSED", + PORT_SCANCLK = "PORT_USED", + PORT_SCANCLKENA = "PORT_USED", + PORT_SCANDATA = "PORT_USED", + PORT_SCANDATAOUT = "PORT_USED", + PORT_SCANDONE = "PORT_USED", + PORT_SCANREAD = "PORT_UNUSED", + PORT_SCANWRITE = "PORT_UNUSED", + PORT_clk0 = "PORT_USED", + PORT_clk1 = "PORT_UNUSED", + PORT_clk2 = "PORT_UNUSED", + PORT_clk3 = "PORT_UNUSED", + PORT_clk4 = "PORT_UNUSED", + PORT_clk5 = "PORT_UNUSED", + PORT_clkena0 = "PORT_UNUSED", + PORT_clkena1 = "PORT_UNUSED", + PORT_clkena2 = "PORT_UNUSED", + PORT_clkena3 = "PORT_UNUSED", + PORT_clkena4 = "PORT_UNUSED", + PORT_clkena5 = "PORT_UNUSED", + PORT_extclk0 = "PORT_UNUSED", + PORT_extclk1 = "PORT_UNUSED", + PORT_extclk2 = "PORT_UNUSED", + PORT_extclk3 = "PORT_UNUSED", + SELF_RESET_ON_LOSS_LOCK = "OFF", + WIDTH_CLOCK = 5, + scan_chain_mif_file = "altpll4.mif" + ); + +BEGIN + + c0 = altpll_component.clk[0..0]; + scandone = altpll_component.scandone; + scandataout = altpll_component.scandataout; + locked = altpll_component.locked; + altpll_component.scanclkena = scanclkena; + altpll_component.inclk[0..0] = inclk0; + altpll_component.inclk[1..1] = GND; + altpll_component.scandata = scandata; + altpll_component.areset = areset; + altpll_component.scanclk = scanclk; + altpll_component.configupdate = configupdate; +END; + + + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" +-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" +-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" +-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" +-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_quartus/altpll_reconfig0.bsf b/FPGA_quartus/altpll_reconfig0.bsf new file mode 100644 index 0000000..452f320 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig0.bsf @@ -0,0 +1,162 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 216 296) + (text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 277 31 292)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) + (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) + (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) + (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8))) + (text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8))) + (text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8))) + (text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 16 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8))) + (text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 16 184)(line_width 1)) + ) + (port + (pt 0 208) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8))) + (line (pt 0 208)(pt 16 208)(line_width 1)) + ) + (port + (pt 0 224) + (input) + (text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8))) + (line (pt 0 224)(pt 16 224)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 16 248)(line_width 1)) + ) + (port + (pt 216 40) + (output) + (text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8))) + (text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8))) + (line (pt 216 40)(pt 200 40)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8))) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (port + (pt 216 152) + (output) + (text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8))) + (line (pt 216 152)(pt 200 152)(line_width 1)) + ) + (port + (pt 216 168) + (output) + (text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8))) + (line (pt 216 168)(pt 200 168)(line_width 1)) + ) + (port + (pt 216 200) + (output) + (text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8))) + (line (pt 216 200)(pt 200 200)(line_width 1)) + ) + (port + (pt 216 216) + (output) + (text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8))) + (line (pt 216 216)(pt 200 216)(line_width 1)) + ) + (port + (pt 216 248) + (output) + (text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8))) + (line (pt 216 248)(pt 200 248)(line_width 1)) + ) + (drawing + (line (pt 0 0)(pt 217 0)(line_width 1)) + (line (pt 217 0)(pt 217 297)(line_width 1)) + (line (pt 0 297)(pt 217 297)(line_width 1)) + (line (pt 0 0)(pt 0 297)(line_width 1)) + (line (pt 16 24)(pt 201 24)(line_width 1)) + (line (pt 201 24)(pt 201 273)(line_width 1)) + (line (pt 16 273)(pt 201 273)(line_width 1)) + (line (pt 16 24)(pt 16 273)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll_reconfig0.qip b/FPGA_quartus/altpll_reconfig0.qip new file mode 100644 index 0000000..3194459 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"] diff --git a/FPGA_quartus/altpll_reconfig1.bsf b/FPGA_quartus/altpll_reconfig1.bsf new file mode 100644 index 0000000..f896607 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1.bsf @@ -0,0 +1,162 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 216 296) + (text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 277 31 292)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) + (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) + (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) + (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8))) + (text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8))) + (text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8))) + (text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 16 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8))) + (text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 16 184)(line_width 1)) + ) + (port + (pt 0 208) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8))) + (line (pt 0 208)(pt 16 208)(line_width 1)) + ) + (port + (pt 0 224) + (input) + (text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8))) + (line (pt 0 224)(pt 16 224)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 16 248)(line_width 1)) + ) + (port + (pt 216 40) + (output) + (text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8))) + (text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8))) + (line (pt 216 40)(pt 200 40)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8))) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (port + (pt 216 152) + (output) + (text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8))) + (line (pt 216 152)(pt 200 152)(line_width 1)) + ) + (port + (pt 216 168) + (output) + (text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8))) + (line (pt 216 168)(pt 200 168)(line_width 1)) + ) + (port + (pt 216 200) + (output) + (text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8))) + (line (pt 216 200)(pt 200 200)(line_width 1)) + ) + (port + (pt 216 216) + (output) + (text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8))) + (line (pt 216 216)(pt 200 216)(line_width 1)) + ) + (port + (pt 216 248) + (output) + (text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8))) + (line (pt 216 248)(pt 200 248)(line_width 1)) + ) + (drawing + (line (pt 0 0)(pt 217 0)(line_width 1)) + (line (pt 217 0)(pt 217 297)(line_width 1)) + (line (pt 0 297)(pt 217 297)(line_width 1)) + (line (pt 0 0)(pt 0 297)(line_width 1)) + (line (pt 16 24)(pt 201 24)(line_width 1)) + (line (pt 201 24)(pt 201 273)(line_width 1)) + (line (pt 16 273)(pt 201 273)(line_width 1)) + (line (pt 16 24)(pt 16 273)(line_width 1)) + ) +) diff --git a/FPGA_quartus/altpll_reconfig1.cmp b/FPGA_quartus/altpll_reconfig1.cmp new file mode 100644 index 0000000..7d409d0 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1.cmp @@ -0,0 +1,38 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll_reconfig1 + PORT + ( + clock : IN STD_LOGIC ; + counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset_in : IN STD_LOGIC := '0'; + pll_scandataout : IN STD_LOGIC ; + pll_scandone : IN STD_LOGIC ; + read_param : IN STD_LOGIC ; + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + write_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset : OUT STD_LOGIC ; + pll_configupdate : OUT STD_LOGIC ; + pll_scanclk : OUT STD_LOGIC ; + pll_scanclkena : OUT STD_LOGIC ; + pll_scandata : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_quartus/altpll_reconfig1.inc b/FPGA_quartus/altpll_reconfig1.inc new file mode 100644 index 0000000..c1a6e65 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1.inc @@ -0,0 +1,39 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll_reconfig1 +( + clock, + counter_param[2..0], + counter_type[3..0], + data_in[8..0], + pll_areset_in, + pll_scandataout, + pll_scandone, + read_param, + reconfig, + reset, + write_param +) + +RETURNS ( + busy, + data_out[8..0], + pll_areset, + pll_configupdate, + pll_scanclk, + pll_scanclkena, + pll_scandata +); diff --git a/FPGA_quartus/altpll_reconfig1.qip b/FPGA_quartus/altpll_reconfig1.qip new file mode 100644 index 0000000..713a3c3 --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"] diff --git a/FPGA_quartus/altpll_reconfig1.tdf b/FPGA_quartus/altpll_reconfig1.tdf new file mode 100644 index 0000000..82ad4ff --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1.tdf @@ -0,0 +1,144 @@ +-- megafunction wizard: %ALTPLL_RECONFIG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll_reconfig + +-- ============================================================ +-- File Name: altpll_reconfig1.tdf +-- Megafunction Name(s): +-- altpll_reconfig +-- +-- Simulation Library Files(s): +-- altera_mf;cycloneiii;lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + +-- Clearbox generated function header +FUNCTION altpll_reconfig1_pllrcfg_t4q (clock, counter_param[2..0], counter_type[3..0], data_in[8..0], pll_areset_in, pll_scandataout, pll_scandone, read_param, reconfig, reset, write_param) +RETURNS ( busy, data_out[8..0], pll_areset, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata); + + + + +SUBDESIGN altpll_reconfig1 +( + clock : INPUT; + counter_param[2..0] : INPUT; + counter_type[3..0] : INPUT; + data_in[8..0] : INPUT; + pll_areset_in : INPUT = GND; + pll_scandataout : INPUT; + pll_scandone : INPUT; + read_param : INPUT; + reconfig : INPUT; + reset : INPUT; + write_param : INPUT; + busy : OUTPUT; + data_out[8..0] : OUTPUT; + pll_areset : OUTPUT; + pll_configupdate : OUTPUT; + pll_scanclk : OUTPUT; + pll_scanclkena : OUTPUT; + pll_scandata : OUTPUT; +) + +VARIABLE + + altpll_reconfig1_pllrcfg_t4q_component : altpll_reconfig1_pllrcfg_t4q; + +BEGIN + + pll_areset = altpll_reconfig1_pllrcfg_t4q_component.pll_areset; + pll_scanclkena = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclkena; + pll_scanclk = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclk; + busy = altpll_reconfig1_pllrcfg_t4q_component.busy; + data_out[8..0] = altpll_reconfig1_pllrcfg_t4q_component.data_out[8..0]; + pll_scandata = altpll_reconfig1_pllrcfg_t4q_component.pll_scandata; + pll_configupdate = altpll_reconfig1_pllrcfg_t4q_component.pll_configupdate; + altpll_reconfig1_pllrcfg_t4q_component.reconfig = reconfig; + altpll_reconfig1_pllrcfg_t4q_component.counter_type[3..0] = counter_type[3..0]; + altpll_reconfig1_pllrcfg_t4q_component.pll_scandone = pll_scandone; + altpll_reconfig1_pllrcfg_t4q_component.pll_scandataout = pll_scandataout; + altpll_reconfig1_pllrcfg_t4q_component.pll_areset_in = pll_areset_in; + altpll_reconfig1_pllrcfg_t4q_component.read_param = read_param; + altpll_reconfig1_pllrcfg_t4q_component.reset = reset; + altpll_reconfig1_pllrcfg_t4q_component.data_in[8..0] = data_in[8..0]; + altpll_reconfig1_pllrcfg_t4q_component.clock = clock; + altpll_reconfig1_pllrcfg_t4q_component.counter_param[2..0] = counter_param[2..0]; + altpll_reconfig1_pllrcfg_t4q_component.write_param = write_param; +END; + + + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]" +-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]" +-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]" +-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]" +-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset" +-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in" +-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate" +-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk" +-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena" +-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata" +-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout" +-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone" +-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param" +-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig" +-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset" +-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param" +-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0 +-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0 +-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0 +-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0 +-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0 +-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0 +-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0 +-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0 +-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0 +-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0 +-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0 +-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0 +-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.tdf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.tdf FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: LIB_FILE: cycloneiii +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/altpll_reconfig1_pllrcfg_bju.tdf b/FPGA_quartus/altpll_reconfig1_pllrcfg_bju.tdf new file mode 100644 index 0000000..81695ae --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1_pllrcfg_bju.tdf @@ -0,0 +1,583 @@ +--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./altpll4.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param +--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +include "altsyncram.inc"; +FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS) +RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]); +FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT) +RETURNS ( aeb, agb, ageb, alb, aleb, aneb); +FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown) +WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width) +RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]); +FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable) +WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH) +RETURNS ( eq[LPM_DECODES-1..0]); + +--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 +OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW"; + +SUBDESIGN altpll_reconfig1_pllrcfg_bju +( + busy : output; + clock : input; + counter_param[2..0] : input; + counter_type[3..0] : input; + data_in[8..0] : input; + data_out[8..0] : output; + pll_areset : output; + pll_areset_in : input; + pll_configupdate : output; + pll_scanclk : output; + pll_scanclkena : output; + pll_scandata : output; + pll_scandataout : input; + pll_scandone : input; + read_param : input; + reconfig : input; + reset : input; + write_param : input; +) +VARIABLE + altsyncram4 : altsyncram + WITH ( + INIT_FILE = "./altpll4.mif", + NUMWORDS_A = 144, + OPERATION_MODE = "SINGLE_PORT", + WIDTH_A = 1, + WIDTH_BYTEENA_A = 1, + WIDTHAD_A = 8 + ); + le_comb10 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "F0F0", + SUM_LUTC_INPUT = "datac" + ); + le_comb8 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "AAAA", + SUM_LUTC_INPUT = "datac" + ); + le_comb9 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "CCCC", + SUM_LUTC_INPUT = "datac" + ); + areset_init_state_1 : dffe; + areset_state : dffe; + C0_data_state : dffe; + C0_ena_state : dffe; + C1_data_state : dffe; + C1_ena_state : dffe; + C2_data_state : dffe; + C2_ena_state : dffe; + C3_data_state : dffe; + C3_ena_state : dffe; + C4_data_state : dffe; + C4_ena_state : dffe; + configupdate2_state : dffe; + configupdate3_state : dffe; + configupdate_state : dffe; + counter_param_latch_reg[2..0] : dffe; + counter_type_latch_reg[3..0] : dffe; + idle_state : dffe + WITH ( + power_up = "low" + ); + nominal_data[17..0] : dffe; + read_data_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_data_state : dffe + WITH ( + power_up = "low" + ); + read_first_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_first_state : dffe + WITH ( + power_up = "low" + ); + read_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_init_state : dffe + WITH ( + power_up = "low" + ); + read_last_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_last_state : dffe + WITH ( + power_up = "low" + ); + reconfig_counter_state : dffe + WITH ( + power_up = "low" + ); + reconfig_init_state : dffe + WITH ( + power_up = "low" + ); + reconfig_post_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_data_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_ena_state : dffe + WITH ( + power_up = "low" + ); + reconfig_wait_state : dffe + WITH ( + power_up = "low" + ); + reset_state : dffe + WITH ( + power_up = "high" + ); + shift_reg[17..0] : dffeas; + tmp_nominal_data_out_state : dffe; + tmp_seq_ena_state : dffe; + write_data_state : dffe + WITH ( + power_up = "low" + ); + write_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + write_init_state : dffe + WITH ( + power_up = "low" + ); + write_nominal_state : dffe + WITH ( + power_up = "low" + ); + add_sub5 : lpm_add_sub + WITH ( + LPM_WIDTH = 9 + ); + add_sub6 : lpm_add_sub + WITH ( + LPM_WIDTH = 8 + ); + cmpr7 : lpm_compare + WITH ( + LPM_WIDTH = 8 + ); + cntr1 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr12 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr13 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 6 + ); + cntr14 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + cntr15 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr2 : lpm_counter + WITH ( + lpm_direction = "UP", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr3 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + decode11 : lpm_decode + WITH ( + LPM_DECODES = 5, + LPM_WIDTH = 3 + ); + addr_counter_enable : WIRE; + addr_counter_out[7..0] : WIRE; + addr_counter_sload : WIRE; + addr_counter_sload_value[7..0] : WIRE; + addr_decoder_out[7..0] : WIRE; + c0_wire[7..0] : WIRE; + c1_wire[7..0] : WIRE; + c2_wire[7..0] : WIRE; + c3_wire[7..0] : WIRE; + c4_wire[7..0] : WIRE; + counter_param_latch[2..0] : WIRE; + counter_type_latch[3..0] : WIRE; + cuda_combout_wire[2..0] : WIRE; + dummy_scandataout : WIRE; + encode_out[2..0] : WIRE; + input_latch_enable : WIRE; + power_up : WIRE; + read_addr_counter_enable : WIRE; + read_addr_counter_out[7..0] : WIRE; + read_addr_counter_sload : WIRE; + read_addr_counter_sload_value[7..0] : WIRE; + read_addr_decoder_out[7..0] : WIRE; + read_nominal_out : WIRE; + reconfig_addr_counter_enable : WIRE; + reconfig_addr_counter_out[7..0] : WIRE; + reconfig_addr_counter_sload : WIRE; + reconfig_addr_counter_sload_value[7..0] : WIRE; + reconfig_done : WIRE; + reconfig_post_done : WIRE; + reconfig_width_counter_done : WIRE; + reconfig_width_counter_enable : WIRE; + reconfig_width_counter_sload : WIRE; + reconfig_width_counter_sload_value[5..0] : WIRE; + rotate_addr_counter_enable : WIRE; + rotate_addr_counter_out[7..0] : WIRE; + rotate_addr_counter_sload : WIRE; + rotate_addr_counter_sload_value[7..0] : WIRE; + rotate_decoder_wires[4..0] : WIRE; + rotate_width_counter_done : WIRE; + rotate_width_counter_enable : WIRE; + rotate_width_counter_sload : WIRE; + rotate_width_counter_sload_value[4..0] : WIRE; + scan_cache_address[7..0] : WIRE; + scan_cache_in : WIRE; + scan_cache_out : WIRE; + scan_cache_write_enable : WIRE; + sel_param_bypass_LF_unused : WIRE; + sel_param_c : WIRE; + sel_param_high_i_postscale : WIRE; + sel_param_low_r : WIRE; + sel_param_nominal_count : WIRE; + sel_param_odd_CP_unused : WIRE; + sel_type_c0 : WIRE; + sel_type_c1 : WIRE; + sel_type_c2 : WIRE; + sel_type_c3 : WIRE; + sel_type_c4 : WIRE; + sel_type_cplf : WIRE; + sel_type_m : WIRE; + sel_type_n : WIRE; + sel_type_vco : WIRE; + seq_addr_wire[7..0] : WIRE; + seq_sload_value[5..0] : WIRE; + shift_reg_clear : WIRE; + shift_reg_load_enable : WIRE; + shift_reg_load_nominal_enable : WIRE; + shift_reg_serial_in : WIRE; + shift_reg_serial_out : WIRE; + shift_reg_shift_enable : WIRE; + shift_reg_shift_nominal_enable : WIRE; + shift_reg_width_select[7..0] : WIRE; + w1565w : WIRE; + w1592w : WIRE; + w64w : WIRE; + width_counter_done : WIRE; + width_counter_enable : WIRE; + width_counter_sload : WIRE; + width_counter_sload_value[4..0] : WIRE; + width_decoder_out[4..0] : WIRE; + width_decoder_select[7..0] : WIRE; + write_from_rom : NODE; + +BEGIN + altsyncram4.address_a[] = scan_cache_address[]; + altsyncram4.clock0 = clock; + altsyncram4.data_a[] = ( scan_cache_in); + altsyncram4.wren_a = scan_cache_write_enable; + le_comb10.dataa = encode_out[0..0]; + le_comb10.datab = encode_out[1..1]; + le_comb10.datac = encode_out[2..2]; + le_comb8.dataa = encode_out[0..0]; + le_comb8.datab = encode_out[1..1]; + le_comb8.datac = encode_out[2..2]; + le_comb9.dataa = encode_out[0..0]; + le_comb9.datab = encode_out[1..1]; + le_comb9.datac = encode_out[2..2]; + areset_init_state_1.clk = clock; + areset_init_state_1.d = pll_scandone; + areset_state.clk = clock; + areset_state.d = (areset_init_state_1.q & (! reset)); + C0_data_state.clk = clock; + C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done))); + C0_ena_state.clk = clock; + C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done); + C1_data_state.clk = clock; + C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done))); + C1_ena_state.clk = clock; + C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done); + C2_data_state.clk = clock; + C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done))); + C2_ena_state.clk = clock; + C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done); + C3_data_state.clk = clock; + C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done))); + C3_ena_state.clk = clock; + C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done); + C4_data_state.clk = clock; + C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done))); + C4_ena_state.clk = clock; + C4_ena_state.d = reconfig_init_state.q; + configupdate2_state.clk = clock; + configupdate2_state.d = configupdate_state.q; + configupdate3_state.clk = (! clock); + configupdate3_state.d = configupdate2_state.q; + configupdate_state.clk = clock; + configupdate_state.d = reconfig_post_state.q; + counter_param_latch_reg[].clk = clock; + counter_param_latch_reg[].clrn = (! reset); + counter_param_latch_reg[].d = counter_param[]; + counter_param_latch_reg[].ena = input_latch_enable; + counter_type_latch_reg[].clk = clock; + counter_type_latch_reg[].clrn = (! reset); + counter_type_latch_reg[].d = counter_type[]; + counter_type_latch_reg[].ena = input_latch_enable; + idle_state.clk = clock; + idle_state.clrn = (! reset); + idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q); + nominal_data[].clk = clock; + nominal_data[].clrn = (! reset); + nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]); + read_data_nominal_state.clk = clock; + read_data_nominal_state.clrn = (! reset); + read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done))); + read_data_state.clk = clock; + read_data_state.clrn = (! reset); + read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done))); + read_first_nominal_state.clk = clock; + read_first_nominal_state.clrn = (! reset); + read_first_nominal_state.d = read_init_nominal_state.q; + read_first_state.clk = clock; + read_first_state.clrn = (! reset); + read_first_state.d = read_init_state.q; + read_init_nominal_state.clk = clock; + read_init_nominal_state.clrn = (! reset); + read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + read_init_state.clk = clock; + read_init_state.clrn = (! reset); + read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + read_last_nominal_state.clk = clock; + read_last_nominal_state.clrn = (! reset); + read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done)); + read_last_state.clk = clock; + read_last_state.clrn = (! reset); + read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done)); + reconfig_counter_state.clk = clock; + reconfig_counter_state.clrn = (! reset); + reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + reconfig_init_state.clk = clock; + reconfig_init_state.clrn = (! reset); + reconfig_init_state.d = (idle_state.q & reconfig); + reconfig_post_state.clk = clock; + reconfig_post_state.clrn = (! reset); + reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done))); + reconfig_seq_data_state.clk = clock; + reconfig_seq_data_state.clrn = (! reset); + reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done))); + reconfig_seq_ena_state.clk = clock; + reconfig_seq_ena_state.clrn = (! reset); + reconfig_seq_ena_state.d = tmp_seq_ena_state.q; + reconfig_wait_state.clk = clock; + reconfig_wait_state.clrn = (! reset); + reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done))); + reset_state.clk = clock; + reset_state.d = power_up; + reset_state.prn = (! reset); + shift_reg[].clk = clock; + shift_reg[].clrn = (! reset); + shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in))); + shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear); + shift_reg[].sclr = shift_reg_clear; + tmp_nominal_data_out_state.clk = clock; + tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q)); + tmp_seq_ena_state.clk = clock; + tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done)); + write_data_state.clk = clock; + write_data_state.clrn = (! reset); + write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done))); + write_init_nominal_state.clk = clock; + write_init_nominal_state.clrn = (! reset); + write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + write_init_state.clk = clock; + write_init_state.clrn = (! reset); + write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + write_nominal_state.clk = clock; + write_nominal_state.clrn = (! reset); + write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done))); + add_sub5.cin = B"0"; + add_sub5.dataa[] = ( B"0", shift_reg[8..1].q); + add_sub5.datab[] = ( B"0", shift_reg[17..10].q); + add_sub6.cin = data_in[0..0]; + add_sub6.dataa[] = ( data_in[8..1]); + cmpr7.dataa[] = ( data_in[7..0]); + cmpr7.datab[] = B"00000001"; + cntr1.clock = clock; + cntr1.cnt_en = addr_counter_enable; + cntr1.data[] = addr_counter_sload_value[]; + cntr1.sload = addr_counter_sload; + cntr12.clock = clock; + cntr12.cnt_en = reconfig_addr_counter_enable; + cntr12.data[] = reconfig_addr_counter_sload_value[]; + cntr12.sload = reconfig_addr_counter_sload; + cntr13.clock = clock; + cntr13.cnt_en = reconfig_width_counter_enable; + cntr13.data[] = reconfig_width_counter_sload_value[]; + cntr13.sload = reconfig_width_counter_sload; + cntr14.clock = clock; + cntr14.cnt_en = rotate_width_counter_enable; + cntr14.data[] = rotate_width_counter_sload_value[]; + cntr14.sload = rotate_width_counter_sload; + cntr15.clock = clock; + cntr15.cnt_en = rotate_addr_counter_enable; + cntr15.data[] = rotate_addr_counter_sload_value[]; + cntr15.sload = rotate_addr_counter_sload; + cntr2.clock = clock; + cntr2.cnt_en = read_addr_counter_enable; + cntr2.data[] = read_addr_counter_sload_value[]; + cntr2.sload = read_addr_counter_sload; + cntr3.clock = clock; + cntr3.cnt_en = width_counter_enable; + cntr3.data[] = width_counter_sload_value[]; + cntr3.sload = width_counter_sload; + decode11.data[] = cuda_combout_wire[]; + addr_counter_enable = (write_data_state.q # write_nominal_state.q); + addr_counter_out[] = cntr1.q[]; + addr_counter_sload = (write_init_state.q # write_init_nominal_state.q); + addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q)); + addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r))); + busy = ((! idle_state.q) # areset_state.q); + c0_wire[] = B"01000111"; + c1_wire[] = B"01011001"; + c2_wire[] = B"01101011"; + c3_wire[] = B"01111101"; + c4_wire[] = B"10001111"; + counter_param_latch[] = counter_param_latch_reg[].q; + counter_type_latch[] = counter_type_latch_reg[].q; + cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout); + data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out))); + dummy_scandataout = pll_scandataout; + encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q)); + input_latch_enable = (idle_state.q & (write_param # read_param)); + pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q)); + pll_configupdate = (configupdate_state.q & (! configupdate3_state.q)); + pll_scanclk = clock; + pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q); + pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q)); + power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q)); + read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q); + read_addr_counter_out[] = cntr2.q[]; + read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q); + read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q)); + read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0")); + read_nominal_out = tmp_nominal_data_out_state.q; + reconfig_addr_counter_enable = reconfig_seq_data_state.q; + reconfig_addr_counter_out[] = cntr12.q[]; + reconfig_addr_counter_sload = reconfig_seq_ena_state.q; + reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]); + reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout))); + reconfig_post_done = pll_scandone; + reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5])); + reconfig_width_counter_enable = reconfig_seq_data_state.q; + reconfig_width_counter_sload = reconfig_seq_ena_state.q; + reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]); + rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_addr_counter_out[] = cntr15.q[]; + rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4])); + rotate_decoder_wires[] = decode11.eq[]; + rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4])); + rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_width_counter_sload_value[] = B"10010"; + scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable)); + scan_cache_in = shift_reg_serial_out; + scan_cache_out = altsyncram4.q_a[0..0]; + scan_cache_write_enable = (write_data_state.q # write_nominal_state.q); + sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2])); + sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]); + sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]); + sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + seq_addr_wire[] = B"00110101"; + seq_sload_value[] = B"110110"; + shift_reg_clear = (read_init_state.q # read_init_nominal_state.q); + shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + shift_reg_serial_in = scan_cache_out; + shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7])); + shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q); + shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q); + shift_reg_width_select[] = width_decoder_select[]; + w1565w = B"0"; + w1592w = B"0"; + w64w = B"0"; + width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4])); + width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q); + width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q); + width_counter_sload_value[] = width_decoder_out[]; + width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0")); + width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused))); + write_from_rom = GND; +END; +--VALID FILE diff --git a/FPGA_quartus/altpll_reconfig1_pllrcfg_t4q.tdf b/FPGA_quartus/altpll_reconfig1_pllrcfg_t4q.tdf new file mode 100644 index 0000000..fae939f --- /dev/null +++ b/FPGA_quartus/altpll_reconfig1_pllrcfg_t4q.tdf @@ -0,0 +1,582 @@ +--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param +--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +include "altsyncram.inc"; +FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS) +RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]); +FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT) +RETURNS ( aeb, agb, ageb, alb, aleb, aneb); +FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown) +WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width) +RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]); +FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable) +WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH) +RETURNS ( eq[LPM_DECODES-1..0]); + +--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 +OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW"; + +SUBDESIGN altpll_reconfig1_pllrcfg_t4q +( + busy : output; + clock : input; + counter_param[2..0] : input; + counter_type[3..0] : input; + data_in[8..0] : input; + data_out[8..0] : output; + pll_areset : output; + pll_areset_in : input; + pll_configupdate : output; + pll_scanclk : output; + pll_scanclkena : output; + pll_scandata : output; + pll_scandataout : input; + pll_scandone : input; + read_param : input; + reconfig : input; + reset : input; + write_param : input; +) +VARIABLE + altsyncram4 : altsyncram + WITH ( + NUMWORDS_A = 144, + OPERATION_MODE = "SINGLE_PORT", + WIDTH_A = 1, + WIDTH_BYTEENA_A = 1, + WIDTHAD_A = 8 + ); + le_comb10 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "F0F0", + SUM_LUTC_INPUT = "datac" + ); + le_comb8 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "AAAA", + SUM_LUTC_INPUT = "datac" + ); + le_comb9 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "CCCC", + SUM_LUTC_INPUT = "datac" + ); + areset_init_state_1 : dffe; + areset_state : dffe; + C0_data_state : dffe; + C0_ena_state : dffe; + C1_data_state : dffe; + C1_ena_state : dffe; + C2_data_state : dffe; + C2_ena_state : dffe; + C3_data_state : dffe; + C3_ena_state : dffe; + C4_data_state : dffe; + C4_ena_state : dffe; + configupdate2_state : dffe; + configupdate3_state : dffe; + configupdate_state : dffe; + counter_param_latch_reg[2..0] : dffe; + counter_type_latch_reg[3..0] : dffe; + idle_state : dffe + WITH ( + power_up = "low" + ); + nominal_data[17..0] : dffe; + read_data_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_data_state : dffe + WITH ( + power_up = "low" + ); + read_first_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_first_state : dffe + WITH ( + power_up = "low" + ); + read_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_init_state : dffe + WITH ( + power_up = "low" + ); + read_last_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_last_state : dffe + WITH ( + power_up = "low" + ); + reconfig_counter_state : dffe + WITH ( + power_up = "low" + ); + reconfig_init_state : dffe + WITH ( + power_up = "low" + ); + reconfig_post_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_data_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_ena_state : dffe + WITH ( + power_up = "low" + ); + reconfig_wait_state : dffe + WITH ( + power_up = "low" + ); + reset_state : dffe + WITH ( + power_up = "high" + ); + shift_reg[17..0] : dffeas; + tmp_nominal_data_out_state : dffe; + tmp_seq_ena_state : dffe; + write_data_state : dffe + WITH ( + power_up = "low" + ); + write_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + write_init_state : dffe + WITH ( + power_up = "low" + ); + write_nominal_state : dffe + WITH ( + power_up = "low" + ); + add_sub5 : lpm_add_sub + WITH ( + LPM_WIDTH = 9 + ); + add_sub6 : lpm_add_sub + WITH ( + LPM_WIDTH = 8 + ); + cmpr7 : lpm_compare + WITH ( + LPM_WIDTH = 8 + ); + cntr1 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr12 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr13 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 6 + ); + cntr14 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + cntr15 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr2 : lpm_counter + WITH ( + lpm_direction = "UP", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr3 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + decode11 : lpm_decode + WITH ( + LPM_DECODES = 5, + LPM_WIDTH = 3 + ); + addr_counter_enable : WIRE; + addr_counter_out[7..0] : WIRE; + addr_counter_sload : WIRE; + addr_counter_sload_value[7..0] : WIRE; + addr_decoder_out[7..0] : WIRE; + c0_wire[7..0] : WIRE; + c1_wire[7..0] : WIRE; + c2_wire[7..0] : WIRE; + c3_wire[7..0] : WIRE; + c4_wire[7..0] : WIRE; + counter_param_latch[2..0] : WIRE; + counter_type_latch[3..0] : WIRE; + cuda_combout_wire[2..0] : WIRE; + dummy_scandataout : WIRE; + encode_out[2..0] : WIRE; + input_latch_enable : WIRE; + power_up : WIRE; + read_addr_counter_enable : WIRE; + read_addr_counter_out[7..0] : WIRE; + read_addr_counter_sload : WIRE; + read_addr_counter_sload_value[7..0] : WIRE; + read_addr_decoder_out[7..0] : WIRE; + read_nominal_out : WIRE; + reconfig_addr_counter_enable : WIRE; + reconfig_addr_counter_out[7..0] : WIRE; + reconfig_addr_counter_sload : WIRE; + reconfig_addr_counter_sload_value[7..0] : WIRE; + reconfig_done : WIRE; + reconfig_post_done : WIRE; + reconfig_width_counter_done : WIRE; + reconfig_width_counter_enable : WIRE; + reconfig_width_counter_sload : WIRE; + reconfig_width_counter_sload_value[5..0] : WIRE; + rotate_addr_counter_enable : WIRE; + rotate_addr_counter_out[7..0] : WIRE; + rotate_addr_counter_sload : WIRE; + rotate_addr_counter_sload_value[7..0] : WIRE; + rotate_decoder_wires[4..0] : WIRE; + rotate_width_counter_done : WIRE; + rotate_width_counter_enable : WIRE; + rotate_width_counter_sload : WIRE; + rotate_width_counter_sload_value[4..0] : WIRE; + scan_cache_address[7..0] : WIRE; + scan_cache_in : WIRE; + scan_cache_out : WIRE; + scan_cache_write_enable : WIRE; + sel_param_bypass_LF_unused : WIRE; + sel_param_c : WIRE; + sel_param_high_i_postscale : WIRE; + sel_param_low_r : WIRE; + sel_param_nominal_count : WIRE; + sel_param_odd_CP_unused : WIRE; + sel_type_c0 : WIRE; + sel_type_c1 : WIRE; + sel_type_c2 : WIRE; + sel_type_c3 : WIRE; + sel_type_c4 : WIRE; + sel_type_cplf : WIRE; + sel_type_m : WIRE; + sel_type_n : WIRE; + sel_type_vco : WIRE; + seq_addr_wire[7..0] : WIRE; + seq_sload_value[5..0] : WIRE; + shift_reg_clear : WIRE; + shift_reg_load_enable : WIRE; + shift_reg_load_nominal_enable : WIRE; + shift_reg_serial_in : WIRE; + shift_reg_serial_out : WIRE; + shift_reg_shift_enable : WIRE; + shift_reg_shift_nominal_enable : WIRE; + shift_reg_width_select[7..0] : WIRE; + w1565w : WIRE; + w1592w : WIRE; + w64w : WIRE; + width_counter_done : WIRE; + width_counter_enable : WIRE; + width_counter_sload : WIRE; + width_counter_sload_value[4..0] : WIRE; + width_decoder_out[4..0] : WIRE; + width_decoder_select[7..0] : WIRE; + write_from_rom : NODE; + +BEGIN + altsyncram4.address_a[] = scan_cache_address[]; + altsyncram4.clock0 = clock; + altsyncram4.data_a[] = ( scan_cache_in); + altsyncram4.wren_a = scan_cache_write_enable; + le_comb10.dataa = encode_out[0..0]; + le_comb10.datab = encode_out[1..1]; + le_comb10.datac = encode_out[2..2]; + le_comb8.dataa = encode_out[0..0]; + le_comb8.datab = encode_out[1..1]; + le_comb8.datac = encode_out[2..2]; + le_comb9.dataa = encode_out[0..0]; + le_comb9.datab = encode_out[1..1]; + le_comb9.datac = encode_out[2..2]; + areset_init_state_1.clk = clock; + areset_init_state_1.d = pll_scandone; + areset_state.clk = clock; + areset_state.d = (areset_init_state_1.q & (! reset)); + C0_data_state.clk = clock; + C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done))); + C0_ena_state.clk = clock; + C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done); + C1_data_state.clk = clock; + C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done))); + C1_ena_state.clk = clock; + C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done); + C2_data_state.clk = clock; + C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done))); + C2_ena_state.clk = clock; + C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done); + C3_data_state.clk = clock; + C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done))); + C3_ena_state.clk = clock; + C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done); + C4_data_state.clk = clock; + C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done))); + C4_ena_state.clk = clock; + C4_ena_state.d = reconfig_init_state.q; + configupdate2_state.clk = clock; + configupdate2_state.d = configupdate_state.q; + configupdate3_state.clk = (! clock); + configupdate3_state.d = configupdate2_state.q; + configupdate_state.clk = clock; + configupdate_state.d = reconfig_post_state.q; + counter_param_latch_reg[].clk = clock; + counter_param_latch_reg[].clrn = (! reset); + counter_param_latch_reg[].d = counter_param[]; + counter_param_latch_reg[].ena = input_latch_enable; + counter_type_latch_reg[].clk = clock; + counter_type_latch_reg[].clrn = (! reset); + counter_type_latch_reg[].d = counter_type[]; + counter_type_latch_reg[].ena = input_latch_enable; + idle_state.clk = clock; + idle_state.clrn = (! reset); + idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q); + nominal_data[].clk = clock; + nominal_data[].clrn = (! reset); + nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]); + read_data_nominal_state.clk = clock; + read_data_nominal_state.clrn = (! reset); + read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done))); + read_data_state.clk = clock; + read_data_state.clrn = (! reset); + read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done))); + read_first_nominal_state.clk = clock; + read_first_nominal_state.clrn = (! reset); + read_first_nominal_state.d = read_init_nominal_state.q; + read_first_state.clk = clock; + read_first_state.clrn = (! reset); + read_first_state.d = read_init_state.q; + read_init_nominal_state.clk = clock; + read_init_nominal_state.clrn = (! reset); + read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + read_init_state.clk = clock; + read_init_state.clrn = (! reset); + read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + read_last_nominal_state.clk = clock; + read_last_nominal_state.clrn = (! reset); + read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done)); + read_last_state.clk = clock; + read_last_state.clrn = (! reset); + read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done)); + reconfig_counter_state.clk = clock; + reconfig_counter_state.clrn = (! reset); + reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + reconfig_init_state.clk = clock; + reconfig_init_state.clrn = (! reset); + reconfig_init_state.d = (idle_state.q & reconfig); + reconfig_post_state.clk = clock; + reconfig_post_state.clrn = (! reset); + reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done))); + reconfig_seq_data_state.clk = clock; + reconfig_seq_data_state.clrn = (! reset); + reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done))); + reconfig_seq_ena_state.clk = clock; + reconfig_seq_ena_state.clrn = (! reset); + reconfig_seq_ena_state.d = tmp_seq_ena_state.q; + reconfig_wait_state.clk = clock; + reconfig_wait_state.clrn = (! reset); + reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done))); + reset_state.clk = clock; + reset_state.d = power_up; + reset_state.prn = (! reset); + shift_reg[].clk = clock; + shift_reg[].clrn = (! reset); + shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in))); + shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear); + shift_reg[].sclr = shift_reg_clear; + tmp_nominal_data_out_state.clk = clock; + tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q)); + tmp_seq_ena_state.clk = clock; + tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done)); + write_data_state.clk = clock; + write_data_state.clrn = (! reset); + write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done))); + write_init_nominal_state.clk = clock; + write_init_nominal_state.clrn = (! reset); + write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + write_init_state.clk = clock; + write_init_state.clrn = (! reset); + write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + write_nominal_state.clk = clock; + write_nominal_state.clrn = (! reset); + write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done))); + add_sub5.cin = B"0"; + add_sub5.dataa[] = ( B"0", shift_reg[8..1].q); + add_sub5.datab[] = ( B"0", shift_reg[17..10].q); + add_sub6.cin = data_in[0..0]; + add_sub6.dataa[] = ( data_in[8..1]); + cmpr7.dataa[] = ( data_in[7..0]); + cmpr7.datab[] = B"00000001"; + cntr1.clock = clock; + cntr1.cnt_en = addr_counter_enable; + cntr1.data[] = addr_counter_sload_value[]; + cntr1.sload = addr_counter_sload; + cntr12.clock = clock; + cntr12.cnt_en = reconfig_addr_counter_enable; + cntr12.data[] = reconfig_addr_counter_sload_value[]; + cntr12.sload = reconfig_addr_counter_sload; + cntr13.clock = clock; + cntr13.cnt_en = reconfig_width_counter_enable; + cntr13.data[] = reconfig_width_counter_sload_value[]; + cntr13.sload = reconfig_width_counter_sload; + cntr14.clock = clock; + cntr14.cnt_en = rotate_width_counter_enable; + cntr14.data[] = rotate_width_counter_sload_value[]; + cntr14.sload = rotate_width_counter_sload; + cntr15.clock = clock; + cntr15.cnt_en = rotate_addr_counter_enable; + cntr15.data[] = rotate_addr_counter_sload_value[]; + cntr15.sload = rotate_addr_counter_sload; + cntr2.clock = clock; + cntr2.cnt_en = read_addr_counter_enable; + cntr2.data[] = read_addr_counter_sload_value[]; + cntr2.sload = read_addr_counter_sload; + cntr3.clock = clock; + cntr3.cnt_en = width_counter_enable; + cntr3.data[] = width_counter_sload_value[]; + cntr3.sload = width_counter_sload; + decode11.data[] = cuda_combout_wire[]; + addr_counter_enable = (write_data_state.q # write_nominal_state.q); + addr_counter_out[] = cntr1.q[]; + addr_counter_sload = (write_init_state.q # write_init_nominal_state.q); + addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q)); + addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r))); + busy = ((! idle_state.q) # areset_state.q); + c0_wire[] = B"01000111"; + c1_wire[] = B"01011001"; + c2_wire[] = B"01101011"; + c3_wire[] = B"01111101"; + c4_wire[] = B"10001111"; + counter_param_latch[] = counter_param_latch_reg[].q; + counter_type_latch[] = counter_type_latch_reg[].q; + cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout); + data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out))); + dummy_scandataout = pll_scandataout; + encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q)); + input_latch_enable = (idle_state.q & (write_param # read_param)); + pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q)); + pll_configupdate = (configupdate_state.q & (! configupdate3_state.q)); + pll_scanclk = clock; + pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q); + pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q)); + power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q)); + read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q); + read_addr_counter_out[] = cntr2.q[]; + read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q); + read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q)); + read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0")); + read_nominal_out = tmp_nominal_data_out_state.q; + reconfig_addr_counter_enable = reconfig_seq_data_state.q; + reconfig_addr_counter_out[] = cntr12.q[]; + reconfig_addr_counter_sload = reconfig_seq_ena_state.q; + reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]); + reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout))); + reconfig_post_done = pll_scandone; + reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5])); + reconfig_width_counter_enable = reconfig_seq_data_state.q; + reconfig_width_counter_sload = reconfig_seq_ena_state.q; + reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]); + rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_addr_counter_out[] = cntr15.q[]; + rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4])); + rotate_decoder_wires[] = decode11.eq[]; + rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4])); + rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_width_counter_sload_value[] = B"10010"; + scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable)); + scan_cache_in = shift_reg_serial_out; + scan_cache_out = altsyncram4.q_a[0..0]; + scan_cache_write_enable = (write_data_state.q # write_nominal_state.q); + sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2])); + sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]); + sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]); + sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + seq_addr_wire[] = B"00110101"; + seq_sload_value[] = B"110110"; + shift_reg_clear = (read_init_state.q # read_init_nominal_state.q); + shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + shift_reg_serial_in = scan_cache_out; + shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7])); + shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q); + shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q); + shift_reg_width_select[] = width_decoder_select[]; + w1565w = B"0"; + w1592w = B"0"; + w64w = B"0"; + width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4])); + width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q); + width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q); + width_counter_sload_value[] = width_decoder_out[]; + width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0")); + width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused))); + write_from_rom = GND; +END; +--VALID FILE diff --git a/FPGA_quartus/firebee1.asm.rpt b/FPGA_quartus/firebee1.asm.rpt new file mode 100644 index 0000000..7ffb13e --- /dev/null +++ b/FPGA_quartus/firebee1.asm.rpt @@ -0,0 +1,128 @@ +Assembler report for firebee1 +Wed Dec 15 02:25:13 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof + 6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Dec 15 02:25:13 2010 ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+------------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+------------+---------------+ +; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ; +; Hexadecimal Output File start address ; 0XE0700000 ; 0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+------------+---------------+ + + ++------------------------------+ +; Assembler Generated Files ; ++------------------------------+ +; File Name ; ++------------------------------+ +; C:/FireBee/FPGA/firebee1.sof ; +; C:/FireBee/FPGA/firebee1.rbf ; ++------------------------------+ + + ++--------------------------------------------------------+ +; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ; ++----------------+---------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------+ +; Device ; EP3C40F484C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x0085E8C6 ; ++----------------+---------------------------------------+ + + ++--------------------------------------------------------+ +; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ; ++---------------------+----------------------------------+ +; Option ; Setting ; ++---------------------+----------------------------------+ +; Raw Binary File ; ; +; Compression Ratio ; 2 ; ++---------------------+----------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:25:08 2010 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 291 megabytes + Info: Processing ended: Wed Dec 15 02:25:13 2010 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/FPGA_quartus/firebee1.bdf b/FPGA_quartus/firebee1.bdf new file mode 100644 index 0000000..46507a2 --- /dev/null +++ b/FPGA_quartus/firebee1.bdf @@ -0,0 +1,5837 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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1400) +) +(connector + (text "ACP_CONF[31..0]" (rect 1682 2568 1797 2583)(font "Arial" )) + (pt 1672 2584) + (pt 1832 2584) + (bus) +) +(connector + (text "ACP_CONF[31..24]" (rect 1146 2064 1269 2079)(font "Arial" )) + (pt 1136 2080) + (pt 1264 2080) + (bus) +) +(connector + (text "TIN0" (rect 1682 2624 1712 2639)(font "Arial" )) + (pt 1832 2640) + (pt 1672 2640) +) +(connector + (pt 1896 -48) + (pt 1856 -48) +) +(connector + (pt 1856 -48) + (pt 1856 -64) +) +(connector + (pt 1856 -64) + (pt 1896 -64) +) +(connector + (pt 2464 -64) + (pt 2424 -64) +) +(connector + (pt 2424 -80) + (pt 2424 -64) +) +(connector + (text "HD_DD" (rect 1050 1616 1100 1631)(font "Arial" )) + (pt 1040 1632) + (pt 1264 1632) +) +(connector + (text "CLK48M" (rect 754 40 809 55)(font "Arial" )) + (pt 744 56) + (pt 840 56) +) +(connector + (text "CLK25M" (rect 754 16 809 31)(font "Arial" )) + (pt 744 32) + (pt 864 32) +) +(connector + (text "DDRCLK[0]" (rect 762 -296 837 -281)(font "Arial" )) + (pt 752 -280) + (pt 848 -280) +) +(connector + (text "DDRCLK[1]" (rect 762 -272 837 -257)(font "Arial" )) + (pt 752 -256) + (pt 848 -256) +) +(connector + (text "DDRCLK[2]" (rect 762 -248 837 -233)(font "Arial" )) + (pt 752 -232) + (pt 848 -232) +) +(connector + (text "DDRCLK[3]" (rect 762 -224 837 -209)(font "Arial" )) + (pt 752 -208) + (pt 848 -208) +) +(connector + (text "DDR_SYNC_66M" (rect 762 -200 876 -185)(font "Arial" )) + (pt 752 -184) + (pt 848 -184) +) +(connector + (pt 408 672) + (pt 472 672) +) +(connector + (text "VIDEO_RECONFIG" (rect 74 496 199 511)(font "Arial" )) + (pt 192 512) + (pt 64 512) +) +(connector + (text "MAIN_CLK" (rect 330 -296 399 -281)(font "Arial" )) + (pt 264 -280) + (pt 448 -280) +) +(connector + (pt 408 640) + (pt 472 640) +) +(connector + (pt 408 624) + (pt 512 624) +) +(connector + (text "VR_D[8..0]" (rect 418 552 486 567)(font "Arial" )) + (pt 496 568) + (pt 408 568) + (bus) +) +(connector + (text "MAIN_CLK" (rect 122 664 191 679)(font "Arial" )) + (pt 112 680) + (pt 192 680) +) +(connector + (pt 536 720) + (pt 408 720) +) +(connector + (pt 1064 808) + (pt 1064 616) +) +(connector + (pt 1072 816) + (pt 1072 592) +) +(connector + (pt 472 672) + (pt 472 664) +) +(connector + (pt 472 640) + (pt 472 616) +) +(connector + (pt 512 624) + (pt 512 640) +) +(connector + (pt 536 720) + (pt 536 592) +) +(connector + (pt 536 592) + (pt 608 592) +) +(connector + (pt 472 616) + (pt 608 616) +) +(connector + (pt 512 640) + (pt 608 640) +) +(connector + (pt 472 664) + (pt 608 664) +) +(connector + (pt 408 688) + (pt 608 688) +) +(connector + (pt 984 592) + (pt 1072 592) +) +(connector + (pt 984 616) + (pt 1064 616) +) +(connector + (text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" )) + (pt 192 584) + (pt 72 584) + (bus) +) +(connector + (pt 1064 808) + (pt 80 808) +) +(connector + (pt 192 656) + (pt 80 656) +) +(connector + (pt 80 656) + (pt 80 808) +) +(connector + (pt 1072 816) + (pt 72 816) +) +(connector + (pt 192 640) + (pt 72 640) +) +(connector + (pt 72 640) + (pt 72 816) +) +(connector + (text "FB_ADR[8..6]" (rect 82 584 168 599)(font "Arial" )) + (pt 192 600) + (pt 72 600) + (bus) +) +(connector + (text "VR_RD" (rect 98 512 146 527)(font "Arial" )) + (pt 64 528) + (pt 192 528) +) +(connector + (text "VR_WR" (rect 98 528 148 543)(font "Arial" )) + (pt 64 544) + (pt 192 544) +) +(connector + (text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" )) + (pt 1144 480) + (pt 1264 480) + (bus) +) +(connector + (text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" )) + (pt 2040 544) + (pt 1960 544) + (bus) +) +(connector + (pt 1672 544) + (pt 1888 544) + (bus) +) +(connector + (pt 1888 544) + (pt 1888 568) + (bus) +) +(connector + (text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" )) + (pt 1944 568) + (pt 1888 568) + (bus) +) +(connector + (pt 1672 520) + (pt 1960 520) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 520) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" )) + (pt 1672 576) + (pt 1792 576) +) +(connector + (text "VR_WR" (rect 1698 592 1748 607)(font "Arial" )) + (pt 1672 608) + (pt 1792 608) +) +(connector + (text "VR_BUSY" (rect 418 496 482 511)(font "Arial" )) + (pt 408 512) + (pt 480 512) +) +(connector + (text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" )) + (pt 1144 464) + (pt 1264 464) +) +(connector + (text "VR_RD" (rect 1698 576 1746 591)(font "Arial" )) + (pt 1792 592) + (pt 1672 592) +) +(connector + (text "nRSTO" (rect -86 680 -39 695)(font "Arial" )) + (pt -96 696) + (pt -16 696) +) +(connector + (pt 32 696) + (pt 192 696) +) +(connector + (text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" )) + (pt 72 568) + (pt 192 568) + (bus) +) +(connector + (text "CLK48M" (rect 538 552 593 567)(font "Arial" )) + (pt 528 568) + (pt 608 568) +) +(connector + (text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" )) + (pt 984 568) + (pt 1264 568) +) +(connector + (text "CLK33M" (rect 1202 584 1257 599)(font "Arial" )) + (pt 1264 600) + (pt 1192 600) +) +(connector + (text "CLK500k" (rect 802 232 862 247)(font "Arial" )) + (pt 768 248) + (pt 864 248) +) +(connector + (text "CLK2M4576" (rect 802 256 882 271)(font "Arial" )) + (pt 768 272) + (pt 864 272) +) +(connector + (text "CLK24M576" (rect 802 280 882 295)(font "Arial" )) + (pt 768 296) + (pt 864 296) +) +(connector + (text "nRSTO" (rect 1018 424 1065 439)(font "Arial" )) + (pt 1008 440) + (pt 1096 440) +) +(connector + (pt 768 320) + (pt 872 320) +) +(connector + (pt 872 432) + (pt 944 432) +) +(connector + (pt 840 448) + (pt 944 448) +) +(connector + (pt 872 320) + (pt 872 432) +) +(connector + (text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" )) + (pt 2304 -80) + (pt 2424 -80) +) +(connector + (pt 2424 -80) + (pt 2464 -80) +) +(connector + (text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" )) + (pt 1736 -64) + (pt 1856 -64) +) +(junction (pt 2504 760)) +(junction (pt 400 248)) +(junction (pt 1856 -64)) +(junction (pt 2424 -80)) diff --git a/FPGA_quartus/firebee1.done b/FPGA_quartus/firebee1.done new file mode 100644 index 0000000..1674c93 --- /dev/null +++ b/FPGA_quartus/firebee1.done @@ -0,0 +1 @@ +Wed Dec 15 02:25:24 2010 diff --git a/FPGA_quartus/firebee1.dpf b/FPGA_quartus/firebee1.dpf new file mode 100644 index 0000000..f0b3ecc --- /dev/null +++ b/FPGA_quartus/firebee1.dpf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_quartus/firebee1.fit.rpt b/FPGA_quartus/firebee1.fit.rpt new file mode 100644 index 0000000..e3df129 --- /dev/null +++ b/FPGA_quartus/firebee1.fit.rpt @@ -0,0 +1,6866 @@ +Fitter report for firebee1 +Wed Dec 15 02:25:03 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Fitter Netlist Optimizations + 7. Ignored Assignments + 8. Incremental Compilation Preservation Summary + 9. Incremental Compilation Partition Settings + 10. Incremental Compilation Placement Preservation + 11. Pin-Out File + 12. Fitter Resource Usage Summary + 13. Input Pins + 14. Output Pins + 15. Bidir Pins + 16. Dual Purpose and Dedicated Pins + 17. I/O Bank Usage + 18. All Package Pins + 19. PLL Summary + 20. PLL Usage + 21. Output Pin Default Load For Reported TCO + 22. Fitter Resource Utilization by Entity + 23. Delay Chain Summary + 24. Pad To Core Delay Chain Fanout + 25. Control Signals + 26. Global & Other Fast Signals + 27. Non-Global High Fan-Out Signals + 28. Fitter RAM Summary + 29. Fitter DSP Block Usage Summary + 30. DSP Block Details + 31. Interconnect Usage Summary + 32. LAB Logic Elements + 33. LAB-wide Signals + 34. LAB Signals Sourced + 35. LAB Signals Sourced Out + 36. LAB Distinct Inputs + 37. I/O Rules Summary + 38. I/O Rules Details + 39. I/O Rules Matrix + 40. Fitter Device Options + 41. Operating Settings and Conditions + 42. Estimated Delay Added for Hold Timing + 43. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Wed Dec 15 02:25:02 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; +; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; Total registers ; 4749 ; +; Total pins ; 295 / 332 ( 89 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; Total PLLs ; 4 / 4 ( 100 % ) ; ++------------------------------------+----------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C40F484C6 ; ; +; Use TimeQuest Timing Analyzer ; Off ; On ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ; +; Perform Register Duplication for Performance ; On ; Off ; +; Physical Synthesis Effort Level ; Fast ; Normal ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Use Best Effort Settings for Compilation ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------------------+ +; I/O Assignment Warnings ; ++---------------+--------------------------------------+ +; Pin Name ; Reason ; ++---------------+--------------------------------------+ +; LP_STR ; Missing drive strength ; +; nACSI_ACK ; Missing drive strength ; +; nACSI_RESET ; Missing drive strength ; +; nACSI_CS ; Missing drive strength ; +; ACSI_DIR ; Missing drive strength ; +; ACSI_A1 ; Missing drive strength ; +; nSCSI_ACK ; Missing drive strength ; +; nSCSI_ATN ; Missing drive strength ; +; SCSI_DIR ; Missing drive strength ; +; MIDI_OLR ; Missing drive strength ; +; MIDI_TLR ; Missing drive strength ; +; TxD ; Missing drive strength ; +; RTS ; Missing drive strength ; +; DTR ; Missing drive strength ; +; IDE_RES ; Missing drive strength ; +; nIDE_CS0 ; Missing drive strength ; +; nIDE_CS1 ; Missing drive strength ; +; nIDE_WR ; Missing drive strength ; +; nIDE_RD ; Missing drive strength ; +; nCF_CS0 ; Missing drive strength ; +; nCF_CS1 ; Missing drive strength ; +; nROM3 ; Missing drive strength ; +; nROM4 ; Missing drive strength ; +; nRP_UDS ; Missing drive strength ; +; nRP_LDS ; Missing drive strength ; +; nSDSEL ; Missing drive strength ; +; nWR_GATE ; Missing drive strength ; +; nWR ; Missing drive strength ; +; YM_QA ; Missing drive strength ; +; YM_QB ; Missing drive strength ; +; YM_QC ; Missing drive strength ; +; SD_CLK ; Missing drive strength ; +; DSA_D ; Missing drive strength ; +; nVWE ; Missing slew rate ; +; nVCAS ; Missing slew rate ; +; nVRAS ; Missing slew rate ; +; nVCS ; Missing slew rate ; +; TIN0 ; Missing drive strength ; +; nDREQ1 ; Missing drive strength ; +; LED_FPGA_OK ; Missing slew rate ; +; VCKE ; Missing slew rate ; +; nFB_TA ; Missing drive strength ; +; nDDR_CLK ; Missing slew rate ; +; DDR_CLK ; Missing slew rate ; +; VSYNC_PAD ; Missing slew rate ; +; HSYNC_PAD ; Missing slew rate ; +; nBLANK_PAD ; Missing slew rate ; +; PIXEL_CLK_PAD ; Missing slew rate ; +; nSYNC ; Missing slew rate ; +; nMOT_ON ; Missing drive strength ; +; nSTEP_DIR ; Missing drive strength ; +; nSTEP ; Missing drive strength ; +; LPDIR ; Missing drive strength ; +; BA[1] ; Missing slew rate ; +; BA[0] ; Missing slew rate ; +; nIRQ[7] ; Missing drive strength ; +; nIRQ[6] ; Missing drive strength ; +; nIRQ[5] ; Missing drive strength ; +; nIRQ[4] ; Missing drive strength and slew rate ; +; nIRQ[3] ; Missing drive strength and slew rate ; +; nIRQ[2] ; Missing drive strength and slew rate ; +; VA[12] ; Missing slew rate ; +; VA[11] ; Missing slew rate ; +; VA[10] ; Missing slew rate ; +; VA[9] ; Missing slew rate ; +; VA[8] ; Missing slew rate ; +; VA[7] ; Missing slew rate ; +; VA[6] ; Missing slew rate ; +; VA[5] ; Missing slew rate ; +; VA[4] ; Missing slew rate ; +; VA[3] ; Missing slew rate ; +; VA[2] ; Missing slew rate ; +; VA[1] ; Missing slew rate ; +; VA[0] ; Missing slew rate ; +; VB[7] ; Missing slew rate ; +; VB[6] ; Missing slew rate ; +; VB[5] ; Missing slew rate ; +; VB[4] ; Missing slew rate ; +; VB[3] ; Missing slew rate ; +; VB[2] ; Missing slew rate ; +; VB[1] ; Missing slew rate ; +; VB[0] ; Missing slew rate ; +; VDM[3] ; Missing slew rate ; +; VDM[2] ; Missing slew rate ; +; VDM[1] ; Missing slew rate ; +; VDM[0] ; Missing slew rate ; +; VG[7] ; Missing slew rate ; +; VG[6] ; Missing slew rate ; +; VG[5] ; Missing slew rate ; +; VG[4] ; Missing slew rate ; +; VG[3] ; Missing slew rate ; +; VG[2] ; Missing slew rate ; +; VG[1] ; Missing slew rate ; +; VG[0] ; Missing slew rate ; +; VR[7] ; Missing slew rate ; +; VR[6] ; Missing slew rate ; +; VR[5] ; Missing slew rate ; +; VR[4] ; Missing slew rate ; +; VR[3] ; Missing slew rate ; +; VR[2] ; Missing slew rate ; +; VR[1] ; Missing slew rate ; +; VR[0] ; Missing slew rate ; +; VD[31] ; Missing slew rate ; +; VD[30] ; Missing slew rate ; +; VD[29] ; Missing slew rate ; +; VD[28] ; Missing slew rate ; +; VD[27] ; Missing slew rate ; +; VD[26] ; Missing slew rate ; +; VD[25] ; Missing slew rate ; +; VD[24] ; Missing slew rate ; +; VD[23] ; Missing slew rate ; +; VD[22] ; Missing slew rate ; +; VD[21] ; Missing slew rate ; +; VD[20] ; Missing slew rate ; +; VD[19] ; Missing slew rate ; +; VD[18] ; Missing slew rate ; +; VD[17] ; Missing slew rate ; +; VD[16] ; Missing slew rate ; +; VD[15] ; Missing slew rate ; +; VD[14] ; Missing slew rate ; +; VD[13] ; Missing slew rate ; +; VD[12] ; Missing slew rate ; +; VD[11] ; Missing slew rate ; +; VD[10] ; Missing slew rate ; +; VD[9] ; Missing slew rate ; +; VD[8] ; Missing slew rate ; +; VD[7] ; Missing slew rate ; +; VD[6] ; Missing slew rate ; +; VD[5] ; Missing slew rate ; +; VD[4] ; Missing slew rate ; +; VD[3] ; Missing slew rate ; +; VD[2] ; Missing slew rate ; +; VD[1] ; Missing slew rate ; +; VD[0] ; Missing slew rate ; +; VDQS[3] ; Missing slew rate ; +; VDQS[2] ; Missing slew rate ; +; VDQS[1] ; Missing slew rate ; +; VDQS[0] ; Missing slew rate ; +; SCSI_PAR ; Missing drive strength ; +; nSCSI_SEL ; Missing drive strength ; +; nSCSI_BUSY ; Missing drive strength ; +; nSCSI_RST ; Missing drive strength ; +; SD_CD_DATA3 ; Missing drive strength ; +; SD_CMD_D1 ; Missing drive strength ; +; ACSI_D[7] ; Missing drive strength ; +; ACSI_D[6] ; Missing drive strength ; +; ACSI_D[5] ; Missing drive strength ; +; ACSI_D[4] ; Missing drive strength ; +; ACSI_D[3] ; Missing drive strength ; +; ACSI_D[2] ; Missing drive strength ; +; ACSI_D[1] ; Missing drive strength ; +; ACSI_D[0] ; Missing drive strength ; +; LP_D[7] ; Missing drive strength ; +; LP_D[6] ; Missing drive strength ; +; LP_D[5] ; Missing drive strength ; +; LP_D[4] ; Missing drive strength ; +; LP_D[3] ; Missing drive strength ; +; LP_D[2] ; Missing drive strength ; +; LP_D[1] ; Missing drive strength ; +; LP_D[0] ; Missing drive strength ; +; SCSI_D[7] ; Missing drive strength ; +; SCSI_D[6] ; Missing drive strength ; +; SCSI_D[5] ; Missing drive strength ; +; SCSI_D[4] ; Missing drive strength ; +; SCSI_D[3] ; Missing drive strength ; +; SCSI_D[2] ; Missing drive strength ; +; SCSI_D[1] ; Missing drive strength ; +; SCSI_D[0] ; Missing drive strength ; ++---------------+--------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP_DIR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nMOT_ON~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR_GATE~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; Packed Register ; Register Packing ; PLL Source Synchronous assignment ; Q ; ; nRD_DATA~input ; O ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSDSEL~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DSA_D~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; RTS~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DTR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_STR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LPDIR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[0]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[1]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[2]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[3]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[4]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[5]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[6]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[7]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_OUTn ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSCSI_BUSY~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nIDE_RD~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0SLOAD_MUX ; Created ; Register Packing ; Timing optimization ; COMBOUT ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Q ; ; +; Video:Fredi_Aschwanden|inst90 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[3]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[2]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[1]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[0]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[28]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[29]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[30]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[31]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[0]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[1]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[2]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[3]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[4]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[5]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[6]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[7]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[8]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[9]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[10]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[11]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[12]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[13]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[14]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[15]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[16]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[17]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[18]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[19]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[20]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[21]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[22]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[23]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[24]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[25]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[26]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[27]~input ; O ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~53 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~168 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~177 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~178 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~368 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~358 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22_BDD23 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector96~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~30 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~31 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_01_STRB~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_10_STRB~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add1~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add3~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add5~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~17 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add10~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add11~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_CLK~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan6~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan7~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan8~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux84~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux92~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux100~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_A[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~162 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163_RESYN8_BDD9 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~3 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[6]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG~13 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0_RESYN30_BDD31 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28_BDD29 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_END[10] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[1]~19 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[10]~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28_RESYN32_BDD33 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~17 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~43 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_26~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_27~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_28~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_30~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_31~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~472 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~478 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~479 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~481 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~482 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~10 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42_BDD43 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN44_BDD45 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN46_BDD47 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34_BDD35 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN36_BDD37 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN38_BDD39 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ +; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_H ; HIGH ; Compiler or HDL Assignment ; +; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_L ; LOW ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ + + ++------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+----------------------+ +; Type ; Value ; ++-------------------------+----------------------+ +; Netlist ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; +; ; ; +; Placement ; ; +; -- Requested ; 0 / 13829 ( 0.00 % ) ; +; -- Achieved ; 0 / 13829 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 13829 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/FireBee/FPGA/firebee1.pin. + + ++----------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------------+ +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; -- Combinational with no register ; 4963 ; +; -- Register only ; 1465 ; +; -- Combinational with a register ; 3098 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4959 ; +; -- 3 input functions ; 1861 ; +; -- <=2 input functions ; 1241 ; +; -- Register only ; 1465 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7262 ; +; -- arithmetic mode ; 799 ; +; ; ; +; Total registers* ; 4,749 / 41,185 ( 12 % ) ; +; -- Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; -- I/O registers ; 186 / 1,585 ( 12 % ) ; +; ; ; +; Total LABs: partially or completely used ; 756 / 2,475 ( 31 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 295 / 332 ( 89 % ) ; +; -- Clock pins ; 7 / 8 ( 88 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; Global signals ; 20 ; +; M9Ks ; 23 / 126 ( 18 % ) ; +; Total block memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Total block memory implementation bits ; 211,968 / 1,161,216 ( 18 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; PLLs ; 4 / 4 ( 100 % ) ; +; Global clocks ; 20 / 20 ( 100 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 15% / 14% / 16% ; +; Peak interconnect usage (total/H/V) ; 59% / 54% / 65% ; +; Maximum fan-out node ; MAIN_CLK~input ; +; Maximum fan-out ; 2272 ; +; Highest non-global fan-out signal ; MAIN_CLK~input ; +; Highest non-global fan-out ; 2272 ; +; Total fan-out ; 44654 ; +; Average fan-out ; 3.02 ; ++---------------------------------------------+------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; AMKB_RX ; Y2 ; 2 ; 0 ; 10 ; 21 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; CLK33M ; AB12 ; 4 ; 36 ; 0 ; 0 ; 16 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; CTS ; H14 ; 7 ; 61 ; 43 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; DCD ; A19 ; 7 ; 56 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; DVI_INT ; A11 ; 8 ; 34 ; 43 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; E0_INT ; G21 ; 6 ; 67 ; 22 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_ALE ; R7 ; 2 ; 0 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_SIZE0 ; U8 ; 3 ; 3 ; 0 ; 21 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_SIZE1 ; Y4 ; 3 ; 3 ; 0 ; 14 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; HD_DD ; F16 ; 7 ; 65 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; IDE_INT ; G22 ; 6 ; 67 ; 22 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; IDE_RDY ; Y1 ; 2 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; LP_BUSY ; G7 ; 8 ; 3 ; 43 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; MAIN_CLK ; G2 ; 1 ; 0 ; 21 ; 0 ; 2272 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; MIDI_IN ; E12 ; 7 ; 36 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; PIC_AMKB_RX ; L7 ; 2 ; 0 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; PIC_INT ; AA2 ; 2 ; 0 ; 7 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; RI ; B19 ; 7 ; 56 ; 43 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; RxD ; H15 ; 7 ; 61 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_CARD_DEDECT ; M20 ; 5 ; 67 ; 19 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA0 ; B16 ; 7 ; 50 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA1 ; A16 ; 7 ; 50 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA2 ; B17 ; 7 ; 50 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_WP ; M19 ; 5 ; 67 ; 19 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; TOUT0 ; T22 ; 5 ; 67 ; 22 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; TRACK00 ; C19 ; 7 ; 61 ; 43 ; 28 ; 11 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; WP_CF_CARD ; T1 ; 2 ; 0 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nACSI_DRQ ; K7 ; 1 ; 0 ; 30 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nACSI_INT ; J4 ; 1 ; 0 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDACK0 ; B12 ; 7 ; 34 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDACK1 ; A12 ; 7 ; 34 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDCHG ; C17 ; 7 ; 56 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_BURST ; T3 ; 2 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS1 ; T8 ; 3 ; 14 ; 0 ; 28 ; 59 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS2 ; T9 ; 3 ; 14 ; 0 ; 21 ; 95 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS3 ; V6 ; 3 ; 1 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_OE ; R6 ; 2 ; 0 ; 3 ; 0 ; 101 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_WR ; T5 ; 2 ; 0 ; 4 ; 0 ; 235 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nINDEX ; E16 ; 7 ; 65 ; 43 ; 28 ; 14 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nMASTER ; T21 ; 5 ; 67 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTA ; AA1 ; 2 ; 0 ; 6 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTB ; V4 ; 2 ; 0 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTC ; V3 ; 2 ; 0 ; 5 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTD ; P6 ; 2 ; 0 ; 5 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nRD_DATA ; A20 ; 7 ; 59 ; 43 ; 7 ; 0 ; 2 ; no ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nRSTO_MCF ; B11 ; 8 ; 34 ; 43 ; 21 ; 27 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_C_D ; H1 ; 1 ; 0 ; 28 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_DRQ ; U1 ; 2 ; 0 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_I_O ; J3 ; 1 ; 0 ; 28 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_MSG ; H2 ; 1 ; 0 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nWP ; D19 ; 7 ; 59 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ +; ACSI_A1 ; M6 ; 2 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; ACSI_DIR ; L6 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; AMKB_TX ; N1 ; 2 ; 0 ; 19 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; BA[0] ; W19 ; 5 ; 67 ; 5 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; BA[1] ; AA19 ; 4 ; 56 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLK24M576 ; AB10 ; 3 ; 34 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLK25M ; T4 ; 2 ; 0 ; 4 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLKUSB ; J1 ; 1 ; 0 ; 28 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DDR_CLK ; AB17 ; 4 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DSA_D ; F15 ; 7 ; 63 ; 43 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DTR ; D15 ; 7 ; 54 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; HSYNC_PAD ; K21 ; 6 ; 67 ; 27 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; IDE_RES ; M5 ; 2 ; 0 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LED_FPGA_OK ; N19 ; 5 ; 67 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 4mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LPDIR ; E5 ; 8 ; 1 ; 43 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LP_STR ; E6 ; 8 ; 1 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; MIDI_OLR ; H5 ; 1 ; 0 ; 31 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; MIDI_TLR ; B2 ; 1 ; 0 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; PIXEL_CLK_PAD ; F19 ; 6 ; 67 ; 37 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; RTS ; B18 ; 7 ; 54 ; 43 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; SCSI_DIR ; J7 ; 1 ; 0 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; SD_CLK ; C15 ; 7 ; 50 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; TIN0 ; R5 ; 2 ; 0 ; 4 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; TxD ; A18 ; 7 ; 54 ; 43 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[0] ; W20 ; 5 ; 67 ; 3 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[10] ; V21 ; 5 ; 67 ; 10 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[11] ; U19 ; 5 ; 67 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[12] ; AA18 ; 4 ; 54 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[1] ; W22 ; 5 ; 67 ; 7 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[2] ; W21 ; 5 ; 67 ; 8 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[3] ; Y22 ; 5 ; 67 ; 6 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[4] ; AA22 ; 5 ; 67 ; 2 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[5] ; Y21 ; 5 ; 67 ; 7 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[6] ; AA21 ; 5 ; 67 ; 2 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[7] ; AA20 ; 4 ; 61 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[8] ; AB20 ; 4 ; 61 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[9] ; AB19 ; 4 ; 59 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[0] ; G18 ; 6 ; 67 ; 37 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[1] ; H17 ; 6 ; 67 ; 38 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[2] ; C22 ; 6 ; 67 ; 38 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[3] ; C21 ; 6 ; 67 ; 38 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[4] ; B22 ; 6 ; 67 ; 39 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[5] ; B21 ; 6 ; 67 ; 39 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[6] ; C20 ; 6 ; 67 ; 39 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[7] ; D20 ; 6 ; 67 ; 40 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VCKE ; U15 ; 4 ; 50 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[0] ; AA16 ; 4 ; 45 ; 0 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[1] ; V16 ; 4 ; 61 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[2] ; U20 ; 5 ; 67 ; 7 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[3] ; T17 ; 5 ; 67 ; 3 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[0] ; H19 ; 6 ; 67 ; 34 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[1] ; E22 ; 6 ; 67 ; 34 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[2] ; E21 ; 6 ; 67 ; 34 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[3] ; H18 ; 6 ; 67 ; 35 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[4] ; J17 ; 6 ; 67 ; 36 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[5] ; H16 ; 6 ; 67 ; 36 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[6] ; D22 ; 6 ; 67 ; 36 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[7] ; D21 ; 6 ; 67 ; 36 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[0] ; J22 ; 6 ; 67 ; 28 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[1] ; J21 ; 6 ; 67 ; 28 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[2] ; H22 ; 6 ; 67 ; 28 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[3] ; H21 ; 6 ; 67 ; 28 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[4] ; K17 ; 6 ; 67 ; 29 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[5] ; K18 ; 6 ; 67 ; 30 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[6] ; J18 ; 6 ; 67 ; 31 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[7] ; F22 ; 6 ; 67 ; 31 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VSYNC_PAD ; K19 ; 6 ; 67 ; 26 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QA ; A17 ; 7 ; 52 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QB ; G13 ; 7 ; 52 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QC ; E15 ; 7 ; 54 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_ACK ; M4 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_CS ; M2 ; 2 ; 0 ; 20 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_RESET ; M1 ; 2 ; 0 ; 20 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nBLANK_PAD ; G17 ; 6 ; 67 ; 41 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nCF_CS0 ; W2 ; 2 ; 0 ; 10 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nCF_CS1 ; W1 ; 2 ; 0 ; 10 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nDDR_CLK ; AA17 ; 4 ; 54 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nDREQ1 ; E11 ; 7 ; 36 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nFB_TA ; T7 ; 2 ; 0 ; 2 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_CS0 ; R2 ; 2 ; 0 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_CS1 ; R1 ; 2 ; 0 ; 16 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_RD ; P1 ; 2 ; 0 ; 17 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_WR ; P2 ; 2 ; 0 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[2] ; F21 ; 6 ; 67 ; 31 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[3] ; H20 ; 6 ; 67 ; 34 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[4] ; F20 ; 6 ; 67 ; 37 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[5] ; P5 ; 2 ; 0 ; 12 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[6] ; P7 ; 2 ; 0 ; 7 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[7] ; N7 ; 2 ; 0 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nMOT_ON ; G16 ; 7 ; 63 ; 43 ; 7 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nPD_VGA ; V1 ; 2 ; 0 ; 13 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nROM3 ; P3 ; 2 ; 0 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nROM4 ; U2 ; 2 ; 0 ; 15 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nRP_LDS ; N5 ; 2 ; 0 ; 16 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nRP_UDS ; P4 ; 2 ; 0 ; 16 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSCSI_ACK ; N2 ; 2 ; 0 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSCSI_ATN ; M3 ; 2 ; 0 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSDSEL ; B20 ; 7 ; 59 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRBHE ; B4 ; 8 ; 7 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRBLE ; A4 ; 8 ; 9 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRCS ; B8 ; 8 ; 25 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSROE ; F11 ; 7 ; 36 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRWE ; F8 ; 8 ; 7 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSTEP ; F14 ; 7 ; 63 ; 43 ; 28 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSTEP_DIR ; G15 ; 7 ; 63 ; 43 ; 21 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSYNC ; F17 ; 6 ; 67 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVCAS ; AB18 ; 4 ; 52 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVCS ; T18 ; 5 ; 67 ; 3 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVRAS ; W17 ; 4 ; 59 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVWE ; Y17 ; 4 ; 61 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nWR ; G14 ; 7 ; 54 ; 43 ; 28 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nWR_GATE ; D17 ; 7 ; 61 ; 43 ; 14 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ +; ACSI_D[0] ; B1 ; 1 ; 0 ; 40 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[1] ; G5 ; 1 ; 0 ; 40 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[2] ; E3 ; 1 ; 0 ; 39 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[3] ; C2 ; 1 ; 0 ; 38 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[4] ; C1 ; 1 ; 0 ; 38 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[5] ; D2 ; 1 ; 0 ; 37 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[6] ; H7 ; 1 ; 0 ; 37 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[7] ; H6 ; 1 ; 0 ; 37 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; FB_AD[0] ; Y3 ; 3 ; 3 ; 0 ; 7 ; 21 ; 25 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[10] ; W7 ; 3 ; 14 ; 0 ; 14 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[11] ; Y7 ; 3 ; 14 ; 0 ; 7 ; 19 ; 14 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[12] ; U9 ; 3 ; 16 ; 0 ; 21 ; 21 ; 8 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[13] ; V8 ; 3 ; 16 ; 0 ; 14 ; 21 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[14] ; W8 ; 3 ; 16 ; 0 ; 7 ; 20 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[15] ; AA7 ; 3 ; 16 ; 0 ; 0 ; 19 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[16] ; AB7 ; 3 ; 18 ; 0 ; 21 ; 142 ; 10 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; +; FB_AD[17] ; Y8 ; 3 ; 18 ; 0 ; 14 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; +; FB_AD[18] ; V9 ; 3 ; 20 ; 0 ; 21 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[19] ; V10 ; 3 ; 20 ; 0 ; 14 ; 142 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; +; FB_AD[1] ; Y6 ; 3 ; 5 ; 0 ; 14 ; 20 ; 158 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[20] ; T10 ; 3 ; 18 ; 0 ; 7 ; 143 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[21] ; U10 ; 3 ; 22 ; 0 ; 14 ; 142 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[22] ; AA8 ; 3 ; 22 ; 0 ; 7 ; 139 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[23] ; AB8 ; 3 ; 22 ; 0 ; 0 ; 136 ; 2 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; +; FB_AD[24] ; T11 ; 3 ; 18 ; 0 ; 0 ; 62 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; +; FB_AD[25] ; AA9 ; 3 ; 27 ; 0 ; 7 ; 58 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; +; FB_AD[26] ; AB9 ; 3 ; 27 ; 0 ; 0 ; 56 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 (inverted) ; - ; +; FB_AD[27] ; U11 ; 3 ; 29 ; 0 ; 28 ; 47 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[28] ; V11 ; 3 ; 34 ; 0 ; 28 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[29] ; W10 ; 3 ; 34 ; 0 ; 21 ; 32 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[2] ; AA3 ; 3 ; 7 ; 0 ; 28 ; 20 ; 120 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[30] ; Y10 ; 3 ; 34 ; 0 ; 14 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[31] ; AA10 ; 3 ; 34 ; 0 ; 7 ; 35 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[3] ; AB3 ; 3 ; 7 ; 0 ; 21 ; 20 ; 97 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[4] ; W6 ; 3 ; 7 ; 0 ; 14 ; 20 ; 83 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[5] ; V7 ; 3 ; 7 ; 0 ; 7 ; 20 ; 161 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[6] ; AA4 ; 3 ; 9 ; 0 ; 28 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[7] ; AB4 ; 3 ; 9 ; 0 ; 21 ; 18 ; 26 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[8] ; AA5 ; 3 ; 9 ; 0 ; 14 ; 20 ; 34 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[9] ; AB5 ; 3 ; 9 ; 0 ; 7 ; 20 ; 22 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; IO[0] ; A8 ; 8 ; 25 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[10] ; B15 ; 7 ; 45 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[11] ; C13 ; 7 ; 45 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[12] ; D13 ; 7 ; 45 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[13] ; E13 ; 7 ; 41 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[14] ; A14 ; 7 ; 41 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[15] ; B14 ; 7 ; 38 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[16] ; A13 ; 7 ; 38 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[17] ; B13 ; 7 ; 38 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[1] ; A7 ; 8 ; 25 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[2] ; B7 ; 8 ; 25 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[3] ; A6 ; 8 ; 25 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[4] ; B6 ; 8 ; 22 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[5] ; E9 ; 8 ; 22 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[6] ; C8 ; 8 ; 20 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[7] ; C7 ; 8 ; 20 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[8] ; G10 ; 8 ; 11 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[9] ; A15 ; 7 ; 45 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; LP_D[0] ; F7 ; 8 ; 3 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[1] ; C4 ; 8 ; 3 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[2] ; C3 ; 8 ; 5 ; 43 ; 28 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[3] ; E7 ; 8 ; 5 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[4] ; D6 ; 8 ; 5 ; 43 ; 14 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[5] ; B3 ; 8 ; 5 ; 43 ; 7 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[6] ; A3 ; 8 ; 5 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[7] ; G8 ; 8 ; 7 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; SCSI_D[0] ; J6 ; 1 ; 0 ; 36 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[1] ; E1 ; 1 ; 0 ; 36 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[2] ; F2 ; 1 ; 0 ; 35 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[3] ; F1 ; 1 ; 0 ; 35 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[4] ; G4 ; 1 ; 0 ; 41 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[5] ; G3 ; 1 ; 0 ; 41 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[6] ; L8 ; 1 ; 0 ; 31 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[7] ; K8 ; 1 ; 0 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_PAR ; M7 ; 2 ; 0 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SD_CD_DATA3 ; F13 ; 7 ; 45 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SD_CMD_D1 ; E14 ; 7 ; 48 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SRD[0] ; B5 ; 8 ; 11 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[10] ; A9 ; 8 ; 32 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[11] ; B10 ; 8 ; 32 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[12] ; D10 ; 8 ; 32 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[13] ; F10 ; 8 ; 9 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[14] ; G9 ; 8 ; 1 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[15] ; H10 ; 8 ; 18 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[1] ; A5 ; 8 ; 14 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[2] ; C6 ; 8 ; 9 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[3] ; G11 ; 8 ; 27 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[4] ; C10 ; 8 ; 29 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[5] ; F9 ; 8 ; 1 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[6] ; E10 ; 8 ; 32 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[7] ; H11 ; 8 ; 20 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[8] ; B9 ; 8 ; 29 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[9] ; A10 ; 8 ; 32 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; VDQS[0] ; AA15 ; 4 ; 43 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; - ; +; VDQS[1] ; W15 ; 4 ; 52 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; - ; +; VDQS[2] ; U22 ; 5 ; 67 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; - ; +; VDQS[3] ; T16 ; 4 ; 63 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90 ; - ; +; VD[0] ; M22 ; 5 ; 67 ; 18 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[10] ; P17 ; 5 ; 67 ; 10 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[11] ; R21 ; 5 ; 67 ; 13 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[12] ; N17 ; 5 ; 67 ; 17 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[13] ; P20 ; 5 ; 67 ; 14 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[14] ; R22 ; 5 ; 67 ; 13 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[15] ; N20 ; 5 ; 67 ; 15 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[16] ; T12 ; 4 ; 45 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[17] ; Y13 ; 4 ; 43 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[18] ; AA13 ; 4 ; 38 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[19] ; V14 ; 4 ; 50 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[1] ; M21 ; 5 ; 67 ; 18 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[20] ; U13 ; 4 ; 50 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[21] ; V15 ; 4 ; 50 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[22] ; W14 ; 4 ; 48 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[23] ; AB16 ; 4 ; 45 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[24] ; AB15 ; 4 ; 43 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[25] ; AA14 ; 4 ; 38 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[26] ; AB14 ; 4 ; 38 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[27] ; V13 ; 4 ; 48 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[28] ; W13 ; 4 ; 43 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[29] ; AB13 ; 4 ; 38 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[2] ; P22 ; 5 ; 67 ; 14 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[30] ; V12 ; 4 ; 41 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[31] ; U12 ; 4 ; 43 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[3] ; R20 ; 5 ; 67 ; 11 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[4] ; P21 ; 5 ; 67 ; 14 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[5] ; R17 ; 5 ; 67 ; 10 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[6] ; R19 ; 5 ; 67 ; 12 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[7] ; U21 ; 5 ; 67 ; 11 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[8] ; V22 ; 5 ; 67 ; 10 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[9] ; R18 ; 5 ; 67 ; 12 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; nSCSI_BUSY ; N8 ; 2 ; 0 ; 11 ; 14 ; 0 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; nSCSI_RST ; N6 ; 2 ; 0 ; 12 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; nSCSI_SEL ; M8 ; 2 ; 0 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ +; D1 ; DIFFIO_L8n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L10p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As input tri-stated ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; N22 ; DIFFIO_R32n, DEV_OE ; Reserved as secondary function ; ~ALTERA_DEV_OE~ ; Dual Purpose Pin ; +; N21 ; DIFFIO_R32p, DEV_CLRn ; Reserved as secondary function ; ~ALTERA_DEV_CLRn~ ; Dual Purpose Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R24n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; K21 ; DIFFIO_R24p, CLKUSR ; Use as general purpose IO ; HSYNC_PAD ; Dual Purpose Pin ; +; E22 ; DIFFIO_R12n, nWE ; Use as regular IO ; VG[1] ; Dual Purpose Pin ; +; E21 ; DIFFIO_R12p, nOE ; Use as regular IO ; VG[2] ; Dual Purpose Pin ; +; F20 ; DIFFIO_R8n, nAVD ; Use as regular IO ; nIRQ[4] ; Dual Purpose Pin ; +; F19 ; DIFFIO_R8n, nAVD ; - ; PIXEL_CLK_PAD ; Dual Purpose Pin ; +; G18 ; DIFFIO_R7n, PADD23 ; Use as regular IO ; VB[0] ; Dual Purpose Pin ; +; B22 ; DIFFIO_R5n, PADD22 ; Use as regular IO ; VB[4] ; Dual Purpose Pin ; +; B21 ; DIFFIO_R5p, PADD21 ; Use as regular IO ; VB[5] ; Dual Purpose Pin ; +; C20 ; DIFFIO_R4n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO ; VB[6] ; Dual Purpose Pin ; +; B18 ; DIFFIO_T45p, PADD0 ; Use as regular IO ; RTS ; Dual Purpose Pin ; +; A17 ; DIFFIO_T41n, PADD1 ; Use as regular IO ; YM_QA ; Dual Purpose Pin ; +; B17 ; DIFFIO_T41p, PADD2 ; Use as regular IO ; SD_DATA2 ; Dual Purpose Pin ; +; E14 ; DIFFIO_T38n, PADD3 ; Use as regular IO ; SD_CMD_D1 ; Dual Purpose Pin ; +; F13 ; DIFFIO_T37p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; SD_CD_DATA3 ; Dual Purpose Pin ; +; A15 ; DIFFIO_T36n, PADD5 ; Use as regular IO ; IO[9] ; Dual Purpose Pin ; +; B15 ; DIFFIO_T36p, PADD6 ; Use as regular IO ; IO[10] ; Dual Purpose Pin ; +; C13 ; DIFFIO_T35n, PADD7 ; Use as regular IO ; IO[11] ; Dual Purpose Pin ; +; D13 ; DIFFIO_T35p, PADD8 ; Use as regular IO ; IO[12] ; Dual Purpose Pin ; +; A14 ; DIFFIO_T31n, PADD9 ; Use as regular IO ; IO[14] ; Dual Purpose Pin ; +; B14 ; DIFFIO_T31p, PADD10 ; Use as regular IO ; IO[15] ; Dual Purpose Pin ; +; A13 ; DIFFIO_T29n, PADD11 ; Use as regular IO ; IO[16] ; Dual Purpose Pin ; +; B13 ; DIFFIO_T29p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; IO[17] ; Dual Purpose Pin ; +; E11 ; DIFFIO_T27n, PADD13 ; Use as regular IO ; nDREQ1 ; Dual Purpose Pin ; +; F11 ; DIFFIO_T27p, PADD14 ; Use as regular IO ; nSROE ; Dual Purpose Pin ; +; B10 ; DIFFIO_T25p, PADD15 ; Use as regular IO ; SRD[11] ; Dual Purpose Pin ; +; A9 ; DIFFIO_T24n, PADD16 ; Use as regular IO ; SRD[10] ; Dual Purpose Pin ; +; B9 ; DIFFIO_T24p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; SRD[8] ; Dual Purpose Pin ; +; A8 ; DIFFIO_T20n, DATA2 ; Use as regular IO ; IO[0] ; Dual Purpose Pin ; +; B8 ; DIFFIO_T20p, DATA3 ; Use as regular IO ; nSRCS ; Dual Purpose Pin ; +; A7 ; DIFFIO_T19n, PADD18 ; Use as regular IO ; IO[1] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T19p, DATA4 ; Use as regular IO ; IO[2] ; Dual Purpose Pin ; +; A6 ; DIFFIO_T18n, PADD19 ; Use as regular IO ; IO[3] ; Dual Purpose Pin ; +; B6 ; DIFFIO_T18p, DATA15 ; Use as regular IO ; IO[4] ; Dual Purpose Pin ; +; C8 ; DIFFIO_T16n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; IO[6] ; Dual Purpose Pin ; +; C7 ; DIFFIO_T16p, DATA13 ; Use as regular IO ; IO[7] ; Dual Purpose Pin ; +; A5 ; DIFFIO_T11p, DATA5 ; Use as regular IO ; SRD[1] ; Dual Purpose Pin ; +; F10 ; DIFFIO_T8p, DATA6 ; Use as regular IO ; SRD[13] ; Dual Purpose Pin ; +; C6 ; DIFFIO_T7n, DATA7 ; Use as regular IO ; SRD[2] ; Dual Purpose Pin ; +; B4 ; DIFFIO_T6p, DATA8 ; Use as regular IO ; nSRBHE ; Dual Purpose Pin ; +; F8 ; DIFFIO_T5n, DATA9 ; Use as regular IO ; nSRWE ; Dual Purpose Pin ; +; A3 ; DIFFIO_T4n, DATA10 ; Use as regular IO ; LP_D[6] ; Dual Purpose Pin ; +; B3 ; DIFFIO_T4p, DATA11 ; Use as regular IO ; LP_D[5] ; Dual Purpose Pin ; +; C4 ; DIFFIO_T3p, DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; LP_D[1] ; Dual Purpose Pin ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 30 / 36 ( 83 % ) ; 3.3V ; -- ; +; 2 ; 44 / 46 ( 96 % ) ; 3.3V ; -- ; +; 3 ; 38 / 42 ( 90 % ) ; 3.3V ; -- ; +; 4 ; 33 / 43 ( 77 % ) ; 2.5V ; -- ; +; 5 ; 37 / 42 ( 88 % ) ; 2.5V ; -- ; +; 6 ; 35 / 37 ( 95 % ) ; 3.0V ; -- ; +; 7 ; 43 / 43 ( 100 % ) ; 3.3V ; -- ; +; 8 ; 42 / 43 ( 98 % ) ; 3.3V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 534 ; 8 ; LP_D[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A4 ; 529 ; 8 ; nSRBLE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A5 ; 518 ; 8 ; SRD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A6 ; 501 ; 8 ; IO[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A7 ; 499 ; 8 ; IO[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A8 ; 497 ; 8 ; IO[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 487 ; 8 ; SRD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 485 ; 8 ; SRD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 481 ; 8 ; DVI_INT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 479 ; 7 ; nDACK1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 473 ; 7 ; IO[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 469 ; 7 ; IO[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 458 ; 7 ; IO[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A16 ; 448 ; 7 ; SD_DATA1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A17 ; 446 ; 7 ; YM_QA ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 437 ; 7 ; TxD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 435 ; 7 ; DCD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A20 ; 430 ; 7 ; nRD_DATA ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 125 ; 2 ; nPCI_INTA ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AA2 ; 124 ; 2 ; PIC_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AA3 ; 154 ; 3 ; FB_AD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA4 ; 158 ; 3 ; FB_AD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA5 ; 160 ; 3 ; FB_AD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA7 ; 173 ; 3 ; FB_AD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA8 ; 183 ; 3 ; FB_AD[22] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA9 ; 189 ; 3 ; FB_AD[25] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA10 ; 202 ; 3 ; FB_AD[31] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA11 ; 204 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 206 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 208 ; 4 ; VD[18] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA14 ; 210 ; 4 ; VD[25] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA15 ; 220 ; 4 ; VDQS[0] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA16 ; 224 ; 4 ; VDM[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA17 ; 243 ; 4 ; nDDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA18 ; 245 ; 4 ; VA[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA19 ; 252 ; 4 ; BA[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA20 ; 259 ; 4 ; VA[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA21 ; 274 ; 5 ; VA[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA22 ; 273 ; 5 ; VA[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 155 ; 3 ; FB_AD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB4 ; 159 ; 3 ; FB_AD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB5 ; 161 ; 3 ; FB_AD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 174 ; 3 ; FB_AD[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB8 ; 184 ; 3 ; FB_AD[23] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB9 ; 190 ; 3 ; FB_AD[26] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB10 ; 203 ; 3 ; CLK24M576 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB11 ; 205 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 207 ; 4 ; CLK33M ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB13 ; 209 ; 4 ; VD[29] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB14 ; 211 ; 4 ; VD[26] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB15 ; 221 ; 4 ; VD[24] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB16 ; 225 ; 4 ; VD[23] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB17 ; 244 ; 4 ; DDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB18 ; 242 ; 4 ; nVCAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB19 ; 253 ; 4 ; VA[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB20 ; 260 ; 4 ; VA[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 4 ; 1 ; ACSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 3 ; 1 ; MIDI_TLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 535 ; 8 ; LP_D[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B4 ; 530 ; 8 ; nSRBHE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B5 ; 523 ; 8 ; SRD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B6 ; 502 ; 8 ; IO[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B7 ; 500 ; 8 ; IO[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B8 ; 498 ; 8 ; nSRCS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B9 ; 488 ; 8 ; SRD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B10 ; 486 ; 8 ; SRD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 482 ; 8 ; nRSTO_MCF ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 480 ; 7 ; nDACK0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B13 ; 474 ; 7 ; IO[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 470 ; 7 ; IO[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 459 ; 7 ; IO[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B16 ; 449 ; 7 ; SD_DATA0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 447 ; 7 ; SD_DATA2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B18 ; 438 ; 7 ; RTS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B19 ; 434 ; 7 ; RI ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B20 ; 431 ; 7 ; nSDSEL ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B21 ; 404 ; 6 ; VB[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B22 ; 403 ; 6 ; VB[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C1 ; 15 ; 1 ; ACSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 14 ; 1 ; ACSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 538 ; 8 ; LP_D[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C4 ; 539 ; 8 ; LP_D[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 526 ; 8 ; SRD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C7 ; 508 ; 8 ; IO[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C8 ; 507 ; 8 ; IO[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 491 ; 8 ; SRD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 460 ; 7 ; IO[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 450 ; 7 ; SD_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7 ; nDCHG ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 428 ; 7 ; TRACK00 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C20 ; 405 ; 6 ; VB[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C21 ; 401 ; 6 ; VB[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C22 ; 400 ; 6 ; VB[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D1 ; 17 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D2 ; 16 ; 1 ; ACSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D6 ; 536 ; 8 ; LP_D[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D7 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D10 ; 483 ; 8 ; SRD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D13 ; 461 ; 7 ; IO[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D15 ; 439 ; 7 ; DTR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D17 ; 426 ; 7 ; nWR_GATE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D19 ; 429 ; 7 ; nWP ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D20 ; 407 ; 6 ; VB[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D21 ; 395 ; 6 ; VG[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D22 ; 394 ; 6 ; VG[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E1 ; 22 ; 1 ; SCSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 21 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; E3 ; 9 ; 1 ; ACSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; 546 ; 8 ; LPDIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E6 ; 545 ; 8 ; LP_STR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E7 ; 537 ; 8 ; LP_D[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E9 ; 506 ; 8 ; IO[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E10 ; 484 ; 8 ; SRD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E11 ; 477 ; 7 ; nDREQ1 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E12 ; 476 ; 7 ; MIDI_IN ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E13 ; 468 ; 7 ; IO[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E14 ; 453 ; 7 ; SD_CMD_D1 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 440 ; 7 ; YM_QC ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 418 ; 7 ; nINDEX ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 388 ; 6 ; VG[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E22 ; 387 ; 6 ; VG[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F1 ; 26 ; 1 ; SCSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F2 ; 25 ; 1 ; SCSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 542 ; 8 ; LP_D[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F8 ; 531 ; 8 ; nSRWE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F9 ; 544 ; 8 ; SRD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F10 ; 525 ; 8 ; SRD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F11 ; 478 ; 7 ; nSROE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F13 ; 457 ; 7 ; SD_CD_DATA3 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F14 ; 423 ; 7 ; nSTEP ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F15 ; 419 ; 7 ; DSA_D ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F16 ; 417 ; 7 ; HD_DD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F17 ; 410 ; 6 ; nSYNC ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 397 ; 6 ; PIXEL_CLK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F20 ; 396 ; 6 ; nIRQ[4] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F21 ; 376 ; 6 ; nIRQ[2] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F22 ; 375 ; 6 ; VR[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G1 ; 67 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 66 ; 1 ; MAIN_CLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G3 ; 1 ; 1 ; SCSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G4 ; 0 ; 1 ; SCSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 5 ; 1 ; ACSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 543 ; 8 ; LP_BUSY ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G8 ; 532 ; 8 ; LP_D[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G9 ; 547 ; 8 ; SRD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G10 ; 524 ; 8 ; IO[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G11 ; 492 ; 8 ; SRD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G13 ; 444 ; 7 ; YM_QB ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G14 ; 441 ; 7 ; nWR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G15 ; 422 ; 7 ; nSTEP_DIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G16 ; 420 ; 7 ; nMOT_ON ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G17 ; 411 ; 6 ; nBLANK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G18 ; 398 ; 6 ; VB[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 345 ; 6 ; E0_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G22 ; 344 ; 6 ; IDE_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H1 ; 52 ; 1 ; nSCSI_C_D ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H2 ; 51 ; 1 ; nSCSI_MSG ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H5 ; 42 ; 1 ; MIDI_OLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H6 ; 19 ; 1 ; ACSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 18 ; 1 ; ACSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H8 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; 512 ; 8 ; SRD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H11 ; 511 ; 8 ; SRD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H14 ; 425 ; 7 ; CTS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H15 ; 424 ; 7 ; RxD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H16 ; 393 ; 6 ; VG[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H17 ; 399 ; 6 ; VB[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H18 ; 391 ; 6 ; VG[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H19 ; 386 ; 6 ; VG[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H20 ; 385 ; 6 ; nIRQ[3] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; H21 ; 365 ; 6 ; VR[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H22 ; 364 ; 6 ; VR[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J1 ; 55 ; 1 ; CLKUSB ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 53 ; 1 ; nSCSI_I_O ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J4 ; 50 ; 1 ; nACSI_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J5 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J6 ; 20 ; 1 ; SCSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J7 ; 45 ; 1 ; SCSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J8 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J17 ; 392 ; 6 ; VG[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J18 ; 374 ; 6 ; VR[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; J21 ; 363 ; 6 ; VR[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J22 ; 362 ; 6 ; VR[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K1 ; 59 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K2 ; 58 ; 1 ; ~ALTERA_DCLK~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K5 ; 60 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 41 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 46 ; 1 ; nACSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K8 ; 44 ; 1 ; SCSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; 369 ; 6 ; VR[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K18 ; 370 ; 6 ; VR[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K19 ; 357 ; 6 ; VSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K20 ; 350 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 361 ; 6 ; HSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K22 ; 360 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.0-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L1 ; 63 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 62 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 65 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 64 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 61 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 70 ; 2 ; ACSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L7 ; 79 ; 2 ; PIC_AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L8 ; 43 ; 1 ; SCSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L17 ; 349 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 348 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 73 ; 2 ; nACSI_RESET ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M2 ; 72 ; 2 ; nACSI_CS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M3 ; 75 ; 2 ; nSCSI_ATN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M4 ; 74 ; 2 ; nACSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M5 ; 80 ; 2 ; IDE_RES ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M6 ; 71 ; 2 ; ACSI_A1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M7 ; 105 ; 2 ; SCSI_PAR ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M8 ; 106 ; 2 ; nSCSI_SEL ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M16 ; 337 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 347 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 346 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 336 ; 5 ; SD_WP ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M20 ; 335 ; 5 ; SD_CARD_DEDECT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M21 ; 334 ; 5 ; VD[1] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M22 ; 333 ; 5 ; VD[0] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N1 ; 77 ; 2 ; AMKB_TX ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; N2 ; 76 ; 2 ; nSCSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N5 ; 87 ; 2 ; nRP_LDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N6 ; 104 ; 2 ; nSCSI_RST ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N7 ; 122 ; 2 ; nIRQ[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N8 ; 107 ; 2 ; nSCSI_BUSY ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 329 ; 5 ; VD[12] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N18 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 324 ; 5 ; LED_FPGA_OK ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N20 ; 323 ; 5 ; VD[15] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N21 ; 332 ; 5 ; ~ALTERA_DEV_CLRn~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N22 ; 331 ; 5 ; ~ALTERA_DEV_OE~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P1 ; 84 ; 2 ; nIDE_RD ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P2 ; 83 ; 2 ; nIDE_WR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P3 ; 89 ; 2 ; nROM3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P4 ; 88 ; 2 ; nRP_UDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P5 ; 103 ; 2 ; nIRQ[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P6 ; 131 ; 2 ; nPCI_INTD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P7 ; 123 ; 2 ; nIRQ[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P15 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 302 ; 5 ; VD[10] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 317 ; 5 ; VD[13] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P21 ; 320 ; 5 ; VD[4] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P22 ; 319 ; 5 ; VD[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R1 ; 86 ; 2 ; nIDE_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R2 ; 85 ; 2 ; nIDE_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R5 ; 135 ; 2 ; TIN0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R6 ; 136 ; 2 ; nFB_OE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R7 ; 137 ; 2 ; FB_ALE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 301 ; 5 ; VD[5] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R18 ; 309 ; 5 ; VD[9] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R19 ; 310 ; 5 ; VD[6] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R20 ; 305 ; 5 ; VD[3] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R21 ; 316 ; 5 ; VD[11] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R22 ; 315 ; 5 ; VD[14] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T1 ; 69 ; 2 ; WP_CF_CARD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T2 ; 68 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 121 ; 2 ; nFB_BURST ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T4 ; 134 ; 2 ; CLK25M ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T5 ; 133 ; 2 ; nFB_WR ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 138 ; 2 ; nFB_TA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T8 ; 166 ; 3 ; nFB_CS1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T9 ; 167 ; 3 ; nFB_CS2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T10 ; 176 ; 3 ; FB_AD[20] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T11 ; 177 ; 3 ; FB_AD[24] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T12 ; 226 ; 4 ; VD[16] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T13 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 266 ; 4 ; VDQS[3] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T17 ; 277 ; 5 ; VDM[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T18 ; 278 ; 5 ; nVCS ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 343 ; 5 ; nMASTER ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T22 ; 342 ; 5 ; TOUT0 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U1 ; 92 ; 2 ; nSCSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U2 ; 91 ; 2 ; nROM4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 146 ; 3 ; FB_SIZE0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U9 ; 170 ; 3 ; FB_AD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U10 ; 182 ; 3 ; FB_AD[21] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U11 ; 191 ; 3 ; FB_AD[27] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U12 ; 222 ; 4 ; VD[31] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U13 ; 233 ; 4 ; VD[20] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U14 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 236 ; 4 ; VCKE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U16 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U17 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 291 ; 5 ; VA[11] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U20 ; 290 ; 5 ; VDM[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U21 ; 308 ; 5 ; VD[7] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U22 ; 307 ; 5 ; VDQS[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; V1 ; 98 ; 2 ; nPD_VGA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 130 ; 2 ; nPCI_INTC ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V4 ; 129 ; 2 ; nPCI_INTB ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V5 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 141 ; 3 ; nFB_CS3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V7 ; 157 ; 3 ; FB_AD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V8 ; 171 ; 3 ; FB_AD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V9 ; 178 ; 3 ; FB_AD[18] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V10 ; 179 ; 3 ; FB_AD[19] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V11 ; 199 ; 3 ; FB_AD[28] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V12 ; 213 ; 4 ; VD[30] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V13 ; 228 ; 4 ; VD[27] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V14 ; 234 ; 4 ; VD[19] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V15 ; 237 ; 4 ; VD[21] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V16 ; 261 ; 4 ; VDM[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 304 ; 5 ; VA[10] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; V22 ; 303 ; 5 ; VD[8] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W1 ; 111 ; 2 ; nCF_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W2 ; 110 ; 2 ; nCF_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W6 ; 156 ; 3 ; FB_AD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W7 ; 168 ; 3 ; FB_AD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W8 ; 172 ; 3 ; FB_AD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W10 ; 200 ; 3 ; FB_AD[29] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 218 ; 4 ; VD[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W14 ; 229 ; 4 ; VD[22] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W15 ; 239 ; 4 ; VDQS[1] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 257 ; 4 ; nVRAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 285 ; 5 ; BA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W20 ; 280 ; 5 ; VA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W21 ; 293 ; 5 ; VA[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W22 ; 292 ; 5 ; VA[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y1 ; 113 ; 2 ; IDE_RDY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y2 ; 112 ; 2 ; AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y3 ; 148 ; 3 ; FB_AD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y4 ; 147 ; 3 ; FB_SIZE1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 152 ; 3 ; FB_AD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y7 ; 169 ; 3 ; FB_AD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y8 ; 175 ; 3 ; FB_AD[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 201 ; 3 ; FB_AD[30] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 219 ; 4 ; VD[17] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 258 ; 4 ; nVWE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 289 ; 5 ; VA[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y22 ; 288 ; 5 ; VA[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ +; Name ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ +; SDC pin name ; inst|altpll_component|auto_generated|pll1 ; inst13|altpll_component|auto_generated|pll1 ; inst12|altpll_component|auto_generated|pll1 ; inst22|altpll_component|auto_generated|pll1 ; +; PLL mode ; Source Synchronous ; Source Synchronous ; Source Synchronous ; Normal ; +; Compensate clock ; clock0 ; clock1 ; clock0 ; clock0 ; +; Compensated input/output pins ; -- ; nRD_DATA ; MAIN_CLK ; -- ; +; Switchover type ; -- ; -- ; -- ; -- ; +; Input frequency 0 ; 33.0 MHz ; 33.0 MHz ; 33.0 MHz ; 48.0 MHz ; +; Input frequency 1 ; -- ; -- ; -- ; -- ; +; Nominal PFD frequency ; 5.5 MHz ; 11.0 MHz ; 33.0 MHz ; 48.0 MHz ; +; Nominal VCO frequency ; 368.5 MHz ; 1199.0 MHz ; 396.0 MHz ; 576.0 MHz ; +; VCO post scale ; 2 ; -- ; 2 ; 2 ; +; VCO frequency control ; Auto ; Auto ; Auto ; Auto ; +; VCO phase shift step ; 339 ps ; 104 ps ; 315 ps ; 217 ps ; +; VCO multiply ; -- ; -- ; -- ; -- ; +; VCO divide ; -- ; -- ; -- ; -- ; +; Freq min lock ; 32.4 MHz ; 16.8 MHz ; 25.0 MHz ; 25.0 MHz ; +; Freq max lock ; 58.23 MHz ; 35.79 MHz ; 54.18 MHz ; 54.18 MHz ; +; M VCO Tap ; 0 ; 0 ; 0 ; 0 ; +; M Initial ; 1 ; 1 ; 1 ; 1 ; +; M value ; 67 ; 109 ; 12 ; 12 ; +; N value ; 6 ; 3 ; 1 ; 1 ; +; Charge pump current ; setting 1 ; setting 1 ; setting 1 ; setting 1 ; +; Loop filter resistance ; setting 16 ; setting 19 ; setting 27 ; setting 27 ; +; Loop filter capacitance ; setting 0 ; setting 0 ; setting 0 ; setting 0 ; +; Bandwidth ; 340 kHz to 540 kHz ; 450 kHz to 560 kHz ; 680 kHz to 980 kHz ; 680 kHz to 980 kHz ; +; Real time reconfigurable ; Off ; Off ; Off ; On ; +; Scan chain MIF file ; -- ; -- ; -- ; altpll4.mif ; +; Preserve PLL counter order ; Off ; Off ; Off ; Off ; +; PLL location ; PLL_3 ; PLL_4 ; PLL_1 ; PLL_2 ; +; Inclk0 signal ; CLK33M ; CLK33M ; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; +; Inclk1 signal ; -- ; -- ; -- ; -- ; +; Inclk0 signal type ; Global Clock ; Dedicated Pin ; Dedicated Pin ; Global Clock ; +; Inclk1 signal type ; -- ; -- ; -- ; -- ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; clock0 ; 1 ; 66 ; 0.5 MHz ; 0 (0 ps) ; 0.67 (339 ps) ; 50/50 ; C1 ; 67 ; 34/33 Odd ; C0 ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; clock1 ; 67 ; 900 ; 2.46 MHz ; 0 (0 ps) ; 0.30 (339 ps) ; 50/50 ; C2 ; 150 ; 75/75 Even ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; clock2 ; 67 ; 90 ; 24.57 MHz ; 0 (0 ps) ; 3.00 (339 ps) ; 50/50 ; C3 ; 15 ; 8/7 Odd ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[2] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 11 ; 5/6 Odd ; -- ; 1 ; 0 ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; clock0 ; 109 ; 1800 ; 2.0 MHz ; 0 (0 ps) ; 0.15 (104 ps) ; 50/50 ; C1 ; 300 ; 150/150 Even ; C0 ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[0] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; clock1 ; 109 ; 225 ; 15.99 MHz ; 0 (0 ps) ; 0.60 (104 ps) ; 50/50 ; C2 ; 75 ; 38/37 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[1] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; clock2 ; 109 ; 144 ; 24.98 MHz ; 0 (0 ps) ; 0.94 (104 ps) ; 50/50 ; C3 ; 48 ; 24/24 Even ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[2] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; clock3 ; 109 ; 75 ; 47.96 MHz ; 0 (0 ps) ; 1.80 (104 ps) ; 50/50 ; C4 ; 25 ; 13/12 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[3] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 2 ; 1/1 Even ; -- ; 1 ; 0 ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; clock0 ; 4 ; 1 ; 132.0 MHz ; 240 (5051 ps) ; 15.00 (315 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 3 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[0] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; clock1 ; 4 ; 1 ; 132.0 MHz ; 0 (0 ps) ; 15.00 (315 ps) ; 50/50 ; C3 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[1] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; clock2 ; 4 ; 1 ; 132.0 MHz ; 180 (3788 ps) ; 15.00 (315 ps) ; 50/50 ; C2 ; 3 ; 2/1 Odd ; -- ; 2 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[2] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; clock3 ; 4 ; 1 ; 132.0 MHz ; 105 (2210 ps) ; 15.00 (315 ps) ; 50/50 ; C4 ; 3 ; 2/1 Odd ; -- ; 1 ; 7 ; inst12|altpll_component|auto_generated|pll1|clk[3] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; clock4 ; 2 ; 1 ; 66.0 MHz ; 270 (11364 ps) ; 7.50 (315 ps) ; 50/50 ; C1 ; 6 ; 3/3 Even ; -- ; 5 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[4] ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; clock0 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 7.50 (217 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; inst22|altpll_component|auto_generated|pll1|clk[0] ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.0-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.0-V LVCMOS ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 3.0-V PCI ; 10 pF ; Not Available ; +; 3.0-V PCI-X ; 10 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 1.2 V ; 0 pF ; Not Available ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 2.5-V SSTL Class I ; 0 pF ; (See SSTL-2) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; 1.2-V HSTL Class I ; 0 pF ; Not Available ; +; Differential 1.2-V HSTL Class I ; 0 pF ; Not Available ; +; 1.2-V HSTL Class II ; 0 pF ; Not Available ; +; Differential 1.2-V HSTL Class II ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; LVDS_E_3R ; 0 pF ; Not Available ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS_E_1R ; 0 pF ; Not Available ; +; RSDS_E_3R ; 0 pF ; Not Available ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS_E_3R ; 0 pF ; Not Available ; +; PPDS ; 0 pF ; Not Available ; +; PPDS_E_3R ; 0 pF ; Not Available ; +; Bus LVDS ; 0 pF ; Not Available ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |firebee1 ; 9526 (10) ; 4563 (0) ; 186 (186) ; 109344 ; 23 ; 6 ; 0 ; 3 ; 295 ; 0 ; 4963 (10) ; 1465 (0) ; 3098 (0) ; |firebee1 ; work ; +; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |firebee1|DSP:Mathias_Alles ; ; +; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 4093 (640) ; 1616 (114) ; 0 (0) ; 16384 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2414 (465) ; 291 (10) ; 1388 (177) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; +; |WF1772IP_TOP_SOC:I_FDC| ; 976 (17) ; 403 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 565 (9) ; 33 (0) ; 378 (15) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; +; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 40 (40) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 26 (26) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; +; |WF1772IP_CONTROL:I_CONTROL| ; 545 (545) ; 196 (196) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 344 (344) ; 12 (12) ; 189 (189) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; +; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 51 (51) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 11 (11) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; +; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 103 (103) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 66 (66) ; 0 (0) ; 37 (37) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; +; |WF1772IP_REGISTERS:I_REGISTERS| ; 105 (105) ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (57) ; 7 (7) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; +; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 120 (120) ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 2 (2) ; 77 (77) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; +; |WF2149IP_TOP_SOC:I_SOUND| ; 490 (36) ; 197 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 293 (20) ; 37 (2) ; 160 (18) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; +; |WF2149IP_WAVE:I_PSG_WAVE| ; 461 (461) ; 181 (181) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 273 (273) ; 35 (35) ; 153 (153) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; +; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; +; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; +; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 208 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 106 (1) ; 1 (0) ; 101 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 21 (21) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 1 (1) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 54 (54) ; 0 (0) ; 47 (47) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 0 (0) ; 46 (46) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 218 (2) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 (2) ; 10 (0) ; 92 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 27 (27) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 6 (6) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (53) ; 3 (3) ; 45 (45) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 88 (88) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 1 (1) ; 38 (38) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF68901IP_TOP_SOC:I_MFP| ; 1261 (110) ; 460 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 797 (107) ; 70 (0) ; 394 (71) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; +; |WF68901IP_GPIO:I_GPIO| ; 49 (49) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 9 (9) ; 17 (17) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; +; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 290 (290) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 159 (159) ; 5 (5) ; 126 (126) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; +; |WF68901IP_TIMERS:I_TIMERS| ; 501 (501) ; 166 (166) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 332 (332) ; 44 (44) ; 125 (125) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; +; |WF68901IP_USART_TOP:I_USART| ; 316 (3) ; 140 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (3) ; 12 (0) ; 128 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; +; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 77 (77) ; 49 (49) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 9 (9) ; 40 (40) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; +; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 160 (160) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 2 (2) ; 58 (58) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; +; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 87 (87) ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 45 (45) ; 1 (1) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; +; |dcfifo0:RDF| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_0hh1:auto_generated| ; 156 (55) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (4) ; 60 (27) ; 66 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; +; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; +; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; +; |a_graycounter_fic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 13 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; +; |a_graycounter_k47:rdptr_g1p| ; 18 (18) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; +; |alt_synch_pipe_ikd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (0) ; 4 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; +; |dffpipe_hd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (14) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; +; |alt_synch_pipe_jkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (0) ; 1 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; +; |dffpipe_id9:dffpipe17| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; +; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:ws_brp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; +; |dffpipe_pe9:ws_bwp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |dcfifo1:WRF| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_3fh1:auto_generated| ; 166 (58) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (6) ; 70 (34) ; 54 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; +; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; +; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; +; |a_graycounter_gic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; +; |a_graycounter_j47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; +; |alt_synch_pipe_kkd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 3 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; +; |dffpipe_jd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; +; |alt_synch_pipe_lkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (0) ; 2 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; +; |dffpipe_kd9:dffpipe15| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; +; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:rs_bwp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 6 (6) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; +; |dffpipe_pe9:rs_brp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |Video:Fredi_Aschwanden| ; 4088 (14) ; 2168 (4) ; 0 (0) ; 92816 ; 20 ; 6 ; 0 ; 3 ; 0 ; 0 ; 1920 (10) ; 916 (4) ; 1252 (0) ; |firebee1|Video:Fredi_Aschwanden ; ; +; |DDR_CTR:DDR_CTR| ; 374 (342) ; 158 (158) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (180) ; 20 (20) ; 143 (140) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; +; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (0) ; 0 (0) ; 3 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1420 (1292) ; 529 (529) ; 0 (0) ; 0 ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; 891 (763) ; 158 (158) ; 371 (252) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; +; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (0) ; 0 (0) ; 75 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (112) ; 0 (0) ; 75 (75) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 44 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 44 (44) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; +; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; +; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; +; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; +; |altddio_bidir0:inst1| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; +; |altddio_bidir:altddio_bidir_component| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; +; |ddio_bidir_3jl:auto_generated| ; 96 (96) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (96) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; +; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; +; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; +; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; +; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; +; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; +; |lpm_ff0:inst13| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 23 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 23 (23) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst14| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 31 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst15| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (25) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst16| ; 28 (0) ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; +; |lpm_ff:lpm_ff_component| ; 28 (28) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst17| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (31) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst18| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 30 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 30 (30) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst19| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst12| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst20| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (28) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst3| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst4| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 6 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst9| ; 24 (0) ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 12 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; +; |lpm_ff:lpm_ff_component| ; 24 (24) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 12 (12) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst46| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; +; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst47| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; +; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst49| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; +; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst52| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; +; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; +; |lpm_ff4:inst10| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; +; |lpm_ff:lpm_ff_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst11| ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; +; |lpm_ff:lpm_ff_component| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst97| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; +; |lpm_ff:lpm_ff_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst71| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (0) ; 41 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; +; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (87) ; 41 (41) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst94| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (0) ; 43 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; +; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (85) ; 43 (43) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; +; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; +; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; +; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; +; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 21 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; +; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; +; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; +; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; +; |lpm_fifo_dc0:inst| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; +; |dcfifo:dcfifo_component| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; +; |dcfifo_8fi1:auto_generated| ; 118 (31) ; 98 (20) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (2) ; 51 (16) ; 47 (10) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; +; |a_graycounter_njc:wrptr_gp| ; 18 (18) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 13 (13) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 14 (14) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; +; |alt_synch_pipe_sld:ws_dgrp| ; 30 (0) ; 30 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; +; |dffpipe_re9:dffpipe22| ; 30 (30) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; +; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; +; |dffpipe_9d9:wraclr| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; +; |dffpipe_oe9:ws_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; +; |dffpipe_oe9:ws_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; +; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; +; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; +; |lpm_mux0:inst21| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; +; |lpm_mux:lpm_mux_component| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; +; |mux_gpe:auto_generated| ; 120 (120) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 71 (71) ; 27 (27) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; +; |lpm_mux1:inst24| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; +; |lpm_mux:lpm_mux_component| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; +; |mux_npe:auto_generated| ; 113 (113) ; 81 (81) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 33 (33) ; 48 (48) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; +; |lpm_mux2:inst25| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; +; |lpm_mux:lpm_mux_component| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; +; |mux_mpe:auto_generated| ; 81 (81) ; 41 (41) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 1 (1) ; 40 (40) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; +; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; +; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; +; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; +; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; +; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; +; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; +; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; +; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; +; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 60 (60) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; +; |lpm_mux6:inst7| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; +; |lpm_mux:lpm_mux_component| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; +; |mux_kpe:auto_generated| ; 91 (91) ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 82 (82) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; +; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; +; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; +; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (128) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; +; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; +; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; +; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (640) ; 0 (0) ; 96 (96) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; +; |lpm_shiftreg0:sr0| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr1| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr2| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr3| ; 17 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 17 (17) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr4| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr5| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg4:inst26| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg6:inst92| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; +; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; +; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; +; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; +; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; +; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; +; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; +; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9 ; work ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; +; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst ; ; +; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component ; ; +; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; +; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; +; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; +; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; +; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; +; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; +; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; +; |altpll_reconfig1:inst7| ; 334 (0) ; 128 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (0) ; 22 (0) ; 106 (0) ; |firebee1|altpll_reconfig1:inst7 ; ; +; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 334 (237) ; 128 (80) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (157) ; 22 (22) ; 106 (57) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; +; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; +; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; +; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 1 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; +; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; +; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; +; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 6 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; +; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; +; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; +; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; +; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; +; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; +; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; +; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; +; |interrupt_handler:nobody| ; 1037 (999) ; 633 (633) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 401 (363) ; 235 (235) ; 401 (355) ; |firebee1|interrupt_handler:nobody ; ; +; |lpm_bustri_BYT:$00000| ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 9 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 9 (9) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 8 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 8 (8) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 14 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 14 (14) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 15 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; +; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; +; |lpm_counter0:inst18| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18 ; ; +; |lpm_counter:lpm_counter_component| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; +; |cntr_mph:auto_generated| ; 19 (19) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 17 (17) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; +; |lpm_ff0:inst1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ +; CLK24M576 ; Output ; -- ; -- ; -- ; -- ; -- ; +; LP_STR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nFB_BURST ; Input ; -- ; -- ; -- ; -- ; -- ; +; nACSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; +; nACSI_INT ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_MSG ; Input ; -- ; -- ; -- ; -- ; -- ; +; nDCHG ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA1 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA2 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_CARD_DEDECT ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_WP ; Input ; -- ; -- ; -- ; -- ; -- ; +; nDACK0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; WP_CF_CARD ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_C_D ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_I_O ; Input ; -- ; -- ; -- ; -- ; -- ; +; nFB_CS3 ; Input ; -- ; -- ; -- ; -- ; -- ; +; CLK25M ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_RESET ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_CS ; Output ; -- ; -- ; -- ; -- ; -- ; +; ACSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; +; ACSI_A1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_ATN ; Output ; -- ; -- ; -- ; -- ; -- ; +; SCSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; +; MIDI_OLR ; Output ; -- ; -- ; -- ; -- ; -- ; +; MIDI_TLR ; Output ; -- ; -- ; -- ; -- ; -- ; +; TxD ; Output ; -- ; -- ; -- ; -- ; -- ; +; RTS ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DTR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; AMKB_TX ; Output ; -- ; -- ; -- ; -- ; -- ; +; IDE_RES ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_WR ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_RD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nCF_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nCF_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nROM3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nROM4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nRP_UDS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nRP_LDS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSDSEL ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nWR_GATE ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nWR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; YM_QA ; Output ; -- ; -- ; -- ; -- ; -- ; +; YM_QB ; Output ; -- ; -- ; -- ; -- ; -- ; +; YM_QC ; Output ; -- ; -- ; -- ; -- ; -- ; +; SD_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; DSA_D ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nVWE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVCAS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVRAS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVCS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nPD_VGA ; Output ; -- ; -- ; -- ; -- ; -- ; +; TIN0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRCS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRBLE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRBHE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRWE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nDREQ1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED_FPGA_OK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSROE ; Output ; -- ; -- ; -- ; -- ; -- ; +; VCKE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nFB_TA ; Output ; -- ; -- ; -- ; -- ; -- ; +; nDDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; DDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; VSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; HSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nBLANK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; PIXEL_CLK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSYNC ; Output ; -- ; -- ; -- ; -- ; -- ; +; nMOT_ON ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSTEP_DIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSTEP ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; CLKUSB ; Output ; -- ; -- ; -- ; -- ; -- ; +; LPDIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; BA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; BA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[12] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[11] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[10] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VB[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; TOUT0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; nMASTER ; Input ; -- ; -- ; -- ; -- ; -- ; +; FB_AD[31] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[30] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[29] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[28] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[27] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[26] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[25] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[24] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[23] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[22] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[21] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[20] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[19] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[18] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[17] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[16] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[15] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[14] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[13] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[12] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[11] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[10] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[9] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[8] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[7] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[6] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[5] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[4] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[3] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[2] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[1] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[0] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; VD[31] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[30] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[29] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[28] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[27] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[26] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[25] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[24] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[23] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[22] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[21] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[20] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[19] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[18] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[17] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[16] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[15] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[13] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[12] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[11] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[10] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[9] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[8] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[6] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[3] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[2] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[1] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[0] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VDQS[3] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[2] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[1] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[0] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; IO[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SRD[15] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[13] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[12] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[11] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[10] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[9] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[8] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[6] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[4] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[3] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[2] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[1] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[0] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SCSI_PAR ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_SEL ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_BUSY ; Bidir ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSCSI_RST ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SD_CD_DATA3 ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SD_CMD_D1 ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; LP_D[7] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[6] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[3] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[2] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[1] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[0] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; SCSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nRSTO_MCF ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nFB_WR ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nFB_CS1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_SIZE1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_SIZE0 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_ALE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nFB_CS2 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; MAIN_CLK ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nDACK1 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nFB_OE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; IDE_RDY ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; CLK33M ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; HD_DD ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nINDEX ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; RxD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nWP ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; LP_BUSY ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; DCD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; CTS ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; TRACK00 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; IDE_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; RI ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTD ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTC ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; nPCI_INTB ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTA ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; DVI_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; E0_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; PIC_INT ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; PIC_AMKB_RX ; Input ; (1) 663 ps ; -- ; -- ; -- ; -- ; +; MIDI_IN ; Input ; -- ; (1) 634 ps ; -- ; -- ; -- ; +; nRD_DATA ; Input ; -- ; -- ; (0) 0 ps ; -- ; -- ; +; AMKB_RX ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; nFB_BURST ; ; ; +; nACSI_DRQ ; ; ; +; nACSI_INT ; ; ; +; nSCSI_DRQ ; ; ; +; nSCSI_MSG ; ; ; +; nDCHG ; ; ; +; SD_DATA0 ; ; ; +; SD_DATA1 ; ; ; +; SD_DATA2 ; ; ; +; SD_CARD_DEDECT ; ; ; +; SD_WP ; ; ; +; nDACK0 ; ; ; +; WP_CF_CARD ; ; ; +; nSCSI_C_D ; ; ; +; nSCSI_I_O ; ; ; +; nFB_CS3 ; ; ; +; TOUT0 ; ; ; +; nMASTER ; ; ; +; FB_AD[31] ; ; ; +; - SRD[15]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~32 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[31] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[31]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[30] ; ; ; +; - SRD[14]~output ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[30]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[14] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[30] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[29] ; ; ; +; - SRD[13]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[29] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[29]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[29] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[29]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[28] ; ; ; +; - SRD[12]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[28] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[28]~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[28]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[27] ; ; ; +; - SRD[11]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[27]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[27] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[27] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[11]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[27]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[26] ; ; ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - SRD[10]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[12]~53 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[26]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[26] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[26] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[10]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[25] ; ; ; +; - SRD[9]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[11]~55 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[25]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[25] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[25] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[25]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[24] ; ; ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]~22 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - SRD[8]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[10]~58 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[24]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[24] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[24] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[24] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]~29 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; +; FB_AD[23] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]~20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[7]~0 ; 1 ; 0 ; +; - SRD[7]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[9]~60 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[23]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[23] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][45] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[7] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][0]~73 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][2]~74 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][4]~75 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~10 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[7] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~24 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][55]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][19]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][8]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[22] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[6]~0 ; 1 ; 0 ; +; - SRD[6]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[8]~62 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[22] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[22] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][11] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][25] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][33] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][38] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][41] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][53] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][62] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[6] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][0]~78 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][2]~79 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][4]~80 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[6]~12 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[6] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~30 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~30 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][63]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][32]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][30]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][56]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][18]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[22]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[21] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[5]~1 ; 1 ; 0 ; +; - SRD[5]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[7]~64 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[5] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][2]~82 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][4]~83 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][0]~85 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[5]~15 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[5] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~36 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~36 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][8]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][20]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][45]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][50]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][61]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[20] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]~2 ; 1 ; 0 ; +; - SRD[4]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[6]~66 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[4] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][2]~86 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][4]~87 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][0]~89 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[4]~18 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~42 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~42 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]~27 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][58]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][22]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][50]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][61]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[19] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[3]~3 ; 1 ; 0 ; +; - SRD[3]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[5]~68 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][8] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[3] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[3]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][2]~90 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][4]~91 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][0]~93 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~47 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~47 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[3]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][61]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][58]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][50]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[18] ; ; ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[2]~4 ; 1 ; 0 ; +; - SRD[2]~output ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[4]~70 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[18] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]~13 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][24] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][33] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][41] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][49] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~6 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][0]~69 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][2]~70 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][4]~71 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[2]~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~18 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]~21 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[2]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][30]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][43]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[2]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][55]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][58]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][36]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][52]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[17] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[1]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[1] ; 1 ; 0 ; +; - SRD[1]~output ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[3]~72 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][49] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][53] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][62] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][0]~65 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][2]~66 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][4]~67 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[1]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~12 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]~18 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][59]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][50]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][48]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][22]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][56]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][63]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][44]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][52]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][32]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][39]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][33]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[16] ; ; ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[0]~6 ; 1 ; 0 ; +; - SRD[0]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VWE ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[16] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[2]~74 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[16] ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][22] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][24] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][38] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][2]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][4]~6 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][13]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~6 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~15 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][59]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][29]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[16]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][31]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][39]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][55]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][19]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[0]~feeder ; 1 ; 0 ; +; FB_AD[15] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[1]~76 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[15] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[14] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[0]~78 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[14] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[14] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[13] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[1]~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[13] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[12] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[0]~11 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[11] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[10] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[10] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[9] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[9] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[8] ; ; ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]~13 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]~23 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[8]~feeder ; 1 ; 0 ; +; FB_AD[7] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[6] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]~23 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[6]~25 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[5] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]~26 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[5]~26 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[4] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]~29 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[4]~27 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[3] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]~32 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[3]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[2] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]~35 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[2]~29 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[1] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]~41 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]~30 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[0] ; ; ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]~43 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[0]~31 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; +; VD[31] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]~feeder ; 0 ; 1 ; +; VD[30] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]~feeder ; 1 ; 1 ; +; VD[29] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]~feeder ; 1 ; 1 ; +; VD[28] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]~feeder ; 1 ; 1 ; +; VD[27] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]~feeder ; 1 ; 1 ; +; VD[26] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]~feeder ; 1 ; 0 ; +; VD[25] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]~feeder ; 0 ; 1 ; +; VD[24] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]~feeder ; 1 ; 1 ; +; VD[23] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]~feeder ; 0 ; 0 ; +; VD[22] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]~feeder ; 1 ; 1 ; +; VD[21] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]~feeder ; 1 ; 1 ; +; VD[20] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]~feeder ; 1 ; 1 ; +; VD[19] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]~feeder ; 0 ; 1 ; +; VD[18] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]~feeder ; 0 ; 0 ; +; VD[17] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]~feeder ; 1 ; 1 ; +; VD[16] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]~feeder ; 0 ; 0 ; +; VD[15] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]~feeder ; 0 ; 2 ; +; VD[14] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]~feeder ; 1 ; 0 ; +; VD[13] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]~feeder ; 0 ; 2 ; +; VD[12] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]~feeder ; 0 ; 2 ; +; VD[11] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]~feeder ; 1 ; 2 ; +; VD[10] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]~feeder ; 0 ; 2 ; +; VD[9] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]~feeder ; 0 ; 2 ; +; VD[8] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]~feeder ; 0 ; 0 ; +; VD[7] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]~feeder ; 0 ; 0 ; +; VD[6] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]~feeder ; 0 ; 2 ; +; VD[5] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]~feeder ; 0 ; 0 ; +; VD[4] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]~feeder ; 0 ; 0 ; +; VD[3] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]~feeder ; 1 ; 2 ; +; VD[2] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]~feeder ; 1 ; 2 ; +; VD[1] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]~feeder ; 0 ; 2 ; +; VD[0] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]~feeder ; 0 ; 2 ; +; VDQS[3] ; ; ; +; VDQS[2] ; ; ; +; VDQS[1] ; ; ; +; VDQS[0] ; ; ; +; IO[17] ; ; ; +; IO[16] ; ; ; +; IO[15] ; ; ; +; IO[14] ; ; ; +; IO[13] ; ; ; +; IO[12] ; ; ; +; IO[11] ; ; ; +; IO[10] ; ; ; +; IO[9] ; ; ; +; IO[8] ; ; ; +; IO[7] ; ; ; +; IO[6] ; ; ; +; IO[5] ; ; ; +; IO[4] ; ; ; +; IO[3] ; ; ; +; IO[2] ; ; ; +; IO[1] ; ; ; +; IO[0] ; ; ; +; SRD[15] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~156 ; 1 ; 0 ; +; SRD[14] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~131 ; 1 ; 0 ; +; SRD[13] ; ; ; +; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; +; SRD[12] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; 0 ; 0 ; +; SRD[11] ; ; ; +; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; +; SRD[10] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~197 ; 1 ; 0 ; +; SRD[9] ; ; ; +; - DSP:Mathias_Alles|FB_AD[25]~0 ; 1 ; 0 ; +; SRD[8] ; ; ; +; - DSP:Mathias_Alles|FB_AD[24]~1 ; 1 ; 0 ; +; SRD[7] ; ; ; +; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; +; SRD[6] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~269 ; 1 ; 0 ; +; SRD[5] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~285 ; 0 ; 0 ; +; SRD[4] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~301 ; 1 ; 0 ; +; SRD[3] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~319 ; 1 ; 0 ; +; SRD[2] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~172 ; 0 ; 0 ; +; SRD[1] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~86 ; 1 ; 0 ; +; SRD[0] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; 0 ; 0 ; +; SCSI_PAR ; ; ; +; nSCSI_SEL ; ; ; +; nSCSI_BUSY ; ; ; +; nSCSI_RST ; ; ; +; SD_CD_DATA3 ; ; ; +; SD_CMD_D1 ; ; ; +; ACSI_D[7] ; ; ; +; ACSI_D[6] ; ; ; +; ACSI_D[5] ; ; ; +; ACSI_D[4] ; ; ; +; ACSI_D[3] ; ; ; +; ACSI_D[2] ; ; ; +; ACSI_D[1] ; ; ; +; ACSI_D[0] ; ; ; +; LP_D[7] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~142 ; 1 ; 0 ; +; LP_D[6] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~112 ; 0 ; 0 ; +; LP_D[5] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~339 ; 0 ; 0 ; +; LP_D[4] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~378 ; 0 ; 0 ; +; LP_D[3] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~383 ; 1 ; 0 ; +; LP_D[2] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~186 ; 1 ; 0 ; +; LP_D[1] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~206 ; 0 ; 0 ; +; LP_D[0] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~227 ; 0 ; 0 ; +; SCSI_D[7] ; ; ; +; SCSI_D[6] ; ; ; +; SCSI_D[5] ; ; ; +; SCSI_D[4] ; ; ; +; SCSI_D[3] ; ; ; +; SCSI_D[2] ; ; ; +; SCSI_D[1] ; ; ; +; SCSI_D[0] ; ; ; +; nRSTO_MCF ; ; ; +; nFB_WR ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SUB_BUS~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; +; - DSP:Mathias_Alles|nSRWE~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPIO_REGISTERS~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector0~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~11 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[31]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|Selector1~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~19 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CONTROL~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~15 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT_EN~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR_READ~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR_READ~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_EN~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|Mux1~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DATA_EN~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~6 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT~5 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~17 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~218 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~42 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~238 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~35 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~37 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~350 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[3]~1 ; 0 ; 0 ; +; - DSP:Mathias_Alles|nSRWE~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nFDC_WR~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[23]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[23]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[5]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~491 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][0]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][1]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~492 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][3]~5 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~496 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][5]~9 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~503 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~504 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~505 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~506 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][10]~10 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][12]~11 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][13]~13 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][14]~15 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][15]~16 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][16]~17 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][17]~18 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][18]~19 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][19]~20 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][20]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][21]~22 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][22]~23 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][23]~24 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][24]~25 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][25]~26 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][26]~27 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][27]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][28]~29 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][29]~30 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][30]~31 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][31]~32 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][32]~33 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][33]~34 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][34]~35 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][35]~36 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][36]~37 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][37]~38 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][38]~39 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][39]~40 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][40]~41 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][41]~42 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][42]~43 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][43]~44 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][44]~45 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][45]~46 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][46]~47 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][47]~48 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][48]~49 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][49]~50 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][50]~51 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][51]~52 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][52]~53 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][53]~54 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][54]~55 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][55]~56 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][56]~57 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][57]~58 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][58]~59 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][59]~60 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][60]~61 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][61]~62 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][62]~63 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][63]~64 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~2 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[31]~3 ; 0 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~4 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_WR~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_RECONFIG~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][11]~77 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_2~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; 0 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state~2 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state~0 ; 1 ; 0 ; +; nFB_CS1 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE_CS ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT_CS~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF_CS ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW_CS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|MFP_CS~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|NEXT_CMD_STATE.T1~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector2~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~28 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~32 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_M ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_H ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~6 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~36 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~37 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~38 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~39 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~27 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~40 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~41 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[9]~81 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~43 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~38 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~44 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~45 ; 1 ; 0 ; +; - interrupt_handler:nobody|TIN0~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_L ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~46 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~47 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~48 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~49 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~50 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~51 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~52 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~53 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~54 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~55 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~34 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~35 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[2]~36 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; 1 ; 0 ; +; FB_SIZE1 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[0]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~22 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_AS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~6 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[2]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 1 ; 0 ; +; FB_SIZE0 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_AS~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~6 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[2]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 0 ; 0 ; +; FB_ALE ; ; ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; 1 ; 0 ; +; nFB_CS2 ; ; ; +; - DSP:Mathias_Alles|nSRCS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~4 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_RECONFIG_CS~0 ; 0 ; 0 ; +; - inst2~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_CONFIG_CS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~23 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~25 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~13 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~14 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~147 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~148 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~195 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~196 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~198 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~199 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~200 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~201 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~24 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~25 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~246 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~247 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~35 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~41 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~42 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~248 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~46 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~47 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~295 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~53 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~54 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~338 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~339 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~60 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~61 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~382 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~383 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~67 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~68 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~426 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~427 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~470 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~471 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~473 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~474 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~71 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~475 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~476 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~73 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~74 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~477 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~75 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~76 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~480 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~77 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~78 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~79 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~80 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~483 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~484 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~485 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~486 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~487 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~488 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~489 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~490 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[15]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[15]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42 ; 0 ; 0 ; +; MAIN_CLK ; ; ; +; nDACK1 ; ; ; +; nFB_OE ; ; ; +; - DSP:Mathias_Alles|nSROE~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~39 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~43 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~45 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~47 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~48 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_RD ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_RD ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~51 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[3]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[0]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~55 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~56 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[1]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[2]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~59 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~60 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~61 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~65 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~67 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~70 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~72 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~77 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[3]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[1]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~85 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~89 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~94 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~111 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~124 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~127 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~129 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDH ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[14]~34 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[15]~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~154 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~160 ; 1 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[2]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDL~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~170 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~175 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~176 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~179 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~181 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~182 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~193 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~195 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~211 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[25]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~215 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~220 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[24]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~235 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~240 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[7]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~250 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~255 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[6]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~267 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~272 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[5]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~283 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~288 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[4]~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~299 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~304 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~308 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~312 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[3]~21 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~317 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[15]~327 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~352 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~356 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[13]~173 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~366 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~375 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~388 ; 1 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~392 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[11]~186 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~411 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~415 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~420 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~424 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[7]~432 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[6]~437 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[5]~445 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[4]~453 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[3]~461 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[2]~469 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~490 ; 1 ; 0 ; +; IDE_RDY ; ; ; +; - inst2~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_TA~0 ; 1 ; 0 ; +; CLK33M ; ; ; +; HD_DD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|HD_DD_OUT~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~62 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PHASE_DECODER~0 ; 1 ; 0 ; +; nINDEX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~78 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOCK~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~113 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~173 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_COUNTER~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~205 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DRQ_IPn~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_INDEX_MARK:LOCK~0 ; 0 ; 0 ; +; - nINDEX~_wirecell ; 0 ; 0 ; +; RxD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|SDATA_IN_I~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SDATA_IN_I~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_SAMPLE~6 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_START_BIT~0 ; 0 ; 0 ; +; nWP ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~85 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~168 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~176 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR~0 ; 1 ; 0 ; +; LP_BUSY ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[0]~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~15 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~15 ; 0 ; 0 ; +; DCD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[1]~43 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~10 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~10 ; 0 ; 0 ; +; CTS ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[2]~63 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~9 ; 1 ; 0 ; +; TRACK00 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TR_CLR ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~18 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~22 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~24 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~26 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~28 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~103 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; 0 ; 0 ; +; IDE_INT ; ; ; +; RI ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT~104 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~11 ; 1 ; 0 ; +; nPCI_INTD ; ; ; +; - interrupt_handler:nobody|INT_LATCH[6]~11 ; 0 ; 6 ; +; - interrupt_handler:nobody|_~484 ; 1 ; 0 ; +; nPCI_INTC ; ; ; +; - interrupt_handler:nobody|INT_LATCH[5]~12 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[5]~5 ; 0 ; 0 ; +; nPCI_INTB ; ; ; +; - interrupt_handler:nobody|INT_LATCH[4]~13 ; 0 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[4]~8 ; 1 ; 0 ; +; nPCI_INTA ; ; ; +; - interrupt_handler:nobody|INT_LATCH[3]~14 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[3]~11 ; 0 ; 0 ; +; DVI_INT ; ; ; +; E0_INT ; ; ; +; PIC_INT ; ; ; +; - interrupt_handler:nobody|INT_LATCH[0]~17 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[0]~20 ; 0 ; 0 ; +; - interrupt_handler:nobody|PIC_INT_SYNC[0] ; 0 ; 0 ; +; PIC_AMKB_RX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|KEYB_RxD ; 0 ; 1 ; +; MIDI_IN ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_I~feeder ; 1 ; 1 ; +; nRD_DATA ; ; ; +; AMKB_RX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~11 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]~9 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]~7 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; 1 ; 0 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ +; CLK33M ; PIN_AB12 ; 12 ; Clock ; yes ; Global Clock ; GCLK15 ; -- ; +; CLK33M ; PIN_AB12 ; 5 ; Clock ; no ; -- ; -- ; -- ; +; DSP:Mathias_Alles|nSRWE~1 ; LCCOMB_X23_Y8_N20 ; 16 ; Output enable ; no ; -- ; -- ; -- ; +; FB_ALE ; PIN_R7 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; LCCOMB_X1_Y10_N14 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; LCCOMB_X18_Y17_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; LCCOMB_X22_Y14_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; LCCOMB_X22_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~0 ; LCCOMB_X16_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]~1 ; LCCOMB_X16_Y14_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 ; LCCOMB_X21_Y12_N8 ; 16 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 ; LCCOMB_X22_Y13_N12 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 ; LCCOMB_X22_Y13_N30 ; 4 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 ; LCCOMB_X22_Y13_N4 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 ; LCCOMB_X22_Y13_N16 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 ; LCCOMB_X22_Y13_N10 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 ; LCCOMB_X33_Y1_N4 ; 5 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector4~1 ; LCCOMB_X23_Y18_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~1 ; LCCOMB_X22_Y13_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|Equal0~4 ; LCCOMB_X22_Y28_N30 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]~1 ; LCCOMB_X21_Y28_N6 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]~3 ; LCCOMB_X21_Y28_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SHFT ; FF_X34_Y29_N7 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SHFT_LOAD_ND~0 ; LCCOMB_X28_Y27_N8 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; LCCOMB_X35_Y25_N2 ; 88 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector78~0 ; LCCOMB_X32_Y25_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor2~5 ; LCCOMB_X36_Y28_N0 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor8 ; LCCOMB_X28_Y27_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]~1 ; LCCOMB_X32_Y27_N4 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]~37 ; LCCOMB_X27_Y26_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT~27 ; LCCOMB_X30_Y30_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; FF_X30_Y32_N13 ; 18 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]~1 ; LCCOMB_X27_Y32_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; FF_X32_Y25_N31 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]~1 ; LCCOMB_X32_Y25_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Equal3~2 ; LCCOMB_X27_Y25_N14 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~1 ; LCCOMB_X29_Y25_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]~9 ; LCCOMB_X28_Y27_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG~8 ; LCCOMB_X30_Y28_N22 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~1 ; LCCOMB_X30_Y26_N20 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]~3 ; LCCOMB_X30_Y26_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT~1 ; LCCOMB_X28_Y30_N28 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT~12 ; LCCOMB_X36_Y29_N10 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK~0 ; LCCOMB_X25_Y29_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]~0 ; LCCOMB_X25_Y27_N6 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; LCCOMB_X18_Y19_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; LCCOMB_X15_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; FF_X4_Y41_N5 ; 8 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; LCCOMB_X7_Y39_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; LCCOMB_X19_Y23_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WAV_STRB ; FF_X9_Y21_N23 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; LCCOMB_X17_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET ; FF_X18_Y22_N21 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; LCCOMB_X18_Y22_N20 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; LCCOMB_X18_Y24_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB~1 ; LCCOMB_X18_Y23_N8 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal14~3 ; LCCOMB_X20_Y21_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal16~3 ; LCCOMB_X19_Y24_N20 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal18~3 ; LCCOMB_X18_Y20_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; LCCOMB_X15_Y14_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; LCCOMB_X20_Y23_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; LCCOMB_X19_Y24_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; LCCOMB_X20_Y20_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; LCCOMB_X18_Y20_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; LCCOMB_X17_Y18_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; LCCOMB_X17_Y25_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; LCCOMB_X20_Y22_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; LCCOMB_X21_Y27_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; LCCOMB_X17_Y19_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT~1 ; LCCOMB_X17_Y25_N24 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]~12 ; LCCOMB_X18_Y25_N10 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]~0 ; LCCOMB_X16_Y24_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]~0 ; LCCOMB_X16_Y24_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]~2 ; LCCOMB_X16_Y24_N24 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]~0 ; LCCOMB_X6_Y18_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N12 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]~1 ; LCCOMB_X5_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X2_Y21_N28 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]~1 ; LCCOMB_X5_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]~1 ; LCCOMB_X1_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X1_Y19_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]~1 ; LCCOMB_X3_Y19_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]~1 ; LCCOMB_X2_Y19_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X1_Y20_N15 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]~3 ; LCCOMB_X1_Y20_N26 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]~1 ; LCCOMB_X7_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]~1 ; LCCOMB_X5_Y16_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X3_Y17_N26 ; 6 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]~1 ; LCCOMB_X4_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]~1 ; LCCOMB_X3_Y17_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X5_Y20_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]~1 ; LCCOMB_X4_Y21_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]~1 ; LCCOMB_X5_Y21_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X6_Y19_N27 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]~1 ; LCCOMB_X6_Y19_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; LCCOMB_X14_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; LCCOMB_X14_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; LCCOMB_X14_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; LCCOMB_X14_Y16_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; LCCOMB_X14_Y16_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; LCCOMB_X16_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; LCCOMB_X16_Y19_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[9]~5 ; LCCOMB_X17_Y21_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST ; FF_X16_Y17_N3 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[0]~7 ; LCCOMB_X17_Y17_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]~0 ; LCCOMB_X16_Y16_N4 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_A~0 ; LCCOMB_X6_Y20_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_B~0 ; LCCOMB_X6_Y20_N8 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_C~0 ; LCCOMB_X3_Y20_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_D~0 ; LCCOMB_X9_Y17_N6 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; LCCOMB_X12_Y16_N22 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~0 ; LCCOMB_X8_Y20_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; LCCOMB_X10_Y18_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~0 ; LCCOMB_X7_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; LCCOMB_X12_Y18_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~0 ; LCCOMB_X10_Y15_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]~0 ; LCCOMB_X4_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERC~1 ; LCCOMB_X10_Y15_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERD~1 ; LCCOMB_X3_Y15_N4 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[0]~0 ; LCCOMB_X10_Y18_N16 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[0]~3 ; LCCOMB_X12_Y17_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[0]~1 ; LCCOMB_X11_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[0]~1 ; LCCOMB_X11_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL_STRB ; FF_X3_Y20_N7 ; 44 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]~0 ; LCCOMB_X14_Y19_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]~0 ; LCCOMB_X14_Y22_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]~1 ; LCCOMB_X14_Y19_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]~0 ; LCCOMB_X12_Y16_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; FF_X14_Y20_N1 ; 19 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~3 ; LCCOMB_X11_Y19_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]~2 ; LCCOMB_X10_Y24_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]~1 ; LCCOMB_X10_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[0]~0 ; LCCOMB_X3_Y27_N20 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT~1 ; LCCOMB_X14_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|CLK_STRB ; FF_X2_Y27_N7 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFTREG~0 ; LCCOMB_X12_Y21_N12 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]~8 ; LCCOMB_X12_Y23_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TX_END ; FF_X12_Y23_N17 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|_~0 ; LCCOMB_X21_Y9_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1 ; LCCOMB_X23_Y7_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_wrreq~1 ; LCCOMB_X18_Y18_N20 ; 18 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|_~0 ; LCCOMB_X22_Y22_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_rdreq~1 ; LCCOMB_X22_Y22_N4 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_wrreq~0 ; LCCOMB_X26_Y24_N4 ; 22 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; LCCOMB_X20_Y16_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; LCCOMB_X20_Y16_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ; +; MAIN_CLK ; PIN_G2 ; 2272 ; Clock ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; FF_X23_Y12_N17 ; 26 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]~1 ; LCCOMB_X27_Y6_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; LCCOMB_X22_Y2_N22 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; LCCOMB_X34_Y2_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; LCCOMB_X21_Y4_N10 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; LCCOMB_X34_Y2_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]~40 ; LCCOMB_X26_Y8_N24 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; LCCOMB_X26_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; LCCOMB_X26_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; LCCOMB_X25_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; LCCOMB_X23_Y11_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[1] ; LCCOMB_X25_Y16_N22 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[2] ; LCCOMB_X25_Y14_N26 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[3] ; LCCOMB_X25_Y16_N0 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; LCCOMB_X22_Y19_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; LCCOMB_X23_Y12_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; LCCOMB_X27_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; LCCOMB_X23_Y18_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; LCCOMB_X28_Y18_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; LCCOMB_X21_Y19_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; LCCOMB_X29_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; LCCOMB_X23_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; LCCOMB_X23_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; LCCOMB_X23_Y19_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; LCCOMB_X28_Y15_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; LCCOMB_X25_Y17_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; LCCOMB_X22_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; LCCOMB_X21_Y19_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; LCCOMB_X28_Y15_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; LCCOMB_X28_Y17_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; LCCOMB_X28_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; LCCOMB_X23_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; LCCOMB_X29_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; LCCOMB_X25_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; LCCOMB_X25_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; LCCOMB_X22_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; LCCOMB_X29_Y18_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; LCCOMB_X23_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; FF_X33_Y18_N13 ; 54 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; FF_X33_Y18_N15 ; 54 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_FIFO_CLR ; FF_X36_Y17_N25 ; 21 ; Async. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; LCCOMB_X23_Y16_N24 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[1] ; LCCOMB_X23_Y16_N8 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[3] ; LCCOMB_X23_Y16_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; LCCOMB_X28_Y16_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; LCCOMB_X28_Y16_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; FF_X37_Y20_N27 ; 141 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; FF_X33_Y12_N25 ; 30 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 3 ; Clock ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0] ; LCCOMB_X26_Y13_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[1] ; LCCOMB_X21_Y13_N14 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; LCCOMB_X29_Y17_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[6]~7 ; LCCOMB_X35_Y17_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX ; FF_X34_Y14_N13 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; LCCOMB_X26_Y16_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]~1 ; LCCOMB_X30_Y13_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]~0 ; LCCOMB_X30_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~1 ; LCCOMB_X30_Y10_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]~0 ; LCCOMB_X29_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]~1 ; LCCOMB_X30_Y10_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]~0 ; LCCOMB_X29_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]~1 ; LCCOMB_X33_Y13_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]~0 ; LCCOMB_X33_Y13_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]~1 ; LCCOMB_X30_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]~0 ; LCCOMB_X30_Y12_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]~1 ; LCCOMB_X29_Y14_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]~0 ; LCCOMB_X26_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; LCCOMB_X26_Y17_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; LCCOMB_X27_Y15_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; LCCOMB_X26_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; LCCOMB_X26_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]~1 ; LCCOMB_X30_Y15_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~0 ; LCCOMB_X29_Y15_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]~1 ; LCCOMB_X25_Y13_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~0 ; LCCOMB_X30_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; LCCOMB_X26_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; LCCOMB_X26_Y13_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]~1 ; LCCOMB_X29_Y14_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]~0 ; LCCOMB_X29_Y13_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]~1 ; LCCOMB_X30_Y15_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]~0 ; LCCOMB_X29_Y16_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]~1 ; LCCOMB_X26_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]~0 ; LCCOMB_X27_Y16_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; LCCOMB_X25_Y18_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; LCCOMB_X27_Y18_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; LCCOMB_X26_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~3 ; LCCOMB_X27_Y18_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~92 ; LCCOMB_X28_Y20_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst37 ; LCCOMB_X66_Y4_N2 ; 32 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst65~0 ; LCCOMB_X37_Y20_N28 ; 34 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst67 ; LCCOMB_X37_Y17_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90 ; DDIOOECELL_X63_Y0_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; DDIOOECELL_X67_Y11_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; DDIOOECELL_X52_Y0_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; DDIOOECELL_X43_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst95 ; FF_X39_Y18_N21 ; 128 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|_~0 ; LCCOMB_X36_Y20_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; Async. clear ; yes ; Global Clock ; GCLK9 ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 ; LCCOMB_X57_Y17_N14 ; 14 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X45_Y15_N1 ; 258 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X18_Y13_N29 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; FF_X18_Y13_N3 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; Clock, Latch enable ; yes ; Global Clock ; GCLK4 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; Clock ; yes ; Global Clock ; GCLK16 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; Clock ; yes ; Global Clock ; GCLK17 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~1 ; LCCOMB_X23_Y26_N8 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|busy ; LCCOMB_X22_Y25_N2 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|input_latch_enable~0 ; LCCOMB_X22_Y26_N10 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X14_Y25_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|_~0 ; LCCOMB_X19_Y28_N4 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X21_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|_~9 ; LCCOMB_X21_Y27_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X18_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|_~0 ; LCCOMB_X21_Y26_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~4 ; LCCOMB_X21_Y26_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~5 ; LCCOMB_X21_Y27_N12 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~0 ; LCCOMB_X21_Y29_N6 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~1 ; LCCOMB_X18_Y29_N24 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; FF_X22_Y29_N31 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|scan_cache_write_enable~0 ; LCCOMB_X20_Y26_N4 ; 3 ; Write enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~3 ; LCCOMB_X22_Y23_N2 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg_clear~0 ; LCCOMB_X22_Y27_N28 ; 35 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; FF_X21_Y25_N29 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK10 ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 119 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACHTELSEKUNDEN[2]~0 ; LCCOMB_X1_Y13_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[15]~3 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[23]~1 ; LCCOMB_X11_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[31]~0 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[7]~4 ; LCCOMB_X15_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[0] ; FF_X17_Y10_N9 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[1] ; FF_X17_Y10_N31 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[2] ; FF_X17_Y10_N1 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[3] ; FF_X17_Y10_N23 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[4] ; FF_X17_Y10_N21 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[5] ; FF_X17_Y10_N11 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[6] ; FF_X17_Y10_N25 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[8] ; FF_X17_Y10_N15 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[9] ; FF_X17_Y10_N29 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[15]~2 ; LCCOMB_X15_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[23]~1 ; LCCOMB_X12_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[31]~3 ; LCCOMB_X18_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[7]~0 ; LCCOMB_X15_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[15]~2 ; LCCOMB_X15_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[23]~1 ; LCCOMB_X12_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[31]~0 ; LCCOMB_X16_Y13_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[7]~3 ; LCCOMB_X15_Y13_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[0]~26 ; LCCOMB_X14_Y13_N30 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[1]~25 ; LCCOMB_X15_Y11_N22 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[2]~24 ; LCCOMB_X15_Y11_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[3]~23 ; LCCOMB_X15_Y10_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[4]~22 ; LCCOMB_X14_Y13_N20 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[5]~21 ; LCCOMB_X15_Y11_N0 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[6]~20 ; LCCOMB_X15_Y12_N26 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[8]~19 ; LCCOMB_X15_Y15_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[9]~18 ; LCCOMB_X15_Y15_N16 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|RTC_ADR[5]~0 ; LCCOMB_X8_Y12_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][0]~1 ; LCCOMB_X6_Y15_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][13]~14 ; LCCOMB_X4_Y14_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][2]~4 ; LCCOMB_X7_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][10]~10 ; LCCOMB_X7_Y14_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][11]~77 ; LCCOMB_X1_Y13_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][12]~11 ; LCCOMB_X8_Y13_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][13]~13 ; LCCOMB_X6_Y14_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][14]~15 ; LCCOMB_X7_Y14_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][15]~16 ; LCCOMB_X11_Y13_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][16]~17 ; LCCOMB_X4_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][17]~18 ; LCCOMB_X3_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][18]~19 ; LCCOMB_X2_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][19]~20 ; LCCOMB_X2_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][1]~2 ; LCCOMB_X7_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][20]~21 ; LCCOMB_X2_Y13_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][21]~22 ; LCCOMB_X3_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][22]~23 ; LCCOMB_X2_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][23]~24 ; LCCOMB_X3_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][24]~25 ; LCCOMB_X3_Y10_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][25]~26 ; LCCOMB_X2_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][26]~27 ; LCCOMB_X2_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][27]~28 ; LCCOMB_X4_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][28]~29 ; LCCOMB_X4_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][29]~30 ; LCCOMB_X3_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][30]~31 ; LCCOMB_X3_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][31]~32 ; LCCOMB_X5_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][32]~33 ; LCCOMB_X4_Y10_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][33]~34 ; LCCOMB_X8_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][34]~35 ; LCCOMB_X8_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][35]~36 ; LCCOMB_X4_Y10_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][36]~37 ; LCCOMB_X2_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][37]~38 ; LCCOMB_X2_Y10_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][38]~39 ; LCCOMB_X7_Y10_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][39]~40 ; LCCOMB_X4_Y10_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][3]~5 ; LCCOMB_X6_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][40]~41 ; LCCOMB_X6_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][41]~42 ; LCCOMB_X5_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][42]~43 ; LCCOMB_X6_Y9_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][43]~44 ; LCCOMB_X9_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][44]~45 ; LCCOMB_X10_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][45]~46 ; LCCOMB_X10_Y10_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][46]~47 ; LCCOMB_X10_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][47]~48 ; LCCOMB_X9_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][48]~49 ; LCCOMB_X9_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][49]~50 ; LCCOMB_X9_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][50]~51 ; LCCOMB_X9_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][51]~52 ; LCCOMB_X8_Y9_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][52]~53 ; LCCOMB_X7_Y9_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][53]~54 ; LCCOMB_X11_Y9_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][54]~55 ; LCCOMB_X10_Y9_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][55]~56 ; LCCOMB_X10_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][56]~57 ; LCCOMB_X10_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][57]~58 ; LCCOMB_X8_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][58]~59 ; LCCOMB_X8_Y12_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][59]~60 ; LCCOMB_X9_Y12_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][5]~9 ; LCCOMB_X6_Y14_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][60]~61 ; LCCOMB_X5_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][61]~62 ; LCCOMB_X5_Y12_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][62]~63 ; LCCOMB_X12_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][63]~64 ; LCCOMB_X11_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~503 ; LCCOMB_X6_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~504 ; LCCOMB_X5_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~505 ; LCCOMB_X4_Y14_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~506 ; LCCOMB_X7_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; CLK33M ; PIN_AB12 ; 12 ; 0 ; Global Clock ; GCLK15 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; 0 ; Global Clock ; GCLK7 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; 0 ; Global Clock ; GCLK5 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; 0 ; Global Clock ; GCLK11 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; 0 ; Global Clock ; GCLK6 ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; 0 ; Global Clock ; GCLK9 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; 0 ; Global Clock ; GCLK14 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK12 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK13 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; 0 ; Global Clock ; GCLK3 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; 0 ; Global Clock ; GCLK1 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; 0 ; Global Clock ; GCLK0 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; 0 ; Global Clock ; GCLK2 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; 0 ; Global Clock ; GCLK4 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; 0 ; Global Clock ; GCLK16 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; 0 ; Global Clock ; GCLK17 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; 0 ; Global Clock ; GCLK18 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; 0 ; Global Clock ; GCLK19 ; -- ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; 0 ; Global Clock ; GCLK10 ; -- ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ +; MAIN_CLK~input ; 2272 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 385 ; +; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 258 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 257 ; +; nFB_WR~input ; 235 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; 225 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 208 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 161 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 158 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; 156 ; +; FB_AD[17]~input ; 145 ; +; FB_AD[18]~input ; 145 ; +; FB_AD[20]~input ; 144 ; +; FB_AD[16]~input ; 143 ; +; FB_AD[19]~input ; 143 ; +; FB_AD[21]~input ; 143 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; 141 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; 141 ; +; FB_AD[22]~input ; 140 ; +; FB_AD[23]~input ; 137 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; 132 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; 132 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 129 ; +; Video:Fredi_Aschwanden|inst95 ; 128 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 120 ; +; inst25 ; 118 ; +; nFB_OE~input ; 101 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 97 ; +; nFB_CS2~input ; 95 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; 88 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 83 ; +; interrupt_handler:nobody|RTC_ADR[4] ; 80 ; +; interrupt_handler:nobody|RTC_ADR[5] ; 79 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ROLL_OVER ; 78 ; +; interrupt_handler:nobody|UHR_DS~5 ; 71 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 68 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; 66 ; +; interrupt_handler:nobody|UHR_DS~6 ; 66 ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; 65 ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 64 ; +; FB_AD[24]~input ; 63 ; +; interrupt_handler:nobody|RTC_ADR[3] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[2] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[1] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[0] ; 62 ; +; ~GND ; 61 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; 60 ; +; nFB_CS1~input ; 59 ; +; FB_AD[25]~input ; 59 ; +; FB_AD[26]~input ; 57 ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 8 ; 256 ; 32 ; yes ; no ; yes ; yes ; 8192 ; 1024 ; 8 ; 256 ; 32 ; 8192 ; 1 ; None ; M9K_X24_Y11_N0 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 32 ; 1024 ; 8 ; yes ; no ; yes ; yes ; 8192 ; 256 ; 32 ; 1024 ; 8 ; 8192 ; 1 ; None ; M9K_X24_Y21_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y13_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y20_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y19_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y17_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y14_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y16_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y18_N0 ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 128 ; 128 ; 128 ; yes ; no ; yes ; no ; 16384 ; 128 ; 128 ; 128 ; 128 ; 16384 ; 4 ; None ; M9K_X40_Y19_N0, M9K_X40_Y20_N0, M9K_X40_Y21_N0, M9K_X40_Y22_N0 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 128 ; 512 ; 128 ; yes ; no ; yes ; yes ; 65536 ; 512 ; 128 ; 512 ; 128 ; 65536 ; 8 ; None ; M9K_X40_Y16_N0, M9K_X40_Y15_N0, M9K_X58_Y16_N0, M9K_X58_Y17_N0, M9K_X40_Y17_N0, M9K_X40_Y14_N0, M9K_X40_Y13_N0, M9K_X40_Y18_N0 ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 144 ; 1 ; -- ; -- ; yes ; no ; -- ; -- ; 144 ; 144 ; 1 ; -- ; -- ; 144 ; 1 ; None ; M9K_X24_Y25_N0 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------------------------------+ +; Fitter DSP Block Usage Summary ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Statistic ; Number Used ; Available per Block ; Maximum Available ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Simple Multipliers (9-bit) ; 0 ; 2 ; 252 ; +; Simple Multipliers (18-bit) ; 3 ; 1 ; 126 ; +; Embedded Multiplier Blocks ; 3 ; -- ; 126 ; +; Embedded Multiplier 9-bit elements ; 6 ; 2 ; 252 ; +; Signed Embedded Multipliers ; 0 ; -- ; -- ; +; Unsigned Embedded Multipliers ; 3 ; -- ; -- ; +; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ; ++---------------------------------------+-------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DSP Block Details ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y14_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y14_N0 ; Unsigned ; ; no ; no ; no ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y10_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y10_N0 ; Unsigned ; ; no ; no ; no ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y12_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y12_N0 ; Unsigned ; ; no ; no ; no ; ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ + + ++--------------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+---------------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+---------------------------+ +; Block interconnects ; 16,358 / 116,715 ( 14 % ) ; +; C16 interconnects ; 749 / 3,886 ( 19 % ) ; +; C4 interconnects ; 10,626 / 73,752 ( 14 % ) ; +; Direct links ; 2,046 / 116,715 ( 2 % ) ; +; Global clocks ; 20 / 20 ( 100 % ) ; +; Local interconnects ; 4,734 / 39,600 ( 12 % ) ; +; R24 interconnects ; 882 / 3,777 ( 23 % ) ; +; R4 interconnects ; 11,442 / 99,858 ( 11 % ) ; ++----------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 12.60) ; Number of LABs (Total = 756) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 41 ; +; 2 ; 20 ; +; 3 ; 22 ; +; 4 ; 11 ; +; 5 ; 13 ; +; 6 ; 12 ; +; 7 ; 15 ; +; 8 ; 13 ; +; 9 ; 13 ; +; 10 ; 30 ; +; 11 ; 23 ; +; 12 ; 32 ; +; 13 ; 29 ; +; 14 ; 47 ; +; 15 ; 59 ; +; 16 ; 376 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 1.78) ; Number of LABs (Total = 756) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 239 ; +; 1 Clock ; 631 ; +; 1 Clock enable ; 289 ; +; 1 Sync. clear ; 20 ; +; 1 Sync. load ; 26 ; +; 2 Async. clears ; 12 ; +; 2 Clock enables ; 84 ; +; 2 Clocks ; 41 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 18.19) ; Number of LABs (Total = 756) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 19 ; +; 2 ; 26 ; +; 3 ; 12 ; +; 4 ; 16 ; +; 5 ; 8 ; +; 6 ; 14 ; +; 7 ; 5 ; +; 8 ; 11 ; +; 9 ; 8 ; +; 10 ; 14 ; +; 11 ; 9 ; +; 12 ; 20 ; +; 13 ; 17 ; +; 14 ; 15 ; +; 15 ; 30 ; +; 16 ; 49 ; +; 17 ; 41 ; +; 18 ; 43 ; +; 19 ; 30 ; +; 20 ; 42 ; +; 21 ; 35 ; +; 22 ; 49 ; +; 23 ; 45 ; +; 24 ; 31 ; +; 25 ; 31 ; +; 26 ; 27 ; +; 27 ; 28 ; +; 28 ; 20 ; +; 29 ; 17 ; +; 30 ; 18 ; +; 31 ; 10 ; +; 32 ; 16 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 8.27) ; Number of LABs (Total = 756) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 1 ; +; 1 ; 61 ; +; 2 ; 48 ; +; 3 ; 47 ; +; 4 ; 43 ; +; 5 ; 40 ; +; 6 ; 51 ; +; 7 ; 50 ; +; 8 ; 53 ; +; 9 ; 71 ; +; 10 ; 46 ; +; 11 ; 45 ; +; 12 ; 51 ; +; 13 ; 46 ; +; 14 ; 26 ; +; 15 ; 25 ; +; 16 ; 19 ; +; 17 ; 5 ; +; 18 ; 9 ; +; 19 ; 6 ; +; 20 ; 4 ; +; 21 ; 1 ; +; 22 ; 2 ; +; 23 ; 0 ; +; 24 ; 3 ; +; 25 ; 2 ; +; 26 ; 0 ; +; 27 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 18.51) ; Number of LABs (Total = 756) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 22 ; +; 3 ; 24 ; +; 4 ; 30 ; +; 5 ; 15 ; +; 6 ; 15 ; +; 7 ; 23 ; +; 8 ; 16 ; +; 9 ; 20 ; +; 10 ; 17 ; +; 11 ; 19 ; +; 12 ; 16 ; +; 13 ; 20 ; +; 14 ; 18 ; +; 15 ; 17 ; +; 16 ; 19 ; +; 17 ; 34 ; +; 18 ; 26 ; +; 19 ; 19 ; +; 20 ; 27 ; +; 21 ; 33 ; +; 22 ; 35 ; +; 23 ; 33 ; +; 24 ; 33 ; +; 25 ; 30 ; +; 26 ; 30 ; +; 27 ; 21 ; +; 28 ; 15 ; +; 29 ; 16 ; +; 30 ; 26 ; +; 31 ; 28 ; +; 32 ; 29 ; +; 33 ; 25 ; +; 34 ; 4 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 17 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 13 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 295 ; 121 ; 295 ; 0 ; 0 ; 295 ; 295 ; 0 ; 295 ; 295 ; 168 ; 3 ; 0 ; 0 ; 183 ; 168 ; 3 ; 183 ; 0 ; 0 ; 11 ; 3 ; 171 ; 0 ; 0 ; 0 ; 0 ; 295 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 174 ; 0 ; 295 ; 295 ; 0 ; 0 ; 295 ; 0 ; 0 ; 127 ; 292 ; 295 ; 295 ; 112 ; 127 ; 292 ; 112 ; 295 ; 295 ; 284 ; 292 ; 124 ; 295 ; 295 ; 295 ; 295 ; 0 ; 295 ; 295 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CLK24M576 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_STR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_BURST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_MSG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDCHG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CARD_DEDECT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_WP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDACK0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; WP_CF_CARD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_C_D ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_I_O ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLK25M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_RESET ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_A1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_ATN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_OLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_TLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RTS ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DTR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; AMKB_TX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_RES ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_RD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nCF_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nCF_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nROM3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nROM4 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRP_UDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRP_LDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSDSEL ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWR_GATE ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DSA_D ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVCAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVRAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPD_VGA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TIN0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRBLE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRBHE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDREQ1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED_FPGA_OK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSROE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VCKE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_TA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nBLANK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIXEL_CLK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSYNC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nMOT_ON ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSTEP_DIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSTEP ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLKUSB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LPDIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; BA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; BA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TOUT0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nMASTER ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_PAR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_SEL ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_BUSY ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_RST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CD_DATA3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CMD_D1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRSTO_MCF ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_SIZE1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_SIZE0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_ALE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MAIN_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDACK1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_OE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_RDY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLK33M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HD_DD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nINDEX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_BUSY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DCD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CTS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TRACK00 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DVI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; E0_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIC_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIC_AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_IN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRD_DATA ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; On ; +; Enable device-wide output enable (DEV_OE) ; On ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Error detection CRC ; Off ; +; Enable Open Drain on CRC Error pin ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; On ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As input tri-stated ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; I/O ; MAIN_CLK ; 245.886 ; +; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 444.109 ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 1092.93 ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:21:57 2010 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +Info: Selected device EP3C40F484C6 for design "firebee1" +Info: Core supply voltage is 1.2V +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Implemented PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 1, clock division of 66, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 67, clock division of 900, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 67, clock division of 90, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] port +Info: None of the inputs fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input + Info: Input "nRD_DATA" that is fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input +Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings + Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 + Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 + Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port +Info: None of the inputs fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input + Info: Input "MAIN_CLK" that is fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input +Info: Implemented PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 240 degrees (5051 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 180 degrees (3788 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 105 degrees (2210 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] port + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 270 degrees (11364 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] port +Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port +Critical Warning: The input clock frequency specification of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is different from the output clock frequency specification of the source PLLs that are driving it + Critical Warning: Input port inclk[0] of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" and its source clk[3] (the output port of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1") have different specified frequencies, 48.0 MHz and 48.0 MHz respectively +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP3C16F484C6 is compatible + Info: Device EP3C55F484C6 is compatible + Info: Device EP3C80F484C6 is compatible +Info: Fitter converted 7 user pins into dedicated programming pins + Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info: Pin ~ALTERA_DCLK~ is reserved at location K2 + Info: Pin ~ALTERA_DATA0~ is reserved at location K1 + Info: Pin ~ALTERA_DEV_OE~ is reserved at location N22 + Info: Pin ~ALTERA_DEV_CLRn~ is reserved at location N21 + Info: Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Warning: The parameters of the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 and the PLL altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged + Info: The values of the parameter "M" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "M" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 67 + Info: The value of the parameter "M" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 109 + Info: The values of the parameter "N" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "N" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 6 + Info: The value of the parameter "N" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 3 + Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 12000 + Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 10000 + Info: The values of the parameter "VCO POST SCALE" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 2 + Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1 + Info: The values of the parameter "Min VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Min VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 + Info: The value of the parameter "Min VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 + Info: The values of the parameter "Max VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Max VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 3333 + Info: The value of the parameter "Max VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1666 + Info: The values of the parameter "Center VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Center VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 + Info: The value of the parameter "Center VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 + Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Min Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 17174 + Info: The value of the parameter "Min Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 27940 + Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Max Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 30864 + Info: The value of the parameter "Max Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 59523 + Info: The values of the parameter "Compensate Clock" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Compensate Clock" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is clock0 + Info: The value of the parameter "Compensate Clock" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is clock1 +Warning: The input ports of the PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 and the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 are mismatched, preventing the PLLs to be merged + Warning: Input clock frequency of PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 differs from input clock frequency of PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 +Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings + Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 + Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 + Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port +Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port +Critical Warning: Input pin "CLK33M" feeds inclk port of PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" by global clock - I/O timing will be affected +Info: Timing-driven compilation is using the Classic Timing Analyzer +Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] (placed in counter C1 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14 +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] (placed in counter C2 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12 +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] (placed in counter C3 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G13 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] (placed in counter C0 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] (placed in counter C3 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] (placed in counter C2 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] (placed in counter C4 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] (placed in counter C1 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] (placed in counter C1 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] (placed in counter C2 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] (placed in counter C3 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] (placed in counter C4 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 +Info: Automatically promoted node altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] (placed in counter C0 of PLL_2) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8 +Info: Automatically promoted node CLK33M~input (placed in PIN AB12 (CLK12, DIFFCLK_7n)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0 + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3 + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M +Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC +Info: Automatically promoted node inst25 + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_WR~reg0 + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[10] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[14] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[15] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[12] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[13] + Info: Non-global destination nodes limited to 10 nodes +Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO + Info: Automatically promoted destinations to use location or clock signal Global Clock +Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC +Info: Automatically promoted node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|_~0 + Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 +Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 + Info: Automatically promoted destinations to use location or clock signal Global Clock +Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[31]~input" is constrained to location IOIBUF_X43_Y0_N1 to improve DDIO timing + Info: Node "VD[31]" is constrained to location PIN U12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "VD[30]~input" is constrained to location IOIBUF_X41_Y0_N29 to improve DDIO timing + Info: Node "VD[30]" is constrained to location PIN V12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[29]~input" is constrained to location IOIBUF_X38_Y0_N22 to improve DDIO timing + Info: Node "VD[29]" is constrained to location PIN AB13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[28]~input" is constrained to location IOIBUF_X43_Y0_N29 to improve DDIO timing + Info: Node "VD[28]" is constrained to location PIN W13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "VD[27]~input" is constrained to location IOIBUF_X48_Y0_N29 to improve DDIO timing + Info: Node "VD[27]" is constrained to location PIN V13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[26]~input" is constrained to location IOIBUF_X38_Y0_N8 to improve DDIO timing + Info: Node "VD[26]" is constrained to location PIN AB14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[25]~input" is constrained to location IOIBUF_X38_Y0_N15 to improve DDIO timing + Info: Node "VD[25]" is constrained to location PIN AA14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[24]~input" is constrained to location IOIBUF_X43_Y0_N8 to improve DDIO timing + Info: Node "VD[24]" is constrained to location PIN AB15 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "VD[23]~input" is constrained to location IOIBUF_X45_Y0_N15 to improve DDIO timing + Info: Node "VD[23]" is constrained to location PIN AB16 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "VD[22]~input" is constrained to location IOIBUF_X48_Y0_N22 to improve DDIO timing + Info: Node "VD[22]" is constrained to location PIN W14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[21]~input" is constrained to location IOIBUF_X50_Y0_N1 to improve DDIO timing + Info: Node "VD[21]" is constrained to location PIN V15 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[20]~input" is constrained to location IOIBUF_X50_Y0_N29 to improve DDIO timing + Info: Node "VD[20]" is constrained to location PIN U13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[19]~input" is constrained to location IOIBUF_X50_Y0_N22 to improve DDIO timing + Info: Node "VD[19]" is constrained to location PIN V14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[18]~input" is constrained to location IOIBUF_X38_Y0_N29 to improve DDIO timing + Info: Node "VD[18]" is constrained to location PIN AA13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[17]~input" is constrained to location IOIBUF_X43_Y0_N22 to improve DDIO timing + Info: Node "VD[17]" is constrained to location PIN Y13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "VD[16]~input" is constrained to location IOIBUF_X45_Y0_N8 to improve DDIO timing + Info: Node "VD[16]" is constrained to location PIN T12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "VD[15]~input" is constrained to location IOIBUF_X67_Y15_N8 to improve DDIO timing + Info: Node "VD[15]" is constrained to location PIN N20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "VD[14]~input" is constrained to location IOIBUF_X67_Y13_N8 to improve DDIO timing + Info: Node "VD[14]" is constrained to location PIN R22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[13]~input" is constrained to location IOIBUF_X67_Y14_N22 to improve DDIO timing + Info: Node "VD[13]" is constrained to location PIN P20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "VD[12]~input" is constrained to location IOIBUF_X67_Y17_N22 to improve DDIO timing + Info: Node "VD[12]" is constrained to location PIN N17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "VD[11]~input" is constrained to location IOIBUF_X67_Y13_N1 to improve DDIO timing + Info: Node "VD[11]" is constrained to location PIN R21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[10]~input" is constrained to location IOIBUF_X67_Y10_N15 to improve DDIO timing + Info: Node "VD[10]" is constrained to location PIN P17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "VD[9]~input" is constrained to location IOIBUF_X67_Y12_N22 to improve DDIO timing + Info: Node "VD[9]" is constrained to location PIN R18 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[8]~input" is constrained to location IOIBUF_X67_Y10_N8 to improve DDIO timing + Info: Node "VD[8]" is constrained to location PIN V22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "VD[7]~input" is constrained to location IOIBUF_X67_Y11_N1 to improve DDIO timing + Info: Node "VD[7]" is constrained to location PIN U21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "VD[6]~input" is constrained to location IOIBUF_X67_Y12_N15 to improve DDIO timing + Info: Node "VD[6]" is constrained to location PIN R19 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[5]~input" is constrained to location IOIBUF_X67_Y10_N22 to improve DDIO timing + Info: Node "VD[5]" is constrained to location PIN R17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[4]~input" is constrained to location IOIBUF_X67_Y14_N1 to improve DDIO timing + Info: Node "VD[4]" is constrained to location PIN P21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "VD[3]~input" is constrained to location IOIBUF_X67_Y11_N22 to improve DDIO timing + Info: Node "VD[3]" is constrained to location PIN R20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[2]~input" is constrained to location IOIBUF_X67_Y14_N8 to improve DDIO timing + Info: Node "VD[2]" is constrained to location PIN P22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "VD[1]~input" is constrained to location IOIBUF_X67_Y18_N1 to improve DDIO timing + Info: Node "VD[1]" is constrained to location PIN M21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "VD[0]~input" is constrained to location IOIBUF_X67_Y18_N8 to improve DDIO timing + Info: Node "VD[0]" is constrained to location PIN M22 to improve DDIO timing +Info: Starting register packing +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] to I/O pin + Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] and I/O node MAIN_CLK -- I/O node is a dedicated I/O pin +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks +Info: Finished register packing + Extra Info: Packed 33 registers into blocks of type I/O Input Buffer + Extra Info: Packed 25 registers into blocks of type I/O Output Buffer + Extra Info: Created 9 register duplicates +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input + Info: Input port INCLK[0] of node "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" is driven by CLK33M~inputclkctrl which is OUTCLK output port of Clock control block type node CLK33M~inputclkctrl +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" output port clk[2] feeds output pin "CLK24M576~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[2] feeds output pin "CLK25M~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[3] feeds output pin "CLKUSB~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[3]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[2]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "nDDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "DDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input + Info: Input port INCLK[0] of node "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is driven by altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl +Info: Starting physical synthesis optimizations for speed +Info: Starting physical synthesis algorithm combinational resynthesis using boolean division +Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2208 ps +Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:23 +Info: Fitter preparation operations ending: elapsed time is 00:00:47 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:18 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:01:10 +Info: Starting physical synthesis optimizations for speed +Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:05 +Info: Estimated most critical path is register to pin delay of 5.130 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12_N0; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[9]' + Info: 2: + IC(0.161 ns) + CELL(0.369 ns) = 0.530 ns; Loc. = LAB_X16_Y12_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15' + Info: 3: + IC(0.528 ns) + CELL(0.243 ns) = 1.301 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359' + Info: 4: + IC(0.172 ns) + CELL(0.130 ns) = 1.603 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~360' + Info: 5: + IC(1.521 ns) + CELL(2.006 ns) = 5.130 ns; Loc. = IOOBUF_X34_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[29]~output' + Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 5.130 ns; Loc. = PIN_W10; Fanout = 0; PIN Node = 'FB_AD[29]' + Info: Total cell delay = 2.748 ns ( 53.57 % ) + Info: Total interconnect delay = 2.382 ns ( 46.43 % ) +Info: Fitter routing operations beginning +Info: 2 (of 32134) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Fitter report for a summary of the relevant clock transfers. Also, check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks. +Info: Average interconnect usage is 13% of the available device resources + Info: Peak interconnect usage is 51% of the available device resources in the region that extends from location X22_Y11 to location X33_Y21 +Info: Fitter routing operations ending: elapsed time is 00:01:18 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Info: Auto delay chain can't change the delay chain setting on I/O pin nRD_DATA since it's a PLL compensated pin +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register +Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning: Total number of single-ended output or bi-directional pins in bank 4 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. + Info: There are 32 output pin(s) with I/O standard 2.5 V and current strength 12mA + Info: Location AA13 (pad PAD_208): Pin VD[18] of type bi-directional uses 2.5 V I/O standard + Info: Location AB13 (pad PAD_209): Pin VD[29] of type bi-directional uses 2.5 V I/O standard + Info: Location AA14 (pad PAD_210): Pin VD[25] of type bi-directional uses 2.5 V I/O standard + Info: Location AB14 (pad PAD_211): Pin VD[26] of type bi-directional uses 2.5 V I/O standard + Info: Location V12 (pad PAD_213): Pin VD[30] of type bi-directional uses 2.5 V I/O standard + Info: Location W13 (pad PAD_218): Pin VD[28] of type bi-directional uses 2.5 V I/O standard + Info: Location Y13 (pad PAD_219): Pin VD[17] of type bi-directional uses 2.5 V I/O standard + Info: Location AA15 (pad PAD_220): Pin VDQS[0] of type bi-directional uses 2.5 V I/O standard + Info: Location AB15 (pad PAD_221): Pin VD[24] of type bi-directional uses 2.5 V I/O standard + Info: Location U12 (pad PAD_222): Pin VD[31] of type bi-directional uses 2.5 V I/O standard + Info: Location AA16 (pad PAD_224): Pin VDM[0] of type output uses 2.5 V I/O standard + Info: Location AB16 (pad PAD_225): Pin VD[23] of type bi-directional uses 2.5 V I/O standard + Info: Location T12 (pad PAD_226): Pin VD[16] of type bi-directional uses 2.5 V I/O standard + Info: Location V13 (pad PAD_228): Pin VD[27] of type bi-directional uses 2.5 V I/O standard + Info: Location W14 (pad PAD_229): Pin VD[22] of type bi-directional uses 2.5 V I/O standard + Info: Location U13 (pad PAD_233): Pin VD[20] of type bi-directional uses 2.5 V I/O standard + Info: Location V14 (pad PAD_234): Pin VD[19] of type bi-directional uses 2.5 V I/O standard + Info: Location U15 (pad PAD_236): Pin VCKE of type output uses 2.5 V I/O standard + Info: Location V15 (pad PAD_237): Pin VD[21] of type bi-directional uses 2.5 V I/O standard + Info: Location W15 (pad PAD_239): Pin VDQS[1] of type bi-directional uses 2.5 V I/O standard + Info: Location AB18 (pad PAD_242): Pin nVCAS of type output uses 2.5 V I/O standard + Info: Location AA17 (pad PAD_243): Pin nDDR_CLK of type output uses 2.5 V I/O standard + Info: Location AB17 (pad PAD_244): Pin DDR_CLK of type output uses 2.5 V I/O standard + Info: Location AA18 (pad PAD_245): Pin VA[12] of type output uses 2.5 V I/O standard + Info: Location AA19 (pad PAD_252): Pin BA[1] of type output uses 2.5 V I/O standard + Info: Location AB19 (pad PAD_253): Pin VA[9] of type output uses 2.5 V I/O standard + Info: Location W17 (pad PAD_257): Pin nVRAS of type output uses 2.5 V I/O standard + Info: Location Y17 (pad PAD_258): Pin nVWE of type output uses 2.5 V I/O standard + Info: Location AA20 (pad PAD_259): Pin VA[7] of type output uses 2.5 V I/O standard + Info: Location AB20 (pad PAD_260): Pin VA[8] of type output uses 2.5 V I/O standard + Info: Location V16 (pad PAD_261): Pin VDM[1] of type output uses 2.5 V I/O standard + Info: Location T16 (pad PAD_266): Pin VDQS[3] of type bi-directional uses 2.5 V I/O standard +Warning: Total number of single-ended output or bi-directional pins in bank 5 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. + Info: There are 30 output pin(s) with I/O standard 2.5 V and current strength 12mA + Info: Location AA22 (pad PAD_273): Pin VA[4] of type output uses 2.5 V I/O standard + Info: Location AA21 (pad PAD_274): Pin VA[6] of type output uses 2.5 V I/O standard + Info: Location T17 (pad PAD_277): Pin VDM[3] of type output uses 2.5 V I/O standard + Info: Location T18 (pad PAD_278): Pin nVCS of type output uses 2.5 V I/O standard + Info: Location W20 (pad PAD_280): Pin VA[0] of type output uses 2.5 V I/O standard + Info: Location W19 (pad PAD_285): Pin BA[0] of type output uses 2.5 V I/O standard + Info: Location Y22 (pad PAD_288): Pin VA[3] of type output uses 2.5 V I/O standard + Info: Location Y21 (pad PAD_289): Pin VA[5] of type output uses 2.5 V I/O standard + Info: Location U20 (pad PAD_290): Pin VDM[2] of type output uses 2.5 V I/O standard + Info: Location U19 (pad PAD_291): Pin VA[11] of type output uses 2.5 V I/O standard + Info: Location W22 (pad PAD_292): Pin VA[1] of type output uses 2.5 V I/O standard + Info: Location W21 (pad PAD_293): Pin VA[2] of type output uses 2.5 V I/O standard + Info: Location R17 (pad PAD_301): Pin VD[5] of type bi-directional uses 2.5 V I/O standard + Info: Location P17 (pad PAD_302): Pin VD[10] of type bi-directional uses 2.5 V I/O standard + Info: Location V22 (pad PAD_303): Pin VD[8] of type bi-directional uses 2.5 V I/O standard + Info: Location V21 (pad PAD_304): Pin VA[10] of type output uses 2.5 V I/O standard + Info: Location R20 (pad PAD_305): Pin VD[3] of type bi-directional uses 2.5 V I/O standard + Info: Location U22 (pad PAD_307): Pin VDQS[2] of type bi-directional uses 2.5 V I/O standard + Info: Location U21 (pad PAD_308): Pin VD[7] of type bi-directional uses 2.5 V I/O standard + Info: Location R18 (pad PAD_309): Pin VD[9] of type bi-directional uses 2.5 V I/O standard + Info: Location R19 (pad PAD_310): Pin VD[6] of type bi-directional uses 2.5 V I/O standard + Info: Location R22 (pad PAD_315): Pin VD[14] of type bi-directional uses 2.5 V I/O standard + Info: Location R21 (pad PAD_316): Pin VD[11] of type bi-directional uses 2.5 V I/O standard + Info: Location P20 (pad PAD_317): Pin VD[13] of type bi-directional uses 2.5 V I/O standard + Info: Location P22 (pad PAD_319): Pin VD[2] of type bi-directional uses 2.5 V I/O standard + Info: Location P21 (pad PAD_320): Pin VD[4] of type bi-directional uses 2.5 V I/O standard + Info: Location N20 (pad PAD_323): Pin VD[15] of type bi-directional uses 2.5 V I/O standard + Info: Location N17 (pad PAD_329): Pin VD[12] of type bi-directional uses 2.5 V I/O standard + Info: Location M22 (pad PAD_333): Pin VD[0] of type bi-directional uses 2.5 V I/O standard + Info: Location M21 (pad PAD_334): Pin VD[1] of type bi-directional uses 2.5 V I/O standard +Warning: 145 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems). + Info: Pin nFB_BURST uses I/O standard 3.3-V LVTTL at T3 + Info: Pin nACSI_DRQ uses I/O standard 3.3-V LVTTL at K7 + Info: Pin nACSI_INT uses I/O standard 3.3-V LVTTL at J4 + Info: Pin nSCSI_DRQ uses I/O standard 3.3-V LVTTL at U1 + Info: Pin nSCSI_MSG uses I/O standard 3.3-V LVTTL at H2 + Info: Pin nDCHG uses I/O standard 3.3-V LVTTL at C17 + Info: Pin SD_DATA0 uses I/O standard 3.3-V LVTTL at B16 + Info: Pin SD_DATA1 uses I/O standard 3.3-V LVTTL at A16 + Info: Pin SD_DATA2 uses I/O standard 3.3-V LVTTL at B17 + Info: Pin SD_CARD_DEDECT uses I/O standard 3.3-V LVTTL at M20 + Info: Pin SD_WP uses I/O standard 3.3-V LVTTL at M19 + Info: Pin nDACK0 uses I/O standard 3.3-V LVTTL at B12 + Info: Pin WP_CF_CARD uses I/O standard 3.3-V LVTTL at T1 + Info: Pin nSCSI_C_D uses I/O standard 3.3-V LVTTL at H1 + Info: Pin nSCSI_I_O uses I/O standard 3.3-V LVTTL at J3 + Info: Pin nFB_CS3 uses I/O standard 3.3-V LVTTL at V6 + Info: Pin TOUT0 uses I/O standard 3.3-V LVTTL at T22 + Info: Pin nMASTER uses I/O standard 3.3-V LVTTL at T21 + Info: Pin FB_AD[31] uses I/O standard 3.3-V LVTTL at AA10 + Info: Pin FB_AD[30] uses I/O standard 3.3-V LVTTL at Y10 + Info: Pin FB_AD[29] uses I/O standard 3.3-V LVTTL at W10 + Info: Pin FB_AD[28] uses I/O standard 3.3-V LVTTL at V11 + Info: Pin FB_AD[27] uses I/O standard 3.3-V LVTTL at U11 + Info: Pin FB_AD[26] uses I/O standard 3.3-V LVTTL at AB9 + Info: Pin FB_AD[25] uses I/O standard 3.3-V LVTTL at AA9 + Info: Pin FB_AD[24] uses I/O standard 3.3-V LVTTL at T11 + Info: Pin FB_AD[23] uses I/O standard 3.3-V LVTTL at AB8 + Info: Pin FB_AD[22] uses I/O standard 3.3-V LVTTL at AA8 + Info: Pin FB_AD[21] uses I/O standard 3.3-V LVTTL at U10 + Info: Pin FB_AD[20] uses I/O standard 3.3-V LVTTL at T10 + Info: Pin FB_AD[19] uses I/O standard 3.3-V LVTTL at V10 + Info: Pin FB_AD[18] uses I/O standard 3.3-V LVTTL at V9 + Info: Pin FB_AD[17] uses I/O standard 3.3-V LVTTL at Y8 + Info: Pin FB_AD[16] uses I/O standard 3.3-V LVTTL at AB7 + Info: Pin FB_AD[15] uses I/O standard 3.3-V LVTTL at AA7 + Info: Pin FB_AD[14] uses I/O standard 3.3-V LVTTL at W8 + Info: Pin FB_AD[13] uses I/O standard 3.3-V LVTTL at V8 + Info: Pin FB_AD[12] uses I/O standard 3.3-V LVTTL at U9 + Info: Pin FB_AD[11] uses I/O standard 3.3-V LVTTL at Y7 + Info: Pin FB_AD[10] uses I/O standard 3.3-V LVTTL at W7 + Info: Pin FB_AD[9] uses I/O standard 3.3-V LVTTL at AB5 + Info: Pin FB_AD[8] uses I/O standard 3.3-V LVTTL at AA5 + Info: Pin FB_AD[7] uses I/O standard 3.3-V LVTTL at AB4 + Info: Pin FB_AD[6] uses I/O standard 3.3-V LVTTL at AA4 + Info: Pin FB_AD[5] uses I/O standard 3.3-V LVTTL at V7 + Info: Pin FB_AD[4] uses I/O standard 3.3-V LVTTL at W6 + Info: Pin FB_AD[3] uses I/O standard 3.3-V LVTTL at AB3 + Info: Pin FB_AD[2] uses I/O standard 3.3-V LVTTL at AA3 + Info: Pin FB_AD[1] uses I/O standard 3.3-V LVTTL at Y6 + Info: Pin FB_AD[0] uses I/O standard 3.3-V LVTTL at Y3 + Info: Pin IO[17] uses I/O standard 3.3-V LVTTL at B13 + Info: Pin IO[16] uses I/O standard 3.3-V LVTTL at A13 + Info: Pin IO[15] uses I/O standard 3.3-V LVTTL at B14 + Info: Pin IO[14] uses I/O standard 3.3-V LVTTL at A14 + Info: Pin IO[13] uses I/O standard 3.3-V LVTTL at E13 + Info: Pin IO[12] uses I/O standard 3.3-V LVTTL at D13 + Info: Pin IO[11] uses I/O standard 3.3-V LVTTL at C13 + Info: Pin IO[10] uses I/O standard 3.3-V LVTTL at B15 + Info: Pin IO[9] uses I/O standard 3.3-V LVTTL at A15 + Info: Pin IO[8] uses I/O standard 3.3-V LVTTL at G10 + Info: Pin IO[7] uses I/O standard 3.3-V LVTTL at C7 + Info: Pin IO[6] uses I/O standard 3.3-V LVTTL at C8 + Info: Pin IO[5] uses I/O standard 3.3-V LVTTL at E9 + Info: Pin IO[4] uses I/O standard 3.3-V LVTTL at B6 + Info: Pin IO[3] uses I/O standard 3.3-V LVTTL at A6 + Info: Pin IO[2] uses I/O standard 3.3-V LVTTL at B7 + Info: Pin IO[1] uses I/O standard 3.3-V LVTTL at A7 + Info: Pin IO[0] uses I/O standard 3.3-V LVTTL at A8 + Info: Pin SRD[15] uses I/O standard 3.3-V LVTTL at H10 + Info: Pin SRD[14] uses I/O standard 3.3-V LVTTL at G9 + Info: Pin SRD[13] uses I/O standard 3.3-V LVTTL at F10 + Info: Pin SRD[12] uses I/O standard 3.3-V LVTTL at D10 + Info: Pin SRD[11] uses I/O standard 3.3-V LVTTL at B10 + Info: Pin SRD[10] uses I/O standard 3.3-V LVTTL at A9 + Info: Pin SRD[9] uses I/O standard 3.3-V LVTTL at A10 + Info: Pin SRD[8] uses I/O standard 3.3-V LVTTL at B9 + Info: Pin SRD[7] uses I/O standard 3.3-V LVTTL at H11 + Info: Pin SRD[6] uses I/O standard 3.3-V LVTTL at E10 + Info: Pin SRD[5] uses I/O standard 3.3-V LVTTL at F9 + Info: Pin SRD[4] uses I/O standard 3.3-V LVTTL at C10 + Info: Pin SRD[3] uses I/O standard 3.3-V LVTTL at G11 + Info: Pin SRD[2] uses I/O standard 3.3-V LVTTL at C6 + Info: Pin SRD[1] uses I/O standard 3.3-V LVTTL at A5 + Info: Pin SRD[0] uses I/O standard 3.3-V LVTTL at B5 + Info: Pin SCSI_PAR uses I/O standard 3.3-V LVTTL at M7 + Info: Pin nSCSI_SEL uses I/O standard 3.3-V LVTTL at M8 + Info: Pin nSCSI_BUSY uses I/O standard 3.3-V LVTTL at N8 + Info: Pin nSCSI_RST uses I/O standard 3.3-V LVTTL at N6 + Info: Pin SD_CD_DATA3 uses I/O standard 3.3-V LVTTL at F13 + Info: Pin SD_CMD_D1 uses I/O standard 3.3-V LVTTL at E14 + Info: Pin ACSI_D[7] uses I/O standard 3.3-V LVTTL at H6 + Info: Pin ACSI_D[6] uses I/O standard 3.3-V LVTTL at H7 + Info: Pin ACSI_D[5] uses I/O standard 3.3-V LVTTL at D2 + Info: Pin ACSI_D[4] uses I/O standard 3.3-V LVTTL at C1 + Info: Pin ACSI_D[3] uses I/O standard 3.3-V LVTTL at C2 + Info: Pin ACSI_D[2] uses I/O standard 3.3-V LVTTL at E3 + Info: Pin ACSI_D[1] uses I/O standard 3.3-V LVTTL at G5 + Info: Pin ACSI_D[0] uses I/O standard 3.3-V LVTTL at B1 + Info: Pin LP_D[7] uses I/O standard 3.3-V LVTTL at G8 + Info: Pin LP_D[6] uses I/O standard 3.3-V LVTTL at A3 + Info: Pin LP_D[5] uses I/O standard 3.3-V LVTTL at B3 + Info: Pin LP_D[4] uses I/O standard 3.3-V LVTTL at D6 + Info: Pin LP_D[3] uses I/O standard 3.3-V LVTTL at E7 + Info: Pin LP_D[2] uses I/O standard 3.3-V LVTTL at C3 + Info: Pin LP_D[1] uses I/O standard 3.3-V LVTTL at C4 + Info: Pin LP_D[0] uses I/O standard 3.3-V LVTTL at F7 + Info: Pin SCSI_D[7] uses I/O standard 3.3-V LVTTL at K8 + Info: Pin SCSI_D[6] uses I/O standard 3.3-V LVTTL at L8 + Info: Pin SCSI_D[5] uses I/O standard 3.3-V LVTTL at G3 + Info: Pin SCSI_D[4] uses I/O standard 3.3-V LVTTL at G4 + Info: Pin SCSI_D[3] uses I/O standard 3.3-V LVTTL at F1 + Info: Pin SCSI_D[2] uses I/O standard 3.3-V LVTTL at F2 + Info: Pin SCSI_D[1] uses I/O standard 3.3-V LVTTL at E1 + Info: Pin SCSI_D[0] uses I/O standard 3.3-V LVTTL at J6 + Info: Pin nRSTO_MCF uses I/O standard 3.3-V LVTTL at B11 + Info: Pin nFB_WR uses I/O standard 3.3-V LVTTL at T5 + Info: Pin nFB_CS1 uses I/O standard 3.3-V LVTTL at T8 + Info: Pin FB_SIZE1 uses I/O standard 3.3-V LVTTL at Y4 + Info: Pin FB_SIZE0 uses I/O standard 3.3-V LVTTL at U8 + Info: Pin FB_ALE uses I/O standard 3.3-V LVTTL at R7 + Info: Pin nFB_CS2 uses I/O standard 3.3-V LVTTL at T9 + Info: Pin MAIN_CLK uses I/O standard 3.3-V LVTTL at G2 + Info: Pin nDACK1 uses I/O standard 3.3-V LVTTL at A12 + Info: Pin nFB_OE uses I/O standard 3.3-V LVTTL at R6 + Info: Pin IDE_RDY uses I/O standard 3.3-V LVTTL at Y1 + Info: Pin CLK33M uses I/O standard 3.3-V LVTTL at AB12 + Info: Pin HD_DD uses I/O standard 3.3-V LVTTL at F16 + Info: Pin nINDEX uses I/O standard 3.3-V LVTTL at E16 + Info: Pin RxD uses I/O standard 3.3-V LVTTL at H15 + Info: Pin nWP uses I/O standard 3.3-V LVTTL at D19 + Info: Pin LP_BUSY uses I/O standard 3.3-V LVTTL at G7 + Info: Pin DCD uses I/O standard 3.3-V LVTTL at A19 + Info: Pin CTS uses I/O standard 3.3-V LVTTL at H14 + Info: Pin TRACK00 uses I/O standard 3.3-V LVTTL at C19 + Info: Pin RI uses I/O standard 3.3-V LVTTL at B19 + Info: Pin nPCI_INTD uses I/O standard 3.3-V LVTTL at P6 + Info: Pin nPCI_INTC uses I/O standard 3.3-V LVTTL at V3 + Info: Pin nPCI_INTB uses I/O standard 3.3-V LVTTL at V4 + Info: Pin nPCI_INTA uses I/O standard 3.3-V LVTTL at AA1 + Info: Pin DVI_INT uses I/O standard 3.3-V LVTTL at A11 + Info: Pin PIC_INT uses I/O standard 3.3-V LVTTL at AA2 + Info: Pin PIC_AMKB_RX uses I/O standard 3.3-V LVTTL at L7 + Info: Pin MIDI_IN uses I/O standard 3.3-V LVTTL at E12 + Info: Pin nRD_DATA uses I/O standard 3.3-V LVTTL at A20 + Info: Pin AMKB_RX uses I/O standard 3.3-V LVTTL at Y2 +Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results + Info: Pin IO[17] has a permanently enabled output enable + Info: Pin IO[16] has a permanently enabled output enable + Info: Pin IO[15] has a permanently enabled output enable + Info: Pin IO[14] has a permanently enabled output enable + Info: Pin IO[13] has a permanently enabled output enable + Info: Pin IO[12] has a permanently enabled output enable + Info: Pin IO[11] has a permanently enabled output enable + Info: Pin IO[10] has a permanently enabled output enable + Info: Pin IO[9] has a permanently enabled output enable + Info: Pin IO[8] has a permanently enabled output enable + Info: Pin IO[7] has a permanently enabled output enable + Info: Pin IO[6] has a permanently enabled output enable + Info: Pin IO[5] has a permanently enabled output enable + Info: Pin IO[4] has a permanently enabled output enable + Info: Pin IO[3] has a permanently enabled output enable + Info: Pin IO[2] has a permanently enabled output enable + Info: Pin IO[1] has a permanently enabled output enable + Info: Pin IO[0] has a permanently enabled output enable + Info: Pin SCSI_PAR has a permanently disabled output enable + Info: Pin nSCSI_SEL has a permanently enabled output enable + Info: Pin nSCSI_BUSY has a permanently enabled output enable + Info: Pin nSCSI_RST has a permanently disabled output enable + Info: Pin SD_CD_DATA3 has a permanently disabled output enable + Info: Pin SD_CMD_D1 has a permanently disabled output enable + Info: Pin ACSI_D[7] has a permanently disabled output enable + Info: Pin ACSI_D[6] has a permanently disabled output enable + Info: Pin ACSI_D[5] has a permanently disabled output enable + Info: Pin ACSI_D[4] has a permanently disabled output enable + Info: Pin ACSI_D[3] has a permanently disabled output enable + Info: Pin ACSI_D[2] has a permanently disabled output enable + Info: Pin ACSI_D[1] has a permanently disabled output enable + Info: Pin ACSI_D[0] has a permanently disabled output enable + Info: Pin SCSI_D[7] has a permanently disabled output enable + Info: Pin SCSI_D[6] has a permanently disabled output enable + Info: Pin SCSI_D[5] has a permanently disabled output enable + Info: Pin SCSI_D[4] has a permanently disabled output enable + Info: Pin SCSI_D[3] has a permanently disabled output enable + Info: Pin SCSI_D[2] has a permanently disabled output enable + Info: Pin SCSI_D[1] has a permanently disabled output enable + Info: Pin SCSI_D[0] has a permanently disabled output enable +Info: Quartus II Fitter was successful. 0 errors, 34 warnings + Info: Peak virtual memory: 334 megabytes + Info: Processing ended: Wed Dec 15 02:25:07 2010 + Info: Elapsed time: 00:03:10 + Info: Total CPU time (on all processors): 00:03:11 + + diff --git a/FPGA_quartus/firebee1.fit.summary b/FPGA_quartus/firebee1.fit.summary new file mode 100644 index 0000000..f177099 --- /dev/null +++ b/FPGA_quartus/firebee1.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Wed Dec 15 02:25:02 2010 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : firebee1 +Top-level Entity Name : firebee1 +Family : Cyclone III +Device : EP3C40F484C6 +Timing Models : Final +Total logic elements : 9,526 / 39,600 ( 24 % ) + Total combinational functions : 8,061 / 39,600 ( 20 % ) + Dedicated logic registers : 4,563 / 39,600 ( 12 % ) +Total registers : 4749 +Total pins : 295 / 332 ( 89 % ) +Total virtual pins : 0 +Total memory bits : 109,344 / 1,161,216 ( 9 % ) +Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % ) +Total PLLs : 4 / 4 ( 100 % ) diff --git a/FPGA_quartus/firebee1.flow.rpt b/FPGA_quartus/firebee1.flow.rpt new file mode 100644 index 0000000..297d7a0 --- /dev/null +++ b/FPGA_quartus/firebee1.flow.rpt @@ -0,0 +1,380 @@ +Flow report for firebee1 +Wed Dec 15 02:25:22 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Wed Dec 15 02:25:21 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; +; Timing Models ; Final ; +; Met timing requirements ; No ; +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; +; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; Total registers ; 4749 ; +; Total pins ; 295 / 332 ( 89 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; Total PLLs ; 4 / 4 ( 100 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/15/2010 02:20:37 ; +; Main task ; Compilation ; +; Revision Name ; firebee1 ; ++-------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 150661768621.129237603704664 ; -- ; -- ; -- ; +; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ; +; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ; +; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ; +; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ; +; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ; +; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ; +; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; +; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; +; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:01:16 ; 1.0 ; 347 MB ; 00:01:17 ; +; Fitter ; 00:03:05 ; 1.0 ; 334 MB ; 00:03:07 ; +; Assembler ; 00:00:05 ; 1.0 ; 291 MB ; 00:00:04 ; +; Classic Timing Analyzer ; 00:00:07 ; 1.0 ; 227 MB ; 00:00:09 ; +; Total ; 00:04:33 ; -- ; -- ; 00:04:37 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Fitter ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Assembler ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Classic Timing Analyzer ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 +quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only + + + diff --git a/FPGA_quartus/firebee1.map.rpt b/FPGA_quartus/firebee1.map.rpt new file mode 100644 index 0000000..11a1ac1 --- /dev/null +++ b/FPGA_quartus/firebee1.map.rpt @@ -0,0 +1,8590 @@ +Analysis & Synthesis report for firebee1 +Wed Dec 15 02:21:56 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis DSP Block Usage Summary + 10. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR + 11. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM + 12. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE + 13. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE + 14. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE + 15. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE + 16. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE + 17. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE + 18. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE + 19. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE + 20. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE + 21. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE + 22. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE + 23. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP + 24. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE + 25. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE + 26. Registers Protected by Synthesis + 27. User-Specified and Inferred Latches + 28. Registers Removed During Synthesis + 29. Removed Registers Triggering Further Register Optimizations + 30. General Register Statistics + 31. Inverted Register Statistics + 32. Multiplexer Restructuring Statistics (Restructuring Performed) + 33. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated + 34. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p + 35. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p + 36. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram + 37. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp + 38. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 + 39. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp + 40. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp + 41. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp + 42. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 + 43. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated + 44. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p + 45. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p + 46. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram + 47. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp + 48. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp + 49. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp + 50. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 + 51. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp + 52. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 + 53. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component + 54. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated + 55. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p + 56. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p + 57. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp + 58. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram + 59. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp + 60. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 + 61. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr + 62. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp + 63. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp + 64. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp + 65. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 + 66. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component + 67. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated + 68. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 69. Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram + 70. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 71. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 72. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 73. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 74. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 75. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 76. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 77. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 78. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component + 79. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated + 80. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component + 81. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated + 82. Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated + 83. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component + 84. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated + 85. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 + 86. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 + 87. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 + 88. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 + 89. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 + 90. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 + 91. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 + 92. Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component + 93. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component + 94. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 95. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component + 96. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 97. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component + 98. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 99. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component +100. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated +101. Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component +102. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component +103. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component +104. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL +105. Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component +106. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component +107. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component +108. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component +109. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component +110. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component +111. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component +112. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component +113. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component +114. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component +115. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component +116. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component +117. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component +118. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component +119. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component +120. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component +121. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component +122. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component +123. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component +124. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component +125. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component +126. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component +127. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component +128. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component +129. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component +130. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component +131. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component +132. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component +133. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component +134. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component +135. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component +136. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component +137. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component +138. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component +139. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component +140. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component +141. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component +142. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component +143. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component +144. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component +145. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component +146. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component +147. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component +148. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component +149. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component +150. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component +151. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component +152. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component +153. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component +154. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component +155. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component +156. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component +157. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component +158. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component +159. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component +160. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component +161. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component +162. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component +163. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component +164. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component +165. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component +166. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component +167. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component +168. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component +169. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component +170. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component +171. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component +172. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component +173. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component +174. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component +175. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component +176. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component +177. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component +178. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component +179. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component +180. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component +181. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component +182. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component +183. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component +184. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component +185. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component +186. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component +187. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component +188. Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component +189. Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component +190. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component +191. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 +192. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 +193. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 +194. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 +195. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 +196. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 +197. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 +198. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 +199. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 +200. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 +201. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 +202. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 +203. Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component +204. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component +205. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component +206. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component +207. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component +208. Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component +209. Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component +210. Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component +211. Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component +212. Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component +213. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 +214. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 +215. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 +216. altpll Parameter Settings by Entity Instance +217. lpm_shiftreg Parameter Settings by Entity Instance +218. dcfifo Parameter Settings by Entity Instance +219. scfifo Parameter Settings by Entity Instance +220. altsyncram Parameter Settings by Entity Instance +221. lpm_mult Parameter Settings by Entity Instance +222. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" +223. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" +224. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" +225. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" +226. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" +227. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" +228. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" +229. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Dec 15 02:21:55 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Total logic elements ; 10,706 ; +; Total combinational functions ; 8,060 ; +; Dedicated logic registers ; 4,612 ; +; Total registers ; 4740 ; +; Total pins ; 295 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Total PLLs ; 4 ; ++------------------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C40F484C6 ; ; +; Top-level entity name ; firebee1 ; firebee1 ; +; Family name ; Cyclone III ; Stratix II ; +; State Machine Processing ; One-Hot ; Auto ; +; Optimization Technique ; Speed ; Balanced ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; +; FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; +; Video/DDR_CTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/DDR_CTR.tdf ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; +; lpm_latch0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_latch0.vhd ; +; altpll1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll1.vhd ; +; Video/lpm_fifoDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifoDZ.vhd ; +; altpll2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll2.vhd ; +; altpll3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll3.vhd ; +; Video/altdpram0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram0.vhd ; +; Video/lpm_muxDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxDZ.vhd ; +; Video/lpm_bustri3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri3.vhd ; +; Video/lpm_ff0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff0.vhd ; +; Video/lpm_ff1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff1.vhd ; +; Video/lpm_ff3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff3.vhd ; +; Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; +; Video/lpm_fifo_dc0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifo_dc0.vhd ; +; Video/Video.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/Video/Video.bdf ; +; firebee1.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/firebee1.bdf ; +; lpm_counter0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_counter0.vhd ; +; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; +; DSP/DSP.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/DSP/DSP.vhd ; +; Video/lpm_shiftreg0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg0.vhd ; +; Video/lpm_bustri1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri1.vhd ; +; Video/altdpram1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram1.vhd ; +; Video/lpm_constant0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant0.vhd ; +; Video/lpm_constant1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant1.vhd ; +; Video/lpm_mux0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux0.vhd ; +; Video/lpm_mux1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux1.vhd ; +; Video/lpm_mux2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux2.vhd ; +; Video/lpm_constant2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant2.vhd ; +; Video/altdpram2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram2.vhd ; +; Video/lpm_mux3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux3.vhd ; +; Video/lpm_mux4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux4.vhd ; +; Video/lpm_constant3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant3.vhd ; +; Interrupt_Handler/interrupt_handler.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Interrupt_Handler/interrupt_handler.tdf ; +; lpm_bustri_LONG.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_LONG.vhd ; +; lpm_bustri_BYT.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_BYT.vhd ; +; lpm_bustri_WORD.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_WORD.vhd ; +; Video/lpm_ff4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff4.vhd ; +; Video/lpm_ff5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff5.vhd ; +; Video/lpm_ff6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff6.vhd ; +; Video/altddio_bidir0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_bidir0.vhd ; +; Video/altddio_out0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out0.vhd ; +; Video/lpm_mux5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux5.vhd ; +; Video/BLITTER/BLITTER.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/Video/BLITTER/BLITTER.vhd ; +; Video/lpm_shiftreg6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg6.vhd ; +; Video/lpm_shiftreg4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg4.vhd ; +; Video/altddio_out2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out2.vhd ; +; altddio_out3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altddio_out3.vhd ; +; Video/lpm_mux6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux6.vhd ; +; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; +; FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; +; Video/lpm_muxVDM.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxVDM.vhd ; +; lpm_bustri_byt.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_byt.inc ; +; lpm_bustri_word.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_word.inc ; +; lpm_bustri_long.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_long.inc ; +; altpll.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.tdf ; +; db/altpll_pul2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_pul2.tdf ; +; dcfifo_mixed_widths.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf ; +; db/dcfifo_0hh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_0hh1.tdf ; +; db/a_gray2bin_lfb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_lfb.tdf ; +; db/a_graycounter_k47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_k47.tdf ; +; db/a_graycounter_fic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_fic.tdf ; +; db/altsyncram_bi31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_bi31.tdf ; +; db/alt_synch_pipe_ikd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_ikd.tdf ; +; db/dffpipe_hd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_hd9.tdf ; +; db/dffpipe_gd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_gd9.tdf ; +; db/dffpipe_pe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_pe9.tdf ; +; db/alt_synch_pipe_jkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_jkd.tdf ; +; db/dffpipe_id9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_id9.tdf ; +; db/cmpr_256.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_256.tdf ; +; db/cmpr_156.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_156.tdf ; +; db/cntr_t2e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_t2e.tdf ; +; db/mux_a18.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_a18.tdf ; +; db/dcfifo_3fh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_3fh1.tdf ; +; db/a_graycounter_j47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_j47.tdf ; +; db/a_graycounter_gic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_gic.tdf ; +; db/altsyncram_ci31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_ci31.tdf ; +; db/alt_synch_pipe_kkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_kkd.tdf ; +; db/dffpipe_jd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_jd9.tdf ; +; db/alt_synch_pipe_lkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_lkd.tdf ; +; db/dffpipe_kd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_kd9.tdf ; +; db/altpll_41p2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_41p2.tdf ; +; lpm_bustri.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_bustri.tdf ; +; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; +; dcfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo.tdf ; +; db/dcfifo_8fi1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_8fi1.tdf ; +; db/a_gray2bin_tgb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_tgb.tdf ; +; db/a_graycounter_s57.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_s57.tdf ; +; db/a_graycounter_ojc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_ojc.tdf ; +; db/a_graycounter_njc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_njc.tdf ; +; db/altsyncram_tl31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_tl31.tdf ; +; db/alt_synch_pipe_rld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_rld.tdf ; +; db/dffpipe_qe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_qe9.tdf ; +; db/dffpipe_9d9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_9d9.tdf ; +; db/dffpipe_oe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_oe9.tdf ; +; db/alt_synch_pipe_sld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_sld.tdf ; +; db/dffpipe_re9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_re9.tdf ; +; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf ; +; db/mux_bbe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_bbe.tdf ; +; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_ff.tdf ; +; altddio_bidir.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_bidir.tdf ; +; db/ddio_bidir_3jl.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_bidir_3jl.tdf ; +; db/mux_58e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_58e.tdf ; +; lpm_latch.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_latch.tdf ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf ; +; db/altsyncram_lf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_lf92.tdf ; +; mux41.bdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/others/maxplus2/mux41.bdf ; +; db/mux_dcf.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_dcf.tdf ; +; scfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/scfifo.tdf ; +; db/scfifo_lk21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/scfifo_lk21.tdf ; +; db/a_dpfifo_oq21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_dpfifo_oq21.tdf ; +; db/altsyncram_gj81.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_gj81.tdf ; +; db/cmpr_br8.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_br8.tdf ; +; db/cntr_omb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_omb.tdf ; +; db/cntr_5n7.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_5n7.tdf ; +; db/cntr_pmb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pmb.tdf ; +; db/altsyncram_rb92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_rb92.tdf ; +; db/altsyncram_pf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_pf92.tdf ; +; db/mux_96e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_96e.tdf ; +; db/mux_mpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_mpe.tdf ; +; db/mux_f6e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_f6e.tdf ; +; lpm_constant.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_constant.tdf ; +; altddio_out.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_out.tdf ; +; db/ddio_out_o2f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_o2f.tdf ; +; db/mux_kpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_kpe.tdf ; +; db/mux_npe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_npe.tdf ; +; db/mux_gpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_gpe.tdf ; +; db/ddio_out_are.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_are.tdf ; +; db/altpll_isv2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_isv2.tdf ; +; altpll4.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll4.tdf ; +; altpll.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.inc ; +; db/altpll_c6j2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_c6j2.tdf ; +; altpll_reconfig1.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll_reconfig1.tdf ; +; altpll_reconfig1_pllrcfg_t4q.tdf ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/altpll_reconfig1_pllrcfg_t4q.tdf ; +; altsyncram.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.inc ; +; db/altsyncram_46r.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_46r.tdf ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf ; +; db/add_sub_hpa.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_hpa.tdf ; +; db/add_sub_k8a.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_k8a.tdf ; +; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_compare.tdf ; +; db/cmpr_tnd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_tnd.tdf ; +; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf ; +; db/cntr_30l.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_30l.tdf ; +; db/cntr_qij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_qij.tdf ; +; db/cntr_pij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pij.tdf ; +; db/cntr_9cj.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_9cj.tdf ; +; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf ; +; db/decode_2af.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/decode_2af.tdf ; +; db/cntr_mph.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_mph.tdf ; +; db/ddio_out_31f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_31f.tdf ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mult.tdf ; +; db/mult_cat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_cat.tdf ; +; db/mult_aat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_aat.tdf ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 10,706 ; +; ; ; +; Total combinational functions ; 8060 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4947 ; +; -- 3 input functions ; 1867 ; +; -- <=2 input functions ; 1246 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7261 ; +; -- arithmetic mode ; 799 ; +; ; ; +; Total registers ; 4740 ; +; -- Dedicated logic registers ; 4612 ; +; -- I/O registers ; 256 ; +; ; ; +; I/O pins ; 295 ; +; Total memory bits ; 109344 ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Total PLLs ; 4 ; +; Maximum fan-out node ; MAIN_CLK~input ; +; Maximum fan-out ; 2327 ; +; Total fan-out ; 49317 ; +; Average fan-out ; 3.57 ; ++---------------------------------------------+----------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |firebee1 ; 8060 (10) ; 4612 (0) ; 109344 ; 6 ; 0 ; 3 ; 295 ; 0 ; |firebee1 ; work ; +; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|DSP:Mathias_Alles ; ; +; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 3814 (634) ; 1633 (114) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; +; |WF1772IP_TOP_SOC:I_FDC| ; 944 (24) ; 406 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; +; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 39 (39) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; +; |WF1772IP_CONTROL:I_CONTROL| ; 533 (533) ; 197 (197) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; +; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 40 (40) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; +; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 104 (104) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; +; |WF1772IP_REGISTERS:I_REGISTERS| ; 86 (86) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; +; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 118 (118) ; 80 (80) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; +; |WF2149IP_TOP_SOC:I_SOUND| ; 445 (32) ; 210 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; +; |WF2149IP_WAVE:I_PSG_WAVE| ; 413 (413) ; 181 (181) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; +; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; +; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; +; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 199 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 16 (16) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 203 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 20 (20) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF68901IP_TOP_SOC:I_MFP| ; 1199 (178) ; 460 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; +; |WF68901IP_GPIO:I_GPIO| ; 25 (25) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; +; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 273 (273) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; +; |WF68901IP_TIMERS:I_TIMERS| ; 434 (434) ; 166 (166) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; +; |WF68901IP_USART_TOP:I_USART| ; 289 (4) ; 140 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; +; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 38 (38) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; +; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 159 (159) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; +; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 88 (88) ; 35 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; +; |dcfifo0:RDF| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_0hh1:auto_generated| ; 94 (17) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; +; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; +; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; +; |a_graycounter_fic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; +; |a_graycounter_k47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; +; |alt_synch_pipe_ikd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; +; |dffpipe_hd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; +; |alt_synch_pipe_jkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; +; |dffpipe_id9:dffpipe17| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; +; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:ws_brp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; +; |dffpipe_pe9:ws_bwp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |dcfifo1:WRF| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_3fh1:auto_generated| ; 96 (18) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; +; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; +; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; +; |a_graycounter_gic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; +; |a_graycounter_j47:rdptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; +; |alt_synch_pipe_kkd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; +; |dffpipe_jd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; +; |alt_synch_pipe_lkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; +; |dffpipe_kd9:dffpipe15| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; +; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:rs_bwp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; +; |dffpipe_pe9:rs_brp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |Video:Fredi_Aschwanden| ; 3109 (10) ; 2172 (4) ; 92816 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden ; ; +; |DDR_CTR:DDR_CTR| ; 348 (314) ; 158 (158) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; +; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1260 (1013) ; 529 (529) ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; +; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; +; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; +; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; +; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; +; |altddio_bidir0:inst1| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; +; |altddio_bidir:altddio_bidir_component| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; +; |ddio_bidir_3jl:auto_generated| ; 0 (0) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; +; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; +; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; +; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; +; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; +; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; +; |lpm_ff0:inst13| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst14| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst15| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst16| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst17| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst18| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst19| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst12| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst20| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst3| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst4| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst9| ; 0 (0) ; 24 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst46| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst47| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst49| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst52| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; +; |lpm_ff4:inst10| ; 0 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst11| ; 0 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst97| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst71| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst94| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; +; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; +; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; +; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; +; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; +; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; +; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; +; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; +; |lpm_fifo_dc0:inst| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; +; |dcfifo:dcfifo_component| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; +; |dcfifo_8fi1:auto_generated| ; 66 (12) ; 98 (20) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; +; |a_graycounter_njc:wrptr_gp| ; 17 (17) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; +; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; +; |alt_synch_pipe_sld:ws_dgrp| ; 0 (0) ; 30 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; +; |dffpipe_re9:dffpipe22| ; 0 (0) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; +; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; +; |dffpipe_9d9:wraclr| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; +; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; +; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; +; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; +; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; +; |lpm_mux0:inst21| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; +; |lpm_mux:lpm_mux_component| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; +; |mux_gpe:auto_generated| ; 48 (48) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; +; |lpm_mux1:inst24| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; +; |lpm_mux:lpm_mux_component| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; +; |mux_npe:auto_generated| ; 80 (80) ; 81 (81) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; +; |lpm_mux2:inst25| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; +; |lpm_mux:lpm_mux_component| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; +; |mux_mpe:auto_generated| ; 80 (80) ; 41 (41) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; +; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; +; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; +; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; +; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; +; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; +; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; +; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; +; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; +; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; +; |lpm_mux6:inst7| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; +; |lpm_mux:lpm_mux_component| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; +; |mux_kpe:auto_generated| ; 90 (90) ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; +; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; +; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; +; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; +; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; +; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; +; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; +; |lpm_shiftreg0:sr0| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr1| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr2| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr3| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr4| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr5| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg4:inst26| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg6:inst92| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; +; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; +; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; +; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; +; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; +; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; +; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; +; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9 ; work ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; +; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst ; ; +; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component ; ; +; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; +; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; +; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; +; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; +; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; +; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; +; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; +; |altpll_reconfig1:inst7| ; 309 (0) ; 128 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7 ; ; +; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 309 (211) ; 128 (80) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; +; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; +; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; +; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; +; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; +; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; +; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; +; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; +; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; +; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; +; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; +; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; +; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; +; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; +; |interrupt_handler:nobody| ; 789 (711) ; 633 (633) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody ; ; +; |lpm_bustri_BYT:$00000| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; +; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; +; |lpm_counter0:inst18| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18 ; ; +; |lpm_counter:lpm_counter_component| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; +; |cntr_mph:auto_generated| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; +; |lpm_ff0:inst1| ; 0 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 28 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 8 ; 256 ; 32 ; 8192 ; None ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 32 ; 1024 ; 8 ; 8192 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 128 ; 128 ; 128 ; 16384 ; None ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 128 ; 512 ; 128 ; 65536 ; None ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 144 ; 1 ; -- ; -- ; 144 ; None ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis DSP Block Usage Summary ; ++---------------------------------------+-------------+ +; Statistic ; Number Used ; ++---------------------------------------+-------------+ +; Simple Multipliers (9-bit) ; 0 ; +; Simple Multipliers (18-bit) ; 3 ; +; Embedded Multiplier Blocks ; -- ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Signed Embedded Multipliers ; 0 ; +; Unsigned Embedded Multipliers ; 3 ; +; Mixed Sign Embedded Multipliers ; 0 ; +; Variable Sign Embedded Multipliers ; 0 ; +; Dedicated Input Shift Register Chains ; 0 ; ++---------------------------------------+-------------+ +Note: number of Embedded Multiplier Blocks used is only available after a successful fit. + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------+ +; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR ; ++---------+-------+-------+-------+-------+----------------------------------+ +; Name ; FR_S3 ; FR_S2 ; FR_S1 ; FR_S0 ; FR_WAIT ; ++---------+-------+-------+-------+-------+----------------------------------+ +; FR_WAIT ; 0 ; 0 ; 0 ; 0 ; 0 ; +; FR_S0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; FR_S1 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; FR_S2 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; FR_S3 ; 1 ; 0 ; 0 ; 0 ; 1 ; ++---------+-------+-------+-------+-------+----------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ +; Name ; DS_R6 ; DS_R5 ; DS_R4 ; DS_R3 ; DS_R2 ; DS_CB8 ; DS_CB6 ; DS_T10F ; DS_T9F ; DS_T8F ; DS_T7F ; DS_T6F ; DS_T5F ; DS_T4F ; DS_T9W ; DS_T8W ; DS_T7W ; DS_T6W ; DS_T5W ; DS_T4W ; DS_T5R ; DS_T4R ; DS_C7 ; DS_C6 ; DS_C5 ; DS_C4 ; DS_C3 ; DS_C2 ; DS_N8 ; DS_N7 ; DS_N6 ; DS_N5 ; DS_T3 ; DS_T2B ; DS_T2A ; DS_T1 ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ +; DS_T1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DS_T2A ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DS_T2B ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DS_T3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DS_N5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; DS_N6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_N7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_N8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T6W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T7W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T8W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T9W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T6F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T7F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T8F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T9F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T10F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_CB6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_CB8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R4 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R5 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ +; Name ; FCF_STATE.FCF_T7 ; FCF_STATE.FCF_T6 ; FCF_STATE.FCF_T3 ; FCF_STATE.FCF_T2 ; FCF_STATE.FCF_T1 ; FCF_STATE.FCF_T0 ; FCF_STATE.FCF_IDLE ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ +; FCF_STATE.FCF_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; FCF_STATE.FCF_T0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; FCF_STATE.FCF_T1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; FCF_STATE.FCF_T2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T3 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T6 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T7 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE ; ++----------------+--------------+--------------+--------------+-------------------------------------+ +; Name ; CMD_STATE.T7 ; CMD_STATE.T6 ; CMD_STATE.T1 ; CMD_STATE.IDLE ; ++----------------+--------------+--------------+--------------+-------------------------------------+ +; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; +; CMD_STATE.T1 ; 0 ; 0 ; 1 ; 1 ; +; CMD_STATE.T6 ; 0 ; 1 ; 0 ; 1 ; +; CMD_STATE.T7 ; 1 ; 0 ; 0 ; 1 ; ++----------------+--------------+--------------+--------------+-------------------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ +; Name ; INT_STATE.VECTOR_OUT ; INT_STATE.REQUEST ; INT_STATE.SCAN ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ +; INT_STATE.SCAN ; 0 ; 0 ; 0 ; +; INT_STATE.REQUEST ; 0 ; 1 ; 1 ; +; INT_STATE.VECTOR_OUT ; 1 ; 0 ; 1 ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.CHECK_BREAK ; TR_STATE.IDLE ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.CHECK_BREAK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ +; Name ; DMA_STATE.DMA_STEP_4 ; DMA_STATE.DMA_STEP_3 ; DMA_STATE.DMA_STEP_2 ; DMA_STATE.DMA_STEP_1 ; DMA_STATE.IDLE ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ +; DMA_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DMA_STATE.DMA_STEP_1 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DMA_STATE.DMA_STEP_2 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DMA_STATE.DMA_STEP_3 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DMA_STATE.DMA_STEP_4 ; 1 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ +; Name ; CTRL_STATE.DMA_INIT_RCV ; CTRL_STATE.DMA_TARG_RCV ; CTRL_STATE.DMA_SEND ; CTRL_STATE.WAIT_2200ns ; CTRL_STATE.WAIT_800ns ; CTRL_STATE.IDLE ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ +; CTRL_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CTRL_STATE.WAIT_800ns ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CTRL_STATE.WAIT_2200ns ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CTRL_STATE.DMA_SEND ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CTRL_STATE.DMA_TARG_RCV ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CTRL_STATE.DMA_INIT_RCV ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ +; Name ; PRECOMP.LATE ; PRECOMP.EARLY ; PRECOMP.NOMINAL ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ +; PRECOMP.NOMINAL ; 0 ; 0 ; 0 ; +; PRECOMP.EARLY ; 0 ; 1 ; 1 ; +; PRECOMP.LATE ; 1 ; 0 ; 1 ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ +; Name ; MFM_STATE.C_10 ; MFM_STATE.B_01 ; MFM_STATE.A_00 ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ +; MFM_STATE.A_00 ; 0 ; 0 ; 0 ; +; MFM_STATE.B_01 ; 0 ; 1 ; 1 ; +; MFM_STATE.C_10 ; 1 ; 0 ; 1 ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ +; Name ; CMD_STATE.T3_VERIFY_CRC ; CMD_STATE.T3_LOAD_SR ; CMD_STATE.T3_CHECK_RD ; CMD_STATE.T3_SET_DRQ_2 ; CMD_STATE.T3_LOAD_DATA_2 ; CMD_STATE.T3_SHIFT_ADR ; CMD_STATE.T3_VERIFY_AM ; CMD_STATE.T3_RD_ADR ; CMD_STATE.T3_SET_DRQ_1 ; CMD_STATE.T3_LOAD_DATA_1 ; CMD_STATE.T3_CHECK_DR ; CMD_STATE.T3_CHECK_BYTE ; CMD_STATE.T3_DETECT_AM ; CMD_STATE.T3_CHECK_INDEX_3 ; CMD_STATE.T3_SHIFT ; CMD_STATE.T3_RD_TRACK ; CMD_STATE.T3_DATALOST ; CMD_STATE.T3_CHECK_INDEX_2 ; CMD_STATE.T3_WR_DATA ; CMD_STATE.T3_LOAD_SHFT ; CMD_STATE.T3_CHECK_INDEX_1 ; CMD_STATE.T3_VERIFY_DRQ ; CMD_STATE.T3_DELAY_B3 ; CMD_STATE.T3_WR ; CMD_STATE.T2_WR_FF ; CMD_STATE.T2_WR_CRC ; CMD_STATE.T2_WRSTAT ; CMD_STATE.T2_DATALOST ; CMD_STATE.T2_VERIFY_DRQ_3 ; CMD_STATE.T2_WR_BYTE ; CMD_STATE.T2_LOAD_SHFT ; CMD_STATE.T2_WR_AM ; CMD_STATE.T2_WR_LEADIN ; CMD_STATE.T2_DELAY_B11 ; CMD_STATE.T2_CHECK_MODE ; CMD_STATE.T2_DELAY_B1 ; CMD_STATE.T2_VERIFY_DRQ_2 ; CMD_STATE.T2_DELAY_B8 ; CMD_STATE.T2_SET_DRQ ; CMD_STATE.T2_DELAY_B2 ; CMD_STATE.T2_MULTISECT ; CMD_STATE.T2_VERIFY_CRC_2 ; CMD_STATE.T2_RDSTAT ; CMD_STATE.T2_VERIFY_DRQ_1 ; CMD_STATE.T2_NEXTBYTE ; CMD_STATE.T2_LOAD_DATA ; CMD_STATE.T2_FIRSTBYTE ; CMD_STATE.T2_VERIFY_AM ; CMD_STATE.T2_VERIFY_CRC_1 ; CMD_STATE.T2_SCAN_LEN ; CMD_STATE.T2_SCAN_SECT ; CMD_STATE.T2_SCAN_TRACK ; CMD_STATE.T2_INIT ; CMD_STATE.T2_RD_WR_SECT ; CMD_STATE.T1_VERIFY_CRC ; CMD_STATE.T1_VERIFY_DELAY ; CMD_STATE.T1_SCAN_CRC ; CMD_STATE.T1_SCAN_TRACK ; CMD_STATE.T1_SPINDOWN ; CMD_STATE.T1_STEP_DELAY ; CMD_STATE.T1_TRAP ; CMD_STATE.T1_STEP ; CMD_STATE.T1_HEAD_CTRL ; CMD_STATE.T1_CHECK_DIR ; CMD_STATE.T1_COMP_TR_DSR ; CMD_STATE.T1_LOAD_SHFT ; CMD_STATE.T1_STEPPING ; CMD_STATE.T1_SEEK_RESTORE ; CMD_STATE.DECODE ; CMD_STATE.DELAY_15MS ; CMD_STATE.SPINUP ; CMD_STATE.INIT ; CMD_STATE.IDLE ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ +; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CMD_STATE.INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CMD_STATE.SPINUP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CMD_STATE.DELAY_15MS ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CMD_STATE.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SEEK_RESTORE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEPPING ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_COMP_TR_DSR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_CHECK_DIR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_HEAD_CTRL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_TRAP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEP_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SPINDOWN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SCAN_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_VERIFY_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_VERIFY_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_RD_WR_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_LEN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_CRC_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_FIRSTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_LOAD_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_NEXTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_RDSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_CRC_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_MULTISECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SET_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_CHECK_MODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_LEADIN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WRSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_FF ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_WR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DELAY_B3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_WR_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_RD_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SHIFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DETECT_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_DR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_DATA_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SET_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_RD_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SHIFT_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_DATA_2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SET_DRQ_2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_RD ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_SR ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_CRC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate3_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[8] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[17] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate2_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_seq_ena_state ; no ; yes ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; User-Specified and Inferred Latches ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Number of user-specified and inferred latches = 32 ; ; ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[31] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[30] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[29] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[28] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[27] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[26] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[25] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[24] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[23] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[22] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[21] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[20] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[19] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[18] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[17] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[16] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[15] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[14] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[13] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[12] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[11] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[10] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[7] ; Lost fanout ; +; interrupt_handler:nobody|WERTE[7][13] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[6][10] ; Stuck at GND due to stuck port clear ; +; interrupt_handler:nobody|WERTE[2][11] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[1][11] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[0][11] ; Stuck at VCC due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_REQ ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0..6] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0..5] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0..7] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[6] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0,2..5,7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[0..2] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[0..7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SPER ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0..2] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6..7] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[2] ; Merged with Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_OUT ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|OE ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[6] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[7] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[0..3] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_DRQ:LOCK ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_ACTIVE_I ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4,7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[1] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe18 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe2 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe20 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe34 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe36 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe4 ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|INT ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DRQ ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[0..7] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDRWR_D_SEL ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[0..2] ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; +; Video:Fredi_Aschwanden|inst88 ; Merged with Video:Fredi_Aschwanden|inst90 ; +; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[0..2] ; Merged with Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_AC ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[2] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DELAY_800ns ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[0..3] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[0] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12] ; Lost fanout ; +; Total Number of Removed Registers = 223 ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN, ; +; ; due to stuck port data_in ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[2] ; +; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[30] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[29] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[28] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[27] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[26] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[25] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[24] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[23] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[22] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[21] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[20] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[19] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[18] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[17] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[16] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[15] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[14] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[13] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[12] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[11] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[10] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[7] ; +; ; due to stuck port clock ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[17] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[16] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[9] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[8] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[1] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[20] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[20] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[19] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[19] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[18] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[18] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[17] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[16] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[12] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[12] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[11] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[11] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[10] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[10] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[9] ; +; ; due to stuck port data_in ; ; +; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[31] ; +; ; due to stuck port clock ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[4] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[4] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[3] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[3] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[2] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[2] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[1] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[8] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[2] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; +; ; due to stuck port data_in ; ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 4612 ; +; Number of registers using Synchronous Clear ; 156 ; +; Number of registers using Synchronous Load ; 204 ; +; Number of registers using Asynchronous Clear ; 1431 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 2735 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Inverted Register Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[2] ; 5 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[1] ; 5 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT[7] ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IRQ_ACIAn ; 2 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; 8 ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; 2 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; 4 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|counter8a0 ; 8 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|parity9 ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; 1 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 3 ; +; Total number of inverted registers = 22 ; ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[7] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4] ; +; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; +; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; +; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[7] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[6] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2] ; +; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[0] ; +; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:CLK_DIVCNT[0] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_START_BIT:TMP[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:LOW_FLT[0] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[3] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[0] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1] ; +; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[7] ; +; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; +; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[19] ; +; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1] ; +; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0] ; +; 4:1 ; 31 bits ; 62 LEs ; 62 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:TIMER[1] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[5] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[2] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[1] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[5] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; +; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2] ; +; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4] ; +; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4] ; +; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5] ; +; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6] ; +; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; +; 7:1 ; 13 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[10] ; +; 6:1 ; 20 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; +; 11:1 ; 2 bits ; 14 LEs ; 10 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1] ; +; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0] ; +; 9:1 ; 2 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5] ; +; 14:1 ; 5 bits ; 45 LEs ; 10 LEs ; 35 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3] ; +; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B[1] ; +; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A[1] ; +; 17:1 ; 4 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[2] ; +; 17:1 ; 4 bits ; 44 LEs ; 0 LEs ; 44 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5] ; +; 3:1 ; 24 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEXCNT ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21] ; +; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|DATA_OUT[4] ; +; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|NEXT_CMD_STATE ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_A[1] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_B[2] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_C[1] ; +; 16:1 ; 8 bits ; 80 LEs ; 24 LEs ; 56 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|DATA_OUT[2] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ADDER_IN[1] ; +; 64:1 ; 3 bits ; 126 LEs ; 126 LEs ; 0 LEs ; No ; |firebee1|interrupt_handler:nobody|_ ; +; 17:1 ; 3 bits ; 33 LEs ; 18 LEs ; 15 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[7] ; +; 18:1 ; 4 bits ; 48 LEs ; 44 LEs ; 4 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[2] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe17|dffe18a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity9a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity8 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity6a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity5 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+----------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+----------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+----------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 4 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; R105 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe22|dffe23a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe15|dffe16a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity12a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity11 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ++---------------------------+-------------+------+---------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_L ; +; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_H ; +; SUPPRESS_DA_RULE_INTERNAL ; D101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; D103 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; D102 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_h ; +; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_l ; +; MEGAFUNCTION_GENERATED_TRI ; ON ; - ; tri_buf1a ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+---------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+---------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ++---------------------------+-------+------+-----------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; ++---------------------------+-------+------+-----------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ++---------------------------------------+-------------+------+------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------+------+------------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 2 ; - ; le_comb10 ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 0 ; - ; le_comb8 ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 1 ; - ; le_comb9 ; +; POWER_UP_LEVEL ; LOW ; - ; idle_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_data_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_first_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_first_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_init_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_last_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_last_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_counter_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_post_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_ena_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_wait_state ; +; POWER_UP_LEVEL ; HIGH ; - ; reset_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_init_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_nominal_state ; ++---------------------------------------+-------------+------+------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------+ +; Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ++---------------------------+-------+------+-----------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-----------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component ; ++-------------------------------+--------------------+------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 67 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 67 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 90 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 900 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 66 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_pul2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; LPM_NUMWORDS ; 1024 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_WIDTH_R ; 32 ; Signed Integer ; +; LPM_WIDTHU ; 10 ; Signed Integer ; +; LPM_WIDTHU_R ; 8 ; Signed Integer ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; CBXI_PARAMETER ; dcfifo_0hh1 ; Untyped ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; LPM_NUMWORDS ; 256 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_WIDTH_R ; 8 ; Signed Integer ; +; LPM_WIDTHU ; 8 ; Signed Integer ; +; LPM_WIDTHU_R ; 10 ; Signed Integer ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; CBXI_PARAMETER ; dcfifo_3fh1 ; Untyped ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; TOP ; 152 ; Signed Integer ; +; BOTTOM ; 104 ; Signed Integer ; +; PHASE_CORR ; 75 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component ; ++-------------------------------+--------------------+--------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+--------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK1 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 16 ; Signed Integer ; +; CLK2_MULTIPLY_BY ; 25 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 16 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 11 ; Signed Integer ; +; CLK2_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_USED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_41p2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+--------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 6 ; Signed Integer ; +; WRSYNC_DELAYPIPE ; 6 ; Signed Integer ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; ON ; Untyped ; +; CBXI_PARAMETER ; dcfifo_8fi1 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+---------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_SIZE ; 16 ; Signed Integer ; +; LPM_WIDTHS ; 4 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_bbe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 32 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; IMPLEMENT_INPUT_IN_LCELL ; ON ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_bidir_3jl ; Untyped ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 64 ; Signed Integer ; +; LPM_SIZE ; 4 ; Signed Integer ; +; LPM_WIDTHS ; 2 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_58e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 1 ; Signed Integer ; +; CBXI_PARAMETER ; mux_dcf ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 128 ; Signed Integer ; +; LPM_NUMWORDS ; 128 ; Signed Integer ; +; LPM_WIDTHU ; 7 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; CBXI_PARAMETER ; scfifo_lk21 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 1 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_96e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_SIZE ; 16 ; Signed Integer ; +; LPM_WIDTHS ; 4 ; Signed Integer ; +; LPM_PIPELINE ; 2 ; Signed Integer ; +; CBXI_PARAMETER ; mux_mpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 7 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_f6e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 7 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_pf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 24 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_o2f ; Untyped ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_SIZE ; 8 ; Signed Integer ; +; LPM_WIDTHS ; 3 ; Signed Integer ; +; LPM_PIPELINE ; 2 ; Signed Integer ; +; CBXI_PARAMETER ; mux_kpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_SIZE ; 8 ; Signed Integer ; +; LPM_WIDTHS ; 3 ; Signed Integer ; +; LPM_PIPELINE ; 4 ; Signed Integer ; +; CBXI_PARAMETER ; mux_npe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_qf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_SIZE ; 4 ; Signed Integer ; +; LPM_WIDTHS ; 2 ; Signed Integer ; +; LPM_PIPELINE ; 4 ; Signed Integer ; +; CBXI_PARAMETER ; mux_gpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 4 ; Signed Integer ; +; POWER_UP_HIGH ; ON ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_are ; Untyped ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component ; ++-------------------------------+--------------------+--------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+--------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK3_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK2_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK3_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK2_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 11364 ; Untyped ; +; CLK3_PHASE_SHIFT ; 2210 ; Untyped ; +; CLK2_PHASE_SHIFT ; 3788 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 5051 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_USED ; Untyped ; +; PORT_CLK4 ; PORT_USED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_isv2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+--------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component ; ++-------------------------------+-------------------+---------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------------------+---------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20833 ; Untyped ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 2 ; Untyped ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 1 ; Untyped ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Untyped ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_USED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_USED ; Untyped ; +; PORT_SCANDONE ; PORT_USED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_USED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_USED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_USED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_USED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_c6j2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Untyped ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; altpll4.mif ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+-------------------+---------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; SINGLE_PORT ; Untyped ; +; WIDTH_A ; 1 ; Untyped ; +; WIDTHAD_A ; 8 ; Untyped ; +; NUMWORDS_A ; 144 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_46r ; Untyped ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 9 ; Untyped ; +; LPM_REPRESENTATION ; SIGNED ; Untyped ; +; LPM_DIRECTION ; DEFAULT ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_hpa ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_REPRESENTATION ; SIGNED ; Untyped ; +; LPM_DIRECTION ; DEFAULT ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_k8a ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; lpm_width ; 8 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; CHAIN_SIZE ; 8 ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CASCADE_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; CASCADE_CHAIN_LENGTH ; 2 ; CASCADE_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; cmpr_tnd ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 6 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_qij ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 5 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_pij ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_9cj ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 5 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_pij ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Untyped ; +; LPM_DECODES ; 5 ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; CASCADE_CHAIN ; MANUAL ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; decode_2af ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ++------------------------+-------------+-------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 18 ; Signed Integer ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_mph ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 6 ; Untyped ; +; LPM_WIDTHP ; 18 ; Untyped ; +; LPM_WIDTHR ; 18 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_cat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 5 ; Untyped ; +; LPM_WIDTHP ; 17 ; Untyped ; +; LPM_WIDTHR ; 17 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_aat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 5 ; Untyped ; +; LPM_WIDTHP ; 17 ; Untyped ; +; LPM_WIDTHR ; 17 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_aat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+----------------------------------------+ +; Name ; Value ; ++-------------------------------+----------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; altpll1:inst|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll3:inst13|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll2:inst12|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll4:inst22|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20833 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+----------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; lpm_shiftreg Parameter Settings by Entity Instance ; ++----------------------------+---------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+---------------------------------------------------------------------------------+ +; Number of entity instances ; 11 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; ++----------------------------+---------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; dcfifo Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 128 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 128 ; +; -- LPM_NUMWORDS ; 128 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; ++----------------------------+------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ +; Number of entity instances ; 10 ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; +; -- OPERATION_MODE ; SINGLE_PORT ; +; -- WIDTH_A ; 1 ; +; -- NUMWORDS_A ; 144 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+-----------------------------------------------------------------------------------+ +; Name ; Value ; ++---------------------------------------+-----------------------------------------------------------------------------------+ +; Number of entity instances ; 3 ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 6 ; +; -- LPM_WIDTHP ; 18 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 5 ; +; -- LPM_WIDTHP ; 17 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 5 ; +; -- LPM_WIDTHP ; 17 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+-----------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ +; seln ; Input ; Info ; Stuck at VCC ; +; bc2 ; Input ; Info ; Stuck at VCC ; +; a9n ; Input ; Info ; Stuck at GND ; +; a8 ; Input ; Info ; Stuck at VCC ; +; da_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_a_in ; Input ; Info ; Stuck at GND ; +; io_a_out[2] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_a_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_b_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; gpip_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; gpip_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; iein ; Input ; Info ; Stuck at GND ; +; ieon ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tai ; Input ; Info ; Stuck at GND ; +; tao ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tbo ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tco ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; so_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; rrn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; trn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ +; cs2n ; Input ; Info ; Stuck at GND ; +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ctsn ; Input ; Info ; Stuck at GND ; +; dcdn ; Input ; Info ; Stuck at GND ; +; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ +; cs1 ; Input ; Info ; Stuck at VCC ; +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ctsn ; Input ; Info ; Stuck at GND ; +; dcdn ; Input ; Info ; Stuck at GND ; +; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; icr_out[7] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; icr_out[5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; csn ; Input ; Info ; Stuck at VCC ; +; eopn ; Input ; Info ; Stuck at VCC ; +; ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ack_inn ; Input ; Info ; Stuck at VCC ; +; ack_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; atn_inn ; Input ; Info ; Stuck at VCC ; +; atn_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; req_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; req_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ion_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; cdn_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; cd_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; msg_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; msg_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; dden ; Input ; Info ; Stuck at GND ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:20:37 2010 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_control.vhd + Info: Found design unit 1: WF5380_CONTROL-BEHAVIOUR + Info: Found entity 1: WF5380_CONTROL +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_pkg.vhd + Info: Found design unit 1: WF5380_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_registers.vhd + Info: Found design unit 1: WF5380_REGISTERS-BEHAVIOUR + Info: Found entity 1: WF5380_REGISTERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_soc_top.vhd + Info: Found design unit 1: WF5380_TOP_SOC-STRUCTURE + Info: Found entity 1: WF5380_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_top.vhd + Info: Found design unit 1: WF5380_TOP-STRUCTURE + Info: Found entity 1: WF5380_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_am_detector.vhd + Info: Found design unit 1: WF1772IP_AM_DETECTOR-BEHAVIOR + Info: Found entity 1: WF1772IP_AM_DETECTOR +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo0.vhd + Info: Found design unit 1: dcfifo0-SYN + Info: Found entity 1: dcfifo0 +Info: Found 1 design units, including 1 entities, in source file video/ddr_ctr.tdf + Info: Found entity 1: DDR_CTR +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri0.vhd + Info: Found design unit 1: lpm_bustri0-SYN + Info: Found entity 1: lpm_bustri0 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_control.vhd + Info: Found design unit 1: WF1772IP_CONTROL-BEHAVIOR + Info: Found entity 1: WF1772IP_CONTROL +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_crc_logic.vhd + Info: Found design unit 1: WF1772IP_CRC_LOGIC-BEHAVIOR + Info: Found entity 1: WF1772IP_CRC_LOGIC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_digital_pll.vhd + Info: Found design unit 1: WF1772IP_DIGITAL_PLL-BEHAVIOR + Info: Found entity 1: WF1772IP_DIGITAL_PLL +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_pkg.vhd + Info: Found design unit 1: WF1772IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_registers.vhd + Info: Found design unit 1: WF1772IP_REGISTERS-BEHAVIOR + Info: Found entity 1: WF1772IP_REGISTERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top.vhd + Info: Found design unit 1: WF1772IP_TOP-STRUCTURE + Info: Found entity 1: WF1772IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top_soc.vhd + Info: Found design unit 1: WF1772IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF1772IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_transceiver.vhd + Info: Found design unit 1: WF1772IP_TRANSCEIVER-BEHAVIOR + Info: Found entity 1: WF1772IP_TRANSCEIVER +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri5.vhd + Info: Found design unit 1: lpm_bustri5-SYN + Info: Found entity 1: lpm_bustri5 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_ctrl_status.vhd + Info: Found design unit 1: WF6850IP_CTRL_STATUS-BEHAVIOR + Info: Found entity 1: WF6850IP_CTRL_STATUS +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri7.vhd + Info: Found design unit 1: lpm_bustri7-SYN + Info: Found entity 1: lpm_bustri7 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_receive.vhd + Info: Found design unit 1: WF6850IP_RECEIVE-BEHAVIOR + Info: Found entity 1: WF6850IP_RECEIVE +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top.vhd + Info: Found design unit 1: WF6850IP_TOP-STRUCTURE + Info: Found entity 1: WF6850IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top_soc.vhd + Info: Found design unit 1: WF6850IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF6850IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_transmit.vhd + Info: Found design unit 1: WF6850IP_TRANSMIT-BEHAVIOR + Info: Found entity 1: WF6850IP_TRANSMIT +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_gpio.vhd + Info: Found design unit 1: WF68901IP_GPIO-BEHAVIOR + Info: Found entity 1: WF68901IP_GPIO +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_interrupts.vhd + Info: Found design unit 1: WF68901IP_INTERRUPTS-BEHAVIOR + Info: Found entity 1: WF68901IP_INTERRUPTS +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_pkg.vhd + Info: Found design unit 1: WF68901IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_timers.vhd + Info: Found design unit 1: WF68901IP_TIMERS-BEHAVIOR + Info: Found entity 1: WF68901IP_TIMERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top.vhd + Info: Found design unit 1: WF68901IP_TOP-STRUCTURE + Info: Found entity 1: WF68901IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top_soc.vhd + Info: Found design unit 1: WF68901IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF68901IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_ctrl.vhd + Info: Found design unit 1: WF68901IP_USART_CTRL-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_CTRL +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_rx.vhd + Info: Found design unit 1: WF68901IP_USART_RX-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_RX +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_top.vhd + Info: Found design unit 1: WF68901IP_USART_TOP-STRUCTURE + Info: Found entity 1: WF68901IP_USART_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_tx.vhd + Info: Found design unit 1: WF68901IP_USART_TX-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_TX +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_pkg.vhd + Info: Found design unit 1: WF2149IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top.vhd + Info: Found design unit 1: WF2149IP_TOP-STRUCTURE + Info: Found entity 1: WF2149IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top_soc.vhd + Info: Found design unit 1: WF2149IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF2149IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_wave.vhd + Info: Found design unit 1: WF2149IP_WAVE-BEHAVIOR + Info: Found entity 1: WF2149IP_WAVE +Info: Found 2 design units, including 1 entities, in source file lpm_latch0.vhd + Info: Found design unit 1: lpm_latch0-SYN + Info: Found entity 1: lpm_latch0 +Info: Found 2 design units, including 1 entities, in source file altpll1.vhd + Info: Found design unit 1: altpll1-SYN + Info: Found entity 1: altpll1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_fifodz.vhd + Info: Found design unit 1: lpm_fifodz-SYN + Info: Found entity 1: lpm_fifoDZ +Info: Found 2 design units, including 1 entities, in source file altpll2.vhd + Info: Found design unit 1: altpll2-SYN + Info: Found entity 1: altpll2 +Info: Found 2 design units, including 1 entities, in source file altpll3.vhd + Info: Found design unit 1: altpll3-SYN + Info: Found entity 1: altpll3 +Info: Found 2 design units, including 1 entities, in source file video/altdpram0.vhd + Info: Found design unit 1: altdpram0-SYN + Info: Found entity 1: altdpram0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz2.vhd + Info: Found design unit 1: lpm_muxdz2-SYN + Info: Found entity 1: lpm_muxDZ2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz.vhd + Info: Found design unit 1: lpm_muxdz-SYN + Info: Found entity 1: lpm_muxDZ +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri3.vhd + Info: Found design unit 1: lpm_bustri3-SYN + Info: Found entity 1: lpm_bustri3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff0.vhd + Info: Found design unit 1: lpm_ff0-SYN + Info: Found entity 1: lpm_ff0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff1.vhd + Info: Found design unit 1: lpm_ff1-SYN + Info: Found entity 1: lpm_ff1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff3.vhd + Info: Found design unit 1: lpm_ff3-SYN + Info: Found entity 1: lpm_ff3 +Info: Found 1 design units, including 1 entities, in source file video/video_mod_mux_clutctr.tdf + Info: Found entity 1: VIDEO_MOD_MUX_CLUTCTR +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff2.vhd + Info: Found design unit 1: lpm_ff2-SYN + Info: Found entity 1: lpm_ff2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_fifo_dc0.vhd + Info: Found design unit 1: lpm_fifo_dc0-SYN + Info: Found entity 1: lpm_fifo_dc0 +Info: Found 1 design units, including 1 entities, in source file video/video.bdf + Info: Found entity 1: Video +Info: Found 1 design units, including 1 entities, in source file firebee1.bdf + Info: Found entity 1: firebee1 +Info: Found 2 design units, including 1 entities, in source file altpll0.vhd + Info: Found design unit 1: altpll0-SYN + Info: Found entity 1: altpll0 +Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd + Info: Found design unit 1: lpm_counter0-SYN + Info: Found entity 1: lpm_counter0 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf.vhd + Info: Found design unit 1: FalconIO_SDCard_IDE_CF-FalconIO_SDCard_IDE_CF_architecture + Info: Found entity 1: FalconIO_SDCard_IDE_CF +Info: Found 2 design units, including 1 entities, in source file dsp/dsp.vhd + Info: Found design unit 1: DSP-DSP_architecture + Info: Found entity 1: DSP +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg0.vhd + Info: Found design unit 1: lpm_shiftreg0-SYN + Info: Found entity 1: lpm_shiftreg0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri1.vhd + Info: Found design unit 1: lpm_bustri1-SYN + Info: Found entity 1: lpm_bustri1 +Info: Found 2 design units, including 1 entities, in source file video/altdpram1.vhd + Info: Found design unit 1: altdpram1-SYN + Info: Found entity 1: altdpram1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri2.vhd + Info: Found design unit 1: lpm_bustri2-SYN + Info: Found entity 1: lpm_bustri2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri4.vhd + Info: Found design unit 1: lpm_bustri4-SYN + Info: Found entity 1: lpm_bustri4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant0.vhd + Info: Found design unit 1: lpm_constant0-SYN + Info: Found entity 1: lpm_constant0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant1.vhd + Info: Found design unit 1: lpm_constant1-SYN + Info: Found entity 1: lpm_constant1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux0.vhd + Info: Found design unit 1: lpm_mux0-SYN + Info: Found entity 1: lpm_mux0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux1.vhd + Info: Found design unit 1: lpm_mux1-SYN + Info: Found entity 1: lpm_mux1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux2.vhd + Info: Found design unit 1: lpm_mux2-SYN + Info: Found entity 1: lpm_mux2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant2.vhd + Info: Found design unit 1: lpm_constant2-SYN + Info: Found entity 1: lpm_constant2 +Info: Found 2 design units, including 1 entities, in source file video/altdpram2.vhd + Info: Found design unit 1: altdpram2-SYN + Info: Found entity 1: altdpram2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri6.vhd + Info: Found design unit 1: lpm_bustri6-SYN + Info: Found entity 1: lpm_bustri6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux3.vhd + Info: Found design unit 1: lpm_mux3-SYN + Info: Found entity 1: lpm_mux3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux4.vhd + Info: Found design unit 1: lpm_mux4-SYN + Info: Found entity 1: lpm_mux4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant3.vhd + Info: Found design unit 1: lpm_constant3-SYN + Info: Found entity 1: lpm_constant3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg1.vhd + Info: Found design unit 1: lpm_shiftreg1-SYN + Info: Found entity 1: lpm_shiftreg1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_latch1.vhd + Info: Found design unit 1: lpm_latch1-SYN + Info: Found entity 1: lpm_latch1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant4.vhd + Info: Found design unit 1: lpm_constant4-SYN + Info: Found entity 1: lpm_constant4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg2.vhd + Info: Found design unit 1: lpm_shiftreg2-SYN + Info: Found entity 1: lpm_shiftreg2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_compare1.vhd + Info: Found design unit 1: lpm_compare1-SYN + Info: Found entity 1: lpm_compare1 +Info: Found 1 design units, including 1 entities, in source file interrupt_handler/interrupt_handler.tdf + Info: Found entity 1: interrupt_handler +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_long.vhd + Info: Found design unit 1: lpm_bustri_long-SYN + Info: Found entity 1: lpm_bustri_LONG +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_byt.vhd + Info: Found design unit 1: lpm_bustri_byt-SYN + Info: Found entity 1: lpm_bustri_BYT +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_word.vhd + Info: Found design unit 1: lpm_bustri_word-SYN + Info: Found entity 1: lpm_bustri_WORD +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff4.vhd + Info: Found design unit 1: lpm_ff4-SYN + Info: Found entity 1: lpm_ff4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff5.vhd + Info: Found design unit 1: lpm_ff5-SYN + Info: Found entity 1: lpm_ff5 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff6.vhd + Info: Found design unit 1: lpm_ff6-SYN + Info: Found entity 1: lpm_ff6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg3.vhd + Info: Found design unit 1: lpm_shiftreg3-SYN + Info: Found entity 1: lpm_shiftreg3 +Info: Found 2 design units, including 1 entities, in source file video/altddio_bidir0.vhd + Info: Found design unit 1: altddio_bidir0-SYN + Info: Found entity 1: altddio_bidir0 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out0.vhd + Info: Found design unit 1: altddio_out0-SYN + Info: Found entity 1: altddio_out0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux5.vhd + Info: Found design unit 1: lpm_mux5-SYN + Info: Found entity 1: lpm_mux5 +Info: Found 2 design units, including 1 entities, in source file video/blitter/blitter.vhd + Info: Found design unit 1: BLITTER-BLITTER_architecture + Info: Found entity 1: BLITTER +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg5.vhd + Info: Found design unit 1: lpm_shiftreg5-SYN + Info: Found entity 1: lpm_shiftreg5 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg6.vhd + Info: Found design unit 1: lpm_shiftreg6-SYN + Info: Found entity 1: lpm_shiftreg6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg4.vhd + Info: Found design unit 1: lpm_shiftreg4-SYN + Info: Found entity 1: lpm_shiftreg4 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out1.vhd + Info: Found design unit 1: altddio_out1-SYN + Info: Found entity 1: altddio_out1 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out2.vhd + Info: Found design unit 1: altddio_out2-SYN + Info: Found entity 1: altddio_out2 +Info: Found 2 design units, including 1 entities, in source file altddio_out3.vhd + Info: Found design unit 1: altddio_out3-SYN + Info: Found entity 1: altddio_out3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux6.vhd + Info: Found design unit 1: lpm_mux6-SYN + Info: Found entity 1: lpm_mux6 +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf_pgk.vhd + Info: Found design unit 1: FalconIO_SDCard_IDE_CF_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo1.vhd + Info: Found design unit 1: dcfifo1-SYN + Info: Found entity 1: dcfifo1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxvdm.vhd + Info: Found design unit 1: lpm_muxvdm-SYN + Info: Found entity 1: lpm_muxVDM +Info: Elaborating entity "firebee1" for the top level hierarchy +Warning: Pin "TOUT0" not connected +Warning: Pin "nMASTER" not connected +Info: Elaborating entity "altpll1" for hierarchy "altpll1:inst" +Info: Elaborating entity "altpll" for hierarchy "altpll1:inst|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll1:inst|altpll:altpll_component" +Info: Instantiated megafunction "altpll1:inst|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "66" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "1" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "clk1_divide_by" = "900" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "67" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "90" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "67" + Info: Parameter "clk2_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_USED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_UNUSED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "self_reset_on_loss_lock" = "OFF" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_pul2.tdf + Info: Found entity 1: altpll_pul2 +Info: Elaborating entity "altpll_pul2" for hierarchy "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated" +Info: Elaborating entity "FalconIO_SDCard_IDE_CF" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden" +Warning (10036): Verilog HDL or VHDL warning at FalconIO_SDCard_IDE_CF.vhd(244): object "SCSI_CSn" assigned a value but never read +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(303): signal "nIDE_RD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(304): signal "nIDE_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(313): signal "IDE_CF_CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(314): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(315): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(324): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(325): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(335): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(336): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Critical Warning (10920): VHDL Incomplete Partial Association warning at FalconIO_SDCard_IDE_CF.vhd(928): port or argument "IO_A_OUT" has 1/8 unassociated elements +Info: Elaborating entity "dcfifo0" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF" +Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "1024" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "8" + Info: Parameter "lpm_widthu" = "10" + Info: Parameter "lpm_widthu_r" = "8" + Info: Parameter "lpm_width_r" = "32" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "rdsync_delaypipe" = "5" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "OFF" + Info: Parameter "wrsync_delaypipe" = "5" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_0hh1.tdf + Info: Found entity 1: dcfifo_0hh1 +Info: Elaborating entity "dcfifo_0hh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_lfb.tdf + Info: Found entity 1: a_gray2bin_lfb +Info: Elaborating entity "a_gray2bin_lfb" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_k47.tdf + Info: Found entity 1: a_graycounter_k47 +Info: Elaborating entity "a_graycounter_k47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fic.tdf + Info: Found entity 1: a_graycounter_fic +Info: Elaborating entity "a_graycounter_fic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bi31.tdf + Info: Found entity 1: altsyncram_bi31 +Info: Elaborating entity "altsyncram_bi31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf + Info: Found entity 1: alt_synch_pipe_ikd +Info: Elaborating entity "alt_synch_pipe_ikd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf + Info: Found entity 1: dffpipe_hd9 +Info: Elaborating entity "dffpipe_hd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf + Info: Found entity 1: dffpipe_gd9 +Info: Elaborating entity "dffpipe_gd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf + Info: Found entity 1: dffpipe_pe9 +Info: Elaborating entity "dffpipe_pe9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jkd.tdf + Info: Found entity 1: alt_synch_pipe_jkd +Info: Elaborating entity "alt_synch_pipe_jkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf + Info: Found entity 1: dffpipe_id9 +Info: Elaborating entity "dffpipe_id9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_256.tdf + Info: Found entity 1: cmpr_256 +Info: Elaborating entity "cmpr_256" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_256:rdempty_eq_comp1_lsb" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_156.tdf + Info: Found entity 1: cmpr_156 +Info: Elaborating entity "cmpr_156" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb" +Info: Found 1 design units, including 1 entities, in source file db/cntr_t2e.tdf + Info: Found entity 1: cntr_t2e +Info: Elaborating entity "cntr_t2e" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b" +Info: Found 1 design units, including 1 entities, in source file db/mux_a18.tdf + Info: Found entity 1: mux_a18 +Info: Elaborating entity "mux_a18" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux" +Info: Elaborating entity "dcfifo1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF" +Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "256" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "32" + Info: Parameter "lpm_widthu" = "8" + Info: Parameter "lpm_widthu_r" = "10" + Info: Parameter "lpm_width_r" = "8" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "rdsync_delaypipe" = "5" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "OFF" + Info: Parameter "wrsync_delaypipe" = "5" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_3fh1.tdf + Info: Found entity 1: dcfifo_3fh1 +Info: Elaborating entity "dcfifo_3fh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j47.tdf + Info: Found entity 1: a_graycounter_j47 +Info: Elaborating entity "a_graycounter_j47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_gic.tdf + Info: Found entity 1: a_graycounter_gic +Info: Elaborating entity "a_graycounter_gic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ci31.tdf + Info: Found entity 1: altsyncram_ci31 +Info: Elaborating entity "altsyncram_ci31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_kkd.tdf + Info: Found entity 1: alt_synch_pipe_kkd +Info: Elaborating entity "alt_synch_pipe_kkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf + Info: Found entity 1: dffpipe_jd9 +Info: Elaborating entity "dffpipe_jd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lkd.tdf + Info: Found entity 1: alt_synch_pipe_lkd +Info: Elaborating entity "alt_synch_pipe_lkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_kd9.tdf + Info: Found entity 1: dffpipe_kd9 +Info: Elaborating entity "dffpipe_kd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15" +Info: Elaborating entity "WF1772IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" +Info: Elaborating entity "WF1772IP_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL" +Info: Elaborating entity "WF1772IP_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS" +Info: Elaborating entity "WF1772IP_DIGITAL_PLL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL" +Info: Elaborating entity "WF1772IP_AM_DETECTOR" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR" +Info: Elaborating entity "WF1772IP_CRC_LOGIC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC" +Info: Elaborating entity "WF1772IP_TRANSCEIVER" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER" +Info: Elaborating entity "WF5380_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" +Info: Elaborating entity "WF5380_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" +Info: Elaborating entity "WF5380_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL" +Info: Elaborating entity "WF6850IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" +Info: Elaborating entity "WF6850IP_CTRL_STATUS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS" +Info: Elaborating entity "WF6850IP_RECEIVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE" +Info: Elaborating entity "WF6850IP_TRANSMIT" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT" +Info: Elaborating entity "WF68901IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" +Info: Elaborating entity "WF68901IP_USART_TOP" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART" +Info: Elaborating entity "WF68901IP_USART_CTRL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL" +Info: Elaborating entity "WF68901IP_USART_RX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE" +Info: Elaborating entity "WF68901IP_USART_TX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT" +Info: Elaborating entity "WF68901IP_INTERRUPTS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS" +Info: Elaborating entity "WF68901IP_GPIO" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO" +Info: Elaborating entity "WF68901IP_TIMERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS" +Info: Elaborating entity "WF2149IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" +Info: Elaborating entity "WF2149IP_WAVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE" +Info: Elaborating entity "altpll3" for hierarchy "altpll3:inst13" +Info: Elaborating entity "altpll" for hierarchy "altpll3:inst13|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll3:inst13|altpll:altpll_component" +Info: Instantiated megafunction "altpll3:inst13|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "33" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "2" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "clk1_divide_by" = "33" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "16" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "33" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "25" + Info: Parameter "clk2_phase_shift" = "0" + Info: Parameter "clk3_divide_by" = "11" + Info: Parameter "clk3_duty_cycle" = "50" + Info: Parameter "clk3_multiply_by" = "16" + Info: Parameter "clk3_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK1" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_UNUSED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_USED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_41p2.tdf + Info: Found entity 1: altpll_41p2 +Info: Elaborating entity "altpll_41p2" for hierarchy "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated" +Info: Elaborating entity "Video" for hierarchy "Video:Fredi_Aschwanden" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ADR[31..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "MAIN_CLK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS1" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS2" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS3" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_WR" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE0" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE1" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nRSTO" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_OE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ALE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDRCLK[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDR_SYNC_66M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK33M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK25M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK_VIDEO" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_D[8..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_BUSY" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VG[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VB[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nBLANK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VA[12..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVWE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCAS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVRAS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDM[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nPD_VGA" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VCKE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "HSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_TA" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "PIXEL_CLK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "BA[1..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_RECONFIG" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_WR" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_RD" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDQS[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_AD[31..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VD[31..0]" +Info: Elaborating entity "VIDEO_MOD_MUX_CLUTCTR" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR" +Warning: Variable or input pin "nRSTO" is defined but never used +Warning: Variable or input pin "nFB_CS3" is defined but never used +Warning: Variable or input pin "nFB_BURST" is defined but never used +Info: Elaborating entity "lpm_bustri_WORD" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "BLITTER" for hierarchy "Video:Fredi_Aschwanden|BLITTER:BLITTER" +Info: Elaborating entity "lpm_shiftreg6" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "RIGHT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "DDR_CTR" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR" +Warning: Variable or input pin "nFB_CS2" is defined but never used +Warning: Variable or input pin "nFB_CS3" is defined but never used +Warning: Variable or input pin "nRSTO" is defined but never used +Info: Elaborating entity "lpm_bustri_BYT" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_fifo_dc0" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst" +Info: Elaborating entity "dcfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "512" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "128" + Info: Parameter "lpm_widthu" = "9" + Info: Parameter "overflow_checking" = "OFF" + Info: Parameter "rdsync_delaypipe" = "6" + Info: Parameter "underflow_checking" = "OFF" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "ON" + Info: Parameter "wrsync_delaypipe" = "6" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_8fi1.tdf + Info: Found entity 1: dcfifo_8fi1 +Info: Elaborating entity "dcfifo_8fi1" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf + Info: Found entity 1: a_gray2bin_tgb +Info: Elaborating entity "a_gray2bin_tgb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf + Info: Found entity 1: a_graycounter_s57 +Info: Elaborating entity "a_graycounter_s57" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf + Info: Found entity 1: a_graycounter_ojc +Info: Elaborating entity "a_graycounter_ojc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_njc.tdf + Info: Found entity 1: a_graycounter_njc +Info: Elaborating entity "a_graycounter_njc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tl31.tdf + Info: Found entity 1: altsyncram_tl31 +Info: Elaborating entity "altsyncram_tl31" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf + Info: Found entity 1: alt_synch_pipe_rld +Info: Elaborating entity "alt_synch_pipe_rld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf + Info: Found entity 1: dffpipe_qe9 +Info: Elaborating entity "dffpipe_qe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_9d9.tdf + Info: Found entity 1: dffpipe_9d9 +Info: Elaborating entity "dffpipe_9d9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf + Info: Found entity 1: dffpipe_oe9 +Info: Elaborating entity "dffpipe_oe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf + Info: Found entity 1: alt_synch_pipe_sld +Info: Elaborating entity "alt_synch_pipe_sld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf + Info: Found entity 1: dffpipe_re9 +Info: Elaborating entity "dffpipe_re9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22" +Info: Elaborating entity "lpm_shiftreg4" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "RIGHT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "lpm_muxVDM" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "128" + Info: Parameter "LPM_SIZE" = "16" + Info: Parameter "LPM_WIDTHS" = "4" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_bbe.tdf + Info: Found entity 1: mux_bbe +Info: Elaborating entity "mux_bbe" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component|mux_bbe:auto_generated" +Info: Elaborating entity "lpm_ff6" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "128" +Info: Elaborating entity "lpm_ff1" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "altddio_bidir0" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1" +Info: Elaborating entity "altddio_bidir" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "implement_input_in_lcell" = "ON" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_bidir" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "32" +Info: Found 1 design units, including 1 entities, in source file db/ddio_bidir_3jl.tdf + Info: Found entity 1: ddio_bidir_3jl +Info: Elaborating entity "ddio_bidir_3jl" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated" +Info: Elaborating entity "lpm_mux5" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "64" + Info: Parameter "LPM_SIZE" = "4" + Info: Parameter "LPM_WIDTHS" = "2" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_58e.tdf + Info: Found entity 1: mux_58e +Info: Elaborating entity "mux_58e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component|mux_58e:auto_generated" +Info: Elaborating entity "lpm_ff0" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_bustri_LONG" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_latch0" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27" +Info: Elaborating entity "lpm_latch" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_LATCH" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_bustri3" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "6" +Info: Elaborating entity "altdpram1" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "256" + Info: Parameter "numwords_b" = "256" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "8" + Info: Parameter "widthad_b" = "8" + Info: Parameter "width_a" = "6" + Info: Parameter "width_b" = "6" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lf92.tdf + Info: Found entity 1: altsyncram_lf92 +Info: Elaborating entity "altsyncram_lf92" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated" +Info: Elaborating entity "lpm_shiftreg0" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "LEFT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "MUX41" for hierarchy "Video:Fredi_Aschwanden|MUX41:inst45" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|MUX41:inst45" +Info: Elaborating entity "lpm_muxDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "128" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "1" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_dcf.tdf + Info: Found entity 1: mux_dcf +Info: Elaborating entity "mux_dcf" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component|mux_dcf:auto_generated" +Info: Elaborating entity "lpm_fifoDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63" +Info: Elaborating entity "scfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" with the following parameter: + Info: Parameter "add_ram_output_register" = "OFF" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "128" + Info: Parameter "lpm_showahead" = "ON" + Info: Parameter "lpm_type" = "scfifo" + Info: Parameter "lpm_width" = "128" + Info: Parameter "lpm_widthu" = "7" + Info: Parameter "overflow_checking" = "OFF" + Info: Parameter "underflow_checking" = "OFF" + Info: Parameter "use_eab" = "ON" +Info: Found 1 design units, including 1 entities, in source file db/scfifo_lk21.tdf + Info: Found entity 1: scfifo_lk21 +Info: Elaborating entity "scfifo_lk21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oq21.tdf + Info: Found entity 1: a_dpfifo_oq21 +Info: Elaborating entity "a_dpfifo_oq21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gj81.tdf + Info: Found entity 1: altsyncram_gj81 +Info: Elaborating entity "altsyncram_gj81" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_br8.tdf + Info: Found entity 1: cmpr_br8 +Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:almost_full_comparer" +Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:three_comparison" +Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf + Info: Found entity 1: cntr_omb +Info: Elaborating entity "cntr_omb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb" +Info: Found 1 design units, including 1 entities, in source file db/cntr_5n7.tdf + Info: Found entity 1: cntr_5n7 +Info: Elaborating entity "cntr_5n7" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter" +Info: Found 1 design units, including 1 entities, in source file db/cntr_pmb.tdf + Info: Found entity 1: cntr_pmb +Info: Elaborating entity "cntr_pmb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr" +Info: Elaborating entity "lpm_bustri1" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "3" +Info: Elaborating entity "altdpram0" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "16" + Info: Parameter "numwords_b" = "16" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "4" + Info: Parameter "widthad_b" = "4" + Info: Parameter "width_a" = "3" + Info: Parameter "width_b" = "3" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rb92.tdf + Info: Found entity 1: altsyncram_rb92 +Info: Elaborating entity "altsyncram_rb92" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated" +Info: Elaborating entity "altdpram2" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "256" + Info: Parameter "numwords_b" = "256" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "8" + Info: Parameter "widthad_b" = "8" + Info: Parameter "width_a" = "8" + Info: Parameter "width_b" = "8" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pf92.tdf + Info: Found entity 1: altsyncram_pf92 +Info: Elaborating entity "altsyncram_pf92" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated" +Info: Elaborating entity "lpm_mux3" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "1" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_96e.tdf + Info: Found entity 1: mux_96e +Info: Elaborating entity "mux_96e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component|mux_96e:auto_generated" +Info: Elaborating entity "lpm_ff5" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_mux2" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" + Info: Parameter "LPM_SIZE" = "16" + Info: Parameter "LPM_WIDTHS" = "4" + Info: Parameter "LPM_PIPELINE" = "2" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_mpe.tdf + Info: Found entity 1: mux_mpe +Info: Elaborating entity "mux_mpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component|mux_mpe:auto_generated" +Info: Elaborating entity "lpm_mux4" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "7" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_f6e.tdf + Info: Found entity 1: mux_f6e +Info: Elaborating entity "mux_f6e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component|mux_f6e:auto_generated" +Info: Elaborating entity "lpm_constant3" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "7" +Info: Elaborating entity "altddio_out2" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5" +Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "24" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_o2f.tdf + Info: Found entity 1: ddio_out_o2f +Info: Elaborating entity "ddio_out_o2f" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated" +Info: Elaborating entity "lpm_mux6" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "24" + Info: Parameter "LPM_SIZE" = "8" + Info: Parameter "LPM_WIDTHS" = "3" + Info: Parameter "LPM_PIPELINE" = "2" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_kpe.tdf + Info: Found entity 1: mux_kpe +Info: Elaborating entity "mux_kpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component|mux_kpe:auto_generated" +Info: Elaborating entity "lpm_ff3" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "24" +Info: Elaborating entity "lpm_constant0" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "lpm_constant1" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "2" +Info: Elaborating entity "lpm_ff4" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "lpm_mux1" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" +Info: Assertion information: Value of LPM_PIPELINE parameter (4) should be lower -- use 1 for best performance/utilization +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "16" + Info: Parameter "LPM_SIZE" = "8" + Info: Parameter "LPM_WIDTHS" = "3" + Info: Parameter "LPM_PIPELINE" = "4" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Assertion information: Value of LPM_PIPELINE parameter 4 should be lower -- use 1 for best performance/utilization +Info: Found 1 design units, including 1 entities, in source file db/mux_npe.tdf + Info: Found entity 1: mux_npe +Info: Elaborating entity "mux_npe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component|mux_npe:auto_generated" +Info: Elaborating entity "lpm_constant2" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_mux0" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "32" + Info: Parameter "LPM_SIZE" = "4" + Info: Parameter "LPM_WIDTHS" = "2" + Info: Parameter "LPM_PIPELINE" = "4" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_gpe.tdf + Info: Found entity 1: mux_gpe +Info: Elaborating entity "mux_gpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component|mux_gpe:auto_generated" +Info: Elaborating entity "altddio_out0" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2" +Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "ON" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "ON" + Info: Parameter "width" = "4" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_are.tdf + Info: Found entity 1: ddio_out_are +Info: Elaborating entity "ddio_out_are" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated" +Info: Elaborating entity "altpll2" for hierarchy "altpll2:inst12" +Info: Elaborating entity "altpll" for hierarchy "altpll2:inst12|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll2:inst12|altpll:altpll_component" +Info: Instantiated megafunction "altpll2:inst12|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "1" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "4" + Info: Parameter "clk0_phase_shift" = "5051" + Info: Parameter "clk1_divide_by" = "1" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "4" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "1" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "4" + Info: Parameter "clk2_phase_shift" = "3788" + Info: Parameter "clk3_divide_by" = "1" + Info: Parameter "clk3_duty_cycle" = "50" + Info: Parameter "clk3_multiply_by" = "4" + Info: Parameter "clk3_phase_shift" = "2210" + Info: Parameter "clk4_divide_by" = "1" + Info: Parameter "clk4_duty_cycle" = "50" + Info: Parameter "clk4_multiply_by" = "2" + Info: Parameter "clk4_phase_shift" = "11364" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_UNUSED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_USED" + Info: Parameter "port_clk4" = "PORT_USED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_isv2.tdf + Info: Found entity 1: altpll_isv2 +Info: Elaborating entity "altpll_isv2" for hierarchy "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated" +Warning: Using design file altpll4.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll4 +Info: Elaborating entity "altpll4" for hierarchy "altpll4:inst22" +Info: Elaborating entity "altpll" for hierarchy "altpll4:inst22|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll4:inst22|altpll:altpll_component" +Info: Instantiated megafunction "altpll4:inst22|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "1" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "2" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "20833" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "NORMAL" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_USED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_UNUSED" + Info: Parameter "port_clk2" = "PORT_UNUSED" + Info: Parameter "port_clk3" = "PORT_UNUSED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_USED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_USED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_USED" + Info: Parameter "port_scanclkena" = "PORT_USED" + Info: Parameter "port_scandata" = "PORT_USED" + Info: Parameter "port_scandataout" = "PORT_USED" + Info: Parameter "port_scandone" = "PORT_USED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "scan_chain_mif_file" = "altpll4.mif" + Info: Parameter "self_reset_on_loss_lock" = "OFF" + Info: Parameter "width_clock" = "5" + Info: Parameter "width_phasecounterselect" = "4" +Info: Found 1 design units, including 1 entities, in source file db/altpll_c6j2.tdf + Info: Found entity 1: altpll_c6j2 +Info: Elaborating entity "altpll_c6j2" for hierarchy "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated" +Warning: Using design file altpll_reconfig1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll_reconfig1 +Info: Elaborating entity "altpll_reconfig1" for hierarchy "altpll_reconfig1:inst7" +Warning: Using design file altpll_reconfig1_pllrcfg_t4q.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll_reconfig1_pllrcfg_t4q +Info: Elaborating entity "altpll_reconfig1_pllrcfg_t4q" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component" +Info: Elaborating entity "altsyncram" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" with the following parameter: + Info: Parameter "OPERATION_MODE" = "SINGLE_PORT" + Info: Parameter "WIDTH_A" = "1" + Info: Parameter "WIDTHAD_A" = "8" + Info: Parameter "NUMWORDS_A" = "144" + Info: Parameter "WIDTH_BYTEENA_A" = "1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46r.tdf + Info: Found entity 1: altsyncram_46r +Info: Elaborating entity "altsyncram_46r" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated" +Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" with the following parameter: + Info: Parameter "LPM_WIDTH" = "9" +Info: Found 1 design units, including 1 entities, in source file db/add_sub_hpa.tdf + Info: Found entity 1: add_sub_hpa +Info: Elaborating entity "add_sub_hpa" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5|add_sub_hpa:auto_generated" +Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/add_sub_k8a.tdf + Info: Found entity 1: add_sub_k8a +Info: Elaborating entity "add_sub_k8a" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6|add_sub_k8a:auto_generated" +Info: Elaborating entity "lpm_compare" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_tnd.tdf + Info: Found entity 1: cmpr_tnd +Info: Elaborating entity "cmpr_tnd" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_modulus" = "144" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cntr_30l.tdf + Info: Found entity 1: cntr_30l +Info: Elaborating entity "cntr_30l" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "6" +Info: Found 1 design units, including 1 entities, in source file db/cntr_qij.tdf + Info: Found entity 1: cntr_qij +Info: Elaborating entity "cntr_qij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "5" +Info: Found 1 design units, including 1 entities, in source file db/cntr_pij.tdf + Info: Found entity 1: cntr_pij +Info: Elaborating entity "cntr_pij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "UP" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cntr_9cj.tdf + Info: Found entity 1: cntr_9cj +Info: Elaborating entity "cntr_9cj" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated" +Info: Elaborating entity "lpm_decode" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" with the following parameter: + Info: Parameter "LPM_DECODES" = "5" + Info: Parameter "LPM_WIDTH" = "3" +Info: Found 1 design units, including 1 entities, in source file db/decode_2af.tdf + Info: Found entity 1: decode_2af +Info: Elaborating entity "decode_2af" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11|decode_2af:auto_generated" +Info: Elaborating entity "DSP" for hierarchy "DSP:Mathias_Alles" +Info: Elaborating entity "interrupt_handler" for hierarchy "interrupt_handler:nobody" +Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst18" +Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component" +Info: Elaborated megafunction instantiation "lpm_counter0:inst18|lpm_counter:lpm_counter_component" +Info: Instantiated megafunction "lpm_counter0:inst18|lpm_counter:lpm_counter_component" with the following parameter: + Info: Parameter "lpm_direction" = "UP" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "lpm_type" = "LPM_COUNTER" + Info: Parameter "lpm_width" = "18" +Info: Found 1 design units, including 1 entities, in source file db/cntr_mph.tdf + Info: Found entity 1: cntr_mph +Info: Elaborating entity "cntr_mph" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated" +Info: Elaborating entity "altddio_out3" for hierarchy "altddio_out3:inst5" +Info: Elaborating entity "altddio_out" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "altddio_out3:inst5|altddio_out:altddio_out_component" +Info: Instantiated megafunction "altddio_out3:inst5|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "1" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_31f.tdf + Info: Found entity 1: ddio_out_31f +Info: Elaborating entity "ddio_out_31f" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated" +Warning: Timing-Driven Synthesis is skipped because the Classic Timing Analyzer is turned on +Info: Inferred 3 megafunctions from design logic + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_14" + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_6" + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_12" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" with the following parameter: + Info: Parameter "LPM_WIDTHA" = "12" + Info: Parameter "LPM_WIDTHB" = "6" + Info: Parameter "LPM_WIDTHP" = "18" + Info: Parameter "LPM_WIDTHR" = "18" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" + Info: Parameter "MAXIMIZE_SPEED" = "5" +Info: Found 1 design units, including 1 entities, in source file db/mult_cat.tdf + Info: Found entity 1: mult_cat +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" with the following parameter: + Info: Parameter "LPM_WIDTHA" = "12" + Info: Parameter "LPM_WIDTHB" = "5" + Info: Parameter "LPM_WIDTHP" = "17" + Info: Parameter "LPM_WIDTHR" = "17" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" + Info: Parameter "MAXIMIZE_SPEED" = "5" +Info: Found 1 design units, including 1 entities, in source file db/mult_aat.tdf + Info: Found entity 1: mult_aat +Warning: The following nodes have both tri-state and non-tri-state drivers + Warning: Inserted always-enabled tri-state buffer between "IO[17]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[16]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[15]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[14]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[13]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[12]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[11]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[10]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[9]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[8]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[7]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[6]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[5]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[4]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[3]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[2]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[1]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[0]" and its non-tri-state driver. +Info: Registers with preset signals will power-up high +Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning: TRI or OPNDRN buffers permanently disabled + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_PAR~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_RST~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[7]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[6]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[5]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[4]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[3]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[2]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[1]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[0]~synth" +Warning: TRI or OPNDRN buffers permanently enabled + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_SEL~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_BUSY~synth" +Warning: Output pins are stuck at VCC or GND + Warning (13410): Pin "nACSI_ACK" is stuck at VCC + Warning (13410): Pin "nACSI_CS" is stuck at VCC + Warning (13410): Pin "ACSI_DIR" is stuck at GND + Warning (13410): Pin "nSCSI_ACK" is stuck at VCC + Warning (13410): Pin "nSCSI_ATN" is stuck at VCC + Warning (13410): Pin "SCSI_DIR" is stuck at VCC + Warning (13410): Pin "nSYNC" is stuck at GND +Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below. + Info: Register "interrupt_handler:nobody|INT_CLEAR[31]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[30]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[29]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[28]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[27]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[26]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[25]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[24]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[23]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[22]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[21]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[20]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[19]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[18]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[17]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[16]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[15]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[14]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[13]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[12]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[11]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[10]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[6]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[5]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[4]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[3]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[2]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[1]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[5]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[4]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[6]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[5]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[4]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]" lost all its fanouts during netlist optimizations. +Info: Found the following redundant logic cells in design + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[0]" + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[1]" + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[2]" +Warning: Design contains 18 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "nFB_BURST" + Warning (15610): No output dependent on input pin "nACSI_DRQ" + Warning (15610): No output dependent on input pin "nACSI_INT" + Warning (15610): No output dependent on input pin "nSCSI_DRQ" + Warning (15610): No output dependent on input pin "nSCSI_MSG" + Warning (15610): No output dependent on input pin "nDCHG" + Warning (15610): No output dependent on input pin "SD_DATA0" + Warning (15610): No output dependent on input pin "SD_DATA1" + Warning (15610): No output dependent on input pin "SD_DATA2" + Warning (15610): No output dependent on input pin "SD_CARD_DEDECT" + Warning (15610): No output dependent on input pin "SD_WP" + Warning (15610): No output dependent on input pin "nDACK0" + Warning (15610): No output dependent on input pin "WP_CF_CARD" + Warning (15610): No output dependent on input pin "nSCSI_C_D" + Warning (15610): No output dependent on input pin "nSCSI_I_O" + Warning (15610): No output dependent on input pin "nFB_CS3" + Warning (15610): No output dependent on input pin "TOUT0" + Warning (15610): No output dependent on input pin "nMASTER" +Info: Implemented 11489 device resources after synthesis - the final resource count might be different + Info: Implemented 51 input pins + Info: Implemented 112 output pins + Info: Implemented 132 bidirectional pins + Info: Implemented 10796 logic cells + Info: Implemented 324 RAM segments + Info: Implemented 4 PLLs + Info: Implemented 6 DSP elements +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 143 warnings + Info: Peak virtual memory: 347 megabytes + Info: Processing ended: Wed Dec 15 02:21:56 2010 + Info: Elapsed time: 00:01:19 + Info: Total CPU time (on all processors): 00:01:20 + + diff --git a/FPGA_quartus/firebee1.map.summary b/FPGA_quartus/firebee1.map.summary new file mode 100644 index 0000000..f8da91e --- /dev/null +++ b/FPGA_quartus/firebee1.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : firebee1 +Top-level Entity Name : firebee1 +Family : Cyclone III +Total logic elements : 10,706 + Total combinational functions : 8,060 + Dedicated logic registers : 4,612 +Total registers : 4740 +Total pins : 295 +Total virtual pins : 0 +Total memory bits : 109,344 +Embedded Multiplier 9-bit elements : 6 +Total PLLs : 4 diff --git a/FPGA_quartus/firebee1.pin b/FPGA_quartus/firebee1.pin new file mode 100644 index 0000000..50b8dd7 --- /dev/null +++ b/FPGA_quartus/firebee1.pin @@ -0,0 +1,557 @@ + -- Copyright (C) 1991-2010 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 3.0V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +CHIP "firebee1" ASSIGNED TO AN: EP3C40F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 3.3V : 8 : +LP_D[6] : A3 : bidir : 3.3-V LVTTL : : 8 : Y +nSRBLE : A4 : output : 3.3-V LVTTL : : 8 : Y +SRD[1] : A5 : bidir : 3.3-V LVTTL : : 8 : Y +IO[3] : A6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[1] : A7 : bidir : 3.3-V LVTTL : : 8 : Y +IO[0] : A8 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[10] : A9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[9] : A10 : bidir : 3.3-V LVTTL : : 8 : Y +DVI_INT : A11 : input : 3.3-V LVTTL : : 8 : Y +nDACK1 : A12 : input : 3.3-V LVTTL : : 7 : Y +IO[16] : A13 : bidir : 3.3-V LVTTL : : 7 : Y +IO[14] : A14 : bidir : 3.3-V LVTTL : : 7 : Y +IO[9] : A15 : bidir : 3.3-V LVTTL : : 7 : Y +SD_DATA1 : A16 : input : 3.3-V LVTTL : : 7 : Y +YM_QA : A17 : output : 3.3-V LVTTL : : 7 : Y +TxD : A18 : output : 3.3-V LVTTL : : 7 : Y +DCD : A19 : input : 3.3-V LVTTL : : 7 : Y +nRD_DATA : A20 : input : 3.3-V LVTTL : : 7 : Y +VCCIO7 : A21 : power : : 3.3V : 7 : +GND : A22 : gnd : : : : +nPCI_INTA : AA1 : input : 3.3-V LVTTL : : 2 : Y +PIC_INT : AA2 : input : 3.3-V LVTTL : : 2 : Y +FB_AD[2] : AA3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[6] : AA4 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[8] : AA5 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AA6 : power : : 3.3V : 3 : +FB_AD[15] : AA7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[22] : AA8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[25] : AA9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[31] : AA10 : bidir : 3.3-V LVTTL : : 3 : Y +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +VD[18] : AA13 : bidir : 2.5 V : : 4 : Y +VD[25] : AA14 : bidir : 2.5 V : : 4 : Y +VDQS[0] : AA15 : bidir : 2.5 V : : 4 : Y +VDM[0] : AA16 : output : 2.5 V : : 4 : Y +nDDR_CLK : AA17 : output : 2.5 V : : 4 : Y +VA[12] : AA18 : output : 2.5 V : : 4 : Y +BA[1] : AA19 : output : 2.5 V : : 4 : Y +VA[7] : AA20 : output : 2.5 V : : 4 : Y +VA[6] : AA21 : output : 2.5 V : : 5 : Y +VA[4] : AA22 : output : 2.5 V : : 5 : Y +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 3.3V : 3 : +FB_AD[3] : AB3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[7] : AB4 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[9] : AB5 : bidir : 3.3-V LVTTL : : 3 : Y +GND : AB6 : gnd : : : : +FB_AD[16] : AB7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[23] : AB8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[26] : AB9 : bidir : 3.3-V LVTTL : : 3 : Y +CLK24M576 : AB10 : output : 3.3-V LVTTL : : 3 : Y +GND+ : AB11 : : : : 3 : +CLK33M : AB12 : input : 3.3-V LVTTL : : 4 : Y +VD[29] : AB13 : bidir : 2.5 V : : 4 : Y +VD[26] : AB14 : bidir : 2.5 V : : 4 : Y +VD[24] : AB15 : bidir : 2.5 V : : 4 : Y +VD[23] : AB16 : bidir : 2.5 V : : 4 : Y +DDR_CLK : AB17 : output : 2.5 V : : 4 : Y +nVCAS : AB18 : output : 2.5 V : : 4 : Y +VA[9] : AB19 : output : 2.5 V : : 4 : Y +VA[8] : AB20 : output : 2.5 V : : 4 : Y +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +ACSI_D[0] : B1 : bidir : 3.3-V LVTTL : : 1 : Y +MIDI_TLR : B2 : output : 3.3-V LVTTL : : 1 : Y +LP_D[5] : B3 : bidir : 3.3-V LVTTL : : 8 : Y +nSRBHE : B4 : output : 3.3-V LVTTL : : 8 : Y +SRD[0] : B5 : bidir : 3.3-V LVTTL : : 8 : Y +IO[4] : B6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[2] : B7 : bidir : 3.3-V LVTTL : : 8 : Y +nSRCS : B8 : output : 3.3-V LVTTL : : 8 : Y +SRD[8] : B9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[11] : B10 : bidir : 3.3-V LVTTL : : 8 : Y +nRSTO_MCF : B11 : input : 3.3-V LVTTL : : 8 : Y +nDACK0 : B12 : input : 3.3-V LVTTL : : 7 : Y +IO[17] : B13 : bidir : 3.3-V LVTTL : : 7 : Y +IO[15] : B14 : bidir : 3.3-V LVTTL : : 7 : Y +IO[10] : B15 : bidir : 3.3-V LVTTL : : 7 : Y +SD_DATA0 : B16 : input : 3.3-V LVTTL : : 7 : Y +SD_DATA2 : B17 : input : 3.3-V LVTTL : : 7 : Y +RTS : B18 : output : 3.3-V LVTTL : : 7 : Y +RI : B19 : input : 3.3-V LVTTL : : 7 : Y +nSDSEL : B20 : output : 3.3-V LVTTL : : 7 : Y +VB[5] : B21 : output : 3.0-V LVTTL : : 6 : Y +VB[4] : B22 : output : 3.0-V LVTTL : : 6 : Y +ACSI_D[4] : C1 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[3] : C2 : bidir : 3.3-V LVTTL : : 1 : Y +LP_D[2] : C3 : bidir : 3.3-V LVTTL : : 8 : Y +LP_D[1] : C4 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C5 : gnd : : : : +SRD[2] : C6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[7] : C7 : bidir : 3.3-V LVTTL : : 8 : Y +IO[6] : C8 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C9 : gnd : : : : +SRD[4] : C10 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +IO[11] : C13 : bidir : 3.3-V LVTTL : : 7 : Y +GND : C14 : gnd : : : : +SD_CLK : C15 : output : 3.3-V LVTTL : : 7 : Y +GND : C16 : gnd : : : : +nDCHG : C17 : input : 3.3-V LVTTL : : 7 : Y +GND : C18 : gnd : : : : +TRACK00 : C19 : input : 3.3-V LVTTL : : 7 : Y +VB[6] : C20 : output : 3.0-V LVTTL : : 6 : Y +VB[3] : C21 : output : 3.0-V LVTTL : : 6 : Y +VB[2] : C22 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1 : input : 3.3-V LVTTL : : 1 : N +ACSI_D[5] : D2 : bidir : 3.3-V LVTTL : : 1 : Y +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 3.3V : 1 : +VCCIO8 : D5 : power : : 3.3V : 8 : +LP_D[4] : D6 : bidir : 3.3-V LVTTL : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 3.3V : 8 : +SRD[12] : D10 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : D11 : power : : 3.3V : 8 : +VCCIO7 : D12 : power : : 3.3V : 7 : +IO[12] : D13 : bidir : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D14 : power : : 3.3V : 7 : +DTR : D15 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D16 : power : : 3.3V : 7 : +nWR_GATE : D17 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D18 : power : : 3.3V : 7 : +nWP : D19 : input : 3.3-V LVTTL : : 7 : Y +VB[7] : D20 : output : 3.0-V LVTTL : : 6 : Y +VG[7] : D21 : output : 3.0-V LVTTL : : 6 : Y +VG[6] : D22 : output : 3.0-V LVTTL : : 6 : Y +SCSI_D[1] : E1 : bidir : 3.3-V LVTTL : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2 : input : 3.3-V LVTTL : : 1 : N +ACSI_D[2] : E3 : bidir : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1 : +LPDIR : E5 : output : 3.3-V LVTTL : : 8 : Y +LP_STR : E6 : output : 3.3-V LVTTL : : 8 : Y +LP_D[3] : E7 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : E8 : power : : 3.3V : 8 : +IO[5] : E9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[6] : E10 : bidir : 3.3-V LVTTL : : 8 : Y +nDREQ1 : E11 : output : 3.3-V LVTTL : : 7 : Y +MIDI_IN : E12 : input : 3.3-V LVTTL : : 7 : Y +IO[13] : E13 : bidir : 3.3-V LVTTL : : 7 : Y +SD_CMD_D1 : E14 : bidir : 3.3-V LVTTL : : 7 : Y +YM_QC : E15 : output : 3.3-V LVTTL : : 7 : Y +nINDEX : E16 : input : 3.3-V LVTTL : : 7 : Y +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 3.0V : 6 : +GND : E20 : gnd : : : : +VG[2] : E21 : output : 3.0-V LVTTL : : 6 : Y +VG[1] : E22 : output : 3.0-V LVTTL : : 6 : Y +SCSI_D[3] : F1 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_D[2] : F2 : bidir : 3.3-V LVTTL : : 1 : Y +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 3.3V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +LP_D[0] : F7 : bidir : 3.3-V LVTTL : : 8 : Y +nSRWE : F8 : output : 3.3-V LVTTL : : 8 : Y +SRD[5] : F9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[13] : F10 : bidir : 3.3-V LVTTL : : 8 : Y +nSROE : F11 : output : 3.3-V LVTTL : : 7 : Y +GND : F12 : gnd : : : : +SD_CD_DATA3 : F13 : bidir : 3.3-V LVTTL : : 7 : Y +nSTEP : F14 : output : 3.3-V LVTTL : : 7 : Y +DSA_D : F15 : output : 3.3-V LVTTL : : 7 : Y +HD_DD : F16 : input : 3.3-V LVTTL : : 7 : Y +nSYNC : F17 : output : 3.0-V LVCMOS : : 6 : Y +VCCA2 : F18 : power : : 2.5V : : +PIXEL_CLK_PAD : F19 : output : 3.0-V LVTTL : : 6 : Y +nIRQ[4] : F20 : output : 3.0-V LVCMOS : : 6 : Y +nIRQ[2] : F21 : output : 3.0-V LVCMOS : : 6 : Y +VR[7] : F22 : output : 3.0-V LVTTL : : 6 : Y +GND+ : G1 : : : : 1 : +MAIN_CLK : G2 : input : 3.3-V LVTTL : : 1 : Y +SCSI_D[5] : G3 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_D[4] : G4 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[1] : G5 : bidir : 3.3-V LVTTL : : 1 : Y +VCCA3 : G6 : power : : 2.5V : : +LP_BUSY : G7 : input : 3.3-V LVTTL : : 8 : Y +LP_D[7] : G8 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[14] : G9 : bidir : 3.3-V LVTTL : : 8 : Y +IO[8] : G10 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[3] : G11 : bidir : 3.3-V LVTTL : : 8 : Y +VCCINT : G12 : power : : 1.2V : : +YM_QB : G13 : output : 3.3-V LVTTL : : 7 : Y +nWR : G14 : output : 3.3-V LVTTL : : 7 : Y +nSTEP_DIR : G15 : output : 3.3-V LVTTL : : 7 : Y +nMOT_ON : G16 : output : 3.3-V LVTTL : : 7 : Y +nBLANK_PAD : G17 : output : 3.0-V LVTTL : : 6 : Y +VB[0] : G18 : output : 3.0-V LVTTL : : 6 : Y +VCCIO6 : G19 : power : : 3.0V : 6 : +GND : G20 : gnd : : : : +E0_INT : G21 : input : 3.3-V LVTTL : : 6 : Y +IDE_INT : G22 : input : 3.3-V LVTTL : : 6 : Y +nSCSI_C_D : H1 : input : 3.3-V LVTTL : : 1 : Y +nSCSI_MSG : H2 : input : 3.3-V LVTTL : : 1 : Y +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 3.3V : 1 : +MIDI_OLR : H5 : output : 3.3-V LVTTL : : 1 : Y +ACSI_D[7] : H6 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[6] : H7 : bidir : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 1 : +VCCINT : H9 : power : : 1.2V : : +SRD[15] : H10 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[7] : H11 : bidir : 3.3-V LVTTL : : 8 : Y +GND : H12 : gnd : : : : +GND : H13 : gnd : : : : +CTS : H14 : input : 3.3-V LVTTL : : 7 : Y +RxD : H15 : input : 3.3-V LVTTL : : 7 : Y +VG[5] : H16 : output : 3.0-V LVTTL : : 6 : Y +VB[1] : H17 : output : 3.0-V LVTTL : : 6 : Y +VG[3] : H18 : output : 3.0-V LVTTL : : 6 : Y +VG[0] : H19 : output : 3.0-V LVTTL : : 6 : Y +nIRQ[3] : H20 : output : 3.0-V LVCMOS : : 6 : Y +VR[3] : H21 : output : 3.0-V LVTTL : : 6 : Y +VR[2] : H22 : output : 3.0-V LVTTL : : 6 : Y +CLKUSB : J1 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : +nSCSI_I_O : J3 : input : 3.3-V LVTTL : : 1 : Y +nACSI_INT : J4 : input : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : +SCSI_D[0] : J6 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_DIR : J7 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1 : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +GND : J15 : gnd : : : : +VCCINT : J16 : power : : 1.2V : : +VG[4] : J17 : output : 3.0-V LVTTL : : 6 : Y +VR[6] : J18 : output : 3.0-V LVTTL : : 6 : Y +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 3.0V : 6 : +VR[1] : J21 : output : 3.0-V LVTTL : : 6 : Y +VR[0] : J22 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_DATA0~ / RESERVED_INPUT : K1 : input : 3.3-V LVTTL : : 1 : N +~ALTERA_DCLK~ / RESERVED_INPUT : K2 : input : 3.3-V LVTTL : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 3.3V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +nACSI_DRQ : K7 : input : 3.3-V LVTTL : : 1 : Y +SCSI_D[7] : K8 : bidir : 3.3-V LVTTL : : 1 : Y +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +VCCINT : K15 : power : : 1.2V : : +GND : K16 : gnd : : : : +VR[4] : K17 : output : 3.0-V LVTTL : : 6 : Y +VR[5] : K18 : output : 3.0-V LVTTL : : 6 : Y +VSYNC_PAD : K19 : output : 3.0-V LVTTL : : 6 : Y +MSEL3 : K20 : : : : 6 : +HSYNC_PAD : K21 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 3.0-V LVTTL : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +ACSI_DIR : L6 : output : 3.3-V LVTTL : : 2 : Y +PIC_AMKB_RX : L7 : input : 3.3-V LVTTL : : 2 : Y +SCSI_D[6] : L8 : bidir : 3.3-V LVTTL : : 1 : Y +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.2V : : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 3.0V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +nACSI_RESET : M1 : output : 3.3-V LVTTL : : 2 : Y +nACSI_CS : M2 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_ATN : M3 : output : 3.3-V LVTTL : : 2 : Y +nACSI_ACK : M4 : output : 3.3-V LVTTL : : 2 : Y +IDE_RES : M5 : output : 3.3-V LVTTL : : 2 : Y +ACSI_A1 : M6 : output : 3.3-V LVTTL : : 2 : Y +SCSI_PAR : M7 : bidir : 3.3-V LVTTL : : 2 : Y +nSCSI_SEL : M8 : bidir : 3.3-V LVTTL : : 2 : Y +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +VCCINT : M15 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +SD_WP : M19 : input : 3.3-V LVTTL : : 5 : Y +SD_CARD_DEDECT : M20 : input : 3.3-V LVTTL : : 5 : Y +VD[1] : M21 : bidir : 2.5 V : : 5 : Y +VD[0] : M22 : bidir : 2.5 V : : 5 : Y +AMKB_TX : N1 : output : 3.3-V LVCMOS : : 2 : Y +nSCSI_ACK : N2 : output : 3.3-V LVTTL : : 2 : Y +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 3.3V : 2 : +nRP_LDS : N5 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_RST : N6 : bidir : 3.3-V LVTTL : : 2 : Y +nIRQ[7] : N7 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_BUSY : N8 : bidir : 3.3-V LVTTL : : 2 : Y +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND : N15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +VD[12] : N17 : bidir : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +LED_FPGA_OK : N19 : output : 2.5 V : : 5 : Y +VD[15] : N20 : bidir : 2.5 V : : 5 : Y +~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21 : input : 2.5 V : : 5 : N +~ALTERA_DEV_OE~ / RESERVED_INPUT : N22 : input : 2.5 V : : 5 : N +nIDE_RD : P1 : output : 3.3-V LVTTL : : 2 : Y +nIDE_WR : P2 : output : 3.3-V LVTTL : : 2 : Y +nROM3 : P3 : output : 3.3-V LVTTL : : 2 : Y +nRP_UDS : P4 : output : 3.3-V LVTTL : : 2 : Y +nIRQ[5] : P5 : output : 3.3-V LVTTL : : 2 : Y +nPCI_INTD : P6 : input : 3.3-V LVTTL : : 2 : Y +nIRQ[6] : P7 : output : 3.3-V LVTTL : : 2 : Y +GND : P8 : gnd : : : : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +VCCINT : P14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +VD[10] : P17 : bidir : 2.5 V : : 5 : Y +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +VD[13] : P20 : bidir : 2.5 V : : 5 : Y +VD[4] : P21 : bidir : 2.5 V : : 5 : Y +VD[2] : P22 : bidir : 2.5 V : : 5 : Y +nIDE_CS1 : R1 : output : 3.3-V LVTTL : : 2 : Y +nIDE_CS0 : R2 : output : 3.3-V LVTTL : : 2 : Y +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 3.3V : 2 : +TIN0 : R5 : output : 3.3-V LVTTL : : 2 : Y +nFB_OE : R6 : input : 3.3-V LVTTL : : 2 : Y +FB_ALE : R7 : input : 3.3-V LVTTL : : 2 : Y +VCCINT : R8 : power : : 1.2V : : +GND : R9 : gnd : : : : +VCCINT : R10 : power : : 1.2V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.2V : : +GND : R13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +VD[5] : R17 : bidir : 2.5 V : : 5 : Y +VD[9] : R18 : bidir : 2.5 V : : 5 : Y +VD[6] : R19 : bidir : 2.5 V : : 5 : Y +VD[3] : R20 : bidir : 2.5 V : : 5 : Y +VD[11] : R21 : bidir : 2.5 V : : 5 : Y +VD[14] : R22 : bidir : 2.5 V : : 5 : Y +WP_CF_CARD : T1 : input : 3.3-V LVTTL : : 2 : Y +GND+ : T2 : : : : 2 : +nFB_BURST : T3 : input : 3.3-V LVTTL : : 2 : Y +CLK25M : T4 : output : 3.3-V LVTTL : : 2 : Y +nFB_WR : T5 : input : 3.3-V LVTTL : : 2 : Y +VCCA1 : T6 : power : : 2.5V : : +nFB_TA : T7 : output : 3.3-V LVTTL : : 2 : Y +nFB_CS1 : T8 : input : 3.3-V LVTTL : : 3 : Y +nFB_CS2 : T9 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[20] : T10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[24] : T11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[16] : T12 : bidir : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VDQS[3] : T16 : bidir : 2.5 V : : 4 : Y +VDM[3] : T17 : output : 2.5 V : : 5 : Y +nVCS : T18 : output : 2.5 V : : 5 : Y +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +nMASTER : T21 : input : 3.3-V LVTTL : : 5 : Y +TOUT0 : T22 : input : 3.3-V LVTTL : : 5 : Y +nSCSI_DRQ : U1 : input : 3.3-V LVTTL : : 2 : Y +nROM4 : U2 : output : 3.3-V LVTTL : : 2 : Y +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 3.3V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +FB_SIZE0 : U8 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[12] : U9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[21] : U10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[27] : U11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[31] : U12 : bidir : 2.5 V : : 4 : Y +VD[20] : U13 : bidir : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +VCKE : U15 : output : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4 : +VCCA4 : U18 : power : : 2.5V : : +VA[11] : U19 : output : 2.5 V : : 5 : Y +VDM[2] : U20 : output : 2.5 V : : 5 : Y +VD[7] : U21 : bidir : 2.5 V : : 5 : Y +VDQS[2] : U22 : bidir : 2.5 V : : 5 : Y +nPD_VGA : V1 : output : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +nPCI_INTC : V3 : input : 3.3-V LVTTL : : 2 : Y +nPCI_INTB : V4 : input : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +nFB_CS3 : V6 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[5] : V7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[13] : V8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[18] : V9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[19] : V10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[28] : V11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[30] : V12 : bidir : 2.5 V : : 4 : Y +VD[27] : V13 : bidir : 2.5 V : : 4 : Y +VD[19] : V14 : bidir : 2.5 V : : 4 : Y +VD[21] : V15 : bidir : 2.5 V : : 4 : Y +VDM[1] : V16 : output : 2.5 V : : 4 : Y +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +VA[10] : V21 : output : 2.5 V : : 5 : Y +VD[8] : V22 : bidir : 2.5 V : : 5 : Y +nCF_CS1 : W1 : output : 3.3-V LVTTL : : 2 : Y +nCF_CS0 : W2 : output : 3.3-V LVTTL : : 2 : Y +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 3.3V : 2 : +VCCIO3 : W5 : power : : 3.3V : 3 : +FB_AD[4] : W6 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[10] : W7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[14] : W8 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : W9 : power : : 3.3V : 3 : +FB_AD[29] : W10 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : W11 : power : : 3.3V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +VD[28] : W13 : bidir : 2.5 V : : 4 : Y +VD[22] : W14 : bidir : 2.5 V : : 4 : Y +VDQS[1] : W15 : bidir : 2.5 V : : 4 : Y +VCCIO4 : W16 : power : : 2.5V : 4 : +nVRAS : W17 : output : 2.5 V : : 4 : Y +VCCIO4 : W18 : power : : 2.5V : 4 : +BA[0] : W19 : output : 2.5 V : : 5 : Y +VA[0] : W20 : output : 2.5 V : : 5 : Y +VA[2] : W21 : output : 2.5 V : : 5 : Y +VA[1] : W22 : output : 2.5 V : : 5 : Y +IDE_RDY : Y1 : input : 3.3-V LVTTL : : 2 : Y +AMKB_RX : Y2 : input : 3.3-V LVTTL : : 2 : Y +FB_AD[0] : Y3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_SIZE1 : Y4 : input : 3.3-V LVTTL : : 3 : Y +GND : Y5 : gnd : : : : +FB_AD[1] : Y6 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[11] : Y7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[17] : Y8 : bidir : 3.3-V LVTTL : : 3 : Y +GND : Y9 : gnd : : : : +FB_AD[30] : Y10 : bidir : 3.3-V LVTTL : : 3 : Y +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +VD[17] : Y13 : bidir : 2.5 V : : 4 : Y +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +nVWE : Y17 : output : 2.5 V : : 4 : Y +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +VA[5] : Y21 : output : 2.5 V : : 5 : Y +VA[3] : Y22 : output : 2.5 V : : 5 : Y diff --git a/FPGA_quartus/firebee1.qsf b/FPGA_quartus/firebee1.qsf new file mode 100644 index 0000000..86e8842 --- /dev/null +++ b/FPGA_quartus/firebee1.qsf @@ -0,0 +1,740 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 12:45:00 November 06, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# firebee1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd" +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd" +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf" +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd" +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 + +# Simulator Assignments +# ===================== +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf + +# start EDA_TOOL_SETTINGS(eda_blast_fpga) +# --------------------------------------- + + # Analysis & Synthesis Assignments + # ================================ +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + +# end EDA_TOOL_SETTINGS(eda_blast_fpga) +# ------------------------------------- + +# start CLOCK(fast) +# ----------------- + + # Classic Timing Assignments + # ========================== +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast + +# end CLOCK(fast) +# --------------- + +# start ASSIGNMENT_GROUP(fast) +# ---------------------------- + + # Assignment Group Assignments + # ============================ +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast + +# end ASSIGNMENT_GROUP(fast) +# -------------------------- + +# ---------------------- +# start ENTITY(firebee1) + + # Classic Timing Assignments + # ========================== +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA + + # Fitter Assignments + # ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX + + # Simulator Assignments + # ===================== +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 + + # start LOGICLOCK_REGION(Root Region) + # ----------------------------------- + + # LogicLock Region Assignments + # ============================ +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + # end LOGICLOCK_REGION(Root Region) + # --------------------------------- + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(firebee1) +# -------------------- +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name QIP_FILE altpll4.qip +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_quartus/firebee1.qws b/FPGA_quartus/firebee1.qws new file mode 100644 index 0000000..ed1a121 --- /dev/null +++ b/FPGA_quartus/firebee1.qws @@ -0,0 +1,4 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames diff --git a/FPGA_quartus/firebee1.rbf b/FPGA_quartus/firebee1.rbf new file mode 100644 index 0000000000000000000000000000000000000000..63c16f1d687e91f02187b06b1c5e3ecfe12b2e04 GIT binary patch literal 428953 zcmeFaeY_l3dFNSGw>q^PJ~A=Q+=L>QwvdU;pNC;{O8v_HQ5i>SJI1 z>SK?7KE_}MWPghUnf^XK()0I74dyC*(z%gHMK0c4%0Pz+m zu6pz3u53PZbrcHb%UoRfPuI_Ux#F(veE8q9j%appAw3t;;nJ$_=yiDtT|Ww4{*%>n zWiI?y>ZtB~zpkwd)yF*k3+p}|4p)D^p5m7Q4u|Vs`A=5g)l=x|&ev1E+6ok(2i1GB z{P{Zb@g>0Fn9o<- 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z&ivBL;$AaWm!s)BK01PB+8#-XzlduP=Kt@Fr^OfFcmos7{E=(o@E@FsQDXV}8~5EW zCVz~H=G(tABbPy8!2j_TqMYFDnR^`S&t6DSj>`y+VDU`Qg{kYAd+ryv{>7M1%*6kC z;>b55v*LLpwk6cW5HHe$AA5@px}ftlB+I=+>Bmgwt`=*WPw>#q?l=V zf&yc#1gReHApt1zfJ=#ouARAGoc$vrt(aKCqD2LZ6m%(`C4fE(!|qCM-epD^9e}*B>bgqP1uDUK6uxXOKdNs%I53 z<^qDCYcwlZaVhFTmxJI%aaMog%*BU4@|!RH+>a>nTYqPKVfv(-Jn14tH{w{lA5Q5d&*4QlX9~@Z zdJZ4_DaB4JeG5XE|LJM8>_o1csmUxmT)Nykl!!!2Mmq1hwaj>GrbxHig>|S^Bw7BV zhN9U@DcdFV4{lGS(0Yt+wYONJaPeU=n=e0q@l^>DUVEYs!Erd6Ek>B$KL5_qd9epH z-i~C(G$+rA_!4>@#x!?pIPZT4Go?dWF2S@bGLS2bX*(*s;QblFbQYBSZ?@gnD z%Vq+yRnuBsv7nh2W0bKNrEsF4hqFa5jub%>KX-2m$Qk6HbwQ=PDAatKK1_r&C)gu literal 0 HcmV?d00001 diff --git a/FPGA_quartus/firebee1.tan.rpt b/FPGA_quartus/firebee1.tan.rpt new file mode 100644 index 0000000..b84e104 --- /dev/null +++ b/FPGA_quartus/firebee1.tan.rpt @@ -0,0 +1,6936 @@ +Classic Timing Analyzer report for firebee1 +Wed Dec 15 02:25:22 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + 7. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + 8. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + 9. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + 10. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + 11. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + 12. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + 13. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + 14. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + 15. Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + 16. Clock Setup: 'CLK33M' + 17. Clock Setup: 'MAIN_CLK' + 18. Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + 19. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + 20. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + 21. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + 22. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + 23. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + 24. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + 25. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + 26. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + 27. Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + 28. Clock Hold: 'CLK33M' + 29. Clock Hold: 'MAIN_CLK' + 30. tsu + 31. tco + 32. tpd + 33. th + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Slow Corner Signal Integrity Metrics + 37. Fast Corner Signal Integrity Metrics + 38. Ignored Timing Assignments + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ +; Worst-case tsu ; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; -- ; MAIN_CLK ; 6867 ; +; Worst-case tco ; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; -- ; 4976 ; +; Worst-case tpd ; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; -- ; -- ; 514 ; +; Worst-case th ; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; -- ; MAIN_CLK ; 117 ; +; Clock Setup: 'CLK33M' ; -5.966 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 3741 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -4.615 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 3741 ; +; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -4.294 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 3741 ; +; Clock Setup: 'MAIN_CLK' ; -4.261 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 27347 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -2.673 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 86 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -1.712 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 29 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 1.672 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 2.965 ns ; 132.01 MHz ( period = 7.575 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 5.299 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 28.590 ns ; 15.99 MHz ( period = 62.552 ns ) ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 498.663 ns ; 2.00 MHz ( period = 500.416 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; +; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 1997.239 ns ; 0.50 MHz ( period = 1999.998 ns ) ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'MAIN_CLK' ; -3.786 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 108 ; +; Clock Hold: 'CLK33M' ; -0.687 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 26 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -0.454 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 26 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 0.502 ns ; 15.99 MHz ( period = 62.552 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; 0.502 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; 0.502 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 0.564 ns ; 2.00 MHz ( period = 500.416 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 0.825 ns ; 0.50 MHz ( period = 1999.998 ns ) ; N/A ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 1.825 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; 2.664 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 3.263 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 4.336 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 51319 ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ +; Device Name ; EP3C40F484C6 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; tpd Requirement ; 1 ns ; ; ; ; +; th Requirement ; 1 ns ; ; ; ; +; tsu Requirement ; 1 ns ; ; ; ; +; tco Requirement ; 1 ns ; ; ; ; +; fmax Requirement ; 30 ns ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; +; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; On ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_0hh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; dcfifo_0hh1 ; +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_3fh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; dcfifo_3fh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; dcfifo_8fi1 ; +; Input Maximum Delay ; 4 ns ; * ; FB_ALE ; ; +; Maximum Delay ; 5 ns ; FB_AD ; BA ; ; +; Maximum Delay ; 5 ns ; FB_AD ; VA ; ; +; Maximum Delay ; 5 ns ; FB_AD ; nVRAS ; ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; ; PLL output ; 0.5 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 1 ; 66 ; -9.578 ns ; ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; ; PLL output ; 2.46 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 900 ; -9.578 ns ; ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; ; PLL output ; 24.57 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 90 ; -9.578 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; ; PLL output ; 2.0 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 1800 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; ; PLL output ; 15.99 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 225 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; ; PLL output ; 24.98 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 144 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; ; PLL output ; 47.96 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 75 ; -1.864 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -3.620 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -1.094 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 2.693 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 1.115 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; ; PLL output ; 66.0 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 2 ; 1 ; -4.884 ns ; ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; ; PLL output ; 95.92 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 218 ; 75 ; -2.843 ns ; ; +; CLK33M ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +; MAIN_CLK ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 1997.239 ns ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.574 ns ; +; 1997.297 ns ; 370.23 MHz ( period = 2.701 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.516 ns ; +; 1997.355 ns ; 378.36 MHz ( period = 2.643 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.458 ns ; +; 1997.413 ns ; 386.85 MHz ( period = 2.585 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.400 ns ; +; 1997.476 ns ; 396.51 MHz ( period = 2.522 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.337 ns ; +; 1997.531 ns ; 405.35 MHz ( period = 2.467 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.282 ns ; +; 1997.593 ns ; 415.80 MHz ( period = 2.405 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.220 ns ; +; 1997.626 ns ; 421.59 MHz ( period = 2.372 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.187 ns ; +; 1997.647 ns ; 425.35 MHz ( period = 2.351 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.166 ns ; +; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; +; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; +; 1997.709 ns ; 436.87 MHz ( period = 2.289 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.104 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.765 ns ; 447.83 MHz ( period = 2.233 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 2.049 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.822 ns ; 459.56 MHz ( period = 2.176 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.992 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.863 ns ; 468.38 MHz ( period = 2.135 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.950 ns ; +; 1997.880 ns ; 472.14 MHz ( period = 2.118 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.934 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.918 ns ; 480.77 MHz ( period = 2.080 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.895 ns ; +; 1997.921 ns ; 481.46 MHz ( period = 2.077 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.892 ns ; +; 1997.941 ns ; 486.14 MHz ( period = 2.057 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.873 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.976 ns ; 494.56 MHz ( period = 2.022 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.837 ns ; +; 1997.979 ns ; 495.29 MHz ( period = 2.019 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.834 ns ; +; 1997.980 ns ; 495.54 MHz ( period = 2.018 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.833 ns ; +; 1997.995 ns ; 499.25 MHz ( period = 2.003 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.819 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; +; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; +; 1998.037 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.776 ns ; +; 1998.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.775 ns ; +; 1998.055 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.759 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.091 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.723 ns ; +; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; +; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; +; 1998.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.718 ns ; +; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; +; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; +; 1998.113 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.701 ns ; +; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; +; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; +; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; +; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; +; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; +; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; +; 1998.152 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.662 ns ; +; 1998.153 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.660 ns ; +; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; +; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; +; 1998.167 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.647 ns ; +; 1998.206 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; +; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; +; 1998.209 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.605 ns ; +; 1998.210 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.604 ns ; +; 1998.211 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.602 ns ; +; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; +; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; +; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; +; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; +; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; +; 1998.268 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.546 ns ; +; 1998.269 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.544 ns ; +; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; +; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; +; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; +; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; +; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; +; 1998.326 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.488 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.432 ns ; +; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.384 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.430 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.374 ns ; +; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; +; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.369 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; +; 1998.445 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.369 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.498 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.316 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.311 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; +; 1998.503 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.311 ns ; +; 1998.671 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.143 ns ; +; 1999.023 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.791 ns ; +; 1999.024 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.790 ns ; +; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; +; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; +; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; +; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; +; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; +; 1999.031 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.783 ns ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.729 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.503 ns ; +; 498.743 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.489 ns ; +; 498.787 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.445 ns ; +; 498.800 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.432 ns ; +; 498.801 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.431 ns ; +; 498.858 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.374 ns ; +; 498.859 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.373 ns ; +; 498.894 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.338 ns ; +; 498.916 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.316 ns ; +; 498.917 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.315 ns ; +; 499.319 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.913 ns ; +; 499.422 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.810 ns ; +; 499.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.788 ns ; +; 499.449 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.783 ns ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 28.590 ns ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.545 ns ; +; 28.759 ns ; 198.65 MHz ( period = 5.034 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.376 ns ; +; 54.429 ns ; 123.11 MHz ( period = 8.123 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.941 ns ; +; 54.452 ns ; 123.46 MHz ( period = 8.100 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.920 ns ; +; 54.563 ns ; 125.17 MHz ( period = 7.989 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.803 ns ; +; 54.586 ns ; 125.53 MHz ( period = 7.966 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.782 ns ; +; 54.600 ns ; 125.75 MHz ( period = 7.952 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.766 ns ; +; 54.623 ns ; 126.12 MHz ( period = 7.929 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.745 ns ; +; 54.812 ns ; 129.20 MHz ( period = 7.740 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.551 ns ; +; 54.822 ns ; 129.37 MHz ( period = 7.730 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.550 ns ; +; 54.835 ns ; 129.58 MHz ( period = 7.717 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.530 ns ; +; 54.845 ns ; 129.75 MHz ( period = 7.707 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 7.529 ns ; +; 54.868 ns ; 130.14 MHz ( period = 7.684 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.491 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.474 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.910 ns ; 130.86 MHz ( period = 7.642 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.456 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.453 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.933 ns ; 131.25 MHz ( period = 7.619 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.435 ns ; +; 54.944 ns ; 131.44 MHz ( period = 7.608 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.417 ns ; +; 54.947 ns ; 131.49 MHz ( period = 7.605 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.414 ns ; +; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; +; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; +; 54.967 ns ; 131.84 MHz ( period = 7.585 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.396 ns ; +; 54.970 ns ; 131.89 MHz ( period = 7.582 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.393 ns ; +; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; +; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; +; 54.979 ns ; 132.05 MHz ( period = 7.573 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.382 ns ; +; 54.981 ns ; 132.08 MHz ( period = 7.571 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.387 ns ; +; 54.996 ns ; 132.35 MHz ( period = 7.556 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.374 ns ; +; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.361 ns ; +; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.353 ns ; +; 55.010 ns ; 132.59 MHz ( period = 7.542 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.362 ns ; +; 55.035 ns ; 133.03 MHz ( period = 7.517 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.326 ns ; +; 55.039 ns ; 133.10 MHz ( period = 7.513 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.316 ns ; +; 55.047 ns ; 133.24 MHz ( period = 7.505 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.312 ns ; +; 55.078 ns ; 133.80 MHz ( period = 7.474 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.291 ns ; +; 55.090 ns ; 134.01 MHz ( period = 7.462 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.270 ns ; +; 55.094 ns ; 134.08 MHz ( period = 7.458 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.266 ns ; +; 55.101 ns ; 134.21 MHz ( period = 7.451 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.371 ns ; 7.270 ns ; +; 55.102 ns ; 134.23 MHz ( period = 7.450 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.259 ns ; +; 55.104 ns ; 134.26 MHz ( period = 7.448 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.257 ns ; +; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.249 ns ; +; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.248 ns ; +; 55.115 ns ; 134.46 MHz ( period = 7.437 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.249 ns ; +; 55.117 ns ; 134.50 MHz ( period = 7.435 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.245 ns ; +; 55.125 ns ; 134.64 MHz ( period = 7.427 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.238 ns ; +; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.236 ns ; +; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.243 ns ; +; 55.130 ns ; 134.73 MHz ( period = 7.422 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.236 ns ; +; 55.136 ns ; 134.84 MHz ( period = 7.416 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.227 ns ; +; 55.140 ns ; 134.92 MHz ( period = 7.412 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.232 ns ; +; 55.144 ns ; 134.99 MHz ( period = 7.408 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.224 ns ; +; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.212 ns ; +; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.218 ns ; +; 55.161 ns ; 135.30 MHz ( period = 7.391 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.208 ns ; +; 55.167 ns ; 135.41 MHz ( period = 7.385 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.199 ns ; +; 55.169 ns ; 135.45 MHz ( period = 7.383 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.188 ns ; +; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.174 ns ; +; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.187 ns ; +; 55.190 ns ; 135.83 MHz ( period = 7.362 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.169 ns ; +; 55.204 ns ; 136.09 MHz ( period = 7.348 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.166 ns ; +; 55.206 ns ; 136.13 MHz ( period = 7.346 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.151 ns ; +; 55.218 ns ; 136.35 MHz ( period = 7.334 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.137 ns ; +; 55.227 ns ; 136.52 MHz ( period = 7.325 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.145 ns ; +; 55.251 ns ; 136.97 MHz ( period = 7.301 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.101 ns ; +; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.105 ns ; +; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.100 ns ; +; 55.272 ns ; 137.36 MHz ( period = 7.280 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.097 ns ; +; 55.274 ns ; 137.40 MHz ( period = 7.278 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.094 ns ; +; 55.278 ns ; 137.48 MHz ( period = 7.274 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.274 ns ; 6.996 ns ; +; 55.286 ns ; 137.63 MHz ( period = 7.266 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.080 ns ; +; 55.288 ns ; 137.67 MHz ( period = 7.264 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.084 ns ; +; 55.294 ns ; 137.78 MHz ( period = 7.258 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.076 ns ; +; 55.295 ns ; 137.80 MHz ( period = 7.257 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.070 ns ; +; 55.298 ns ; 137.85 MHz ( period = 7.254 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.068 ns ; +; 55.299 ns ; 137.87 MHz ( period = 7.253 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.065 ns ; +; 55.300 ns ; 137.89 MHz ( period = 7.252 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.068 ns ; +; 55.303 ns ; 137.95 MHz ( period = 7.249 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.061 ns ; +; 55.311 ns ; 138.10 MHz ( period = 7.241 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.057 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.052 ns ; +; 55.317 ns ; 138.22 MHz ( period = 7.235 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.044 ns ; +; 55.319 ns ; 138.26 MHz ( period = 7.233 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.042 ns ; +; 55.322 ns ; 138.31 MHz ( period = 7.230 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.044 ns ; +; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.043 ns ; +; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.047 ns ; +; 55.324 ns ; 138.35 MHz ( period = 7.228 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.031 ns ; +; 55.326 ns ; 138.39 MHz ( period = 7.226 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.040 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.024 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.032 ns ; +; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.029 ns ; +; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.028 ns ; +; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.033 ns ; +; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; +; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.031 ns ; +; 55.340 ns ; 138.66 MHz ( period = 7.212 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.023 ns ; +; 55.341 ns ; 138.68 MHz ( period = 7.211 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.019 ns ; +; 55.342 ns ; 138.70 MHz ( period = 7.210 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.021 ns ; +; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.016 ns ; +; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.022 ns ; +; 55.349 ns ; 138.83 MHz ( period = 7.203 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.006 ns ; +; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.011 ns ; +; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.008 ns ; +; 55.355 ns ; 138.95 MHz ( period = 7.197 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.007 ns ; +; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; +; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; +; 55.361 ns ; 139.06 MHz ( period = 7.191 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 6.994 ns ; +; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.997 ns ; +; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.998 ns ; +; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.995 ns ; +; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.001 ns ; +; 55.374 ns ; 139.31 MHz ( period = 7.178 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.996 ns ; +; 55.376 ns ; 139.35 MHz ( period = 7.176 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.987 ns ; +; 55.379 ns ; 139.41 MHz ( period = 7.173 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.984 ns ; +; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.980 ns ; +; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.967 ns ; +; 55.384 ns ; 139.51 MHz ( period = 7.168 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.986 ns ; +; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.964 ns ; +; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.982 ns ; +; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; +; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; +; 55.389 ns ; 139.61 MHz ( period = 7.163 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.983 ns ; +; 55.393 ns ; 139.68 MHz ( period = 7.159 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.972 ns ; +; 55.399 ns ; 139.80 MHz ( period = 7.153 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.966 ns ; +; 55.403 ns ; 139.88 MHz ( period = 7.149 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 6.971 ns ; +; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; +; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; +; 55.408 ns ; 139.98 MHz ( period = 7.144 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.739 ns ; 7.331 ns ; +; 55.409 ns ; 140.00 MHz ( period = 7.143 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.961 ns ; +; 55.415 ns ; 140.11 MHz ( period = 7.137 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.944 ns ; +; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.936 ns ; +; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.932 ns ; +; 55.422 ns ; 140.25 MHz ( period = 7.130 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.946 ns ; +; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.938 ns ; +; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.935 ns ; +; 55.430 ns ; 140.41 MHz ( period = 7.122 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.922 ns ; +; 55.440 ns ; 140.61 MHz ( period = 7.112 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.921 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.920 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.918 ns ; +; 55.443 ns ; 140.67 MHz ( period = 7.109 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.922 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.907 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.459 ns ; 140.98 MHz ( period = 7.093 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.909 ns ; +; 55.462 ns ; 141.04 MHz ( period = 7.090 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.902 ns ; +; 55.463 ns ; 141.06 MHz ( period = 7.089 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.901 ns ; +; 55.465 ns ; 141.10 MHz ( period = 7.087 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.901 ns ; +; 55.467 ns ; 141.14 MHz ( period = 7.085 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.897 ns ; +; 55.469 ns ; 141.18 MHz ( period = 7.083 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.895 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.895 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.471 ns ; 141.22 MHz ( period = 7.081 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.893 ns ; +; 55.477 ns ; 141.34 MHz ( period = 7.075 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.889 ns ; +; 55.478 ns ; 141.36 MHz ( period = 7.074 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.890 ns ; +; 55.480 ns ; 141.40 MHz ( period = 7.072 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.888 ns ; +; 55.483 ns ; 141.46 MHz ( period = 7.069 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.885 ns ; +; 55.486 ns ; 141.52 MHz ( period = 7.066 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.880 ns ; +; 55.487 ns ; 141.54 MHz ( period = 7.065 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.883 ns ; +; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.278 ns ; 6.788 ns ; +; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.876 ns ; +; 55.491 ns ; 141.62 MHz ( period = 7.061 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.877 ns ; +; 55.492 ns ; 141.64 MHz ( period = 7.060 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.874 ns ; +; 55.494 ns ; 141.68 MHz ( period = 7.058 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.872 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.859 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.496 ns ; 141.72 MHz ( period = 7.056 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.863 ns ; +; 55.497 ns ; 141.74 MHz ( period = 7.055 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.866 ns ; +; 55.499 ns ; 141.78 MHz ( period = 7.053 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.860 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.861 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; +; 55.501 ns ; 141.82 MHz ( period = 7.051 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.869 ns ; +; 55.503 ns ; 141.86 MHz ( period = 7.049 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.867 ns ; +; 55.506 ns ; 141.92 MHz ( period = 7.046 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.864 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.845 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.856 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.508 ns ; 141.96 MHz ( period = 7.044 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.855 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -4.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.687 ns ; +; -4.573 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.921 ns ; 3.652 ns ; +; -4.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.642 ns ; +; -4.562 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.915 ns ; 3.647 ns ; +; -4.553 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.635 ns ; +; -4.549 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.631 ns ; +; -4.541 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.613 ns ; +; -4.533 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.610 ns ; +; -4.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.608 ns ; +; -4.479 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.898 ns ; +; -4.440 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.141 ns ; +; -4.440 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.517 ns ; +; -4.413 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.114 ns ; +; -4.409 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.486 ns ; +; -4.407 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.491 ns ; +; -4.406 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.914 ns ; 3.492 ns ; +; -4.394 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.468 ns ; +; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.465 ns ; +; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.466 ns ; +; -4.386 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.461 ns ; +; -4.381 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.458 ns ; +; -4.378 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.455 ns ; +; -4.372 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.445 ns ; +; -4.369 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 4.068 ns ; +; -4.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.444 ns ; +; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; +; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; +; -4.364 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.441 ns ; +; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.063 ns ; +; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.440 ns ; +; -4.361 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.436 ns ; +; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.434 ns ; +; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.435 ns ; +; -4.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.431 ns ; +; -4.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.433 ns ; +; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; +; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; +; -4.351 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.420 ns ; +; -4.348 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.426 ns ; +; -4.318 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.402 ns ; +; -4.316 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.919 ns ; 3.397 ns ; +; -4.308 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.008 ns ; +; -4.306 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.725 ns ; +; -4.305 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.379 ns ; +; -4.301 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.002 ns ; +; -4.299 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.376 ns ; +; -4.298 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.924 ns ; 3.374 ns ; +; -4.297 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.374 ns ; +; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.372 ns ; +; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.370 ns ; +; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.371 ns ; +; -4.290 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.365 ns ; +; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.366 ns ; +; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.364 ns ; +; -4.288 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.363 ns ; +; -4.279 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.356 ns ; +; -4.278 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.355 ns ; +; -4.277 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.354 ns ; +; -4.273 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.347 ns ; +; -4.271 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.972 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.970 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.343 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; +; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; +; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; +; -4.267 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.344 ns ; +; -4.266 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.343 ns ; +; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; +; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; +; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; +; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; +; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.960 ns ; +; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.334 ns ; +; -4.258 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.332 ns ; +; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; +; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; +; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.329 ns ; +; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.330 ns ; +; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.330 ns ; +; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.327 ns ; +; -4.251 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.328 ns ; +; -4.248 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.325 ns ; +; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.324 ns ; +; -4.246 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.323 ns ; +; -4.245 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.319 ns ; +; -4.243 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.944 ns ; +; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.316 ns ; +; -4.236 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.310 ns ; +; -4.230 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.929 ns ; +; -4.229 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.928 ns ; +; -4.219 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.919 ns ; +; -4.217 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.292 ns ; +; -4.215 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.916 ns ; +; -4.203 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.904 ns ; +; -4.199 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.899 ns ; +; -4.195 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.614 ns ; +; -4.194 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.269 ns ; +; -4.190 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.257 ns ; +; -4.188 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.887 ns ; +; -4.188 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.564 ns ; +; -4.179 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.248 ns ; +; -4.175 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.876 ns ; +; -4.172 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.591 ns ; +; -4.156 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.855 ns ; +; -4.154 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.551 ns ; +; -4.149 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.850 ns ; +; -4.148 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.847 ns ; +; -4.143 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.540 ns ; +; -4.142 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.530 ns ; +; -4.140 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.516 ns ; +; -4.139 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.216 ns ; +; -4.138 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.838 ns ; +; -4.137 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.211 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.134 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.211 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.210 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; +; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.204 ns ; +; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.205 ns ; +; -4.128 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.205 ns ; +; -4.127 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.202 ns ; +; -4.125 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.199 ns ; +; -4.124 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.191 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.616 ns ; 3.497 ns ; +; -4.109 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.186 ns ; +; -4.108 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.505 ns ; +; -4.104 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.171 ns ; +; -4.102 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.176 ns ; +; -4.101 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.802 ns ; +; -4.100 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.519 ns ; +; -4.098 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.936 ns ; 3.162 ns ; +; -4.098 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.495 ns ; +; -4.097 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.796 ns ; +; -4.092 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.793 ns ; +; -4.088 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.507 ns ; +; -4.083 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.480 ns ; +; -4.078 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.779 ns ; +; -4.069 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.763 ns ; +; -4.068 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.456 ns ; +; -4.068 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.762 ns ; +; -4.064 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.307 ns ; 3.757 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.436 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; +; -4.041 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.308 ns ; 3.733 ns ; +; -4.038 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.615 ns ; 3.423 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.096 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.943 ns ; 3.091 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.734 ns ; +; -4.024 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.411 ns ; +; -4.019 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.438 ns ; +; -4.016 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.093 ns ; +; -4.015 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.092 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.088 ns ; +; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.085 ns ; +; -4.009 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.084 ns ; +; -4.006 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.080 ns ; +; -4.006 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.403 ns ; +; -4.005 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.080 ns ; +; -4.004 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.703 ns ; +; -4.000 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.419 ns ; +; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.075 ns ; +; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.699 ns ; +; -3.996 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.073 ns ; +; -3.995 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.392 ns ; +; -3.993 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.070 ns ; +; -3.991 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.068 ns ; +; -3.989 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.051 ns ; +; -3.989 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.610 ns ; 3.379 ns ; +; -3.988 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.065 ns ; +; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; +; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.058 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.059 ns ; +; -3.983 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.057 ns ; +; -3.982 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.056 ns ; +; -3.981 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.055 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.369 ns ; +; -3.970 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.037 ns ; +; -3.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.666 ns ; +; -3.954 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.935 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -2.673 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.814 ns ; 3.487 ns ; +; -2.447 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 3.530 ns ; +; -2.348 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_BANK_OK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.155 ns ; +; -2.346 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.153 ns ; +; -2.275 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.082 ns ; +; -2.254 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.061 ns ; +; -2.243 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.138 ns ; 3.381 ns ; +; -2.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.100 ns ; 3.294 ns ; +; -2.187 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 3.262 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.239 ns ; +; -2.024 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.169 ns ; +; -2.006 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.151 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 3.125 ns ; +; -1.990 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_FIFO_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.797 ns ; +; -1.911 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 3.051 ns ; +; -1.896 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.986 ns ; +; -1.895 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.985 ns ; +; -1.873 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.680 ns ; +; -1.871 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.678 ns ; +; -1.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; -1.306 ns ; 0.532 ns ; +; -1.834 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.965 ns ; +; -1.828 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.907 ns ; +; -1.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.906 ns ; +; -1.824 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.903 ns ; +; -1.800 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.931 ns ; +; -1.800 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.879 ns ; +; -1.765 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.910 ns ; +; -1.763 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 2.895 ns ; +; -1.755 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.891 ns ; +; -1.647 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.780 ns ; +; -1.646 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.779 ns ; +; -1.641 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.770 ns ; +; -1.610 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.739 ns ; +; -1.593 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.152 ns ; 2.745 ns ; +; -1.556 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.134 ns ; 2.690 ns ; +; -1.553 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.682 ns ; +; -1.470 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.612 ns ; +; -1.465 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.594 ns ; +; -1.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.127 ns ; 2.590 ns ; +; -1.451 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.596 ns ; +; -1.441 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.586 ns ; +; -1.436 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.572 ns ; +; -1.413 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.555 ns ; +; -1.361 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.506 ns ; +; -1.341 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.486 ns ; +; -1.329 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.404 ns ; +; -1.327 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.410 ns ; +; -1.326 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.410 ns ; +; -1.302 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.385 ns ; +; -1.298 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.126 ns ; 2.424 ns ; +; -1.271 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 2.348 ns ; +; -1.252 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.335 ns ; +; -1.216 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.358 ns ; +; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; +; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; +; -1.181 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.264 ns ; +; -1.167 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_CB8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.246 ns ; +; -1.162 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.241 ns ; +; -1.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.130 ns ; 2.269 ns ; +; -1.102 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.186 ns ; +; -1.077 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 2.217 ns ; +; -1.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.151 ns ; 2.199 ns ; +; -1.047 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.131 ns ; +; -0.910 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.123 ns ; 2.033 ns ; +; -0.901 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.992 ns ; +; -0.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.917 ns ; +; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; +; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; +; -0.741 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.832 ns ; +; -0.642 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.730 ns ; +; -0.623 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.711 ns ; +; -0.616 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.704 ns ; +; -0.600 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.688 ns ; +; -0.596 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.087 ns ; 1.683 ns ; +; -0.413 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.490 ns ; +; -0.410 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.487 ns ; +; -0.199 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.289 ns ; +; -0.193 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2B ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.283 ns ; +; -0.191 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.282 ns ; +; -0.186 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.361 ns ; +; -0.183 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.274 ns ; +; -0.102 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.040 ns ; 3.142 ns ; +; -0.068 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.239 ns ; +; -0.062 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.237 ns ; +; -0.041 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 4.203 ns ; +; -0.024 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.205 ns ; +; 0.003 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.165 ns ; +; 0.039 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.134 ns ; +; 0.059 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.032 ns ; +; 0.073 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.098 ns ; +; 0.080 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 4.087 ns ; +; 0.108 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.073 ns ; +; 0.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.045 ns ; +; 0.165 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 4.017 ns ; +; 0.166 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.007 ns ; +; 0.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 3.973 ns ; +; 0.201 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 3.961 ns ; +; 0.250 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.464 ns ; 4.214 ns ; +; 0.301 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.522 ns ; 4.221 ns ; +; 0.306 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.483 ns ; 4.177 ns ; +; 0.375 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.514 ns ; 4.139 ns ; +; 0.401 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.475 ns ; 4.074 ns ; +; 0.451 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 3.731 ns ; +; 0.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.477 ns ; 4.023 ns ; +; 0.467 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.473 ns ; 4.006 ns ; +; 0.509 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.503 ns ; 3.994 ns ; +; 0.514 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.469 ns ; 3.955 ns ; +; 0.539 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.484 ns ; 3.945 ns ; +; 0.568 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.823 ns ; +; 0.576 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.470 ns ; 3.894 ns ; +; 0.579 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.804 ns ; +; 0.580 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.408 ns ; 3.828 ns ; +; 0.619 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.768 ns ; +; 0.677 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.516 ns ; 3.839 ns ; +; 0.695 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.508 ns ; 3.813 ns ; +; 0.773 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.512 ns ; 3.739 ns ; +; 0.800 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.587 ns ; +; 0.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.582 ns ; +; 0.810 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.509 ns ; 3.699 ns ; +; 0.818 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.523 ns ; 3.705 ns ; +; 0.834 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.212 ns ; 3.378 ns ; +; 0.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.545 ns ; +; 0.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.551 ns ; +; 0.841 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.551 ns ; +; 0.933 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.454 ns ; +; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; +; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; +; 1.026 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.365 ns ; +; 1.038 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 3.347 ns ; +; 1.057 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.334 ns ; +; 1.110 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.947 ns ; +; 1.120 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.272 ns ; +; 1.147 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.244 ns ; +; 1.153 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.245 ns ; +; 1.207 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.185 ns ; +; 1.266 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 3.133 ns ; +; 1.344 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.713 ns ; +; 1.374 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.024 ns ; +; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; +; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; +; 1.426 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.973 ns ; +; 1.426 ns ; 162.63 MHz ( period = 6.149 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.936 ns ; +; 1.427 ns ; 162.65 MHz ( period = 6.148 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.935 ns ; +; 1.481 ns ; 164.10 MHz ( period = 6.094 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.881 ns ; +; 1.482 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.916 ns ; +; 1.484 ns ; 164.18 MHz ( period = 6.091 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.878 ns ; +; 1.526 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.055 ns ; 1.529 ns ; +; 1.527 ns ; 165.34 MHz ( period = 6.048 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.835 ns ; +; 1.540 ns ; 165.70 MHz ( period = 6.035 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.822 ns ; +; 1.543 ns ; 165.78 MHz ( period = 6.032 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.819 ns ; +; 1.582 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.858 ns ; 3.276 ns ; +; 1.589 ns ; 167.06 MHz ( period = 5.986 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.773 ns ; +; 1.598 ns ; 167.31 MHz ( period = 5.977 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.764 ns ; +; 1.601 ns ; 167.39 MHz ( period = 5.974 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.761 ns ; +; 1.656 ns ; 168.95 MHz ( period = 5.919 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.706 ns ; +; 1.676 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.850 ns ; 3.174 ns ; +; 1.677 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.147 ns ; +; 1.679 ns ; 169.61 MHz ( period = 5.896 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.700 ns ; +; 1.680 ns ; 169.64 MHz ( period = 5.895 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.699 ns ; +; 1.686 ns ; 169.81 MHz ( period = 5.889 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.668 ns ; +; 1.687 ns ; 169.84 MHz ( period = 5.888 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.667 ns ; +; 1.714 ns ; 170.62 MHz ( period = 5.861 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.648 ns ; +; 1.734 ns ; 171.20 MHz ( period = 5.841 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.645 ns ; +; 1.737 ns ; 171.29 MHz ( period = 5.838 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.642 ns ; +; 1.738 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.103 ns ; +; 1.741 ns ; 171.41 MHz ( period = 5.834 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.613 ns ; +; 1.744 ns ; 171.50 MHz ( period = 5.831 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.610 ns ; +; 1.746 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.095 ns ; +; 1.747 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.118 ns ; +; 1.750 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.866 ns ; 3.116 ns ; +; 1.756 ns ; 171.85 MHz ( period = 5.819 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.606 ns ; +; 1.760 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.105 ns ; +; 1.779 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.045 ns ; +; 1.780 ns ; 172.56 MHz ( period = 5.795 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.599 ns ; +; 1.787 ns ; 172.77 MHz ( period = 5.788 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.567 ns ; +; 1.792 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.032 ns ; +; 1.793 ns ; 172.95 MHz ( period = 5.782 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.586 ns ; +; 1.796 ns ; 173.04 MHz ( period = 5.779 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.583 ns ; +; 1.800 ns ; 173.16 MHz ( period = 5.775 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.554 ns ; +; 1.803 ns ; 173.25 MHz ( period = 5.772 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.551 ns ; +; 1.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.580 ns ; +; 1.808 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.577 ns ; +; 1.812 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.831 ns ; 3.019 ns ; +; 1.829 ns ; 174.03 MHz ( period = 5.746 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.525 ns ; +; 1.830 ns ; 174.06 MHz ( period = 5.745 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.524 ns ; +; 1.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.559 ns ; +; 1.842 ns ; 174.43 MHz ( period = 5.733 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.537 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.557 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 2.982 ns ; +; 1.845 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.002 ns ; +; 1.847 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.000 ns ; +; 1.849 ns ; 174.64 MHz ( period = 5.726 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.505 ns ; +; 1.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.547 ns ; +; 1.851 ns ; 174.70 MHz ( period = 5.724 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.528 ns ; +; 1.854 ns ; 174.79 MHz ( period = 5.721 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.525 ns ; +; 1.858 ns ; 174.92 MHz ( period = 5.717 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.496 ns ; +; 1.861 ns ; 175.01 MHz ( period = 5.714 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.493 ns ; +; 1.865 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.826 ns ; 2.961 ns ; +; 1.873 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.956 ns ; +; 1.881 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.948 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 2.965 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.639 ns ; +; 2.966 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.638 ns ; +; 2.967 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.637 ns ; +; 2.968 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.636 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 5.299 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.118 ns ; 0.819 ns ; +; 5.479 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.637 ns ; +; 5.480 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.636 ns ; +; 5.606 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.510 ns ; +; 5.608 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.508 ns ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 1.672 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.636 ns ; +; 1.683 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.304 ns ; 3.621 ns ; +; 1.703 ns ; 170.30 MHz ( period = 5.872 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 5.190 ns ; +; 1.806 ns ; 173.34 MHz ( period = 5.769 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 5.081 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.327 ns ; 3.485 ns ; +; 1.881 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.428 ns ; +; 1.904 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.325 ns ; 3.421 ns ; +; 1.914 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.395 ns ; +; 1.923 ns ; 176.93 MHz ( period = 5.652 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.970 ns ; +; 2.000 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.308 ns ; +; 2.018 ns ; 179.95 MHz ( period = 5.557 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.865 ns ; +; 2.034 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 3.287 ns ; +; 2.040 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 3.253 ns ; +; 2.068 ns ; 181.59 MHz ( period = 5.507 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 4.819 ns ; +; 2.105 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 3.197 ns ; +; 2.112 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.488 ns ; 2.376 ns ; +; 2.131 ns ; 183.69 MHz ( period = 5.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.896 ns ; 4.765 ns ; +; 2.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 3.175 ns ; +; 2.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 3.156 ns ; +; 2.155 ns ; 184.50 MHz ( period = 5.420 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.900 ns ; 4.745 ns ; +; 2.159 ns ; 184.64 MHz ( period = 5.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.732 ns ; +; 2.166 ns ; 184.88 MHz ( period = 5.409 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.712 ns ; +; 2.178 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.131 ns ; +; 2.202 ns ; 186.12 MHz ( period = 5.373 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.691 ns ; +; 2.203 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 3.109 ns ; +; 2.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.335 ns ; 3.128 ns ; +; 2.238 ns ; 187.37 MHz ( period = 5.337 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.640 ns ; +; 2.242 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 3.075 ns ; +; 2.260 ns ; 188.15 MHz ( period = 5.315 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.631 ns ; +; 2.265 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.428 ns ; 2.163 ns ; +; 2.273 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.492 ns ; 2.219 ns ; +; 2.298 ns ; 189.50 MHz ( period = 5.277 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.603 ns ; +; 2.325 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.991 ns ; +; 2.338 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.383 ns ; 3.045 ns ; +; 2.357 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 2.964 ns ; +; 2.370 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 2.932 ns ; +; 2.376 ns ; 192.34 MHz ( period = 5.199 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.507 ns ; +; 2.385 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 3.250 ns ; +; 2.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.906 ns ; +; 2.417 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 2.890 ns ; +; 2.434 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.939 ns ; +; 2.445 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.495 ns ; 2.050 ns ; +; 2.447 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.865 ns ; +; 2.470 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.175 ns ; +; 2.502 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 3.150 ns ; +; 2.509 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.134 ns ; +; 2.516 ns ; 197.67 MHz ( period = 5.059 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.725 ns ; +; 2.517 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 2.791 ns ; +; 2.520 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.773 ns ; +; 2.523 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.122 ns ; +; 2.531 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 3.108 ns ; +; 2.548 ns ; 198.93 MHz ( period = 5.027 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.248 ns ; 4.700 ns ; +; 2.549 ns ; 198.97 MHz ( period = 5.026 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.329 ns ; +; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.351 ns ; +; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.689 ns ; +; 2.561 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.814 ns ; +; 2.567 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.290 ns ; 2.723 ns ; +; 2.569 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 2.748 ns ; +; 2.569 ns ; 199.76 MHz ( period = 5.006 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.662 ns ; +; 2.570 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.805 ns ; +; 2.571 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.072 ns ; +; 2.572 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.306 ns ; 2.734 ns ; +; 2.597 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.719 ns ; +; 2.603 ns ; 201.13 MHz ( period = 4.972 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.638 ns ; +; 2.614 ns ; 201.57 MHz ( period = 4.961 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.625 ns ; +; 2.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.761 ns ; +; 2.622 ns ; 201.90 MHz ( period = 4.953 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 4.325 ns ; +; 2.641 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.004 ns ; +; 2.685 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.330 ns ; 2.645 ns ; +; 2.690 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.949 ns ; +; 2.695 ns ; 204.92 MHz ( period = 4.880 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.254 ns ; +; 2.697 ns ; 205.00 MHz ( period = 4.878 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.529 ns ; +; 2.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.940 ns ; +; 2.716 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.596 ns ; +; 2.717 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.913 ns ; +; 2.718 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.912 ns ; +; 2.724 ns ; 206.14 MHz ( period = 4.851 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.517 ns ; +; 2.733 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.356 ns ; 2.623 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.911 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.381 ns ; 2.647 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.559 ns ; 1.825 ns ; +; 2.751 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.626 ns ; +; 2.758 ns ; 207.60 MHz ( period = 4.817 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.244 ns ; 4.486 ns ; +; 2.761 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.874 ns ; +; 2.761 ns ; 207.73 MHz ( period = 4.814 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.188 ns ; +; 2.764 ns ; 207.86 MHz ( period = 4.811 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.185 ns ; +; 2.768 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 2.884 ns ; +; 2.771 ns ; 208.16 MHz ( period = 4.804 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.464 ns ; +; 2.776 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.867 ns ; +; 2.778 ns ; 208.46 MHz ( period = 4.797 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.948 ns ; 4.170 ns ; +; 2.780 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.855 ns ; +; 2.793 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.852 ns ; +; 2.793 ns ; 209.12 MHz ( period = 4.782 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.433 ns ; +; 2.797 ns ; 209.29 MHz ( period = 4.778 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.429 ns ; +; 2.798 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.378 ns ; 2.580 ns ; +; 2.807 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.972 ns ; +; 2.808 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.374 ns ; 2.566 ns ; +; 2.815 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.558 ns ; +; 2.821 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.818 ns ; +; 2.838 ns ; 211.10 MHz ( period = 4.737 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.393 ns ; +; 2.839 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.804 ns ; +; 2.846 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.447 ns ; +; 2.851 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.334 ns ; 2.483 ns ; +; 2.862 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.454 ns ; +; 2.909 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.736 ns ; +; 2.935 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.423 ns ; +; 2.937 ns ; 215.61 MHz ( period = 4.638 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 4.006 ns ; +; 2.951 ns ; 216.26 MHz ( period = 4.624 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 3.998 ns ; +; 2.954 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.685 ns ; +; 2.960 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.695 ns ; +; 2.963 ns ; 216.83 MHz ( period = 4.612 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.980 ns ; +; 2.969 ns ; 217.11 MHz ( period = 4.606 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.978 ns ; +; 2.977 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.671 ns ; +; 2.983 ns ; 217.77 MHz ( period = 4.592 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.252 ns ; +; 2.984 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.646 ns ; +; 2.985 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.645 ns ; +; 2.988 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.791 ns ; +; 3.004 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.358 ns ; +; 3.005 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.364 ns ; 2.359 ns ; +; 3.010 ns ; 219.06 MHz ( period = 4.565 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.282 ns ; +; 3.018 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.635 ns ; +; 3.027 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.608 ns ; +; 3.042 ns ; 220.60 MHz ( period = 4.533 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 4.252 ns ; +; 3.047 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.729 ns ; 2.682 ns ; +; 3.051 ns ; 221.04 MHz ( period = 4.524 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.198 ns ; +; 3.058 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.354 ns ; 2.296 ns ; +; 3.061 ns ; 221.53 MHz ( period = 4.514 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.188 ns ; +; 3.074 ns ; 222.17 MHz ( period = 4.501 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.872 ns ; +; 3.096 ns ; 223.26 MHz ( period = 4.479 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.851 ns ; +; 3.115 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.246 ns ; +; 3.127 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.234 ns ; +; 3.131 ns ; 225.02 MHz ( period = 4.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.812 ns ; +; 3.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.325 ns ; 2.184 ns ; +; 3.143 ns ; 225.63 MHz ( period = 4.432 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.152 ns ; +; 3.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.479 ns ; +; 3.158 ns ; 226.40 MHz ( period = 4.417 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.134 ns ; +; 3.159 ns ; 226.45 MHz ( period = 4.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.132 ns ; +; 3.162 ns ; 226.60 MHz ( period = 4.413 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.133 ns ; +; 3.163 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.780 ns ; 2.617 ns ; +; 3.173 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.680 ns ; 2.507 ns ; +; 3.181 ns ; 227.58 MHz ( period = 4.394 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.763 ns ; +; 3.192 ns ; 228.15 MHz ( period = 4.383 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.755 ns ; +; 3.199 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.431 ns ; +; 3.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.671 ns ; 2.464 ns ; +; 3.208 ns ; 228.99 MHz ( period = 4.367 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.738 ns ; +; 3.209 ns ; 229.04 MHz ( period = 4.366 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.735 ns ; +; 3.225 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.470 ns ; +; 3.226 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.429 ns ; +; 3.233 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 2.126 ns ; +; 3.236 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.125 ns ; +; 3.251 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.107 ns ; +; 3.253 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.355 ns ; 2.102 ns ; +; 3.261 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.097 ns ; +; 3.262 ns ; 231.86 MHz ( period = 4.313 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 4.035 ns ; +; 3.263 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.100 ns ; +; 3.266 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.097 ns ; +; 3.271 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.091 ns ; +; 3.277 ns ; 232.67 MHz ( period = 4.298 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.014 ns ; +; 3.279 ns ; 232.77 MHz ( period = 4.296 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.012 ns ; +; 3.282 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.371 ns ; +; 3.307 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.383 ns ; 2.076 ns ; +; 3.346 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.352 ns ; +; 3.351 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.344 ns ; +; 3.365 ns ; 237.53 MHz ( period = 4.210 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.296 ns ; 3.931 ns ; +; 3.387 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.974 ns ; +; 3.390 ns ; 238.95 MHz ( period = 4.185 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 3.904 ns ; +; 3.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 1.952 ns ; +; 3.415 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.283 ns ; +; 3.429 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 1.929 ns ; +; 3.438 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 1.937 ns ; +; 3.450 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.250 ns ; +; 3.458 ns ; 242.90 MHz ( period = 4.117 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.837 ns ; +; 3.459 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.239 ns ; +; 3.461 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.781 ns ; 2.320 ns ; +; 3.474 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.380 ns ; 1.906 ns ; +; 3.477 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.882 ns ; +; 3.492 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.203 ns ; +; 3.495 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.205 ns ; +; 3.499 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.860 ns ; +; 3.504 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.857 ns ; +; 3.558 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.141 ns ; +; 3.575 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.122 ns ; +; 3.602 ns ; 251.70 MHz ( period = 3.973 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.693 ns ; +; 3.610 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.089 ns ; +; 3.614 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.084 ns ; +; 3.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.701 ns ; 2.085 ns ; +; 3.617 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.079 ns ; +; 3.620 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.077 ns ; +; 3.625 ns ; 253.16 MHz ( period = 3.950 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.672 ns ; +; 3.640 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.059 ns ; +; 3.649 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.726 ns ; 2.077 ns ; +; 3.657 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.042 ns ; +; 3.663 ns ; 255.62 MHz ( period = 3.912 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.634 ns ; +; 3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.032 ns ; +; 3.673 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 2.030 ns ; +; 3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.024 ns ; +; 3.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.702 ns ; 1.994 ns ; +; 3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 1.983 ns ; +; 3.738 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 1.959 ns ; +; 3.825 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 1.874 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -1.712 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 1.118 ns ; 2.830 ns ; +; -1.664 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.656 ns ; +; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; +; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; +; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; +; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.248 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.237 ns ; +; -1.243 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.232 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; 4.485 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 6.311 ns ; 6.117 ns ; 1.632 ns ; +; 6.612 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.393 ns ; 3.781 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.843 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.545 ns ; 3.702 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 7.011 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.390 ns ; 3.379 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.111 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.514 ns ; 3.403 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.264 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.548 ns ; 3.284 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.687 ns ; +; -4.252 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.600 ns ; 3.652 ns ; +; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.642 ns ; +; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.594 ns ; 3.647 ns ; +; -4.232 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.635 ns ; +; -4.228 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.631 ns ; +; -4.220 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.613 ns ; +; -4.212 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.610 ns ; +; -4.205 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.608 ns ; +; -4.158 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.898 ns ; +; -4.119 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.141 ns ; +; -4.119 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.517 ns ; +; -4.092 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.114 ns ; +; -4.088 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.486 ns ; +; -4.086 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.491 ns ; +; -4.085 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.593 ns ; 3.492 ns ; +; -4.073 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.468 ns ; +; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.465 ns ; +; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.466 ns ; +; -4.065 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.461 ns ; +; -4.060 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.458 ns ; +; -4.057 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.455 ns ; +; -4.051 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.445 ns ; +; -4.048 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 4.068 ns ; +; -4.046 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.444 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; +; -4.043 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.441 ns ; +; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.063 ns ; +; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.440 ns ; +; -4.040 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.436 ns ; +; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.434 ns ; +; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.435 ns ; +; -4.036 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.431 ns ; +; -4.035 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.433 ns ; +; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; +; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; +; -4.030 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.420 ns ; +; -4.027 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.426 ns ; +; -3.997 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.402 ns ; +; -3.995 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.598 ns ; 3.397 ns ; +; -3.987 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.008 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.725 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.379 ns ; +; -3.980 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.002 ns ; +; -3.978 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.376 ns ; +; -3.977 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.603 ns ; 3.374 ns ; +; -3.976 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.374 ns ; +; -3.973 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.372 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.370 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.371 ns ; +; -3.969 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.365 ns ; +; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.366 ns ; +; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.364 ns ; +; -3.967 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.363 ns ; +; -3.958 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.356 ns ; +; -3.957 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.355 ns ; +; -3.956 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.354 ns ; +; -3.952 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.347 ns ; +; -3.950 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.972 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.970 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.343 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; +; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; +; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; +; -3.946 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.344 ns ; +; -3.945 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.343 ns ; +; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; +; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; +; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; +; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; +; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.960 ns ; +; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.334 ns ; +; -3.937 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.332 ns ; +; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; +; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; +; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.329 ns ; +; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.330 ns ; +; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.330 ns ; +; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.327 ns ; +; -3.930 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.328 ns ; +; -3.927 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.325 ns ; +; -3.926 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.324 ns ; +; -3.925 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.323 ns ; +; -3.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.319 ns ; +; -3.922 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.944 ns ; +; -3.920 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.316 ns ; +; -3.915 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.310 ns ; +; -3.909 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.929 ns ; +; -3.908 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.928 ns ; +; -3.898 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.919 ns ; +; -3.896 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.292 ns ; +; -3.894 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.916 ns ; +; -3.882 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.904 ns ; +; -3.878 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.899 ns ; +; -3.874 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.614 ns ; +; -3.873 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.269 ns ; +; -3.869 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.257 ns ; +; -3.867 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.887 ns ; +; -3.867 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.564 ns ; +; -3.858 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.248 ns ; +; -3.854 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.876 ns ; +; -3.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.591 ns ; +; -3.835 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.855 ns ; +; -3.833 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.551 ns ; +; -3.828 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.850 ns ; +; -3.827 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.847 ns ; +; -3.822 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.540 ns ; +; -3.821 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.530 ns ; +; -3.819 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.516 ns ; +; -3.818 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.216 ns ; +; -3.817 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.838 ns ; +; -3.816 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.211 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.813 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.211 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.210 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; +; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.204 ns ; +; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.205 ns ; +; -3.807 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.205 ns ; +; -3.806 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.202 ns ; +; -3.804 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.199 ns ; +; -3.803 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.191 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.295 ns ; 3.497 ns ; +; -3.788 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.186 ns ; +; -3.787 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.505 ns ; +; -3.783 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.171 ns ; +; -3.781 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.176 ns ; +; -3.780 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.802 ns ; +; -3.779 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.519 ns ; +; -3.777 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.615 ns ; 3.162 ns ; +; -3.777 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.495 ns ; +; -3.776 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.796 ns ; +; -3.771 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.793 ns ; +; -3.767 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.507 ns ; +; -3.762 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.480 ns ; +; -3.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.779 ns ; +; -3.748 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.763 ns ; +; -3.747 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.456 ns ; +; -3.747 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.762 ns ; +; -3.743 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.014 ns ; 3.757 ns ; +; -3.728 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.436 ns ; +; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; +; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; +; -3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.013 ns ; 3.733 ns ; +; -3.717 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.294 ns ; 3.423 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.096 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.622 ns ; 3.091 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.734 ns ; +; -3.703 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.411 ns ; +; -3.698 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.438 ns ; +; -3.695 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.093 ns ; +; -3.694 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.092 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.088 ns ; +; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.085 ns ; +; -3.688 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.084 ns ; +; -3.685 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.080 ns ; +; -3.685 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.403 ns ; +; -3.684 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.080 ns ; +; -3.683 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.703 ns ; +; -3.679 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.419 ns ; +; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.075 ns ; +; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.699 ns ; +; -3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.073 ns ; +; -3.674 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.392 ns ; +; -3.672 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.070 ns ; +; -3.670 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.068 ns ; +; -3.668 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.051 ns ; +; -3.668 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.289 ns ; 3.379 ns ; +; -3.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.065 ns ; +; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; +; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; +; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.058 ns ; +; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.059 ns ; +; -3.662 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.057 ns ; +; -3.661 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.056 ns ; +; -3.660 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.055 ns ; +; -3.651 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.369 ns ; +; -3.649 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.037 ns ; +; -3.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.666 ns ; +; -3.633 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.614 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'CLK33M' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; -5.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.687 ns ; +; -5.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.272 ns ; 3.652 ns ; +; -5.919 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.642 ns ; +; -5.913 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.266 ns ; 3.647 ns ; +; -5.904 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.635 ns ; +; -5.900 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.631 ns ; +; -5.892 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.613 ns ; +; -5.884 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.610 ns ; +; -5.877 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.608 ns ; +; -5.830 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.898 ns ; +; -5.791 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.141 ns ; +; -5.791 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.517 ns ; +; -5.764 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.114 ns ; +; -5.760 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.486 ns ; +; -5.758 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.491 ns ; +; -5.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.265 ns ; 3.492 ns ; +; -5.745 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.468 ns ; +; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.465 ns ; +; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.466 ns ; +; -5.737 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.461 ns ; +; -5.732 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.458 ns ; +; -5.729 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.455 ns ; +; -5.723 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.445 ns ; +; -5.720 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 4.068 ns ; +; -5.718 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.444 ns ; +; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; +; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; +; -5.715 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.441 ns ; +; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.063 ns ; +; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.440 ns ; +; -5.712 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.436 ns ; +; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.434 ns ; +; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.435 ns ; +; -5.708 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.431 ns ; +; -5.707 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.433 ns ; +; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; +; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; +; -5.702 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.420 ns ; +; -5.699 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.426 ns ; +; -5.669 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.402 ns ; +; -5.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.270 ns ; 3.397 ns ; +; -5.659 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.008 ns ; +; -5.657 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.725 ns ; +; -5.656 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.379 ns ; +; -5.652 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.002 ns ; +; -5.650 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.376 ns ; +; -5.649 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.275 ns ; 3.374 ns ; +; -5.648 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.374 ns ; +; -5.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.372 ns ; +; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.370 ns ; +; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.371 ns ; +; -5.641 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.365 ns ; +; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.366 ns ; +; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.364 ns ; +; -5.639 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.363 ns ; +; -5.630 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.356 ns ; +; -5.629 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.355 ns ; +; -5.628 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.354 ns ; +; -5.624 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.347 ns ; +; -5.622 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.972 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.970 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.343 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; +; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; +; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; +; -5.618 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.344 ns ; +; -5.617 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.343 ns ; +; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; +; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; +; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; +; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; +; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.960 ns ; +; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.334 ns ; +; -5.609 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.332 ns ; +; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; +; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; +; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.329 ns ; +; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.330 ns ; +; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.330 ns ; +; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.327 ns ; +; -5.602 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.328 ns ; +; -5.599 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.325 ns ; +; -5.598 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.324 ns ; +; -5.597 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.323 ns ; +; -5.596 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.319 ns ; +; -5.594 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.944 ns ; +; -5.592 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.316 ns ; +; -5.587 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.310 ns ; +; -5.581 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.929 ns ; +; -5.580 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.928 ns ; +; -5.570 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.919 ns ; +; -5.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.292 ns ; +; -5.566 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.916 ns ; +; -5.554 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.904 ns ; +; -5.550 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.899 ns ; +; -5.546 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.614 ns ; +; -5.545 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.269 ns ; +; -5.541 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.257 ns ; +; -5.539 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.887 ns ; +; -5.539 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.564 ns ; +; -5.530 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.248 ns ; +; -5.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.876 ns ; +; -5.523 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.591 ns ; +; -5.507 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.855 ns ; +; -5.505 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.551 ns ; +; -5.500 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.850 ns ; +; -5.499 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.847 ns ; +; -5.494 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.540 ns ; +; -5.493 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.530 ns ; +; -5.491 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.516 ns ; +; -5.490 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.216 ns ; +; -5.489 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.838 ns ; +; -5.488 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.211 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.485 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.211 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.210 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; +; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.204 ns ; +; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.205 ns ; +; -5.479 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.205 ns ; +; -5.478 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.202 ns ; +; -5.476 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.199 ns ; +; -5.475 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.191 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.967 ns ; 3.497 ns ; +; -5.460 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.186 ns ; +; -5.459 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.505 ns ; +; -5.455 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.171 ns ; +; -5.453 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.176 ns ; +; -5.452 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.802 ns ; +; -5.451 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.519 ns ; +; -5.449 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.287 ns ; 3.162 ns ; +; -5.449 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.495 ns ; +; -5.448 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.796 ns ; +; -5.443 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.793 ns ; +; -5.439 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.507 ns ; +; -5.434 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.480 ns ; +; -5.429 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.779 ns ; +; -5.420 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.763 ns ; +; -5.419 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.456 ns ; +; -5.419 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.762 ns ; +; -5.415 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.658 ns ; 3.757 ns ; +; -5.400 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.436 ns ; +; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; +; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; +; -5.392 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.659 ns ; 3.733 ns ; +; -5.389 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.966 ns ; 3.423 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.096 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.294 ns ; 3.091 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.734 ns ; +; -5.375 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.411 ns ; +; -5.370 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.438 ns ; +; -5.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.093 ns ; +; -5.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.092 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.088 ns ; +; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.085 ns ; +; -5.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.084 ns ; +; -5.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.080 ns ; +; -5.357 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.403 ns ; +; -5.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.080 ns ; +; -5.355 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.703 ns ; +; -5.351 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.419 ns ; +; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.075 ns ; +; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.699 ns ; +; -5.347 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.073 ns ; +; -5.346 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.392 ns ; +; -5.344 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.070 ns ; +; -5.342 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.068 ns ; +; -5.340 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.051 ns ; +; -5.340 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.961 ns ; 3.379 ns ; +; -5.339 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.065 ns ; +; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; +; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; +; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.058 ns ; +; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.059 ns ; +; -5.334 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.057 ns ; +; -5.333 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.056 ns ; +; -5.332 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.055 ns ; +; -5.323 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.369 ns ; +; -5.321 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.037 ns ; +; -5.317 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.666 ns ; +; -5.305 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.286 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'MAIN_CLK' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; -4.261 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.318 ns ; +; -4.260 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.317 ns ; +; -4.258 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.315 ns ; +; -4.239 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.296 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.071 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~portb_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.225 ns ; 4.296 ns ; +; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; +; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; +; -3.979 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.272 ns ; 4.251 ns ; +; -3.910 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.967 ns ; +; -3.907 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.964 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.546 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.603 ns ; +; -3.544 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.601 ns ; +; -3.541 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.096 ns ; 3.637 ns ; +; -3.426 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.413 ns ; +; -3.055 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.360 ns ; 3.415 ns ; +; -3.039 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WRF_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.026 ns ; +; -2.598 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.205 ns ; 2.803 ns ; +; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; +; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; +; -2.375 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 7.143 ns ; +; -2.355 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.341 ns ; +; -2.320 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.304 ns ; +; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; +; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; +; -2.290 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 7.056 ns ; +; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; +; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; +; -2.246 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.245 ns ; +; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; +; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; +; -2.229 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.997 ns ; +; -2.209 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.195 ns ; +; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; +; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; +; -2.183 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.312 ns ; +; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; +; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.920 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; +; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; +; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; +; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; +; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; +; -2.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.905 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.133 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.119 ns ; +; -2.132 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.116 ns ; +; -2.131 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 6.118 ns ; +; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; +; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; +; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; +; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; +; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; +; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; +; -2.100 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.099 ns ; +; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; +; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.083 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.620 ns ; +; -2.062 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.830 ns ; +; -2.060 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.828 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.811 ns ; +; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|UE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.701 ns ; 5.746 ns ; +; -2.037 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.166 ns ; +; -2.035 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.573 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[3][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[4][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[5][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.017 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.568 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; +; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.799 ns ; +; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.539 ns ; 6.569 ns ; +; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.563 ns ; +; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.564 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.000 ns ; 6.022 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.013 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.551 ns ; +; -2.010 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 5.997 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.002 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.986 ns ; +; -2.001 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.985 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 5.997 ns ; +; -1.997 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.981 ns ; +; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; +; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; +; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; +; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; +; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; +; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.825 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; +; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; +; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; +; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; +; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; +; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; +; 0.832 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.790 ns ; +; 0.833 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.791 ns ; +; 1.185 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.143 ns ; +; 1.353 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.311 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.311 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.358 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.411 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.369 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.369 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; +; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; +; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; +; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.373 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; +; 1.472 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.430 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; +; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.431 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; +; 1.530 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.488 ns ; +; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; +; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; +; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; +; 1.587 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.544 ns ; +; 1.588 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.546 ns ; +; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; +; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; +; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; +; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; +; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; +; 1.645 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.602 ns ; +; 1.646 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.604 ns ; +; 1.647 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.605 ns ; +; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; +; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.650 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.607 ns ; +; 1.689 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.647 ns ; +; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; +; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; +; 1.703 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.660 ns ; +; 1.704 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.662 ns ; +; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; +; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; +; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; +; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; +; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; +; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; +; 1.743 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.701 ns ; +; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; +; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; +; 1.761 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.718 ns ; +; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; +; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; +; 1.765 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.801 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.759 ns ; +; 1.818 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.775 ns ; +; 1.819 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.776 ns ; +; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; +; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.861 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.819 ns ; +; 1.876 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.833 ns ; +; 1.877 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.834 ns ; +; 1.880 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.837 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.915 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.873 ns ; +; 1.935 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.892 ns ; +; 1.938 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.895 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.976 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.934 ns ; +; 1.993 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.950 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 2.034 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.992 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.091 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 2.049 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.147 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.104 ns ; +; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; +; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; +; 2.209 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.166 ns ; +; 2.230 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.187 ns ; +; 2.263 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.220 ns ; +; 2.325 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.282 ns ; +; 2.380 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.337 ns ; +; 2.443 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.400 ns ; +; 2.501 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.458 ns ; +; 2.559 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.516 ns ; +; 2.617 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.574 ns ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.564 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.522 ns ; +; 0.825 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; +; 0.830 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.852 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.810 ns ; +; 0.955 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.913 ns ; +; 1.357 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.358 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; +; 1.380 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.338 ns ; +; 1.415 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.416 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; +; 1.473 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.474 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; +; 1.487 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.445 ns ; +; 1.531 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.545 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.503 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.547 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.505 ns ; +; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\ADRMARK_STROBES:DDATA_AM_LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|DDATA_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.562 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.563 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.571 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.573 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.577 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.535 ns ; +; 0.580 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.538 ns ; +; 0.582 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; +; 0.584 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.542 ns ; +; 0.591 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.549 ns ; +; 0.592 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; +; 0.593 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; +; 0.608 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.566 ns ; +; 0.609 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.567 ns ; +; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; +; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; +; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; +; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; +; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; +; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; +; 0.625 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.583 ns ; +; 0.626 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.584 ns ; +; 0.627 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.585 ns ; +; 0.667 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[23] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.625 ns ; +; 0.668 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.626 ns ; +; 0.669 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.627 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[21] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.631 ns ; +; 0.675 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.679 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.639 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.681 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; +; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; +; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; +; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.649 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.691 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.652 ns ; +; 0.698 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.028 ns ; +; 0.699 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.700 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; +; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; +; 0.706 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.664 ns ; +; 0.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.666 ns ; +; 0.711 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.669 ns ; +; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; +; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.670 ns ; +; 0.714 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.673 ns ; +; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; +; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; +; 0.720 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_PRES ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.678 ns ; +; 0.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.682 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.056 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.685 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.684 ns ; +; 0.728 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.686 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.531 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.443 ns ; +; 0.536 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.403 ns ; 2.939 ns ; +; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; +; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; +; 0.541 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.453 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.459 ns ; +; 0.556 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.503 ns ; +; 0.557 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.960 ns ; 1.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.471 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.935 ns ; 1.494 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.583 ns ; 1.143 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.476 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.478 ns ; +; 0.564 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.134 ns ; +; 0.567 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.514 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.486 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.478 ns ; +; 0.576 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.505 ns ; +; 0.578 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.490 ns ; +; 0.579 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.493 ns ; +; 0.580 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.864 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.919 ns ; 1.502 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.584 ns ; 1.167 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.494 ns ; +; 0.584 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.551 ns ; +; 0.585 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.496 ns ; +; 0.586 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.500 ns ; +; 0.588 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.504 ns ; +; 0.589 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.495 ns ; +; 0.589 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.498 ns ; +; 0.590 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.504 ns ; +; 0.591 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.875 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.507 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.521 ns ; +; 0.597 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.511 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.517 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.524 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.521 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.882 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.513 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.926 ns ; 1.527 ns ; +; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.551 ns ; +; 0.608 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.524 ns ; +; 0.608 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.522 ns ; +; 0.609 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.401 ns ; 3.010 ns ; +; 0.610 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.894 ns ; +; 0.611 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.528 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.527 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.530 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.580 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.561 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; +; 0.617 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.534 ns ; +; 0.618 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.962 ns ; 1.580 ns ; +; 0.619 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.540 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.534 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.542 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.539 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.546 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.597 ns ; 1.219 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.528 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.537 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.544 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.283 ns ; 1.906 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.547 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.548 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.551 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.544 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.912 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.545 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.541 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.553 ns ; +; 0.630 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.544 ns ; +; 0.630 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.554 ns ; +; 0.631 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.545 ns ; +; 0.632 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.588 ns ; 1.220 ns ; +; 0.633 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.546 ns ; +; 0.633 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.549 ns ; +; 0.636 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.545 ns ; +; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; +; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.555 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.549 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.552 ns ; +; 0.639 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.556 ns ; +; 0.639 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.555 ns ; +; 0.641 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.558 ns ; +; 0.641 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.555 ns ; +; 0.642 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.558 ns ; +; 0.643 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.557 ns ; +; 0.644 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.558 ns ; +; 0.644 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.611 ns ; +; 0.645 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.557 ns ; +; 0.646 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.560 ns ; +; 0.646 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.586 ns ; 1.232 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.561 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.225 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.560 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.562 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.566 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.567 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.563 ns ; +; 0.650 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.568 ns ; +; 0.650 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.220 ns ; +; 0.651 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.228 ns ; +; 0.651 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.404 ns ; 3.055 ns ; +; 0.652 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.576 ns ; +; 0.653 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; +; 0.653 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; +; 0.655 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.602 ns ; +; 0.656 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.241 ns ; +; 0.656 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.938 ns ; +; 0.657 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.581 ns ; +; 0.657 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.571 ns ; +; 0.658 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.563 ns ; +; 0.658 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.572 ns ; +; 0.659 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.565 ns ; +; 0.660 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.627 ns ; +; 0.661 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.608 ns ; +; 0.661 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.575 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.577 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.574 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.576 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.580 ns ; +; 0.663 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.579 ns ; +; 0.663 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.610 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.575 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.930 ns ; 1.594 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.570 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.584 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.582 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.579 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.578 ns ; +; 0.666 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; +; 0.666 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.587 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.580 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.634 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.254 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.582 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.953 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.636 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.583 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.584 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.587 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.586 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.579 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[75] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[99] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[65] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[81] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[87] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[105] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[110] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[94] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[124] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[123] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[66] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[126] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe19a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[102] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[86] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[118] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[67] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[83] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[125] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[92] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[73] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[121] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_DDR_SYNC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.554 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[120] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; +; 0.554 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[42] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[56] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[32] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[39] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[52] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[57] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.572 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[84] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[84] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[95] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[95] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.574 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.532 ns ; +; 0.582 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[70] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[70] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.541 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; +; 0.593 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; +; 0.595 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.553 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.559 ns ; +; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.562 ns ; +; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; +; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; +; 0.643 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.340 ns ; 0.983 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 0.979 ns ; +; 0.654 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 0.988 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 1.002 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.673 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.007 ns ; +; 0.675 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[90] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; +; 0.676 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C2 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.634 ns ; +; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[88] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[97] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[85] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[100] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[93] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[114] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.681 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[98] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; +; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; +; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[41] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[49] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[44] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[33] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[61] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[43] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[54] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[91] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.649 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_N5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.693 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.651 ns ; +; 0.694 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.028 ns ; +; 0.695 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[106] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[45] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[109] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.655 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.657 ns ; +; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[78] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[78] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[53] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[82] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T4W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T5W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.703 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; +; 0.703 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; +; 0.704 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.031 ns ; +; 0.705 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.341 ns ; 1.046 ns ; +; 0.706 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.033 ns ; +; 0.707 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[51] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.665 ns ; +; 0.710 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.669 ns ; +; 0.712 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.465 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.636 ns ; +; 4.466 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.637 ns ; +; 4.467 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.638 ns ; +; 4.468 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.639 ns ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 1.825 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.508 ns ; +; 1.827 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.510 ns ; +; 1.953 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.636 ns ; +; 1.954 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.637 ns ; +; 2.134 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.315 ns ; 0.819 ns ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 3.263 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.570 ns ; +; 3.273 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.580 ns ; +; 3.460 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.363 ns ; +; 3.511 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.818 ns ; +; 3.539 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 1.845 ns ; +; 3.543 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.857 ns ; +; 3.548 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.860 ns ; +; 3.569 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 1.874 ns ; +; 3.570 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.882 ns ; +; 3.573 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.667 ns ; 1.906 ns ; +; 3.609 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 1.937 ns ; +; 3.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 1.929 ns ; +; 3.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 1.952 ns ; +; 3.656 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 1.959 ns ; +; 3.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.974 ns ; +; 3.674 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 1.983 ns ; +; 3.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 1.994 ns ; +; 3.719 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.024 ns ; +; 3.721 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.030 ns ; +; 3.730 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.032 ns ; +; 3.731 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.634 ns ; +; 3.737 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.042 ns ; +; 3.740 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.664 ns ; 2.076 ns ; +; 3.745 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.668 ns ; 2.077 ns ; +; 3.754 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.059 ns ; +; 3.769 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.672 ns ; +; 3.774 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.077 ns ; +; 3.776 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.091 ns ; +; 3.777 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.079 ns ; +; 3.778 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.085 ns ; +; 3.780 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.084 ns ; +; 3.781 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.097 ns ; +; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.089 ns ; +; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.100 ns ; +; 3.786 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.097 ns ; +; 3.792 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.693 ns ; +; 3.794 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 2.102 ns ; +; 3.796 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.107 ns ; +; 3.811 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.125 ns ; +; 3.814 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 2.126 ns ; +; 3.819 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.122 ns ; +; 3.836 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.141 ns ; +; 3.838 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.735 ns ; +; 3.839 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.738 ns ; +; 3.855 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.755 ns ; +; 3.866 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.763 ns ; +; 3.899 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.205 ns ; +; 3.902 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.203 ns ; +; 3.906 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.722 ns ; 2.184 ns ; +; 3.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.812 ns ; +; 3.920 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.234 ns ; +; 3.932 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.246 ns ; +; 3.933 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.613 ns ; 2.320 ns ; +; 3.935 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.239 ns ; +; 3.936 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.837 ns ; +; 3.944 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.250 ns ; +; 3.951 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.851 ns ; +; 3.973 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.872 ns ; +; 3.979 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.283 ns ; +; 3.989 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.296 ns ; +; 4.004 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.904 ns ; +; 4.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.931 ns ; +; 4.042 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.683 ns ; 2.359 ns ; +; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.358 ns ; +; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.344 ns ; +; 4.048 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.352 ns ; +; 4.078 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.978 ns ; +; 4.084 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.980 ns ; +; 4.096 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.998 ns ; +; 4.110 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 4.006 ns ; +; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.371 ns ; +; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.423 ns ; +; 4.115 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.012 ns ; +; 4.117 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.014 ns ; +; 4.132 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 4.035 ns ; +; 4.168 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.429 ns ; +; 4.169 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.470 ns ; +; 4.185 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.454 ns ; +; 4.187 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.723 ns ; 2.464 ns ; +; 4.195 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.431 ns ; +; 4.196 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.713 ns ; 2.483 ns ; +; 4.201 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.447 ns ; +; 4.221 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.714 ns ; 2.507 ns ; +; 4.231 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.614 ns ; 2.617 ns ; +; 4.232 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.133 ns ; +; 4.232 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.558 ns ; +; 4.235 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.132 ns ; +; 4.236 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.134 ns ; +; 4.239 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.673 ns ; 2.566 ns ; +; 4.243 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.479 ns ; +; 4.249 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.669 ns ; 2.580 ns ; +; 4.251 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.152 ns ; +; 4.269 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.170 ns ; +; 4.283 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.185 ns ; +; 4.286 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.188 ns ; +; 4.296 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.626 ns ; +; 4.313 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.666 ns ; 2.647 ns ; +; 4.314 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.623 ns ; +; 4.331 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.596 ns ; +; 4.333 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.188 ns ; +; 4.343 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.198 ns ; +; 4.347 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.665 ns ; 2.682 ns ; +; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.254 ns ; +; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.252 ns ; +; 4.362 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.717 ns ; 2.645 ns ; +; 4.367 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.608 ns ; +; 4.376 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.635 ns ; +; 4.384 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.282 ns ; +; 4.406 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.791 ns ; +; 4.409 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.645 ns ; +; 4.410 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.646 ns ; +; 4.411 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.252 ns ; +; 4.417 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.671 ns ; +; 4.425 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.325 ns ; +; 4.431 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.761 ns ; +; 4.434 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.695 ns ; +; 4.440 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.685 ns ; +; 4.450 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.719 ns ; +; 4.475 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.734 ns ; +; 4.477 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.805 ns ; +; 4.478 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 2.748 ns ; +; 4.480 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.757 ns ; 2.723 ns ; +; 4.485 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.736 ns ; +; 4.486 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.814 ns ; +; 4.497 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.351 ns ; +; 4.498 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.329 ns ; +; 4.527 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.773 ns ; +; 4.530 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.791 ns ; +; 4.555 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.804 ns ; +; 4.556 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.393 ns ; +; 4.573 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.818 ns ; +; 4.587 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.972 ns ; +; 4.597 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.429 ns ; +; 4.600 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.865 ns ; +; 4.601 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.852 ns ; +; 4.601 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.433 ns ; +; 4.613 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.939 ns ; +; 4.614 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.855 ns ; +; 4.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.867 ns ; +; 4.623 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.464 ns ; +; 4.626 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 2.884 ns ; +; 4.630 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 2.890 ns ; +; 4.633 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.874 ns ; +; 4.636 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.150 ns ; 4.486 ns ; +; 4.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.906 ns ; +; 4.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.911 ns ; +; 4.670 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.517 ns ; +; 4.671 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.507 ns ; +; 4.676 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.912 ns ; +; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 2.932 ns ; +; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.913 ns ; +; 4.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.940 ns ; +; 4.690 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 2.964 ns ; +; 4.697 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.529 ns ; +; 4.699 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.874 ns ; 1.825 ns ; +; 4.704 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.949 ns ; +; 4.709 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.664 ns ; 3.045 ns ; +; 4.722 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.991 ns ; +; 4.749 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.603 ns ; +; 4.753 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.004 ns ; +; 4.780 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.625 ns ; +; 4.787 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.631 ns ; +; 4.791 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.638 ns ; +; 4.805 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 3.075 ns ; +; 4.809 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.640 ns ; +; 4.823 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.072 ns ; +; 4.825 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.662 ns ; +; 4.840 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.712 ns ; 3.128 ns ; +; 4.844 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 3.109 ns ; +; 4.844 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.689 ns ; +; 4.845 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.691 ns ; +; 4.846 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.700 ns ; +; 4.863 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 3.108 ns ; +; 4.869 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.131 ns ; +; 4.871 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.122 ns ; +; 4.878 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.725 ns ; +; 4.881 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.712 ns ; +; 4.885 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.134 ns ; +; 4.888 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.732 ns ; +; 4.892 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.147 ns ; 4.745 ns ; +; 4.892 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 3.150 ns ; +; 4.896 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 3.156 ns ; +; 4.906 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 3.175 ns ; +; 4.916 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.866 ns ; 2.050 ns ; +; 4.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.151 ns ; 4.765 ns ; +; 4.924 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.175 ns ; +; 4.942 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 3.197 ns ; +; 4.979 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.160 ns ; 4.819 ns ; +; 5.007 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 3.253 ns ; +; 5.009 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 3.250 ns ; +; 5.013 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 3.287 ns ; +; 5.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.865 ns ; +; 5.047 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 3.308 ns ; +; 5.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.869 ns ; 2.219 ns ; +; 5.096 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.933 ns ; 2.163 ns ; +; 5.124 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.970 ns ; +; 5.133 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.395 ns ; +; 5.143 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.722 ns ; 3.421 ns ; +; 5.166 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.428 ns ; +; 5.205 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.720 ns ; 3.485 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.679 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.232 ns ; +; 2.684 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.237 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; +; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; +; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.948 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -1.264 ns ; -1.316 ns ; 1.632 ns ; +; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; +; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; +; 3.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.042 ns ; 3.046 ns ; +; 3.100 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.656 ns ; +; 3.146 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.316 ns ; 2.830 ns ; +; 6.237 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.309 ns ; 1.928 ns ; +; 6.282 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.386 ns ; 1.896 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.218 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.355 ns ; 2.863 ns ; +; 7.413 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.763 ns ; +; 7.427 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.777 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.686 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.470 ns ; 3.216 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 1.487 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.443 ns ; +; 1.492 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.447 ns ; 2.939 ns ; +; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; +; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; +; 1.497 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.453 ns ; +; 1.507 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.459 ns ; +; 1.512 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.503 ns ; +; 1.513 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.004 ns ; 1.517 ns ; +; 1.515 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.471 ns ; +; 1.515 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.021 ns ; 1.494 ns ; +; 1.516 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.373 ns ; 1.143 ns ; +; 1.516 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.476 ns ; +; 1.517 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.478 ns ; +; 1.520 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.134 ns ; +; 1.523 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.514 ns ; +; 1.526 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.486 ns ; +; 1.529 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.478 ns ; +; 1.532 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.505 ns ; +; 1.534 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.490 ns ; +; 1.535 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.493 ns ; +; 1.536 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.864 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.037 ns ; 1.502 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.372 ns ; 1.167 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.494 ns ; +; 1.540 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.551 ns ; +; 1.541 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.496 ns ; +; 1.542 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.500 ns ; +; 1.544 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.504 ns ; +; 1.545 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.495 ns ; +; 1.545 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.498 ns ; +; 1.546 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.504 ns ; +; 1.547 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.875 ns ; +; 1.548 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.507 ns ; +; 1.548 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.521 ns ; +; 1.553 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.511 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.517 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.524 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.521 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.882 ns ; +; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.513 ns ; +; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.030 ns ; 1.527 ns ; +; 1.560 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.551 ns ; +; 1.564 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.524 ns ; +; 1.564 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.522 ns ; +; 1.565 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.445 ns ; 3.010 ns ; +; 1.566 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.894 ns ; +; 1.567 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.528 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.527 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.530 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.580 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.561 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; +; 1.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.534 ns ; +; 1.574 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.006 ns ; 1.580 ns ; +; 1.575 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.540 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.534 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.542 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.539 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.546 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.359 ns ; 1.219 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.528 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.537 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.544 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.906 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.547 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.548 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.551 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.544 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.912 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.545 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.541 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.553 ns ; +; 1.586 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.544 ns ; +; 1.586 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.554 ns ; +; 1.587 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.545 ns ; +; 1.588 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.368 ns ; 1.220 ns ; +; 1.589 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.546 ns ; +; 1.589 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.549 ns ; +; 1.592 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.545 ns ; +; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; +; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.555 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.549 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.552 ns ; +; 1.595 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.556 ns ; +; 1.595 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.555 ns ; +; 1.597 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.558 ns ; +; 1.597 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.555 ns ; +; 1.598 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.558 ns ; +; 1.599 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.557 ns ; +; 1.600 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.558 ns ; +; 1.600 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.611 ns ; +; 1.601 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.557 ns ; +; 1.602 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.560 ns ; +; 1.602 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.370 ns ; 1.232 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.561 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.225 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.560 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.562 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.566 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.567 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.563 ns ; +; 1.606 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.568 ns ; +; 1.606 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.220 ns ; +; 1.607 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.228 ns ; +; 1.607 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.448 ns ; 3.055 ns ; +; 1.608 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.576 ns ; +; 1.609 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; +; 1.609 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; +; 1.611 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.602 ns ; +; 1.612 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.241 ns ; +; 1.612 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.938 ns ; +; 1.613 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.581 ns ; +; 1.613 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.571 ns ; +; 1.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.563 ns ; +; 1.614 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.572 ns ; +; 1.615 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.565 ns ; +; 1.616 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.627 ns ; +; 1.617 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.608 ns ; +; 1.617 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.575 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.577 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.574 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.576 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.580 ns ; +; 1.619 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.579 ns ; +; 1.619 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.610 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.575 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.026 ns ; 1.594 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.570 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.584 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.582 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.579 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.578 ns ; +; 1.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; +; 1.622 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.587 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.580 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.634 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.254 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.582 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.953 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.636 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.583 ns ; +; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.584 ns ; +; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.587 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.586 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.579 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.585 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'CLK33M' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; 0.298 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.443 ns ; +; 0.303 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.636 ns ; 2.939 ns ; +; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; +; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; +; 0.308 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.453 ns ; +; 0.318 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.459 ns ; +; 0.323 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.503 ns ; +; 0.324 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.193 ns ; 1.517 ns ; +; 0.326 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.471 ns ; +; 0.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; CLK33M ; CLK33M ; 0.000 ns ; 1.168 ns ; 1.494 ns ; +; 0.327 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 0.816 ns ; 1.143 ns ; +; 0.327 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.476 ns ; +; 0.328 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.478 ns ; +; 0.331 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.134 ns ; +; 0.334 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.514 ns ; +; 0.337 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.486 ns ; +; 0.340 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.478 ns ; +; 0.343 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.505 ns ; +; 0.345 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.490 ns ; +; 0.346 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.493 ns ; +; 0.347 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.864 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.152 ns ; 1.502 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 0.817 ns ; 1.167 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.494 ns ; +; 0.351 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.551 ns ; +; 0.352 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.496 ns ; +; 0.353 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.500 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.504 ns ; +; 0.356 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.495 ns ; +; 0.356 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.498 ns ; +; 0.357 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.504 ns ; +; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.875 ns ; +; 0.359 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.507 ns ; +; 0.359 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.521 ns ; +; 0.364 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.511 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.517 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.524 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.521 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.882 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.513 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.159 ns ; 1.527 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.551 ns ; +; 0.375 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.524 ns ; +; 0.375 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.522 ns ; +; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.634 ns ; 3.010 ns ; +; 0.377 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.894 ns ; +; 0.378 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.528 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.527 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.530 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.580 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.561 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; +; 0.384 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.534 ns ; +; 0.385 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.195 ns ; 1.580 ns ; +; 0.386 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.540 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.534 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.542 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.539 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.546 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; CLK33M ; CLK33M ; 0.000 ns ; 0.830 ns ; 1.219 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.528 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.537 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.544 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.516 ns ; 1.906 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.547 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.548 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.551 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.544 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.912 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.545 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.541 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.553 ns ; +; 0.397 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.544 ns ; +; 0.397 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.554 ns ; +; 0.398 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.545 ns ; +; 0.399 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; CLK33M ; CLK33M ; 0.000 ns ; 0.821 ns ; 1.220 ns ; +; 0.400 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.546 ns ; +; 0.400 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.549 ns ; +; 0.403 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.545 ns ; +; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; +; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.555 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.549 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.552 ns ; +; 0.406 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.556 ns ; +; 0.406 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.555 ns ; +; 0.408 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.558 ns ; +; 0.408 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.555 ns ; +; 0.409 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.558 ns ; +; 0.410 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.557 ns ; +; 0.411 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.558 ns ; +; 0.411 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.611 ns ; +; 0.412 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.557 ns ; +; 0.413 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.560 ns ; +; 0.413 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; CLK33M ; CLK33M ; 0.000 ns ; 0.819 ns ; 1.232 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.561 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.225 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.560 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.562 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.566 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.567 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.563 ns ; +; 0.417 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.568 ns ; +; 0.417 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.220 ns ; +; 0.418 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.228 ns ; +; 0.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; CLK33M ; CLK33M ; 0.000 ns ; 2.637 ns ; 3.055 ns ; +; 0.419 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.576 ns ; +; 0.420 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; +; 0.420 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; +; 0.422 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.602 ns ; +; 0.423 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.241 ns ; +; 0.423 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.938 ns ; +; 0.424 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.581 ns ; +; 0.424 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.571 ns ; +; 0.425 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.563 ns ; +; 0.425 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.572 ns ; +; 0.426 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.565 ns ; +; 0.427 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.627 ns ; +; 0.428 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.608 ns ; +; 0.428 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.575 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.577 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.574 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.576 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.580 ns ; +; 0.430 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.579 ns ; +; 0.430 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.610 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.575 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.163 ns ; 1.594 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.570 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.584 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.582 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.579 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.578 ns ; +; 0.433 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; +; 0.433 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.587 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.580 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.634 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.254 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.582 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.953 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.636 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.583 ns ; +; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.584 ns ; +; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.587 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.586 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.579 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.585 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'MAIN_CLK' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; -3.786 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.716 ns ; 1.930 ns ; +; -3.611 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.756 ns ; 2.145 ns ; +; -3.448 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 2.261 ns ; +; -3.293 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.327 ns ; 1.034 ns ; +; -3.012 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.694 ns ; +; -2.912 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.794 ns ; +; -2.048 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 1.692 ns ; +; -1.996 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.147 ns ; +; -1.985 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.371 ns ; +; -1.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.104 ns ; 1.143 ns ; +; -1.958 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.184 ns ; +; -1.934 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.422 ns ; +; -1.923 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.433 ns ; +; -1.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.276 ns ; +; -1.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.514 ns ; +; -1.835 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.555 ns ; +; -1.795 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.597 ns ; +; -1.749 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.641 ns ; +; -1.745 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.647 ns ; +; -1.641 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.348 ns ; 1.707 ns ; +; -1.595 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.204 ns ; 1.609 ns ; +; -1.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.573 ns ; +; -1.508 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.111 ns ; 1.603 ns ; +; -1.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe31 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.398 ns ; 2.048 ns ; +; -1.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.623 ns ; 2.297 ns ; +; -1.242 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.145 ns ; 1.903 ns ; +; -1.234 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.973 ns ; 0.739 ns ; +; -1.159 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 1.922 ns ; +; -1.152 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe35 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 1.989 ns ; +; -1.113 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 2.627 ns ; +; -1.095 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.046 ns ; +; -1.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe19 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.362 ns ; 2.290 ns ; +; -1.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.086 ns ; +; -1.001 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.966 ns ; 0.965 ns ; +; -0.993 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 1.310 ns ; +; -0.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.120 ns ; +; -0.918 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.364 ns ; 2.446 ns ; +; -0.893 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.457 ns ; +; -0.849 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.714 ns ; +; -0.825 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.266 ns ; +; -0.819 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.261 ns ; +; -0.770 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.310 ns ; +; -0.743 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.436 ns ; +; -0.742 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.437 ns ; +; -0.692 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.089 ns ; 2.397 ns ; +; -0.675 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.521 ns ; 2.846 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.668 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 2.975 ns ; +; -0.658 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.905 ns ; +; -0.655 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.908 ns ; +; -0.591 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.490 ns ; +; -0.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.731 ns ; +; -0.553 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.296 ns ; 1.743 ns ; +; -0.530 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.033 ns ; +; -0.447 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.903 ns ; +; -0.441 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.090 ns ; 1.649 ns ; +; -0.422 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.878 ns ; +; -0.420 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.880 ns ; +; -0.407 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.684 ns ; +; -0.353 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.210 ns ; +; -0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.980 ns ; +; -0.319 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.981 ns ; +; -0.198 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.328 ns ; +; -0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 5.525 ns ; +; -0.155 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.216 ns ; 3.061 ns ; +; -0.143 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 3.990 ns ; +; -0.133 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.585 ns ; +; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.007 ns ; +; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.685 ns ; 5.559 ns ; +; -0.125 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.004 ns ; +; -0.116 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.017 ns ; +; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.593 ns ; +; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.314 ns ; +; -0.092 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.037 ns ; +; -0.070 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.815 ns ; +; -0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.214 ns ; 3.147 ns ; +; -0.065 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.784 ns ; +; -0.060 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 3.857 ns ; +; -0.059 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe21 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.363 ns ; 3.304 ns ; +; -0.046 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.311 ns ; 4.265 ns ; +; -0.025 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.665 ns ; +; -0.022 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.389 ns ; +; -0.006 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.030 ns ; +; 0.007 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.760 ns ; 3.767 ns ; +; 0.026 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.715 ns ; +; 0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.593 ns ; +; 0.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.598 ns ; +; 0.091 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.728 ns ; +; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.978 ns ; +; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.961 ns ; 1.054 ns ; +; 0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.133 ns ; +; 0.104 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.822 ns ; +; 0.118 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.761 ns ; +; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; +; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; +; 0.121 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.719 ns ; +; 0.123 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.972 ns ; +; 0.132 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.083 ns ; 2.215 ns ; +; 0.150 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.815 ns ; 3.965 ns ; +; 0.151 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.280 ns ; +; 0.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.228 ns ; 1.386 ns ; +; 0.167 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.470 ns ; +; 0.168 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.817 ns ; 3.985 ns ; +; 0.177 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.357 ns ; 2.534 ns ; +; 0.181 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.870 ns ; +; 0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.017 ns ; 6.201 ns ; +; 0.186 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.615 ns ; 3.801 ns ; +; 0.188 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 4.037 ns ; +; 0.191 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.323 ns ; +; 0.192 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.324 ns ; +; 0.195 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.693 ns ; +; 0.216 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.685 ns ; 3.901 ns ; +; 0.226 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.824 ns ; +; 0.231 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.938 ns ; +; 0.235 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.013 ns ; 6.248 ns ; +; 0.243 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.459 ns ; 3.702 ns ; +; 0.261 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.177 ns ; +; 0.262 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.178 ns ; +; 0.265 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.397 ns ; +; 0.266 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.973 ns ; +; 0.291 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 4.208 ns ; +; 0.311 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.722 ns ; +; 0.313 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.443 ns ; +; 0.314 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.447 ns ; +; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.813 ns ; +; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.033 ns ; 2.348 ns ; +; 0.318 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.621 ns ; 2.939 ns ; +; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; +; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; +; 0.323 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.453 ns ; +; 0.324 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.768 ns ; 6.092 ns ; +; 0.333 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.126 ns ; 1.459 ns ; +; 0.338 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.503 ns ; +; 0.339 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.178 ns ; 1.517 ns ; +; 0.341 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.471 ns ; +; 0.341 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.153 ns ; 1.494 ns ; +; 0.342 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.801 ns ; 1.143 ns ; +; 0.342 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.476 ns ; +; 0.343 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.478 ns ; +; 0.344 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.981 ns ; +; 0.346 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.788 ns ; 1.134 ns ; +; 0.347 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.990 ns ; +; 0.349 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.514 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.653 ns ; +; 0.352 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.486 ns ; +; 0.354 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.067 ns ; 6.421 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.123 ns ; 1.478 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.853 ns ; +; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.505 ns ; +; 0.360 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.490 ns ; +; 0.360 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.771 ns ; +; 0.361 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.493 ns ; +; 0.362 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.864 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.137 ns ; 1.502 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.802 ns ; 1.167 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.494 ns ; +; 0.366 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.185 ns ; 1.551 ns ; +; 0.366 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.747 ns ; 6.113 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.496 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.868 ns ; 1.235 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.746 ns ; 6.113 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.500 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.264 ns ; 4.632 ns ; +; 0.370 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.504 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.124 ns ; 1.495 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.127 ns ; 1.498 ns ; +; 0.372 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.504 ns ; +; 0.373 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.875 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.133 ns ; 1.507 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 6.080 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.521 ns ; +; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 6.066 ns ; +; 0.379 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.511 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.460 ns ; 3.841 ns ; +; 0.382 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.517 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; MAIN_CLK ; +; -4.169 ns ; 1.000 ns ; 5.169 ns ; VD[19] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; MAIN_CLK ; +; -4.134 ns ; 1.000 ns ; 5.134 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -4.083 ns ; 1.000 ns ; 5.083 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.956 ns ; 1.000 ns ; 4.956 ns ; VD[27] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; MAIN_CLK ; +; -3.930 ns ; 1.000 ns ; 4.930 ns ; nINDEX ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; +; -3.930 ns ; 1.000 ns ; 4.930 ns ; VD[31] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; MAIN_CLK ; +; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[1] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; MAIN_CLK ; +; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[9] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; MAIN_CLK ; +; -3.913 ns ; 1.000 ns ; 4.913 ns ; VD[2] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; MAIN_CLK ; +; -3.912 ns ; 1.000 ns ; 4.912 ns ; VD[12] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.885 ns ; 1.000 ns ; 4.885 ns ; VD[20] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; MAIN_CLK ; +; -3.883 ns ; 1.000 ns ; 4.883 ns ; VD[25] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.859 ns ; 1.000 ns ; 4.859 ns ; VD[28] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; MAIN_CLK ; +; -3.855 ns ; 1.000 ns ; 4.855 ns ; VD[22] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; MAIN_CLK ; +; -3.851 ns ; 1.000 ns ; 4.851 ns ; VD[17] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.827 ns ; 1.000 ns ; 4.827 ns ; VD[11] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.804 ns ; 1.000 ns ; 4.804 ns ; VD[0] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; MAIN_CLK ; +; -3.801 ns ; 1.000 ns ; 4.801 ns ; VD[10] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; MAIN_CLK ; +; -3.796 ns ; 1.000 ns ; 4.796 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; MAIN_CLK ; +; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; MAIN_CLK ; +; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; MAIN_CLK ; +; -3.783 ns ; 1.000 ns ; 4.783 ns ; VD[14] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.765 ns ; 1.000 ns ; 4.765 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.752 ns ; 1.000 ns ; 4.752 ns ; VD[6] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.744 ns ; 1.000 ns ; 4.744 ns ; VD[21] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; MAIN_CLK ; +; -3.742 ns ; 1.000 ns ; 4.742 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.740 ns ; 1.000 ns ; 4.740 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.740 ns ; 1.000 ns ; 4.740 ns ; VD[16] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; MAIN_CLK ; +; -3.739 ns ; 1.000 ns ; 4.739 ns ; VD[29] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; MAIN_CLK ; +; -3.735 ns ; 1.000 ns ; 4.735 ns ; VD[15] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; MAIN_CLK ; +; -3.708 ns ; 1.000 ns ; 4.708 ns ; VD[26] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; MAIN_CLK ; +; -3.707 ns ; 1.000 ns ; 4.707 ns ; VD[13] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.703 ns ; 1.000 ns ; 4.703 ns ; VD[3] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; MAIN_CLK ; +; -3.699 ns ; 1.000 ns ; 4.699 ns ; VD[30] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; MAIN_CLK ; +; -3.694 ns ; 1.000 ns ; 4.694 ns ; VD[24] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.680 ns ; 1.000 ns ; 4.680 ns ; FB_AD[30] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.634 ns ; 1.000 ns ; 4.634 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.471 ns ; 1.000 ns ; 4.471 ns ; VD[4] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.386 ns ; 1.000 ns ; 4.386 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; +; -3.339 ns ; 1.000 ns ; 4.339 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.334 ns ; 1.000 ns ; 4.334 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; CLK33M ; +; -3.324 ns ; 1.000 ns ; 4.324 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.290 ns ; 1.000 ns ; 4.290 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.272 ns ; 1.000 ns ; 4.272 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.248 ns ; 1.000 ns ; 4.248 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; CLK33M ; +; -3.245 ns ; 1.000 ns ; 4.245 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.236 ns ; 1.000 ns ; 4.236 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.218 ns ; 1.000 ns ; 4.218 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.211 ns ; 1.000 ns ; 4.211 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; +; -3.208 ns ; 1.000 ns ; 4.208 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.206 ns ; 1.000 ns ; 4.206 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.203 ns ; 1.000 ns ; 4.203 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.199 ns ; 1.000 ns ; 4.199 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.197 ns ; 1.000 ns ; 4.197 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.194 ns ; 1.000 ns ; 4.194 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.193 ns ; 1.000 ns ; 4.193 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.190 ns ; 1.000 ns ; 4.190 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.187 ns ; 1.000 ns ; 4.187 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.182 ns ; 1.000 ns ; 4.182 ns ; HD_DD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[1] ; CLK33M ; +; -3.181 ns ; 1.000 ns ; 4.181 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.174 ns ; 1.000 ns ; 4.174 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.173 ns ; 1.000 ns ; 4.173 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.172 ns ; 1.000 ns ; 4.172 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.171 ns ; 1.000 ns ; 4.171 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.167 ns ; 1.000 ns ; 4.167 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.162 ns ; 1.000 ns ; 4.162 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.160 ns ; 1.000 ns ; 4.160 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tco ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ +; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; +; -14.829 ns ; 1.000 ns ; 15.829 ns ; interrupt_handler:nobody|INT_LATCH[9] ; nIRQ[5] ; MAIN_CLK ; +; -13.764 ns ; 1.000 ns ; 14.764 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[8] ; MAIN_CLK ; +; -13.654 ns ; 1.000 ns ; 14.654 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[9] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[29] ; MAIN_CLK ; +; -13.575 ns ; 1.000 ns ; 14.575 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[29] ; MAIN_CLK ; +; -13.493 ns ; 1.000 ns ; 14.493 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[18] ; MAIN_CLK ; +; -13.477 ns ; 1.000 ns ; 14.477 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[18] ; MAIN_CLK ; +; -13.457 ns ; 1.000 ns ; 14.457 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; FB_AD[18] ; MAIN_CLK ; +; -13.418 ns ; 1.000 ns ; 14.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.386 ns ; 1.000 ns ; 14.386 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; FB_AD[7] ; MAIN_CLK ; +; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[18] ; MAIN_CLK ; +; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[18] ; MAIN_CLK ; +; -13.309 ns ; 1.000 ns ; 14.309 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[27] ; MAIN_CLK ; +; -13.294 ns ; 1.000 ns ; 14.294 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; FB_AD[27] ; MAIN_CLK ; +; -13.259 ns ; 1.000 ns ; 14.259 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.250 ns ; 1.000 ns ; 14.250 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.227 ns ; 1.000 ns ; 14.227 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.207 ns ; 1.000 ns ; 14.207 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[18] ; MAIN_CLK ; +; -13.171 ns ; 1.000 ns ; 14.171 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.170 ns ; 1.000 ns ; 14.170 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; FB_AD[27] ; MAIN_CLK ; +; -13.157 ns ; 1.000 ns ; 14.157 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.028 ns ; 1.000 ns ; 14.028 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[27] ; MAIN_CLK ; +; -13.015 ns ; 1.000 ns ; 14.015 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; FB_AD[27] ; MAIN_CLK ; +; -12.999 ns ; 1.000 ns ; 13.999 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.921 ns ; 1.000 ns ; 13.921 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.886 ns ; 1.000 ns ; 13.886 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.876 ns ; 1.000 ns ; 13.876 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.861 ns ; 1.000 ns ; 13.861 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; FB_AD[27] ; MAIN_CLK ; +; -12.846 ns ; 1.000 ns ; 13.846 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[27] ; MAIN_CLK ; +; -12.836 ns ; 1.000 ns ; 13.836 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.823 ns ; 1.000 ns ; 13.823 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.817 ns ; 1.000 ns ; 13.817 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; FB_AD[27] ; MAIN_CLK ; +; -12.784 ns ; 1.000 ns ; 13.784 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[27] ; MAIN_CLK ; +; -12.732 ns ; 1.000 ns ; 13.732 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.620 ns ; 1.000 ns ; 13.620 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.567 ns ; 1.000 ns ; 13.567 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; FB_AD[27] ; MAIN_CLK ; +; -12.434 ns ; 1.000 ns ; 13.434 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.425 ns ; 1.000 ns ; 13.425 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[7] ; MAIN_CLK ; +; -12.404 ns ; 1.000 ns ; 13.404 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[8] ; MAIN_CLK ; +; -12.403 ns ; 1.000 ns ; 13.403 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; FB_AD[23] ; MAIN_CLK ; +; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.302 ns ; 1.000 ns ; 13.302 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4] ; FB_AD[7] ; MAIN_CLK ; +; -12.301 ns ; 1.000 ns ; 13.301 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27] ; FB_AD[27] ; MAIN_CLK ; +; -12.300 ns ; 1.000 ns ; 13.300 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.286 ns ; 1.000 ns ; 13.286 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.285 ns ; 1.000 ns ; 13.285 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.283 ns ; 1.000 ns ; 13.283 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; FB_AD[7] ; CLK33M ; +; -12.260 ns ; 1.000 ns ; 13.260 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.241 ns ; 1.000 ns ; 13.241 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.219 ns ; 1.000 ns ; 13.219 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.211 ns ; 1.000 ns ; 13.211 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.205 ns ; 1.000 ns ; 13.205 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[27] ; MAIN_CLK ; +; -12.200 ns ; 1.000 ns ; 13.200 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.186 ns ; 1.000 ns ; 13.186 ns ; interrupt_handler:nobody|WERTE[2][0] ; FB_AD[18] ; MAIN_CLK ; +; -12.182 ns ; 1.000 ns ; 13.182 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; FB_AD[22] ; MAIN_CLK ; +; -12.177 ns ; 1.000 ns ; 13.177 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[18] ; MAIN_CLK ; +; -12.175 ns ; 1.000 ns ; 13.175 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.173 ns ; 1.000 ns ; 13.173 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[17] ; MAIN_CLK ; +; -12.166 ns ; 1.000 ns ; 13.166 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.158 ns ; 1.000 ns ; 13.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.157 ns ; 1.000 ns ; 13.157 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[17] ; MAIN_CLK ; +; -12.082 ns ; 1.000 ns ; 13.082 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.055 ns ; 1.000 ns ; 13.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; FB_AD[21] ; MAIN_CLK ; +; -12.052 ns ; 1.000 ns ; 13.052 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; FB_AD[17] ; MAIN_CLK ; +; -12.039 ns ; 1.000 ns ; 13.039 ns ; interrupt_handler:nobody|ACP_CONF[28] ; FB_AD[7] ; MAIN_CLK ; +; -12.038 ns ; 1.000 ns ; 13.038 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[17] ; MAIN_CLK ; +; -12.022 ns ; 1.000 ns ; 13.022 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.008 ns ; 1.000 ns ; 13.008 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QB ; MAIN_CLK ; +; -12.005 ns ; 1.000 ns ; 13.005 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_DOUT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.004 ns ; 1.000 ns ; 13.004 ns ; interrupt_handler:nobody|WERTE[2][62] ; FB_AD[18] ; MAIN_CLK ; +; -11.984 ns ; 1.000 ns ; 12.984 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[27] ; MAIN_CLK ; +; -11.978 ns ; 1.000 ns ; 12.978 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; YM_QB ; MAIN_CLK ; +; -11.968 ns ; 1.000 ns ; 12.968 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.957 ns ; 1.000 ns ; 12.957 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[7] ; MAIN_CLK ; +; -11.946 ns ; 1.000 ns ; 12.946 ns ; interrupt_handler:nobody|WERTE[2][42] ; FB_AD[18] ; MAIN_CLK ; +; -11.939 ns ; 1.000 ns ; 12.939 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[17] ; MAIN_CLK ; +; -11.938 ns ; 1.000 ns ; 12.938 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; YM_QB ; MAIN_CLK ; +; -11.937 ns ; 1.000 ns ; 12.937 ns ; interrupt_handler:nobody|WERTE[2][10] ; FB_AD[18] ; MAIN_CLK ; +; -11.935 ns ; 1.000 ns ; 12.935 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[9] ; MAIN_CLK ; +; -11.933 ns ; 1.000 ns ; 12.933 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[18] ; MAIN_CLK ; +; -11.924 ns ; 1.000 ns ; 12.924 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[26] ; MAIN_CLK ; +; -11.922 ns ; 1.000 ns ; 12.922 ns ; interrupt_handler:nobody|WERTE[2][58] ; FB_AD[18] ; MAIN_CLK ; +; -11.900 ns ; 1.000 ns ; 12.900 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[17] ; MAIN_CLK ; +; -11.874 ns ; 1.000 ns ; 12.874 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.871 ns ; 1.000 ns ; 12.871 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[20] ; MAIN_CLK ; +; -11.867 ns ; 1.000 ns ; 12.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.859 ns ; 1.000 ns ; 12.859 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[7] ; MAIN_CLK ; +; -11.857 ns ; 1.000 ns ; 12.857 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.845 ns ; 1.000 ns ; 12.845 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[17] ; MAIN_CLK ; +; -11.842 ns ; 1.000 ns ; 12.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; FB_AD[20] ; MAIN_CLK ; +; -11.834 ns ; 1.000 ns ; 12.834 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[20] ; MAIN_CLK ; +; -11.831 ns ; 1.000 ns ; 12.831 ns ; interrupt_handler:nobody|WERTE[2][4] ; FB_AD[18] ; MAIN_CLK ; +; -11.813 ns ; 1.000 ns ; 12.813 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; FB_AD[18] ; MAIN_CLK ; +; -11.794 ns ; 1.000 ns ; 12.794 ns ; interrupt_handler:nobody|WERTE[2][43] ; FB_AD[18] ; MAIN_CLK ; +; -11.787 ns ; 1.000 ns ; 12.787 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[18] ; MAIN_CLK ; +; -11.775 ns ; 1.000 ns ; 12.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[7] ; MAIN_CLK ; +; -11.774 ns ; 1.000 ns ; 12.774 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[27] ; MAIN_CLK ; +; -11.769 ns ; 1.000 ns ; 12.769 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[18] ; MAIN_CLK ; +; -11.762 ns ; 1.000 ns ; 12.762 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.751 ns ; 1.000 ns ; 12.751 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; YM_QC ; MAIN_CLK ; +; -11.747 ns ; 1.000 ns ; 12.747 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.746 ns ; 1.000 ns ; 12.746 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.736 ns ; 1.000 ns ; 12.736 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[7] ; MAIN_CLK ; +; -11.727 ns ; 1.000 ns ; 12.727 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.725 ns ; 1.000 ns ; 12.725 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.VECTOR_OUT ; FB_AD[7] ; MAIN_CLK ; +; -11.724 ns ; 1.000 ns ; 12.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; YM_QC ; MAIN_CLK ; +; -11.721 ns ; 1.000 ns ; 12.721 ns ; interrupt_handler:nobody|WERTE[5][8] ; FB_AD[21] ; MAIN_CLK ; +; -11.717 ns ; 1.000 ns ; 12.717 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[23] ; MAIN_CLK ; +; -11.710 ns ; 1.000 ns ; 12.710 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[9] ; MAIN_CLK ; +; -11.709 ns ; 1.000 ns ; 12.709 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[18] ; MAIN_CLK ; +; -11.708 ns ; 1.000 ns ; 12.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.700 ns ; 1.000 ns ; 12.700 ns ; interrupt_handler:nobody|WERTE[2][2] ; FB_AD[18] ; MAIN_CLK ; +; -11.694 ns ; 1.000 ns ; 12.694 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[28] ; MAIN_CLK ; +; -11.693 ns ; 1.000 ns ; 12.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[9] ; MAIN_CLK ; +; -11.692 ns ; 1.000 ns ; 12.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[18] ; MAIN_CLK ; +; -11.680 ns ; 1.000 ns ; 12.680 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.675 ns ; 1.000 ns ; 12.675 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[23] ; MAIN_CLK ; +; -11.673 ns ; 1.000 ns ; 12.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.659 ns ; 1.000 ns ; 12.659 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.649 ns ; 1.000 ns ; 12.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.648 ns ; 1.000 ns ; 12.648 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[25] ; MAIN_CLK ; +; -11.646 ns ; 1.000 ns ; 12.646 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[20] ; MAIN_CLK ; +; -11.640 ns ; 1.000 ns ; 12.640 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.633 ns ; 1.000 ns ; 12.633 ns ; interrupt_handler:nobody|WERTE[2][38] ; FB_AD[18] ; MAIN_CLK ; +; -11.631 ns ; 1.000 ns ; 12.631 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[19] ; MAIN_CLK ; +; -11.628 ns ; 1.000 ns ; 12.628 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.628 ns ; 1.000 ns ; 12.628 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[27] ; MAIN_CLK ; +; -11.627 ns ; 1.000 ns ; 12.627 ns ; interrupt_handler:nobody|WERTE[2][63] ; FB_AD[18] ; MAIN_CLK ; +; -11.620 ns ; 1.000 ns ; 12.620 ns ; interrupt_handler:nobody|WERTE[2][61] ; FB_AD[18] ; MAIN_CLK ; +; -11.620 ns ; 1.000 ns ; 12.620 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[18] ; MAIN_CLK ; +; -11.619 ns ; 1.000 ns ; 12.619 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0] ; YM_QB ; MAIN_CLK ; +; -11.618 ns ; 1.000 ns ; 12.618 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[18] ; MAIN_CLK ; +; -11.616 ns ; 1.000 ns ; 12.616 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[20] ; MAIN_CLK ; +; -11.616 ns ; 1.000 ns ; 12.616 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; FB_AD[25] ; MAIN_CLK ; +; -11.608 ns ; 1.000 ns ; 12.608 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[19] ; MAIN_CLK ; +; -11.607 ns ; 1.000 ns ; 12.607 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[21] ; MAIN_CLK ; +; -11.595 ns ; 1.000 ns ; 12.595 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[27] ; MAIN_CLK ; +; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[20] ; MAIN_CLK ; +; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[18] ; MAIN_CLK ; +; -11.589 ns ; 1.000 ns ; 12.589 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; YM_QA ; MAIN_CLK ; +; -11.588 ns ; 1.000 ns ; 12.588 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.588 ns ; 1.000 ns ; 12.588 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FB_AD[18] ; MAIN_CLK ; +; -11.583 ns ; 1.000 ns ; 12.583 ns ; interrupt_handler:nobody|WERTE[2][57] ; FB_AD[18] ; MAIN_CLK ; +; -11.582 ns ; 1.000 ns ; 12.582 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[22] ; MAIN_CLK ; +; -11.579 ns ; 1.000 ns ; 12.579 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QA ; MAIN_CLK ; +; -11.578 ns ; 1.000 ns ; 12.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.576 ns ; 1.000 ns ; 12.576 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.576 ns ; 1.000 ns ; 12.576 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[22] ; MAIN_CLK ; +; -11.567 ns ; 1.000 ns ; 12.567 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[22] ; MAIN_CLK ; +; -11.559 ns ; 1.000 ns ; 12.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[23] ; MAIN_CLK ; +; -11.552 ns ; 1.000 ns ; 12.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QC ; MAIN_CLK ; +; -11.550 ns ; 1.000 ns ; 12.550 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[27] ; MAIN_CLK ; +; -11.545 ns ; 1.000 ns ; 12.545 ns ; interrupt_handler:nobody|WERTE[2][31] ; FB_AD[18] ; MAIN_CLK ; +; -11.544 ns ; 1.000 ns ; 12.544 ns ; interrupt_handler:nobody|WERTE[2][6] ; FB_AD[18] ; MAIN_CLK ; +; -11.543 ns ; 1.000 ns ; 12.543 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.542 ns ; 1.000 ns ; 12.542 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.541 ns ; 1.000 ns ; 12.541 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[23] ; MAIN_CLK ; +; -11.540 ns ; 1.000 ns ; 12.540 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.540 ns ; 1.000 ns ; 12.540 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.537 ns ; 1.000 ns ; 12.537 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; FB_AD[3] ; MAIN_CLK ; +; -11.531 ns ; 1.000 ns ; 12.531 ns ; interrupt_handler:nobody|WERTE[2][45] ; FB_AD[18] ; MAIN_CLK ; +; -11.527 ns ; 1.000 ns ; 12.527 ns ; interrupt_handler:nobody|WERTE[2][7] ; FB_AD[18] ; MAIN_CLK ; +; -11.527 ns ; 1.000 ns ; 12.527 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; FB_AD[25] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[23] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[23] ; MAIN_CLK ; +; -11.508 ns ; 1.000 ns ; 12.508 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; FB_AD[27] ; MAIN_CLK ; +; -11.507 ns ; 1.000 ns ; 12.507 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[18] ; MAIN_CLK ; +; -11.505 ns ; 1.000 ns ; 12.505 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[23] ; MAIN_CLK ; +; -11.504 ns ; 1.000 ns ; 12.504 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.502 ns ; 1.000 ns ; 12.502 ns ; interrupt_handler:nobody|WERTE[2][60] ; FB_AD[18] ; MAIN_CLK ; +; -11.502 ns ; 1.000 ns ; 12.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; FB_AD[26] ; MAIN_CLK ; +; -11.495 ns ; 1.000 ns ; 12.495 ns ; interrupt_handler:nobody|WERTE[2][53] ; FB_AD[18] ; MAIN_CLK ; +; -11.492 ns ; 1.000 ns ; 12.492 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FB_AD[18] ; MAIN_CLK ; +; -11.488 ns ; 1.000 ns ; 12.488 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; FB_AD[3] ; MAIN_CLK ; +; -11.487 ns ; 1.000 ns ; 12.487 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[7] ; MAIN_CLK ; +; -11.480 ns ; 1.000 ns ; 12.480 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[23] ; MAIN_CLK ; +; -11.480 ns ; 1.000 ns ; 12.480 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.479 ns ; 1.000 ns ; 12.479 ns ; interrupt_handler:nobody|WERTE[2][36] ; FB_AD[18] ; MAIN_CLK ; +; -11.478 ns ; 1.000 ns ; 12.478 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[2] ; YM_QB ; MAIN_CLK ; +; -11.470 ns ; 1.000 ns ; 12.470 ns ; interrupt_handler:nobody|WERTE[2][15] ; FB_AD[18] ; MAIN_CLK ; +; -11.461 ns ; 1.000 ns ; 12.461 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[27] ; MAIN_CLK ; +; -11.460 ns ; 1.000 ns ; 12.460 ns ; interrupt_handler:nobody|WERTE[2][8] ; FB_AD[18] ; MAIN_CLK ; +; -11.459 ns ; 1.000 ns ; 12.459 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[27] ; MAIN_CLK ; +; -11.455 ns ; 1.000 ns ; 12.455 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; YM_QA ; MAIN_CLK ; +; -11.455 ns ; 1.000 ns ; 12.455 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[22] ; MAIN_CLK ; +; -11.451 ns ; 1.000 ns ; 12.451 ns ; interrupt_handler:nobody|WERTE[2][50] ; FB_AD[18] ; MAIN_CLK ; +; -11.447 ns ; 1.000 ns ; 12.447 ns ; interrupt_handler:nobody|WERTE[2][52] ; FB_AD[18] ; MAIN_CLK ; +; -11.444 ns ; 1.000 ns ; 12.444 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FB_AD[27] ; MAIN_CLK ; +; -11.443 ns ; 1.000 ns ; 12.443 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[20] ; MAIN_CLK ; +; -11.441 ns ; 1.000 ns ; 12.441 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; FB_AD[18] ; MAIN_CLK ; +; -11.435 ns ; 1.000 ns ; 12.435 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[18] ; MAIN_CLK ; +; -11.433 ns ; 1.000 ns ; 12.433 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[4] ; YM_QB ; MAIN_CLK ; +; -11.432 ns ; 1.000 ns ; 12.432 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.431 ns ; 1.000 ns ; 12.431 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[20] ; MAIN_CLK ; +; -11.429 ns ; 1.000 ns ; 12.429 ns ; interrupt_handler:nobody|WERTE[2][55] ; FB_AD[18] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; tpd ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ +; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; +; -11.849 ns ; 1.000 ns ; 12.849 ns ; FB_SIZE0 ; FB_AD[27] ; +; -11.785 ns ; 1.000 ns ; 12.785 ns ; nFB_CS1 ; FB_AD[27] ; +; -11.694 ns ; 1.000 ns ; 12.694 ns ; nFB_CS1 ; FB_AD[7] ; +; -11.672 ns ; 1.000 ns ; 12.672 ns ; FB_SIZE1 ; FB_AD[27] ; +; -11.625 ns ; 1.000 ns ; 12.625 ns ; nFB_WR ; FB_AD[7] ; +; -11.514 ns ; 1.000 ns ; 12.514 ns ; FB_SIZE0 ; FB_AD[18] ; +; -11.464 ns ; 1.000 ns ; 12.464 ns ; IDE_INT ; FB_AD[7] ; +; -11.450 ns ; 1.000 ns ; 12.450 ns ; SRD[11] ; FB_AD[27] ; +; -11.438 ns ; 1.000 ns ; 12.438 ns ; nFB_OE ; FB_AD[27] ; +; -11.420 ns ; 1.000 ns ; 12.420 ns ; nFB_CS2 ; FB_AD[27] ; +; -11.399 ns ; 1.000 ns ; 12.399 ns ; nFB_WR ; FB_AD[27] ; +; -11.376 ns ; 1.000 ns ; 12.376 ns ; nFB_WR ; FB_AD[18] ; +; -11.337 ns ; 1.000 ns ; 12.337 ns ; FB_SIZE1 ; FB_AD[18] ; +; -11.243 ns ; 1.000 ns ; 12.243 ns ; nFB_CS2 ; FB_AD[18] ; +; -10.918 ns ; 1.000 ns ; 11.918 ns ; nFB_CS1 ; FB_AD[20] ; +; -10.824 ns ; 1.000 ns ; 11.824 ns ; nFB_CS2 ; FB_AD[7] ; +; -10.814 ns ; 1.000 ns ; 11.814 ns ; FB_SIZE0 ; FB_AD[7] ; +; -10.798 ns ; 1.000 ns ; 11.798 ns ; nFB_OE ; FB_AD[7] ; +; -10.779 ns ; 1.000 ns ; 11.779 ns ; CTS ; FB_AD[18] ; +; -10.758 ns ; 1.000 ns ; 11.758 ns ; FB_SIZE1 ; FB_AD[7] ; +; -10.658 ns ; 1.000 ns ; 11.658 ns ; MAIN_CLK ; FB_AD[27] ; +; -10.631 ns ; 1.000 ns ; 11.631 ns ; nFB_OE ; FB_AD[18] ; +; -10.578 ns ; 1.000 ns ; 11.578 ns ; MAIN_CLK ; FB_AD[7] ; +; -10.573 ns ; 1.000 ns ; 11.573 ns ; nFB_CS2 ; FB_AD[20] ; +; -10.561 ns ; 1.000 ns ; 11.561 ns ; nFB_CS1 ; FB_AD[6] ; +; -10.549 ns ; 1.000 ns ; 11.549 ns ; FB_SIZE0 ; FB_AD[20] ; +; -10.543 ns ; 1.000 ns ; 11.543 ns ; nFB_CS1 ; FB_AD[9] ; +; -10.529 ns ; 1.000 ns ; 11.529 ns ; FB_SIZE0 ; FB_AD[23] ; +; -10.521 ns ; 1.000 ns ; 11.521 ns ; nFB_CS1 ; FB_AD[23] ; +; -10.471 ns ; 1.000 ns ; 11.471 ns ; FB_SIZE1 ; FB_AD[20] ; +; -10.451 ns ; 1.000 ns ; 11.451 ns ; FB_SIZE1 ; FB_AD[23] ; +; -10.425 ns ; 1.000 ns ; 11.425 ns ; nFB_WR ; FB_AD[9] ; +; -10.420 ns ; 1.000 ns ; 11.420 ns ; nFB_CS1 ; FB_AD[17] ; +; -10.415 ns ; 1.000 ns ; 11.415 ns ; nFB_CS1 ; FB_AD[25] ; +; -10.412 ns ; 1.000 ns ; 11.412 ns ; nFB_CS1 ; FB_AD[21] ; +; -10.370 ns ; 1.000 ns ; 11.370 ns ; nFB_OE ; FB_AD[20] ; +; -10.364 ns ; 1.000 ns ; 11.364 ns ; nFB_WR ; FB_AD[25] ; +; -10.362 ns ; 1.000 ns ; 11.362 ns ; nFB_CS1 ; FB_AD[26] ; +; -10.361 ns ; 1.000 ns ; 11.361 ns ; nFB_WR ; FB_AD[20] ; +; -10.335 ns ; 1.000 ns ; 11.335 ns ; nFB_CS2 ; FB_AD[23] ; +; -10.318 ns ; 1.000 ns ; 11.318 ns ; nFB_CS2 ; FB_AD[21] ; +; -10.317 ns ; 1.000 ns ; 11.317 ns ; nFB_WR ; FB_AD[22] ; +; -10.312 ns ; 1.000 ns ; 11.312 ns ; nFB_CS1 ; FB_AD[22] ; +; -10.311 ns ; 1.000 ns ; 11.311 ns ; nFB_WR ; FB_AD[26] ; +; -10.291 ns ; 1.000 ns ; 11.291 ns ; nFB_WR ; FB_AD[23] ; +; -10.278 ns ; 1.000 ns ; 11.278 ns ; FB_SIZE0 ; FB_AD[17] ; +; -10.277 ns ; 1.000 ns ; 11.277 ns ; MAIN_CLK ; FB_AD[18] ; +; -10.221 ns ; 1.000 ns ; 11.221 ns ; FB_SIZE0 ; FB_AD[29] ; +; -10.220 ns ; 1.000 ns ; 11.220 ns ; nFB_CS2 ; FB_AD[22] ; +; -10.178 ns ; 1.000 ns ; 11.178 ns ; FB_SIZE0 ; FB_AD[19] ; +; -10.146 ns ; 1.000 ns ; 11.146 ns ; FB_SIZE0 ; FB_AD[31] ; +; -10.136 ns ; 1.000 ns ; 11.136 ns ; nFB_CS1 ; FB_AD[24] ; +; -10.123 ns ; 1.000 ns ; 11.123 ns ; nFB_CS1 ; FB_AD[19] ; +; -10.101 ns ; 1.000 ns ; 11.101 ns ; FB_SIZE1 ; FB_AD[17] ; +; -10.085 ns ; 1.000 ns ; 11.085 ns ; nFB_WR ; FB_AD[24] ; +; -10.081 ns ; 1.000 ns ; 11.081 ns ; nFB_CS1 ; FB_AD[16] ; +; -10.077 ns ; 1.000 ns ; 11.077 ns ; nFB_CS2 ; FB_AD[19] ; +; -10.077 ns ; 1.000 ns ; 11.077 ns ; FB_SIZE0 ; FB_AD[21] ; +; -10.076 ns ; 1.000 ns ; 11.076 ns ; FB_SIZE1 ; FB_AD[19] ; +; -10.074 ns ; 1.000 ns ; 11.074 ns ; SRD[9] ; FB_AD[25] ; +; -10.070 ns ; 1.000 ns ; 11.070 ns ; nFB_CS1 ; FB_AD[29] ; +; -10.061 ns ; 1.000 ns ; 11.061 ns ; nFB_OE ; FB_AD[21] ; +; -10.060 ns ; 1.000 ns ; 11.060 ns ; nFB_WR ; FB_AD[21] ; +; -10.051 ns ; 1.000 ns ; 11.051 ns ; nFB_WR ; FB_AD[19] ; +; -10.044 ns ; 1.000 ns ; 11.044 ns ; FB_SIZE1 ; FB_AD[29] ; +; -10.041 ns ; 1.000 ns ; 11.041 ns ; FB_SIZE0 ; FB_AD[30] ; +; -10.021 ns ; 1.000 ns ; 11.021 ns ; FB_SIZE1 ; FB_AD[21] ; +; -10.019 ns ; 1.000 ns ; 11.019 ns ; nFB_WR ; FB_AD[29] ; +; -10.004 ns ; 1.000 ns ; 11.004 ns ; nFB_WR ; FB_AD[6] ; +; -9.969 ns ; 1.000 ns ; 10.969 ns ; FB_SIZE1 ; FB_AD[31] ; +; -9.951 ns ; 1.000 ns ; 10.951 ns ; FB_SIZE0 ; FB_AD[22] ; +; -9.938 ns ; 1.000 ns ; 10.938 ns ; nFB_CS2 ; FB_AD[26] ; +; -9.918 ns ; 1.000 ns ; 10.918 ns ; nFB_CS1 ; FB_AD[31] ; +; -9.914 ns ; 1.000 ns ; 10.914 ns ; nFB_CS2 ; FB_AD[17] ; +; -9.903 ns ; 1.000 ns ; 10.903 ns ; FB_SIZE0 ; FB_AD[25] ; +; -9.899 ns ; 1.000 ns ; 10.899 ns ; IDE_INT ; FB_AD[21] ; +; -9.876 ns ; 1.000 ns ; 10.876 ns ; nFB_CS2 ; FB_AD[31] ; +; -9.864 ns ; 1.000 ns ; 10.864 ns ; FB_SIZE1 ; FB_AD[30] ; +; -9.835 ns ; 1.000 ns ; 10.835 ns ; LP_D[3] ; FB_AD[27] ; +; -9.823 ns ; 1.000 ns ; 10.823 ns ; nFB_WR ; FB_AD[17] ; +; -9.820 ns ; 1.000 ns ; 10.820 ns ; nFB_CS2 ; FB_AD[30] ; +; -9.813 ns ; 1.000 ns ; 10.813 ns ; MAIN_CLK ; FB_AD[20] ; +; -9.802 ns ; 1.000 ns ; 10.802 ns ; nFB_CS2 ; FB_AD[25] ; +; -9.801 ns ; 1.000 ns ; 10.801 ns ; FB_SIZE1 ; FB_AD[25] ; +; -9.792 ns ; 1.000 ns ; 10.792 ns ; nFB_CS2 ; FB_AD[29] ; +; -9.791 ns ; 1.000 ns ; 10.791 ns ; nFB_OE ; FB_AD[25] ; +; -9.778 ns ; 1.000 ns ; 10.778 ns ; FB_SIZE1 ; FB_AD[22] ; +; -9.770 ns ; 1.000 ns ; 10.770 ns ; nFB_OE ; FB_AD[23] ; +; -9.763 ns ; 1.000 ns ; 10.763 ns ; nFB_CS1 ; FB_AD[2] ; +; -9.750 ns ; 1.000 ns ; 10.750 ns ; nFB_WR ; FB_AD[31] ; +; -9.729 ns ; 1.000 ns ; 10.729 ns ; FB_SIZE0 ; FB_AD[9] ; +; -9.729 ns ; 1.000 ns ; 10.729 ns ; nFB_CS1 ; FB_AD[30] ; +; -9.701 ns ; 1.000 ns ; 10.701 ns ; MAIN_CLK ; FB_AD[21] ; +; -9.699 ns ; 1.000 ns ; 10.699 ns ; FB_SIZE0 ; FB_AD[24] ; +; -9.692 ns ; 1.000 ns ; 10.692 ns ; nFB_OE ; FB_AD[22] ; +; -9.685 ns ; 1.000 ns ; 10.685 ns ; nFB_OE ; FB_AD[31] ; +; -9.684 ns ; 1.000 ns ; 10.684 ns ; nFB_OE ; FB_AD[19] ; +; -9.671 ns ; 1.000 ns ; 10.671 ns ; nFB_OE ; FB_AD[17] ; +; -9.634 ns ; 1.000 ns ; 10.634 ns ; nFB_CS2 ; FB_AD[24] ; +; -9.630 ns ; 1.000 ns ; 10.630 ns ; SRD[2] ; FB_AD[18] ; +; -9.629 ns ; 1.000 ns ; 10.629 ns ; nFB_WR ; FB_AD[30] ; +; -9.628 ns ; 1.000 ns ; 10.628 ns ; nFB_CS2 ; FB_AD[9] ; +; -9.627 ns ; 1.000 ns ; 10.627 ns ; FB_SIZE1 ; FB_AD[9] ; +; -9.600 ns ; 1.000 ns ; 10.600 ns ; nFB_CS1 ; FB_AD[28] ; +; -9.597 ns ; 1.000 ns ; 10.597 ns ; FB_SIZE1 ; FB_AD[24] ; +; -9.593 ns ; 1.000 ns ; 10.593 ns ; nFB_WR ; FB_AD[16] ; +; -9.574 ns ; 1.000 ns ; 10.574 ns ; FB_SIZE0 ; FB_AD[28] ; +; -9.572 ns ; 1.000 ns ; 10.572 ns ; DCD ; FB_AD[17] ; +; -9.565 ns ; 1.000 ns ; 10.565 ns ; nFB_OE ; FB_AD[24] ; +; -9.559 ns ; 1.000 ns ; 10.559 ns ; nFB_WR ; FB_AD[8] ; +; -9.554 ns ; 1.000 ns ; 10.554 ns ; nFB_CS1 ; FB_AD[8] ; +; -9.521 ns ; 1.000 ns ; 10.521 ns ; nFB_CS1 ; FB_AD[3] ; +; -9.491 ns ; 1.000 ns ; 10.491 ns ; nFB_WR ; FB_AD[28] ; +; -9.477 ns ; 1.000 ns ; 10.477 ns ; nFB_CS2 ; FB_AD[3] ; +; -9.455 ns ; 1.000 ns ; 10.455 ns ; FB_SIZE0 ; FB_AD[26] ; +; -9.418 ns ; 1.000 ns ; 10.418 ns ; RI ; FB_AD[22] ; +; -9.410 ns ; 1.000 ns ; 10.410 ns ; nFB_CS1 ; FB_AD[5] ; +; -9.398 ns ; 1.000 ns ; 10.398 ns ; MAIN_CLK ; FB_AD[26] ; +; -9.397 ns ; 1.000 ns ; 10.397 ns ; FB_SIZE1 ; FB_AD[28] ; +; -9.394 ns ; 1.000 ns ; 10.394 ns ; SRD[8] ; FB_AD[24] ; +; -9.381 ns ; 1.000 ns ; 10.381 ns ; nFB_OE ; FB_AD[26] ; +; -9.380 ns ; 1.000 ns ; 10.380 ns ; nFB_CS2 ; FB_AD[11] ; +; -9.371 ns ; 1.000 ns ; 10.371 ns ; FB_SIZE0 ; FB_AD[4] ; +; -9.370 ns ; 1.000 ns ; 10.370 ns ; nFB_WR ; FB_AD[5] ; +; -9.355 ns ; 1.000 ns ; 10.355 ns ; nFB_OE ; FB_AD[4] ; +; -9.344 ns ; 1.000 ns ; 10.344 ns ; nFB_CS2 ; FB_AD[5] ; +; -9.333 ns ; 1.000 ns ; 10.333 ns ; FB_SIZE0 ; FB_AD[16] ; +; -9.328 ns ; 1.000 ns ; 10.328 ns ; FB_SIZE0 ; FB_AD[2] ; +; -9.315 ns ; 1.000 ns ; 10.315 ns ; FB_SIZE1 ; FB_AD[4] ; +; -9.312 ns ; 1.000 ns ; 10.312 ns ; FB_SIZE0 ; FB_AD[3] ; +; -9.312 ns ; 1.000 ns ; 10.312 ns ; nFB_OE ; FB_AD[2] ; +; -9.309 ns ; 1.000 ns ; 10.309 ns ; MAIN_CLK ; FB_AD[22] ; +; -9.305 ns ; 1.000 ns ; 10.305 ns ; MAIN_CLK ; FB_AD[25] ; +; -9.296 ns ; 1.000 ns ; 10.296 ns ; nFB_OE ; FB_AD[3] ; +; -9.278 ns ; 1.000 ns ; 10.278 ns ; FB_SIZE1 ; FB_AD[26] ; +; -9.275 ns ; 1.000 ns ; 10.275 ns ; nFB_WR ; FB_AD[2] ; +; -9.273 ns ; 1.000 ns ; 10.273 ns ; nFB_CS1 ; nFB_TA ; +; -9.272 ns ; 1.000 ns ; 10.272 ns ; FB_SIZE1 ; FB_AD[2] ; +; -9.271 ns ; 1.000 ns ; 10.271 ns ; nFB_CS2 ; FB_AD[16] ; +; -9.262 ns ; 1.000 ns ; 10.262 ns ; nFB_OE ; FB_AD[28] ; +; -9.256 ns ; 1.000 ns ; 10.256 ns ; FB_SIZE1 ; FB_AD[3] ; +; -9.245 ns ; 1.000 ns ; 10.245 ns ; nFB_CS2 ; FB_AD[2] ; +; -9.231 ns ; 1.000 ns ; 10.231 ns ; CLK33M ; VB[7] ; +; -9.210 ns ; 1.000 ns ; 10.210 ns ; nFB_CS2 ; FB_AD[4] ; +; -9.203 ns ; 1.000 ns ; 10.203 ns ; nFB_OE ; FB_AD[9] ; +; -9.201 ns ; 1.000 ns ; 10.201 ns ; nFB_CS2 ; FB_AD[8] ; +; -9.199 ns ; 1.000 ns ; 10.199 ns ; MAIN_CLK ; FB_AD[31] ; +; -9.198 ns ; 1.000 ns ; 10.198 ns ; CLK33M ; VSYNC_PAD ; +; -9.193 ns ; 1.000 ns ; 10.193 ns ; CLK33M ; VR[6] ; +; -9.191 ns ; 1.000 ns ; 10.191 ns ; CLK33M ; VG[3] ; +; -9.176 ns ; 1.000 ns ; 10.176 ns ; nFB_CS1 ; FB_AD[4] ; +; -9.168 ns ; 1.000 ns ; 10.168 ns ; LP_D[7] ; FB_AD[31] ; +; -9.156 ns ; 1.000 ns ; 10.156 ns ; FB_SIZE1 ; FB_AD[16] ; +; -9.145 ns ; 1.000 ns ; 10.145 ns ; MAIN_CLK ; FB_AD[23] ; +; -9.145 ns ; 1.000 ns ; 10.145 ns ; nFB_CS2 ; FB_AD[28] ; +; -9.112 ns ; 1.000 ns ; 10.112 ns ; nFB_WR ; FB_AD[3] ; +; -9.099 ns ; 1.000 ns ; 10.099 ns ; MAIN_CLK ; FB_AD[19] ; +; -9.089 ns ; 1.000 ns ; 10.089 ns ; nFB_OE ; FB_AD[5] ; +; -9.088 ns ; 1.000 ns ; 10.088 ns ; SRD[5] ; FB_AD[21] ; +; -9.081 ns ; 1.000 ns ; 10.081 ns ; nFB_OE ; FB_AD[16] ; +; -9.079 ns ; 1.000 ns ; 10.079 ns ; MAIN_CLK ; FB_AD[24] ; +; -9.047 ns ; 1.000 ns ; 10.047 ns ; nFB_CS2 ; FB_AD[10] ; +; -9.019 ns ; 1.000 ns ; 10.019 ns ; nFB_CS2 ; FB_AD[13] ; +; -9.004 ns ; 1.000 ns ; 10.004 ns ; FB_SIZE0 ; FB_AD[8] ; +; -8.984 ns ; 1.000 ns ; 9.984 ns ; LP_D[5] ; FB_AD[29] ; +; -8.935 ns ; 1.000 ns ; 9.935 ns ; SRD[4] ; FB_AD[20] ; +; -8.933 ns ; 1.000 ns ; 9.933 ns ; nFB_OE ; FB_AD[30] ; +; -8.927 ns ; 1.000 ns ; 9.927 ns ; SRD[10] ; FB_AD[26] ; +; -8.926 ns ; 1.000 ns ; 9.926 ns ; nFB_OE ; FB_AD[8] ; +; -8.924 ns ; 1.000 ns ; 9.924 ns ; nFB_CS2 ; FB_AD[6] ; +; -8.921 ns ; 1.000 ns ; 9.921 ns ; nFB_WR ; FB_AD[4] ; +; -8.916 ns ; 1.000 ns ; 9.916 ns ; LP_D[6] ; FB_AD[30] ; +; -8.909 ns ; 1.000 ns ; 9.909 ns ; nFB_CS2 ; FB_AD[15] ; +; -8.902 ns ; 1.000 ns ; 9.902 ns ; FB_SIZE1 ; FB_AD[8] ; +; -8.896 ns ; 1.000 ns ; 9.896 ns ; FB_SIZE0 ; FB_AD[5] ; +; -8.876 ns ; 1.000 ns ; 9.876 ns ; nFB_CS2 ; FB_AD[14] ; +; -8.873 ns ; 1.000 ns ; 9.873 ns ; LP_BUSY ; FB_AD[16] ; +; -8.869 ns ; 1.000 ns ; 9.869 ns ; MAIN_CLK ; FB_AD[4] ; +; -8.864 ns ; 1.000 ns ; 9.864 ns ; nFB_OE ; FB_AD[29] ; +; -8.852 ns ; 1.000 ns ; 9.852 ns ; nFB_CS2 ; FB_AD[12] ; +; -8.840 ns ; 1.000 ns ; 9.840 ns ; FB_SIZE1 ; FB_AD[5] ; +; -8.826 ns ; 1.000 ns ; 9.826 ns ; MAIN_CLK ; FB_AD[2] ; +; -8.819 ns ; 1.000 ns ; 9.819 ns ; DCD ; FB_AD[3] ; +; -8.810 ns ; 1.000 ns ; 9.810 ns ; MAIN_CLK ; FB_AD[3] ; +; -8.804 ns ; 1.000 ns ; 9.804 ns ; nFB_OE ; FB_AD[13] ; +; -8.803 ns ; 1.000 ns ; 9.803 ns ; SRD[7] ; FB_AD[23] ; +; -8.780 ns ; 1.000 ns ; 9.780 ns ; nFB_CS2 ; FB_AD[1] ; +; -8.776 ns ; 1.000 ns ; 9.776 ns ; MAIN_CLK ; FB_AD[28] ; +; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[12] ; +; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[11] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; FB_SIZE0 ; BA[0] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[12] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[11] ; +; -8.672 ns ; 1.000 ns ; 9.672 ns ; FB_SIZE0 ; FB_AD[6] ; +; -8.660 ns ; 1.000 ns ; 9.660 ns ; RI ; FB_AD[8] ; +; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[12] ; +; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[11] ; +; -8.656 ns ; 1.000 ns ; 9.656 ns ; nFB_OE ; FB_AD[6] ; +; -8.651 ns ; 1.000 ns ; 9.651 ns ; FB_SIZE0 ; FB_AD[0] ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; th ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; MAIN_CLK ; +; -0.386 ns ; 1.000 ns ; 1.386 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; MAIN_CLK ; +; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; MAIN_CLK ; +; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; MAIN_CLK ; +; -0.370 ns ; 1.000 ns ; 1.370 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[2] ; MAIN_CLK ; +; -0.339 ns ; 1.000 ns ; 1.339 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; MAIN_CLK ; +; -0.333 ns ; 1.000 ns ; 1.333 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; MAIN_CLK ; +; -0.328 ns ; 1.000 ns ; 1.328 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; MAIN_CLK ; +; -0.325 ns ; 1.000 ns ; 1.325 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; MAIN_CLK ; +; -0.325 ns ; 1.000 ns ; 1.325 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[14] ; MAIN_CLK ; +; -0.321 ns ; 1.000 ns ; 1.321 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; MAIN_CLK ; +; -0.320 ns ; 1.000 ns ; 1.320 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; MAIN_CLK ; +; -0.310 ns ; 1.000 ns ; 1.310 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; MAIN_CLK ; +; -0.302 ns ; 1.000 ns ; 1.302 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; MAIN_CLK ; +; -0.302 ns ; 1.000 ns ; 1.302 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[2] ; MAIN_CLK ; +; -0.293 ns ; 1.000 ns ; 1.293 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; MAIN_CLK ; +; -0.285 ns ; 1.000 ns ; 1.285 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; MAIN_CLK ; +; -0.283 ns ; 1.000 ns ; 1.283 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9] ; MAIN_CLK ; +; -0.275 ns ; 1.000 ns ; 1.275 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17] ; MAIN_CLK ; +; -0.272 ns ; 1.000 ns ; 1.272 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; MAIN_CLK ; +; -0.269 ns ; 1.000 ns ; 1.269 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; MAIN_CLK ; +; -0.265 ns ; 1.000 ns ; 1.265 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; MAIN_CLK ; +; -0.252 ns ; 1.000 ns ; 1.252 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; MAIN_CLK ; +; -0.247 ns ; 1.000 ns ; 1.247 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8] ; MAIN_CLK ; +; -0.246 ns ; 1.000 ns ; 1.246 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26] ; MAIN_CLK ; +; -0.245 ns ; 1.000 ns ; 1.245 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; MAIN_CLK ; +; -0.238 ns ; 1.000 ns ; 1.238 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; MAIN_CLK ; +; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; MAIN_CLK ; +; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; MAIN_CLK ; +; -0.227 ns ; 1.000 ns ; 1.227 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; MAIN_CLK ; +; -0.226 ns ; 1.000 ns ; 1.226 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10] ; MAIN_CLK ; +; -0.224 ns ; 1.000 ns ; 1.224 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; MAIN_CLK ; +; -0.223 ns ; 1.000 ns ; 1.223 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; MAIN_CLK ; +; -0.222 ns ; 1.000 ns ; 1.222 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; MAIN_CLK ; +; -0.216 ns ; 1.000 ns ; 1.216 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; MAIN_CLK ; +; -0.208 ns ; 1.000 ns ; 1.208 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; MAIN_CLK ; +; -0.202 ns ; 1.000 ns ; 1.202 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; MAIN_CLK ; +; -0.197 ns ; 1.000 ns ; 1.197 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9] ; MAIN_CLK ; +; -0.194 ns ; 1.000 ns ; 1.194 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; MAIN_CLK ; +; -0.191 ns ; 1.000 ns ; 1.191 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5] ; MAIN_CLK ; +; -0.189 ns ; 1.000 ns ; 1.189 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; MAIN_CLK ; +; -0.187 ns ; 1.000 ns ; 1.187 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; MAIN_CLK ; +; -0.181 ns ; 1.000 ns ; 1.181 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; MAIN_CLK ; +; -0.179 ns ; 1.000 ns ; 1.179 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; MAIN_CLK ; +; -0.173 ns ; 1.000 ns ; 1.173 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; MAIN_CLK ; +; -0.172 ns ; 1.000 ns ; 1.172 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; MAIN_CLK ; +; -0.166 ns ; 1.000 ns ; 1.166 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10] ; MAIN_CLK ; +; -0.165 ns ; 1.000 ns ; 1.165 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; MAIN_CLK ; +; -0.162 ns ; 1.000 ns ; 1.162 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; MAIN_CLK ; +; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; MAIN_CLK ; +; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; MAIN_CLK ; +; -0.154 ns ; 1.000 ns ; 1.154 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; MAIN_CLK ; +; -0.151 ns ; 1.000 ns ; 1.151 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; MAIN_CLK ; +; -0.149 ns ; 1.000 ns ; 1.149 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; MAIN_CLK ; +; -0.146 ns ; 1.000 ns ; 1.146 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; MAIN_CLK ; +; -0.145 ns ; 1.000 ns ; 1.145 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; MAIN_CLK ; +; -0.142 ns ; 1.000 ns ; 1.142 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; MAIN_CLK ; +; -0.141 ns ; 1.000 ns ; 1.141 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; MAIN_CLK ; +; -0.140 ns ; 1.000 ns ; 1.140 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; MAIN_CLK ; +; -0.137 ns ; 1.000 ns ; 1.137 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; MAIN_CLK ; +; -0.134 ns ; 1.000 ns ; 1.134 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7] ; MAIN_CLK ; +; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22] ; MAIN_CLK ; +; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; MAIN_CLK ; +; -0.125 ns ; 1.000 ns ; 1.125 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; MAIN_CLK ; +; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; MAIN_CLK ; +; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; MAIN_CLK ; +; -0.113 ns ; 1.000 ns ; 1.113 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; MAIN_CLK ; +; -0.109 ns ; 1.000 ns ; 1.109 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; MAIN_CLK ; +; -0.108 ns ; 1.000 ns ; 1.108 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; MAIN_CLK ; +; -0.099 ns ; 1.000 ns ; 1.099 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; MAIN_CLK ; +; -0.094 ns ; 1.000 ns ; 1.094 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19] ; MAIN_CLK ; +; -0.092 ns ; 1.000 ns ; 1.092 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; MAIN_CLK ; +; -0.090 ns ; 1.000 ns ; 1.090 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; MAIN_CLK ; +; -0.089 ns ; 1.000 ns ; 1.089 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23] ; MAIN_CLK ; +; -0.087 ns ; 1.000 ns ; 1.087 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; MAIN_CLK ; +; -0.086 ns ; 1.000 ns ; 1.086 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; MAIN_CLK ; +; -0.085 ns ; 1.000 ns ; 1.085 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; MAIN_CLK ; +; -0.081 ns ; 1.000 ns ; 1.081 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; -0.079 ns ; 1.000 ns ; 1.079 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; MAIN_CLK ; +; -0.078 ns ; 1.000 ns ; 1.078 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; MAIN_CLK ; +; -0.077 ns ; 1.000 ns ; 1.077 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; MAIN_CLK ; +; -0.075 ns ; 1.000 ns ; 1.075 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; MAIN_CLK ; +; -0.074 ns ; 1.000 ns ; 1.074 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; MAIN_CLK ; +; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1] ; MAIN_CLK ; +; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; MAIN_CLK ; +; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; MAIN_CLK ; +; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; -0.065 ns ; 1.000 ns ; 1.065 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14] ; MAIN_CLK ; +; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; MAIN_CLK ; +; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; MAIN_CLK ; +; -0.062 ns ; 1.000 ns ; 1.062 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; MAIN_CLK ; +; -0.059 ns ; 1.000 ns ; 1.059 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; MAIN_CLK ; +; -0.057 ns ; 1.000 ns ; 1.057 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; MAIN_CLK ; +; -0.053 ns ; 1.000 ns ; 1.053 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; MAIN_CLK ; +; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; MAIN_CLK ; +; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; MAIN_CLK ; +; -0.046 ns ; 1.000 ns ; 1.046 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; MAIN_CLK ; +; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; MAIN_CLK ; +; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; MAIN_CLK ; +; -0.039 ns ; 1.000 ns ; 1.039 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21] ; MAIN_CLK ; +; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; MAIN_CLK ; +; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; MAIN_CLK ; +; -0.035 ns ; 1.000 ns ; 1.035 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; MAIN_CLK ; +; -0.033 ns ; 1.000 ns ; 1.033 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20] ; MAIN_CLK ; +; -0.028 ns ; 1.000 ns ; 1.028 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; MAIN_CLK ; +; -0.026 ns ; 1.000 ns ; 1.026 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; MAIN_CLK ; +; -0.022 ns ; 1.000 ns ; 1.022 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; MAIN_CLK ; +; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; MAIN_CLK ; +; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; MAIN_CLK ; +; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; MAIN_CLK ; +; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; MAIN_CLK ; +; -0.011 ns ; 1.000 ns ; 1.011 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; MAIN_CLK ; +; -0.010 ns ; 1.000 ns ; 1.010 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; MAIN_CLK ; +; -0.004 ns ; 1.000 ns ; 1.004 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; MAIN_CLK ; +; 0.007 ns ; 1.000 ns ; 0.993 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; MAIN_CLK ; +; 0.008 ns ; 1.000 ns ; 0.992 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25] ; MAIN_CLK ; +; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; MAIN_CLK ; +; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; MAIN_CLK ; +; 0.010 ns ; 1.000 ns ; 0.990 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25] ; MAIN_CLK ; +; 0.015 ns ; 1.000 ns ; 0.985 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; MAIN_CLK ; +; 0.018 ns ; 1.000 ns ; 0.982 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; MAIN_CLK ; +; 0.021 ns ; 1.000 ns ; 0.979 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; MAIN_CLK ; +; 0.022 ns ; 1.000 ns ; 0.978 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; MAIN_CLK ; +; 0.027 ns ; 1.000 ns ; 0.973 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; MAIN_CLK ; +; 0.033 ns ; 1.000 ns ; 0.967 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; MAIN_CLK ; +; 0.036 ns ; 1.000 ns ; 0.964 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; MAIN_CLK ; +; 0.042 ns ; 1.000 ns ; 0.958 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; MAIN_CLK ; +; 0.044 ns ; 1.000 ns ; 0.956 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; MAIN_CLK ; +; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; MAIN_CLK ; +; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; MAIN_CLK ; +; 0.046 ns ; 1.000 ns ; 0.954 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; MAIN_CLK ; +; 0.047 ns ; 1.000 ns ; 0.953 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; MAIN_CLK ; +; 0.050 ns ; 1.000 ns ; 0.950 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; MAIN_CLK ; +; 0.050 ns ; 1.000 ns ; 0.950 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[14] ; MAIN_CLK ; +; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; MAIN_CLK ; +; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; MAIN_CLK ; +; 0.055 ns ; 1.000 ns ; 0.945 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; MAIN_CLK ; +; 0.055 ns ; 1.000 ns ; 0.945 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; MAIN_CLK ; +; 0.057 ns ; 1.000 ns ; 0.943 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; MAIN_CLK ; +; 0.064 ns ; 1.000 ns ; 0.936 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; MAIN_CLK ; +; 0.078 ns ; 1.000 ns ; 0.922 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; MAIN_CLK ; +; 0.081 ns ; 1.000 ns ; 0.919 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; MAIN_CLK ; +; 0.082 ns ; 1.000 ns ; 0.918 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; MAIN_CLK ; +; 0.091 ns ; 1.000 ns ; 0.909 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; MAIN_CLK ; +; 0.098 ns ; 1.000 ns ; 0.902 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; MAIN_CLK ; +; 0.106 ns ; 1.000 ns ; 0.894 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; MAIN_CLK ; +; 0.107 ns ; 1.000 ns ; 0.893 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; MAIN_CLK ; +; 0.109 ns ; 1.000 ns ; 0.891 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; MAIN_CLK ; +; 0.110 ns ; 1.000 ns ; 0.890 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; MAIN_CLK ; +; 0.114 ns ; 1.000 ns ; 0.886 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.119 ns ; 1.000 ns ; 0.881 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21] ; MAIN_CLK ; +; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; MAIN_CLK ; +; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; MAIN_CLK ; +; 0.128 ns ; 1.000 ns ; 0.872 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; MAIN_CLK ; +; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; MAIN_CLK ; +; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; MAIN_CLK ; +; 0.132 ns ; 1.000 ns ; 0.868 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.133 ns ; 1.000 ns ; 0.867 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; MAIN_CLK ; +; 0.136 ns ; 1.000 ns ; 0.864 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0] ; MAIN_CLK ; +; 0.148 ns ; 1.000 ns ; 0.852 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; MAIN_CLK ; +; 0.149 ns ; 1.000 ns ; 0.851 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; MAIN_CLK ; +; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; MAIN_CLK ; +; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; MAIN_CLK ; +; 0.158 ns ; 1.000 ns ; 0.842 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; MAIN_CLK ; +; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; MAIN_CLK ; +; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; MAIN_CLK ; +; 0.161 ns ; 1.000 ns ; 0.839 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; MAIN_CLK ; +; 0.163 ns ; 1.000 ns ; 0.837 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; MAIN_CLK ; +; 0.168 ns ; 1.000 ns ; 0.832 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; MAIN_CLK ; +; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6] ; MAIN_CLK ; +; 0.172 ns ; 1.000 ns ; 0.828 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; MAIN_CLK ; +; 0.178 ns ; 1.000 ns ; 0.822 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; MAIN_CLK ; +; 0.180 ns ; 1.000 ns ; 0.820 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; MAIN_CLK ; +; 0.181 ns ; 1.000 ns ; 0.819 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; MAIN_CLK ; +; 0.186 ns ; 1.000 ns ; 0.814 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; MAIN_CLK ; +; 0.188 ns ; 1.000 ns ; 0.812 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; MAIN_CLK ; +; 0.191 ns ; 1.000 ns ; 0.809 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26] ; MAIN_CLK ; +; 0.195 ns ; 1.000 ns ; 0.805 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.198 ns ; 1.000 ns ; 0.802 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; MAIN_CLK ; +; 0.201 ns ; 1.000 ns ; 0.799 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; MAIN_CLK ; +; 0.202 ns ; 1.000 ns ; 0.798 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; MAIN_CLK ; +; 0.209 ns ; 1.000 ns ; 0.791 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; MAIN_CLK ; +; 0.213 ns ; 1.000 ns ; 0.787 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; MAIN_CLK ; +; 0.216 ns ; 1.000 ns ; 0.784 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; MAIN_CLK ; +; 0.220 ns ; 1.000 ns ; 0.780 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; MAIN_CLK ; +; 0.221 ns ; 1.000 ns ; 0.779 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; MAIN_CLK ; +; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; MAIN_CLK ; +; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; MAIN_CLK ; +; 0.233 ns ; 1.000 ns ; 0.767 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_STR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; CLK25M ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; TxD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; RTS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DTR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IDE_RES ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_WR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_RD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nROM3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nROM4 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nRP_UDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nRP_LDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSDSEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nWR_GATE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nWR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QC ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DSA_D ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVWE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVCAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVRAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVCS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nPD_VGA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; TIN0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRCS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRBLE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRBHE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRWE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nDREQ1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LED_FPGA_OK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSROE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VCKE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nFB_TA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nDDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSYNC ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nMOT_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSTEP ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; CLKUSB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LPDIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; BA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; BA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; nFB_BURST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nACSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nACSI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_MSG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDCHG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CARD_DEDECT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_WP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDACK0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; WP_CF_CARD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_C_D ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_I_O ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; TOUT0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nMASTER ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; VD[31] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[30] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[29] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[28] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[27] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[26] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[25] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[24] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[23] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[22] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[21] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[20] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[19] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[18] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; IO[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_PAR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_SEL ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_RST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nRSTO_MCF ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_WR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_SIZE1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_SIZE0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_ALE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; MAIN_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDACK1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_OE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IDE_RDY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLK33M ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; HD_DD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nINDEX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; RxD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nWP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DCD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; TRACK00 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IDE_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; RI ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTC ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTB ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DVI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; E0_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PIC_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PIC_AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; MIDI_IN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nRD_DATA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DEV_OE~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DEV_CLRn~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; +; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; +; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; +; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; +; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; +; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; +; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; +; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; +; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Ignored Timing Assignments ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; From ; To ; Entity Name ; Help ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; dcfifo_8fi1 ; Node named delayed_wrptr_g removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK ; ; Node named DDRCLK removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[0] ; ; Node named DDRCLK[0] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[1] ; ; Node named DDRCLK[1] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[2] ; ; Node named DDRCLK[2] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[3] ; ; Node named DDRCLK[3] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK ; ; Node named Video:Fredi_Aschwanden|DDRCLK removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[0] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[0] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[1] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[1] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[2] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[2] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[3] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[3] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] was found in the netlist ; +; Maximum Delay ; 5 ns ; VD ; FB_AD ; ; No timing path applicable to specified source and destination ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[16] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[22] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[17] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[24] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[15] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[25] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[19] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[23] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[14] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[26] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[21] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[20] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[2] ; ; Assignment is illegal for node and/or path ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:25:14 2010 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only +Warning: Timing Analysis is analyzing one or more combinational loops as latches + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]" is a latch +Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled +Warning: Clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" frequency requirement of 47.96 MHz overrides "Cyclone III" PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 48.0 MHz +Warning: Clock Setting "fast" is unassigned +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" input frequency requirement of 0.5 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" input frequency requirement of 2.46 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" input frequency requirement of 24.57 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" input frequency requirement of 2.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" input frequency requirement of 15.99 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" input frequency requirement of 24.98 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" input frequency requirement of 47.96 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" input frequency requirement of 66.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 95.92 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[3]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[1]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[4]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[2]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[5]" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[3]~23" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[1]~25" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[4]~22" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[2]~24" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[0]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[6]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[9]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[8]" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[5]~21" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[0]~26" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[6]~20" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[9]~18" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[8]~19" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~31" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~30" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~2" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~29" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1" as buffer +Info: Found timing assignments -- calculating delays +Info: Slack time is 1.997 us for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]" + Info: Fmax is 362.45 MHz (period= 2.759 ns) + Info: + Largest register to register requirement is 1999.813 ns + Info: + Setup relationship between source and destination is 1999.998 ns + Info: + Latch edge is 1990.420 ns + Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is -9.578 ns + Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.001 ns + Info: + Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.532 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.084 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.998 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 2.574 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' + Info: 2: + IC(0.325 ns) + CELL(0.446 ns) = 0.771 ns; Loc. = LCCOMB_X65_Y16_N14; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita0~COUT' + Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.829 ns; Loc. = LCCOMB_X65_Y16_N16; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita1~COUT' + Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.887 ns; Loc. = LCCOMB_X65_Y16_N18; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita2~COUT' + Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.945 ns; Loc. = LCCOMB_X65_Y16_N20; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita3~COUT' + Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 1.003 ns; Loc. = LCCOMB_X65_Y16_N22; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita4~COUT' + Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 1.061 ns; Loc. = LCCOMB_X65_Y16_N24; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita5~COUT' + Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 1.119 ns; Loc. = LCCOMB_X65_Y16_N26; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita6~COUT' + Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 1.177 ns; Loc. = LCCOMB_X65_Y16_N28; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita7~COUT' + Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 1.235 ns; Loc. = LCCOMB_X65_Y16_N30; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita8~COUT' + Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 1.293 ns; Loc. = LCCOMB_X65_Y15_N0; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita9~COUT' + Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 1.351 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10~COUT' + Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 1.409 ns; Loc. = LCCOMB_X65_Y15_N4; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita11~COUT' + Info: 14: + IC(0.000 ns) + CELL(0.058 ns) = 1.467 ns; Loc. = LCCOMB_X65_Y15_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita12~COUT' + Info: 15: + IC(0.000 ns) + CELL(0.058 ns) = 1.525 ns; Loc. = LCCOMB_X65_Y15_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita13~COUT' + Info: 16: + IC(0.000 ns) + CELL(0.058 ns) = 1.583 ns; Loc. = LCCOMB_X65_Y15_N10; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita14~COUT' + Info: 17: + IC(0.000 ns) + CELL(0.058 ns) = 1.641 ns; Loc. = LCCOMB_X65_Y15_N12; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita15~COUT' + Info: 18: + IC(0.000 ns) + CELL(0.058 ns) = 1.699 ns; Loc. = LCCOMB_X65_Y15_N14; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita16~COUT' + Info: 19: + IC(0.000 ns) + CELL(0.455 ns) = 2.154 ns; Loc. = LCCOMB_X65_Y15_N16; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita17' + Info: 20: + IC(0.199 ns) + CELL(0.130 ns) = 2.483 ns; Loc. = LCCOMB_X65_Y15_N26; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]~feeder' + Info: 21: + IC(0.000 ns) + CELL(0.091 ns) = 2.574 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' + Info: Total cell delay = 2.050 ns ( 79.64 % ) + Info: Total interconnect delay = 0.524 ns ( 20.36 % ) +Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" +Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" +Info: Slack time is 498.663 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]" + Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits + Info: + Largest register to register requirement is 500.232 ns + Info: + Setup relationship between source and destination is 500.416 ns + Info: + Latch edge is 498.552 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.000 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 1.569 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: 2: + IC(0.344 ns) + CELL(0.376 ns) = 0.720 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 5; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13' + Info: 3: + IC(0.240 ns) + CELL(0.609 ns) = 1.569 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' + Info: Total cell delay = 0.985 ns ( 62.78 % ) + Info: Total interconnect delay = 0.584 ns ( 37.22 % ) +Info: Slack time is 28.59 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK" + Info: Fmax is 186.15 MHz (period= 5.372 ns) + Info: + Largest register to register requirement is 31.135 ns + Info: + Setup relationship between source and destination is 31.276 ns + Info: + Latch edge is 60.688 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 29.412 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with inverted offset of 29.412 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.020 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.508 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.065 ns) + CELL(0.534 ns) = 3.508 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' + Info: Total cell delay = 0.534 ns ( 15.22 % ) + Info: Total interconnect delay = 2.974 ns ( 84.78 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.488 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.131 ns) + CELL(0.448 ns) = 3.488 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' + Info: Total cell delay = 0.448 ns ( 12.84 % ) + Info: Total interconnect delay = 3.040 ns ( 87.16 % ) + Info: - Micro clock to output delay of source is 0.176 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 2.545 ns + Info: 1: + IC(0.000 ns) + CELL(0.418 ns) = 0.418 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' + Info: 2: + IC(1.655 ns) + CELL(0.381 ns) = 2.454 ns; Loc. = LCCOMB_X30_Y32_N2; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK~0' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 2.545 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' + Info: Total cell delay = 0.890 ns ( 34.97 % ) + Info: Total interconnect delay = 1.655 ns ( 65.03 % ) +Info: Slack time is -4.615 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -0.928 ns + Info: + Setup relationship between source and destination is 0.145 ns + Info: + Latch edge is 0.221 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.076 ns + Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.862 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 7.507 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 7.507 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 1.084 ns ( 14.44 % ) + Info: Total interconnect delay = 6.423 ns ( 85.56 % ) + Info: - Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source memory is 8.369 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.112 ns) + CELL(0.816 ns) = 8.369 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.525 ns ( 18.22 % ) + Info: Total interconnect delay = 6.844 ns ( 81.78 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' along 3741 path(s). See Report window for details. +Info: No valid register-to-register data paths exist for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" +Info: Slack time is -2.673 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC" + Info: + Largest pin to register requirement is 0.814 ns + Info: + Setup relationship between source and destination is 1.262 ns + Info: + Latch edge is 3.955 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 3.537 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.537 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.102 ns) + CELL(0.534 ns) = 3.537 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' + Info: Total cell delay = 0.534 ns ( 15.10 % ) + Info: Total interconnect delay = 3.003 ns ( 84.90 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 3.487 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.144 ns) + CELL(0.130 ns) = 2.215 ns; Loc. = LCCOMB_X22_Y6_N18; Fanout = 18; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5' + Info: 4: + IC(0.241 ns) + CELL(0.130 ns) = 2.586 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 19; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~0' + Info: 5: + IC(0.680 ns) + CELL(0.130 ns) = 3.396 ns; Loc. = LCCOMB_X25_Y6_N20; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC~1' + Info: 6: + IC(0.000 ns) + CELL(0.091 ns) = 3.487 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' + Info: Total cell delay = 1.422 ns ( 40.78 % ) + Info: Total interconnect delay = 2.065 ns ( 59.22 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' along 86 path(s). See Report window for details. +Info: Slack time is 2.965 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" + Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits + Info: + Largest register to register requirement is 3.604 ns + Info: + Setup relationship between source and destination is 3.788 ns + Info: + Latch edge is 6.481 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.000 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 0.639 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' + Info: 2: + IC(0.297 ns) + CELL(0.342 ns) = 0.639 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' + Info: Total cell delay = 0.342 ns ( 53.52 % ) + Info: Total interconnect delay = 0.297 ns ( 46.48 % ) +Info: Slack time is 5.299 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]" + Info: + Largest register to register requirement is 6.118 ns + Info: + Setup relationship between source and destination is 6.313 ns + Info: + Latch edge is 10.268 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 3.955 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.011 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.532 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.097 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.998 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' + Info: Total cell delay = 0.534 ns ( 15.07 % ) + Info: Total interconnect delay = 3.009 ns ( 84.93 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 0.819 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' + Info: 2: + IC(0.598 ns) + CELL(0.130 ns) = 0.728 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.819 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' + Info: Total cell delay = 0.221 ns ( 26.98 % ) + Info: Total interconnect delay = 0.598 ns ( 73.02 % ) +Info: Slack time is 1.672 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI" + Info: + Largest register to register requirement is 5.308 ns + Info: + Setup relationship between source and destination is 5.999 ns + Info: + Latch edge is 8.690 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.691 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.064 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.487 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' + Info: 3: + IC(1.098 ns) + CELL(0.488 ns) = 3.487 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' + Info: Total cell delay = 0.488 ns ( 13.99 % ) + Info: Total interconnect delay = 2.999 ns ( 86.01 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.551 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.116 ns) + CELL(0.534 ns) = 3.551 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 0.534 ns ( 15.04 % ) + Info: Total interconnect delay = 3.017 ns ( 84.96 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is 0.428 ns + Info: - Longest register to register delay is 3.636 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' + Info: 2: + IC(0.330 ns) + CELL(0.367 ns) = 0.697 ns; Loc. = LCCOMB_X22_Y2_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[34]~59' + Info: 3: + IC(2.591 ns) + CELL(0.348 ns) = 3.636 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' + Info: Total cell delay = 0.715 ns ( 19.66 % ) + Info: Total interconnect delay = 2.921 ns ( 80.34 % ) +Info: Slack time is -1.712 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ" + Info: + Largest pin to register requirement is 1.118 ns + Info: + Setup relationship between source and destination is 1.576 ns + Info: + Latch edge is 2.691 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 1.115 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 3.527 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.527 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.092 ns) + CELL(0.534 ns) = 3.527 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.993 ns ( 84.86 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 2.830 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.138 ns) + CELL(0.130 ns) = 2.209 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 7; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL' + Info: 4: + IC(0.400 ns) + CELL(0.130 ns) = 2.739 ns; Loc. = LCCOMB_X21_Y6_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~2' + Info: 5: + IC(0.000 ns) + CELL(0.091 ns) = 2.830 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' + Info: Total cell delay = 1.292 ns ( 45.65 % ) + Info: Total interconnect delay = 1.538 ns ( 54.35 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' along 29 path(s). See Report window for details. +Info: Slack time is -4.294 ns for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -0.607 ns + Info: + Setup relationship between source and destination is 0.272 ns + Info: + Latch edge is 0.493 ns + Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.221 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.668 ns + Info: + Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.082 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 8.082 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 1.243 ns ( 15.38 % ) + Info: Total interconnect delay = 6.839 ns ( 84.62 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.680 ns ( 19.20 % ) + Info: Total interconnect delay = 7.070 ns ( 80.80 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' along 3741 path(s). See Report window for details. +Info: Slack time is -5.966 ns for clock "CLK33M" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -2.279 ns + Info: + Setup relationship between source and destination is 0.196 ns + Info: + Latch edge is 0.278 ns + Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.082 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -2.264 ns + Info: + Shortest clock path from clock "CLK33M" to destination register is 6.486 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 6.486 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.006 ns ( 30.93 % ) + Info: Total interconnect delay = 4.480 ns ( 69.07 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.680 ns ( 19.20 % ) + Info: Total interconnect delay = 7.070 ns ( 80.80 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'CLK33M' along 3741 path(s). See Report window for details. +Info: Slack time is -4.261 ns for clock "MAIN_CLK" between source pin "FB_ALE" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7" + Info: + Largest pin to register requirement is 0.057 ns + Info: + Setup relationship between source and destination is 1.094 ns + Info: + Latch edge is 7.575 ns + Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 6.481 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 2.948 ns + Info: + Shortest clock path from clock "MAIN_CLK" to destination register is 2.948 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.433 ns) + CELL(0.534 ns) = 2.948 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' + Info: Total cell delay = 1.515 ns ( 51.39 % ) + Info: Total interconnect delay = 1.433 ns ( 48.61 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 4.318 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.524 ns) + CELL(0.130 ns) = 2.595 ns; Loc. = LCCOMB_X23_Y7_N20; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2' + Info: 4: + IC(0.212 ns) + CELL(0.130 ns) = 2.937 ns; Loc. = LCCOMB_X23_Y7_N18; Fanout = 52; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1' + Info: 5: + IC(0.445 ns) + CELL(0.130 ns) = 3.512 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 4; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~2' + Info: 6: + IC(0.235 ns) + CELL(0.130 ns) = 3.877 ns; Loc. = LCCOMB_X22_Y7_N28; Fanout = 3; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~4' + Info: 7: + IC(0.220 ns) + CELL(0.130 ns) = 4.227 ns; Loc. = LCCOMB_X22_Y7_N16; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7~0' + Info: 8: + IC(0.000 ns) + CELL(0.091 ns) = 4.318 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' + Info: Total cell delay = 1.682 ns ( 38.95 % ) + Info: Total interconnect delay = 2.636 ns ( 61.05 % ) +Warning: Can't achieve timing requirement Clock Setup: 'MAIN_CLK' along 27347 path(s). See Report window for details. +Info: Minimum slack time is 825 ps for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" + Info: + Shortest register to register delay is 0.783 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: 2: + IC(0.323 ns) + CELL(0.369 ns) = 0.692 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.783 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.460 ns ( 58.75 % ) + Info: Total interconnect delay = 0.323 ns ( 41.25 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -9.578 ns + Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -9.578 ns + Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 564 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" + Info: + Shortest register to register delay is 0.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: 2: + IC(0.301 ns) + CELL(0.130 ns) = 0.431 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.221 ns ( 42.34 % ) + Info: Total interconnect delay = 0.301 ns ( 57.66 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 502 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y28_N4; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector77~1' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.526 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.992 ns ( 84.86 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.526 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.992 ns ( 84.86 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is -454 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is 0.914 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.956 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 8.469 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 8.469 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.398 ns ( 16.51 % ) + Info: Total interconnect delay = 7.071 ns ( 83.49 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source register is 7.513 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 7.513 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.084 ns ( 14.43 % ) + Info: Total interconnect delay = 6.429 ns ( 85.57 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] along 26 path(s). See Report window for details. +Info: Minimum slack time is 502 ps for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X45_Y15_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]~3' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -3.620 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -3.620 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.559 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.534 ns ( 15.00 % ) + Info: Total interconnect delay = 3.025 ns ( 85.00 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.559 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.534 ns ( 15.00 % ) + Info: Total interconnect delay = 3.025 ns ( 85.00 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 4.336 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" + Info: + Shortest register to register delay is 0.507 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' + Info: 2: + IC(0.286 ns) + CELL(0.130 ns) = 0.416 ns; Loc. = LCCOMB_X66_Y14_N30; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.507 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' + Info: Total cell delay = 0.221 ns ( 43.59 % ) + Info: Total interconnect delay = 0.286 ns ( 56.41 % ) + Info: - Smallest register to register requirement is -3.829 ns + Info: + Hold relationship between source and destination is -3.787 ns + Info: + Latch edge is -1.094 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.538 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' + Info: Total cell delay = 0.534 ns ( 15.09 % ) + Info: Total interconnect delay = 3.004 ns ( 84.91 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.538 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' + Info: Total cell delay = 0.534 ns ( 15.09 % ) + Info: Total interconnect delay = 3.004 ns ( 84.91 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 1.825 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]" + Info: + Shortest register to register delay is 0.508 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' + Info: 2: + IC(0.287 ns) + CELL(0.130 ns) = 0.417 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.508 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' + Info: Total cell delay = 0.221 ns ( 43.50 % ) + Info: Total interconnect delay = 0.287 ns ( 56.50 % ) + Info: - Smallest register to register requirement is -1.317 ns + Info: + Hold relationship between source and destination is -1.262 ns + Info: + Latch edge is 2.693 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 3.955 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is -0.013 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.530 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.095 ns) + CELL(0.534 ns) = 3.530 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' + Info: Total cell delay = 0.534 ns ( 15.13 % ) + Info: Total interconnect delay = 2.996 ns ( 84.87 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' + Info: Total cell delay = 0.534 ns ( 15.07 % ) + Info: Total interconnect delay = 3.009 ns ( 84.93 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 3.263 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO" + Info: + Shortest register to register delay is 1.570 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y2_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[29]~4' + Info: 3: + IC(0.737 ns) + CELL(0.464 ns) = 1.570 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' + Info: Total cell delay = 0.833 ns ( 53.06 % ) + Info: Total interconnect delay = 0.737 ns ( 46.94 % ) + Info: - Smallest register to register requirement is -1.693 ns + Info: + Hold relationship between source and destination is -1.576 ns + Info: + Latch edge is 1.115 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 2.691 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is -0.019 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' + Info: 3: + IC(1.154 ns) + CELL(0.488 ns) = 3.543 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' + Info: Total cell delay = 0.488 ns ( 13.77 % ) + Info: Total interconnect delay = 3.055 ns ( 86.23 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.562 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.127 ns) + CELL(0.534 ns) = 3.562 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' + Info: Total cell delay = 0.534 ns ( 14.99 % ) + Info: Total interconnect delay = 3.028 ns ( 85.01 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.101 ns +Info: Minimum slack time is 2.664 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]" + Info: + Shortest pin to register delay is 2.216 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(0.929 ns) + CELL(0.346 ns) = 2.216 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 1.287 ns ( 58.08 % ) + Info: Total interconnect delay = 0.929 ns ( 41.92 % ) + Info: - Smallest pin to register requirement is -0.448 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -4.884 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -4.884 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 3.500 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.151 ns) + CELL(0.448 ns) = 3.500 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 0.448 ns ( 12.80 % ) + Info: Total interconnect delay = 3.052 ns ( 87.20 % ) + Info: + Micro hold delay of destination is 0.052 ns + Info: - Min Input delay of pin is 4.0 ns +Info: Minimum slack time is 502 ps for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -2.843 ns + Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -2.843 ns + Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.088 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.243 ns ( 15.37 % ) + Info: Total interconnect delay = 6.845 ns ( 84.63 % ) + Info: - Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source register is 8.088 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.243 ns ( 15.37 % ) + Info: Total interconnect delay = 6.845 ns ( 84.63 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is -687 ps for clock "CLK33M" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is 1.147 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 1.189 ns + Info: + Longest clock path from clock "CLK33M" to destination register is 7.681 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.161 ns) + CELL(0.733 ns) = 2.812 ns; Loc. = FF_X33_Y18_N25; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M' + Info: 4: + IC(0.852 ns) + CELL(0.311 ns) = 3.975 ns; Loc. = LCCOMB_X26_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4' + Info: 5: + IC(0.197 ns) + CELL(0.130 ns) = 4.302 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.034 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 7.681 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 2.626 ns ( 34.19 % ) + Info: Total interconnect delay = 5.055 ns ( 65.81 % ) + Info: - Shortest clock path from clock "CLK33M" to source register is 6.492 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 6.492 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 2.006 ns ( 30.90 % ) + Info: Total interconnect delay = 4.486 ns ( 69.10 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement CLK33M along 26 path(s). See Report window for details. +Info: Minimum slack time is -3.786 ns for clock "MAIN_CLK" between source register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]" + Info: + Shortest register to register delay is 1.930 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' + Info: 2: + IC(1.597 ns) + CELL(0.242 ns) = 1.839 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]~1' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 1.930 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' + Info: Total cell delay = 0.333 ns ( 17.25 % ) + Info: Total interconnect delay = 1.597 ns ( 82.75 % ) + Info: - Smallest register to register requirement is 5.716 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 5.758 ns + Info: + Longest clock path from clock "MAIN_CLK" to destination register is 8.630 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' + Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.988 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.108 ns) + CELL(0.534 ns) = 8.630 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' + Info: Total cell delay = 2.858 ns ( 33.12 % ) + Info: Total interconnect delay = 5.772 ns ( 66.88 % ) + Info: - Shortest clock path from clock "MAIN_CLK" to source register is 2.872 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.357 ns) + CELL(0.534 ns) = 2.872 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' + Info: Total cell delay = 1.515 ns ( 52.75 % ) + Info: Total interconnect delay = 1.357 ns ( 47.25 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement MAIN_CLK along 108 path(s). See Report window for details. +Warning: Can't achieve timing requirement tsu along 6867 path(s). See Report window for details. +Info: Slack time is -4.528 ns for clock "MAIN_CLK" between source clock "MAIN_CLK" and destination register "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state" + Info: + tsu requirement for source pin and destination register is 1.000 ns + Info: - tsu from clock to input pin is 5.528 ns + Info: + Longest clock to register delay is 8.706 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(4.109 ns) + CELL(0.869 ns) = 5.959 ns; Loc. = PLL_2; Fanout = 4; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|scandone' + Info: 4: + IC(1.722 ns) + CELL(0.130 ns) = 7.811 ns; Loc. = LCCOMB_X21_Y26_N18; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~0' + Info: 5: + IC(0.198 ns) + CELL(0.130 ns) = 8.139 ns; Loc. = LCCOMB_X21_Y26_N28; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~1' + Info: 6: + IC(0.346 ns) + CELL(0.130 ns) = 8.615 ns; Loc. = LCCOMB_X22_Y26_N16; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~2' + Info: 7: + IC(0.000 ns) + CELL(0.091 ns) = 8.706 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' + Info: Total cell delay = 2.331 ns ( 26.77 % ) + Info: Total interconnect delay = 6.375 ns ( 73.23 % ) + Info: + Micro setup delay of destination is -0.015 ns + Info: - Shortest clock path from clock "MAIN_CLK" to destination register is 3.163 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.648 ns) + CELL(0.534 ns) = 3.163 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' + Info: Total cell delay = 1.515 ns ( 47.90 % ) + Info: Total interconnect delay = 1.648 ns ( 52.10 % ) +Warning: Can't achieve timing requirement tco along 4976 path(s). See Report window for details. +Info: Slack time is -14.84 ns for clock "MAIN_CLK" between source register "interrupt_handler:nobody|INT_LATCH[8]" and destination pin "nIRQ[5]" + Info: + tco requirement for source register and destination pin is 1.000 ns + Info: - tco from clock to output pin is 15.840 ns + Info: + Longest clock path from clock "MAIN_CLK" to source register is 9.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' + Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.232 ns) + CELL(0.733 ns) = 7.221 ns; Loc. = FF_X18_Y15_N21; Fanout = 5; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' + Info: 7: + IC(0.716 ns) + CELL(0.308 ns) = 8.245 ns; Loc. = LCCOMB_X15_Y15_N6; Fanout = 1; COMB Node = 'interrupt_handler:nobody|INT_LATCH[8]~19' + Info: 8: + IC(0.681 ns) + CELL(0.534 ns) = 9.460 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' + Info: Total cell delay = 3.899 ns ( 41.22 % ) + Info: Total interconnect delay = 5.561 ns ( 58.78 % ) + Info: + Micro clock to output delay of source is 0.199 ns + Info: + Longest register to pin delay is 6.181 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' + Info: 2: + IC(0.325 ns) + CELL(0.241 ns) = 0.566 ns; Loc. = LCCOMB_X16_Y12_N20; Fanout = 1; COMB Node = 'interrupt_handler:nobody|_~17' + Info: 3: + IC(0.198 ns) + CELL(0.130 ns) = 0.894 ns; Loc. = LCCOMB_X16_Y12_N22; Fanout = 1; COMB Node = 'interrupt_handler:nobody|nIRQ[5]' + Info: 4: + IC(1.158 ns) + CELL(4.129 ns) = 6.181 ns; Loc. = IOOBUF_X0_Y12_N16; Fanout = 1; COMB Node = 'nIRQ[5]~output' + Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 6.181 ns; Loc. = PIN_P5; Fanout = 0; PIN Node = 'nIRQ[5]' + Info: Total cell delay = 4.500 ns ( 72.80 % ) + Info: Total interconnect delay = 1.681 ns ( 27.20 % ) +Info: Slack time is -11.944 ns between source pin "nFB_CS1" and destination pin "FB_AD[18]" + Info: + Longest pin to pin requirement is 1.000 ns + Info: - Longest pin to pin delay is 12.944 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T8; Fanout = 1; PIN Node = 'nFB_CS1' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X14_Y0_N29; Fanout = 59; COMB Node = 'nFB_CS1~input' + Info: 3: + IC(1.591 ns) + CELL(0.241 ns) = 2.750 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 68; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1' + Info: 4: + IC(0.915 ns) + CELL(0.130 ns) = 3.795 ns; Loc. = LCCOMB_X29_Y10_N14; Fanout = 12; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB_CS' + Info: 5: + IC(0.302 ns) + CELL(0.342 ns) = 4.439 ns; Loc. = LCCOMB_X29_Y10_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~44' + Info: 6: + IC(0.648 ns) + CELL(0.243 ns) = 5.330 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~48' + Info: 7: + IC(0.807 ns) + CELL(0.243 ns) = 6.380 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~55' + Info: 8: + IC(0.200 ns) + CELL(0.130 ns) = 6.710 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5' + Info: 9: + IC(1.088 ns) + CELL(0.242 ns) = 8.040 ns; Loc. = LCCOMB_X21_Y14_N4; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180' + Info: 10: + IC(0.876 ns) + CELL(4.028 ns) = 12.944 ns; Loc. = IOOBUF_X20_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[18]~output' + Info: 11: + IC(0.000 ns) + CELL(0.000 ns) = 12.944 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'FB_AD[18]' + Info: Total cell delay = 6.517 ns ( 50.35 % ) + Info: Total interconnect delay = 6.427 ns ( 49.65 % ) +Warning: Can't achieve timing requirement tpd along 514 path(s). See Report window for details. +Warning: Can't achieve timing requirement th along 117 path(s). See Report window for details. +Info: Minimum slack time is -401 ps for clock "MAIN_CLK" between source pin "FB_AD[25]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]" + Info: + th requirement for source pin and destination register is 1.000 ns + Info: - th from clock to input pin is 1.401 ns + Info: + Longest clock path from clock "MAIN_CLK" to destination register is 4.679 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(3.164 ns) + CELL(0.534 ns) = 4.679 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' + Info: Total cell delay = 1.515 ns ( 32.38 % ) + Info: Total interconnect delay = 3.164 ns ( 67.62 % ) + Info: + Micro hold delay of destination is 0.157 ns + Info: - Shortest pin to register delay is 3.435 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'FB_AD[25]' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X27_Y0_N8; Fanout = 59; COMB Node = 'FB_AD[25]~input' + Info: 3: + IC(2.175 ns) + CELL(0.342 ns) = 3.435 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' + Info: Total cell delay = 1.260 ns ( 36.68 % ) + Info: Total interconnect delay = 2.175 ns ( 63.32 % ) +Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. +Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 65 warnings + Info: Peak virtual memory: 238 megabytes + Info: Processing ended: Wed Dec 15 02:25:23 2010 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:11 + + diff --git a/FPGA_quartus/firebee1.tan.summary b/FPGA_quartus/firebee1.tan.summary new file mode 100644 index 0000000..219f117 --- /dev/null +++ b/FPGA_quartus/firebee1.tan.summary @@ -0,0 +1,296 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : -4.528 ns +Required Time : 1.000 ns +Actual Time : 5.528 ns +From : MAIN_CLK +To : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state +From Clock : -- +To Clock : MAIN_CLK +Failed Paths : 6867 + +Type : Worst-case tco +Slack : -14.840 ns +Required Time : 1.000 ns +Actual Time : 15.840 ns +From : interrupt_handler:nobody|INT_LATCH[8] +To : nIRQ[5] +From Clock : MAIN_CLK +To Clock : -- +Failed Paths : 4976 + +Type : Worst-case tpd +Slack : -11.944 ns +Required Time : 1.000 ns +Actual Time : 12.944 ns +From : nFB_CS1 +To : FB_AD[18] +From Clock : -- +To Clock : -- +Failed Paths : 514 + +Type : Worst-case th +Slack : -0.401 ns +Required Time : 1.000 ns +Actual Time : 1.401 ns +From : FB_AD[25] +To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] +From Clock : -- +To Clock : MAIN_CLK +Failed Paths : 117 + +Type : Clock Setup: 'CLK33M' +Slack : -5.966 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : CLK33M +Failed Paths : 3741 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' +Slack : -4.615 ns +Required Time : 24.98 MHz ( period = 40.033 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +Failed Paths : 3741 + +Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' +Slack : -4.294 ns +Required Time : 95.92 MHz ( period = 10.425 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +Failed Paths : 3741 + +Type : Clock Setup: 'MAIN_CLK' +Slack : -4.261 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : FB_ALE +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : MAIN_CLK +Failed Paths : 27347 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' +Slack : -2.673 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : FB_ALE +To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +Failed Paths : 86 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' +Slack : -1.712 ns +Required Time : 66.00 MHz ( period = 15.151 ns ) +Actual Time : N/A +From : FB_ALE +To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +Failed Paths : 29 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' +Slack : 1.672 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +Failed Paths : 0 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' +Slack : 2.965 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) +From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' +Slack : 5.299 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] +To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +Failed Paths : 0 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' +Slack : 28.590 ns +Required Time : 15.99 MHz ( period = 62.552 ns ) +Actual Time : 186.15 MHz ( period = 5.372 ns ) +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' +Slack : 498.663 ns +Required Time : 2.00 MHz ( period = 500.416 ns ) +Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' +Slack : 1997.239 ns +Required Time : 0.50 MHz ( period = 1999.998 ns ) +Actual Time : 362.45 MHz ( period = 2.759 ns ) +From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] +To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] +From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'MAIN_CLK' +Slack : -3.786 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] +To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] +From Clock : MAIN_CLK +To Clock : MAIN_CLK +Failed Paths : 108 + +Type : Clock Hold: 'CLK33M' +Slack : -0.687 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : CLK33M +To Clock : CLK33M +Failed Paths : 26 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' +Slack : -0.454 ns +Required Time : 24.98 MHz ( period = 40.033 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +Failed Paths : 26 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' +Slack : 0.502 ns +Required Time : 15.99 MHz ( period = 62.552 ns ) +Actual Time : N/A +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' +Slack : 0.502 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] +To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' +Slack : 0.502 ns +Required Time : 95.92 MHz ( period = 10.425 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' +Slack : 0.564 ns +Required Time : 2.00 MHz ( period = 500.416 ns ) +Actual Time : N/A +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' +Slack : 0.825 ns +Required Time : 0.50 MHz ( period = 1999.998 ns ) +Actual Time : N/A +From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] +To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] +From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' +Slack : 1.825 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] +To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' +Slack : 2.664 ns +Required Time : 66.00 MHz ( period = 15.151 ns ) +Actual Time : N/A +From : FB_ALE +To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' +Slack : 3.263 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' +Slack : 4.336 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 51319 + +-------------------------------------------------------------------------------------- + diff --git a/FPGA_quartus/firebee1_assignment_defaults.qdf b/FPGA_quartus/firebee1_assignment_defaults.qdf new file mode 100644 index 0000000..2119467 --- /dev/null +++ b/FPGA_quartus/firebee1_assignment_defaults.qdf @@ -0,0 +1,687 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 08:49:57 June 14, 2010 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV E" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS Off +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name PARALLEL_SYNTHESIS -value ON +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Arria II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy IV" +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? diff --git a/FPGA_quartus/firebeei1.qpf b/FPGA_quartus/firebeei1.qpf new file mode 100644 index 0000000..8ab6c97 --- /dev/null +++ b/FPGA_quartus/firebeei1.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.1" +DATE = "10:07:29 September 03, 2009" + + +# Revisions + +PROJECT_REVISION = "firebee1" diff --git a/FPGA_quartus/firebeei1.qws b/FPGA_quartus/firebeei1.qws new file mode 100644 index 0000000..89bdcec --- /dev/null +++ b/FPGA_quartus/firebeei1.qws @@ -0,0 +1,27 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +ptn_Child4=Document-3 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=firebee1.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/FPGA_quartus/lpm_bustri_BYT.bsf b/FPGA_quartus/lpm_bustri_BYT.bsf new file mode 100644 index 0000000..dcc4b63 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_BYT.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 40) + (text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 96 24) + (bidir) + (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "8" (rect 71 25 76 37)(font "Arial" )) + (text "8" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 66 28)(pt 74 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/lpm_bustri_BYT.cmp b/FPGA_quartus/lpm_bustri_BYT.cmp new file mode 100644 index 0000000..3cf925e --- /dev/null +++ b/FPGA_quartus/lpm_bustri_BYT.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_BYT + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/lpm_bustri_BYT.inc b/FPGA_quartus/lpm_bustri_BYT.inc new file mode 100644 index 0000000..8cb4941 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_BYT.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_BYT +( + data[7..0], + enabledt +) + +RETURNS ( + tridata[7..0] +); diff --git a/FPGA_quartus/lpm_bustri_BYT.qip b/FPGA_quartus/lpm_bustri_BYT.qip new file mode 100644 index 0000000..89e40bd --- /dev/null +++ b/FPGA_quartus/lpm_bustri_BYT.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.cmp"] diff --git a/FPGA_quartus/lpm_bustri_BYT.vhd b/FPGA_quartus/lpm_bustri_BYT.vhd new file mode 100644 index 0000000..d24e3cb --- /dev/null +++ b/FPGA_quartus/lpm_bustri_BYT.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_BYT.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_BYT IS + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_bustri_BYT; + + +ARCHITECTURE SYN OF lpm_bustri_byt IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 8 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0] +-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/lpm_bustri_LONG.bsf b/FPGA_quartus/lpm_bustri_LONG.bsf new file mode 100644 index 0000000..6535d3e --- /dev/null +++ b/FPGA_quartus/lpm_bustri_LONG.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 112 40) + (text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 112 24) + (bidir) + (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 112 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "32" (rect 77 25 87 37)(font "Arial" )) + (text "32" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 72 28)(pt 80 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/lpm_bustri_LONG.cmp b/FPGA_quartus/lpm_bustri_LONG.cmp new file mode 100644 index 0000000..3a268db --- /dev/null +++ b/FPGA_quartus/lpm_bustri_LONG.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_LONG + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/lpm_bustri_LONG.inc b/FPGA_quartus/lpm_bustri_LONG.inc new file mode 100644 index 0000000..f180c48 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_LONG.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_LONG +( + data[31..0], + enabledt +) + +RETURNS ( + tridata[31..0] +); diff --git a/FPGA_quartus/lpm_bustri_LONG.qip b/FPGA_quartus/lpm_bustri_LONG.qip new file mode 100644 index 0000000..67b7232 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_LONG.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.cmp"] diff --git a/FPGA_quartus/lpm_bustri_LONG.vhd b/FPGA_quartus/lpm_bustri_LONG.vhd new file mode 100644 index 0000000..3de83c0 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_LONG.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_LONG.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_LONG IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_bustri_LONG; + + +ARCHITECTURE SYN OF lpm_bustri_long IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 32 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0] +-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/lpm_bustri_WORD.bsf b/FPGA_quartus/lpm_bustri_WORD.bsf new file mode 100644 index 0000000..4e882d1 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_WORD.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 112 40) + (text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 112 24) + (bidir) + (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 112 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "16" (rect 77 25 87 37)(font "Arial" )) + (text "16" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 72 28)(pt 80 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_quartus/lpm_bustri_WORD.cmp b/FPGA_quartus/lpm_bustri_WORD.cmp new file mode 100644 index 0000000..1f03a0e --- /dev/null +++ b/FPGA_quartus/lpm_bustri_WORD.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_WORD + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/lpm_bustri_WORD.inc b/FPGA_quartus/lpm_bustri_WORD.inc new file mode 100644 index 0000000..09f6251 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_WORD.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_WORD +( + data[15..0], + enabledt +) + +RETURNS ( + tridata[15..0] +); diff --git a/FPGA_quartus/lpm_bustri_WORD.qip b/FPGA_quartus/lpm_bustri_WORD.qip new file mode 100644 index 0000000..57bbe2e --- /dev/null +++ b/FPGA_quartus/lpm_bustri_WORD.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.cmp"] diff --git a/FPGA_quartus/lpm_bustri_WORD.vhd b/FPGA_quartus/lpm_bustri_WORD.vhd new file mode 100644 index 0000000..85cbdd1 --- /dev/null +++ b/FPGA_quartus/lpm_bustri_WORD.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_WORD.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_WORD IS + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_bustri_WORD; + + +ARCHITECTURE SYN OF lpm_bustri_word IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 16 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] +-- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/lpm_counter0.bsf b/FPGA_quartus/lpm_counter0.bsf new file mode 100644 index 0000000..7fc7aaa --- /dev/null +++ b/FPGA_quartus/lpm_counter0.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 64) + (text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 48 25 60)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 144 40) + (output) + (text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8))) + (line (pt 144 40)(pt 128 40)(line_width 3)) + ) + (drawing + (text "up counter" (rect 84 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 48)(line_width 1)) + (line (pt 128 48)(pt 16 48)(line_width 1)) + (line (pt 16 48)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_quartus/lpm_counter0.cmp b/FPGA_quartus/lpm_counter0.cmp new file mode 100644 index 0000000..ad18248 --- /dev/null +++ b/FPGA_quartus/lpm_counter0.cmp @@ -0,0 +1,22 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_counter0 + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/lpm_counter0.qip b/FPGA_quartus/lpm_counter0.qip new file mode 100644 index 0000000..a72845b --- /dev/null +++ b/FPGA_quartus/lpm_counter0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] diff --git a/FPGA_quartus/lpm_counter0.vhd b/FPGA_quartus/lpm_counter0.vhd new file mode 100644 index 0000000..9135dbc --- /dev/null +++ b/FPGA_quartus/lpm_counter0.vhd @@ -0,0 +1,126 @@ +-- megafunction wizard: %LPM_COUNTER% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_counter + +-- ============================================================ +-- File Name: lpm_counter0.vhd +-- Megafunction Name(s): +-- lpm_counter +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_counter0 IS + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END lpm_counter0; + + +ARCHITECTURE SYN OF lpm_counter0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0); + + + + COMPONENT lpm_counter + GENERIC ( + lpm_direction : STRING; + lpm_port_updown : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(17 DOWNTO 0); + + lpm_counter_component : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_type => "LPM_COUNTER", + lpm_width => 18 + ) + PORT MAP ( + clock => clock, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CarryIn NUMERIC "0" +-- Retrieval info: PRIVATE: CarryOut NUMERIC "0" +-- Retrieval info: PRIVATE: Direction NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "18" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" +-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE 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za-(M2sF^lurj45EfA!!SHPc4Tv{5r{;7l7h69lwv;7l7h(?0;&P+R)1^HW2F~>Nfcl?-dq-`){;>fgbqo$J?1gWQ}nZx zpV)SyXpeo7rhTzl`_6>DW!p|@TOCX|pX0B@+oyEz)|nq~SwB4=ZkB#gQ#QT*yzco1 zT+Lv(S*_cCstuTKzxVMOS6VXHouWNRMbkZP%F* + +Sample Waveforms for lpm_counter0.vhd + + +

Sample behavioral waveforms for design file lpm_counter0.vhd

+

The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter.

+
+

Fig. 1 : Wave showing counter operation.

+

+

+ + diff --git a/FPGA_quartus/lpm_counter1_waveforms.html b/FPGA_quartus/lpm_counter1_waveforms.html new file mode 100644 index 0000000..cea3320 --- /dev/null +++ b/FPGA_quartus/lpm_counter1_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for lpm_counter1.vhd + + +

Sample behavioral waveforms for design file lpm_counter1.vhd

+

The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter.

+
+

Fig. 1 : Wave showing counter operation.

+

+
+

Fig. 2 : Wave showing counter cout and/or modulus operation.

+

The counter counts till the modulus value 7.

+

+ + diff --git a/FPGA_quartus/lpm_fifo_dc0_waveforms.html b/FPGA_quartus/lpm_fifo_dc0_waveforms.html new file mode 100644 index 0000000..12ad5c2 --- /dev/null +++ b/FPGA_quartus/lpm_fifo_dc0_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for "lpm_fifo_dc0.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd"

+

The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions .

+
+

Fig. 2 : Wave showing FIFO full operation.

+

The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.

+

+ + diff --git a/FPGA_quartus/lpm_latch0.bsf b/FPGA_quartus/lpm_latch0.bsf new file mode 100644 index 0000000..ddb325c --- /dev/null +++ b/FPGA_quartus/lpm_latch0.bsf @@ -0,0 +1,53 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 80) + (text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) + (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 64)(line_width 1)) + (line (pt 144 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_quartus/lpm_latch0.cmp b/FPGA_quartus/lpm_latch0.cmp new file mode 100644 index 0000000..87fbc04 --- /dev/null +++ b/FPGA_quartus/lpm_latch0.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_latch0 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_quartus/lpm_latch0.qip b/FPGA_quartus/lpm_latch0.qip new file mode 100644 index 0000000..1bda27a --- /dev/null +++ b/FPGA_quartus/lpm_latch0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.cmp"] diff --git a/FPGA_quartus/lpm_latch0.vhd b/FPGA_quartus/lpm_latch0.vhd new file mode 100644 index 0000000..1eda161 --- /dev/null +++ b/FPGA_quartus/lpm_latch0.vhd @@ -0,0 +1,110 @@ +-- megafunction wizard: %LPM_LATCH% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_latch + +-- ============================================================ +-- File Name: lpm_latch0.vhd +-- Megafunction Name(s): +-- lpm_latch +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_latch0 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_latch0; + + +ARCHITECTURE SYN OF lpm_latch0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_latch + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_latch_component : lpm_latch + GENERIC MAP ( + lpm_type => "LPM_LATCH", + lpm_width => 32 + ) + PORT MAP ( + data => data, + gate => gate, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: aset NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_quartus/serv_req_info.txt b/FPGA_quartus/serv_req_info.txt new file mode 100644 index 0000000..51a4176 --- /dev/null +++ b/FPGA_quartus/serv_req_info.txt @@ -0,0 +1,115 @@ + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:01:46 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:11:00 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: GED + Wed Oct 14 23:17:06 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW, STED + Thu Oct 15 19:23:19 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW, STED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + + 0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6) + + Current editor: RPW, SFW +Current dockable window: PJN + Fri Oct 16 00:14:03 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 0X1002D196 +Current editor: RPW, SFW +Current dockable window: PJN +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW + Sat Oct 17 19:01:54 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + AFC + /quartus/gcl/afc/afc_child_frame.cpp + 1940 + + 0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a) + + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) + Mon Oct 19 21:58:36 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: RPW, GED + Tue Oct 20 00:53:11 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: RPW, GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + diff --git a/FPGA_quartus/undo_redo.txt b/FPGA_quartus/undo_redo.txt new file mode 100644 index 0000000..e69de29 diff --git a/Flash/BaS_15_12_10.S19 b/Flash/BaS_15_12_10.S19 new file mode 100644 index 0000000..27a561c --- /dev/null +++ b/Flash/BaS_15_12_10.S19 @@ -0,0 +1,362 @@ +S0030000FC +S321E000000060064EF9E000000846FC2700203CFF0000004E7B0C0F23C0FF10084483 +S321E000001C203CFF0400014E7B0008428023C0FF040000203CFF1000074E7B0C04BE +S321E0000038203CFF1010014E7B0C054FF9FF100FFC203C000C81004E7B00024E719B +S321E000005460FF00000D0E4E7541F9FF00090020BCFFFFFFFF41F9FF00090410BC41 +S321E0000070000541F9FF00860C20BC534C542041F9FF00860C20BC4F4B212041F913 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z)MC|UW_73TtJ;-eDsGQLW%_vSZ?`ghz$nXuLtuhof`Ng-f_=wG5bQh`Pv*Xa0LzSl z2E+Te`hSD;|E-0!i@AxpxsipFrLhq!rx7cg5i1Lmi;0D@JQVc*?g9TdrT + + ; define config bits + __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _XT_OSC + + ;4 MHz Clock + +;************************ Input output usage ******************** + +; RA0 Atari / Amiga select i/p +; RA1 PS2 mouse data +; RA2 PS2 mouse clock +; RA3 Not used +; RA4 Not used + +; RB0 Atari XA / Amiga XA o/p +; RB1 Atari XB / Amiga YB o/p +; RB2 Atari YA / Amiga YA o/p +; RB3 Atari YB / Amiga XB o/p +; RB4 Left button o/p +; RB5 Right button o/p +; RB6 Not used +; RB7 Not used + +;******************************************************************* + + +;********** I/O port equates ************** + + +ps2data equ 1 ;ps2 mouse data signal +ps2clk equ 2 ;ps2 mouse clock signal + + +;********** User register equates ********* + +temp equ 0ch ;Temporary storage +byte1 equ 0dh ;Byte 1 store +byte2 equ 0eh ;Byte 2 store +byte3 equ 0fh ;Byte 3 store +xinc equ 010h ;last x increment read +yinc equ 011h ;last y increment read +xlow equ 012h ;low byte of 16 bit x counter +xhigh equ 013h ;high byte of 16 bit x counter +ylow equ 014h ;low byte of 16 bit y counter +yhigh equ 015h ;high byte of 16 bit y counter +xpat equ 016h ;x pattern position +ypat equ 017h ;y pattern position +bcnt equ 018h ;bit counter +brec equ 019h ;byte received +timer equ 01ah ;timer counter +parity equ 01bh ;parity store +flag equ 01ch ;flag bits (bit 0 = ack error flag) + ; (bit 1 = parity error flag) + ; (bit 2 = middle button pressed flag) + ; (bit 3 = middle state flag) + ; (bit 4 = left button flag) + +;***************************************************************************************** + +;***** initialise program ******* + +reset clrwdt + bcf status,rp0 ;set page0 + clrf intcon ;disable interupts + bsf status,rp0 + movlw 084h ;set tmr0 to int clk,prescale/32 + movwf option_reg + bcf status,rp0 + clrf porta ;all porta outputs will be low when enabled + movlw 0h ;set mouse buttons and x y start levels + movwf portb + bsf status,rp0 + movlw 017h ;set porta bit 3 as an unused output + movwf trisa + movlw 030h ;set portb bit 4 and 5 as inputs (left/right button o/ps open collector) + movwf trisb + bcf status,rp0 + + clrf byte1 ;set start up values + clrf byte2 + clrf byte3 + clrf xinc + clrf yinc + clrf xlow + clrf xhigh + clrf ylow + clrf yhigh + clrf xpat + clrf ypat + clrf flag + + +;***************** set up ps2 mouse ********************* + + +start call ps2read ;read power up self test report + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0aah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read power up pc mouse id + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0h ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + +restart movlw 0ffh ;send reset pc mouse command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read self test report + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0aah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read pc mouse id + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0h ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + movlw 0f4h ;send enable reporting command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + + movlw 0f3h ;send set sample rate command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + + movlw 028h ;send sample rate (40) + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + +;******************* Main program loop **************************** + +main call ps2read ;read 3 byte pc mouse packet + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte1 + call ps2read + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte2 + call ps2read + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte3 + +;adjust the 16 bit x counter + + clrf temp ;use temp as high byte + btfsc byte1,4 ;extend sign bit into high byte + decf temp,f + + movf byte2,w ;add low bytes + addwf xlow,f + btfsc status,c ;add carry to high + incf xhigh,f + movf temp,w ;add high bytes + addwf xhigh,f + +;adjust the 16 bit y counter + + clrf temp ;use temp as high byte + btfsc byte1,5 ;extend sign bit into high byte + decf temp,f + + movf byte3,w ;add low bytes + addwf ylow,f + btfsc status,c ;add carry to high + incf yhigh,f + movf temp,w ;add high bytes + addwf yhigh,f + +;left button + + btfss byte1,0 ;is the left pc mouse button pressed + goto lbutt ;no so jump + bsf flag,4 ;set left button flag + goto nbutt +lbutt bcf flag,4 ;reset left button flag + +;right button + +nbutt btfss byte1,1 ;is the right pc mouse button pressed + goto rbutt ;no so jump + bcf portb,5 ;set right button as pressed + bsf status,rp0 ;by setting pin as a low output + bcf trisb,5 + bcf status,rp0 + goto mbut +rbutt bsf status,rp0 ;set right button as not pressed + bsf trisb,5 ;by setting pin as an input + bcf status,rp0 + +;middle button + +mbut btfss byte1,2 ;check if middle button pressed + goto mbutt ;jump if not + btfsc flag,2 ;check middle button pressed flag + goto mbex ;set so jump + movlw 08h ;toggle middle state flag + xorwf flag,f + bsf flag,2 ;set middle button pressed flag + goto mbex + +mbutt btfss flag,2 + goto mbex + bcf flag,2 ;reset middle button pressed flag +mbex + + btfsc flag,3 ;check middle state flag + goto setlb ;jump if set + btfsc flag,4 ;check left button flag + goto setlb ;jump if set + bsf status,rp0 ;no flags set so set left buuton not pressed + bsf trisb,4 ;by setting pin as an input + bcf status,rp0 + goto main +setlb bcf portb,4 ;set left button pressed + bsf status,rp0 ;by setting pin as a low output + bcf trisb,4 + bcf status,rp0 + goto main + + +;***************************** Subs ***************************************** + +;***** Read a byte from the ps2 mouse ****** + +ps2read btfss porta,ps2data ;data low ? + goto ps2r1 ;yes so start reading data + call trans ;no so do emulated mouse move + clrf tmr0 ;clear rtcc before delay + +oned btfss porta,ps2data ;data low ? + goto ps2r1 ;yes so start reading data + movlw 0dh ;delay between emulated mouse moves + subwf tmr0,w + btfss status,z + goto oned ;not done so jump + goto ps2read ;check again + +ps2r1 call wlow ;wait until clock goes low for start bit + + call whigh ;wait until clock is high + + movlw 08h ;read 8 data bits + movwf bcnt + clrf parity ;clear parity counter + +ps2r2 call wlow ;wait until clock is low + bcf status,c ;clear carry flag + btfss porta,ps2data ;data bit set ? + goto ps2r3 ;no so jump + incf parity,f ;yes so inc the parity counter + bsf status,c ;set carry bit +ps2r3 rrf brec,f ;shift carry into destination + + call whigh ;wait until clock is high + + decfsz bcnt,f ;finished the 8 bits? + goto ps2r2 ;no so do again + + call wlow ;for the parity bit + btfsc porta,ps2data ;parity bit set? + incf parity,f ;yes so inc the parity counter + bcf flag,1 ;clear flag (no error) + btfss parity,0 ;check calculated parity + bsf flag,1 ;set flag (parity error!) + call whigh + + call wlow ;for the stop bit + call whigh + + return ;and exit + +;***** Write a byte to the ps2 mouse ****** + +ps2wri movwf brec ;speed not important at this point so + movwf temp ;calculate parity seperate for sake of + movlw 08h ;clarity + movwf bcnt + clrf parity +ps2w1 rrf temp,f ;shift bit into carry + movlw 01h ;preset for bit set + btfss status,c ;test carry + clrw ;bit zero so no addition + addwf parity,f ;update parity + decfsz bcnt,f ;any more bits to do? + goto ps2w1 ;yes so jump + comf parity,f ;only intrested in bit 0. + ;parity bit is complement of bit 0 + + movlw 08h ;bit count to 8 + movwf bcnt + + call clkl ;set clock low + + movlw 021h ;wait 100 uS + movwf temp +ps2ww decfsz temp,f + goto ps2ww + + call datl ;set data low + nop ;wait 5 uS + nop + nop + nop + nop + call clkh ;set clock high + +ps2w2 call wlow ;wait for clock to go low + rrf brec,f ;rotate bit into carry for testing + btfss status,c + goto ps2w3 ;jump if bit is low + call dath ;set data high + goto ps2w4 +ps2w3 call datl ;set data low +ps2w4 call whigh ;wait for clock to go high + + decfsz bcnt,f ;any more bits to send? + goto ps2w2 ;yes so jump + + call wlow ;wait for clock to go low + btfss parity,0 ;send parity bit + goto ps2w5 + call dath + goto ps2w6 +ps2w5 call datl +ps2w6 call whigh + + call wlow ;send stop bit + call dath + call whigh + + call wlow ;read ack from mouse + bcf flag,0 + btfsc porta,ps2data + bsf flag,0 + call whigh + + return + + +;******* wait for ps2 clock to go low ********** + +wlow btfsc porta,ps2clk + goto wlow + return + + +;******* wait for ps2 clock to go high ********** + +whigh btfss porta,ps2clk + goto whigh + return + + +;******* set ps2 clock low ********************* + +clkl bsf status,rp0 + bcf trisa,ps2clk + bcf status,rp0 + return + + +;******* set ps2 clock high ******************** + +clkh bsf status,rp0 + bsf trisa,ps2clk + bcf status,rp0 + return + + +;******* set ps2 data low ********************* + +datl bsf status,rp0 + bcf trisa,ps2data + bcf status,rp0 + return + + +;******* set ps2 data high ********************* + +dath bsf status,rp0 + bsf trisa,ps2data + bcf status,rp0 + return + + + +;********* emulate mouse move *************************** + +;move the emulated mouse by one step in the x direction if needed + +trans movf xlow,w ;is the x counter zero? + iorwf xhigh,w + btfsc status,z + goto ymove ;no so jump to y direction + + btfsc xhigh,7 ;is the x counter positive or negative? + goto xneg ;jump if negative + + incf xpat,f ;increment the pattern list position + movlw 04h ;test if end of pattern list + subwf xpat,w + btfsc status,z + clrf xpat ;end of pattern list so reset + movlw 0ffh ;subtract 1 from the 16 bit counter by adding ffffh + addwf xlow,f + btfsc status,c ;add carry to high byte + incf xhigh,f + addwf xhigh,f + goto ymove ;exit to y direction + +xneg decf xpat,f ;decrement the pattern list position + movlw 0ffh ;test if end of pattern list + subwf xpat,w + btfss status,z + goto xno + movlw 03h ;end of pattern list so reset + movwf xpat +xno movlw 01h ;add 1 to the 16 bit counter + addwf xlow,f + btfsc status,c ;add carry to high byte + incf xhigh,f + +;move the emulated mouse by one step in the y direction if needed + +ymove movf ylow,w ;is the y counter zero? + iorwf yhigh,w + btfsc status,z + goto out ;no so jump to output pattern + + btfsc yhigh,7 ;is the y counter positive or negative? + goto yneg ;jump if negative + + incf ypat,f ;increment the pattern list position + movlw 04h ;test if end of pattern list + subwf ypat,w + btfsc status,z + clrf ypat ;end of pattern list so reset + movlw 0ffh ;subtract 1 from the 16 bit counter by adding ffffh + addwf ylow,f + btfsc status,c ;add carry to high byte + incf yhigh,f + addwf yhigh,f + goto out ;exit to output pattern + +yneg decf ypat,f ;decrement the pattern list position + movlw 0ffh ;test if end of pattern list + subwf ypat,w + btfss status,z + goto yno + movlw 03h ;end of pattern list so reset + movwf ypat +yno movlw 01h ;add 1 to the 16 bit counter + addwf ylow,f + btfsc status,c ;add carry to high byte + incf yhigh,f + +;output new x and y patterns + +out btfsc porta,0 ;test if set for atari + goto amiga + + movf xpat,w ;get the x pattern bits + bsf pclath,1 ;set page 2 + call pattx + movwf temp ;store the pattern in temp + movf ypat,w ;get the y pattern bits + call patty + clrf pclath ;set page 0 + iorwf temp,f ;store the pattern in temp + + goto outpat + +amiga movf xpat,w ;get the x pattern bits + bsf pclath,1 ;set page 2 + call apatx + movwf temp ;store the pattern in temp + movf ypat,w ;get the y pattern bits + call apaty + clrf pclath ;set page 0 + iorwf temp,f ;store the pattern in temp + +outpat movf temp,w ;get patterns + andlw 0fh ;ensure high nibble stays zero + movwf portb ;ouput patterns + + + return + + +;*************** pattern lists ************** + + org 0200h + +;atari patterns +pattx addwf pcl,f + retlw 0 + retlw 1 + retlw 3 + retlw 2 + +patty addwf pcl,f + retlw 0 + retlw 4 + retlw 0ch + retlw 8 + +;amiga patterns +apatx addwf pcl,f + retlw 0 + retlw 1 + retlw 9 + retlw 8 + +apaty addwf pcl,f + retlw 0 + retlw 4 + retlw 6 + retlw 2 + +;******************************************************************************* + + END + + diff --git a/MLAB/firebee1/Thumbs.db b/MLAB/firebee1/Thumbs.db new file mode 100644 index 0000000000000000000000000000000000000000..5c84dfb6d19a66e008ecbeb8e2f2638efa71ba6d GIT binary patch literal 22528 zcmeFYcUV+UmoB;ykeqXBvY_OglSq;u5|k_;B9dvz4Kz9DB%mNk1SE@OXmS?GNpe&& zbQ4=>n$ynAH#6t^=FBtqKIi^%&YkM#-Jy2vu38n=s#^8#@iB_Ef*Qtk;O~MWfDNE; z34pu*E*=YW{RjUP$N}IE=Hkyi`u6trpCbVPbNS!l|DYPU!Ibq+`~AV6fQxC!KW&bO z0X_x<7!YDWgaI)IBp8rlK!yRP3jh=tP+~xZ0W}6R7|>!shXFkXfBu&db7sPT83Ps! zKp3!Mz=i=k1{@f0V!(v~HwO1G;K6_wgZmgfz~FD?`=>(w_u+qA4Hy7m%+C|k7HWVi z=IjpmVru)p9%upFe;xCGbiscX)=a7lEmViG{d{#){YI6naHVExfUf2)vxNbny-;9%ms{&X%(__zEeFu95TQ|{83 z{Dc89%(V>$w*PeZ&#C|Mh{^w7^ZrwYe@yX@F$|cf$UmL_e^dCI?ElsL|9!Uq{@wq+ z{{LSM{L#_a7`XmRe}praXd^kz&HjBK`S0uhdu!lt?Qiif`mmbZ^~dzG9rf*x+ckjv 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zfp@;P`Nm`V$>60|*^}}!EW`PfKlgxjL_+-rPwn2y;?n)2O}r=u9>$}N>#EP`Cxh$M zpRvEAc|-V9`_i6Sx^MMQ8IPnLz?1WWx9pDn6nS`i8qbH&p%XG*KfglTc^g0J{p9J= z>wA=k7a0i_W{l@)N0c|{!}#qjz0Uf34W4dVuwO#$arzGM&>oZWY+J|1lK4f_!cFj( z&dJ&A@?NV6j{NdG!u3PuP)73>@(NV-;Fr`7Zq%VYV{#3ir(J{BN{k=8X_dl@sXN?6 zf8mnRU%&5&8WXJJJo>TqNIU+pO%0-Jgxt{wCMcH785lX SQ|X7!8>9YTivKJ|;J*Q^($^~h literal 0 HcmV?d00001 diff --git a/MLAB/firebee1/firebee1.asm b/MLAB/firebee1/firebee1.asm new file mode 100644 index 0000000..cc1d11a --- /dev/null +++ b/MLAB/firebee1/firebee1.asm @@ -0,0 +1,845 @@ +;********************************************************** +;* firebee1 PIC18F4321 MAIN FILE +;********************************************************** +;* CREATED BY FREDI ASCHWANDEN +;* DATE 22.9.2009 +;********************************************************** + list PE=18f4520 ;EXTENDED INSTRUCTION SET + include "P18f4520.inc" +;------------------------ Equates --------------------------; +;Register addresses +;BANK 0 +SECS equ 0x00 +SECS_ALARM EQU 0x01 +MINS equ 0x02 +MINS_ALRAM EQU 0x03 +HOURS equ 0x04 +HOURS_ALARM EQU 0x05 +DAY_OF_WEEK EQU 0x06 +DAYS EQU 0x07 +MONTHS EQU 0x08 +YEARS EQU 0x09 ;offset vom 1968 +REGA EQU 0x0A +REGB EQU 0x0B +REGC EQU 0x0C +REGD EQU 0x0D +RTC_RAM EQU 0x0E ; bis 0x3F +free equ 0x40 +TICKS equ 0x41 ;125MS +TASTE_ON_TIME EQU 0x42 +TASTE_OFF_TIME EQU 0x43 +POWER_ON_TIME EQU 0x44 +AD_KANAL EQU 0x45 +U_ERR EQU 0x46 ;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WARTEN AUF GELADEN +U_ERR_TIME EQU 0x47 ;ZEIT SEIT SPANNUNGSFEHLER +U_POWER_IN EQU 0x48 ;SPANNUNG POWER IN 1V CA. 6E +RX_B EQU 0x49 ;RECEIVED BYT +RX_STATUS EQU 0x4A ;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x82=EMPFANGE 64BYT FROM RTC +TX_STATUS EQU 0x4B ;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM RTC +GO_SUB EQU 0x4C ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN +GO_INT EQU 0x4D ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN +EAPIR1 EQU 0x4E ;INTERRUPT ACTIV UND ENABLE +EAPIR2 EQU 0x4F ;INTERRUPT ACTIV UND ENABLE +;BANK 1 AB 0x100 +RX_BUFFER EQU 0x100 ;0x80 BYT BUFFER BIS 0x17F BANK +TX_BUFFER EQU 0x180 ;0X80 BYT BUFFER BIS 0x1FF BANK + +;-------------------------------------------------------------- +SEND_RTC_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +RESET_ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +RESET_OFF_TIME EQU .4 ;0.5 SEC (EINHEIT IST EIN TICK = 128MS +OFF_TIME EQU .20 ;2.5 SEC (EINHEIT IST EIN TICK = 128MS +ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +TIMER_HB EQU .240 ;256- (32768Hz PRO 1/8SEC = 4096TICKS/256) => 256-16=240 (resp 256-16/4 (wenn osco) = 252) +TIME_MAX EQU .160 ;MAXIMALTIME +U_ERR_PW_AUS EQU .5 ;5 SEC +;SERIEL +SYNC1 EQU 0FFh +SYNC1_DATA EQU 'A'; +SYNC2 EQU 0FEh +SYNC2_DATA EQU 'C'; +SYNC3 EQU 0FDh +SYNC3_DATA EQU 'P'; +SYNC4 EQU 0FCh +SYNC4_DATA EQU 'F'; +REQ_RTCD_FROM_PIC EQU 01h ;RTC AND NVRAM DATEN VOM PIC ANFORDERN +RTCD_FROM_PIC EQU 81h ;RTC AND NVRAM DATEN HEADER UND STATUS +REQ_RTCD_FROM_MCF EQU 02h ;RTC AND NVRAM DATEN VOM MCF ANFORDERN +RTCD_FROM_MCF EQU 82h ;RTC AND NVRAM DATEN HEADER UND STATUS +U_MIN_TO_MCF EQU 03h ;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR +EXT_SUB_GO EQU 04h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU AKTIVIEREN +EXT_SUB_STOP EQU 05h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU STOPPEN +CLK_SLEEP EQU B'00010010' ;125kHz intern, SLEEP MODE +CLK_ACTIV EQU B'01110010' ;inTernal CLK=8MHz, SLEEP MODE, SLEEP MODE +EXT_CODE EQU 0xFB ;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS AUSFÜHREN (FireBee!) +EXTERN_INT_ADR EQU 0x2000 ;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS AUSFÜHRBAR +EXTERN_INTERRUPTS EQU 0x2002 ;STARTPUNKT EXTERNE SUBROUTINES +EXTERN_SUB_ADR EQU 0x2010 ;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES AUSFÜHRBAR +EXTERN_SUBROUTINES EQU 0x2012 ;STARTPUNKT EXTERNE SUBROUTINES +REQ_BLOCK EQU 0xA0 ;BLOCK DATEN LESEN -> CODE UND 3 BYTS ADRESSE = TOTAL 4 BYTES +READ_BLOCK EQU 0xA1 ;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES +WRITE_BLOCK EQU 0xA2 ;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES +PRG_OK_PIC EQU 0x22 ;PROGRAMMIERUNG BLOCK FERTIG +;**********************************************************************************************""""""""""""" +; Start at the reset vector +Reset_Vector code 0x000 + BRA KALT_START +;-------------------------------------------------------------- +HIGH_INT_VEC code 0x0008 + GOTO 0x18 + +LOW_INT_VEC code 0x0018 +INT_HANDLER + CLRF BSR ;IMMER ACCESS BANK +;SETZEN GRUPPE 1 + MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN + MOVF PIR1,0 ;MASKE + ANDWF EAPIR1 ;ACTIVE SETZEN + BTFSC EAPIR1,TMR1IF ;uhr interrupt? + BRA RTC_ISR ;ja-> + BTFSC EAPIR1,ADIF ;AD INTERRUTP? + BRA AD_ISR ;JA-> + BTFSC EAPIR1,TXIF ;seriell TX? + BRA TX_ISR ;JA-> + BTFSC EAPIR1,RCIF ;seriell RX? + BRA RX_ISR ;JA-> + +;SETZEN GRUPPE 2 + MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN + MOVF PIR2,0 ;MASKE + ANDWF EAPIR2 ;ACTIVE SETZEN + + BTFSC EAPIR2,HLVDIF ;UNDER/OVERVOLTAGE DETECT + BRA HLVD_ISR ;JA-> + RETFIE + +;TESTEN UND SETZEN GRUPPE 1 + MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN + MOVF PIR1,0 ;MASKE + ANDWF EAPIR1 ;ACTIVE SETZEN + TSTFSZ EAPIR1 + BRA INT_HANDLER +;TESTEN UND SETZEN GRUPPE 2 + MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN + MOVF PIR2,0 ;MASKE + ANDWF EAPIR2 ;ACTIVE SETZEN + TSTFSZ EAPIR2 + BRA INT_HANDLER + + MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? + CPFSEQ GO_INT ;SKIP WENN JA + RETFIE + GOTO EXTERN_INTERRUPTS ;REGISTER SICHERN UND STARTEN +;**********************************************************************************************""""""""""""" + ; Start application beyond vector area + CODE 0x0100 +KALT_START +;RESET MODE + CLRF BSR ;BANK 0 +;ALLE INT AUS UND RÜCKSETZEN + CLRF INTCON ;alle INTERRUPT AUS + CLRF RCON ;INT PRIORITY AUS + CLRF PIE1 ;MASK DISABLE + CLRF PIE2 + CLRF PIR1 ;INT ACT AUS + CLRF PIR2 + CLRF IPR1 ;LOW PRIORITY + CLRF IPR2 + ; clock +; MOVLW B'01000000' ;32MHZ +; MOVWF OSCTUNE + CLRF OSCTUNE +;CLOCK + MOVLW CLK_ACTIV + MOVWF OSCCON + ; div init +;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3/2 **1:1V25 **0:POWER_IN/11 + CLRF PORTA ;#master(7)=0, REST=0 + MOVLW B'11111111' ;DIRECTION: alles auf Input + MOVWF TRISA +;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PORT PIN6 **0: GAME PORT PIN5 + CLRF PORTB ;ALLES AUF 0 + MOVWF TRISB +;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN13 **1+0: OCS 32K768Hz + CLRF PORTC + MOVWF TRISC +;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1:TASTER **0:POWER ON/OFF (0=ON) +; SET TASTE UND POWER + CLRF PORTD ;ALLES AUF 0 + MOVWF TRISD ;ALLES AUF INPUT +;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON) + MOVLW B'00000001' ;LED OFF + CLRF PORTE ;ALLES AUF 0 + MOVWF TRISE ;ALLES AUF INPUT +;-------------------------- +; set OVERvoltage detekt + MOVLW B'10011011' ;INT WENN ÜBER 3.9V + MOVWF HLVDCON + MOVLW B'00000011' ;ERRORS ON, WAIT AUF LADEN + MOVWF U_ERR + MOVLW .20 ;SEIT 20SEC ERROR + MOVWF U_ERR_TIME ;SETZEN + BSF PIE2,HLVDIE ;Enable interrupt +;INTIALISIERUNGSPROGAMME + CALL LADESTROM ;LADESTROM EINSTELLEN +;UHR initialisieren + MOVLW TIMER_HB ;Preload TMR1 register + MOVWF TMR1H ; + CLRF TMR1L ;=0 + MOVLW B'00001111' ; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE + MOVWF T1CON ; SET + CLRF TICKS ; 1/8 sec register + CLRF SECS ; Initialize timekeeping registers + CLRF MINS ; + MOVLW .12 + MOVWF HOURS + MOVLW .1 + MOVWF DAY_OF_WEEK + MOVLW .1 + MOVWF DAYS + MOVLW .8 + MOVWF MONTHS + MOVLW .42 + MOVWF YEARS ;MONTAG 19.7.2010 12:00:00 (JAHR-1968) + CLRF TASTE_ON_TIME + CLRF TASTE_OFF_TIME + CLRF POWER_ON_TIME + BSF PIE1,TMR1IE ;Enable Timer1 interrupt +;AD WANDLER INITIALISIEREN + CLRF AD_KANAL ;BEI 0 BEGINNEN + CLRF ADCON0 ;AD MOUDUL AUS + MOVLW B'00001001' ;VREF=VDD,ANALOG INPUT AN0-AN5 + MOVWF ADCON1 + MOVLW B'00000000' ;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2 + MOVWF ADCON2 +; BSF PIE1,ADIE ;INTERRUPT ENABLE + CLRF U_POWER_IN ;WERT AUF 0 VOLT +; seriell initialisieren + CLRF SPBRGH + MOVLW .16 + MOVWF SPBRG ;BAUDE RATE = 115K + MOVLW B'00000100' ;TX AUS, ASYNC HIGH SPEED + MOVWF TXSTA + MOVLW B'10010000' ;SERIEL EIN,RX EIN, + MOVWF RCSTA + MOVLW B'00001000' ;16BIT BRG, RISING EDGE INTERRUPT + MOVWF BAUDCON ;SETZEN +;EXTERNER SUBROUTINES + CLRF GO_SUB +; interrupts + CLRF INTCON3 ;EXTER INTERRUPT AUS, low priority + MOVLW B'11110000' ;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BPIP Low priority + MOVWF INTCON2 + MOVLW B'11000000' ;global on, PERIPHERAL INT on + MOVWF INTCON +;CLOCK + MOVLW CLK_SLEEP ;GEHT JETZT IN SLEEP MODE + MOVWF OSCCON +;------------------------------------------------------------------------- +;---------------------------- MAIN LOOP ------------------------------------------------- +;------------------------------------------------------------------------- +MAIN + MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? + CPFSEQ GO_SUB ;SKIP WENN JA + BRA WARTEN ;SONST WARTEN + CALL MAIN2,1 ;REGISTER SICHERN UND STARTEN +WARTEN + BTFSC TRISD,RD0 ;SKIP IF POWER ON + SLEEP ;SLEPP BIS ZUM NÄCHSTEN INTERRUPT + BRA MAIN +MAIN2 + CALL EXTERN_SUBROUTINES ;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONST UNGÜLTIG + RETURN 1 ;RETURN MIT REGISTER ZURÜCK +;**********************************************************************************************""""""""""""" +;--------------------------- subroutines ------------------------------------------------- +;**********************************************************************************************""""""""""""" +;POWER ON/OFF +POWER_EIN +;CLOCK + MOVLW CLK_ACTIV + MOVWF OSCCON + + BCF TRISA,RA7 ;CLOCK EINSCHALTEN + BCF TRISD,RD7 ;#RSTI AKTIVIEREN = LOW + BCF TRISB,RB4 ;PIC_INT AKTIVIEREN + BCF TRISD,RD0 ;POWER ON + BRA LS_ON_POWER ;LADESTROM EINSTELLEN +POWER_AUS +;CLOCK + MOVLW CLK_SLEEP + MOVWF OSCCON + + BSF TRISD,RD0 ;POWER OFF + BSF TRISD,RD7 ;#RSTI DEAKTIVIEREN + BSF TRISB,RB4 ;PIC INT DEAKTIVIEREN + BSF TRISA,RA7 ;CLOCK DEAKTIVIEREN + CLRF POWER_ON_TIME ;RÜCKSETZEN + BRA LS_OFF_POWER ;LADESTROM EINSTELLEN +;LADESTROM EINSTELLEN ---------------------------- +LADESTROM + BTFSC TRISD,RD0 ; ONPOWER? + BRA LS_OFF_POWER ; NEIN-> +LS_ON_POWER ;GROSSER LADESTROM 5A + BCF TRISA,RA4 ;10K ON + RETURN +LS_OFF_POWER ;KLEINER LADESTROM_MIN 1.85A + BSF TRISA,RA4 ;10K OFF + RETURN +;--------------------------------------------------- +;SERIELL AUS/EIN +SERIAL_OFF + BCF TXSTA,TXEN ;TX AUS + BCF PIE1,RCIE ;DISABLE RX interrupt + BCF PIR1,RCIF ;CLEAR RX interrupt + BCF PIE1,TXIE ;DISABLE TX interrupt + BCF PIR1,TXIF ;CLEAR TX interrupt + RETURN +SERIAL_ON + BTFSC TXSTA,TXEN ;SCHON EIN? + RETURN ;JA-> + BSF TXSTA,TXEN ;TX EIN + MOVLW SYNC1 + MOVWF RX_STATUS ;AUF SYNC WARTEN + CLRF TX_STATUS + MOVFF RCREG,RX_B ;RCREG LEEREN + MOVFF RCREG,RX_B ;RCREG LEEREN + BCF PIR1,TXIF ;CLEAR TX interrupt + BCF PIR1,RCIF ;INTERRUPT RX FLAG LÖSCHEN + BSF PIE1,RCIE ;ENABLE RX interrupt + NOP + RETURN +;--------------------------------------------------------------------- +; TASTENDRUCK +TASTE + BTFSS PORTD,RD1 ;TASTE GEDRÜCKT? + BRA TG_JA ;->JA +;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN + CLRF TASTE_ON_TIME ;RÜCKSETZEN + + MOVLW TIME_MAX ;MAX + CPFSGT TASTE_OFF_TIME ;LÄNGER? + INCF TASTE_OFF_TIME ;NEIN ERHÖHEN + + MOVLW RESET_OFF_TIME ;2SEC + CPFSGT POWER_ON_TIME ;LÄNGER? + RETURN ;NEIN-> +;RESET AUFHEBEN + BSF TRISD,RD7 ;JA -> #RSTI DEAKTIVIEREN =HIGH + CALL SERIAL_ON ;SERIELL EINSCHALTEN + RETURN +;TASTE GEDRÜCKT +TG_JA + MOVLW OFF_TIME+1 + CPFSLT TASTE_ON_TIME ;KÜRZER ALS ONTIME+1 + RETURN ;NEIN->FERTIG + BTFSC TRISD,RD0 ;ONPOWER? + BRA TG_OFF_POWER ;NEIN-> +TG_ON_POWER + MOVLW SEND_RTC_TIME ;ZEIT FÜR RTC REQ FROM MCF HOLEN? + CPFSEQ TASTE_ON_TIME ;TEST + BRA TG_ON_POWER2 ;NEIN-> +SEND_RTC_REG + MOVLW REQ_RTCD_FROM_MCF + MOVWF TXREG ;SENDEN + BRA TG_END; +TG_ON_POWER2 + MOVLW RESET_ON_TIME ; + CPFSLT TASTE_ON_TIME ;KÜRZER? + BRA RESETEN +TG_ON_POWER3 + MOVLW OFF_TIME + CPFSLT TASTE_ON_TIME ;KÜRZER ON/OFF TIME? + CALL POWER_AUS ;NEIN->POWER OFF + BRA TG_END +TG_OFF_POWER + MOVLW ON_TIME + CPFSLT TASTE_ON_TIME ;KÜRZER ALS ON/OFF TIME? + CALL POWER_EIN ;NEIN->POWER ON +TG_END + CLRF TASTE_OFF_TIME ;RÜCKSETZEN + INCF TASTE_ON_TIME ;ERHÖHEN + RETURN +RESETEN + BCF TRISD,RD7 ;NEIN-> #RSTI AKTIVIEREN =LOW -->>>RESET + CALL SERIAL_OFF ;SERIELL DEAKTIVIEREN + BRA TG_ON_POWER3 +;**********************************************************************************************""""""""""""" +;----------------------------------------- INTERRUPTS +;**********************************************************************************************""""""""""""" +; SERIELL INTERRUPTS +;**********************************************************************************************""""""""""""" +;TX +TX_ISR ;TRANSMIT + MOVLW RTCD_FROM_PIC ;RTC DATEN SENDEN? + CPFSEQ TX_STATUS ;SKIP JA + BRA TX_ISR1 ;NEIN-> + MOVFF POSTINC0,TXREG ;BYT SENDEN + MOVLW 0x3F ;SCHON LETZTES BYTS? + CPFSGT FSR0L ;SKIP WENN FERTIG + RETFIE ;NEIN WEITERE SENDEN +TX_ISR_FERTIG + CLRF TX_STATUS + BCF PIE1,TXIE ;SONST DISABLE interrupt + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + RETFIE +TX_ISR1 + MOVLW READ_BLOCK ;READ BLOCK? + CPFSEQ TX_STATUS ;SKIP JA + BRA TX_ISR2 ;NEIN-> + MOVFF POSTINC0,TXREG ;BYT SENDEN + MOVLW 0xC3 ;SCHON LETZTES BYTS? + CPFSGT FSR0L ;SKIP WENN FERTIG + RETFIE ;NEIN WEITERE SENDEN +TX_ISR2 + BRA TX_ISR_FERTIG +;**********************************************************************************************""""""""""""" +;RX +RX_ISR ; BYT RECEIVED + MOVFF RCREG,RX_B ; BYT HOLEN +; MOVFF RX_B,TXREG ; ECHO + MOVLW SYNC4 ;IM SYNC STATUS? + CPFSLT RX_STATUS ;SKIP WENN NEIN + BRA RX_SYNC_START ;JA -> ZUERST SYNC EMPFANGEN +;--------------- + MOVLW RTCD_FROM_MCF ; DATEN VOM MCF CODE 0x82? + CPFSEQ RX_STATUS ; WENN JA-> SKIP + BRA RX_ISR1 ; NEIN-> +;64 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x3F ;64 BYT ÜBERTRAGEN? + CPFSLT FSR1L ;NEIN ->SKIP + CLRF RX_STATUS ;JA FERTIG + RETFIE +;------------------------------------------------------------------------------------- +RX_ISR1 + CPFSEQ RX_B ;BLOCK HEADER 0X82? + BRA RX_ISR2 ;NEIN-> + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,.0 ;BYT COUNTER AUF O + RETFIE +RX_ISR2 + MOVLW REQ_RTCD_FROM_PIC ;DATEN SENDEN? + CPFSEQ RX_B ;SKIP WENN JA + BRA RX_ISR3 ;SONST NEXT +;BLOCK HEADER UND 64 BYT SENDEN ----------------------------------------- + LFSR 0,.0 + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + BSF PIE1,TXIE ;Enable interrupt + MOVLW RTCD_FROM_PIC + MOVWF TX_STATUS ;STATUS SETZEN + MOVWF TXREG ;BLOCK HEADER = 0X81 + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR3 + MOVLW EXT_SUB_GO ;EXT SUB FREIGEBEN? + CPFSEQ RX_B + BRA RX_ISR4 ;NEIN-> +;EXT SUBS FREIGEBEN -------------------------------------------------------------- + MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 + MOVWF TBLPTRU + MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 + MOVWF TBLPTRH + MOVLW (EXTERN_INT_ADR & 0x0000FF) + MOVWF TBLPTRL ;ADRESSE SETZEN + TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) + MOVFF TABLAT,GO_INT ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK + MOVLW (EXTERN_SUB_ADR & 0xFF0000)>>16 + MOVWF TBLPTRU + MOVLW (EXTERN_SUB_ADR & 0x00FF00)>>8 + MOVWF TBLPTRH + MOVLW (EXTERN_SUB_ADR & 0x0000FF) + MOVWF TBLPTRL ;ADRESSE SETZEN + TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) + MOVFF TABLAT,GO_SUB ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR4 + MOVLW EXT_SUB_STOP ;EXT SUB STOPPEN? + CPFSEQ RX_B + BRA RX_ISR5 ;NEIN-> +;EXT SUBS STOPPEN -------------------------------------------------------------- + CLRF GO_INT ;STOPPEN + CLRF GO_SUB ;STOPPEN + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR5 + MOVLW REQ_BLOCK ;REQ BLOCK? + CPFSEQ RX_B + BRA RX_ISR6 ;NEIN-> +;REQ BLOCK ---------------------------------------------------------------- + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,TX_BUFFER ;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN + RETFIE +RX_ISR6 + CPFSEQ RX_STATUS ;REQ BLOCK ADRESSE EMPFANGFEN? + BRA RX_ISR7 ;NEIN-> +;3 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x82 ;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 + CPFSLT FSR1L ;NEIN ->SKIP + BRA RX_RB3BOK + RETFIE +RX_RB3BOK + LFSR 1,TX_BUFFER ;BYT RX COUNTER AUF TX_BUFFER + MOVFF POSTINC1,TBLPTRU ;ADRESSE EINTRAGEN + MOVFF POSTINC1,TBLPTRH + MOVFF POSTINC1,TBLPTRL + MOVLW 0xC2 ;67 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 +RX_RB3B2 + TBLRD *+ ;LESEN UND NEXT + MOVFF TABLAT,POSTINC1 ;UND EINTRAGEN + CPFSEQ FSR1L ;WENN FERTIG ->SKIP + BRA RX_RB3B2 ;SONST LOOP +;BLOCK HEADER 3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN ----------------------------------------- + LFSR 0,TX_BUFFER ;TX COUNTER AUF TX_BUFFER + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + BSF PIE1,TXIE ;Enable interrupt + MOVLW READ_BLOCK ;CODE HEADER 0xA1 + MOVWF TX_STATUS ;STATUS SETZEN + MOVWF TXREG ;BLOCK HEADER = 0XA1 + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR7 + MOVLW WRITE_BLOCK ;WRITE BLOCK 0xA2 BYT EMPFANGEN? + CPFSEQ RX_STATUS ;WENN JA-> SKIP + BRA RX_ISR8 ;NEIN-> +;WRITE BLOCK ---------------------------------------------------------------------------- +;67 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x42 ;67 BYT ÜBERTRAGEN? + CPFSLT FSR1L ;WENN FERTIG ->SKIP + RETFIE +; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH + LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER + MOVFF POSTINC1,TBLPTRU ;TABLE POINTER SETZEN + MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 + CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT + BRA NO_PROG ;JA-> + MOVFF POSTINC1,TBLPTRH ;TABLE POINTER SETZEN + MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 + CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT + BRA NO_PROG ;JA-> + MOVFF POSTINC1,TBLPTRL ;TABLE POINTER SETZEN +;EREASE BLOCK + BSF EECON1,EEPGD ; point to Flash program memory + BCF EECON1,CFGS ; access Flash program memory + BSF EECON1,WREN ; enable write to memory + BSF EECON1,FREE ; enable Row Erase operation + MOVLW 55h + MOVWF EECON2 ; write 55h + MOVLW 0AAh ; write 0AAh + MOVWF EECON2 + BSF EECON1,WR ; start erase (CPU stall) + MOVLW 0x42 ;67 BYT +WRITE_WORD_TO_HREGS + MOVFF POSTINC1,TABLAT ; get byte of buffer data + TBLWT+* ; write data, perform a short write to internal TBLWT holding register. + CPFSLT FSR1L ;SCHON BEI 67 BYTES? + BRA WRITE_WORD_TO_HREGS ;NEIN->LOOP +PROGRAM_MEMORY + BSF EECON1,EEPGD ; point to Flash program memory + BCF EECON1,CFGS ; access Flash program memory + BSF EECON1,WREN ; enable write to memory + MOVLW 55h + MOVWF EECON2 ; write 55h + MOVLW 0AAh + MOVWF EECON2 ; write 0AAh + BSF EECON1,WR ; start program (CPU stall) + BCF EECON1,WREN ; disable write to memory +NO_PROG + CLRF RX_STATUS ;AUF NORMLA SCHALTEN + RETFIE ;UND FERTIG +;WRITE BLOCK SETZEN? +RX_ISR8 + CPFSEQ RX_B ;BLOCK HEADER COMMANDOE 0XA2? + BRA RX_ISR9 ;NEIN-> + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER + RETFIE +;------------------------------------------------------------------------------------- +RX_ISR9 + CLRF RX_STATUS + RETFIE +;------------------------------------------------------------------------------------- +;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ---------------------------------------------------- +;------------------------------------------------------------------------------------- +RX_SYNC_START + MOVLW SYNC1 + CPFSEQ RX_STATUS + BRA RX_SYNC2 + MOVLW SYNC1_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC2 + MOVWF RX_STATUS + RETFIE +NON_SYNC + MOVLW SYNC1 + MOVWF RX_STATUS + RETFIE +RX_SYNC2 ;TEST AUF SYNC UND DATA 2 + MOVLW SYNC2 + CPFSEQ RX_STATUS + BRA RX_SYNC3 ;NICHT SYNC 2 + MOVLW SYNC2_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC3 + MOVWF RX_STATUS + RETFIE +RX_SYNC3 ;TEST AUF SYNC UND DATA 3 + MOVLW SYNC3 + CPFSEQ RX_STATUS + BRA RX_SYNC4 ;NICHT SYNC 3 + MOVLW SYNC3_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC4 + MOVWF RX_STATUS + RETFIE +RX_SYNC4 ;TEST AUF SYNC UND DATA 4 + MOVLW SYNC4 + CPFSEQ RX_STATUS + BRA NON_SYNC ;WIEDER VON VORN + MOVLW SYNC4_DATA + CPFSEQ RX_B ;SKIP OK + BRA NON_SYNC ;NICHT SYNC4 DATA +RX_WAIT1 + BTFSS TXSTA,TRMT + BRA RX_WAIT1 + MOVLW 'O' ;SENDE OK! + MOVWF TXREG; +RX_WAIT2 + BTFSS TXSTA,TRMT + BRA RX_WAIT2 + MOVLW 'K' ;SENDE OK! + MOVWF TXREG; +RX_WAIT3 + BTFSS TXSTA,TRMT + BRA RX_WAIT3 + MOVLW '!' + MOVWF TXREG; + CLRF RX_STATUS ;OK START NORMAL + RETFIE +;**********************************************************************************************""""""""""""" +;SPANNUNGSÜBERWACHUNGS INTERRUPT +HLVD_ISR + BTFSS U_ERR,1 ;WARTEN AUF GELADEN? + BRA HLVD_LE ;NEIN UNTERSPANNUNG DETEKT-> + BCF U_ERR,0 ;SPANNUNGSFEHLER AUS + BCF U_ERR,1 ;WARTEN AUF GELADEN=AUS + MOVLW U_ERR_PW_AUS+2 ;POWER AUS ÜBERSPRINGEN + MOVWF U_ERR_TIME ;ZEIT SETZEN + MOVLW B'00010111' ;INT WENN UNTER 3.12V + MOVWF HLVDCON +WAIT_LVDOK: + BTFSS HLVDCON,IVRST ;ABWARTEN BIS AENDERUNG AKTIV + BRA WAIT_LVDOK + BCF PIR2,HLVDIF ;INTERRUPT FLAG LÖSCHEN + RETFIE +HLVD_LE ;UNTERSPANNUNG + BSF U_ERR,0 ;ERROR SETZEN + BSF U_ERR,1 ;WARTEN AUF GELADEN SETZEN + CLRF U_ERR_TIME ;RÜCKSETZEN +;MESSAGE AN PROCESSOR + MOVLW U_MIN_TO_MCF + MOVWF TXREG ;SENDEN + + MOVLW B'10011010' ;INT WENN ÜBER 3.7V + MOVWF HLVDCON + BRA WAIT_LVDOK +;**********************************************************************************************""""""""""""" +;A/D INTERRUPT +AD_ISR + BCF PIR1,ADIF ;CLEAR INTERRUPT PENDIG + RETFIE ;RETURN +;************************************************************************************************************* +; uhr interrupt ALLE 1/8 SEC +RTC_ISR +;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN + MOVLW TIMER_HB ;WIEDER AUF STARTWERT + MOVWF TMR1H ;SETZEN + BCF PIR1,TMR1IF ;INTERRUPT FLAG LÖSCHEN + BSF PORTB,RB4 ;PIC INT HIGH -------- + BSF TRISE,RE0 ;LED=OFF + BCF PORTB,RB4 ;PIC INT = LOW + BTFSC TRISD,RD0 ;POWER OFF? + BRA POWER_OFF_I ;JA-> +; POWER IS ON: +; BLINKEN 4X/SEC WENN RESET + BTFSC TRISD,RD7 ;RESET AKTIV? + BRA PINGS ;NEIN-> + BTFSC TICKS,0 ;UNGERADE TICKS? + BCF TRISE,RE0 ;NEIN->LED=ON + BRA PINGS +POWER_OFF_I + MOVLW .3 + ANDWF SECS,0 ;4 SEKUNDEN AUSMASKIEREN + BNZ PINGS ;NICHT MODULO4 -> + MOVLW .7 + CPFSEQ TICKS ;7. TICK? + BRA POWER_OFF_I2 ;NEIN-> + BCF TRISE,RE0 ;JA->LED=ON +POWER_OFF_I2 + MOVLW .30 ; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER? + CPFSLT U_ERR_TIME + BRA PINGS ;NEIN-> + MOVLW .5 + CPFSEQ TICKS ;5. TICK? + BRA PINGS ;NEIN-> + BCF TRISE,RE0 ;JA->LED=ON +PINGS + CALL TASTE ;UP TASTE +; TASTE LOSGELASSEN? + MOVLW RESET_OFF_TIME + CPFSGT TASTE_OFF_TIME ;TASTE LÄNGER ALS 2 SEC LOSGELASSEN? + BRA PINGW ;NEIN-> + BSF TRISD,RD7 ;JA-> #RSTI INAKTIV =HIGH + BTFSS TRISD,RD0 ;POWER ON? + CALL SERIAL_ON ;ja->SERIELL EINSCHALTEN +;--TICKS=125MS +PINGW + INCF TICKS ;inc ticks + BTFSS TRISD,RD0 ;POWER ON? + BRA PINGS2 ;JA-> + MOVLW 20 + CPFSLT U_POWER_IN ;LADEGERÄT ANGESCHLOSSEN? + BRA PINGS2 ;->JA LED HELLER + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSLT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + BSF TRISE,RE0 ;JA -> LED OFF +PINGS2 + MOVLW .7 ; 7? + CPFSGT TICKS + RETFIE ; NEIN ->RETURN +SEKUNDEN +;led blinken POWER ON----------------------------------------- + BTFSS TRISD,RD0 ;POWER ON? + BCF TRISE,RE0 ;JA -> LED_ON +;TIMER U_ERR ERHÖHEN + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + INCF U_ERR_TIME ;NEIN ERHÖHEN +;SPANNUNGSFEHLER BEARBEITEN ---------------------------------------- + MOVLW U_ERR_PW_AUS ;POWER AUS ZEIT? + CPFSEQ U_ERR_TIME ; + BRA SEK_NPA ;NEIN + CALL POWER_AUS ;JA AUSSCHALTEN +;-------------------------------------------------------- +SEK_NPA +;SPANNUNG POWER IN MESSEN + MOVLW B'00000001' ;KANAL 0, AD ON + MOVWF ADCON0 ; + BSF ADCON0,1 ;GO +SEK_2 + BTFSC ADCON0,1 ;FERTIG? + BRA SEK_2 ;NEIN + MOVFF ADRESH,U_POWER_IN ;OK WERT EINTRAGEN + +;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1 + BTFSC TRISD,RD0 ;POWER ON? + BRA SEK_4 ;NEIN NICHT MESSEN + + MOVLW B'00001101' ;KANAL 3, AD ON + MOVWF ADCON0 ; + BSF ADCON0,1 ;GO +SEK_3 + BTFSC ADCON0,1 ;FERTIG? + BRA SEK_3 ;NEIN + MOVLW .200 ;UNTER 3.2V -> WENN WERT ÜBER 78% + CPFSLT ADRESH ;JA -> + BRA SEK_4 ;SONST WEITER +;TIMER U_ERR ERHÖHEN + BTFSS U_ERR,0 ;SPANNUNGSERROR? + BRA SEK_4 ;NEIN + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + DECF U_ERR_TIME ;NEIN -> -1 +;------------------------------------------------------------- +SEK_4 + CLRF TICKS + INCF SECS ; Increment seconds + MOVLW .59 ; 60 seconds elapsed? + CPFSGT SECS + RETFIE ;RETURN +MINUTEN + CLRF SECS ; Clear seconds + INCF MINS ; Increment minutes + MOVLW .59 ; 60 minutes elapsed? + CPFSGT MINS + RETFIE ;RETURN +STUNDEN + CLRF MINS ; clear minutes + INCF HOURS ; Increment hours + MOVLW .23 ; 24 hours elapsed? + CPFSGT HOURS + RETFIE ;RETURN +TAGE_UND_TAG_DER_WOCHE + CLRF HOURS ; Reset hours + MOVLW .7 + CPFSLT DAY_OF_WEEK + CLRF DAY_OF_WEEK + INCF DAY_OF_WEEK + INCF DAYS + MOVLW .28 + CPFSGT DAYS + RETFIE ;RETURN +MEHR_ALS_28_TAGE + MOVLW .2 + CPFSEQ MONTHS ;FEB? + BRA NOT_FEB ;NEIN-> +FEB + MOVLW .3 + ANDWF YEARS,0 ;SCHALTJAHR + BNZ NEXT_MONTH ;NEIN-> +SCHALTJAHR + MOVLW .29 + CPFSGT DAYS + RETFIE ;RETURN +NEXT_MONTH + MOVLW .1 + MOVWF DAYS + INCF MONTHS + MOVLW 12 + CPFSGT MONTHS + RETFIE ;RETURN +YEAR + MOVLW .1 + MOVWF MONTHS + INCF YEARS + RETFIE ;RETURN +NOT_FEB + MOVLW .30 + CPFSGT DAYS + RETFIE +MEHR_ALS_30_TAGE + MOVLW .4 ;APRIL? + CPFSEQ MONTHS ;SKIP + BRA NOT_APRIL + BRA NEXT_MONTH ;APRIL-> +NOT_APRIL + MOVLW .6 ;JUNI? + CPFSEQ MONTHS + BRA NOT_JUNI + BRA NEXT_MONTH ;JUNI-> +NOT_JUNI + MOVLW .9 ;SEPTEMBER? + CPFSEQ MONTHS + BRA NOT_SEP + BRA NEXT_MONTH ;SEPTEMBER-> +NOT_SEP + MOVLW .11 ;NOVEMBER? + CPFSEQ MONTHS ;SKIP + RETFIE ;SIND MONATE MIT 31 TAGEN-> + BRA NEXT_MONTH ;SONST NOVEMBER-> +;**********************************************************************************************""""""""""""" +; ENDE MAIN +;**********************************************************************************************""""""""""""" +;**********************************************************************************************""""""""""""" +; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN +;**********************************************************************************************""""""""""""" + end diff --git a/MLAB/firebee1/firebee1.cof b/MLAB/firebee1/firebee1.cof new file mode 100644 index 0000000000000000000000000000000000000000..d3b53d4f93c350bd8aa7b64c1e68c9480c001170 GIT binary patch literal 13640 zcmZ|V4SY;@x(D#*c}_&4dOA{6t=iP8s%Vx-Q>#`pNhWV5libOOm(7}x#LI+xk)=d$sN*b!EYS>iOwW_MBYOOM?idCzqRaGTbZ(GX#|1+7G-}K)3n3@0gcb@Y< zXHL$Wb53$h3;Jls>-Gh4M8km55eFkiY{&)+(KKUz&MHQtN9)|aU9q-W&;M`LxK;{nIp?G8EKZ*$1; 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+:10054000086F092B10001E0E07651000040E0863CB +:1005500001D0EFD7060E086301D0EBD7090E086370 +:0C05600001D0E7D70B0E08631000E3D7B2 +:00000001FF diff --git a/MLAB/firebee1/firebee1.lst b/MLAB/firebee1/firebee1.lst new file mode 100644 index 0000000..8b08d7e --- /dev/null +++ b/MLAB/firebee1/firebee1.lst @@ -0,0 +1,1979 @@ +MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 1 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00001 ;********************************************************** + 00002 ;* firebee1 PIC18F4321 MAIN FILE + 00003 ;********************************************************** + 00004 ;* CREATED BY FREDI ASCHWANDEN + 00005 ;* DATE 22.9.2009 + 00006 ;********************************************************** + 00007 list PE=18f4520 ;EXTENDED INSTRUCTION SET + 00008 include "P18f4520.inc" + 00001 LIST + 00002 + 00003 ;========================================================================== + 00004 ; MPASM PIC18F4520 processor include + 00005 ; + 00006 ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved + 00007 ;========================================================================== + 00008 + 01336 LIST + 00009 ;------------------------ Equates --------------------------; + 00010 ;Register addresses + 00011 ;BANK 0 + 00000000 00012 SECS equ 0x00 + 00000001 00013 SECS_ALARM EQU 0x01 + 00000002 00014 MINS equ 0x02 + 00000003 00015 MINS_ALRAM EQU 0x03 + 00000004 00016 HOURS equ 0x04 + 00000005 00017 HOURS_ALARM EQU 0x05 + 00000006 00018 DAY_OF_WEEK EQU 0x06 + 00000007 00019 DAYS EQU 0x07 + 00000008 00020 MONTHS EQU 0x08 + 00000009 00021 YEARS EQU 0x09 ;offset vom 1968 + 0000000A 00022 REGA EQU 0x0A + 0000000B 00023 REGB EQU 0x0B + 0000000C 00024 REGC EQU 0x0C + 0000000D 00025 REGD EQU 0x0D + 0000000E 00026 RTC_RAM EQU 0x0E ; bis 0x3F + 00000040 00027 free equ 0x40 + 00000041 00028 TICKS equ 0x41 ;125MS + 00000042 00029 TASTE_ON_TIME EQU 0x42 + 00000043 00030 TASTE_OFF_TIME EQU 0x43 + 00000044 00031 POWER_ON_TIME EQU 0x44 + 00000045 00032 AD_KANAL EQU 0x45 + 00000046 00033 U_ERR EQU 0x46 ;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WA + RTEN AUF GELADEN + 00000047 00034 U_ERR_TIME EQU 0x47 ;ZEIT SEIT SPANNUNGSFEHLER + 00000048 00035 U_POWER_IN EQU 0x48 ;SPANNUNG POWER IN 1V CA. 6E + 00000049 00036 RX_B EQU 0x49 ;RECEIVED BYT + 0000004A 00037 RX_STATUS EQU 0x4A ;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x8 + 2=EMPFANGE 64BYT FROM RTC + 0000004B 00038 TX_STATUS EQU 0x4B ;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM + RTC + 0000004C 00039 GO_SUB EQU 0x4C ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH + REN + 0000004D 00040 GO_INT EQU 0x4D ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 2 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + REN + 0000004E 00041 EAPIR1 EQU 0x4E ;INTERRUPT ACTIV UND ENABLE + 0000004F 00042 EAPIR2 EQU 0x4F ;INTERRUPT ACTIV UND ENABLE + 00043 ;BANK 1 AB 0x100 + 00000100 00044 RX_BUFFER EQU 0x100 ;0x80 BYT BUFFER BIS 0x17F BANK + 00000180 00045 TX_BUFFER EQU 0x180 ;0X80 BYT BUFFER BIS 0x1FF BANK + 00046 + 00047 ;-------------------------------------------------------------- + 00000002 00048 SEND_RTC_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS + 00000002 00049 RESET_ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS + 00000004 00050 RESET_OFF_TIME EQU .4 ;0.5 SEC (EINHEIT IST EIN TICK = 128MS + 00000014 00051 OFF_TIME EQU .20 ;2.5 SEC (EINHEIT IST EIN TICK = + 128MS + 00000002 00052 ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK + = 128MS + 000000F0 00053 TIMER_HB EQU .240 ;256- (32768Hz PRO 1/8SEC = 4096TICKS/25 + 6) => 256-16=240 (resp 256-16/4 (wenn osco) = 252) + 000000A0 00054 TIME_MAX EQU .160 ;MAXIMALTIME + 00000005 00055 U_ERR_PW_AUS EQU .5 ;5 SEC + 00056 ;SERIEL + 000000FF 00057 SYNC1 EQU 0FFh + 00000041 00058 SYNC1_DATA EQU 'A'; + 000000FE 00059 SYNC2 EQU 0FEh + 00000043 00060 SYNC2_DATA EQU 'C'; + 000000FD 00061 SYNC3 EQU 0FDh + 00000050 00062 SYNC3_DATA EQU 'P'; + 000000FC 00063 SYNC4 EQU 0FCh + 00000046 00064 SYNC4_DATA EQU 'F'; + 00000001 00065 REQ_RTCD_FROM_PIC EQU 01h ;RTC AND NVRAM DATEN VOM PIC ANFORDERN + 00000081 00066 RTCD_FROM_PIC EQU 81h ;RTC AND NVRAM DATEN HEADER UND STATUS + 00000002 00067 REQ_RTCD_FROM_MCF EQU 02h ;RTC AND NVRAM DATEN VOM MCF ANFORDERN + 00000082 00068 RTCD_FROM_MCF EQU 82h ;RTC AND NVRAM DATEN HEADER UND STATUS + 00000003 00069 U_MIN_TO_MCF EQU 03h ;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR + 00000004 00070 EXT_SUB_GO EQU 04h ;SERIELL CODE UM SUBROUTINEN/INT + ERRUPTS ZU AKTIVIEREN + 00000005 00071 EXT_SUB_STOP EQU 05h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS + ZU STOPPEN + 00000012 00072 CLK_SLEEP EQU B'00010010' ;125kHz intern, SLEEP MODE + 00000072 00073 CLK_ACTIV EQU B'01110010' ;inTernal CLK=8MHz, SLEEP MODE, + SLEEP MODE + 000000FB 00074 EXT_CODE EQU 0xFB ;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS + AUSFÜHREN (FireBee!) + 00002000 00075 EXTERN_INT_ADR EQU 0x2000 ;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS A + USFÜHRBAR + 00002002 00076 EXTERN_INTERRUPTS EQU 0x2002 ;STARTPUNKT EXTERNE SUBROUTINES + 00002010 00077 EXTERN_SUB_ADR EQU 0x2010 ;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES + AUSFÜHRBAR + 00002012 00078 EXTERN_SUBROUTINES EQU 0x2012 ;STARTPUNKT EXTERNE SUBROUTINES + 000000A0 00079 REQ_BLOCK EQU 0xA0 ;BLOCK DATEN LESEN -> CODE UND 3 BYTS AD + RESSE = TOTAL 4 BYTES + 000000A1 00080 READ_BLOCK EQU 0xA1 ;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS + ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES + 000000A2 00081 WRITE_BLOCK EQU 0xA2 ;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 3 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES + 00000022 00082 PRG_OK_PIC EQU 0x22 ;PROGRAMMIERUNG BLOCK FERTIG + 00083 ;**********************************************************************************************""""""""" + """" + 00084 ; Start at the reset vector + 00085 Reset_Vector code 0x000 +000000 D??? 00086 BRA KALT_START + 00087 ;-------------------------------------------------------------- + 00088 HIGH_INT_VEC code 0x0008 +000008 EF0C F000 00089 GOTO 0x18 + 00090 + 00091 LOW_INT_VEC code 0x0018 +000018 00092 INT_HANDLER +000018 6AE0 00093 CLRF BSR ;IMMER ACCESS BANK + 00094 ;SETZEN GRUPPE 1 +00001A CF9D F04E 00095 MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN +00001E 509E 00096 MOVF PIR1,0 ;MASKE +000020 174E 00097 ANDWF EAPIR1 ;ACTIVE SETZEN +000022 B14E 00098 BTFSC EAPIR1,TMR1IF ;uhr interrupt? +000024 D??? 00099 BRA RTC_ISR ;ja-> +000026 BD4E 00100 BTFSC EAPIR1,ADIF ;AD INTERRUTP? +000028 D??? 00101 BRA AD_ISR ;JA-> +00002A B94E 00102 BTFSC EAPIR1,TXIF ;seriell TX? +00002C D??? 00103 BRA TX_ISR ;JA-> +00002E BB4E 00104 BTFSC EAPIR1,RCIF ;seriell RX? +000030 D??? 00105 BRA RX_ISR ;JA-> + 00106 + 00107 ;SETZEN GRUPPE 2 +000032 CFA0 F04F 00108 MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN +000036 50A1 00109 MOVF PIR2,0 ;MASKE +000038 174F 00110 ANDWF EAPIR2 ;ACTIVE SETZEN + 00111 +00003A B54F 00112 BTFSC EAPIR2,HLVDIF ;UNDER/OVERVOLTAGE DETECT +00003C D??? 00113 BRA HLVD_ISR ;JA-> +00003E 0010 00114 RETFIE + 00115 + 00116 ;TESTEN UND SETZEN GRUPPE 1 +000040 CF9D F04E 00117 MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN +000044 509E 00118 MOVF PIR1,0 ;MASKE +000046 174E 00119 ANDWF EAPIR1 ;ACTIVE SETZEN +000048 674E 00120 TSTFSZ EAPIR1 +00004A D??? 00121 BRA INT_HANDLER + 00122 ;TESTEN UND SETZEN GRUPPE 2 +00004C CFA0 F04F 00123 MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN +000050 50A1 00124 MOVF PIR2,0 ;MASKE +000052 174F 00125 ANDWF EAPIR2 ;ACTIVE SETZEN +000054 674F 00126 TSTFSZ EAPIR2 +000056 D??? 00127 BRA INT_HANDLER + 00128 +000058 0EFB 00129 MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? +00005A 634D 00130 CPFSEQ GO_INT ;SKIP WENN JA +00005C 0010 00131 RETFIE +00005E EF01 F010 00132 GOTO EXTERN_INTERRUPTS ;REGISTER SICHERN UND STARTEN + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 4 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00133 ;**********************************************************************************************""""""""" + """" + 00134 ; Start application beyond vector area + 00135 CODE 0x0100 +000100 00136 KALT_START + 00137 ;RESET MODE +000100 6AE0 00138 CLRF BSR ;BANK 0 + 00139 ;ALLE INT AUS UND RÜCKSETZEN +000102 6AF2 00140 CLRF INTCON ;alle INTERRUPT AUS +000104 6AD0 00141 CLRF RCON ;INT PRIORITY AUS +000106 6A9D 00142 CLRF PIE1 ;MASK DISABLE +000108 6AA0 00143 CLRF PIE2 +00010A 6A9E 00144 CLRF PIR1 ;INT ACT AUS +00010C 6AA1 00145 CLRF PIR2 +00010E 6A9F 00146 CLRF IPR1 ;LOW PRIORITY +000110 6AA2 00147 CLRF IPR2 + 00148 ; clock + 00149 ; MOVLW B'01000000' ;32MHZ + 00150 ; MOVWF OSCTUNE +000112 6A9B 00151 CLRF OSCTUNE + 00152 ;CLOCK +000114 0E72 00153 MOVLW CLK_ACTIV +000116 6ED3 00154 MOVWF OSCCON + 00155 ; div init + 00156 ;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3 + /2 **1:1V25 **0:POWER_IN/11 +000118 6A80 00157 CLRF PORTA ;#master(7)=0, REST=0 +00011A 0EFF 00158 MOVLW B'11111111' ;DIRECTION: alles auf Input +00011C 6E92 00159 MOVWF TRISA + 00160 ;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PO + RT PIN6 **0: GAME PORT PIN5 +00011E 6A81 00161 CLRF PORTB ;ALLES AUF 0 +000120 6E93 00162 MOVWF TRISB + 00163 ;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN + 13 **1+0: OCS 32K768Hz +000122 6A82 00164 CLRF PORTC +000124 6E94 00165 MOVWF TRISC + 00166 ;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1: + TASTER **0:POWER ON/OFF (0=ON) + 00167 ; SET TASTE UND POWER +000126 6A83 00168 CLRF PORTD ;ALLES AUF 0 +000128 6E95 00169 MOVWF TRISD ;ALLES AUF INPUT + 00170 ;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON) +00012A 0E01 00171 MOVLW B'00000001' ;LED OFF +00012C 6A84 00172 CLRF PORTE ;ALLES AUF 0 +00012E 6E96 00173 MOVWF TRISE ;ALLES AUF INPUT + 00174 ;-------------------------- + 00175 ; set OVERvoltage detekt +000130 0E9B 00176 MOVLW B'10011011' ;INT WENN ÜBER 3.9V +000132 6ED2 00177 MOVWF HLVDCON +000134 0E03 00178 MOVLW B'00000011' ;ERRORS ON, WAIT AUF LADEN +000136 6F46 00179 MOVWF U_ERR +000138 0E14 00180 MOVLW .20 ;SEIT 20SEC ERROR + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 5 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00013A 6F47 00181 MOVWF U_ERR_TIME ;SETZEN +00013C 84A0 00182 BSF PIE2,HLVDIE ;Enable interrupt + 00183 ;INTIALISIERUNGSPROGAMME +00013E EC?? F??? 00184 CALL LADESTROM ;LADESTROM EINSTELLEN + 00185 ;UHR initialisieren +000142 0EF0 00186 MOVLW TIMER_HB ;Preload TMR1 register +000144 6ECF 00187 MOVWF TMR1H ; +000146 6ACE 00188 CLRF TMR1L ;=0 +000148 0E0F 00189 MOVLW B'00001111' ; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE +00014A 6ECD 00190 MOVWF T1CON ; SET +00014C 6B41 00191 CLRF TICKS ; 1/8 sec register +00014E 6B00 00192 CLRF SECS ; Initialize timekeeping registers +000150 6B02 00193 CLRF MINS ; +000152 0E0C 00194 MOVLW .12 +000154 6F04 00195 MOVWF HOURS +000156 0E01 00196 MOVLW .1 +000158 6F06 00197 MOVWF DAY_OF_WEEK +00015A 0E01 00198 MOVLW .1 +00015C 6F07 00199 MOVWF DAYS +00015E 0E08 00200 MOVLW .8 +000160 6F08 00201 MOVWF MONTHS +000162 0E2A 00202 MOVLW .42 +000164 6F09 00203 MOVWF YEARS ;MONTAG 19.7.2010 12:00:00 (JAHR-1968) +000166 6B42 00204 CLRF TASTE_ON_TIME +000168 6B43 00205 CLRF TASTE_OFF_TIME +00016A 6B44 00206 CLRF POWER_ON_TIME +00016C 809D 00207 BSF PIE1,TMR1IE ;Enable Timer1 interrupt + 00208 ;AD WANDLER INITIALISIEREN +00016E 6B45 00209 CLRF AD_KANAL ;BEI 0 BEGINNEN +000170 6AC2 00210 CLRF ADCON0 ;AD MOUDUL AUS +000172 0E09 00211 MOVLW B'00001001' ;VREF=VDD,ANALOG INPUT AN0-AN5 +000174 6EC1 00212 MOVWF ADCON1 +000176 0E00 00213 MOVLW B'00000000' ;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2 +000178 6EC0 00214 MOVWF ADCON2 + 00215 ; BSF PIE1,ADIE ;INTERRUPT ENABLE +00017A 6B48 00216 CLRF U_POWER_IN ;WERT AUF 0 VOLT + 00217 ; seriell initialisieren +00017C 6AB0 00218 CLRF SPBRGH +00017E 0E10 00219 MOVLW .16 +000180 6EAF 00220 MOVWF SPBRG ;BAUDE RATE = 115K +000182 0E04 00221 MOVLW B'00000100' ;TX AUS, ASYNC HIGH SPEED +000184 6EAC 00222 MOVWF TXSTA +000186 0E90 00223 MOVLW B'10010000' ;SERIEL EIN,RX EIN, +000188 6EAB 00224 MOVWF RCSTA +00018A 0E08 00225 MOVLW B'00001000' ;16BIT BRG, RISING EDGE INTERRUPT +00018C 6EB8 00226 MOVWF BAUDCON ;SETZEN + 00227 ;EXTERNER SUBROUTINES +00018E 6B4C 00228 CLRF GO_SUB + 00229 ; interrupts +000190 6AF0 00230 CLRF INTCON3 ;EXTER INTERRUPT AUS, low priority +000192 0EF0 00231 MOVLW B'11110000' ;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BP + IP Low priority +000194 6EF1 00232 MOVWF INTCON2 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 6 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000196 0EC0 00233 MOVLW B'11000000' ;global on, PERIPHERAL INT on +000198 6EF2 00234 MOVWF INTCON + 00235 ;CLOCK +00019A 0E12 00236 MOVLW CLK_SLEEP ;GEHT JETZT IN SLEEP MODE +00019C 6ED3 00237 MOVWF OSCCON + 00238 ;------------------------------------------------------------------------- + 00239 ;---------------------------- MAIN LOOP ------------------------------------------------- + 00240 ;------------------------------------------------------------------------- +00019E 00241 MAIN +00019E 0EFB 00242 MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? +0001A0 634C 00243 CPFSEQ GO_SUB ;SKIP WENN JA +0001A2 D??? 00244 BRA WARTEN ;SONST WARTEN +0001A4 ED00 F000 00245 CALL MAIN2,1 ;REGISTER SICHERN UND STARTEN +0001A8 00246 WARTEN +0001A8 B095 00247 BTFSC TRISD,RD0 ;SKIP IF POWER ON +0001AA 0003 00248 SLEEP ;SLEPP BIS ZUM NÄCHSTEN INTERRUPT +0001AC D??? 00249 BRA MAIN +0001AE 00250 MAIN2 +0001AE EC09 F010 00251 CALL EXTERN_SUBROUTINES ;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONS + T UNGÜLTIG +0001B2 0013 00252 RETURN 1 ;RETURN MIT REGISTER ZURÜCK + 00253 ;**********************************************************************************************""""""""" + """" + 00254 ;--------------------------- subroutines ------------------------------------------------- + 00255 ;**********************************************************************************************""""""""" + """" + 00256 ;POWER ON/OFF +0001B4 00257 POWER_EIN + 00258 ;CLOCK +0001B4 0E72 00259 MOVLW CLK_ACTIV +0001B6 6ED3 00260 MOVWF OSCCON + 00261 +0001B8 9E92 00262 BCF TRISA,RA7 ;CLOCK EINSCHALTEN +0001BA 9E95 00263 BCF TRISD,RD7 ;#RSTI AKTIVIEREN = LOW +0001BC 9893 00264 BCF TRISB,RB4 ;PIC_INT AKTIVIEREN +0001BE 9095 00265 BCF TRISD,RD0 ;POWER ON +0001C0 D??? 00266 BRA LS_ON_POWER ;LADESTROM EINSTELLEN +0001C2 00267 POWER_AUS + 00268 ;CLOCK +0001C2 0E12 00269 MOVLW CLK_SLEEP +0001C4 6ED3 00270 MOVWF OSCCON + 00271 +0001C6 8095 00272 BSF TRISD,RD0 ;POWER OFF +0001C8 8E95 00273 BSF TRISD,RD7 ;#RSTI DEAKTIVIEREN +0001CA 8893 00274 BSF TRISB,RB4 ;PIC INT DEAKTIVIEREN +0001CC 8E92 00275 BSF TRISA,RA7 ;CLOCK DEAKTIVIEREN +0001CE 6B44 00276 CLRF POWER_ON_TIME ;RÜCKSETZEN +0001D0 D??? 00277 BRA LS_OFF_POWER ;LADESTROM EINSTELLEN + 00278 ;LADESTROM EINSTELLEN ---------------------------- +0001D2 00279 LADESTROM +0001D2 B095 00280 BTFSC TRISD,RD0 ; ONPOWER? +0001D4 D??? 00281 BRA LS_OFF_POWER ; NEIN-> +0001D6 00282 LS_ON_POWER ;GROSSER LADESTROM 5A + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 7 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0001D6 9892 00283 BCF TRISA,RA4 ;10K ON +0001D8 0012 00284 RETURN +0001DA 00285 LS_OFF_POWER ;KLEINER LADESTROM_MIN 1.85A +0001DA 8892 00286 BSF TRISA,RA4 ;10K OFF +0001DC 0012 00287 RETURN + 00288 ;--------------------------------------------------- + 00289 ;SERIELL AUS/EIN +0001DE 00290 SERIAL_OFF +0001DE 9AAC 00291 BCF TXSTA,TXEN ;TX AUS +0001E0 9A9D 00292 BCF PIE1,RCIE ;DISABLE RX interrupt +0001E2 9A9E 00293 BCF PIR1,RCIF ;CLEAR RX interrupt +0001E4 989D 00294 BCF PIE1,TXIE ;DISABLE TX interrupt +0001E6 989E 00295 BCF PIR1,TXIF ;CLEAR TX interrupt +0001E8 0012 00296 RETURN +0001EA 00297 SERIAL_ON +0001EA BAAC 00298 BTFSC TXSTA,TXEN ;SCHON EIN? +0001EC 0012 00299 RETURN ;JA-> +0001EE 8AAC 00300 BSF TXSTA,TXEN ;TX EIN +0001F0 0EFF 00301 MOVLW SYNC1 +0001F2 6F4A 00302 MOVWF RX_STATUS ;AUF SYNC WARTEN +0001F4 6B4B 00303 CLRF TX_STATUS +0001F6 CFAE F049 00304 MOVFF RCREG,RX_B ;RCREG LEEREN +0001FA CFAE F049 00305 MOVFF RCREG,RX_B ;RCREG LEEREN +0001FE 989E 00306 BCF PIR1,TXIF ;CLEAR TX interrupt +000200 9A9E 00307 BCF PIR1,RCIF ;INTERRUPT RX FLAG LÖSCHEN +000202 8A9D 00308 BSF PIE1,RCIE ;ENABLE RX interrupt +000204 0000 00309 NOP +000206 0012 00310 RETURN + 00311 ;--------------------------------------------------------------------- + 00312 ; TASTENDRUCK +000208 00313 TASTE +000208 A283 00314 BTFSS PORTD,RD1 ;TASTE GEDRÜCKT? +00020A D??? 00315 BRA TG_JA ;->JA + 00316 ;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN +00020C 6B42 00317 CLRF TASTE_ON_TIME ;RÜCKSETZEN + 00318 +00020E 0EA0 00319 MOVLW TIME_MAX ;MAX +000210 6543 00320 CPFSGT TASTE_OFF_TIME ;LÄNGER? +000212 2B43 00321 INCF TASTE_OFF_TIME ;NEIN ERHÖHEN + 00322 +000214 0E04 00323 MOVLW RESET_OFF_TIME ;2SEC +000216 6544 00324 CPFSGT POWER_ON_TIME ;LÄNGER? +000218 0012 00325 RETURN ;NEIN-> + 00326 ;RESET AUFHEBEN +00021A 8E95 00327 BSF TRISD,RD7 ;JA -> #RSTI DEAKTIVIEREN =HIGH +00021C EC?? F??? 00328 CALL SERIAL_ON ;SERIELL EINSCHALTEN +000220 0012 00329 RETURN + 00330 ;TASTE GEDRÜCKT +000222 00331 TG_JA +000222 0E15 00332 MOVLW OFF_TIME+1 +000224 6142 00333 CPFSLT TASTE_ON_TIME ;KÜRZER ALS ONTIME+1 +000226 0012 00334 RETURN ;NEIN->FERTIG +000228 B095 00335 BTFSC TRISD,RD0 ;ONPOWER? + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 8 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00022A D??? 00336 BRA TG_OFF_POWER ;NEIN-> +00022C 00337 TG_ON_POWER +00022C 0E02 00338 MOVLW SEND_RTC_TIME ;ZEIT FÜR RTC REQ FROM MCF HOLEN? +00022E 6342 00339 CPFSEQ TASTE_ON_TIME ;TEST +000230 D??? 00340 BRA TG_ON_POWER2 ;NEIN-> +000232 00341 SEND_RTC_REG +000232 0E02 00342 MOVLW REQ_RTCD_FROM_MCF +000234 6EAD 00343 MOVWF TXREG ;SENDEN +000236 D??? 00344 BRA TG_END; +000238 00345 TG_ON_POWER2 +000238 0E02 00346 MOVLW RESET_ON_TIME ; +00023A 6142 00347 CPFSLT TASTE_ON_TIME ;KÜRZER? +00023C D??? 00348 BRA RESETEN +00023E 00349 TG_ON_POWER3 +00023E 0E14 00350 MOVLW OFF_TIME +000240 6142 00351 CPFSLT TASTE_ON_TIME ;KÜRZER ON/OFF TIME? +000242 EC?? F??? 00352 CALL POWER_AUS ;NEIN->POWER OFF +000246 D??? 00353 BRA TG_END +000248 00354 TG_OFF_POWER +000248 0E02 00355 MOVLW ON_TIME +00024A 6142 00356 CPFSLT TASTE_ON_TIME ;KÜRZER ALS ON/OFF TIME? +00024C EC?? F??? 00357 CALL POWER_EIN ;NEIN->POWER ON +000250 00358 TG_END +000250 6B43 00359 CLRF TASTE_OFF_TIME ;RÜCKSETZEN +000252 2B42 00360 INCF TASTE_ON_TIME ;ERHÖHEN +000254 0012 00361 RETURN +000256 00362 RESETEN +000256 9E95 00363 BCF TRISD,RD7 ;NEIN-> #RSTI AKTIVIEREN =LOW -->>>RESET +000258 EC?? F??? 00364 CALL SERIAL_OFF ;SERIELL DEAKTIVIEREN +00025C D??? 00365 BRA TG_ON_POWER3 + 00366 ;**********************************************************************************************""""""""" + """" + 00367 ;----------------------------------------- INTERRUPTS + 00368 ;**********************************************************************************************""""""""" + """" + 00369 ; SERIELL INTERRUPTS + 00370 ;**********************************************************************************************""""""""" + """" + 00371 ;TX +00025E 00372 TX_ISR ;TRANSMIT +00025E 0E81 00373 MOVLW RTCD_FROM_PIC ;RTC DATEN SENDEN? +000260 634B 00374 CPFSEQ TX_STATUS ;SKIP JA +000262 D??? 00375 BRA TX_ISR1 ;NEIN-> +000264 CFEE FFAD 00376 MOVFF POSTINC0,TXREG ;BYT SENDEN +000268 0E3F 00377 MOVLW 0x3F ;SCHON LETZTES BYTS? +00026A 64E9 00378 CPFSGT FSR0L ;SKIP WENN FERTIG +00026C 0010 00379 RETFIE ;NEIN WEITERE SENDEN +00026E 00380 TX_ISR_FERTIG +00026E 6B4B 00381 CLRF TX_STATUS +000270 989D 00382 BCF PIE1,TXIE ;SONST DISABLE interrupt +000272 989E 00383 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +000274 0010 00384 RETFIE +000276 00385 TX_ISR1 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 9 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000276 0EA1 00386 MOVLW READ_BLOCK ;READ BLOCK? +000278 634B 00387 CPFSEQ TX_STATUS ;SKIP JA +00027A D??? 00388 BRA TX_ISR2 ;NEIN-> +00027C CFEE FFAD 00389 MOVFF POSTINC0,TXREG ;BYT SENDEN +000280 0EC3 00390 MOVLW 0xC3 ;SCHON LETZTES BYTS? +000282 64E9 00391 CPFSGT FSR0L ;SKIP WENN FERTIG +000284 0010 00392 RETFIE ;NEIN WEITERE SENDEN +000286 00393 TX_ISR2 +000286 D??? 00394 BRA TX_ISR_FERTIG + 00395 ;**********************************************************************************************""""""""" + """" + 00396 ;RX +000288 00397 RX_ISR ; BYT RECEIVED +000288 CFAE F049 00398 MOVFF RCREG,RX_B ; BYT HOLEN + 00399 ; MOVFF RX_B,TXREG ; ECHO +00028C 0EFC 00400 MOVLW SYNC4 ;IM SYNC STATUS? +00028E 614A 00401 CPFSLT RX_STATUS ;SKIP WENN NEIN +000290 D??? 00402 BRA RX_SYNC_START ;JA -> ZUERST SYNC EMPFANGEN + 00403 ;--------------- +000292 0E82 00404 MOVLW RTCD_FROM_MCF ; DATEN VOM MCF CODE 0x82? +000294 634A 00405 CPFSEQ RX_STATUS ; WENN JA-> SKIP +000296 D??? 00406 BRA RX_ISR1 ; NEIN-> + 00407 ;64 BYT EMPFANGEN ------------------------------------- +000298 C049 FFE6 00408 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00029C 0E3F 00409 MOVLW 0x3F ;64 BYT ÜBERTRAGEN? +00029E 60E1 00410 CPFSLT FSR1L ;NEIN ->SKIP +0002A0 6B4A 00411 CLRF RX_STATUS ;JA FERTIG +0002A2 0010 00412 RETFIE + 00413 ;------------------------------------------------------------------------------------- +0002A4 00414 RX_ISR1 +0002A4 6349 00415 CPFSEQ RX_B ;BLOCK HEADER 0X82? +0002A6 D??? 00416 BRA RX_ISR2 ;NEIN-> +0002A8 6F4A 00417 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +0002AA EE10 F000 00418 LFSR 1,.0 ;BYT COUNTER AUF O +0002AE 0010 00419 RETFIE +0002B0 00420 RX_ISR2 +0002B0 0E01 00421 MOVLW REQ_RTCD_FROM_PIC ;DATEN SENDEN? +0002B2 6349 00422 CPFSEQ RX_B ;SKIP WENN JA +0002B4 D??? 00423 BRA RX_ISR3 ;SONST NEXT + 00424 ;BLOCK HEADER UND 64 BYT SENDEN ----------------------------------------- +0002B6 EE00 F000 00425 LFSR 0,.0 +0002BA 989E 00426 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +0002BC 889D 00427 BSF PIE1,TXIE ;Enable interrupt +0002BE 0E81 00428 MOVLW RTCD_FROM_PIC +0002C0 6F4B 00429 MOVWF TX_STATUS ;STATUS SETZEN +0002C2 6EAD 00430 MOVWF TXREG ;BLOCK HEADER = 0X81 +0002C4 6B4A 00431 CLRF RX_STATUS ;STATUS RÜCKSETZEN +0002C6 0010 00432 RETFIE ;UND WEG + 00433 ;------------------------------------------------------------------------------------- +0002C8 00434 RX_ISR3 +0002C8 0E04 00435 MOVLW EXT_SUB_GO ;EXT SUB FREIGEBEN? +0002CA 6349 00436 CPFSEQ RX_B +0002CC D??? 00437 BRA RX_ISR4 ;NEIN-> + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 10 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00438 ;EXT SUBS FREIGEBEN -------------------------------------------------------------- +0002CE 0E00 00439 MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 +0002D0 6EF8 00440 MOVWF TBLPTRU +0002D2 0E20 00441 MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 +0002D4 6EF7 00442 MOVWF TBLPTRH +0002D6 0E00 00443 MOVLW (EXTERN_INT_ADR & 0x0000FF) +0002D8 6EF6 00444 MOVWF TBLPTRL ;ADRESSE SETZEN +0002DA 0008 00445 TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) +0002DC CFF5 F04D 00446 MOVFF TABLAT,GO_INT ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK +0002E0 0E00 00447 MOVLW (EXTERN_SUB_ADR & 0xFF0000)>>16 +0002E2 6EF8 00448 MOVWF TBLPTRU +0002E4 0E20 00449 MOVLW (EXTERN_SUB_ADR & 0x00FF00)>>8 +0002E6 6EF7 00450 MOVWF TBLPTRH +0002E8 0E10 00451 MOVLW (EXTERN_SUB_ADR & 0x0000FF) +0002EA 6EF6 00452 MOVWF TBLPTRL ;ADRESSE SETZEN +0002EC 0008 00453 TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) +0002EE CFF5 F04C 00454 MOVFF TABLAT,GO_SUB ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK +0002F2 6B4A 00455 CLRF RX_STATUS ;STATUS RÜCKSETZEN +0002F4 0010 00456 RETFIE ;UND WEG + 00457 ;------------------------------------------------------------------------------------- +0002F6 00458 RX_ISR4 +0002F6 0E05 00459 MOVLW EXT_SUB_STOP ;EXT SUB STOPPEN? +0002F8 6349 00460 CPFSEQ RX_B +0002FA D??? 00461 BRA RX_ISR5 ;NEIN-> + 00462 ;EXT SUBS STOPPEN -------------------------------------------------------------- +0002FC 6B4D 00463 CLRF GO_INT ;STOPPEN +0002FE 6B4C 00464 CLRF GO_SUB ;STOPPEN +000300 6B4A 00465 CLRF RX_STATUS ;STATUS RÜCKSETZEN +000302 0010 00466 RETFIE ;UND WEG + 00467 ;------------------------------------------------------------------------------------- +000304 00468 RX_ISR5 +000304 0EA0 00469 MOVLW REQ_BLOCK ;REQ BLOCK? +000306 6349 00470 CPFSEQ RX_B +000308 D??? 00471 BRA RX_ISR6 ;NEIN-> + 00472 ;REQ BLOCK ---------------------------------------------------------------- +00030A 6F4A 00473 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +00030C EE11 F080 00474 LFSR 1,TX_BUFFER ;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN +000310 0010 00475 RETFIE +000312 00476 RX_ISR6 +000312 634A 00477 CPFSEQ RX_STATUS ;REQ BLOCK ADRESSE EMPFANGFEN? +000314 D??? 00478 BRA RX_ISR7 ;NEIN-> + 00479 ;3 BYT EMPFANGEN ------------------------------------- +000316 C049 FFE6 00480 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00031A 0E82 00481 MOVLW 0x82 ;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 +00031C 60E1 00482 CPFSLT FSR1L ;NEIN ->SKIP +00031E D??? 00483 BRA RX_RB3BOK +000320 0010 00484 RETFIE +000322 00485 RX_RB3BOK +000322 EE11 F080 00486 LFSR 1,TX_BUFFER ;BYT RX COUNTER AUF TX_BUFFER +000326 CFE6 FFF8 00487 MOVFF POSTINC1,TBLPTRU ;ADRESSE EINTRAGEN +00032A CFE6 FFF7 00488 MOVFF POSTINC1,TBLPTRH +00032E CFE6 FFF6 00489 MOVFF POSTINC1,TBLPTRL +000332 0EC2 00490 MOVLW 0xC2 ;67 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 11 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000334 00491 RX_RB3B2 +000334 0009 00492 TBLRD *+ ;LESEN UND NEXT +000336 CFF5 FFE6 00493 MOVFF TABLAT,POSTINC1 ;UND EINTRAGEN +00033A 62E1 00494 CPFSEQ FSR1L ;WENN FERTIG ->SKIP +00033C D??? 00495 BRA RX_RB3B2 ;SONST LOOP + 00496 ;BLOCK HEADER 3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN ----------------------------------------- +00033E EE01 F080 00497 LFSR 0,TX_BUFFER ;TX COUNTER AUF TX_BUFFER +000342 989E 00498 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +000344 889D 00499 BSF PIE1,TXIE ;Enable interrupt +000346 0EA1 00500 MOVLW READ_BLOCK ;CODE HEADER 0xA1 +000348 6F4B 00501 MOVWF TX_STATUS ;STATUS SETZEN +00034A 6EAD 00502 MOVWF TXREG ;BLOCK HEADER = 0XA1 +00034C 6B4A 00503 CLRF RX_STATUS ;STATUS RÜCKSETZEN +00034E 0010 00504 RETFIE ;UND WEG + 00505 ;------------------------------------------------------------------------------------- +000350 00506 RX_ISR7 +000350 0EA2 00507 MOVLW WRITE_BLOCK ;WRITE BLOCK 0xA2 BYT EMPFANGEN? +000352 634A 00508 CPFSEQ RX_STATUS ;WENN JA-> SKIP +000354 D??? 00509 BRA RX_ISR8 ;NEIN-> + 00510 ;WRITE BLOCK ---------------------------------------------------------------------------- + 00511 ;67 BYT EMPFANGEN ------------------------------------- +000356 C049 FFE6 00512 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00035A 0E42 00513 MOVLW 0x42 ;67 BYT ÜBERTRAGEN? +00035C 60E1 00514 CPFSLT FSR1L ;WENN FERTIG ->SKIP +00035E 0010 00515 RETFIE + 00516 ; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH +000360 EE11 F000 00517 LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER +000364 CFE6 FFF8 00518 MOVFF POSTINC1,TBLPTRU ;TABLE POINTER SETZEN +000368 0E00 00519 MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 +00036A 60F8 00520 CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT +00036C D??? 00521 BRA NO_PROG ;JA-> +00036E CFE6 FFF7 00522 MOVFF POSTINC1,TBLPTRH ;TABLE POINTER SETZEN +000372 0E20 00523 MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 +000374 60F8 00524 CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT +000376 D??? 00525 BRA NO_PROG ;JA-> +000378 CFE6 FFF6 00526 MOVFF POSTINC1,TBLPTRL ;TABLE POINTER SETZEN + 00527 ;EREASE BLOCK +00037C 8EA6 00528 BSF EECON1,EEPGD ; point to Flash program memory +00037E 9CA6 00529 BCF EECON1,CFGS ; access Flash program memory +000380 84A6 00530 BSF EECON1,WREN ; enable write to memory +000382 88A6 00531 BSF EECON1,FREE ; enable Row Erase operation +000384 0E55 00532 MOVLW 55h +000386 6EA7 00533 MOVWF EECON2 ; write 55h +000388 0EAA 00534 MOVLW 0AAh ; write 0AAh +00038A 6EA7 00535 MOVWF EECON2 +00038C 82A6 00536 BSF EECON1,WR ; start erase (CPU stall) +00038E 0E42 00537 MOVLW 0x42 ;67 BYT +000390 00538 WRITE_WORD_TO_HREGS +000390 CFE6 FFF5 00539 MOVFF POSTINC1,TABLAT ; get byte of buffer data +000394 000F 00540 TBLWT+* ; write data, perform a short write to internal + TBLWT holding register. +000396 60E1 00541 CPFSLT FSR1L ;SCHON BEI 67 BYTES? +000398 D??? 00542 BRA WRITE_WORD_TO_HREGS ;NEIN->LOOP + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 12 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00039A 00543 PROGRAM_MEMORY +00039A 8EA6 00544 BSF EECON1,EEPGD ; point to Flash program memory +00039C 9CA6 00545 BCF EECON1,CFGS ; access Flash program memory +00039E 84A6 00546 BSF EECON1,WREN ; enable write to memory +0003A0 0E55 00547 MOVLW 55h +0003A2 6EA7 00548 MOVWF EECON2 ; write 55h +0003A4 0EAA 00549 MOVLW 0AAh +0003A6 6EA7 00550 MOVWF EECON2 ; write 0AAh +0003A8 82A6 00551 BSF EECON1,WR ; start program (CPU stall) +0003AA 94A6 00552 BCF EECON1,WREN ; disable write to memory +0003AC 00553 NO_PROG +0003AC 6B4A 00554 CLRF RX_STATUS ;AUF NORMLA SCHALTEN +0003AE 0010 00555 RETFIE ;UND FERTIG + 00556 ;WRITE BLOCK SETZEN? +0003B0 00557 RX_ISR8 +0003B0 6349 00558 CPFSEQ RX_B ;BLOCK HEADER COMMANDOE 0XA2? +0003B2 D??? 00559 BRA RX_ISR9 ;NEIN-> +0003B4 6F4A 00560 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +0003B6 EE11 F000 00561 LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER +0003BA 0010 00562 RETFIE + 00563 ;------------------------------------------------------------------------------------- +0003BC 00564 RX_ISR9 +0003BC 6B4A 00565 CLRF RX_STATUS +0003BE 0010 00566 RETFIE + 00567 ;------------------------------------------------------------------------------------- + 00568 ;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ---------------------------------------------------- + 00569 ;------------------------------------------------------------------------------------- +0003C0 00570 RX_SYNC_START +0003C0 0EFF 00571 MOVLW SYNC1 +0003C2 634A 00572 CPFSEQ RX_STATUS +0003C4 D??? 00573 BRA RX_SYNC2 +0003C6 0E41 00574 MOVLW SYNC1_DATA +0003C8 6349 00575 CPFSEQ RX_B +0003CA D??? 00576 BRA NON_SYNC +0003CC 0EFE 00577 MOVLW SYNC2 +0003CE 6F4A 00578 MOVWF RX_STATUS +0003D0 0010 00579 RETFIE +0003D2 00580 NON_SYNC +0003D2 0EFF 00581 MOVLW SYNC1 +0003D4 6F4A 00582 MOVWF RX_STATUS +0003D6 0010 00583 RETFIE +0003D8 00584 RX_SYNC2 ;TEST AUF SYNC UND DATA 2 +0003D8 0EFE 00585 MOVLW SYNC2 +0003DA 634A 00586 CPFSEQ RX_STATUS +0003DC D??? 00587 BRA RX_SYNC3 ;NICHT SYNC 2 +0003DE 0E43 00588 MOVLW SYNC2_DATA +0003E0 6349 00589 CPFSEQ RX_B +0003E2 D??? 00590 BRA NON_SYNC +0003E4 0EFD 00591 MOVLW SYNC3 +0003E6 6F4A 00592 MOVWF RX_STATUS +0003E8 0010 00593 RETFIE +0003EA 00594 RX_SYNC3 ;TEST AUF SYNC UND DATA 3 +0003EA 0EFD 00595 MOVLW SYNC3 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 13 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0003EC 634A 00596 CPFSEQ RX_STATUS +0003EE D??? 00597 BRA RX_SYNC4 ;NICHT SYNC 3 +0003F0 0E50 00598 MOVLW SYNC3_DATA +0003F2 6349 00599 CPFSEQ RX_B +0003F4 D??? 00600 BRA NON_SYNC +0003F6 0EFC 00601 MOVLW SYNC4 +0003F8 6F4A 00602 MOVWF RX_STATUS +0003FA 0010 00603 RETFIE +0003FC 00604 RX_SYNC4 ;TEST AUF SYNC UND DATA 4 +0003FC 0EFC 00605 MOVLW SYNC4 +0003FE 634A 00606 CPFSEQ RX_STATUS +000400 D??? 00607 BRA NON_SYNC ;WIEDER VON VORN +000402 0E46 00608 MOVLW SYNC4_DATA +000404 6349 00609 CPFSEQ RX_B ;SKIP OK +000406 D??? 00610 BRA NON_SYNC ;NICHT SYNC4 DATA +000408 00611 RX_WAIT1 +000408 A2AC 00612 BTFSS TXSTA,TRMT +00040A D??? 00613 BRA RX_WAIT1 +00040C 0E4F 00614 MOVLW 'O' ;SENDE OK! +00040E 6EAD 00615 MOVWF TXREG; +000410 00616 RX_WAIT2 +000410 A2AC 00617 BTFSS TXSTA,TRMT +000412 D??? 00618 BRA RX_WAIT2 +000414 0E4B 00619 MOVLW 'K' ;SENDE OK! +000416 6EAD 00620 MOVWF TXREG; +000418 00621 RX_WAIT3 +000418 A2AC 00622 BTFSS TXSTA,TRMT +00041A D??? 00623 BRA RX_WAIT3 +00041C 0E21 00624 MOVLW '!' +00041E 6EAD 00625 MOVWF TXREG; +000420 6B4A 00626 CLRF RX_STATUS ;OK START NORMAL +000422 0010 00627 RETFIE + 00628 ;**********************************************************************************************""""""""" + """" + 00629 ;SPANNUNGSÜBERWACHUNGS INTERRUPT +000424 00630 HLVD_ISR +000424 A346 00631 BTFSS U_ERR,1 ;WARTEN AUF GELADEN? +000426 D??? 00632 BRA HLVD_LE ;NEIN UNTERSPANNUNG DETEKT-> +000428 9146 00633 BCF U_ERR,0 ;SPANNUNGSFEHLER AUS +00042A 9346 00634 BCF U_ERR,1 ;WARTEN AUF GELADEN=AUS +00042C 0E07 00635 MOVLW U_ERR_PW_AUS+2 ;POWER AUS ÜBERSPRINGEN +00042E 6F47 00636 MOVWF U_ERR_TIME ;ZEIT SETZEN +000430 0E17 00637 MOVLW B'00010111' ;INT WENN UNTER 3.12V +000432 6ED2 00638 MOVWF HLVDCON +000434 00639 WAIT_LVDOK: +000434 AAD2 00640 BTFSS HLVDCON,IVRST ;ABWARTEN BIS AENDERUNG AKTIV +000436 D??? 00641 BRA WAIT_LVDOK +000438 94A1 00642 BCF PIR2,HLVDIF ;INTERRUPT FLAG LÖSCHEN +00043A 0010 00643 RETFIE +00043C 00644 HLVD_LE ;UNTERSPANNUNG +00043C 8146 00645 BSF U_ERR,0 ;ERROR SETZEN +00043E 8346 00646 BSF U_ERR,1 ;WARTEN AUF GELADEN SETZEN +000440 6B47 00647 CLRF U_ERR_TIME ;RÜCKSETZEN + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 14 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00648 ;MESSAGE AN PROCESSOR +000442 0E03 00649 MOVLW U_MIN_TO_MCF +000444 6EAD 00650 MOVWF TXREG ;SENDEN + 00651 +000446 0E9A 00652 MOVLW B'10011010' ;INT WENN ÜBER 3.7V +000448 6ED2 00653 MOVWF HLVDCON +00044A D??? 00654 BRA WAIT_LVDOK + 00655 ;**********************************************************************************************""""""""" + """" + 00656 ;A/D INTERRUPT +00044C 00657 AD_ISR +00044C 9C9E 00658 BCF PIR1,ADIF ;CLEAR INTERRUPT PENDIG +00044E 0010 00659 RETFIE ;RETURN + 00660 ;******************************************************************************************************* + ****** + 00661 ; uhr interrupt ALLE 1/8 SEC +000450 00662 RTC_ISR + 00663 ;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN +000450 0EF0 00664 MOVLW TIMER_HB ;WIEDER AUF STARTWERT +000452 6ECF 00665 MOVWF TMR1H ;SETZEN +000454 909E 00666 BCF PIR1,TMR1IF ;INTERRUPT FLAG LÖSCHEN +000456 8881 00667 BSF PORTB,RB4 ;PIC INT HIGH -------- +000458 8096 00668 BSF TRISE,RE0 ;LED=OFF +00045A 9881 00669 BCF PORTB,RB4 ;PIC INT = LOW +00045C B095 00670 BTFSC TRISD,RD0 ;POWER OFF? +00045E D??? 00671 BRA POWER_OFF_I ;JA-> + 00672 ; POWER IS ON: + 00673 ; BLINKEN 4X/SEC WENN RESET +000460 BE95 00674 BTFSC TRISD,RD7 ;RESET AKTIV? +000462 D??? 00675 BRA PINGS ;NEIN-> +000464 B141 00676 BTFSC TICKS,0 ;UNGERADE TICKS? +000466 9096 00677 BCF TRISE,RE0 ;NEIN->LED=ON +000468 D??? 00678 BRA PINGS +00046A 00679 POWER_OFF_I +00046A 0E03 00680 MOVLW .3 +00046C 1500 00681 ANDWF SECS,0 ;4 SEKUNDEN AUSMASKIEREN +00046E E1?? 00682 BNZ PINGS ;NICHT MODULO4 -> +000470 0E07 00683 MOVLW .7 +000472 6341 00684 CPFSEQ TICKS ;7. TICK? +000474 D??? 00685 BRA POWER_OFF_I2 ;NEIN-> +000476 9096 00686 BCF TRISE,RE0 ;JA->LED=ON +000478 00687 POWER_OFF_I2 +000478 0E1E 00688 MOVLW .30 ; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER? +00047A 6147 00689 CPFSLT U_ERR_TIME +00047C D??? 00690 BRA PINGS ;NEIN-> +00047E 0E05 00691 MOVLW .5 +000480 6341 00692 CPFSEQ TICKS ;5. TICK? +000482 D??? 00693 BRA PINGS ;NEIN-> +000484 9096 00694 BCF TRISE,RE0 ;JA->LED=ON +000486 00695 PINGS +000486 EC?? F??? 00696 CALL TASTE ;UP TASTE + 00697 ; TASTE LOSGELASSEN? +00048A 0E04 00698 MOVLW RESET_OFF_TIME + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 15 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00048C 6543 00699 CPFSGT TASTE_OFF_TIME ;TASTE LÄNGER ALS 2 SEC LOSGELASSEN? +00048E D??? 00700 BRA PINGW ;NEIN-> +000490 8E95 00701 BSF TRISD,RD7 ;JA-> #RSTI INAKTIV =HIGH +000492 A095 00702 BTFSS TRISD,RD0 ;POWER ON? +000494 EC?? F??? 00703 CALL SERIAL_ON ;ja->SERIELL EINSCHALTEN + 00704 ;--TICKS=125MS +000498 00705 PINGW +000498 2B41 00706 INCF TICKS ;inc ticks +00049A A095 00707 BTFSS TRISD,RD0 ;POWER ON? +00049C D??? 00708 BRA PINGS2 ;JA-> +00049E 0E20 00709 MOVLW 20 +0004A0 6148 00710 CPFSLT U_POWER_IN ;LADEGERÄT ANGESCHLOSSEN? +0004A2 D??? 00711 BRA PINGS2 ;->JA LED HELLER +0004A4 0EA0 00712 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004A6 6147 00713 CPFSLT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004A8 8096 00714 BSF TRISE,RE0 ;JA -> LED OFF +0004AA 00715 PINGS2 +0004AA 0E07 00716 MOVLW .7 ; 7? +0004AC 6541 00717 CPFSGT TICKS +0004AE 0010 00718 RETFIE ; NEIN ->RETURN +0004B0 00719 SEKUNDEN + 00720 ;led blinken POWER ON----------------------------------------- +0004B0 A095 00721 BTFSS TRISD,RD0 ;POWER ON? +0004B2 9096 00722 BCF TRISE,RE0 ;JA -> LED_ON + 00723 ;TIMER U_ERR ERHÖHEN +0004B4 0EA0 00724 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004B6 6547 00725 CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004B8 2B47 00726 INCF U_ERR_TIME ;NEIN ERHÖHEN + 00727 ;SPANNUNGSFEHLER BEARBEITEN ---------------------------------------- +0004BA 0E05 00728 MOVLW U_ERR_PW_AUS ;POWER AUS ZEIT? +0004BC 6347 00729 CPFSEQ U_ERR_TIME ; +0004BE D??? 00730 BRA SEK_NPA ;NEIN +0004C0 EC?? F??? 00731 CALL POWER_AUS ;JA AUSSCHALTEN + 00732 ;-------------------------------------------------------- +0004C4 00733 SEK_NPA + 00734 ;SPANNUNG POWER IN MESSEN +0004C4 0E01 00735 MOVLW B'00000001' ;KANAL 0, AD ON +0004C6 6EC2 00736 MOVWF ADCON0 ; +0004C8 82C2 00737 BSF ADCON0,1 ;GO +0004CA 00738 SEK_2 +0004CA B2C2 00739 BTFSC ADCON0,1 ;FERTIG? +0004CC D??? 00740 BRA SEK_2 ;NEIN +0004CE CFC4 F048 00741 MOVFF ADRESH,U_POWER_IN ;OK WERT EINTRAGEN + 00742 + 00743 ;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1 +0004D2 B095 00744 BTFSC TRISD,RD0 ;POWER ON? +0004D4 D??? 00745 BRA SEK_4 ;NEIN NICHT MESSEN + 00746 +0004D6 0E0D 00747 MOVLW B'00001101' ;KANAL 3, AD ON +0004D8 6EC2 00748 MOVWF ADCON0 ; +0004DA 82C2 00749 BSF ADCON0,1 ;GO +0004DC 00750 SEK_3 +0004DC B2C2 00751 BTFSC ADCON0,1 ;FERTIG? + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 16 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0004DE D??? 00752 BRA SEK_3 ;NEIN +0004E0 0EC8 00753 MOVLW .200 ;UNTER 3.2V -> WENN WERT ÜBER 78% +0004E2 60C4 00754 CPFSLT ADRESH ;JA -> +0004E4 D??? 00755 BRA SEK_4 ;SONST WEITER + 00756 ;TIMER U_ERR ERHÖHEN +0004E6 A146 00757 BTFSS U_ERR,0 ;SPANNUNGSERROR? +0004E8 D??? 00758 BRA SEK_4 ;NEIN +0004EA 0EA0 00759 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004EC 6547 00760 CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004EE 0747 00761 DECF U_ERR_TIME ;NEIN -> -1 + 00762 ;------------------------------------------------------------- +0004F0 00763 SEK_4 +0004F0 6B41 00764 CLRF TICKS +0004F2 2B00 00765 INCF SECS ; Increment seconds +0004F4 0E3B 00766 MOVLW .59 ; 60 seconds elapsed? +0004F6 6500 00767 CPFSGT SECS +0004F8 0010 00768 RETFIE ;RETURN +0004FA 00769 MINUTEN +0004FA 6B00 00770 CLRF SECS ; Clear seconds +0004FC 2B02 00771 INCF MINS ; Increment minutes +0004FE 0E3B 00772 MOVLW .59 ; 60 minutes elapsed? +000500 6502 00773 CPFSGT MINS +000502 0010 00774 RETFIE ;RETURN +000504 00775 STUNDEN +000504 6B02 00776 CLRF MINS ; clear minutes +000506 2B04 00777 INCF HOURS ; Increment hours +000508 0E17 00778 MOVLW .23 ; 24 hours elapsed? +00050A 6504 00779 CPFSGT HOURS +00050C 0010 00780 RETFIE ;RETURN +00050E 00781 TAGE_UND_TAG_DER_WOCHE +00050E 6B04 00782 CLRF HOURS ; Reset hours +000510 0E07 00783 MOVLW .7 +000512 6106 00784 CPFSLT DAY_OF_WEEK +000514 6B06 00785 CLRF DAY_OF_WEEK +000516 2B06 00786 INCF DAY_OF_WEEK +000518 2B07 00787 INCF DAYS +00051A 0E1C 00788 MOVLW .28 +00051C 6507 00789 CPFSGT DAYS +00051E 0010 00790 RETFIE ;RETURN +000520 00791 MEHR_ALS_28_TAGE +000520 0E02 00792 MOVLW .2 +000522 6308 00793 CPFSEQ MONTHS ;FEB? +000524 D??? 00794 BRA NOT_FEB ;NEIN-> +000526 00795 FEB +000526 0E03 00796 MOVLW .3 +000528 1509 00797 ANDWF YEARS,0 ;SCHALTJAHR +00052A E1?? 00798 BNZ NEXT_MONTH ;NEIN-> +00052C 00799 SCHALTJAHR +00052C 0E1D 00800 MOVLW .29 +00052E 6507 00801 CPFSGT DAYS +000530 0010 00802 RETFIE ;RETURN +000532 00803 NEXT_MONTH +000532 0E01 00804 MOVLW .1 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 17 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000534 6F07 00805 MOVWF DAYS +000536 2B08 00806 INCF MONTHS +000538 0E12 00807 MOVLW 12 +00053A 6508 00808 CPFSGT MONTHS +00053C 0010 00809 RETFIE ;RETURN +00053E 00810 YEAR +00053E 0E01 00811 MOVLW .1 +000540 6F08 00812 MOVWF MONTHS +000542 2B09 00813 INCF YEARS +000544 0010 00814 RETFIE ;RETURN +000546 00815 NOT_FEB +000546 0E1E 00816 MOVLW .30 +000548 6507 00817 CPFSGT DAYS +00054A 0010 00818 RETFIE +00054C 00819 MEHR_ALS_30_TAGE +00054C 0E04 00820 MOVLW .4 ;APRIL? +00054E 6308 00821 CPFSEQ MONTHS ;SKIP +000550 D??? 00822 BRA NOT_APRIL +000552 D??? 00823 BRA NEXT_MONTH ;APRIL-> +000554 00824 NOT_APRIL +000554 0E06 00825 MOVLW .6 ;JUNI? +000556 6308 00826 CPFSEQ MONTHS +000558 D??? 00827 BRA NOT_JUNI +00055A D??? 00828 BRA NEXT_MONTH ;JUNI-> +00055C 00829 NOT_JUNI +00055C 0E09 00830 MOVLW .9 ;SEPTEMBER? +00055E 6308 00831 CPFSEQ MONTHS +000560 D??? 00832 BRA NOT_SEP +000562 D??? 00833 BRA NEXT_MONTH ;SEPTEMBER-> +000564 00834 NOT_SEP +000564 0E0B 00835 MOVLW .11 ;NOVEMBER? +000566 6308 00836 CPFSEQ MONTHS ;SKIP +000568 0010 00837 RETFIE ;SIND MONATE MIT 31 TAGEN-> +00056A D??? 00838 BRA NEXT_MONTH ;SONST NOVEMBER-> + 00839 ;**********************************************************************************************""""""""" + """" + 00840 ; ENDE MAIN + 00841 ;**********************************************************************************************""""""""" + """" + 00842 ;**********************************************************************************************""""""""" + """" + 00843 ; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN + 00844 ;**********************************************************************************************""""""""" + """" + 00845 end + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 18 + + +SYMBOL TABLE + LABEL VALUE + +A 00000000 +ABDEN 00000000 +ABDOVF 00000007 +ACCESS 00000000 +ACKDT 00000005 +ACKEN 00000004 +ACKSTAT 00000006 +ACQT0 00000003 +ACQT1 00000004 +ACQT2 00000005 +ADCON0 00000FC2 +ADCON1 00000FC1 +ADCON2 00000FC0 +ADCS0 00000000 +ADCS1 00000001 +ADCS2 00000002 +ADDEN 00000003 +ADEN 00000003 +ADFM 00000007 +ADIE 00000006 +ADIF 00000006 +ADIP 00000006 +ADON 00000000 +ADRES 00000FC3 +ADRESH 00000FC4 +ADRESL 00000FC3 +AD_ISR 0000044C +AD_KANAL 00000045 +AN0 00000000 +AN1 00000001 +AN10 00000001 +AN11 00000004 +AN12 00000000 +AN2 00000002 +AN3 00000003 +AN4 00000005 +AN5 00000000 +AN6 00000001 +AN7 00000002 +AN8 00000002 +AN9 00000003 +BANKED 00000001 +BAUDCON 00000FB8 +BAUDCTL 00000FB8 +BCLIE 00000003 +BCLIF 00000003 +BCLIP 00000003 +BF 00000000 +BGST 00000005 +BOR 00000000 +BRG16 00000003 +BRGH 00000002 +BSR 00000FE0 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 19 + + +SYMBOL TABLE + LABEL VALUE + +C 00000000 +C1INV 00000004 +C1OUT 00000006 +C2INV 00000005 +C2OUT 00000007 +CCP1 00000002 +CCP1CON 00000FBD +CCP1IE 00000002 +CCP1IF 00000002 +CCP1IP 00000002 +CCP1M0 00000000 +CCP1M1 00000001 +CCP1M2 00000002 +CCP1M3 00000003 +CCP1X 00000005 +CCP1Y 00000004 +CCP2CON 00000FBA +CCP2IE 00000000 +CCP2IF 00000000 +CCP2IP 00000000 +CCP2M0 00000000 +CCP2M1 00000001 +CCP2M2 00000002 +CCP2M3 00000003 +CCP2X 00000005 +CCP2Y 00000004 +CCP2_PORTB 00000003 +CCP2_PORTC 00000001 +CCPR1 00000FBE +CCPR1H 00000FBF +CCPR1L 00000FBE +CCPR2 00000FBB +CCPR2H 00000FBC +CCPR2L 00000FBB +CFGS 00000006 +CHS0 00000002 +CHS1 00000003 +CHS2 00000004 +CHS3 00000005 +CIS 00000003 +CK 00000006 +CKE 00000006 +CKP 00000004 +CLKI 00000007 +CLKO 00000006 +CLK_ACTIV 00000072 +CLK_SLEEP 00000012 +CM0 00000000 +CM1 00000001 +CM2 00000002 +CMCON 00000FB4 +CMIE 00000006 +CMIF 00000006 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 20 + + +SYMBOL TABLE + LABEL VALUE + +CMIP 00000006 +CREN 00000004 +CS 00000002 +CSRC 00000007 +CVR0 00000000 +CVR1 00000001 +CVR2 00000002 +CVR3 00000003 +CVRCON 00000FB5 +CVREF 00000002 +CVREN 00000007 +CVROE 00000006 +CVRR 00000005 +CVRSS 00000004 +D 00000005 +DAYS 00000007 +DAY_OF_WEEK 00000006 +DC 00000001 +DC1B0 00000004 +DC1B1 00000005 +DC2B0 00000004 +DC2B1 00000005 +DDRA TRISA +DDRB TRISB +DDRC TRISC +DDRD TRISD +DDRE TRISE +DONE 00000001 +D_A 00000005 +EAPIR1 0000004E +EAPIR2 0000004F +ECCP1AS 00000FB6 +ECCPAS0 00000004 +ECCPAS1 00000005 +ECCPAS2 00000006 +ECCPASE 00000007 +EEADR 00000FA9 +EECON1 00000FA6 +EECON2 00000FA7 +EEDATA 00000FA8 +EEIE 00000004 +EEIF 00000004 +EEIP 00000004 +EEPGD 00000007 +EXTERN_INTERRUPTS 00002002 +EXTERN_INT_ADR 00002000 +EXTERN_SUBROUTINES 00002012 +EXTERN_SUB_ADR 00002010 +EXT_CODE 000000FB +EXT_SUB_GO 00000004 +EXT_SUB_STOP 00000005 +FAST 00000001 +FEB 00000526 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 21 + + +SYMBOL TABLE + LABEL VALUE + +FERR 00000002 +FLTS 00000002 +FREE 00000004 +FSR0 00000000 +FSR0H 00000FEA +FSR0L 00000FE9 +FSR1 00000001 +FSR1H 00000FE2 +FSR1L 00000FE1 +FSR2 00000002 +FSR2H 00000FDA +FSR2L 00000FD9 +GCEN 00000007 +GIE 00000007 +GIEH 00000007 +GIEL 00000006 +GO 00000001 +GO_DONE 00000001 +GO_INT 0000004D +GO_SUB 0000004C +HLVDCON 00000FD2 +HLVDEN 00000004 +HLVDIE 00000002 +HLVDIF 00000002 +HLVDIP 00000002 +HLVDL0 00000000 +HLVDL1 00000001 +HLVDL2 00000002 +HLVDL3 00000003 +HLVD_ISR 00000424 +HLVD_LE 0000043C +HOURS 00000004 +HOURS_ALARM 00000005 +IBF 00000007 +IBOV 00000005 +IDLEN 00000007 +INDF0 00000FEF +INDF1 00000FE7 +INDF2 00000FDF +INT0 00000000 +INT0E 00000004 +INT0F 00000001 +INT0IE 00000004 +INT0IF 00000001 +INT1 00000001 +INT1E 00000003 +INT1F 00000000 +INT1IE 00000003 +INT1IF 00000000 +INT1IP 00000006 +INT1P 00000006 +INT2 00000002 +INT2E 00000004 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 22 + + +SYMBOL TABLE + LABEL VALUE + +INT2F 00000001 +INT2IE 00000004 +INT2IF 00000001 +INT2IP 00000007 +INT2P 00000007 +INTCON 00000FF2 +INTCON2 00000FF1 +INTCON3 00000FF0 +INTEDG0 00000006 +INTEDG1 00000005 +INTEDG2 00000004 +INTSRC 00000007 +INT_HANDLER 00000018 +IOFS 00000002 +IPEN 00000007 +IPR1 00000F9F +IPR2 00000FA2 +IRCF0 00000004 +IRCF1 00000005 +IRCF2 00000006 +IRVST 00000005 +IVRST 00000005 +KALT_START 00000100 +KBI0 00000004 +KBI1 00000005 +KBI2 00000006 +KBI3 00000007 +LADESTROM 000001D2 +LATA 00000F89 +LATA0 00000000 +LATA1 00000001 +LATA2 00000002 +LATA3 00000003 +LATA4 00000004 +LATA5 00000005 +LATA6 00000006 +LATA7 00000007 +LATB 00000F8A +LATB0 00000000 +LATB1 00000001 +LATB2 00000002 +LATB3 00000003 +LATB4 00000004 +LATB5 00000005 +LATB6 00000006 +LATB7 00000007 +LATC 00000F8B +LATC0 00000000 +LATC1 00000001 +LATC2 00000002 +LATC3 00000003 +LATC4 00000004 +LATC5 00000005 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 23 + + +SYMBOL TABLE + LABEL VALUE + +LATC6 00000006 +LATC7 00000007 +LATD 00000F8C +LATD0 00000000 +LATD1 00000001 +LATD2 00000002 +LATD3 00000003 +LATD4 00000004 +LATD5 00000005 +LATD6 00000006 +LATD7 00000007 +LATE 00000F8D +LATE0 00000000 +LATE1 00000001 +LATE2 00000002 +LS_OFF_POWER 000001DA +LS_ON_POWER 000001D6 +LVDCON 00000FD2 +LVDEN 00000004 +LVDIE 00000002 +LVDIF 00000002 +LVDIN 00000005 +LVDIP 00000002 +LVDL0 00000000 +LVDL1 00000001 +LVDL2 00000002 +LVDL3 00000003 +LVV0 00000000 +LVV1 00000001 +LVV2 00000002 +LVV3 00000003 +MAIN 0000019E +MAIN2 000001AE +MCLR 00000003 +MEHR_ALS_28_TAGE 00000520 +MEHR_ALS_30_TAGE 0000054C +MINS 00000002 +MINS_ALRAM 00000003 +MINUTEN 000004FA +MONTHS 00000008 +N 00000004 +NEXT_MONTH 00000532 +NON_SYNC 000003D2 +NOT_A 00000005 +NOT_ADDRESS 00000005 +NOT_APRIL 00000554 +NOT_BOR 00000000 +NOT_CS 00000002 +NOT_DONE 00000001 +NOT_FEB 00000546 +NOT_JUNI 0000055C +NOT_MCLR 00000003 +NOT_PD 00000002 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 24 + + +SYMBOL TABLE + LABEL VALUE + +NOT_POR 00000001 +NOT_RBPU 00000007 +NOT_RD 00000000 +NOT_RI 00000004 +NOT_SEP 00000564 +NOT_SS 00000005 +NOT_T1SYNC 00000002 +NOT_T3SYNC 00000002 +NOT_TO 00000003 +NOT_W 00000002 +NOT_WR 00000001 +NOT_WRITE 00000002 +NO_PROG 000003AC +OBF 00000006 +OERR 00000001 +OFF_TIME 00000014 +ON_TIME 00000002 +OSC1 00000007 +OSC2 00000006 +OSCCON 00000FD3 +OSCFIE 00000007 +OSCFIF 00000007 +OSCFIP 00000007 +OSCTUNE 00000F9B +OSTS 00000003 +OV 00000003 +P 00000004 +P1B 00000005 +P1C 00000006 +P1D 00000007 +P1M0 00000006 +P1M1 00000007 +PC 00000FF9 +PCFG0 00000000 +PCFG1 00000001 +PCFG2 00000002 +PCFG3 00000003 +PCL 00000FF9 +PCLATH 00000FFA +PCLATU 00000FFB +PD 00000002 +PDC0 00000000 +PDC1 00000001 +PDC2 00000002 +PDC3 00000003 +PDC4 00000004 +PDC5 00000005 +PDC6 00000006 +PEIE 00000006 +PEN 00000002 +PGC 00000006 +PGD 00000007 +PGM 00000005 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 25 + + +SYMBOL TABLE + LABEL VALUE + +PIE1 00000F9D +PIE2 00000FA0 +PINGS 00000486 +PINGS2 000004AA +PINGW 00000498 +PIR1 00000F9E +PIR2 00000FA1 +PLLEN 00000006 +PLUSW0 00000FEB +PLUSW1 00000FE3 +PLUSW2 00000FDB +POR 00000001 +PORTA 00000F80 +PORTB 00000F81 +PORTC 00000F82 +PORTD 00000F83 +PORTE 00000F84 +POSTDEC0 00000FED +POSTDEC1 00000FE5 +POSTDEC2 00000FDD +POSTINC0 00000FEE +POSTINC1 00000FE6 +POSTINC2 00000FDE +POWER_AUS 000001C2 +POWER_EIN 000001B4 +POWER_OFF_I 0000046A +POWER_OFF_I2 00000478 +POWER_ON_TIME 00000044 +PR2 00000FCB +PREINC0 00000FEC +PREINC1 00000FE4 +PREINC2 00000FDC +PRG_OK_PIC 00000022 +PROD 00000FF3 +PRODH 00000FF4 +PRODL 00000FF3 +PROGRAM_MEMORY 0000039A +PRSEN 00000007 +PSA 00000003 +PSP0 00000000 +PSP1 00000001 +PSP2 00000002 +PSP3 00000003 +PSP4 00000004 +PSP5 00000005 +PSP6 00000006 +PSP7 00000007 +PSPIE 00000007 +PSPIF 00000007 +PSPIP 00000007 +PSPMODE 00000004 +PSSAC0 00000002 +PSSAC1 00000003 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 26 + + +SYMBOL TABLE + LABEL VALUE + +PSSBD0 00000000 +PSSBD1 00000001 +PWM1CON 00000FB7 +R 00000002 +RA0 00000000 +RA1 00000001 +RA2 00000002 +RA3 00000003 +RA4 00000004 +RA5 00000005 +RA6 00000006 +RA7 00000007 +RB0 00000000 +RB1 00000001 +RB2 00000002 +RB3 00000003 +RB4 00000004 +RB5 00000005 +RB6 00000006 +RB7 00000007 +RBIE 00000003 +RBIF 00000000 +RBIP 00000000 +RBPU 00000007 +RC0 00000000 +RC1 00000001 +RC2 00000002 +RC3 00000003 +RC4 00000004 +RC5 00000005 +RC6 00000006 +RC7 00000007 +RCEN 00000003 +RCIDL 00000006 +RCIE 00000005 +RCIF 00000005 +RCIP 00000005 +RCMT 00000006 +RCON 00000FD0 +RCREG 00000FAE +RCSTA 00000FAB +RD 00000000 +RD0 00000000 +RD1 00000001 +RD16 00000007 +RD2 00000002 +RD3 00000003 +RD4 00000004 +RD5 00000005 +RD6 00000006 +RD7 00000007 +RE0 00000000 +RE1 00000001 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 27 + + +SYMBOL TABLE + LABEL VALUE + +RE2 00000002 +RE3 00000003 +READ_BLOCK 000000A1 +REGA 0000000A +REGB 0000000B +REGC 0000000C +REGD 0000000D +REQ_BLOCK 000000A0 +REQ_RTCD_FROM_MCF 00000002 +REQ_RTCD_FROM_PIC 00000001 +RESETEN 00000256 +RESET_OFF_TIME 00000004 +RESET_ON_TIME 00000002 +RI 00000004 +RSEN 00000001 +RTCD_FROM_MCF 00000082 +RTCD_FROM_PIC 00000081 +RTC_ISR 00000450 +RTC_RAM 0000000E +RX 00000007 +RX9 00000006 +RX9D 00000000 +RXDTP 00000005 +RX_B 00000049 +RX_BUFFER 00000100 +RX_ISR 00000288 +RX_ISR1 000002A4 +RX_ISR2 000002B0 +RX_ISR3 000002C8 +RX_ISR4 000002F6 +RX_ISR5 00000304 +RX_ISR6 00000312 +RX_ISR7 00000350 +RX_ISR8 000003B0 +RX_ISR9 000003BC +RX_RB3B2 00000334 +RX_RB3BOK 00000322 +RX_STATUS 0000004A +RX_SYNC2 000003D8 +RX_SYNC3 000003EA +RX_SYNC4 000003FC +RX_SYNC_START 000003C0 +RX_WAIT1 00000408 +RX_WAIT2 00000410 +RX_WAIT3 00000418 +R_W 00000002 +S 00000003 +SBOREN 00000006 +SCHALTJAHR 0000052C +SCK 00000003 +SCKP 00000004 +SCL 00000003 +SCS0 00000000 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 28 + + +SYMBOL TABLE + LABEL VALUE + +SCS1 00000001 +SDA 00000004 +SDI 00000004 +SDO 00000005 +SECS 00000000 +SECS_ALARM 00000001 +SEKUNDEN 000004B0 +SEK_2 000004CA +SEK_3 000004DC +SEK_4 000004F0 +SEK_NPA 000004C4 +SEN 00000000 +SENDB 00000003 +SEND_RTC_REG 00000232 +SEND_RTC_TIME 00000002 +SERIAL_OFF 000001DE +SERIAL_ON 000001EA +SMP 00000007 +SP0 00000000 +SP1 00000001 +SP2 00000002 +SP3 00000003 +SP4 00000004 +SPBRG 00000FAF +SPBRGH 00000FB0 +SPEN 00000007 +SREN 00000005 +SS 00000005 +SSPADD 00000FC8 +SSPBUF 00000FC9 +SSPCON1 00000FC6 +SSPCON2 00000FC5 +SSPEN 00000005 +SSPIE 00000003 +SSPIF 00000003 +SSPIP 00000003 +SSPM0 00000000 +SSPM1 00000001 +SSPM2 00000002 +SSPM3 00000003 +SSPOV 00000006 +SSPSTAT 00000FC7 +STATUS 00000FD8 +STKFUL 00000007 +STKOVF 00000007 +STKPTR 00000FFC +STKUNF 00000006 +STUNDEN 00000504 +SWDTE 00000000 +SWDTEN 00000000 +SYNC 00000004 +SYNC1 000000FF +SYNC1_DATA 00000041 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 29 + + +SYMBOL TABLE + LABEL VALUE + +SYNC2 000000FE +SYNC2_DATA 00000043 +SYNC3 000000FD +SYNC3_DATA 00000050 +SYNC4 000000FC +SYNC4_DATA 00000046 +T08BIT 00000006 +T0CKI 00000004 +T0CON 00000FD5 +T0CS 00000005 +T0IE 00000005 +T0IF 00000002 +T0PS0 00000000 +T0PS1 00000001 +T0PS2 00000002 +T0SE 00000004 +T13CKI 00000000 +T1CKI 00000000 +T1CKPS0 00000004 +T1CKPS1 00000005 +T1CON 00000FCD +T1OSCEN 00000003 +T1OSI 00000001 +T1OSO 00000000 +T1RUN 00000006 +T1SYNC 00000002 +T2CKPS0 00000000 +T2CKPS1 00000001 +T2CON 00000FCA +T2OUTPS0 00000003 +T2OUTPS1 00000004 +T2OUTPS2 00000005 +T2OUTPS3 00000006 +T3CCP1 00000003 +T3CCP2 00000006 +T3CKPS0 00000004 +T3CKPS1 00000005 +T3CON 00000FB1 +T3SYNC 00000002 +TABLAT 00000FF5 +TAGE_UND_TAG_DER_WOCHE 0000050E +TASTE 00000208 +TASTE_OFF_TIME 00000043 +TASTE_ON_TIME 00000042 +TBLPTR 00000FF6 +TBLPTRH 00000FF7 +TBLPTRL 00000FF6 +TBLPTRU 00000FF8 +TG_END 00000250 +TG_JA 00000222 +TG_OFF_POWER 00000248 +TG_ON_POWER 0000022C +TG_ON_POWER2 00000238 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 30 + + +SYMBOL TABLE + LABEL VALUE + +TG_ON_POWER3 0000023E +TICKS 00000041 +TIMER_HB 000000F0 +TIME_MAX 000000A0 +TMR0H 00000FD7 +TMR0IE 00000005 +TMR0IF 00000002 +TMR0IP 00000002 +TMR0L 00000FD6 +TMR0ON 00000007 +TMR1CS 00000001 +TMR1H 00000FCF +TMR1IE 00000000 +TMR1IF 00000000 +TMR1IP 00000000 +TMR1L 00000FCE +TMR1ON 00000000 +TMR2 00000FCC +TMR2IE 00000001 +TMR2IF 00000001 +TMR2IP 00000001 +TMR2ON 00000002 +TMR3CS 00000001 +TMR3H 00000FB3 +TMR3IE 00000001 +TMR3IF 00000001 +TMR3IP 00000001 +TMR3L 00000FB2 +TMR3ON 00000000 +TO 00000003 +TOS 00000FFD +TOSH 00000FFE +TOSL 00000FFD +TOSU 00000FFF +TRISA 00000F92 +TRISA0 00000000 +TRISA1 00000001 +TRISA2 00000002 +TRISA3 00000003 +TRISA4 00000004 +TRISA5 00000005 +TRISA6 00000006 +TRISA7 00000007 +TRISB 00000F93 +TRISB0 00000000 +TRISB1 00000001 +TRISB2 00000002 +TRISB3 00000003 +TRISB4 00000004 +TRISB5 00000005 +TRISB6 00000006 +TRISB7 00000007 +TRISC 00000F94 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 31 + + +SYMBOL TABLE + LABEL VALUE + +TRISC0 00000000 +TRISC1 00000001 +TRISC2 00000002 +TRISC3 00000003 +TRISC4 00000004 +TRISC5 00000005 +TRISC6 00000006 +TRISC7 00000007 +TRISD 00000F95 +TRISD0 00000000 +TRISD1 00000001 +TRISD2 00000002 +TRISD3 00000003 +TRISD4 00000004 +TRISD5 00000005 +TRISD6 00000006 +TRISD7 00000007 +TRISE 00000F96 +TRISE0 00000000 +TRISE1 00000001 +TRISE2 00000002 +TRMT 00000001 +TUN0 00000000 +TUN1 00000001 +TUN2 00000002 +TUN3 00000003 +TUN4 00000004 +TX 00000006 +TX9 00000006 +TX9D 00000000 +TXCKP 00000004 +TXEN 00000005 +TXIE 00000004 +TXIF 00000004 +TXIP 00000004 +TXREG 00000FAD +TXSTA 00000FAC +TX_BUFFER 00000180 +TX_ISR 0000025E +TX_ISR1 00000276 +TX_ISR2 00000286 +TX_ISR_FERTIG 0000026E +TX_STATUS 0000004B +UA 00000001 +U_ERR 00000046 +U_ERR_PW_AUS 00000005 +U_ERR_TIME 00000047 +U_MIN_TO_MCF 00000003 +U_POWER_IN 00000048 +VCFG0 00000004 +VCFG1 00000005 +VDIRMAG 00000007 +VPP 00000003 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 32 + + +SYMBOL TABLE + LABEL VALUE + +VREFN 00000002 +VREFP 00000003 +W 00000000 +WAIT_LVDOK 00000434 +WARTEN 000001A8 +WCOL 00000007 +WDTCON 00000FD1 +WR 00000001 +WREG 00000FE8 +WREN 00000002 +WRERR 00000003 +WRITE_BLOCK 000000A2 +WRITE_WORD_TO_HREGS 00000390 +WUE 00000001 +YEAR 0000053E +YEARS 00000009 +Z 00000002 +_BOREN_NOSLP_2L 000000FD +_BOREN_OFF_2L 000000F9 +_BOREN_ON_2L 000000FB +_BOREN_SBORDIS_2L 000000FF +_BORV_0_2L 000000E7 +_BORV_1_2L 000000EF +_BORV_2_2L 000000F7 +_BORV_3_2L 000000FF +_CCP2MX_PORTBE_3H 000000FE +_CCP2MX_PORTC_3H 000000FF +_CONFIG1H 00300001 +_CONFIG2H 00300003 +_CONFIG2L 00300002 +_CONFIG3H 00300005 +_CONFIG4L 00300006 +_CONFIG5H 00300009 +_CONFIG5L 00300008 +_CONFIG6H 0030000B +_CONFIG6L 0030000A +_CONFIG7H 0030000D +_CONFIG7L 0030000C +_CP0_OFF_5L 000000FF +_CP0_ON_5L 000000FE +_CP1_OFF_5L 000000FF +_CP1_ON_5L 000000FD +_CP2_OFF_5L 000000FF +_CP2_ON_5L 000000FB +_CP3_OFF_5L 000000FF +_CP3_ON_5L 000000F7 +_CPB_OFF_5H 000000FF +_CPB_ON_5H 000000BF +_CPD_OFF_5H 000000FF +_CPD_ON_5H 0000007F +_DEBUG_OFF_4L 000000FF +_DEBUG_ON_4L 0000007F +_DEVID1 003FFFFE + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 33 + + +SYMBOL TABLE + LABEL VALUE + +_DEVID2 003FFFFF +_EBTR0_OFF_7L 000000FF +_EBTR0_ON_7L 000000FE +_EBTR1_OFF_7L 000000FF +_EBTR1_ON_7L 000000FD +_EBTR2_OFF_7L 000000FF +_EBTR2_ON_7L 000000FB +_EBTR3_OFF_7L 000000FF +_EBTR3_ON_7L 000000F7 +_EBTRB_OFF_7H 000000FF +_EBTRB_ON_7H 000000BF +_FCMEN_OFF_1H 000000BF +_FCMEN_ON_1H 000000FF +_IDLOC0 00200000 +_IDLOC1 00200001 +_IDLOC2 00200002 +_IDLOC3 00200003 +_IDLOC4 00200004 +_IDLOC5 00200005 +_IDLOC6 00200006 +_IDLOC7 00200007 +_IESO_OFF_1H 0000007F +_IESO_ON_1H 000000FF +_LPT1OSC_OFF_3H 000000FB +_LPT1OSC_ON_3H 000000FF +_LVP_OFF_4L 000000FB +_LVP_ON_4L 000000FF +_MCLRE_OFF_3H 0000007F +_MCLRE_ON_3H 000000FF +_OSC_ECIO6_1H 000000F5 +_OSC_EC_1H 000000F4 +_OSC_HSPLL_1H 000000F6 +_OSC_HS_1H 000000F2 +_OSC_INTIO67_1H 000000F8 +_OSC_INTIO7_1H 000000F9 +_OSC_LP_1H 000000F0 +_OSC_RCIO6_1H 000000F7 +_OSC_RC_1H 000000F3 +_OSC_XT_1H 000000F1 +_PBADEN_OFF_3H 000000FD +_PBADEN_ON_3H 000000FF +_PWRT_OFF_2L 000000FF +_PWRT_ON_2L 000000FE +_STVREN_OFF_4L 000000FE +_STVREN_ON_4L 000000FF +_WDTPS_1024_2H 000000F5 +_WDTPS_128_2H 000000EF +_WDTPS_16384_2H 000000FD +_WDTPS_16_2H 000000E9 +_WDTPS_1_2H 000000E1 +_WDTPS_2048_2H 000000F7 +_WDTPS_256_2H 000000F1 +_WDTPS_2_2H 000000E3 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 34 + + +SYMBOL TABLE + LABEL VALUE + +_WDTPS_32768_2H 000000FF +_WDTPS_32_2H 000000EB +_WDTPS_4096_2H 000000F9 +_WDTPS_4_2H 000000E5 +_WDTPS_512_2H 000000F3 +_WDTPS_64_2H 000000ED +_WDTPS_8192_2H 000000FB +_WDTPS_8_2H 000000E7 +_WDT_OFF_2H 000000FE +_WDT_ON_2H 000000FF +_WRT0_OFF_6L 000000FF +_WRT0_ON_6L 000000FE +_WRT1_OFF_6L 000000FF +_WRT1_ON_6L 000000FD +_WRT2_OFF_6L 000000FF +_WRT2_ON_6L 000000FB +_WRT3_OFF_6L 000000FF +_WRT3_ON_6L 000000F7 +_WRTB_OFF_6H 000000FF +_WRTB_ON_6H 000000BF +_WRTC_OFF_6H 000000FF +_WRTC_ON_6H 000000DF +_WRTD_OFF_6H 000000FF +_WRTD_ON_6H 0000007F +_XINST_OFF_4L 000000BF +_XINST_ON_4L 000000FF +__18F4520 00000001 +free 00000040 + +Errors : 0 +Warnings : 0 reported, 0 suppressed +Messages : 0 reported, 0 suppressed + + \ No newline at end of file diff --git a/MLAB/firebee1/firebee1.map b/MLAB/firebee1/firebee1.map new file mode 100644 index 0000000..678b3b3 --- /dev/null +++ b/MLAB/firebee1/firebee1.map @@ -0,0 +1,188 @@ +MPLINK 4.35, Linker +Linker Map File - Created Fri Oct 01 13:06:43 2010 + + Section Info + Section Type Address Location Size(Bytes) + --------- --------- --------- --------- --------- + Reset_Vector code 0x000000 program 0x000002 + .cinit romdata 0x000002 program 0x000002 + HIGH_INT_VEC code 0x000008 program 0x000004 + LOW_INT_VEC code 0x000018 program 0x00004a + .code code 0x000100 program 0x00046c + + + + Program Memory Usage + Start End + --------- --------- + 0x000000 0x000003 + 0x000008 0x00000b + 0x000018 0x000061 + 0x000100 0x00056b + 1214 out of 33048 program addresses used, program memory utilization is 3% + + + + Symbols - Sorted by Name + Name Address Location Storage File + --------- --------- --------- --------- --------- + AD_ISR 0x00044c program static C:\FireBee\MLAB\firebee1\firebee1.asm + FEB 0x000526 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000424 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00043c program static C:\FireBee\MLAB\firebee1\firebee1.asm + INT_HANDLER 0x000018 program static C:\FireBee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001da program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN2 0x0001ae program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x000520 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x00054c program static C:\FireBee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0004fa program static C:\FireBee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x000532 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0003d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x000554 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x000546 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x00055c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000564 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NO_PROG 0x0003ac program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS 0x000486 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS2 0x0004aa program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGW 0x000498 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001b4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x00046a program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000478 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PROGRAM_MEMORY 0x00039a program static C:\FireBee\MLAB\firebee1\firebee1.asm + RESETEN 0x000256 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000450 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR 0x000288 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR1 0x0002a4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR2 0x0002b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR3 0x0002c8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR4 0x0002f6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR5 0x000304 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR6 0x000312 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR7 0x000350 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR8 0x0003b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR9 0x0003bc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3B2 0x000334 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3BOK 0x000322 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC2 0x0003d8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC3 0x0003ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC4 0x0003fc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC_START 0x0003c0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT1 0x000408 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT2 0x000410 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT3 0x000418 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x00052c program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x0004b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_2 0x0004ca program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_3 0x0004dc program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_4 0x0004f0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x0004c4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x000232 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_OFF 0x0001de program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_ON 0x0001ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + STUNDEN 0x000504 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x00050e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TASTE 0x000208 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_END 0x000250 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_JA 0x000222 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000248 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x00022c program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000238 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x00023e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00025e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000276 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR2 0x000286 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00026e program static C:\FireBee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000434 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WRITE_WORD_TO_HREGS 0x000390 program static C:\FireBee\MLAB\firebee1\firebee1.asm + YEAR 0x00053e program static C:\FireBee\MLAB\firebee1\firebee1.asm + + + + Symbols - Sorted by Address + Name Address Location Storage File + --------- --------- --------- --------- --------- + INT_HANDLER 0x000018 program static C:\FireBee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\FireBee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN2 0x0001ae program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001b4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001da program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_OFF 0x0001de program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_ON 0x0001ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + TASTE 0x000208 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_JA 0x000222 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x00022c program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x000232 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000238 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x00023e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000248 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_END 0x000250 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RESETEN 0x000256 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00025e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00026e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000276 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR2 0x000286 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR 0x000288 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR1 0x0002a4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR2 0x0002b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR3 0x0002c8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR4 0x0002f6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR5 0x000304 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR6 0x000312 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3BOK 0x000322 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3B2 0x000334 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR7 0x000350 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WRITE_WORD_TO_HREGS 0x000390 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PROGRAM_MEMORY 0x00039a program static C:\FireBee\MLAB\firebee1\firebee1.asm + NO_PROG 0x0003ac program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR8 0x0003b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR9 0x0003bc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC_START 0x0003c0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0003d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC2 0x0003d8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC3 0x0003ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC4 0x0003fc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT1 0x000408 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT2 0x000410 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT3 0x000418 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000424 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000434 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00043c program static C:\FireBee\MLAB\firebee1\firebee1.asm + AD_ISR 0x00044c program static C:\FireBee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000450 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x00046a program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000478 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS 0x000486 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGW 0x000498 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS2 0x0004aa program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x0004b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x0004c4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_2 0x0004ca program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_3 0x0004dc program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_4 0x0004f0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0004fa program static C:\FireBee\MLAB\firebee1\firebee1.asm + STUNDEN 0x000504 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x00050e program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x000520 program static C:\FireBee\MLAB\firebee1\firebee1.asm + FEB 0x000526 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x00052c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x000532 program static C:\FireBee\MLAB\firebee1\firebee1.asm + YEAR 0x00053e program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x000546 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x00054c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x000554 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x00055c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000564 program static C:\FireBee\MLAB\firebee1\firebee1.asm + + diff --git a/MLAB/firebee1/firebee1.mcp b/MLAB/firebee1/firebee1.mcp new file mode 100644 index 0000000..45e7dcc --- /dev/null +++ b/MLAB/firebee1/firebee1.mcp @@ -0,0 +1,53 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +device=PIC18F4520 +[PATH_INFO] +BuildDirPolicy=BuildDirIsProjectDir +dir_src= +dir_bin= +dir_tmp= +dir_sin= +dir_inc= +dir_lib= +dir_lkr= +[CAT_FILTERS] +filter_src=*.asm +filter_inc=*.h;*.inc +filter_obj=*.o +filter_lib=*.lib +filter_lkr=*.lkr +[CAT_SUBFOLDERS] +subfolder_src= +subfolder_inc= +subfolder_obj= +subfolder_lib= +subfolder_lkr= +[FILE_SUBFOLDERS] +file_000=. +file_001=. +[GENERATED_FILES] +file_000=no +file_001=no +[OTHER_FILES] +file_000=no +file_001=no +[FILE_INFO] +file_000=firebee1.asm +file_001=C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr +[SUITE_INFO] +suite_guid={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +suite_state= +[TOOL_SETTINGS] +TS{DD2213A8-6310-47B1-8376-9430CDFC013F}= +TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}= +[INSTRUMENTED_TRACE] +enable=0 +transport=0 +format=0 +[CUSTOM_BUILD] +Pre-Build= +Pre-BuildEnabled=1 +Post-Build= +Post-BuildEnabled=1 diff --git a/MLAB/firebee1/firebee1.mcs b/MLAB/firebee1/firebee1.mcs new file mode 100644 index 0000000..242fa7b --- /dev/null +++ b/MLAB/firebee1/firebee1.mcs @@ -0,0 +1,71 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 +[File000] +Location=C:\FireBee\MLAB\firebee1\firebee1.o +Folder=Intermediary +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File001] +Location=C:\FireBee\MLAB\firebee1\firebee1.err +Folder=Intermediary +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File002] +Location=C:\FireBee\MLAB\firebee1\firebee1.lst +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File003] +Location=C:\FireBee\MLAB\firebee1\firebee1.cof +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TraceCmdString= +DebugOptions= +[File004] +Location=C:\FireBee\MLAB\firebee1\firebee1.hex +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TraceCmdString= +DebugOptions= +[TOOL_LOC_STAMPS] +tool_loc{49D3CA3F-D9A3-4518-9943-226A347E8CC7}=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe diff --git a/MLAB/firebee1/firebee1.mcw b/MLAB/firebee1/firebee1.mcw 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zug?7aO#;6?8SR(9%vz?7;rB1SD9USQy8Qk(;Op)67=e+#J7|_P|JwQIcf|_1{ih|b zdma5R^!uw$eEG3MRN{NjWPrc^(lXzMEL2y18oqyKeE*Kz)8*$Eiu2A$-T;0Wzd!1O K{(aW(kNyXv-`UOp literal 0 HcmV?d00001 diff --git a/MLAB/firebee1/firebeei1.map b/MLAB/firebee1/firebeei1.map new file mode 100644 index 0000000..e12b3b5 --- /dev/null +++ b/MLAB/firebee1/firebeei1.map @@ -0,0 +1,156 @@ +MPLINK 4.33, Linker +Linker Map File - Created Mon Jan 11 14:35:58 2010 + + Section Info + Section Type Address Location Size(Bytes) + --------- --------- --------- --------- --------- + Reset_Vector code 0x000000 program 0x000004 + .cinit romdata 0x000004 program 0x000002 + LOW_INT_VEC code 0x000018 program 0x00004a + .code code 0x000100 program 0x00033c + + + + Program Memory Usage + Start End + --------- --------- + 0x000000 0x000005 + 0x000018 0x000061 + 0x000100 0x00043b + 908 out of 33048 program addresses used, program memory utilization is 2% + + + + Symbols - Sorted by Name + Name Address Location Storage File + --------- --------- --------- --------- --------- + AD_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + FEB 0x0003ee program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000300 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00031a program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER 0x00001e program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER2 0x00002e program static C:\firebee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\firebee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001de program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x0003e6 program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x000414 program static C:\firebee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0003c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x0003fa program static C:\firebee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0002ae program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x00041e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x00040e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x000428 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000432 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS 0x000368 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS2 0x000380 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001a6 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x000346 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000356 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR 0x000256 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR1 0x000268 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR2 0x000274 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RFM 0x000290 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RRFP 0x000280 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC2 0x0002b4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC3 0x0002c6 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC4 0x0002d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC_START 0x00029c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_UNBEK 0x00027c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT1 0x0002e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT2 0x0002ec program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT3 0x0002f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RESETEN 0x000232 program static C:\firebee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x0003f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x000386 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_2 0x0003ac program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x00039c program static C:\firebee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x00020c program static C:\firebee\MLAB\firebee1\firebee1.asm + STUNDEN 0x0003ca program static C:\firebee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x0003d4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TASTE 0x0001e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_END 0x00022c program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_JA 0x0001fa program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000224 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x000206 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000212 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x000218 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00023c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000254 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00024c program static C:\firebee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000312 program static C:\firebee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a0 program static C:\firebee\MLAB\firebee1\firebee1.asm + YEAR 0x000406 program static C:\firebee\MLAB\firebee1\firebee1.asm + + + + Symbols - Sorted by Address + Name Address Location Storage File + --------- --------- --------- --------- --------- + INT_HANDLER 0x00001e program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER2 0x00002e program static C:\firebee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\firebee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\firebee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a0 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001a6 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001de program static C:\firebee\MLAB\firebee1\firebee1.asm + TASTE 0x0001e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_JA 0x0001fa program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x000206 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x00020c program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000212 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x000218 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000224 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_END 0x00022c program static C:\firebee\MLAB\firebee1\firebee1.asm + RESETEN 0x000232 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00023c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00024c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000254 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR 0x000256 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR1 0x000268 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR2 0x000274 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_UNBEK 0x00027c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RRFP 0x000280 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RFM 0x000290 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC_START 0x00029c program static C:\firebee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0002ae program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC2 0x0002b4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC3 0x0002c6 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC4 0x0002d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT1 0x0002e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT2 0x0002ec program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT3 0x0002f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000300 program static C:\firebee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000312 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00031a program static C:\firebee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + AD_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x000346 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000356 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS 0x000368 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS2 0x000380 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x000386 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x00039c program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_2 0x0003ac program static C:\firebee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0003c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + STUNDEN 0x0003ca program static C:\firebee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x0003d4 program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x0003e6 program static C:\firebee\MLAB\firebee1\firebee1.asm + FEB 0x0003ee program static C:\firebee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x0003f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x0003fa program static C:\firebee\MLAB\firebee1\firebee1.asm + YEAR 0x000406 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x00040e program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x000414 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x00041e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x000428 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000432 program static C:\firebee\MLAB\firebee1\firebee1.asm + + diff --git a/MLAB/firebee1/readme.txt b/MLAB/firebee1/readme.txt new file mode 100644 index 0000000..4f5b8f3 --- /dev/null +++ b/MLAB/firebee1/readme.txt @@ -0,0 +1,125 @@ + PS2 -> Atari /Amiga Mouse Adapter + ~~~~~~~~~~~~~~~~~~~~~~~ + + + Version 1.4 July 2010 + + +Due to the short supply of mice for the Atari computers I decided to build an adapter that would allow me to use a serial mouse on my Atari, but even these are getting a bit old now, so I got the soldering iron out again and here's the result. A PS2 Mouse adapter for the Atari. It supports a standard PS2 mouse with 2 or 3 buttons and can also be used with the Microsoft optical IntelliMouse that comes with a USB to PS2 adapter. The middle button on the PS2 mouse is used as a left click and hold function for easy selection. Click the middle button again to release. Now for the bad news, for some reason Microsoft mice don't support the middle button in standard PS2 mode. :-( + +Please don't shout at me all you Atari users but as an added feature if you change a link then the adapter can be used with an Amiga as well. + + +All files, programs etc contained in this archive are copright 2010 by Tom Kirk. Personal use is allowed but any commercial use is not allowed. Please feel free to use my work but don't rip me off. + + + + Files in this archive. + ~~~~~~~~~~~~~~~~~~~~~~ + +readme.txt This text file +circuit.bmp Picture of circuit in bitmap format +PS2Atari_v1_4.hex Object code of the PIC16F84 program in Intel hex +PS2Atari_v1_4.asm Source code of the PIC16F84 program +pcbtop.bmp Top layer of the PCB in bitmap format +pcbbot.bmp Bottom layer of the PCB in bitmap format + + + + Technical Details. + ~~~~~~~~~~~~~~~~~~ + +When the PS2 mouse is moved or a button changes state a packet of data is sent, my circuit decodes this data and then simulates the Atari mouse. + +The circuit consists of a single microcontroller that contains a program to do the conversion. The circuit is shown in the file circuit.bmp + +The microcontroller (PIC) can be either a PIC16C84 or PIC16F84 or PIC16F84A. + +The PIC (IC1) needs to be programmed with the program. +The program is supplied in two forms PS2Atari_v1_4.hex is an object code file in Intel hex and can be read by most programmers capable of programming the PIC + +PS2Atari_v1_4.asm is the source code of the program and can be assembled with the free MPLAB / MPASM software from Microchip if you wish to create your own object file. Note needs "Disable case sensitivity" under build options setting in MPLAB to assemble without errors. + +The PIC should be programmed with oscillator as XT, watchdog disabled, powerup timer enabled and code protection off. (No point code protecting a freely available program.) + +The source code and object code is compatible with all the PIC microcontrollers listed above. + +I've built mine using a printed circuit board but it's small enough to be built using a small piece of stripboard. + +On my PCB I have a 6 pin mini din socket at one end and a 9 pin D type socket at the other. I can then use a standard port extender lead to connect to the Atari. I've found that a 9 pin PC serial extension lead can also be used for this as well if you remove the fastening screws. + +If you decide to build one on a piece of stripboard it will be easier to use cable mounted sockets as PCB types don't fit onto a stripboard. + +Once built the board can be mounted into a small plastic box. + +No special software is required on the Atari and it will work with all software. +Your favourite mouse accelerator program may be used if required. + + + + Parts list. + ~~~~~~~~~~~ + +IC1 PIC16F84A or PIC16F84 or PIC16C84 + +Fi1 4 MHz Ceramic resonator + +R1 10K +R2 10K + +C1 4.7 uF +C2 0.1 uF + +All capacitors should be rated at 16V or more. + +CN1 6 pin mini din PCB mounting socket +CN2 9 Pin D type PCB mounting socket + + +JP1 3 pin header and 2 way link + + +If building on a piece of stripboard I suggest using cable mounting types of connectors and use a small piece of multicore cable between the sockets and the stripboard. You will find the PCB sockets do not fit on a piece of stripboard. + +If you don't need the switchable Atari/Amiga support forget the 3 pin header and just use a wire link instead. + + + + History. + ~~~~~~~~ + +Version 1.4 July 2010 +Unused Pin RA4 now correctly set as an imput. +(Pin is tied to +5V on PCB for easier PCB routing.) +My oversight when transfering from prototype to PCB. +Thanks to Luciano for informing me. + +Version 1.3 Released March 2010 +Corrected a bug in button routine preventing both buttons being active together under certain conditions. +Thanks to Oliver Fleischmann for informing me. +(Can't believe it taken 6 Years for this bug to show itself!!) + +Version 1.2 Released March 2009 +Changed left/right button outputs to fake open collector. +Needed to stop conflits when using a joystick pluged into other port. + +Version 1.1 Released September 2004. +Added support for the Amiga and added the middle button support. + +Version 1.0 Never released. +My original version for the Atari only. + + + + Help. + ~~~~~ + +If you need further information or help then contact me at tgkirk@aol.com + +Please allow a few days for a reply as I have other commitments as well. + + Tom Kirk July 2010 + +P.S. I also have on my web site a Playstation controller to Atari adapter and a PC viewer for Atari format picture files. + + http://www.tgkirk.110mb.com diff --git a/usb/store/config.h b/usb/store/config.h index ce5464f..c929993 100644 --- a/usb/store/config.h +++ b/usb/store/config.h @@ -38,9 +38,9 @@ #define DEBUG_GLOBAL 1 #if DEBUG_GLOBAL /* Define only one of the three debug posibilities below */ -#define DEBUG_TO_FILE 1 +#define DEBUG_TO_FILE 0 #define DEBUG_TO_ARANYM 0 /* NOTE: No arguments are passed to the printf function */ -#define DEBUG_TO_CONSOLE 0 +#define DEBUG_TO_CONSOLE 1 /* Define which local layer you want on */ #define DEBUG_HOST_LAYER 0 diff --git a/usb/store/main.c b/usb/store/main.c index 32d7f4b..46a9e3f 100644 --- a/usb/store/main.c +++ b/usb/store/main.c @@ -96,6 +96,7 @@ printf("idx %d PCI handle: %lx\n", idx -1, handle); /* Galvez: Debug */ int main(int argc, char **argv) { +printf("main()\n"); #ifdef CONFIG_USB_STORAGE long p = 0; int r; diff --git a/usb/store/makefile b/usb/store/makefile index 2164391..624462b 100644 --- a/usb/store/makefile +++ b/usb/store/makefile @@ -39,7 +39,7 @@ PROGRAM = stor_pci.tos endif STACKSIZE = 64k -OPTIMISATION = -O -fomit-frame-pointer +OPTIMISATION = -O2 -fomit-frame-pointer CPU = -m68020-60 LIB = ASFLAGS = $(CPU) diff --git a/usb/store/usb_storage.c b/usb/store/usb_storage.c index e48724e..85e0218 100644 --- a/usb/store/usb_storage.c +++ b/usb/store/usb_storage.c @@ -198,7 +198,7 @@ typedef struct disk_partition { } disk_partition_t; //extern unsigned long swap_long(unsigned long val); -#define le32_to_int(a) swap_32(*(unsigned long *)a) +//#define le32_to_int(a) swap_32(*(unsigned long *)a) int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss); @@ -289,8 +289,8 @@ static int get_partition_info_extended(block_dev_desc_t *dev_desc, int ext_part_ { info->type = (unsigned long)pt->sys_ind; info->blksz = 512; - info->start = ext_part_sector + le32_to_int(pt->start4); - info->size = le32_to_int(pt->size4); + info->start = ext_part_sector + __le32_to_cpu(pt->start4); + info->size = __le32_to_cpu(pt->size4); DEBUG_STORAGE("DOS partition at offset 0x%lx, size 0x%lx, type 0x%x %s\r\n", info->start, info->size, pt->sys_ind, (is_extended(pt->sys_ind) ? " Extd" : "")); @@ -307,7 +307,7 @@ static int get_partition_info_extended(block_dev_desc_t *dev_desc, int ext_part_ { if(is_extended(pt->sys_ind)) { - int lba_start = le32_to_int(pt->start4) + relative; + int lba_start = __le32_to_cpu(pt->start4) + relative; usb_free(buffer); return get_partition_info_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, part_num, which_part, info); }

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z)MC|UW_73TtJ;-eDsGQLW%_vSZ?`ghz$nXuLtuhof`Ng-f_=wG5bQh`Pv*Xa0LzSl z2E+Te`hSD;|E-0!i@AxpxsipFrLhq!rx7cg5i1Lmi;0D@JQVc*?g9TdrT + + ; define config bits + __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _XT_OSC + + ;4 MHz Clock + +;************************ Input output usage ******************** + +; RA0 Atari / Amiga select i/p +; RA1 PS2 mouse data +; RA2 PS2 mouse clock +; RA3 Not used +; RA4 Not used + +; RB0 Atari XA / Amiga XA o/p +; RB1 Atari XB / Amiga YB o/p +; RB2 Atari YA / Amiga YA o/p +; RB3 Atari YB / Amiga XB o/p +; RB4 Left button o/p +; RB5 Right button o/p +; RB6 Not used +; RB7 Not used + +;******************************************************************* + + +;********** I/O port equates ************** + + +ps2data equ 1 ;ps2 mouse data signal +ps2clk equ 2 ;ps2 mouse clock signal + + +;********** User register equates ********* + +temp equ 0ch ;Temporary storage +byte1 equ 0dh ;Byte 1 store +byte2 equ 0eh ;Byte 2 store +byte3 equ 0fh ;Byte 3 store +xinc equ 010h ;last x increment read +yinc equ 011h ;last y increment read +xlow equ 012h ;low byte of 16 bit x counter +xhigh equ 013h ;high byte of 16 bit x counter +ylow equ 014h ;low byte of 16 bit y counter +yhigh equ 015h ;high byte of 16 bit y counter +xpat equ 016h ;x pattern position +ypat equ 017h ;y pattern position +bcnt equ 018h ;bit counter +brec equ 019h ;byte received +timer equ 01ah ;timer counter +parity equ 01bh ;parity store +flag equ 01ch ;flag bits (bit 0 = ack error flag) + ; (bit 1 = parity error flag) + ; (bit 2 = middle button pressed flag) + ; (bit 3 = middle state flag) + ; (bit 4 = left button flag) + +;***************************************************************************************** + +;***** initialise program ******* + +reset clrwdt + bcf status,rp0 ;set page0 + clrf intcon ;disable interupts + bsf status,rp0 + movlw 084h ;set tmr0 to int clk,prescale/32 + movwf option_reg + bcf status,rp0 + clrf porta ;all porta outputs will be low when enabled + movlw 0h ;set mouse buttons and x y start levels + movwf portb + bsf status,rp0 + movlw 017h ;set porta bit 3 as an unused output + movwf trisa + movlw 030h ;set portb bit 4 and 5 as inputs (left/right button o/ps open collector) + movwf trisb + bcf status,rp0 + + clrf byte1 ;set start up values + clrf byte2 + clrf byte3 + clrf xinc + clrf yinc + clrf xlow + clrf xhigh + clrf ylow + clrf yhigh + clrf xpat + clrf ypat + clrf flag + + +;***************** set up ps2 mouse ********************* + + +start call ps2read ;read power up self test report + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0aah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read power up pc mouse id + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0h ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + +restart movlw 0ffh ;send reset pc mouse command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read self test report + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0aah ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + call ps2read ;read pc mouse id + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0h ;correct ? + subwf brec,w + btfss status,z + goto restart ;no so jump + + movlw 0f4h ;send enable reporting command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + + movlw 0f3h ;send set sample rate command + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + + movlw 028h ;send sample rate (40) + call ps2wri + btfsc flag,0 ;ack bit? + goto restart ;no so jump + + call ps2read ;ack returned + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movlw 0fah ;correct ? + subwf brec,w + btfss status,z + goto restart + +;******************* Main program loop **************************** + +main call ps2read ;read 3 byte pc mouse packet + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte1 + call ps2read + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte2 + call ps2read + btfsc flag,1 ;parity error? + goto restart ;yes so jump + movf brec,w + movwf byte3 + +;adjust the 16 bit x counter + + clrf temp ;use temp as high byte + btfsc byte1,4 ;extend sign bit into high byte + decf temp,f + + movf byte2,w ;add low bytes + addwf xlow,f + btfsc status,c ;add carry to high + incf xhigh,f + movf temp,w ;add high bytes + addwf xhigh,f + +;adjust the 16 bit y counter + + clrf temp ;use temp as high byte + btfsc byte1,5 ;extend sign bit into high byte + decf temp,f + + movf byte3,w ;add low bytes + addwf ylow,f + btfsc status,c ;add carry to high + incf yhigh,f + movf temp,w ;add high bytes + addwf yhigh,f + +;left button + + btfss byte1,0 ;is the left pc mouse button pressed + goto lbutt ;no so jump + bsf flag,4 ;set left button flag + goto nbutt +lbutt bcf flag,4 ;reset left button flag + +;right button + +nbutt btfss byte1,1 ;is the right pc mouse button pressed + goto rbutt ;no so jump + bcf portb,5 ;set right button as pressed + bsf status,rp0 ;by setting pin as a low output + bcf trisb,5 + bcf status,rp0 + goto mbut +rbutt bsf status,rp0 ;set right button as not pressed + bsf trisb,5 ;by setting pin as an input + bcf status,rp0 + +;middle button + +mbut btfss byte1,2 ;check if middle button pressed + goto mbutt ;jump if not + btfsc flag,2 ;check middle button pressed flag + goto mbex ;set so jump + movlw 08h ;toggle middle state flag + xorwf flag,f + bsf flag,2 ;set middle button pressed flag + goto mbex + +mbutt btfss flag,2 + goto mbex + bcf flag,2 ;reset middle button pressed flag +mbex + + btfsc flag,3 ;check middle state flag + goto setlb ;jump if set + btfsc flag,4 ;check left button flag + goto setlb ;jump if set + bsf status,rp0 ;no flags set so set left buuton not pressed + bsf trisb,4 ;by setting pin as an input + bcf status,rp0 + goto main +setlb bcf portb,4 ;set left button pressed + bsf status,rp0 ;by setting pin as a low output + bcf trisb,4 + bcf status,rp0 + goto main + + +;***************************** Subs ***************************************** + +;***** Read a byte from the ps2 mouse ****** + +ps2read btfss porta,ps2data ;data low ? + goto ps2r1 ;yes so start reading data + call trans ;no so do emulated mouse move + clrf tmr0 ;clear rtcc before delay + +oned btfss porta,ps2data ;data low ? + goto ps2r1 ;yes so start reading data + movlw 0dh ;delay between emulated mouse moves + subwf tmr0,w + btfss status,z + goto oned ;not done so jump + goto ps2read ;check again + +ps2r1 call wlow ;wait until clock goes low for start bit + + call whigh ;wait until clock is high + + movlw 08h ;read 8 data bits + movwf bcnt + clrf parity ;clear parity counter + +ps2r2 call wlow ;wait until clock is low + bcf status,c ;clear carry flag + btfss porta,ps2data ;data bit set ? + goto ps2r3 ;no so jump + incf parity,f ;yes so inc the parity counter + bsf status,c ;set carry bit +ps2r3 rrf brec,f ;shift carry into destination + + call whigh ;wait until clock is high + + decfsz bcnt,f ;finished the 8 bits? + goto ps2r2 ;no so do again + + call wlow ;for the parity bit + btfsc porta,ps2data ;parity bit set? + incf parity,f ;yes so inc the parity counter + bcf flag,1 ;clear flag (no error) + btfss parity,0 ;check calculated parity + bsf flag,1 ;set flag (parity error!) + call whigh + + call wlow ;for the stop bit + call whigh + + return ;and exit + +;***** Write a byte to the ps2 mouse ****** + +ps2wri movwf brec ;speed not important at this point so + movwf temp ;calculate parity seperate for sake of + movlw 08h ;clarity + movwf bcnt + clrf parity +ps2w1 rrf temp,f ;shift bit into carry + movlw 01h ;preset for bit set + btfss status,c ;test carry + clrw ;bit zero so no addition + addwf parity,f ;update parity + decfsz bcnt,f ;any more bits to do? + goto ps2w1 ;yes so jump + comf parity,f ;only intrested in bit 0. + ;parity bit is complement of bit 0 + + movlw 08h ;bit count to 8 + movwf bcnt + + call clkl ;set clock low + + movlw 021h ;wait 100 uS + movwf temp +ps2ww decfsz temp,f + goto ps2ww + + call datl ;set data low + nop ;wait 5 uS + nop + nop + nop + nop + call clkh ;set clock high + +ps2w2 call wlow ;wait for clock to go low + rrf brec,f ;rotate bit into carry for testing + btfss status,c + goto ps2w3 ;jump if bit is low + call dath ;set data high + goto ps2w4 +ps2w3 call datl ;set data low +ps2w4 call whigh ;wait for clock to go high + + decfsz bcnt,f ;any more bits to send? + goto ps2w2 ;yes so jump + + call wlow ;wait for clock to go low + btfss parity,0 ;send parity bit + goto ps2w5 + call dath + goto ps2w6 +ps2w5 call datl +ps2w6 call whigh + + call wlow ;send stop bit + call dath + call whigh + + call wlow ;read ack from mouse + bcf flag,0 + btfsc porta,ps2data + bsf flag,0 + call whigh + + return + + +;******* wait for ps2 clock to go low ********** + +wlow btfsc porta,ps2clk + goto wlow + return + + +;******* wait for ps2 clock to go high ********** + +whigh btfss porta,ps2clk + goto whigh + return + + +;******* set ps2 clock low ********************* + +clkl bsf status,rp0 + bcf trisa,ps2clk + bcf status,rp0 + return + + +;******* set ps2 clock high ******************** + +clkh bsf status,rp0 + bsf trisa,ps2clk + bcf status,rp0 + return + + +;******* set ps2 data low ********************* + +datl bsf status,rp0 + bcf trisa,ps2data + bcf status,rp0 + return + + +;******* set ps2 data high ********************* + +dath bsf status,rp0 + bsf trisa,ps2data + bcf status,rp0 + return + + + +;********* emulate mouse move *************************** + +;move the emulated mouse by one step in the x direction if needed + +trans movf xlow,w ;is the x counter zero? + iorwf xhigh,w + btfsc status,z + goto ymove ;no so jump to y direction + + btfsc xhigh,7 ;is the x counter positive or negative? + goto xneg ;jump if negative + + incf xpat,f ;increment the pattern list position + movlw 04h ;test if end of pattern list + subwf xpat,w + btfsc status,z + clrf xpat ;end of pattern list so reset + movlw 0ffh ;subtract 1 from the 16 bit counter by adding ffffh + addwf xlow,f + btfsc status,c ;add carry to high byte + incf xhigh,f + addwf xhigh,f + goto ymove ;exit to y direction + +xneg decf xpat,f ;decrement the pattern list position + movlw 0ffh ;test if end of pattern list + subwf xpat,w + btfss status,z + goto xno + movlw 03h ;end of pattern list so reset + movwf xpat +xno movlw 01h ;add 1 to the 16 bit counter + addwf xlow,f + btfsc status,c ;add carry to high byte + incf xhigh,f + +;move the emulated mouse by one step in the y direction if needed + +ymove movf ylow,w ;is the y counter zero? + iorwf yhigh,w + btfsc status,z + goto out ;no so jump to output pattern + + btfsc yhigh,7 ;is the y counter positive or negative? + goto yneg ;jump if negative + + incf ypat,f ;increment the pattern list position + movlw 04h ;test if end of pattern list + subwf ypat,w + btfsc status,z + clrf ypat ;end of pattern list so reset + movlw 0ffh ;subtract 1 from the 16 bit counter by adding ffffh + addwf ylow,f + btfsc status,c ;add carry to high byte + incf yhigh,f + addwf yhigh,f + goto out ;exit to output pattern + +yneg decf ypat,f ;decrement the pattern list position + movlw 0ffh ;test if end of pattern list + subwf ypat,w + btfss status,z + goto yno + movlw 03h ;end of pattern list so reset + movwf ypat +yno movlw 01h ;add 1 to the 16 bit counter + addwf ylow,f + btfsc status,c ;add carry to high byte + incf yhigh,f + +;output new x and y patterns + +out btfsc porta,0 ;test if set for atari + goto amiga + + movf xpat,w ;get the x pattern bits + bsf pclath,1 ;set page 2 + call pattx + movwf temp ;store the pattern in temp + movf ypat,w ;get the y pattern bits + call patty + clrf pclath ;set page 0 + iorwf temp,f ;store the pattern in temp + + goto outpat + +amiga movf xpat,w ;get the x pattern bits + bsf pclath,1 ;set page 2 + call apatx + movwf temp ;store the pattern in temp + movf ypat,w ;get the y pattern bits + call apaty + clrf pclath ;set page 0 + iorwf temp,f ;store the pattern in temp + +outpat movf temp,w ;get patterns + andlw 0fh ;ensure high nibble stays zero + movwf portb ;ouput patterns + + + return + + +;*************** pattern lists ************** + + org 0200h + +;atari patterns +pattx addwf pcl,f + retlw 0 + retlw 1 + retlw 3 + retlw 2 + +patty addwf pcl,f + retlw 0 + retlw 4 + retlw 0ch + retlw 8 + +;amiga patterns +apatx addwf pcl,f + retlw 0 + retlw 1 + retlw 9 + retlw 8 + +apaty addwf pcl,f + retlw 0 + retlw 4 + retlw 6 + retlw 2 + +;******************************************************************************* + + END + + diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/Thumbs.db b/BaS_codewarrior/FireBee/MLAB/firebee1/Thumbs.db new file mode 100644 index 0000000000000000000000000000000000000000..5c84dfb6d19a66e008ecbeb8e2f2638efa71ba6d GIT binary patch literal 22528 zcmeFYcUV+UmoB;ykeqXBvY_OglSq;u5|k_;B9dvz4Kz9DB%mNk1SE@OXmS?GNpe&& zbQ4=>n$ynAH#6t^=FBtqKIi^%&YkM#-Jy2vu38n=s#^8#@iB_Ef*Qtk;O~MWfDNE; z34pu*E*=YW{RjUP$N}IE=Hkyi`u6trpCbVPbNS!l|DYPU!Ibq+`~AV6fQxC!KW&bO z0X_x<7!YDWgaI)IBp8rlK!yRP3jh=tP+~xZ0W}6R7|>!shXFkXfBu&db7sPT83Ps! zKp3!Mz=i=k1{@f0V!(v~HwO1G;K6_wgZmgfz~FD?`=>(w_u+qA4Hy7m%+C|k7HWVi z=IjpmVru)p9%upFe;xCGbiscX)=a7lEmViG{d{#){YI6naHVExfUf2)vxNbny-;9%ms{&X%(__zEeFu95TQ|{83 z{Dc89%(V>$w*PeZ&#C|Mh{^w7^ZrwYe@yX@F$|cf$UmL_e^dCI?ElsL|9!Uq{@wq+ z{{LSM{L#_a7`XmRe}praXd^kz&HjBK`S0uhdu!lt?Qiif`mmbZ^~dzG9rf*x+ckjv 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zfp@;P`Nm`V$>60|*^}}!EW`PfKlgxjL_+-rPwn2y;?n)2O}r=u9>$}N>#EP`Cxh$M zpRvEAc|-V9`_i6Sx^MMQ8IPnLz?1WWx9pDn6nS`i8qbH&p%XG*KfglTc^g0J{p9J= z>wA=k7a0i_W{l@)N0c|{!}#qjz0Uf34W4dVuwO#$arzGM&>oZWY+J|1lK4f_!cFj( z&dJ&A@?NV6j{NdG!u3PuP)73>@(NV-;Fr`7Zq%VYV{#3ir(J{BN{k=8X_dl@sXN?6 zf8mnRU%&5&8WXJJJo>TqNIU+pO%0-Jgxt{wCMcH785lX SQ|X7!8>9YTivKJ|;J*Q^($^~h literal 0 HcmV?d00001 diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.asm b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.asm new file mode 100644 index 0000000..cc1d11a --- /dev/null +++ b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.asm @@ -0,0 +1,845 @@ +;********************************************************** +;* firebee1 PIC18F4321 MAIN FILE +;********************************************************** +;* CREATED BY FREDI ASCHWANDEN +;* DATE 22.9.2009 +;********************************************************** + list PE=18f4520 ;EXTENDED INSTRUCTION SET + include "P18f4520.inc" +;------------------------ Equates --------------------------; +;Register addresses +;BANK 0 +SECS equ 0x00 +SECS_ALARM EQU 0x01 +MINS equ 0x02 +MINS_ALRAM EQU 0x03 +HOURS equ 0x04 +HOURS_ALARM EQU 0x05 +DAY_OF_WEEK EQU 0x06 +DAYS EQU 0x07 +MONTHS EQU 0x08 +YEARS EQU 0x09 ;offset vom 1968 +REGA EQU 0x0A +REGB EQU 0x0B +REGC EQU 0x0C +REGD EQU 0x0D +RTC_RAM EQU 0x0E ; bis 0x3F +free equ 0x40 +TICKS equ 0x41 ;125MS +TASTE_ON_TIME EQU 0x42 +TASTE_OFF_TIME EQU 0x43 +POWER_ON_TIME EQU 0x44 +AD_KANAL EQU 0x45 +U_ERR EQU 0x46 ;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WARTEN AUF GELADEN +U_ERR_TIME EQU 0x47 ;ZEIT SEIT SPANNUNGSFEHLER +U_POWER_IN EQU 0x48 ;SPANNUNG POWER IN 1V CA. 6E +RX_B EQU 0x49 ;RECEIVED BYT +RX_STATUS EQU 0x4A ;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x82=EMPFANGE 64BYT FROM RTC +TX_STATUS EQU 0x4B ;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM RTC +GO_SUB EQU 0x4C ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN +GO_INT EQU 0x4D ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN +EAPIR1 EQU 0x4E ;INTERRUPT ACTIV UND ENABLE +EAPIR2 EQU 0x4F ;INTERRUPT ACTIV UND ENABLE +;BANK 1 AB 0x100 +RX_BUFFER EQU 0x100 ;0x80 BYT BUFFER BIS 0x17F BANK +TX_BUFFER EQU 0x180 ;0X80 BYT BUFFER BIS 0x1FF BANK + +;-------------------------------------------------------------- +SEND_RTC_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +RESET_ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +RESET_OFF_TIME EQU .4 ;0.5 SEC (EINHEIT IST EIN TICK = 128MS +OFF_TIME EQU .20 ;2.5 SEC (EINHEIT IST EIN TICK = 128MS +ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS +TIMER_HB EQU .240 ;256- (32768Hz PRO 1/8SEC = 4096TICKS/256) => 256-16=240 (resp 256-16/4 (wenn osco) = 252) +TIME_MAX EQU .160 ;MAXIMALTIME +U_ERR_PW_AUS EQU .5 ;5 SEC +;SERIEL +SYNC1 EQU 0FFh +SYNC1_DATA EQU 'A'; +SYNC2 EQU 0FEh +SYNC2_DATA EQU 'C'; +SYNC3 EQU 0FDh +SYNC3_DATA EQU 'P'; +SYNC4 EQU 0FCh +SYNC4_DATA EQU 'F'; +REQ_RTCD_FROM_PIC EQU 01h ;RTC AND NVRAM DATEN VOM PIC ANFORDERN +RTCD_FROM_PIC EQU 81h ;RTC AND NVRAM DATEN HEADER UND STATUS +REQ_RTCD_FROM_MCF EQU 02h ;RTC AND NVRAM DATEN VOM MCF ANFORDERN +RTCD_FROM_MCF EQU 82h ;RTC AND NVRAM DATEN HEADER UND STATUS +U_MIN_TO_MCF EQU 03h ;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR +EXT_SUB_GO EQU 04h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU AKTIVIEREN +EXT_SUB_STOP EQU 05h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU STOPPEN +CLK_SLEEP EQU B'00010010' ;125kHz intern, SLEEP MODE +CLK_ACTIV EQU B'01110010' ;inTernal CLK=8MHz, SLEEP MODE, SLEEP MODE +EXT_CODE EQU 0xFB ;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS AUSFÜHREN (FireBee!) +EXTERN_INT_ADR EQU 0x2000 ;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS AUSFÜHRBAR +EXTERN_INTERRUPTS EQU 0x2002 ;STARTPUNKT EXTERNE SUBROUTINES +EXTERN_SUB_ADR EQU 0x2010 ;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES AUSFÜHRBAR +EXTERN_SUBROUTINES EQU 0x2012 ;STARTPUNKT EXTERNE SUBROUTINES +REQ_BLOCK EQU 0xA0 ;BLOCK DATEN LESEN -> CODE UND 3 BYTS ADRESSE = TOTAL 4 BYTES +READ_BLOCK EQU 0xA1 ;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES +WRITE_BLOCK EQU 0xA2 ;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES +PRG_OK_PIC EQU 0x22 ;PROGRAMMIERUNG BLOCK FERTIG +;**********************************************************************************************""""""""""""" +; Start at the reset vector +Reset_Vector code 0x000 + BRA KALT_START +;-------------------------------------------------------------- +HIGH_INT_VEC code 0x0008 + GOTO 0x18 + +LOW_INT_VEC code 0x0018 +INT_HANDLER + CLRF BSR ;IMMER ACCESS BANK +;SETZEN GRUPPE 1 + MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN + MOVF PIR1,0 ;MASKE + ANDWF EAPIR1 ;ACTIVE SETZEN + BTFSC EAPIR1,TMR1IF ;uhr interrupt? + BRA RTC_ISR ;ja-> + BTFSC EAPIR1,ADIF ;AD INTERRUTP? + BRA AD_ISR ;JA-> + BTFSC EAPIR1,TXIF ;seriell TX? + BRA TX_ISR ;JA-> + BTFSC EAPIR1,RCIF ;seriell RX? + BRA RX_ISR ;JA-> + +;SETZEN GRUPPE 2 + MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN + MOVF PIR2,0 ;MASKE + ANDWF EAPIR2 ;ACTIVE SETZEN + + BTFSC EAPIR2,HLVDIF ;UNDER/OVERVOLTAGE DETECT + BRA HLVD_ISR ;JA-> + RETFIE + +;TESTEN UND SETZEN GRUPPE 1 + MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN + MOVF PIR1,0 ;MASKE + ANDWF EAPIR1 ;ACTIVE SETZEN + TSTFSZ EAPIR1 + BRA INT_HANDLER +;TESTEN UND SETZEN GRUPPE 2 + MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN + MOVF PIR2,0 ;MASKE + ANDWF EAPIR2 ;ACTIVE SETZEN + TSTFSZ EAPIR2 + BRA INT_HANDLER + + MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? + CPFSEQ GO_INT ;SKIP WENN JA + RETFIE + GOTO EXTERN_INTERRUPTS ;REGISTER SICHERN UND STARTEN +;**********************************************************************************************""""""""""""" + ; Start application beyond vector area + CODE 0x0100 +KALT_START +;RESET MODE + CLRF BSR ;BANK 0 +;ALLE INT AUS UND RÜCKSETZEN + CLRF INTCON ;alle INTERRUPT AUS + CLRF RCON ;INT PRIORITY AUS + CLRF PIE1 ;MASK DISABLE + CLRF PIE2 + CLRF PIR1 ;INT ACT AUS + CLRF PIR2 + CLRF IPR1 ;LOW PRIORITY + CLRF IPR2 + ; clock +; MOVLW B'01000000' ;32MHZ +; MOVWF OSCTUNE + CLRF OSCTUNE +;CLOCK + MOVLW CLK_ACTIV + MOVWF OSCCON + ; div init +;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3/2 **1:1V25 **0:POWER_IN/11 + CLRF PORTA ;#master(7)=0, REST=0 + MOVLW B'11111111' ;DIRECTION: alles auf Input + MOVWF TRISA +;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PORT PIN6 **0: GAME PORT PIN5 + CLRF PORTB ;ALLES AUF 0 + MOVWF TRISB +;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN13 **1+0: OCS 32K768Hz + CLRF PORTC + MOVWF TRISC +;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1:TASTER **0:POWER ON/OFF (0=ON) +; SET TASTE UND POWER + CLRF PORTD ;ALLES AUF 0 + MOVWF TRISD ;ALLES AUF INPUT +;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON) + MOVLW B'00000001' ;LED OFF + CLRF PORTE ;ALLES AUF 0 + MOVWF TRISE ;ALLES AUF INPUT +;-------------------------- +; set OVERvoltage detekt + MOVLW B'10011011' ;INT WENN ÜBER 3.9V + MOVWF HLVDCON + MOVLW B'00000011' ;ERRORS ON, WAIT AUF LADEN + MOVWF U_ERR + MOVLW .20 ;SEIT 20SEC ERROR + MOVWF U_ERR_TIME ;SETZEN + BSF PIE2,HLVDIE ;Enable interrupt +;INTIALISIERUNGSPROGAMME + CALL LADESTROM ;LADESTROM EINSTELLEN +;UHR initialisieren + MOVLW TIMER_HB ;Preload TMR1 register + MOVWF TMR1H ; + CLRF TMR1L ;=0 + MOVLW B'00001111' ; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE + MOVWF T1CON ; SET + CLRF TICKS ; 1/8 sec register + CLRF SECS ; Initialize timekeeping registers + CLRF MINS ; + MOVLW .12 + MOVWF HOURS + MOVLW .1 + MOVWF DAY_OF_WEEK + MOVLW .1 + MOVWF DAYS + MOVLW .8 + MOVWF MONTHS + MOVLW .42 + MOVWF YEARS ;MONTAG 19.7.2010 12:00:00 (JAHR-1968) + CLRF TASTE_ON_TIME + CLRF TASTE_OFF_TIME + CLRF POWER_ON_TIME + BSF PIE1,TMR1IE ;Enable Timer1 interrupt +;AD WANDLER INITIALISIEREN + CLRF AD_KANAL ;BEI 0 BEGINNEN + CLRF ADCON0 ;AD MOUDUL AUS + MOVLW B'00001001' ;VREF=VDD,ANALOG INPUT AN0-AN5 + MOVWF ADCON1 + MOVLW B'00000000' ;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2 + MOVWF ADCON2 +; BSF PIE1,ADIE ;INTERRUPT ENABLE + CLRF U_POWER_IN ;WERT AUF 0 VOLT +; seriell initialisieren + CLRF SPBRGH + MOVLW .16 + MOVWF SPBRG ;BAUDE RATE = 115K + MOVLW B'00000100' ;TX AUS, ASYNC HIGH SPEED + MOVWF TXSTA + MOVLW B'10010000' ;SERIEL EIN,RX EIN, + MOVWF RCSTA + MOVLW B'00001000' ;16BIT BRG, RISING EDGE INTERRUPT + MOVWF BAUDCON ;SETZEN +;EXTERNER SUBROUTINES + CLRF GO_SUB +; interrupts + CLRF INTCON3 ;EXTER INTERRUPT AUS, low priority + MOVLW B'11110000' ;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BPIP Low priority + MOVWF INTCON2 + MOVLW B'11000000' ;global on, PERIPHERAL INT on + MOVWF INTCON +;CLOCK + MOVLW CLK_SLEEP ;GEHT JETZT IN SLEEP MODE + MOVWF OSCCON +;------------------------------------------------------------------------- +;---------------------------- MAIN LOOP ------------------------------------------------- +;------------------------------------------------------------------------- +MAIN + MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? + CPFSEQ GO_SUB ;SKIP WENN JA + BRA WARTEN ;SONST WARTEN + CALL MAIN2,1 ;REGISTER SICHERN UND STARTEN +WARTEN + BTFSC TRISD,RD0 ;SKIP IF POWER ON + SLEEP ;SLEPP BIS ZUM NÄCHSTEN INTERRUPT + BRA MAIN +MAIN2 + CALL EXTERN_SUBROUTINES ;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONST UNGÜLTIG + RETURN 1 ;RETURN MIT REGISTER ZURÜCK +;**********************************************************************************************""""""""""""" +;--------------------------- subroutines ------------------------------------------------- +;**********************************************************************************************""""""""""""" +;POWER ON/OFF +POWER_EIN +;CLOCK + MOVLW CLK_ACTIV + MOVWF OSCCON + + BCF TRISA,RA7 ;CLOCK EINSCHALTEN + BCF TRISD,RD7 ;#RSTI AKTIVIEREN = LOW + BCF TRISB,RB4 ;PIC_INT AKTIVIEREN + BCF TRISD,RD0 ;POWER ON + BRA LS_ON_POWER ;LADESTROM EINSTELLEN +POWER_AUS +;CLOCK + MOVLW CLK_SLEEP + MOVWF OSCCON + + BSF TRISD,RD0 ;POWER OFF + BSF TRISD,RD7 ;#RSTI DEAKTIVIEREN + BSF TRISB,RB4 ;PIC INT DEAKTIVIEREN + BSF TRISA,RA7 ;CLOCK DEAKTIVIEREN + CLRF POWER_ON_TIME ;RÜCKSETZEN + BRA LS_OFF_POWER ;LADESTROM EINSTELLEN +;LADESTROM EINSTELLEN ---------------------------- +LADESTROM + BTFSC TRISD,RD0 ; ONPOWER? + BRA LS_OFF_POWER ; NEIN-> +LS_ON_POWER ;GROSSER LADESTROM 5A + BCF TRISA,RA4 ;10K ON + RETURN +LS_OFF_POWER ;KLEINER LADESTROM_MIN 1.85A + BSF TRISA,RA4 ;10K OFF + RETURN +;--------------------------------------------------- +;SERIELL AUS/EIN +SERIAL_OFF + BCF TXSTA,TXEN ;TX AUS + BCF PIE1,RCIE ;DISABLE RX interrupt + BCF PIR1,RCIF ;CLEAR RX interrupt + BCF PIE1,TXIE ;DISABLE TX interrupt + BCF PIR1,TXIF ;CLEAR TX interrupt + RETURN +SERIAL_ON + BTFSC TXSTA,TXEN ;SCHON EIN? + RETURN ;JA-> + BSF TXSTA,TXEN ;TX EIN + MOVLW SYNC1 + MOVWF RX_STATUS ;AUF SYNC WARTEN + CLRF TX_STATUS + MOVFF RCREG,RX_B ;RCREG LEEREN + MOVFF RCREG,RX_B ;RCREG LEEREN + BCF PIR1,TXIF ;CLEAR TX interrupt + BCF PIR1,RCIF ;INTERRUPT RX FLAG LÖSCHEN + BSF PIE1,RCIE ;ENABLE RX interrupt + NOP + RETURN +;--------------------------------------------------------------------- +; TASTENDRUCK +TASTE + BTFSS PORTD,RD1 ;TASTE GEDRÜCKT? + BRA TG_JA ;->JA +;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN + CLRF TASTE_ON_TIME ;RÜCKSETZEN + + MOVLW TIME_MAX ;MAX + CPFSGT TASTE_OFF_TIME ;LÄNGER? + INCF TASTE_OFF_TIME ;NEIN ERHÖHEN + + MOVLW RESET_OFF_TIME ;2SEC + CPFSGT POWER_ON_TIME ;LÄNGER? + RETURN ;NEIN-> +;RESET AUFHEBEN + BSF TRISD,RD7 ;JA -> #RSTI DEAKTIVIEREN =HIGH + CALL SERIAL_ON ;SERIELL EINSCHALTEN + RETURN +;TASTE GEDRÜCKT +TG_JA + MOVLW OFF_TIME+1 + CPFSLT TASTE_ON_TIME ;KÜRZER ALS ONTIME+1 + RETURN ;NEIN->FERTIG + BTFSC TRISD,RD0 ;ONPOWER? + BRA TG_OFF_POWER ;NEIN-> +TG_ON_POWER + MOVLW SEND_RTC_TIME ;ZEIT FÜR RTC REQ FROM MCF HOLEN? + CPFSEQ TASTE_ON_TIME ;TEST + BRA TG_ON_POWER2 ;NEIN-> +SEND_RTC_REG + MOVLW REQ_RTCD_FROM_MCF + MOVWF TXREG ;SENDEN + BRA TG_END; +TG_ON_POWER2 + MOVLW RESET_ON_TIME ; + CPFSLT TASTE_ON_TIME ;KÜRZER? + BRA RESETEN +TG_ON_POWER3 + MOVLW OFF_TIME + CPFSLT TASTE_ON_TIME ;KÜRZER ON/OFF TIME? + CALL POWER_AUS ;NEIN->POWER OFF + BRA TG_END +TG_OFF_POWER + MOVLW ON_TIME + CPFSLT TASTE_ON_TIME ;KÜRZER ALS ON/OFF TIME? + CALL POWER_EIN ;NEIN->POWER ON +TG_END + CLRF TASTE_OFF_TIME ;RÜCKSETZEN + INCF TASTE_ON_TIME ;ERHÖHEN + RETURN +RESETEN + BCF TRISD,RD7 ;NEIN-> #RSTI AKTIVIEREN =LOW -->>>RESET + CALL SERIAL_OFF ;SERIELL DEAKTIVIEREN + BRA TG_ON_POWER3 +;**********************************************************************************************""""""""""""" +;----------------------------------------- INTERRUPTS +;**********************************************************************************************""""""""""""" +; SERIELL INTERRUPTS +;**********************************************************************************************""""""""""""" +;TX +TX_ISR ;TRANSMIT + MOVLW RTCD_FROM_PIC ;RTC DATEN SENDEN? + CPFSEQ TX_STATUS ;SKIP JA + BRA TX_ISR1 ;NEIN-> + MOVFF POSTINC0,TXREG ;BYT SENDEN + MOVLW 0x3F ;SCHON LETZTES BYTS? + CPFSGT FSR0L ;SKIP WENN FERTIG + RETFIE ;NEIN WEITERE SENDEN +TX_ISR_FERTIG + CLRF TX_STATUS + BCF PIE1,TXIE ;SONST DISABLE interrupt + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + RETFIE +TX_ISR1 + MOVLW READ_BLOCK ;READ BLOCK? + CPFSEQ TX_STATUS ;SKIP JA + BRA TX_ISR2 ;NEIN-> + MOVFF POSTINC0,TXREG ;BYT SENDEN + MOVLW 0xC3 ;SCHON LETZTES BYTS? + CPFSGT FSR0L ;SKIP WENN FERTIG + RETFIE ;NEIN WEITERE SENDEN +TX_ISR2 + BRA TX_ISR_FERTIG +;**********************************************************************************************""""""""""""" +;RX +RX_ISR ; BYT RECEIVED + MOVFF RCREG,RX_B ; BYT HOLEN +; MOVFF RX_B,TXREG ; ECHO + MOVLW SYNC4 ;IM SYNC STATUS? + CPFSLT RX_STATUS ;SKIP WENN NEIN + BRA RX_SYNC_START ;JA -> ZUERST SYNC EMPFANGEN +;--------------- + MOVLW RTCD_FROM_MCF ; DATEN VOM MCF CODE 0x82? + CPFSEQ RX_STATUS ; WENN JA-> SKIP + BRA RX_ISR1 ; NEIN-> +;64 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x3F ;64 BYT ÜBERTRAGEN? + CPFSLT FSR1L ;NEIN ->SKIP + CLRF RX_STATUS ;JA FERTIG + RETFIE +;------------------------------------------------------------------------------------- +RX_ISR1 + CPFSEQ RX_B ;BLOCK HEADER 0X82? + BRA RX_ISR2 ;NEIN-> + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,.0 ;BYT COUNTER AUF O + RETFIE +RX_ISR2 + MOVLW REQ_RTCD_FROM_PIC ;DATEN SENDEN? + CPFSEQ RX_B ;SKIP WENN JA + BRA RX_ISR3 ;SONST NEXT +;BLOCK HEADER UND 64 BYT SENDEN ----------------------------------------- + LFSR 0,.0 + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + BSF PIE1,TXIE ;Enable interrupt + MOVLW RTCD_FROM_PIC + MOVWF TX_STATUS ;STATUS SETZEN + MOVWF TXREG ;BLOCK HEADER = 0X81 + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR3 + MOVLW EXT_SUB_GO ;EXT SUB FREIGEBEN? + CPFSEQ RX_B + BRA RX_ISR4 ;NEIN-> +;EXT SUBS FREIGEBEN -------------------------------------------------------------- + MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 + MOVWF TBLPTRU + MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 + MOVWF TBLPTRH + MOVLW (EXTERN_INT_ADR & 0x0000FF) + MOVWF TBLPTRL ;ADRESSE SETZEN + TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) + MOVFF TABLAT,GO_INT ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK + MOVLW (EXTERN_SUB_ADR & 0xFF0000)>>16 + MOVWF TBLPTRU + MOVLW (EXTERN_SUB_ADR & 0x00FF00)>>8 + MOVWF TBLPTRH + MOVLW (EXTERN_SUB_ADR & 0x0000FF) + MOVWF TBLPTRL ;ADRESSE SETZEN + TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) + MOVFF TABLAT,GO_SUB ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR4 + MOVLW EXT_SUB_STOP ;EXT SUB STOPPEN? + CPFSEQ RX_B + BRA RX_ISR5 ;NEIN-> +;EXT SUBS STOPPEN -------------------------------------------------------------- + CLRF GO_INT ;STOPPEN + CLRF GO_SUB ;STOPPEN + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR5 + MOVLW REQ_BLOCK ;REQ BLOCK? + CPFSEQ RX_B + BRA RX_ISR6 ;NEIN-> +;REQ BLOCK ---------------------------------------------------------------- + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,TX_BUFFER ;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN + RETFIE +RX_ISR6 + CPFSEQ RX_STATUS ;REQ BLOCK ADRESSE EMPFANGFEN? + BRA RX_ISR7 ;NEIN-> +;3 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x82 ;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 + CPFSLT FSR1L ;NEIN ->SKIP + BRA RX_RB3BOK + RETFIE +RX_RB3BOK + LFSR 1,TX_BUFFER ;BYT RX COUNTER AUF TX_BUFFER + MOVFF POSTINC1,TBLPTRU ;ADRESSE EINTRAGEN + MOVFF POSTINC1,TBLPTRH + MOVFF POSTINC1,TBLPTRL + MOVLW 0xC2 ;67 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 +RX_RB3B2 + TBLRD *+ ;LESEN UND NEXT + MOVFF TABLAT,POSTINC1 ;UND EINTRAGEN + CPFSEQ FSR1L ;WENN FERTIG ->SKIP + BRA RX_RB3B2 ;SONST LOOP +;BLOCK HEADER 3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN ----------------------------------------- + LFSR 0,TX_BUFFER ;TX COUNTER AUF TX_BUFFER + BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN + BSF PIE1,TXIE ;Enable interrupt + MOVLW READ_BLOCK ;CODE HEADER 0xA1 + MOVWF TX_STATUS ;STATUS SETZEN + MOVWF TXREG ;BLOCK HEADER = 0XA1 + CLRF RX_STATUS ;STATUS RÜCKSETZEN + RETFIE ;UND WEG +;------------------------------------------------------------------------------------- +RX_ISR7 + MOVLW WRITE_BLOCK ;WRITE BLOCK 0xA2 BYT EMPFANGEN? + CPFSEQ RX_STATUS ;WENN JA-> SKIP + BRA RX_ISR8 ;NEIN-> +;WRITE BLOCK ---------------------------------------------------------------------------- +;67 BYT EMPFANGEN ------------------------------------- + MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) + MOVLW 0x42 ;67 BYT ÜBERTRAGEN? + CPFSLT FSR1L ;WENN FERTIG ->SKIP + RETFIE +; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH + LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER + MOVFF POSTINC1,TBLPTRU ;TABLE POINTER SETZEN + MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 + CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT + BRA NO_PROG ;JA-> + MOVFF POSTINC1,TBLPTRH ;TABLE POINTER SETZEN + MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 + CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT + BRA NO_PROG ;JA-> + MOVFF POSTINC1,TBLPTRL ;TABLE POINTER SETZEN +;EREASE BLOCK + BSF EECON1,EEPGD ; point to Flash program memory + BCF EECON1,CFGS ; access Flash program memory + BSF EECON1,WREN ; enable write to memory + BSF EECON1,FREE ; enable Row Erase operation + MOVLW 55h + MOVWF EECON2 ; write 55h + MOVLW 0AAh ; write 0AAh + MOVWF EECON2 + BSF EECON1,WR ; start erase (CPU stall) + MOVLW 0x42 ;67 BYT +WRITE_WORD_TO_HREGS + MOVFF POSTINC1,TABLAT ; get byte of buffer data + TBLWT+* ; write data, perform a short write to internal TBLWT holding register. + CPFSLT FSR1L ;SCHON BEI 67 BYTES? + BRA WRITE_WORD_TO_HREGS ;NEIN->LOOP +PROGRAM_MEMORY + BSF EECON1,EEPGD ; point to Flash program memory + BCF EECON1,CFGS ; access Flash program memory + BSF EECON1,WREN ; enable write to memory + MOVLW 55h + MOVWF EECON2 ; write 55h + MOVLW 0AAh + MOVWF EECON2 ; write 0AAh + BSF EECON1,WR ; start program (CPU stall) + BCF EECON1,WREN ; disable write to memory +NO_PROG + CLRF RX_STATUS ;AUF NORMLA SCHALTEN + RETFIE ;UND FERTIG +;WRITE BLOCK SETZEN? +RX_ISR8 + CPFSEQ RX_B ;BLOCK HEADER COMMANDOE 0XA2? + BRA RX_ISR9 ;NEIN-> + MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT + LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER + RETFIE +;------------------------------------------------------------------------------------- +RX_ISR9 + CLRF RX_STATUS + RETFIE +;------------------------------------------------------------------------------------- +;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ---------------------------------------------------- +;------------------------------------------------------------------------------------- +RX_SYNC_START + MOVLW SYNC1 + CPFSEQ RX_STATUS + BRA RX_SYNC2 + MOVLW SYNC1_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC2 + MOVWF RX_STATUS + RETFIE +NON_SYNC + MOVLW SYNC1 + MOVWF RX_STATUS + RETFIE +RX_SYNC2 ;TEST AUF SYNC UND DATA 2 + MOVLW SYNC2 + CPFSEQ RX_STATUS + BRA RX_SYNC3 ;NICHT SYNC 2 + MOVLW SYNC2_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC3 + MOVWF RX_STATUS + RETFIE +RX_SYNC3 ;TEST AUF SYNC UND DATA 3 + MOVLW SYNC3 + CPFSEQ RX_STATUS + BRA RX_SYNC4 ;NICHT SYNC 3 + MOVLW SYNC3_DATA + CPFSEQ RX_B + BRA NON_SYNC + MOVLW SYNC4 + MOVWF RX_STATUS + RETFIE +RX_SYNC4 ;TEST AUF SYNC UND DATA 4 + MOVLW SYNC4 + CPFSEQ RX_STATUS + BRA NON_SYNC ;WIEDER VON VORN + MOVLW SYNC4_DATA + CPFSEQ RX_B ;SKIP OK + BRA NON_SYNC ;NICHT SYNC4 DATA +RX_WAIT1 + BTFSS TXSTA,TRMT + BRA RX_WAIT1 + MOVLW 'O' ;SENDE OK! + MOVWF TXREG; +RX_WAIT2 + BTFSS TXSTA,TRMT + BRA RX_WAIT2 + MOVLW 'K' ;SENDE OK! + MOVWF TXREG; +RX_WAIT3 + BTFSS TXSTA,TRMT + BRA RX_WAIT3 + MOVLW '!' + MOVWF TXREG; + CLRF RX_STATUS ;OK START NORMAL + RETFIE +;**********************************************************************************************""""""""""""" +;SPANNUNGSÜBERWACHUNGS INTERRUPT +HLVD_ISR + BTFSS U_ERR,1 ;WARTEN AUF GELADEN? + BRA HLVD_LE ;NEIN UNTERSPANNUNG DETEKT-> + BCF U_ERR,0 ;SPANNUNGSFEHLER AUS + BCF U_ERR,1 ;WARTEN AUF GELADEN=AUS + MOVLW U_ERR_PW_AUS+2 ;POWER AUS ÜBERSPRINGEN + MOVWF U_ERR_TIME ;ZEIT SETZEN + MOVLW B'00010111' ;INT WENN UNTER 3.12V + MOVWF HLVDCON +WAIT_LVDOK: + BTFSS HLVDCON,IVRST ;ABWARTEN BIS AENDERUNG AKTIV + BRA WAIT_LVDOK + BCF PIR2,HLVDIF ;INTERRUPT FLAG LÖSCHEN + RETFIE +HLVD_LE ;UNTERSPANNUNG + BSF U_ERR,0 ;ERROR SETZEN + BSF U_ERR,1 ;WARTEN AUF GELADEN SETZEN + CLRF U_ERR_TIME ;RÜCKSETZEN +;MESSAGE AN PROCESSOR + MOVLW U_MIN_TO_MCF + MOVWF TXREG ;SENDEN + + MOVLW B'10011010' ;INT WENN ÜBER 3.7V + MOVWF HLVDCON + BRA WAIT_LVDOK +;**********************************************************************************************""""""""""""" +;A/D INTERRUPT +AD_ISR + BCF PIR1,ADIF ;CLEAR INTERRUPT PENDIG + RETFIE ;RETURN +;************************************************************************************************************* +; uhr interrupt ALLE 1/8 SEC +RTC_ISR +;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN + MOVLW TIMER_HB ;WIEDER AUF STARTWERT + MOVWF TMR1H ;SETZEN + BCF PIR1,TMR1IF ;INTERRUPT FLAG LÖSCHEN + BSF PORTB,RB4 ;PIC INT HIGH -------- + BSF TRISE,RE0 ;LED=OFF + BCF PORTB,RB4 ;PIC INT = LOW + BTFSC TRISD,RD0 ;POWER OFF? + BRA POWER_OFF_I ;JA-> +; POWER IS ON: +; BLINKEN 4X/SEC WENN RESET + BTFSC TRISD,RD7 ;RESET AKTIV? + BRA PINGS ;NEIN-> + BTFSC TICKS,0 ;UNGERADE TICKS? + BCF TRISE,RE0 ;NEIN->LED=ON + BRA PINGS +POWER_OFF_I + MOVLW .3 + ANDWF SECS,0 ;4 SEKUNDEN AUSMASKIEREN + BNZ PINGS ;NICHT MODULO4 -> + MOVLW .7 + CPFSEQ TICKS ;7. TICK? + BRA POWER_OFF_I2 ;NEIN-> + BCF TRISE,RE0 ;JA->LED=ON +POWER_OFF_I2 + MOVLW .30 ; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER? + CPFSLT U_ERR_TIME + BRA PINGS ;NEIN-> + MOVLW .5 + CPFSEQ TICKS ;5. TICK? + BRA PINGS ;NEIN-> + BCF TRISE,RE0 ;JA->LED=ON +PINGS + CALL TASTE ;UP TASTE +; TASTE LOSGELASSEN? + MOVLW RESET_OFF_TIME + CPFSGT TASTE_OFF_TIME ;TASTE LÄNGER ALS 2 SEC LOSGELASSEN? + BRA PINGW ;NEIN-> + BSF TRISD,RD7 ;JA-> #RSTI INAKTIV =HIGH + BTFSS TRISD,RD0 ;POWER ON? + CALL SERIAL_ON ;ja->SERIELL EINSCHALTEN +;--TICKS=125MS +PINGW + INCF TICKS ;inc ticks + BTFSS TRISD,RD0 ;POWER ON? + BRA PINGS2 ;JA-> + MOVLW 20 + CPFSLT U_POWER_IN ;LADEGERÄT ANGESCHLOSSEN? + BRA PINGS2 ;->JA LED HELLER + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSLT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + BSF TRISE,RE0 ;JA -> LED OFF +PINGS2 + MOVLW .7 ; 7? + CPFSGT TICKS + RETFIE ; NEIN ->RETURN +SEKUNDEN +;led blinken POWER ON----------------------------------------- + BTFSS TRISD,RD0 ;POWER ON? + BCF TRISE,RE0 ;JA -> LED_ON +;TIMER U_ERR ERHÖHEN + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + INCF U_ERR_TIME ;NEIN ERHÖHEN +;SPANNUNGSFEHLER BEARBEITEN ---------------------------------------- + MOVLW U_ERR_PW_AUS ;POWER AUS ZEIT? + CPFSEQ U_ERR_TIME ; + BRA SEK_NPA ;NEIN + CALL POWER_AUS ;JA AUSSCHALTEN +;-------------------------------------------------------- +SEK_NPA +;SPANNUNG POWER IN MESSEN + MOVLW B'00000001' ;KANAL 0, AD ON + MOVWF ADCON0 ; + BSF ADCON0,1 ;GO +SEK_2 + BTFSC ADCON0,1 ;FERTIG? + BRA SEK_2 ;NEIN + MOVFF ADRESH,U_POWER_IN ;OK WERT EINTRAGEN + +;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1 + BTFSC TRISD,RD0 ;POWER ON? + BRA SEK_4 ;NEIN NICHT MESSEN + + MOVLW B'00001101' ;KANAL 3, AD ON + MOVWF ADCON0 ; + BSF ADCON0,1 ;GO +SEK_3 + BTFSC ADCON0,1 ;FERTIG? + BRA SEK_3 ;NEIN + MOVLW .200 ;UNTER 3.2V -> WENN WERT ÜBER 78% + CPFSLT ADRESH ;JA -> + BRA SEK_4 ;SONST WEITER +;TIMER U_ERR ERHÖHEN + BTFSS U_ERR,0 ;SPANNUNGSERROR? + BRA SEK_4 ;NEIN + MOVLW TIME_MAX ;>=MAXIMALZEIT? + CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER + DECF U_ERR_TIME ;NEIN -> -1 +;------------------------------------------------------------- +SEK_4 + CLRF TICKS + INCF SECS ; Increment seconds + MOVLW .59 ; 60 seconds elapsed? + CPFSGT SECS + RETFIE ;RETURN +MINUTEN + CLRF SECS ; Clear seconds + INCF MINS ; Increment minutes + MOVLW .59 ; 60 minutes elapsed? + CPFSGT MINS + RETFIE ;RETURN +STUNDEN + CLRF MINS ; clear minutes + INCF HOURS ; Increment hours + MOVLW .23 ; 24 hours elapsed? + CPFSGT HOURS + RETFIE ;RETURN +TAGE_UND_TAG_DER_WOCHE + CLRF HOURS ; Reset hours + MOVLW .7 + CPFSLT DAY_OF_WEEK + CLRF DAY_OF_WEEK + INCF DAY_OF_WEEK + INCF DAYS + MOVLW .28 + CPFSGT DAYS + RETFIE ;RETURN +MEHR_ALS_28_TAGE + MOVLW .2 + CPFSEQ MONTHS ;FEB? + BRA NOT_FEB ;NEIN-> +FEB + MOVLW .3 + ANDWF YEARS,0 ;SCHALTJAHR + BNZ NEXT_MONTH ;NEIN-> +SCHALTJAHR + MOVLW .29 + CPFSGT DAYS + RETFIE ;RETURN +NEXT_MONTH + MOVLW .1 + MOVWF DAYS + INCF MONTHS + MOVLW 12 + CPFSGT MONTHS + RETFIE ;RETURN +YEAR + MOVLW .1 + MOVWF MONTHS + INCF YEARS + RETFIE ;RETURN +NOT_FEB + MOVLW .30 + CPFSGT DAYS + RETFIE +MEHR_ALS_30_TAGE + MOVLW .4 ;APRIL? + CPFSEQ MONTHS ;SKIP + BRA NOT_APRIL + BRA NEXT_MONTH ;APRIL-> +NOT_APRIL + MOVLW .6 ;JUNI? + CPFSEQ MONTHS + BRA NOT_JUNI + BRA NEXT_MONTH ;JUNI-> +NOT_JUNI + MOVLW .9 ;SEPTEMBER? + CPFSEQ MONTHS + BRA NOT_SEP + BRA NEXT_MONTH ;SEPTEMBER-> +NOT_SEP + MOVLW .11 ;NOVEMBER? + CPFSEQ MONTHS ;SKIP + RETFIE ;SIND MONATE MIT 31 TAGEN-> + BRA NEXT_MONTH ;SONST NOVEMBER-> +;**********************************************************************************************""""""""""""" +; ENDE MAIN +;**********************************************************************************************""""""""""""" +;**********************************************************************************************""""""""""""" +; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN +;**********************************************************************************************""""""""""""" + end diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.cof b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.cof new file mode 100644 index 0000000000000000000000000000000000000000..d3b53d4f93c350bd8aa7b64c1e68c9480c001170 GIT binary patch literal 13640 zcmZ|V4SY;@x(D#*c}_&4dOA{6t=iP8s%Vx-Q>#`pNhWV5libOOm(7}x#LI+xk)=d$sN*b!EYS>iOwW_MBYOOM?idCzqRaGTbZ(GX#|1+7G-}K)3n3@0gcb@Y< zXHL$Wb53$h3;Jls>-Gh4M8km55eFkiY{&)+(KKUz&MHQtN9)|aU9q-W&;M`LxK;{nIp?G8EKZ*$1; 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"P18f4520.inc" + 00001 LIST + 00002 + 00003 ;========================================================================== + 00004 ; MPASM PIC18F4520 processor include + 00005 ; + 00006 ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved + 00007 ;========================================================================== + 00008 + 01336 LIST + 00009 ;------------------------ Equates --------------------------; + 00010 ;Register addresses + 00011 ;BANK 0 + 00000000 00012 SECS equ 0x00 + 00000001 00013 SECS_ALARM EQU 0x01 + 00000002 00014 MINS equ 0x02 + 00000003 00015 MINS_ALRAM EQU 0x03 + 00000004 00016 HOURS equ 0x04 + 00000005 00017 HOURS_ALARM EQU 0x05 + 00000006 00018 DAY_OF_WEEK EQU 0x06 + 00000007 00019 DAYS EQU 0x07 + 00000008 00020 MONTHS EQU 0x08 + 00000009 00021 YEARS EQU 0x09 ;offset vom 1968 + 0000000A 00022 REGA EQU 0x0A + 0000000B 00023 REGB EQU 0x0B + 0000000C 00024 REGC EQU 0x0C + 0000000D 00025 REGD EQU 0x0D + 0000000E 00026 RTC_RAM EQU 0x0E ; bis 0x3F + 00000040 00027 free equ 0x40 + 00000041 00028 TICKS equ 0x41 ;125MS + 00000042 00029 TASTE_ON_TIME EQU 0x42 + 00000043 00030 TASTE_OFF_TIME EQU 0x43 + 00000044 00031 POWER_ON_TIME EQU 0x44 + 00000045 00032 AD_KANAL EQU 0x45 + 00000046 00033 U_ERR EQU 0x46 ;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WA + RTEN AUF GELADEN + 00000047 00034 U_ERR_TIME EQU 0x47 ;ZEIT SEIT SPANNUNGSFEHLER + 00000048 00035 U_POWER_IN EQU 0x48 ;SPANNUNG POWER IN 1V CA. 6E + 00000049 00036 RX_B EQU 0x49 ;RECEIVED BYT + 0000004A 00037 RX_STATUS EQU 0x4A ;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x8 + 2=EMPFANGE 64BYT FROM RTC + 0000004B 00038 TX_STATUS EQU 0x4B ;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM + RTC + 0000004C 00039 GO_SUB EQU 0x4C ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH + REN + 0000004D 00040 GO_INT EQU 0x4D ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 2 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + REN + 0000004E 00041 EAPIR1 EQU 0x4E ;INTERRUPT ACTIV UND ENABLE + 0000004F 00042 EAPIR2 EQU 0x4F ;INTERRUPT ACTIV UND ENABLE + 00043 ;BANK 1 AB 0x100 + 00000100 00044 RX_BUFFER EQU 0x100 ;0x80 BYT BUFFER BIS 0x17F BANK + 00000180 00045 TX_BUFFER EQU 0x180 ;0X80 BYT BUFFER BIS 0x1FF BANK + 00046 + 00047 ;-------------------------------------------------------------- + 00000002 00048 SEND_RTC_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS + 00000002 00049 RESET_ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK = 128MS + 00000004 00050 RESET_OFF_TIME EQU .4 ;0.5 SEC (EINHEIT IST EIN TICK = 128MS + 00000014 00051 OFF_TIME EQU .20 ;2.5 SEC (EINHEIT IST EIN TICK = + 128MS + 00000002 00052 ON_TIME EQU .2 ;0.25 SEC (EINHEIT IST EIN TICK + = 128MS + 000000F0 00053 TIMER_HB EQU .240 ;256- (32768Hz PRO 1/8SEC = 4096TICKS/25 + 6) => 256-16=240 (resp 256-16/4 (wenn osco) = 252) + 000000A0 00054 TIME_MAX EQU .160 ;MAXIMALTIME + 00000005 00055 U_ERR_PW_AUS EQU .5 ;5 SEC + 00056 ;SERIEL + 000000FF 00057 SYNC1 EQU 0FFh + 00000041 00058 SYNC1_DATA EQU 'A'; + 000000FE 00059 SYNC2 EQU 0FEh + 00000043 00060 SYNC2_DATA EQU 'C'; + 000000FD 00061 SYNC3 EQU 0FDh + 00000050 00062 SYNC3_DATA EQU 'P'; + 000000FC 00063 SYNC4 EQU 0FCh + 00000046 00064 SYNC4_DATA EQU 'F'; + 00000001 00065 REQ_RTCD_FROM_PIC EQU 01h ;RTC AND NVRAM DATEN VOM PIC ANFORDERN + 00000081 00066 RTCD_FROM_PIC EQU 81h ;RTC AND NVRAM DATEN HEADER UND STATUS + 00000002 00067 REQ_RTCD_FROM_MCF EQU 02h ;RTC AND NVRAM DATEN VOM MCF ANFORDERN + 00000082 00068 RTCD_FROM_MCF EQU 82h ;RTC AND NVRAM DATEN HEADER UND STATUS + 00000003 00069 U_MIN_TO_MCF EQU 03h ;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR + 00000004 00070 EXT_SUB_GO EQU 04h ;SERIELL CODE UM SUBROUTINEN/INT + ERRUPTS ZU AKTIVIEREN + 00000005 00071 EXT_SUB_STOP EQU 05h ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS + ZU STOPPEN + 00000012 00072 CLK_SLEEP EQU B'00010010' ;125kHz intern, SLEEP MODE + 00000072 00073 CLK_ACTIV EQU B'01110010' ;inTernal CLK=8MHz, SLEEP MODE, + SLEEP MODE + 000000FB 00074 EXT_CODE EQU 0xFB ;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS + AUSFÜHREN (FireBee!) + 00002000 00075 EXTERN_INT_ADR EQU 0x2000 ;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS A + USFÜHRBAR + 00002002 00076 EXTERN_INTERRUPTS EQU 0x2002 ;STARTPUNKT EXTERNE SUBROUTINES + 00002010 00077 EXTERN_SUB_ADR EQU 0x2010 ;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES + AUSFÜHRBAR + 00002012 00078 EXTERN_SUBROUTINES EQU 0x2012 ;STARTPUNKT EXTERNE SUBROUTINES + 000000A0 00079 REQ_BLOCK EQU 0xA0 ;BLOCK DATEN LESEN -> CODE UND 3 BYTS AD + RESSE = TOTAL 4 BYTES + 000000A1 00080 READ_BLOCK EQU 0xA1 ;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS + ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES + 000000A2 00081 WRITE_BLOCK EQU 0xA2 ;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 3 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES + 00000022 00082 PRG_OK_PIC EQU 0x22 ;PROGRAMMIERUNG BLOCK FERTIG + 00083 ;**********************************************************************************************""""""""" + """" + 00084 ; Start at the reset vector + 00085 Reset_Vector code 0x000 +000000 D??? 00086 BRA KALT_START + 00087 ;-------------------------------------------------------------- + 00088 HIGH_INT_VEC code 0x0008 +000008 EF0C F000 00089 GOTO 0x18 + 00090 + 00091 LOW_INT_VEC code 0x0018 +000018 00092 INT_HANDLER +000018 6AE0 00093 CLRF BSR ;IMMER ACCESS BANK + 00094 ;SETZEN GRUPPE 1 +00001A CF9D F04E 00095 MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN +00001E 509E 00096 MOVF PIR1,0 ;MASKE +000020 174E 00097 ANDWF EAPIR1 ;ACTIVE SETZEN +000022 B14E 00098 BTFSC EAPIR1,TMR1IF ;uhr interrupt? +000024 D??? 00099 BRA RTC_ISR ;ja-> +000026 BD4E 00100 BTFSC EAPIR1,ADIF ;AD INTERRUTP? +000028 D??? 00101 BRA AD_ISR ;JA-> +00002A B94E 00102 BTFSC EAPIR1,TXIF ;seriell TX? +00002C D??? 00103 BRA TX_ISR ;JA-> +00002E BB4E 00104 BTFSC EAPIR1,RCIF ;seriell RX? +000030 D??? 00105 BRA RX_ISR ;JA-> + 00106 + 00107 ;SETZEN GRUPPE 2 +000032 CFA0 F04F 00108 MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN +000036 50A1 00109 MOVF PIR2,0 ;MASKE +000038 174F 00110 ANDWF EAPIR2 ;ACTIVE SETZEN + 00111 +00003A B54F 00112 BTFSC EAPIR2,HLVDIF ;UNDER/OVERVOLTAGE DETECT +00003C D??? 00113 BRA HLVD_ISR ;JA-> +00003E 0010 00114 RETFIE + 00115 + 00116 ;TESTEN UND SETZEN GRUPPE 1 +000040 CF9D F04E 00117 MOVFF PIE1,EAPIR1 ;INTERRUPTS HOLEN +000044 509E 00118 MOVF PIR1,0 ;MASKE +000046 174E 00119 ANDWF EAPIR1 ;ACTIVE SETZEN +000048 674E 00120 TSTFSZ EAPIR1 +00004A D??? 00121 BRA INT_HANDLER + 00122 ;TESTEN UND SETZEN GRUPPE 2 +00004C CFA0 F04F 00123 MOVFF PIE2,EAPIR2 ;INTERRUPTS HOLEN +000050 50A1 00124 MOVF PIR2,0 ;MASKE +000052 174F 00125 ANDWF EAPIR2 ;ACTIVE SETZEN +000054 674F 00126 TSTFSZ EAPIR2 +000056 D??? 00127 BRA INT_HANDLER + 00128 +000058 0EFB 00129 MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? +00005A 634D 00130 CPFSEQ GO_INT ;SKIP WENN JA +00005C 0010 00131 RETFIE +00005E EF01 F010 00132 GOTO EXTERN_INTERRUPTS ;REGISTER SICHERN UND STARTEN + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 4 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00133 ;**********************************************************************************************""""""""" + """" + 00134 ; Start application beyond vector area + 00135 CODE 0x0100 +000100 00136 KALT_START + 00137 ;RESET MODE +000100 6AE0 00138 CLRF BSR ;BANK 0 + 00139 ;ALLE INT AUS UND RÜCKSETZEN +000102 6AF2 00140 CLRF INTCON ;alle INTERRUPT AUS +000104 6AD0 00141 CLRF RCON ;INT PRIORITY AUS +000106 6A9D 00142 CLRF PIE1 ;MASK DISABLE +000108 6AA0 00143 CLRF PIE2 +00010A 6A9E 00144 CLRF PIR1 ;INT ACT AUS +00010C 6AA1 00145 CLRF PIR2 +00010E 6A9F 00146 CLRF IPR1 ;LOW PRIORITY +000110 6AA2 00147 CLRF IPR2 + 00148 ; clock + 00149 ; MOVLW B'01000000' ;32MHZ + 00150 ; MOVWF OSCTUNE +000112 6A9B 00151 CLRF OSCTUNE + 00152 ;CLOCK +000114 0E72 00153 MOVLW CLK_ACTIV +000116 6ED3 00154 MOVWF OSCCON + 00155 ; div init + 00156 ;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3 + /2 **1:1V25 **0:POWER_IN/11 +000118 6A80 00157 CLRF PORTA ;#master(7)=0, REST=0 +00011A 0EFF 00158 MOVLW B'11111111' ;DIRECTION: alles auf Input +00011C 6E92 00159 MOVWF TRISA + 00160 ;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PO + RT PIN6 **0: GAME PORT PIN5 +00011E 6A81 00161 CLRF PORTB ;ALLES AUF 0 +000120 6E93 00162 MOVWF TRISB + 00163 ;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN + 13 **1+0: OCS 32K768Hz +000122 6A82 00164 CLRF PORTC +000124 6E94 00165 MOVWF TRISC + 00166 ;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1: + TASTER **0:POWER ON/OFF (0=ON) + 00167 ; SET TASTE UND POWER +000126 6A83 00168 CLRF PORTD ;ALLES AUF 0 +000128 6E95 00169 MOVWF TRISD ;ALLES AUF INPUT + 00170 ;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON) +00012A 0E01 00171 MOVLW B'00000001' ;LED OFF +00012C 6A84 00172 CLRF PORTE ;ALLES AUF 0 +00012E 6E96 00173 MOVWF TRISE ;ALLES AUF INPUT + 00174 ;-------------------------- + 00175 ; set OVERvoltage detekt +000130 0E9B 00176 MOVLW B'10011011' ;INT WENN ÜBER 3.9V +000132 6ED2 00177 MOVWF HLVDCON +000134 0E03 00178 MOVLW B'00000011' ;ERRORS ON, WAIT AUF LADEN +000136 6F46 00179 MOVWF U_ERR +000138 0E14 00180 MOVLW .20 ;SEIT 20SEC ERROR + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 5 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00013A 6F47 00181 MOVWF U_ERR_TIME ;SETZEN +00013C 84A0 00182 BSF PIE2,HLVDIE ;Enable interrupt + 00183 ;INTIALISIERUNGSPROGAMME +00013E EC?? F??? 00184 CALL LADESTROM ;LADESTROM EINSTELLEN + 00185 ;UHR initialisieren +000142 0EF0 00186 MOVLW TIMER_HB ;Preload TMR1 register +000144 6ECF 00187 MOVWF TMR1H ; +000146 6ACE 00188 CLRF TMR1L ;=0 +000148 0E0F 00189 MOVLW B'00001111' ; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE +00014A 6ECD 00190 MOVWF T1CON ; SET +00014C 6B41 00191 CLRF TICKS ; 1/8 sec register +00014E 6B00 00192 CLRF SECS ; Initialize timekeeping registers +000150 6B02 00193 CLRF MINS ; +000152 0E0C 00194 MOVLW .12 +000154 6F04 00195 MOVWF HOURS +000156 0E01 00196 MOVLW .1 +000158 6F06 00197 MOVWF DAY_OF_WEEK +00015A 0E01 00198 MOVLW .1 +00015C 6F07 00199 MOVWF DAYS +00015E 0E08 00200 MOVLW .8 +000160 6F08 00201 MOVWF MONTHS +000162 0E2A 00202 MOVLW .42 +000164 6F09 00203 MOVWF YEARS ;MONTAG 19.7.2010 12:00:00 (JAHR-1968) +000166 6B42 00204 CLRF TASTE_ON_TIME +000168 6B43 00205 CLRF TASTE_OFF_TIME +00016A 6B44 00206 CLRF POWER_ON_TIME +00016C 809D 00207 BSF PIE1,TMR1IE ;Enable Timer1 interrupt + 00208 ;AD WANDLER INITIALISIEREN +00016E 6B45 00209 CLRF AD_KANAL ;BEI 0 BEGINNEN +000170 6AC2 00210 CLRF ADCON0 ;AD MOUDUL AUS +000172 0E09 00211 MOVLW B'00001001' ;VREF=VDD,ANALOG INPUT AN0-AN5 +000174 6EC1 00212 MOVWF ADCON1 +000176 0E00 00213 MOVLW B'00000000' ;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2 +000178 6EC0 00214 MOVWF ADCON2 + 00215 ; BSF PIE1,ADIE ;INTERRUPT ENABLE +00017A 6B48 00216 CLRF U_POWER_IN ;WERT AUF 0 VOLT + 00217 ; seriell initialisieren +00017C 6AB0 00218 CLRF SPBRGH +00017E 0E10 00219 MOVLW .16 +000180 6EAF 00220 MOVWF SPBRG ;BAUDE RATE = 115K +000182 0E04 00221 MOVLW B'00000100' ;TX AUS, ASYNC HIGH SPEED +000184 6EAC 00222 MOVWF TXSTA +000186 0E90 00223 MOVLW B'10010000' ;SERIEL EIN,RX EIN, +000188 6EAB 00224 MOVWF RCSTA +00018A 0E08 00225 MOVLW B'00001000' ;16BIT BRG, RISING EDGE INTERRUPT +00018C 6EB8 00226 MOVWF BAUDCON ;SETZEN + 00227 ;EXTERNER SUBROUTINES +00018E 6B4C 00228 CLRF GO_SUB + 00229 ; interrupts +000190 6AF0 00230 CLRF INTCON3 ;EXTER INTERRUPT AUS, low priority +000192 0EF0 00231 MOVLW B'11110000' ;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BP + IP Low priority +000194 6EF1 00232 MOVWF INTCON2 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 6 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000196 0EC0 00233 MOVLW B'11000000' ;global on, PERIPHERAL INT on +000198 6EF2 00234 MOVWF INTCON + 00235 ;CLOCK +00019A 0E12 00236 MOVLW CLK_SLEEP ;GEHT JETZT IN SLEEP MODE +00019C 6ED3 00237 MOVWF OSCCON + 00238 ;------------------------------------------------------------------------- + 00239 ;---------------------------- MAIN LOOP ------------------------------------------------- + 00240 ;------------------------------------------------------------------------- +00019E 00241 MAIN +00019E 0EFB 00242 MOVLW EXT_CODE ;GO EXTERNE SUBROUTINEN AKTIV? +0001A0 634C 00243 CPFSEQ GO_SUB ;SKIP WENN JA +0001A2 D??? 00244 BRA WARTEN ;SONST WARTEN +0001A4 ED00 F000 00245 CALL MAIN2,1 ;REGISTER SICHERN UND STARTEN +0001A8 00246 WARTEN +0001A8 B095 00247 BTFSC TRISD,RD0 ;SKIP IF POWER ON +0001AA 0003 00248 SLEEP ;SLEPP BIS ZUM NÄCHSTEN INTERRUPT +0001AC D??? 00249 BRA MAIN +0001AE 00250 MAIN2 +0001AE EC09 F010 00251 CALL EXTERN_SUBROUTINES ;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONS + T UNGÜLTIG +0001B2 0013 00252 RETURN 1 ;RETURN MIT REGISTER ZURÜCK + 00253 ;**********************************************************************************************""""""""" + """" + 00254 ;--------------------------- subroutines ------------------------------------------------- + 00255 ;**********************************************************************************************""""""""" + """" + 00256 ;POWER ON/OFF +0001B4 00257 POWER_EIN + 00258 ;CLOCK +0001B4 0E72 00259 MOVLW CLK_ACTIV +0001B6 6ED3 00260 MOVWF OSCCON + 00261 +0001B8 9E92 00262 BCF TRISA,RA7 ;CLOCK EINSCHALTEN +0001BA 9E95 00263 BCF TRISD,RD7 ;#RSTI AKTIVIEREN = LOW +0001BC 9893 00264 BCF TRISB,RB4 ;PIC_INT AKTIVIEREN +0001BE 9095 00265 BCF TRISD,RD0 ;POWER ON +0001C0 D??? 00266 BRA LS_ON_POWER ;LADESTROM EINSTELLEN +0001C2 00267 POWER_AUS + 00268 ;CLOCK +0001C2 0E12 00269 MOVLW CLK_SLEEP +0001C4 6ED3 00270 MOVWF OSCCON + 00271 +0001C6 8095 00272 BSF TRISD,RD0 ;POWER OFF +0001C8 8E95 00273 BSF TRISD,RD7 ;#RSTI DEAKTIVIEREN +0001CA 8893 00274 BSF TRISB,RB4 ;PIC INT DEAKTIVIEREN +0001CC 8E92 00275 BSF TRISA,RA7 ;CLOCK DEAKTIVIEREN +0001CE 6B44 00276 CLRF POWER_ON_TIME ;RÜCKSETZEN +0001D0 D??? 00277 BRA LS_OFF_POWER ;LADESTROM EINSTELLEN + 00278 ;LADESTROM EINSTELLEN ---------------------------- +0001D2 00279 LADESTROM +0001D2 B095 00280 BTFSC TRISD,RD0 ; ONPOWER? +0001D4 D??? 00281 BRA LS_OFF_POWER ; NEIN-> +0001D6 00282 LS_ON_POWER ;GROSSER LADESTROM 5A + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 7 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0001D6 9892 00283 BCF TRISA,RA4 ;10K ON +0001D8 0012 00284 RETURN +0001DA 00285 LS_OFF_POWER ;KLEINER LADESTROM_MIN 1.85A +0001DA 8892 00286 BSF TRISA,RA4 ;10K OFF +0001DC 0012 00287 RETURN + 00288 ;--------------------------------------------------- + 00289 ;SERIELL AUS/EIN +0001DE 00290 SERIAL_OFF +0001DE 9AAC 00291 BCF TXSTA,TXEN ;TX AUS +0001E0 9A9D 00292 BCF PIE1,RCIE ;DISABLE RX interrupt +0001E2 9A9E 00293 BCF PIR1,RCIF ;CLEAR RX interrupt +0001E4 989D 00294 BCF PIE1,TXIE ;DISABLE TX interrupt +0001E6 989E 00295 BCF PIR1,TXIF ;CLEAR TX interrupt +0001E8 0012 00296 RETURN +0001EA 00297 SERIAL_ON +0001EA BAAC 00298 BTFSC TXSTA,TXEN ;SCHON EIN? +0001EC 0012 00299 RETURN ;JA-> +0001EE 8AAC 00300 BSF TXSTA,TXEN ;TX EIN +0001F0 0EFF 00301 MOVLW SYNC1 +0001F2 6F4A 00302 MOVWF RX_STATUS ;AUF SYNC WARTEN +0001F4 6B4B 00303 CLRF TX_STATUS +0001F6 CFAE F049 00304 MOVFF RCREG,RX_B ;RCREG LEEREN +0001FA CFAE F049 00305 MOVFF RCREG,RX_B ;RCREG LEEREN +0001FE 989E 00306 BCF PIR1,TXIF ;CLEAR TX interrupt +000200 9A9E 00307 BCF PIR1,RCIF ;INTERRUPT RX FLAG LÖSCHEN +000202 8A9D 00308 BSF PIE1,RCIE ;ENABLE RX interrupt +000204 0000 00309 NOP +000206 0012 00310 RETURN + 00311 ;--------------------------------------------------------------------- + 00312 ; TASTENDRUCK +000208 00313 TASTE +000208 A283 00314 BTFSS PORTD,RD1 ;TASTE GEDRÜCKT? +00020A D??? 00315 BRA TG_JA ;->JA + 00316 ;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN +00020C 6B42 00317 CLRF TASTE_ON_TIME ;RÜCKSETZEN + 00318 +00020E 0EA0 00319 MOVLW TIME_MAX ;MAX +000210 6543 00320 CPFSGT TASTE_OFF_TIME ;LÄNGER? +000212 2B43 00321 INCF TASTE_OFF_TIME ;NEIN ERHÖHEN + 00322 +000214 0E04 00323 MOVLW RESET_OFF_TIME ;2SEC +000216 6544 00324 CPFSGT POWER_ON_TIME ;LÄNGER? +000218 0012 00325 RETURN ;NEIN-> + 00326 ;RESET AUFHEBEN +00021A 8E95 00327 BSF TRISD,RD7 ;JA -> #RSTI DEAKTIVIEREN =HIGH +00021C EC?? F??? 00328 CALL SERIAL_ON ;SERIELL EINSCHALTEN +000220 0012 00329 RETURN + 00330 ;TASTE GEDRÜCKT +000222 00331 TG_JA +000222 0E15 00332 MOVLW OFF_TIME+1 +000224 6142 00333 CPFSLT TASTE_ON_TIME ;KÜRZER ALS ONTIME+1 +000226 0012 00334 RETURN ;NEIN->FERTIG +000228 B095 00335 BTFSC TRISD,RD0 ;ONPOWER? + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 8 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00022A D??? 00336 BRA TG_OFF_POWER ;NEIN-> +00022C 00337 TG_ON_POWER +00022C 0E02 00338 MOVLW SEND_RTC_TIME ;ZEIT FÜR RTC REQ FROM MCF HOLEN? +00022E 6342 00339 CPFSEQ TASTE_ON_TIME ;TEST +000230 D??? 00340 BRA TG_ON_POWER2 ;NEIN-> +000232 00341 SEND_RTC_REG +000232 0E02 00342 MOVLW REQ_RTCD_FROM_MCF +000234 6EAD 00343 MOVWF TXREG ;SENDEN +000236 D??? 00344 BRA TG_END; +000238 00345 TG_ON_POWER2 +000238 0E02 00346 MOVLW RESET_ON_TIME ; +00023A 6142 00347 CPFSLT TASTE_ON_TIME ;KÜRZER? +00023C D??? 00348 BRA RESETEN +00023E 00349 TG_ON_POWER3 +00023E 0E14 00350 MOVLW OFF_TIME +000240 6142 00351 CPFSLT TASTE_ON_TIME ;KÜRZER ON/OFF TIME? +000242 EC?? F??? 00352 CALL POWER_AUS ;NEIN->POWER OFF +000246 D??? 00353 BRA TG_END +000248 00354 TG_OFF_POWER +000248 0E02 00355 MOVLW ON_TIME +00024A 6142 00356 CPFSLT TASTE_ON_TIME ;KÜRZER ALS ON/OFF TIME? +00024C EC?? F??? 00357 CALL POWER_EIN ;NEIN->POWER ON +000250 00358 TG_END +000250 6B43 00359 CLRF TASTE_OFF_TIME ;RÜCKSETZEN +000252 2B42 00360 INCF TASTE_ON_TIME ;ERHÖHEN +000254 0012 00361 RETURN +000256 00362 RESETEN +000256 9E95 00363 BCF TRISD,RD7 ;NEIN-> #RSTI AKTIVIEREN =LOW -->>>RESET +000258 EC?? F??? 00364 CALL SERIAL_OFF ;SERIELL DEAKTIVIEREN +00025C D??? 00365 BRA TG_ON_POWER3 + 00366 ;**********************************************************************************************""""""""" + """" + 00367 ;----------------------------------------- INTERRUPTS + 00368 ;**********************************************************************************************""""""""" + """" + 00369 ; SERIELL INTERRUPTS + 00370 ;**********************************************************************************************""""""""" + """" + 00371 ;TX +00025E 00372 TX_ISR ;TRANSMIT +00025E 0E81 00373 MOVLW RTCD_FROM_PIC ;RTC DATEN SENDEN? +000260 634B 00374 CPFSEQ TX_STATUS ;SKIP JA +000262 D??? 00375 BRA TX_ISR1 ;NEIN-> +000264 CFEE FFAD 00376 MOVFF POSTINC0,TXREG ;BYT SENDEN +000268 0E3F 00377 MOVLW 0x3F ;SCHON LETZTES BYTS? +00026A 64E9 00378 CPFSGT FSR0L ;SKIP WENN FERTIG +00026C 0010 00379 RETFIE ;NEIN WEITERE SENDEN +00026E 00380 TX_ISR_FERTIG +00026E 6B4B 00381 CLRF TX_STATUS +000270 989D 00382 BCF PIE1,TXIE ;SONST DISABLE interrupt +000272 989E 00383 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +000274 0010 00384 RETFIE +000276 00385 TX_ISR1 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 9 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000276 0EA1 00386 MOVLW READ_BLOCK ;READ BLOCK? +000278 634B 00387 CPFSEQ TX_STATUS ;SKIP JA +00027A D??? 00388 BRA TX_ISR2 ;NEIN-> +00027C CFEE FFAD 00389 MOVFF POSTINC0,TXREG ;BYT SENDEN +000280 0EC3 00390 MOVLW 0xC3 ;SCHON LETZTES BYTS? +000282 64E9 00391 CPFSGT FSR0L ;SKIP WENN FERTIG +000284 0010 00392 RETFIE ;NEIN WEITERE SENDEN +000286 00393 TX_ISR2 +000286 D??? 00394 BRA TX_ISR_FERTIG + 00395 ;**********************************************************************************************""""""""" + """" + 00396 ;RX +000288 00397 RX_ISR ; BYT RECEIVED +000288 CFAE F049 00398 MOVFF RCREG,RX_B ; BYT HOLEN + 00399 ; MOVFF RX_B,TXREG ; ECHO +00028C 0EFC 00400 MOVLW SYNC4 ;IM SYNC STATUS? +00028E 614A 00401 CPFSLT RX_STATUS ;SKIP WENN NEIN +000290 D??? 00402 BRA RX_SYNC_START ;JA -> ZUERST SYNC EMPFANGEN + 00403 ;--------------- +000292 0E82 00404 MOVLW RTCD_FROM_MCF ; DATEN VOM MCF CODE 0x82? +000294 634A 00405 CPFSEQ RX_STATUS ; WENN JA-> SKIP +000296 D??? 00406 BRA RX_ISR1 ; NEIN-> + 00407 ;64 BYT EMPFANGEN ------------------------------------- +000298 C049 FFE6 00408 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00029C 0E3F 00409 MOVLW 0x3F ;64 BYT ÜBERTRAGEN? +00029E 60E1 00410 CPFSLT FSR1L ;NEIN ->SKIP +0002A0 6B4A 00411 CLRF RX_STATUS ;JA FERTIG +0002A2 0010 00412 RETFIE + 00413 ;------------------------------------------------------------------------------------- +0002A4 00414 RX_ISR1 +0002A4 6349 00415 CPFSEQ RX_B ;BLOCK HEADER 0X82? +0002A6 D??? 00416 BRA RX_ISR2 ;NEIN-> +0002A8 6F4A 00417 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +0002AA EE10 F000 00418 LFSR 1,.0 ;BYT COUNTER AUF O +0002AE 0010 00419 RETFIE +0002B0 00420 RX_ISR2 +0002B0 0E01 00421 MOVLW REQ_RTCD_FROM_PIC ;DATEN SENDEN? +0002B2 6349 00422 CPFSEQ RX_B ;SKIP WENN JA +0002B4 D??? 00423 BRA RX_ISR3 ;SONST NEXT + 00424 ;BLOCK HEADER UND 64 BYT SENDEN ----------------------------------------- +0002B6 EE00 F000 00425 LFSR 0,.0 +0002BA 989E 00426 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +0002BC 889D 00427 BSF PIE1,TXIE ;Enable interrupt +0002BE 0E81 00428 MOVLW RTCD_FROM_PIC +0002C0 6F4B 00429 MOVWF TX_STATUS ;STATUS SETZEN +0002C2 6EAD 00430 MOVWF TXREG ;BLOCK HEADER = 0X81 +0002C4 6B4A 00431 CLRF RX_STATUS ;STATUS RÜCKSETZEN +0002C6 0010 00432 RETFIE ;UND WEG + 00433 ;------------------------------------------------------------------------------------- +0002C8 00434 RX_ISR3 +0002C8 0E04 00435 MOVLW EXT_SUB_GO ;EXT SUB FREIGEBEN? +0002CA 6349 00436 CPFSEQ RX_B +0002CC D??? 00437 BRA RX_ISR4 ;NEIN-> + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 10 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00438 ;EXT SUBS FREIGEBEN -------------------------------------------------------------- +0002CE 0E00 00439 MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 +0002D0 6EF8 00440 MOVWF TBLPTRU +0002D2 0E20 00441 MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 +0002D4 6EF7 00442 MOVWF TBLPTRH +0002D6 0E00 00443 MOVLW (EXTERN_INT_ADR & 0x0000FF) +0002D8 6EF6 00444 MOVWF TBLPTRL ;ADRESSE SETZEN +0002DA 0008 00445 TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) +0002DC CFF5 F04D 00446 MOVFF TABLAT,GO_INT ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK +0002E0 0E00 00447 MOVLW (EXTERN_SUB_ADR & 0xFF0000)>>16 +0002E2 6EF8 00448 MOVWF TBLPTRU +0002E4 0E20 00449 MOVLW (EXTERN_SUB_ADR & 0x00FF00)>>8 +0002E6 6EF7 00450 MOVWF TBLPTRH +0002E8 0E10 00451 MOVLW (EXTERN_SUB_ADR & 0x0000FF) +0002EA 6EF6 00452 MOVWF TBLPTRL ;ADRESSE SETZEN +0002EC 0008 00453 TBLRD* ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG) +0002EE CFF5 F04C 00454 MOVFF TABLAT,GO_SUB ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK +0002F2 6B4A 00455 CLRF RX_STATUS ;STATUS RÜCKSETZEN +0002F4 0010 00456 RETFIE ;UND WEG + 00457 ;------------------------------------------------------------------------------------- +0002F6 00458 RX_ISR4 +0002F6 0E05 00459 MOVLW EXT_SUB_STOP ;EXT SUB STOPPEN? +0002F8 6349 00460 CPFSEQ RX_B +0002FA D??? 00461 BRA RX_ISR5 ;NEIN-> + 00462 ;EXT SUBS STOPPEN -------------------------------------------------------------- +0002FC 6B4D 00463 CLRF GO_INT ;STOPPEN +0002FE 6B4C 00464 CLRF GO_SUB ;STOPPEN +000300 6B4A 00465 CLRF RX_STATUS ;STATUS RÜCKSETZEN +000302 0010 00466 RETFIE ;UND WEG + 00467 ;------------------------------------------------------------------------------------- +000304 00468 RX_ISR5 +000304 0EA0 00469 MOVLW REQ_BLOCK ;REQ BLOCK? +000306 6349 00470 CPFSEQ RX_B +000308 D??? 00471 BRA RX_ISR6 ;NEIN-> + 00472 ;REQ BLOCK ---------------------------------------------------------------- +00030A 6F4A 00473 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +00030C EE11 F080 00474 LFSR 1,TX_BUFFER ;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN +000310 0010 00475 RETFIE +000312 00476 RX_ISR6 +000312 634A 00477 CPFSEQ RX_STATUS ;REQ BLOCK ADRESSE EMPFANGFEN? +000314 D??? 00478 BRA RX_ISR7 ;NEIN-> + 00479 ;3 BYT EMPFANGEN ------------------------------------- +000316 C049 FFE6 00480 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00031A 0E82 00481 MOVLW 0x82 ;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 +00031C 60E1 00482 CPFSLT FSR1L ;NEIN ->SKIP +00031E D??? 00483 BRA RX_RB3BOK +000320 0010 00484 RETFIE +000322 00485 RX_RB3BOK +000322 EE11 F080 00486 LFSR 1,TX_BUFFER ;BYT RX COUNTER AUF TX_BUFFER +000326 CFE6 FFF8 00487 MOVFF POSTINC1,TBLPTRU ;ADRESSE EINTRAGEN +00032A CFE6 FFF7 00488 MOVFF POSTINC1,TBLPTRH +00032E CFE6 FFF6 00489 MOVFF POSTINC1,TBLPTRL +000332 0EC2 00490 MOVLW 0xC2 ;67 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 11 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000334 00491 RX_RB3B2 +000334 0009 00492 TBLRD *+ ;LESEN UND NEXT +000336 CFF5 FFE6 00493 MOVFF TABLAT,POSTINC1 ;UND EINTRAGEN +00033A 62E1 00494 CPFSEQ FSR1L ;WENN FERTIG ->SKIP +00033C D??? 00495 BRA RX_RB3B2 ;SONST LOOP + 00496 ;BLOCK HEADER 3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN ----------------------------------------- +00033E EE01 F080 00497 LFSR 0,TX_BUFFER ;TX COUNTER AUF TX_BUFFER +000342 989E 00498 BCF PIR1,TXIF ;INTERRUPT FLAG LÖSCHEN +000344 889D 00499 BSF PIE1,TXIE ;Enable interrupt +000346 0EA1 00500 MOVLW READ_BLOCK ;CODE HEADER 0xA1 +000348 6F4B 00501 MOVWF TX_STATUS ;STATUS SETZEN +00034A 6EAD 00502 MOVWF TXREG ;BLOCK HEADER = 0XA1 +00034C 6B4A 00503 CLRF RX_STATUS ;STATUS RÜCKSETZEN +00034E 0010 00504 RETFIE ;UND WEG + 00505 ;------------------------------------------------------------------------------------- +000350 00506 RX_ISR7 +000350 0EA2 00507 MOVLW WRITE_BLOCK ;WRITE BLOCK 0xA2 BYT EMPFANGEN? +000352 634A 00508 CPFSEQ RX_STATUS ;WENN JA-> SKIP +000354 D??? 00509 BRA RX_ISR8 ;NEIN-> + 00510 ;WRITE BLOCK ---------------------------------------------------------------------------- + 00511 ;67 BYT EMPFANGEN ------------------------------------- +000356 C049 FFE6 00512 MOVFF RX_B,POSTINC1 ;HOLEN -> (CNT+) +00035A 0E42 00513 MOVLW 0x42 ;67 BYT ÜBERTRAGEN? +00035C 60E1 00514 CPFSLT FSR1L ;WENN FERTIG ->SKIP +00035E 0010 00515 RETFIE + 00516 ; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH +000360 EE11 F000 00517 LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER +000364 CFE6 FFF8 00518 MOVFF POSTINC1,TBLPTRU ;TABLE POINTER SETZEN +000368 0E00 00519 MOVLW (EXTERN_INT_ADR & 0xFF0000)>>16 +00036A 60F8 00520 CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT +00036C D??? 00521 BRA NO_PROG ;JA-> +00036E CFE6 FFF7 00522 MOVFF POSTINC1,TBLPTRH ;TABLE POINTER SETZEN +000372 0E20 00523 MOVLW (EXTERN_INT_ADR & 0x00FF00)>>8 +000374 60F8 00524 CPFSLT TBLPTRU ;TEST OB WENIGER ALS ERLAUBT +000376 D??? 00525 BRA NO_PROG ;JA-> +000378 CFE6 FFF6 00526 MOVFF POSTINC1,TBLPTRL ;TABLE POINTER SETZEN + 00527 ;EREASE BLOCK +00037C 8EA6 00528 BSF EECON1,EEPGD ; point to Flash program memory +00037E 9CA6 00529 BCF EECON1,CFGS ; access Flash program memory +000380 84A6 00530 BSF EECON1,WREN ; enable write to memory +000382 88A6 00531 BSF EECON1,FREE ; enable Row Erase operation +000384 0E55 00532 MOVLW 55h +000386 6EA7 00533 MOVWF EECON2 ; write 55h +000388 0EAA 00534 MOVLW 0AAh ; write 0AAh +00038A 6EA7 00535 MOVWF EECON2 +00038C 82A6 00536 BSF EECON1,WR ; start erase (CPU stall) +00038E 0E42 00537 MOVLW 0x42 ;67 BYT +000390 00538 WRITE_WORD_TO_HREGS +000390 CFE6 FFF5 00539 MOVFF POSTINC1,TABLAT ; get byte of buffer data +000394 000F 00540 TBLWT+* ; write data, perform a short write to internal + TBLWT holding register. +000396 60E1 00541 CPFSLT FSR1L ;SCHON BEI 67 BYTES? +000398 D??? 00542 BRA WRITE_WORD_TO_HREGS ;NEIN->LOOP + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 12 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00039A 00543 PROGRAM_MEMORY +00039A 8EA6 00544 BSF EECON1,EEPGD ; point to Flash program memory +00039C 9CA6 00545 BCF EECON1,CFGS ; access Flash program memory +00039E 84A6 00546 BSF EECON1,WREN ; enable write to memory +0003A0 0E55 00547 MOVLW 55h +0003A2 6EA7 00548 MOVWF EECON2 ; write 55h +0003A4 0EAA 00549 MOVLW 0AAh +0003A6 6EA7 00550 MOVWF EECON2 ; write 0AAh +0003A8 82A6 00551 BSF EECON1,WR ; start program (CPU stall) +0003AA 94A6 00552 BCF EECON1,WREN ; disable write to memory +0003AC 00553 NO_PROG +0003AC 6B4A 00554 CLRF RX_STATUS ;AUF NORMLA SCHALTEN +0003AE 0010 00555 RETFIE ;UND FERTIG + 00556 ;WRITE BLOCK SETZEN? +0003B0 00557 RX_ISR8 +0003B0 6349 00558 CPFSEQ RX_B ;BLOCK HEADER COMMANDOE 0XA2? +0003B2 D??? 00559 BRA RX_ISR9 ;NEIN-> +0003B4 6F4A 00560 MOVWF RX_STATUS ;STATUS SETZEN = EMPFANGENES BYT +0003B6 EE11 F000 00561 LFSR 1,RX_BUFFER ;BYT COUNTER AUF RX BUFFER +0003BA 0010 00562 RETFIE + 00563 ;------------------------------------------------------------------------------------- +0003BC 00564 RX_ISR9 +0003BC 6B4A 00565 CLRF RX_STATUS +0003BE 0010 00566 RETFIE + 00567 ;------------------------------------------------------------------------------------- + 00568 ;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ---------------------------------------------------- + 00569 ;------------------------------------------------------------------------------------- +0003C0 00570 RX_SYNC_START +0003C0 0EFF 00571 MOVLW SYNC1 +0003C2 634A 00572 CPFSEQ RX_STATUS +0003C4 D??? 00573 BRA RX_SYNC2 +0003C6 0E41 00574 MOVLW SYNC1_DATA +0003C8 6349 00575 CPFSEQ RX_B +0003CA D??? 00576 BRA NON_SYNC +0003CC 0EFE 00577 MOVLW SYNC2 +0003CE 6F4A 00578 MOVWF RX_STATUS +0003D0 0010 00579 RETFIE +0003D2 00580 NON_SYNC +0003D2 0EFF 00581 MOVLW SYNC1 +0003D4 6F4A 00582 MOVWF RX_STATUS +0003D6 0010 00583 RETFIE +0003D8 00584 RX_SYNC2 ;TEST AUF SYNC UND DATA 2 +0003D8 0EFE 00585 MOVLW SYNC2 +0003DA 634A 00586 CPFSEQ RX_STATUS +0003DC D??? 00587 BRA RX_SYNC3 ;NICHT SYNC 2 +0003DE 0E43 00588 MOVLW SYNC2_DATA +0003E0 6349 00589 CPFSEQ RX_B +0003E2 D??? 00590 BRA NON_SYNC +0003E4 0EFD 00591 MOVLW SYNC3 +0003E6 6F4A 00592 MOVWF RX_STATUS +0003E8 0010 00593 RETFIE +0003EA 00594 RX_SYNC3 ;TEST AUF SYNC UND DATA 3 +0003EA 0EFD 00595 MOVLW SYNC3 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 13 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0003EC 634A 00596 CPFSEQ RX_STATUS +0003EE D??? 00597 BRA RX_SYNC4 ;NICHT SYNC 3 +0003F0 0E50 00598 MOVLW SYNC3_DATA +0003F2 6349 00599 CPFSEQ RX_B +0003F4 D??? 00600 BRA NON_SYNC +0003F6 0EFC 00601 MOVLW SYNC4 +0003F8 6F4A 00602 MOVWF RX_STATUS +0003FA 0010 00603 RETFIE +0003FC 00604 RX_SYNC4 ;TEST AUF SYNC UND DATA 4 +0003FC 0EFC 00605 MOVLW SYNC4 +0003FE 634A 00606 CPFSEQ RX_STATUS +000400 D??? 00607 BRA NON_SYNC ;WIEDER VON VORN +000402 0E46 00608 MOVLW SYNC4_DATA +000404 6349 00609 CPFSEQ RX_B ;SKIP OK +000406 D??? 00610 BRA NON_SYNC ;NICHT SYNC4 DATA +000408 00611 RX_WAIT1 +000408 A2AC 00612 BTFSS TXSTA,TRMT +00040A D??? 00613 BRA RX_WAIT1 +00040C 0E4F 00614 MOVLW 'O' ;SENDE OK! +00040E 6EAD 00615 MOVWF TXREG; +000410 00616 RX_WAIT2 +000410 A2AC 00617 BTFSS TXSTA,TRMT +000412 D??? 00618 BRA RX_WAIT2 +000414 0E4B 00619 MOVLW 'K' ;SENDE OK! +000416 6EAD 00620 MOVWF TXREG; +000418 00621 RX_WAIT3 +000418 A2AC 00622 BTFSS TXSTA,TRMT +00041A D??? 00623 BRA RX_WAIT3 +00041C 0E21 00624 MOVLW '!' +00041E 6EAD 00625 MOVWF TXREG; +000420 6B4A 00626 CLRF RX_STATUS ;OK START NORMAL +000422 0010 00627 RETFIE + 00628 ;**********************************************************************************************""""""""" + """" + 00629 ;SPANNUNGSÜBERWACHUNGS INTERRUPT +000424 00630 HLVD_ISR +000424 A346 00631 BTFSS U_ERR,1 ;WARTEN AUF GELADEN? +000426 D??? 00632 BRA HLVD_LE ;NEIN UNTERSPANNUNG DETEKT-> +000428 9146 00633 BCF U_ERR,0 ;SPANNUNGSFEHLER AUS +00042A 9346 00634 BCF U_ERR,1 ;WARTEN AUF GELADEN=AUS +00042C 0E07 00635 MOVLW U_ERR_PW_AUS+2 ;POWER AUS ÜBERSPRINGEN +00042E 6F47 00636 MOVWF U_ERR_TIME ;ZEIT SETZEN +000430 0E17 00637 MOVLW B'00010111' ;INT WENN UNTER 3.12V +000432 6ED2 00638 MOVWF HLVDCON +000434 00639 WAIT_LVDOK: +000434 AAD2 00640 BTFSS HLVDCON,IVRST ;ABWARTEN BIS AENDERUNG AKTIV +000436 D??? 00641 BRA WAIT_LVDOK +000438 94A1 00642 BCF PIR2,HLVDIF ;INTERRUPT FLAG LÖSCHEN +00043A 0010 00643 RETFIE +00043C 00644 HLVD_LE ;UNTERSPANNUNG +00043C 8146 00645 BSF U_ERR,0 ;ERROR SETZEN +00043E 8346 00646 BSF U_ERR,1 ;WARTEN AUF GELADEN SETZEN +000440 6B47 00647 CLRF U_ERR_TIME ;RÜCKSETZEN + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 14 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + + 00648 ;MESSAGE AN PROCESSOR +000442 0E03 00649 MOVLW U_MIN_TO_MCF +000444 6EAD 00650 MOVWF TXREG ;SENDEN + 00651 +000446 0E9A 00652 MOVLW B'10011010' ;INT WENN ÜBER 3.7V +000448 6ED2 00653 MOVWF HLVDCON +00044A D??? 00654 BRA WAIT_LVDOK + 00655 ;**********************************************************************************************""""""""" + """" + 00656 ;A/D INTERRUPT +00044C 00657 AD_ISR +00044C 9C9E 00658 BCF PIR1,ADIF ;CLEAR INTERRUPT PENDIG +00044E 0010 00659 RETFIE ;RETURN + 00660 ;******************************************************************************************************* + ****** + 00661 ; uhr interrupt ALLE 1/8 SEC +000450 00662 RTC_ISR + 00663 ;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN +000450 0EF0 00664 MOVLW TIMER_HB ;WIEDER AUF STARTWERT +000452 6ECF 00665 MOVWF TMR1H ;SETZEN +000454 909E 00666 BCF PIR1,TMR1IF ;INTERRUPT FLAG LÖSCHEN +000456 8881 00667 BSF PORTB,RB4 ;PIC INT HIGH -------- +000458 8096 00668 BSF TRISE,RE0 ;LED=OFF +00045A 9881 00669 BCF PORTB,RB4 ;PIC INT = LOW +00045C B095 00670 BTFSC TRISD,RD0 ;POWER OFF? +00045E D??? 00671 BRA POWER_OFF_I ;JA-> + 00672 ; POWER IS ON: + 00673 ; BLINKEN 4X/SEC WENN RESET +000460 BE95 00674 BTFSC TRISD,RD7 ;RESET AKTIV? +000462 D??? 00675 BRA PINGS ;NEIN-> +000464 B141 00676 BTFSC TICKS,0 ;UNGERADE TICKS? +000466 9096 00677 BCF TRISE,RE0 ;NEIN->LED=ON +000468 D??? 00678 BRA PINGS +00046A 00679 POWER_OFF_I +00046A 0E03 00680 MOVLW .3 +00046C 1500 00681 ANDWF SECS,0 ;4 SEKUNDEN AUSMASKIEREN +00046E E1?? 00682 BNZ PINGS ;NICHT MODULO4 -> +000470 0E07 00683 MOVLW .7 +000472 6341 00684 CPFSEQ TICKS ;7. TICK? +000474 D??? 00685 BRA POWER_OFF_I2 ;NEIN-> +000476 9096 00686 BCF TRISE,RE0 ;JA->LED=ON +000478 00687 POWER_OFF_I2 +000478 0E1E 00688 MOVLW .30 ; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER? +00047A 6147 00689 CPFSLT U_ERR_TIME +00047C D??? 00690 BRA PINGS ;NEIN-> +00047E 0E05 00691 MOVLW .5 +000480 6341 00692 CPFSEQ TICKS ;5. TICK? +000482 D??? 00693 BRA PINGS ;NEIN-> +000484 9096 00694 BCF TRISE,RE0 ;JA->LED=ON +000486 00695 PINGS +000486 EC?? F??? 00696 CALL TASTE ;UP TASTE + 00697 ; TASTE LOSGELASSEN? +00048A 0E04 00698 MOVLW RESET_OFF_TIME + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 15 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +00048C 6543 00699 CPFSGT TASTE_OFF_TIME ;TASTE LÄNGER ALS 2 SEC LOSGELASSEN? +00048E D??? 00700 BRA PINGW ;NEIN-> +000490 8E95 00701 BSF TRISD,RD7 ;JA-> #RSTI INAKTIV =HIGH +000492 A095 00702 BTFSS TRISD,RD0 ;POWER ON? +000494 EC?? F??? 00703 CALL SERIAL_ON ;ja->SERIELL EINSCHALTEN + 00704 ;--TICKS=125MS +000498 00705 PINGW +000498 2B41 00706 INCF TICKS ;inc ticks +00049A A095 00707 BTFSS TRISD,RD0 ;POWER ON? +00049C D??? 00708 BRA PINGS2 ;JA-> +00049E 0E20 00709 MOVLW 20 +0004A0 6148 00710 CPFSLT U_POWER_IN ;LADEGERÄT ANGESCHLOSSEN? +0004A2 D??? 00711 BRA PINGS2 ;->JA LED HELLER +0004A4 0EA0 00712 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004A6 6147 00713 CPFSLT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004A8 8096 00714 BSF TRISE,RE0 ;JA -> LED OFF +0004AA 00715 PINGS2 +0004AA 0E07 00716 MOVLW .7 ; 7? +0004AC 6541 00717 CPFSGT TICKS +0004AE 0010 00718 RETFIE ; NEIN ->RETURN +0004B0 00719 SEKUNDEN + 00720 ;led blinken POWER ON----------------------------------------- +0004B0 A095 00721 BTFSS TRISD,RD0 ;POWER ON? +0004B2 9096 00722 BCF TRISE,RE0 ;JA -> LED_ON + 00723 ;TIMER U_ERR ERHÖHEN +0004B4 0EA0 00724 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004B6 6547 00725 CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004B8 2B47 00726 INCF U_ERR_TIME ;NEIN ERHÖHEN + 00727 ;SPANNUNGSFEHLER BEARBEITEN ---------------------------------------- +0004BA 0E05 00728 MOVLW U_ERR_PW_AUS ;POWER AUS ZEIT? +0004BC 6347 00729 CPFSEQ U_ERR_TIME ; +0004BE D??? 00730 BRA SEK_NPA ;NEIN +0004C0 EC?? F??? 00731 CALL POWER_AUS ;JA AUSSCHALTEN + 00732 ;-------------------------------------------------------- +0004C4 00733 SEK_NPA + 00734 ;SPANNUNG POWER IN MESSEN +0004C4 0E01 00735 MOVLW B'00000001' ;KANAL 0, AD ON +0004C6 6EC2 00736 MOVWF ADCON0 ; +0004C8 82C2 00737 BSF ADCON0,1 ;GO +0004CA 00738 SEK_2 +0004CA B2C2 00739 BTFSC ADCON0,1 ;FERTIG? +0004CC D??? 00740 BRA SEK_2 ;NEIN +0004CE CFC4 F048 00741 MOVFF ADRESH,U_POWER_IN ;OK WERT EINTRAGEN + 00742 + 00743 ;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1 +0004D2 B095 00744 BTFSC TRISD,RD0 ;POWER ON? +0004D4 D??? 00745 BRA SEK_4 ;NEIN NICHT MESSEN + 00746 +0004D6 0E0D 00747 MOVLW B'00001101' ;KANAL 3, AD ON +0004D8 6EC2 00748 MOVWF ADCON0 ; +0004DA 82C2 00749 BSF ADCON0,1 ;GO +0004DC 00750 SEK_3 +0004DC B2C2 00751 BTFSC ADCON0,1 ;FERTIG? + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 16 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +0004DE D??? 00752 BRA SEK_3 ;NEIN +0004E0 0EC8 00753 MOVLW .200 ;UNTER 3.2V -> WENN WERT ÜBER 78% +0004E2 60C4 00754 CPFSLT ADRESH ;JA -> +0004E4 D??? 00755 BRA SEK_4 ;SONST WEITER + 00756 ;TIMER U_ERR ERHÖHEN +0004E6 A146 00757 BTFSS U_ERR,0 ;SPANNUNGSERROR? +0004E8 D??? 00758 BRA SEK_4 ;NEIN +0004EA 0EA0 00759 MOVLW TIME_MAX ;>=MAXIMALZEIT? +0004EC 6547 00760 CPFSGT U_ERR_TIME ;SEIT SPANNUNGSFEHLER +0004EE 0747 00761 DECF U_ERR_TIME ;NEIN -> -1 + 00762 ;------------------------------------------------------------- +0004F0 00763 SEK_4 +0004F0 6B41 00764 CLRF TICKS +0004F2 2B00 00765 INCF SECS ; Increment seconds +0004F4 0E3B 00766 MOVLW .59 ; 60 seconds elapsed? +0004F6 6500 00767 CPFSGT SECS +0004F8 0010 00768 RETFIE ;RETURN +0004FA 00769 MINUTEN +0004FA 6B00 00770 CLRF SECS ; Clear seconds +0004FC 2B02 00771 INCF MINS ; Increment minutes +0004FE 0E3B 00772 MOVLW .59 ; 60 minutes elapsed? +000500 6502 00773 CPFSGT MINS +000502 0010 00774 RETFIE ;RETURN +000504 00775 STUNDEN +000504 6B02 00776 CLRF MINS ; clear minutes +000506 2B04 00777 INCF HOURS ; Increment hours +000508 0E17 00778 MOVLW .23 ; 24 hours elapsed? +00050A 6504 00779 CPFSGT HOURS +00050C 0010 00780 RETFIE ;RETURN +00050E 00781 TAGE_UND_TAG_DER_WOCHE +00050E 6B04 00782 CLRF HOURS ; Reset hours +000510 0E07 00783 MOVLW .7 +000512 6106 00784 CPFSLT DAY_OF_WEEK +000514 6B06 00785 CLRF DAY_OF_WEEK +000516 2B06 00786 INCF DAY_OF_WEEK +000518 2B07 00787 INCF DAYS +00051A 0E1C 00788 MOVLW .28 +00051C 6507 00789 CPFSGT DAYS +00051E 0010 00790 RETFIE ;RETURN +000520 00791 MEHR_ALS_28_TAGE +000520 0E02 00792 MOVLW .2 +000522 6308 00793 CPFSEQ MONTHS ;FEB? +000524 D??? 00794 BRA NOT_FEB ;NEIN-> +000526 00795 FEB +000526 0E03 00796 MOVLW .3 +000528 1509 00797 ANDWF YEARS,0 ;SCHALTJAHR +00052A E1?? 00798 BNZ NEXT_MONTH ;NEIN-> +00052C 00799 SCHALTJAHR +00052C 0E1D 00800 MOVLW .29 +00052E 6507 00801 CPFSGT DAYS +000530 0010 00802 RETFIE ;RETURN +000532 00803 NEXT_MONTH +000532 0E01 00804 MOVLW .1 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 17 + + +LOC OBJECT CODE LINE SOURCE TEXT + VALUE + +000534 6F07 00805 MOVWF DAYS +000536 2B08 00806 INCF MONTHS +000538 0E12 00807 MOVLW 12 +00053A 6508 00808 CPFSGT MONTHS +00053C 0010 00809 RETFIE ;RETURN +00053E 00810 YEAR +00053E 0E01 00811 MOVLW .1 +000540 6F08 00812 MOVWF MONTHS +000542 2B09 00813 INCF YEARS +000544 0010 00814 RETFIE ;RETURN +000546 00815 NOT_FEB +000546 0E1E 00816 MOVLW .30 +000548 6507 00817 CPFSGT DAYS +00054A 0010 00818 RETFIE +00054C 00819 MEHR_ALS_30_TAGE +00054C 0E04 00820 MOVLW .4 ;APRIL? +00054E 6308 00821 CPFSEQ MONTHS ;SKIP +000550 D??? 00822 BRA NOT_APRIL +000552 D??? 00823 BRA NEXT_MONTH ;APRIL-> +000554 00824 NOT_APRIL +000554 0E06 00825 MOVLW .6 ;JUNI? +000556 6308 00826 CPFSEQ MONTHS +000558 D??? 00827 BRA NOT_JUNI +00055A D??? 00828 BRA NEXT_MONTH ;JUNI-> +00055C 00829 NOT_JUNI +00055C 0E09 00830 MOVLW .9 ;SEPTEMBER? +00055E 6308 00831 CPFSEQ MONTHS +000560 D??? 00832 BRA NOT_SEP +000562 D??? 00833 BRA NEXT_MONTH ;SEPTEMBER-> +000564 00834 NOT_SEP +000564 0E0B 00835 MOVLW .11 ;NOVEMBER? +000566 6308 00836 CPFSEQ MONTHS ;SKIP +000568 0010 00837 RETFIE ;SIND MONATE MIT 31 TAGEN-> +00056A D??? 00838 BRA NEXT_MONTH ;SONST NOVEMBER-> + 00839 ;**********************************************************************************************""""""""" + """" + 00840 ; ENDE MAIN + 00841 ;**********************************************************************************************""""""""" + """" + 00842 ;**********************************************************************************************""""""""" + """" + 00843 ; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN + 00844 ;**********************************************************************************************""""""""" + """" + 00845 end + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 18 + + +SYMBOL TABLE + LABEL VALUE + +A 00000000 +ABDEN 00000000 +ABDOVF 00000007 +ACCESS 00000000 +ACKDT 00000005 +ACKEN 00000004 +ACKSTAT 00000006 +ACQT0 00000003 +ACQT1 00000004 +ACQT2 00000005 +ADCON0 00000FC2 +ADCON1 00000FC1 +ADCON2 00000FC0 +ADCS0 00000000 +ADCS1 00000001 +ADCS2 00000002 +ADDEN 00000003 +ADEN 00000003 +ADFM 00000007 +ADIE 00000006 +ADIF 00000006 +ADIP 00000006 +ADON 00000000 +ADRES 00000FC3 +ADRESH 00000FC4 +ADRESL 00000FC3 +AD_ISR 0000044C +AD_KANAL 00000045 +AN0 00000000 +AN1 00000001 +AN10 00000001 +AN11 00000004 +AN12 00000000 +AN2 00000002 +AN3 00000003 +AN4 00000005 +AN5 00000000 +AN6 00000001 +AN7 00000002 +AN8 00000002 +AN9 00000003 +BANKED 00000001 +BAUDCON 00000FB8 +BAUDCTL 00000FB8 +BCLIE 00000003 +BCLIF 00000003 +BCLIP 00000003 +BF 00000000 +BGST 00000005 +BOR 00000000 +BRG16 00000003 +BRGH 00000002 +BSR 00000FE0 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 19 + + +SYMBOL TABLE + LABEL VALUE + +C 00000000 +C1INV 00000004 +C1OUT 00000006 +C2INV 00000005 +C2OUT 00000007 +CCP1 00000002 +CCP1CON 00000FBD +CCP1IE 00000002 +CCP1IF 00000002 +CCP1IP 00000002 +CCP1M0 00000000 +CCP1M1 00000001 +CCP1M2 00000002 +CCP1M3 00000003 +CCP1X 00000005 +CCP1Y 00000004 +CCP2CON 00000FBA +CCP2IE 00000000 +CCP2IF 00000000 +CCP2IP 00000000 +CCP2M0 00000000 +CCP2M1 00000001 +CCP2M2 00000002 +CCP2M3 00000003 +CCP2X 00000005 +CCP2Y 00000004 +CCP2_PORTB 00000003 +CCP2_PORTC 00000001 +CCPR1 00000FBE +CCPR1H 00000FBF +CCPR1L 00000FBE +CCPR2 00000FBB +CCPR2H 00000FBC +CCPR2L 00000FBB +CFGS 00000006 +CHS0 00000002 +CHS1 00000003 +CHS2 00000004 +CHS3 00000005 +CIS 00000003 +CK 00000006 +CKE 00000006 +CKP 00000004 +CLKI 00000007 +CLKO 00000006 +CLK_ACTIV 00000072 +CLK_SLEEP 00000012 +CM0 00000000 +CM1 00000001 +CM2 00000002 +CMCON 00000FB4 +CMIE 00000006 +CMIF 00000006 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 20 + + +SYMBOL TABLE + LABEL VALUE + +CMIP 00000006 +CREN 00000004 +CS 00000002 +CSRC 00000007 +CVR0 00000000 +CVR1 00000001 +CVR2 00000002 +CVR3 00000003 +CVRCON 00000FB5 +CVREF 00000002 +CVREN 00000007 +CVROE 00000006 +CVRR 00000005 +CVRSS 00000004 +D 00000005 +DAYS 00000007 +DAY_OF_WEEK 00000006 +DC 00000001 +DC1B0 00000004 +DC1B1 00000005 +DC2B0 00000004 +DC2B1 00000005 +DDRA TRISA +DDRB TRISB +DDRC TRISC +DDRD TRISD +DDRE TRISE +DONE 00000001 +D_A 00000005 +EAPIR1 0000004E +EAPIR2 0000004F +ECCP1AS 00000FB6 +ECCPAS0 00000004 +ECCPAS1 00000005 +ECCPAS2 00000006 +ECCPASE 00000007 +EEADR 00000FA9 +EECON1 00000FA6 +EECON2 00000FA7 +EEDATA 00000FA8 +EEIE 00000004 +EEIF 00000004 +EEIP 00000004 +EEPGD 00000007 +EXTERN_INTERRUPTS 00002002 +EXTERN_INT_ADR 00002000 +EXTERN_SUBROUTINES 00002012 +EXTERN_SUB_ADR 00002010 +EXT_CODE 000000FB +EXT_SUB_GO 00000004 +EXT_SUB_STOP 00000005 +FAST 00000001 +FEB 00000526 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 21 + + +SYMBOL TABLE + LABEL VALUE + +FERR 00000002 +FLTS 00000002 +FREE 00000004 +FSR0 00000000 +FSR0H 00000FEA +FSR0L 00000FE9 +FSR1 00000001 +FSR1H 00000FE2 +FSR1L 00000FE1 +FSR2 00000002 +FSR2H 00000FDA +FSR2L 00000FD9 +GCEN 00000007 +GIE 00000007 +GIEH 00000007 +GIEL 00000006 +GO 00000001 +GO_DONE 00000001 +GO_INT 0000004D +GO_SUB 0000004C +HLVDCON 00000FD2 +HLVDEN 00000004 +HLVDIE 00000002 +HLVDIF 00000002 +HLVDIP 00000002 +HLVDL0 00000000 +HLVDL1 00000001 +HLVDL2 00000002 +HLVDL3 00000003 +HLVD_ISR 00000424 +HLVD_LE 0000043C +HOURS 00000004 +HOURS_ALARM 00000005 +IBF 00000007 +IBOV 00000005 +IDLEN 00000007 +INDF0 00000FEF +INDF1 00000FE7 +INDF2 00000FDF +INT0 00000000 +INT0E 00000004 +INT0F 00000001 +INT0IE 00000004 +INT0IF 00000001 +INT1 00000001 +INT1E 00000003 +INT1F 00000000 +INT1IE 00000003 +INT1IF 00000000 +INT1IP 00000006 +INT1P 00000006 +INT2 00000002 +INT2E 00000004 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 22 + + +SYMBOL TABLE + LABEL VALUE + +INT2F 00000001 +INT2IE 00000004 +INT2IF 00000001 +INT2IP 00000007 +INT2P 00000007 +INTCON 00000FF2 +INTCON2 00000FF1 +INTCON3 00000FF0 +INTEDG0 00000006 +INTEDG1 00000005 +INTEDG2 00000004 +INTSRC 00000007 +INT_HANDLER 00000018 +IOFS 00000002 +IPEN 00000007 +IPR1 00000F9F +IPR2 00000FA2 +IRCF0 00000004 +IRCF1 00000005 +IRCF2 00000006 +IRVST 00000005 +IVRST 00000005 +KALT_START 00000100 +KBI0 00000004 +KBI1 00000005 +KBI2 00000006 +KBI3 00000007 +LADESTROM 000001D2 +LATA 00000F89 +LATA0 00000000 +LATA1 00000001 +LATA2 00000002 +LATA3 00000003 +LATA4 00000004 +LATA5 00000005 +LATA6 00000006 +LATA7 00000007 +LATB 00000F8A +LATB0 00000000 +LATB1 00000001 +LATB2 00000002 +LATB3 00000003 +LATB4 00000004 +LATB5 00000005 +LATB6 00000006 +LATB7 00000007 +LATC 00000F8B +LATC0 00000000 +LATC1 00000001 +LATC2 00000002 +LATC3 00000003 +LATC4 00000004 +LATC5 00000005 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 23 + + +SYMBOL TABLE + LABEL VALUE + +LATC6 00000006 +LATC7 00000007 +LATD 00000F8C +LATD0 00000000 +LATD1 00000001 +LATD2 00000002 +LATD3 00000003 +LATD4 00000004 +LATD5 00000005 +LATD6 00000006 +LATD7 00000007 +LATE 00000F8D +LATE0 00000000 +LATE1 00000001 +LATE2 00000002 +LS_OFF_POWER 000001DA +LS_ON_POWER 000001D6 +LVDCON 00000FD2 +LVDEN 00000004 +LVDIE 00000002 +LVDIF 00000002 +LVDIN 00000005 +LVDIP 00000002 +LVDL0 00000000 +LVDL1 00000001 +LVDL2 00000002 +LVDL3 00000003 +LVV0 00000000 +LVV1 00000001 +LVV2 00000002 +LVV3 00000003 +MAIN 0000019E +MAIN2 000001AE +MCLR 00000003 +MEHR_ALS_28_TAGE 00000520 +MEHR_ALS_30_TAGE 0000054C +MINS 00000002 +MINS_ALRAM 00000003 +MINUTEN 000004FA +MONTHS 00000008 +N 00000004 +NEXT_MONTH 00000532 +NON_SYNC 000003D2 +NOT_A 00000005 +NOT_ADDRESS 00000005 +NOT_APRIL 00000554 +NOT_BOR 00000000 +NOT_CS 00000002 +NOT_DONE 00000001 +NOT_FEB 00000546 +NOT_JUNI 0000055C +NOT_MCLR 00000003 +NOT_PD 00000002 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 24 + + +SYMBOL TABLE + LABEL VALUE + +NOT_POR 00000001 +NOT_RBPU 00000007 +NOT_RD 00000000 +NOT_RI 00000004 +NOT_SEP 00000564 +NOT_SS 00000005 +NOT_T1SYNC 00000002 +NOT_T3SYNC 00000002 +NOT_TO 00000003 +NOT_W 00000002 +NOT_WR 00000001 +NOT_WRITE 00000002 +NO_PROG 000003AC +OBF 00000006 +OERR 00000001 +OFF_TIME 00000014 +ON_TIME 00000002 +OSC1 00000007 +OSC2 00000006 +OSCCON 00000FD3 +OSCFIE 00000007 +OSCFIF 00000007 +OSCFIP 00000007 +OSCTUNE 00000F9B +OSTS 00000003 +OV 00000003 +P 00000004 +P1B 00000005 +P1C 00000006 +P1D 00000007 +P1M0 00000006 +P1M1 00000007 +PC 00000FF9 +PCFG0 00000000 +PCFG1 00000001 +PCFG2 00000002 +PCFG3 00000003 +PCL 00000FF9 +PCLATH 00000FFA +PCLATU 00000FFB +PD 00000002 +PDC0 00000000 +PDC1 00000001 +PDC2 00000002 +PDC3 00000003 +PDC4 00000004 +PDC5 00000005 +PDC6 00000006 +PEIE 00000006 +PEN 00000002 +PGC 00000006 +PGD 00000007 +PGM 00000005 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 25 + + +SYMBOL TABLE + LABEL VALUE + +PIE1 00000F9D +PIE2 00000FA0 +PINGS 00000486 +PINGS2 000004AA +PINGW 00000498 +PIR1 00000F9E +PIR2 00000FA1 +PLLEN 00000006 +PLUSW0 00000FEB +PLUSW1 00000FE3 +PLUSW2 00000FDB +POR 00000001 +PORTA 00000F80 +PORTB 00000F81 +PORTC 00000F82 +PORTD 00000F83 +PORTE 00000F84 +POSTDEC0 00000FED +POSTDEC1 00000FE5 +POSTDEC2 00000FDD +POSTINC0 00000FEE +POSTINC1 00000FE6 +POSTINC2 00000FDE +POWER_AUS 000001C2 +POWER_EIN 000001B4 +POWER_OFF_I 0000046A +POWER_OFF_I2 00000478 +POWER_ON_TIME 00000044 +PR2 00000FCB +PREINC0 00000FEC +PREINC1 00000FE4 +PREINC2 00000FDC +PRG_OK_PIC 00000022 +PROD 00000FF3 +PRODH 00000FF4 +PRODL 00000FF3 +PROGRAM_MEMORY 0000039A +PRSEN 00000007 +PSA 00000003 +PSP0 00000000 +PSP1 00000001 +PSP2 00000002 +PSP3 00000003 +PSP4 00000004 +PSP5 00000005 +PSP6 00000006 +PSP7 00000007 +PSPIE 00000007 +PSPIF 00000007 +PSPIP 00000007 +PSPMODE 00000004 +PSSAC0 00000002 +PSSAC1 00000003 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 26 + + +SYMBOL TABLE + LABEL VALUE + +PSSBD0 00000000 +PSSBD1 00000001 +PWM1CON 00000FB7 +R 00000002 +RA0 00000000 +RA1 00000001 +RA2 00000002 +RA3 00000003 +RA4 00000004 +RA5 00000005 +RA6 00000006 +RA7 00000007 +RB0 00000000 +RB1 00000001 +RB2 00000002 +RB3 00000003 +RB4 00000004 +RB5 00000005 +RB6 00000006 +RB7 00000007 +RBIE 00000003 +RBIF 00000000 +RBIP 00000000 +RBPU 00000007 +RC0 00000000 +RC1 00000001 +RC2 00000002 +RC3 00000003 +RC4 00000004 +RC5 00000005 +RC6 00000006 +RC7 00000007 +RCEN 00000003 +RCIDL 00000006 +RCIE 00000005 +RCIF 00000005 +RCIP 00000005 +RCMT 00000006 +RCON 00000FD0 +RCREG 00000FAE +RCSTA 00000FAB +RD 00000000 +RD0 00000000 +RD1 00000001 +RD16 00000007 +RD2 00000002 +RD3 00000003 +RD4 00000004 +RD5 00000005 +RD6 00000006 +RD7 00000007 +RE0 00000000 +RE1 00000001 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 27 + + +SYMBOL TABLE + LABEL VALUE + +RE2 00000002 +RE3 00000003 +READ_BLOCK 000000A1 +REGA 0000000A +REGB 0000000B +REGC 0000000C +REGD 0000000D +REQ_BLOCK 000000A0 +REQ_RTCD_FROM_MCF 00000002 +REQ_RTCD_FROM_PIC 00000001 +RESETEN 00000256 +RESET_OFF_TIME 00000004 +RESET_ON_TIME 00000002 +RI 00000004 +RSEN 00000001 +RTCD_FROM_MCF 00000082 +RTCD_FROM_PIC 00000081 +RTC_ISR 00000450 +RTC_RAM 0000000E +RX 00000007 +RX9 00000006 +RX9D 00000000 +RXDTP 00000005 +RX_B 00000049 +RX_BUFFER 00000100 +RX_ISR 00000288 +RX_ISR1 000002A4 +RX_ISR2 000002B0 +RX_ISR3 000002C8 +RX_ISR4 000002F6 +RX_ISR5 00000304 +RX_ISR6 00000312 +RX_ISR7 00000350 +RX_ISR8 000003B0 +RX_ISR9 000003BC +RX_RB3B2 00000334 +RX_RB3BOK 00000322 +RX_STATUS 0000004A +RX_SYNC2 000003D8 +RX_SYNC3 000003EA +RX_SYNC4 000003FC +RX_SYNC_START 000003C0 +RX_WAIT1 00000408 +RX_WAIT2 00000410 +RX_WAIT3 00000418 +R_W 00000002 +S 00000003 +SBOREN 00000006 +SCHALTJAHR 0000052C +SCK 00000003 +SCKP 00000004 +SCL 00000003 +SCS0 00000000 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 28 + + +SYMBOL TABLE + LABEL VALUE + +SCS1 00000001 +SDA 00000004 +SDI 00000004 +SDO 00000005 +SECS 00000000 +SECS_ALARM 00000001 +SEKUNDEN 000004B0 +SEK_2 000004CA +SEK_3 000004DC +SEK_4 000004F0 +SEK_NPA 000004C4 +SEN 00000000 +SENDB 00000003 +SEND_RTC_REG 00000232 +SEND_RTC_TIME 00000002 +SERIAL_OFF 000001DE +SERIAL_ON 000001EA +SMP 00000007 +SP0 00000000 +SP1 00000001 +SP2 00000002 +SP3 00000003 +SP4 00000004 +SPBRG 00000FAF +SPBRGH 00000FB0 +SPEN 00000007 +SREN 00000005 +SS 00000005 +SSPADD 00000FC8 +SSPBUF 00000FC9 +SSPCON1 00000FC6 +SSPCON2 00000FC5 +SSPEN 00000005 +SSPIE 00000003 +SSPIF 00000003 +SSPIP 00000003 +SSPM0 00000000 +SSPM1 00000001 +SSPM2 00000002 +SSPM3 00000003 +SSPOV 00000006 +SSPSTAT 00000FC7 +STATUS 00000FD8 +STKFUL 00000007 +STKOVF 00000007 +STKPTR 00000FFC +STKUNF 00000006 +STUNDEN 00000504 +SWDTE 00000000 +SWDTEN 00000000 +SYNC 00000004 +SYNC1 000000FF +SYNC1_DATA 00000041 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 29 + + +SYMBOL TABLE + LABEL VALUE + +SYNC2 000000FE +SYNC2_DATA 00000043 +SYNC3 000000FD +SYNC3_DATA 00000050 +SYNC4 000000FC +SYNC4_DATA 00000046 +T08BIT 00000006 +T0CKI 00000004 +T0CON 00000FD5 +T0CS 00000005 +T0IE 00000005 +T0IF 00000002 +T0PS0 00000000 +T0PS1 00000001 +T0PS2 00000002 +T0SE 00000004 +T13CKI 00000000 +T1CKI 00000000 +T1CKPS0 00000004 +T1CKPS1 00000005 +T1CON 00000FCD +T1OSCEN 00000003 +T1OSI 00000001 +T1OSO 00000000 +T1RUN 00000006 +T1SYNC 00000002 +T2CKPS0 00000000 +T2CKPS1 00000001 +T2CON 00000FCA +T2OUTPS0 00000003 +T2OUTPS1 00000004 +T2OUTPS2 00000005 +T2OUTPS3 00000006 +T3CCP1 00000003 +T3CCP2 00000006 +T3CKPS0 00000004 +T3CKPS1 00000005 +T3CON 00000FB1 +T3SYNC 00000002 +TABLAT 00000FF5 +TAGE_UND_TAG_DER_WOCHE 0000050E +TASTE 00000208 +TASTE_OFF_TIME 00000043 +TASTE_ON_TIME 00000042 +TBLPTR 00000FF6 +TBLPTRH 00000FF7 +TBLPTRL 00000FF6 +TBLPTRU 00000FF8 +TG_END 00000250 +TG_JA 00000222 +TG_OFF_POWER 00000248 +TG_ON_POWER 0000022C +TG_ON_POWER2 00000238 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 30 + + +SYMBOL TABLE + LABEL VALUE + +TG_ON_POWER3 0000023E +TICKS 00000041 +TIMER_HB 000000F0 +TIME_MAX 000000A0 +TMR0H 00000FD7 +TMR0IE 00000005 +TMR0IF 00000002 +TMR0IP 00000002 +TMR0L 00000FD6 +TMR0ON 00000007 +TMR1CS 00000001 +TMR1H 00000FCF +TMR1IE 00000000 +TMR1IF 00000000 +TMR1IP 00000000 +TMR1L 00000FCE +TMR1ON 00000000 +TMR2 00000FCC +TMR2IE 00000001 +TMR2IF 00000001 +TMR2IP 00000001 +TMR2ON 00000002 +TMR3CS 00000001 +TMR3H 00000FB3 +TMR3IE 00000001 +TMR3IF 00000001 +TMR3IP 00000001 +TMR3L 00000FB2 +TMR3ON 00000000 +TO 00000003 +TOS 00000FFD +TOSH 00000FFE +TOSL 00000FFD +TOSU 00000FFF +TRISA 00000F92 +TRISA0 00000000 +TRISA1 00000001 +TRISA2 00000002 +TRISA3 00000003 +TRISA4 00000004 +TRISA5 00000005 +TRISA6 00000006 +TRISA7 00000007 +TRISB 00000F93 +TRISB0 00000000 +TRISB1 00000001 +TRISB2 00000002 +TRISB3 00000003 +TRISB4 00000004 +TRISB5 00000005 +TRISB6 00000006 +TRISB7 00000007 +TRISC 00000F94 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 31 + + +SYMBOL TABLE + LABEL VALUE + +TRISC0 00000000 +TRISC1 00000001 +TRISC2 00000002 +TRISC3 00000003 +TRISC4 00000004 +TRISC5 00000005 +TRISC6 00000006 +TRISC7 00000007 +TRISD 00000F95 +TRISD0 00000000 +TRISD1 00000001 +TRISD2 00000002 +TRISD3 00000003 +TRISD4 00000004 +TRISD5 00000005 +TRISD6 00000006 +TRISD7 00000007 +TRISE 00000F96 +TRISE0 00000000 +TRISE1 00000001 +TRISE2 00000002 +TRMT 00000001 +TUN0 00000000 +TUN1 00000001 +TUN2 00000002 +TUN3 00000003 +TUN4 00000004 +TX 00000006 +TX9 00000006 +TX9D 00000000 +TXCKP 00000004 +TXEN 00000005 +TXIE 00000004 +TXIF 00000004 +TXIP 00000004 +TXREG 00000FAD +TXSTA 00000FAC +TX_BUFFER 00000180 +TX_ISR 0000025E +TX_ISR1 00000276 +TX_ISR2 00000286 +TX_ISR_FERTIG 0000026E +TX_STATUS 0000004B +UA 00000001 +U_ERR 00000046 +U_ERR_PW_AUS 00000005 +U_ERR_TIME 00000047 +U_MIN_TO_MCF 00000003 +U_POWER_IN 00000048 +VCFG0 00000004 +VCFG1 00000005 +VDIRMAG 00000007 +VPP 00000003 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 32 + + +SYMBOL TABLE + LABEL VALUE + +VREFN 00000002 +VREFP 00000003 +W 00000000 +WAIT_LVDOK 00000434 +WARTEN 000001A8 +WCOL 00000007 +WDTCON 00000FD1 +WR 00000001 +WREG 00000FE8 +WREN 00000002 +WRERR 00000003 +WRITE_BLOCK 000000A2 +WRITE_WORD_TO_HREGS 00000390 +WUE 00000001 +YEAR 0000053E +YEARS 00000009 +Z 00000002 +_BOREN_NOSLP_2L 000000FD +_BOREN_OFF_2L 000000F9 +_BOREN_ON_2L 000000FB +_BOREN_SBORDIS_2L 000000FF +_BORV_0_2L 000000E7 +_BORV_1_2L 000000EF +_BORV_2_2L 000000F7 +_BORV_3_2L 000000FF +_CCP2MX_PORTBE_3H 000000FE +_CCP2MX_PORTC_3H 000000FF +_CONFIG1H 00300001 +_CONFIG2H 00300003 +_CONFIG2L 00300002 +_CONFIG3H 00300005 +_CONFIG4L 00300006 +_CONFIG5H 00300009 +_CONFIG5L 00300008 +_CONFIG6H 0030000B +_CONFIG6L 0030000A +_CONFIG7H 0030000D +_CONFIG7L 0030000C +_CP0_OFF_5L 000000FF +_CP0_ON_5L 000000FE +_CP1_OFF_5L 000000FF +_CP1_ON_5L 000000FD +_CP2_OFF_5L 000000FF +_CP2_ON_5L 000000FB +_CP3_OFF_5L 000000FF +_CP3_ON_5L 000000F7 +_CPB_OFF_5H 000000FF +_CPB_ON_5H 000000BF +_CPD_OFF_5H 000000FF +_CPD_ON_5H 0000007F +_DEBUG_OFF_4L 000000FF +_DEBUG_ON_4L 0000007F +_DEVID1 003FFFFE + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 33 + + +SYMBOL TABLE + LABEL VALUE + +_DEVID2 003FFFFF +_EBTR0_OFF_7L 000000FF +_EBTR0_ON_7L 000000FE +_EBTR1_OFF_7L 000000FF +_EBTR1_ON_7L 000000FD +_EBTR2_OFF_7L 000000FF +_EBTR2_ON_7L 000000FB +_EBTR3_OFF_7L 000000FF +_EBTR3_ON_7L 000000F7 +_EBTRB_OFF_7H 000000FF +_EBTRB_ON_7H 000000BF +_FCMEN_OFF_1H 000000BF +_FCMEN_ON_1H 000000FF +_IDLOC0 00200000 +_IDLOC1 00200001 +_IDLOC2 00200002 +_IDLOC3 00200003 +_IDLOC4 00200004 +_IDLOC5 00200005 +_IDLOC6 00200006 +_IDLOC7 00200007 +_IESO_OFF_1H 0000007F +_IESO_ON_1H 000000FF +_LPT1OSC_OFF_3H 000000FB +_LPT1OSC_ON_3H 000000FF +_LVP_OFF_4L 000000FB +_LVP_ON_4L 000000FF +_MCLRE_OFF_3H 0000007F +_MCLRE_ON_3H 000000FF +_OSC_ECIO6_1H 000000F5 +_OSC_EC_1H 000000F4 +_OSC_HSPLL_1H 000000F6 +_OSC_HS_1H 000000F2 +_OSC_INTIO67_1H 000000F8 +_OSC_INTIO7_1H 000000F9 +_OSC_LP_1H 000000F0 +_OSC_RCIO6_1H 000000F7 +_OSC_RC_1H 000000F3 +_OSC_XT_1H 000000F1 +_PBADEN_OFF_3H 000000FD +_PBADEN_ON_3H 000000FF +_PWRT_OFF_2L 000000FF +_PWRT_ON_2L 000000FE +_STVREN_OFF_4L 000000FE +_STVREN_ON_4L 000000FF +_WDTPS_1024_2H 000000F5 +_WDTPS_128_2H 000000EF +_WDTPS_16384_2H 000000FD +_WDTPS_16_2H 000000E9 +_WDTPS_1_2H 000000E1 +_WDTPS_2048_2H 000000F7 +_WDTPS_256_2H 000000F1 +_WDTPS_2_2H 000000E3 + MPASM 5.35 FIREBEE1.ASM 10-1-2010 13:06:42 PAGE 34 + + +SYMBOL TABLE + LABEL VALUE + +_WDTPS_32768_2H 000000FF +_WDTPS_32_2H 000000EB +_WDTPS_4096_2H 000000F9 +_WDTPS_4_2H 000000E5 +_WDTPS_512_2H 000000F3 +_WDTPS_64_2H 000000ED +_WDTPS_8192_2H 000000FB +_WDTPS_8_2H 000000E7 +_WDT_OFF_2H 000000FE +_WDT_ON_2H 000000FF +_WRT0_OFF_6L 000000FF +_WRT0_ON_6L 000000FE +_WRT1_OFF_6L 000000FF +_WRT1_ON_6L 000000FD +_WRT2_OFF_6L 000000FF +_WRT2_ON_6L 000000FB +_WRT3_OFF_6L 000000FF +_WRT3_ON_6L 000000F7 +_WRTB_OFF_6H 000000FF +_WRTB_ON_6H 000000BF +_WRTC_OFF_6H 000000FF +_WRTC_ON_6H 000000DF +_WRTD_OFF_6H 000000FF +_WRTD_ON_6H 0000007F +_XINST_OFF_4L 000000BF +_XINST_ON_4L 000000FF +__18F4520 00000001 +free 00000040 + +Errors : 0 +Warnings : 0 reported, 0 suppressed +Messages : 0 reported, 0 suppressed + + \ No newline at end of file diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.map b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.map new file mode 100644 index 0000000..678b3b3 --- /dev/null +++ b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.map @@ -0,0 +1,188 @@ +MPLINK 4.35, Linker +Linker Map File - Created Fri Oct 01 13:06:43 2010 + + Section Info + Section Type Address Location Size(Bytes) + --------- --------- --------- --------- --------- + Reset_Vector code 0x000000 program 0x000002 + .cinit romdata 0x000002 program 0x000002 + HIGH_INT_VEC code 0x000008 program 0x000004 + LOW_INT_VEC code 0x000018 program 0x00004a + .code code 0x000100 program 0x00046c + + + + Program Memory Usage + Start End + --------- --------- + 0x000000 0x000003 + 0x000008 0x00000b + 0x000018 0x000061 + 0x000100 0x00056b + 1214 out of 33048 program addresses used, program memory utilization is 3% + + + + Symbols - Sorted by Name + Name Address Location Storage File + --------- --------- --------- --------- --------- + AD_ISR 0x00044c program static C:\FireBee\MLAB\firebee1\firebee1.asm + FEB 0x000526 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000424 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00043c program static C:\FireBee\MLAB\firebee1\firebee1.asm + INT_HANDLER 0x000018 program static C:\FireBee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001da program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN2 0x0001ae program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x000520 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x00054c program static C:\FireBee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0004fa program static C:\FireBee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x000532 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0003d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x000554 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x000546 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x00055c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000564 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NO_PROG 0x0003ac program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS 0x000486 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS2 0x0004aa program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGW 0x000498 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001b4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x00046a program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000478 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PROGRAM_MEMORY 0x00039a program static C:\FireBee\MLAB\firebee1\firebee1.asm + RESETEN 0x000256 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000450 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR 0x000288 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR1 0x0002a4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR2 0x0002b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR3 0x0002c8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR4 0x0002f6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR5 0x000304 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR6 0x000312 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR7 0x000350 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR8 0x0003b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR9 0x0003bc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3B2 0x000334 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3BOK 0x000322 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC2 0x0003d8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC3 0x0003ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC4 0x0003fc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC_START 0x0003c0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT1 0x000408 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT2 0x000410 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT3 0x000418 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x00052c program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x0004b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_2 0x0004ca program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_3 0x0004dc program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_4 0x0004f0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x0004c4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x000232 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_OFF 0x0001de program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_ON 0x0001ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + STUNDEN 0x000504 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x00050e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TASTE 0x000208 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_END 0x000250 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_JA 0x000222 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000248 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x00022c program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000238 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x00023e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00025e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000276 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR2 0x000286 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00026e program static C:\FireBee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000434 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WRITE_WORD_TO_HREGS 0x000390 program static C:\FireBee\MLAB\firebee1\firebee1.asm + YEAR 0x00053e program static C:\FireBee\MLAB\firebee1\firebee1.asm + + + + Symbols - Sorted by Address + Name Address Location Storage File + --------- --------- --------- --------- --------- + INT_HANDLER 0x000018 program static C:\FireBee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\FireBee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MAIN2 0x0001ae program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001b4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001da program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_OFF 0x0001de program static C:\FireBee\MLAB\firebee1\firebee1.asm + SERIAL_ON 0x0001ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + TASTE 0x000208 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_JA 0x000222 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x00022c program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x000232 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000238 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x00023e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000248 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TG_END 0x000250 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RESETEN 0x000256 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00025e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00026e program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000276 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TX_ISR2 0x000286 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR 0x000288 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR1 0x0002a4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR2 0x0002b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR3 0x0002c8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR4 0x0002f6 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR5 0x000304 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR6 0x000312 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3BOK 0x000322 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_RB3B2 0x000334 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR7 0x000350 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WRITE_WORD_TO_HREGS 0x000390 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PROGRAM_MEMORY 0x00039a program static C:\FireBee\MLAB\firebee1\firebee1.asm + NO_PROG 0x0003ac program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR8 0x0003b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_ISR9 0x0003bc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC_START 0x0003c0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0003d2 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC2 0x0003d8 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC3 0x0003ea program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_SYNC4 0x0003fc program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT1 0x000408 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT2 0x000410 program static C:\FireBee\MLAB\firebee1\firebee1.asm + RX_WAIT3 0x000418 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000424 program static C:\FireBee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000434 program static C:\FireBee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00043c program static C:\FireBee\MLAB\firebee1\firebee1.asm + AD_ISR 0x00044c program static C:\FireBee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000450 program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x00046a program static C:\FireBee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000478 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS 0x000486 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGW 0x000498 program static C:\FireBee\MLAB\firebee1\firebee1.asm + PINGS2 0x0004aa program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x0004b0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x0004c4 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_2 0x0004ca program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_3 0x0004dc program static C:\FireBee\MLAB\firebee1\firebee1.asm + SEK_4 0x0004f0 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0004fa program static C:\FireBee\MLAB\firebee1\firebee1.asm + STUNDEN 0x000504 program static C:\FireBee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x00050e program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x000520 program static C:\FireBee\MLAB\firebee1\firebee1.asm + FEB 0x000526 program static C:\FireBee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x00052c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x000532 program static C:\FireBee\MLAB\firebee1\firebee1.asm + YEAR 0x00053e program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x000546 program static C:\FireBee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x00054c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x000554 program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x00055c program static C:\FireBee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000564 program static C:\FireBee\MLAB\firebee1\firebee1.asm + + diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcp b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcp new file mode 100644 index 0000000..45e7dcc --- /dev/null +++ b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcp @@ -0,0 +1,53 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +device=PIC18F4520 +[PATH_INFO] +BuildDirPolicy=BuildDirIsProjectDir +dir_src= +dir_bin= +dir_tmp= +dir_sin= +dir_inc= +dir_lib= +dir_lkr= +[CAT_FILTERS] +filter_src=*.asm +filter_inc=*.h;*.inc +filter_obj=*.o +filter_lib=*.lib +filter_lkr=*.lkr +[CAT_SUBFOLDERS] +subfolder_src= +subfolder_inc= +subfolder_obj= +subfolder_lib= +subfolder_lkr= +[FILE_SUBFOLDERS] +file_000=. +file_001=. +[GENERATED_FILES] +file_000=no +file_001=no +[OTHER_FILES] +file_000=no +file_001=no +[FILE_INFO] +file_000=firebee1.asm +file_001=C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr +[SUITE_INFO] +suite_guid={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +suite_state= +[TOOL_SETTINGS] +TS{DD2213A8-6310-47B1-8376-9430CDFC013F}= +TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}= +[INSTRUMENTED_TRACE] +enable=0 +transport=0 +format=0 +[CUSTOM_BUILD] +Pre-Build= +Pre-BuildEnabled=1 +Post-Build= +Post-BuildEnabled=1 diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcs b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcs new file mode 100644 index 0000000..242fa7b --- /dev/null +++ b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcs @@ -0,0 +1,71 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 +[File000] +Location=C:\FireBee\MLAB\firebee1\firebee1.o +Folder=Intermediary +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File001] +Location=C:\FireBee\MLAB\firebee1\firebee1.err +Folder=Intermediary +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File002] +Location=C:\FireBee\MLAB\firebee1\firebee1.lst +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString= +TraceCmdString= +DebugOptions= +[File003] +Location=C:\FireBee\MLAB\firebee1\firebee1.cof +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TraceCmdString= +DebugOptions= +[File004] +Location=C:\FireBee\MLAB\firebee1\firebee1.hex +Folder=Output +DeviceName=PIC18F4520 +LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484} +LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C} +LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)|| +SOLK=|firebee1.asm|||||||C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr|| +SuiteArgsString= +ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W +TraceCmdString= +DebugOptions= +[TOOL_LOC_STAMPS] +tool_loc{49D3CA3F-D9A3-4518-9943-226A347E8CC7}=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe +tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcw b/BaS_codewarrior/FireBee/MLAB/firebee1/firebee1.mcw new file mode 100644 index 0000000000000000000000000000000000000000..74deeebf5b6100924ee5ebf2631438d976dfbda0 GIT binary patch literal 33280 zcmeHQ3vgUj89tj(+Ab|kN*}Q=La0z`37a&e8?d&?X46&@vL=NTnnG@NZ_>4!-DMxy zwyaVf)d~m|7_CeTNQH{%SOle_j+Ge|2b9X-3@`VxSH<7pMo80B)cGI3HlyPs3kog_l|W$7rbDm!@`z2>vB77G4pC9}}CvO!008 zW{hkY=gmlN@8$cPmuQbWN+GnI0}XenXot>#(D8RH?quvhQa}A->(DJh4|+c!qWBv| z8^}PL(BNyLzo<4b|8k%aXaYPyGvEbUfEB<>U={FL-~yl(Xag<;+5tbnzI4Fv1XcqV0T%;Zz#4%0 zm%?8QbOY;v%Ye&)9zX-~`Cz;s>Fa?Y@OfYZ5CR5(Fc1Nvz!d;jP8>)8Nnj920UH6X z=FPyBKpOZ0@I~M%U<<&pZciqn$pjaq=e+KgU`%h)_3pOT#-{E*M0$0-CKIUE;se~y zJEOWksD&z9cux4hk_S7n8_d;V2d*`CW-WR9gZJ!l$L~Io^Zm7umh|A1>4r=YE!M%h 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code 0x000000 program 0x000004 + .cinit romdata 0x000004 program 0x000002 + LOW_INT_VEC code 0x000018 program 0x00004a + .code code 0x000100 program 0x00033c + + + + Program Memory Usage + Start End + --------- --------- + 0x000000 0x000005 + 0x000018 0x000061 + 0x000100 0x00043b + 908 out of 33048 program addresses used, program memory utilization is 2% + + + + Symbols - Sorted by Name + Name Address Location Storage File + --------- --------- --------- --------- --------- + AD_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + FEB 0x0003ee program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000300 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00031a program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER 0x00001e program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER2 0x00002e program static C:\firebee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\firebee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001de program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x0003e6 program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x000414 program static C:\firebee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0003c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x0003fa program static C:\firebee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0002ae program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x00041e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x00040e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x000428 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000432 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS 0x000368 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS2 0x000380 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001a6 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x000346 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000356 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR 0x000256 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR1 0x000268 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR2 0x000274 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RFM 0x000290 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RRFP 0x000280 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC2 0x0002b4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC3 0x0002c6 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC4 0x0002d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC_START 0x00029c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_UNBEK 0x00027c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT1 0x0002e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT2 0x0002ec program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT3 0x0002f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RESETEN 0x000232 program static C:\firebee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x0003f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x000386 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_2 0x0003ac program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x00039c program static C:\firebee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x00020c program static C:\firebee\MLAB\firebee1\firebee1.asm + STUNDEN 0x0003ca program static C:\firebee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x0003d4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TASTE 0x0001e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_END 0x00022c program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_JA 0x0001fa program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000224 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x000206 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000212 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x000218 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00023c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000254 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00024c program static C:\firebee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000312 program static C:\firebee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a0 program static C:\firebee\MLAB\firebee1\firebee1.asm + YEAR 0x000406 program static C:\firebee\MLAB\firebee1\firebee1.asm + + + + Symbols - Sorted by Address + Name Address Location Storage File + --------- --------- --------- --------- --------- + INT_HANDLER 0x00001e program static C:\firebee\MLAB\firebee1\firebee1.asm + INT_HANDLER2 0x00002e program static C:\firebee\MLAB\firebee1\firebee1.asm + KALT_START 0x000100 program static C:\firebee\MLAB\firebee1\firebee1.asm + MAIN 0x00019e program static C:\firebee\MLAB\firebee1\firebee1.asm + WARTEN 0x0001a0 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_EIN 0x0001a6 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_AUS 0x0001c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + LADESTROM 0x0001d2 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_ON_POWER 0x0001d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + LS_OFF_POWER 0x0001de program static C:\firebee\MLAB\firebee1\firebee1.asm + TASTE 0x0001e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_JA 0x0001fa program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER 0x000206 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEND_RTC_REG 0x00020c program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER2 0x000212 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_ON_POWER3 0x000218 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_OFF_POWER 0x000224 program static C:\firebee\MLAB\firebee1\firebee1.asm + TG_END 0x00022c program static C:\firebee\MLAB\firebee1\firebee1.asm + RESETEN 0x000232 program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR 0x00023c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR_FERTIG 0x00024c program static C:\firebee\MLAB\firebee1\firebee1.asm + TX_ISR1 0x000254 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR 0x000256 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR1 0x000268 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_ISR2 0x000274 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_UNBEK 0x00027c program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RRFP 0x000280 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_RFM 0x000290 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC_START 0x00029c program static C:\firebee\MLAB\firebee1\firebee1.asm + NON_SYNC 0x0002ae program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC2 0x0002b4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC3 0x0002c6 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_SYNC4 0x0002d8 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT1 0x0002e4 program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT2 0x0002ec program static C:\firebee\MLAB\firebee1\firebee1.asm + RC_WAIT3 0x0002f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_ISR 0x000300 program static C:\firebee\MLAB\firebee1\firebee1.asm + WAIT_LVDOK 0x000312 program static C:\firebee\MLAB\firebee1\firebee1.asm + HLVD_LE 0x00031a program static C:\firebee\MLAB\firebee1\firebee1.asm + RTC_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + AD_ISR 0x000326 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I 0x000346 program static C:\firebee\MLAB\firebee1\firebee1.asm + POWER_OFF_I2 0x000356 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS 0x000368 program static C:\firebee\MLAB\firebee1\firebee1.asm + PINGS2 0x000380 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEKUNDEN 0x000386 program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_NPA 0x00039c program static C:\firebee\MLAB\firebee1\firebee1.asm + SEK_2 0x0003ac program static C:\firebee\MLAB\firebee1\firebee1.asm + MINUTEN 0x0003c0 program static C:\firebee\MLAB\firebee1\firebee1.asm + STUNDEN 0x0003ca program static C:\firebee\MLAB\firebee1\firebee1.asm + TAGE_UND_TAG_DER_WOCHE 0x0003d4 program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_28_TAGE 0x0003e6 program static C:\firebee\MLAB\firebee1\firebee1.asm + FEB 0x0003ee program static C:\firebee\MLAB\firebee1\firebee1.asm + SCHALTJAHR 0x0003f4 program static C:\firebee\MLAB\firebee1\firebee1.asm + NEXT_MONTH 0x0003fa program static C:\firebee\MLAB\firebee1\firebee1.asm + YEAR 0x000406 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_FEB 0x00040e program static C:\firebee\MLAB\firebee1\firebee1.asm + MEHR_ALS_30_TAGE 0x000414 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_APRIL 0x00041e program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_JUNI 0x000428 program static C:\firebee\MLAB\firebee1\firebee1.asm + NOT_SEP 0x000432 program static C:\firebee\MLAB\firebee1\firebee1.asm + + diff --git a/BaS_codewarrior/FireBee/MLAB/firebee1/readme.txt b/BaS_codewarrior/FireBee/MLAB/firebee1/readme.txt new file mode 100644 index 0000000..4f5b8f3 --- /dev/null +++ b/BaS_codewarrior/FireBee/MLAB/firebee1/readme.txt @@ -0,0 +1,125 @@ + PS2 -> Atari /Amiga Mouse Adapter + ~~~~~~~~~~~~~~~~~~~~~~~ + + + Version 1.4 July 2010 + + +Due to the short supply of mice for the Atari computers I decided to build an adapter that would allow me to use a serial mouse on my Atari, but even these are getting a bit old now, so I got the soldering iron out again and here's the result. A PS2 Mouse adapter for the Atari. It supports a standard PS2 mouse with 2 or 3 buttons and can also be used with the Microsoft optical IntelliMouse that comes with a USB to PS2 adapter. The middle button on the PS2 mouse is used as a left click and hold function for easy selection. Click the middle button again to release. Now for the bad news, for some reason Microsoft mice don't support the middle button in standard PS2 mode. :-( + +Please don't shout at me all you Atari users but as an added feature if you change a link then the adapter can be used with an Amiga as well. + + +All files, programs etc contained in this archive are copright 2010 by Tom Kirk. Personal use is allowed but any commercial use is not allowed. Please feel free to use my work but don't rip me off. + + + + Files in this archive. + ~~~~~~~~~~~~~~~~~~~~~~ + +readme.txt This text file +circuit.bmp Picture of circuit in bitmap format +PS2Atari_v1_4.hex Object code of the PIC16F84 program in Intel hex +PS2Atari_v1_4.asm Source code of the PIC16F84 program +pcbtop.bmp Top layer of the PCB in bitmap format +pcbbot.bmp Bottom layer of the PCB in bitmap format + + + + Technical Details. + ~~~~~~~~~~~~~~~~~~ + +When the PS2 mouse is moved or a button changes state a packet of data is sent, my circuit decodes this data and then simulates the Atari mouse. + +The circuit consists of a single microcontroller that contains a program to do the conversion. The circuit is shown in the file circuit.bmp + +The microcontroller (PIC) can be either a PIC16C84 or PIC16F84 or PIC16F84A. + +The PIC (IC1) needs to be programmed with the program. +The program is supplied in two forms PS2Atari_v1_4.hex is an object code file in Intel hex and can be read by most programmers capable of programming the PIC + +PS2Atari_v1_4.asm is the source code of the program and can be assembled with the free MPLAB / MPASM software from Microchip if you wish to create your own object file. Note needs "Disable case sensitivity" under build options setting in MPLAB to assemble without errors. + +The PIC should be programmed with oscillator as XT, watchdog disabled, powerup timer enabled and code protection off. (No point code protecting a freely available program.) + +The source code and object code is compatible with all the PIC microcontrollers listed above. + +I've built mine using a printed circuit board but it's small enough to be built using a small piece of stripboard. + +On my PCB I have a 6 pin mini din socket at one end and a 9 pin D type socket at the other. I can then use a standard port extender lead to connect to the Atari. I've found that a 9 pin PC serial extension lead can also be used for this as well if you remove the fastening screws. + +If you decide to build one on a piece of stripboard it will be easier to use cable mounted sockets as PCB types don't fit onto a stripboard. + +Once built the board can be mounted into a small plastic box. + +No special software is required on the Atari and it will work with all software. +Your favourite mouse accelerator program may be used if required. + + + + Parts list. + ~~~~~~~~~~~ + +IC1 PIC16F84A or PIC16F84 or PIC16C84 + +Fi1 4 MHz Ceramic resonator + +R1 10K +R2 10K + +C1 4.7 uF +C2 0.1 uF + +All capacitors should be rated at 16V or more. + +CN1 6 pin mini din PCB mounting socket +CN2 9 Pin D type PCB mounting socket + + +JP1 3 pin header and 2 way link + + +If building on a piece of stripboard I suggest using cable mounting types of connectors and use a small piece of multicore cable between the sockets and the stripboard. You will find the PCB sockets do not fit on a piece of stripboard. + +If you don't need the switchable Atari/Amiga support forget the 3 pin header and just use a wire link instead. + + + + History. + ~~~~~~~~ + +Version 1.4 July 2010 +Unused Pin RA4 now correctly set as an imput. +(Pin is tied to +5V on PCB for easier PCB routing.) +My oversight when transfering from prototype to PCB. +Thanks to Luciano for informing me. + +Version 1.3 Released March 2010 +Corrected a bug in button routine preventing both buttons being active together under certain conditions. +Thanks to Oliver Fleischmann for informing me. +(Can't believe it taken 6 Years for this bug to show itself!!) + +Version 1.2 Released March 2009 +Changed left/right button outputs to fake open collector. +Needed to stop conflits when using a joystick pluged into other port. + +Version 1.1 Released September 2004. +Added support for the Amiga and added the middle button support. + +Version 1.0 Never released. +My original version for the Atari only. + + + + Help. + ~~~~~ + +If you need further information or help then contact me at tgkirk@aol.com + +Please allow a few days for a reply as I have other commitments as well. + + Tom Kirk July 2010 + +P.S. I also have on my web site a Playstation controller to Atari adapter and a PC viewer for Atari format picture files. + + http://www.tgkirk.110mb.com diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder.h new file mode 100644 index 0000000..3d4f13c --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M68K_BYTEORDER_H +#define _M68K_BYTEORDER_H + +#include "types.h" + +#ifdef __GNUC__ +#define __sw16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define __sw32(x) \ + ((__u32)( \ + (((__u32)(x)) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x)) >> 24) )) + +extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +{ + unsigned result = *addr; + return __sw16(result); +} + +extern __inline__ void st_le16(volatile unsigned short *addr, + const unsigned val) +{ + *addr = __sw16(val); +} + +extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +{ + unsigned result = *addr; + return __sw32(result); +} + +extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +{ + *addr = __sw32(val); +} + +#if 0 +/* alas, egcs sounds like it has a bug in this code that doesn't use the + inline asm correctly, and can cause file corruption. Until I hear that + it's fixed, I can live without the extra speed. I hope. */ +#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) +#if 0 +# define __arch_swab16(x) ld_le16(&x) +# define __arch_swab32(x) ld_le32(&x) +#else +static __inline__ __attribute__ ((const)) +__u16 ___arch__swab16(__u16 value) +{ + return __sw16(value); +} + +static __inline__ __attribute__ ((const)) +__u32 ___arch__swab32(__u32 value) +{ + return __sw32(value); +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* 0 */ + +#endif + +/* The same, but returns converted value from the location pointer by addr. */ +#define __arch__swab16p(addr) ld_le16(addr) +#define __arch__swab32p(addr) ld_le32(addr) + +/* The same, but do the conversion in situ, ie. put the value back to addr. */ +#define __arch__swab16s(addr) st_le16(addr,*addr) +#define __arch__swab32s(addr) st_le32(addr,*addr) +#endif + +#endif /* __GNUC__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#define __BYTEORDER_HAS_U64__ +#endif +#include "byteorder/big_endian.h" + +#endif /* _M68K_BYTEORDER_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h new file mode 100644 index 0000000..fbdea2c --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __BIG_ENDIAN + +#include "swab.h" + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___swab64((x)) +#define __constant_le64_to_cpu(x) ___swab64((x)) +#define __constant_cpu_to_le32(x) ___swab32((x)) +#define __constant_le32_to_cpu(x) ___swab32((x)) +#define __constant_cpu_to_le16(x) ___swab16((x)) +#define __constant_le16_to_cpu(x) ___swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64*)(x)) +#define __be64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_be32p(x) (*(__u32*)(x)) +#define __be32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_be16p(x) (*(__u16*)(x)) +#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include "generic.h" + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h new file mode 100644 index 0000000..e3db5cc --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h @@ -0,0 +1,180 @@ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +//#if defined(__KERNEL__) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +//#endif + + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); + + +#if defined(__GNUC__) && (__GNUC__ >= 2) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h new file mode 100644 index 0000000..b6c67eb --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __LITTLE_ENDIAN + +#include "swab.h" + +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + +#include "generic.h" + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h new file mode 100644 index 0000000..d3394b0 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +/* + * linux/byteorder/swab.h + * Byte-swapping, independently from CPU endianness + * swabXX[ps]?(foo) + * + * Francois-Rene Rideau 19971205 + * separated swab functions from cpu_to_XX, + * to clean up support for bizarre-endian architectures. + * + * See asm-i386/byteorder.h and suches for examples of how to provide + * architecture-dependent optimized versions + * + */ + +/* casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___swab16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#define ___swab64(x) \ + ((__u64)( \ + (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swab16 +# define __arch__swab16(x) ___swab16(x) +#endif +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif +#ifndef __arch__swab64 +# define __arch__swab64(x) ___swab64(x) +#endif + +#ifndef __arch__swab16p +# define __arch__swab16p(x) __swab16(*(x)) +#endif +#ifndef __arch__swab32p +# define __arch__swab32p(x) __swab32(*(x)) +#endif +#ifndef __arch__swab64p +# define __arch__swab64p(x) __swab64(*(x)) +#endif + +#ifndef __arch__swab16s +# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) +#endif +#ifndef __arch__swab32s +# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) +#endif +#ifndef __arch__swab64s +# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swab16(x) \ +(__builtin_constant_p((__u16)(x)) ? \ + ___swab16((x)) : \ + __fswab16((x))) +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) +# define __swab64(x) \ +(__builtin_constant_p((__u64)(x)) ? \ + ___swab64((x)) : \ + __fswab64((x))) +#else +# define __swab16(x) __fswab16(x) +# define __swab32(x) __fswab32(x) +# define __swab64(x) __fswab64(x) +#endif /* OPTIMIZE */ + + +static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} +static __inline__ __u16 __swab16p(__u16 *x) +{ + return __arch__swab16p(x); +} +static __inline__ void __swab16s(__u16 *addr) +{ + __arch__swab16s(addr); +} + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} +static __inline__ __u32 __swab32p(__u32 *x) +{ + return __arch__swab32p(x); +} +static __inline__ void __swab32s(__u32 *addr) +{ + __arch__swab32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ +static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) +{ +# ifdef __SWAB_64_THRU_32__ + __u32 h = x >> 32; + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); +# else + return __arch__swab64(x); +# endif +} +static __inline__ __u64 __swab64p(__u64 *x) +{ + return __arch__swab64p(x); +} +static __inline__ void __swab64s(__u64 *addr) +{ + __arch__swab64s(addr); +} +#endif /* __BYTEORDER_HAS_U64__ */ + +//#if defined(__KERNEL__) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +//#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/io.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/io.h new file mode 100644 index 0000000..3c6455d --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/io.h @@ -0,0 +1,263 @@ +/* + * IO header file + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_M68K_IO_H__ +#define __ASM_M68K_IO_H__ + +#include "byteorder.h" + +#define __raw_readb(addr) (*(volatile u8 *)(addr)) +#define __raw_readw(addr) (*(volatile u16 *)(addr)) +#define __raw_readl(addr) (*(volatile u32 *)(addr)) + +#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) +#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w)) +#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l)) + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#if !defined(__BIG_ENDIAN) +//#if defined(__BIG_ENDIAN) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else /* Galvez: in_le16() does the swap reading + * twice from fifo (register), when reading + * from fifo once the value is changed by the new one */ +#define readw(addr) ld_le16((volatile u16 *)(addr)) /* instead of in_le16((volatile u16 *)(addr))*/ +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#endif + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#if !defined(__BIG_ENDIAN) +//#if defined(__BIG_ENDIAN) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#else +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#endif + +extern inline void _insb(volatile u8 * port, void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsb(volatile u8 * port, const void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *port = *data++; +} + +extern inline void _insw(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = __sw16(*port); +} + +extern inline void _outsw(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = __sw16(*data); + data++; + } +} + +extern inline void _insl(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = __sw32(*port); +} + +extern inline void _outsl(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = __sw32(*data); + data++; + } +} + +extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = *data++; + } +} + +extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = *port; +} + +extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = *data; + data++; + } +} + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define IO_SPACE_LIMIT ~0 + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile u8 * addr) +{ + return (int)*addr; +} + +extern inline void out_8(volatile u8 * addr, int val) +{ + *addr = (u8) val; +} + +extern inline int in_le16(volatile u16 * addr) +{ + return __sw16(*addr); +} + +extern inline int in_be16(volatile u16 * addr) +{ + return (*addr & 0xFFFF); +} + +extern inline void out_le16(volatile u16 * addr, int val) +{ + *addr = __sw16(val); +} + +extern inline void out_be16(volatile u16 * addr, int val) +{ + *addr = (u16) val; +} + +extern inline unsigned in_le32(volatile u32 * addr) +{ + return __sw32(*addr); +} + +extern inline unsigned in_be32(volatile u32 * addr) +{ + return (*addr); +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + *addr = __sw32(val); +} + +extern inline void out_be32(volatile unsigned *addr, int val) +{ + *addr = val; +} + +static inline void sync(void) +{ + /* This sync function is for PowerPC or other architecture instruction + * ColdFire does not have this instruction. Dummy function, added for + * compatibility (CFI driver) + */ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void *map_physmem(phys_addr_t paddr, unsigned long len, + unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +#endif /* __ASM_M68K_IO_H__ */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/types.h b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/types.h new file mode 100644 index 0000000..42ff2a6 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/asm-m68k/types.h @@ -0,0 +1,53 @@ +#ifndef _M68K_TYPES_H +#define _M68K_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute__((aligned(16))) vector128; + +//#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +//#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/bios.S b/BaS_codewarrior/FireBee/trunk/usb/store/bios.S new file mode 100644 index 0000000..fb83a92 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/bios.S @@ -0,0 +1,1378 @@ +/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards + * and USB-disk / Ram-Disk utility + * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr + * + * Modified to be used as an application by David Gálvez 2010. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + + +#include "config.h" +#include "vars.h" + +#define old_pun_ptr 0x516 + +#undef pun_ptr +#define pun_ptr pun_ptr_usb + +.global _max_logical_drive + +#define MAX_LOGICAL_DRIVE _max_logical_drive + +.chip 68040 + +.global ___mint + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \ + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) +#ifdef CONFIG_USB_STORAGE + .global _install_usb_stor,_usb_stor_read,_usb_stor_write,_usb_1st_disk_drive,_SuperFromUser, _SuperTouser +#endif /* CONFIG_USB_STORAGE */ +#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */ + + + +#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE) +.global _asm_set_ipl +.global _call_ikbdvec,_call_mousevec +#endif + +#ifdef DEBUG_BIOS_LAYER + .global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug +#endif + + .data + +/* XHDI */ + +#define XH_DL_SECSIZ 0 // maximal sector size (BIOS level) +#define XH_DL_MINFAT 1 // minimal number of FATs +#define XH_DL_MAXFAT 2 // maximal number of FATs +#define XH_DL_MINSPC 3 // sectors per cluster minimal +#define XH_DL_MAXSPC 4 // sectors per cluster maximal +#define XH_DL_CLUSTS 5 // maximal number of clusters of a 16 bit FAT +#define XH_DL_MAXSEC 6 // maximal number of sectors +#define XH_DL_DRIVES 7 // maximal number of BIOS drives supported by the DOS + + +/* AHDI */ + +#define PUN_DEV 0x1F /* device number of HD */ +#define PUN_UNIT 0x07 /* Unit number */ +#define PUN_SCSI 0x08 /* 1=SCSI 0=ACSI */ +#define PUN_IDE 0x10 /* Falcon IDE */ +#define PUN_USB 0x20 /* USB */ +#define PUN_REMOVABLE 0x40 /* Removable media */ +#define PUN_VALID 0x80 /* zero if valid */ + +#define pinfo_puns 0 // 2 bytes +#define pinfo_pun 2 // 32 bytes +#define pinfo_pstart 34 // 32 x 4 bytes +#define pinfo_cookie 162 // 4 bytes +#define pinfo_cookptr 166 // 4 bytes +#define pinfo_vernum 170 // 2 bytes +#define pinfo_maxsiz 172 // 2 bytes +#define pinfo_ptype 174 // 32 x 4 bytes +#define pinfo_psize 302 // 32 x 4 bytes +#define pinfo_flags 430 // 32 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable +#define pinfo_bpb 494 // 32 x 32 bytes +#define pinfo_devnum 1518 // 32 bytes +#define pinfo_size 1550 + + +#if 1//#ifdef DEBUG_BIOS_LAYER +//debug1: .asciz "XBIOS #0x" +//debug2: .asciz "Setscreen 0x" +debug3: .asciz "hdv_rw 0x" +debug4: .ascii "hdv_bpb" + .byte 13,10,0 +debug5: .ascii "hdv_mediach" + .byte 13,10,0 +//debug6: .asciz "Vsetmode 0x" +//debug7: .asciz "ValidMode 0x" +//debug8: .asciz "Gettime 0x +debug132: .asciz "XHDI XHReadWrite 0x" +debug133: .ascii "XHDI XHInqTarget2" + .byte 13,10,0 +debug134: .ascii "XHDI XHInqDev" + .byte 13,10,0 +debug135: .ascii "XHDI XHInqDriver" + .byte 13,10,0 +debug136: .ascii "XHDI XHInqDev2" + .byte 13,10,0 +debug137: .ascii "XHDI XHDOSLimits" + .byte 13,10,0 +debug138: .ascii "GALVEZ DEBUG" /* Galvez: DEBUG */ + .byte 13,10,0 +debug139: .ascii "XHDI XHReadWrite" /* Galvez: DEBUG */ + .byte 13,10,0 + .align 2 +#endif + + +// dc.l 0x58425241 // XBRA +// dc.l 0x5F504349 // _PCI +// dc.l 0 // cannot store here because we are in flash + + + +text_color: + + moveq #0,D0 + move.w 0x3E86,D0 // number of planes + cmp.l #2,D0 + bls.s .black_and_white + pea (A0) + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP +.black_and_white: + rts + +#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE) +_asm_set_ipl: + link A6,#-8 + movem.l D6-D7,(SP) + move.w SR,D7 // current SR + move.l D7,D0 // prepare return value + and.l #0x0700,D0 // mask out IPL + lsr.l #8,D0 // IPL + move.l 8(A6),D6 // get argument + and.l #7,D6 // least significant three bits + lsl.l #8,D6 // move over to make mask + and.l #0x0000F8FF,D7 // zero out current IPL + or.l D6,D7 // place new IPL in SR + move.w D7,SR + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts + +_call_ikbdvec: + + lea -24(SP),SP + movem.l D0-D2/A0-A2,(SP) + move.l 28(SP),D0 // ikbd code + move.l 32(SP),A0 // iorec + and.l #0xFF,D0 + move.l 0x1132,A2 // ikbdvec + jsr (A2) + movem.l (SP),D0-D2/A0-A2 + lea 24(SP),SP + rts + +_call_mousevec: + + lea -24(SP),SP + movem.l D0-D2/A0-A2,(SP) + move.l 28(SP),A0 // data + move.l 32(SP),A2 + move.l (A2),A2 // mousevec + jsr (A2) + movem.l (SP),D0-D2/A0-A2 + lea 24(SP),SP + rts +#endif + +install_xbra: // A0: handler, D0: vector, D1: ID + + lea -28(SP),SP + movem.l D1-D3/A0-A3,(SP) + moveq #0,D3 + move.w D0,D3 // vector + move.l A0,A3 // handler + move.l D1,-(SP) + move.w #3,-(SP) // TT ram if possible + move.l #18,-(SP) // size + move.w #0x44,-(SP) // Mxalloc + trap #1 + addq.l #8,SP + move.l (SP)+,D1 + tst.l D0 + beq.s .error_xbra + move.l D0,A0 + move.l #0x58425241,(A0)+ // XBRA + move.l D1,(A0)+ + clr.l (A0)+ + move.w #0x4EF9,(A0)+ // JMP + move.l A3,(A0)+ // handler + lea -10(A0),A0 + + cpusha BC + + move.l D3,A1 + move.l (A1),D0 + move.l D0,(A0)+ // old vector + move.l A0,(A1) // JMP, new vector +.error_xbra: + tst.l D0 + movem.l (SP),D1-D3/A0-A3 + lea 28(SP),SP + rts +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \ + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) +#ifdef CONFIG_USB_STORAGE +_install_usb_stor: + lea -32(SP),SP + movem.l D1-D4/A0-A3,(SP) + move.l 36(SP),D0 // dev_num + cmp.l #PUN_DEV,D0 + bhi .no_pinfo // error + move.l 40(SP),D2 // part_type + move.l D2,D1 + and.l #0xFFFFFF,D1 // ID + // GEMDOS + cmp.l #0x47454D,D1 // GEM up to 16M + beq.s .partition_ok + cmp.l #0x42474D,D1 // BGM over 16M + beq.s .partition_ok + cmp.l #0x524157,D1 // RAW + beq.s .partition_ok + // DOS 1:FAT12, 0xB/0xC:FAT32 + cmp.l #0x4,D2 // FAT16 up to 32M + beq.s .partition_ok + cmp.l #0x6,D2 // FAT16 over 32M + beq.s .partition_ok + tst.l ___mint // Galvez: NOT MiNT? then go out + beq .invalid_partition_type + cmp.l #0xE,D2 // WIN95 FAT16 + beq .partition_ok + cmp.l #0xB,D2 // FAT32 + beq.s .partition_ok + cmp.l #0xC,D2 // FAT32 + bne .partition_ok + cmp.l #0x81,D2 // MINIX + bne .partition_ok + cmp.l #0x83,D2 // EXT2/LNX + bne .partition_ok +.partition_ok: + move.l old_pun_ptr,A2 // Galvez: we need it to update hd driver pun struct + move.l pun_ptr,D0 + bne.s .pinfo_ok + move.w #3,-(SP) // TT ram if possible + move.l #pinfo_size,-(SP) + move.w #0x44,-(SP) // Mxalloc + trap #1 + addq.l #8,SP + move.l D0,pun_ptr + beq.s .no_pinfo + move.l D0,A3 + clr.w pinfo_puns(A3) + move.w #0x0300,D0 + move.w D0,pinfo_vernum(A3) + move.w #0x4000,D0 + move.w D0,pinfo_maxsiz(A3) + lea pinfo_pun(A3),A0 + moveq #-1,D0 + move.w D0,(A0)+ // drives A/B + move.l D0,(A0)+ + move.l D0,(A0)+ + move.l D0,(A0)+ + move.l D0,(A0)+ + move.l D0,(A0)+ + move.l D0,(A0)+ + move.l D0,(A0)+ + move.w D0,(A0) + lea pinfo_pstart(A3),A0 + lea pinfo_size(A3),A1 +.clrpun: + clr.w -(A1) + cmp.l A0,A1 + bgt.s .clrpun + move.l A3,D0 // pun_ptr +.pinfo_ok: + move.l D0,A3 // pun_ptr + moveq #2,D4 // drive C + move.l _drvbits,D0 +.search_empty_drive_usb: + btst D4,D0 + beq.s .drive_not_exist_usb + addq.l #1,D4 + cmp.l #MAX_LOGICAL_DRIVE,D4 + bcs.s .search_empty_drive_usb + bra .drive_full_usb // all drives already used +.no_pinfo: + moveq #0,D0 // not installed + bra .end_usb_disk +.drive_not_exist_usb: + move.w pinfo_puns(A3),D0 + addq.l #1,D0 + move.w D0,pinfo_puns(A3) + moveq #0,D0 + bset #7,D0 // changed + lea pinfo_flags(A3),A0 + move.l D0,(A0,D4.l*4) // B15:swap, B7:change, B0:bootable + lea pinfo_psize(A3),A0 + move.l 48(SP),D3 // part_size + move.l 44(SP),D1 // part_offset + move.l 40(SP),D2 // part_type + move.l 36(SP),D0 // dev_num + move.b D0,pinfo_devnum(A3,D4.l) + move.l D2,pinfo_ptype(A3,D4.l*4) + move.l D4,D2 + or.l #PUN_USB,D2 + move.b D2,pinfo_pun(A3,D4.l) + cmp.l #15,D4 // Galvez: update AHDI pun struct: + bgt .ahdi_part_num_limit // Galvez: if logical part. > 16 + move.b D2,pinfo_pun(A2,D4.l) // Galvez: don't update pun struct, + move.w D0,-(SP) // Galvez: to avoid corruption. + move.w pinfo_puns(A2),D0 // Galvez: update hd driver pun stuct + addq.l #1,D0 // Galvez: othewise MiNT only handles 16MB + move.w D0,pinfo_puns(A2) // Galvez: when not using XHDI + move.w (SP)+,D0 // Galvez: see BLOCK_IO.c (MiNT sources) +.ahdi_part_num_limit: + move.l D3,(A0,D4.l*4) // size + move.l D1,pinfo_pstart(A3,D4.l*4) + move.l _dskbufp,A0 + move.l A0,-(SP) // buffer + move.l #1,-(SP) // blkcnt + move.l D1,-(SP) // blknr + move.l D0,-(SP) // devnum + jsr _usb_stor_read + lea 16(SP),SP + tst.l D0 + beq .end_usb_disk // read error + tst.l _usb_1st_disk_drive + bne .usb_1st_drive_ok // hdv vectors installed + move.l D4,_usb_1st_disk_drive + move.w SR,D0 + move.w D0,-(SP) + or.l #0x700,D0 // mask interrupts + move.w D0,SR + move.l #0x5F555342,D1 // _USB + lea det_hdv_bpb_usb(PC),A0 + move.w #hdv_bpb,D0 + bsr install_xbra + move.l D0,old_hdv_bpb_usb + lea det_hdv_rw_usb(PC),A0 + move.w #hdv_rw,D0 + bsr install_xbra + move.l D0,old_hdv_rw_usb + lea det_hdv_mediach_usb(PC),A0 + move.w #hdv_mediach,D0 + bsr install_xbra + move.l D0,old_hdv_mediach_usb + move.l cookie,D0 + beq.s .no_cookie_jar + move.l D0,A0 + move.l #0x58484449,D1 // XHDI +.find_cookie_jar: + tst.l (A0) + beq.s .cookie_slot_free + cmp.l (A0),D1 + beq.s .cookie_found + addq.l #8,A0 + bra.s .find_cookie_jar +.cookie_found: + move.l 4(A0),D0 + move.l D0,old_xhdi + lea xhdi(PC),A1 + clr.l -(SP) // XHGetVersion + move.l D0,A0 + jsr (A0) + addq.l #4,SP + move.l D0,old_xhdi_version + move.l A1,-(SP) + move.w #9,-(SP) // Galvez: XHNewCookie + jsr (A0) + add.l #6,SP + tst.l D0 + beq.s .no_cookie_jar + move.l A1,4(A0) // Galvez: Replace cookie "by-hand" + bra.s .no_cookie_jar +.cookie_slot_free: + move.l 4(A0),12(A0) // copy size + lea xhdi(PC),A1 + move.l A1,(A0)+ + clr.l (A0) + clr.l old_xhdi + move.l #0x120,D0 // protocol version + move.l D0,old_xhdi_version +.no_cookie_jar: + move.w (SP)+,D0 + move.w D0,SR // restore interrupts +.usb_1st_drive_ok: + move.l _dskbufp,A0 // boot sector + lea pinfo_bpb(A3),A1 + move.l D4,D2 // logical drive + asl.l #5,D2 // * 32 + add.l D2,A1 + moveq #0,D2 + move.b 0xC(A0),D2 + asl.l #8,D2 + move.b 0xB(A0),D2 // BPS + move.w D2,(A1) // sector size + moveq #0,D1 + move.b 0xD(A0),D1 // SPC + move.w D1,2(A1) // cluster size in sectors + move.w D1,D0 + mulu D2,D0 + move.w D0,4(A1) // cluster size in bytes + moveq #0,D0 + move.b 0x12(A0),D0 + asl.l #8,D0 + move.b 0x11(A0),D0 // NDIRS + asl.l #5,D0 // * 32 + + divu D2,D0 // / sector size + + move.w D0,6(A1) // size directory in sectors + moveq #0,D2 + move.b 0x17(A0),D2 + asl.l #8,D2 + move.b 0x16(A0),D2 // SPF + move.w D2,8(A1) // FAT size + moveq #0,D0 + move.b 0xF(A0),D0 + asl.l #8,D0 + move.b 0xE(A0),D0 // RES + move.l D0,D3 + add.l D2,D3 // + FAT size + move.w D3,10(A1) // 1st sector of FAT2 + moveq #0,D3 + move.b 0x10(A0),D3 // NFATS + mulu D2,D3 // * FAT size + add.l D0,D3 // + RES + moveq #0,D0 + move.w 6(A1),D0 // size directory in sectors + add.l D3,D0 + move.w D0,12(A1) // 1st data sector + moveq #0,D2 + move.b 0x14(A0),D2 + asl.l #8,D2 + move.b 0x13(A0),D2 // NSECTS + bne.s .nsects_ok_usb + lea pinfo_psize(A3),A2 + move.l (A2,D4.w*4),D2 // partition size in sectors + sub.l D0,D2 // - 1st data sector +.nsects_ok_usb: + divu D1,D2 + + move.w D2,14(A1) // total clusters + moveq #1,D0 + move.w D0,16(A1) // FAT 16 + clr.w 18(A1) + clr.l 20(A1) + clr.l 24(A1) + clr.l 28(A1) + move.l _drvbits,D0 + bset D4,D0 + move.l D0,_drvbits + moveq #2,D0 // drive C + cmp.l D4,D0 + bne.s .no_set_drive_usb + move.w D0,_bootdev + move.w D0,-(SP) + move.w #0xE,-(SP) // Dsetdrv + trap #1 + addq.l #4,SP +.no_set_drive_usb: + move.l 36(SP),D0 // devnum + movem.l 52(SP),A1/A2/A3 // vendor / revision / product + move.l product_name,A0 // save product name pointer for XHDI +#if DEBUG_BIOS_LAYER + move.l D0, -(SP) + move.b D4,D0 + jsr hex_byte /* Galvez: DEBUG device */ + move.l (SP)+,D0 +#endif + move.l A3,(A0,D4.l*4) + bsr display_drive_usb + pea message2b(PC) + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + moveq #0x41,D0 // A + add.l D4,D0 + move.w D0,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + pea crlf(PC) + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + move.l D4,D0 // OK + bra.s .end_usb_disk +.invalid_partition_type: + pea error4(PC) + bra.s .display_error_usb +.drive_full_usb: + pea error2(PC) +.display_error_usb: + move.l 36+4(SP),D0 // devnum + movem.l 52+4(SP),A1/A2/A3 // vendor / revision / product + bsr display_drive_usb + move.w #0x2C,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.w #0x20,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + moveq #0,D0 // not installed +.end_usb_disk: + movem.l (SP),D1-D4/A0-A3 + lea 32(SP),SP + rts + +display_drive_usb: + + move.l A1,-(SP) + moveq #0x30,D1 + add.l D1,D0 // dev_num + move.w D0,-(SP) + lea blue(PC),A0 + bsr text_color + pea message2(PC) // USB-disk installed + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.w #0x2E,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.w #0x30,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + lea black(PC),A0 + bsr text_color + move.w #0x20,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + move.w #0x20,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.l A2,-(SP) + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + move.w #0x20,-(SP) + move.w #2,-(SP) + trap #1 // Cconout + addq.l #4,SP + move.l A3,-(SP) + move.w #9,-(SP) + trap #1 // Cconws + addq.l #6,SP + rts + +det_hdv_bpb_usb: + move.l A0,-(SP) + move.l pun_ptr,A0 + moveq #0,D0 + move.w 4+4(SP),D0 // drive + cmp.l _usb_1st_disk_drive,D0 + bcs.s .dhbu2 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .dhbu2 + tst.b pinfo_pun(A0,D0.l) + bpl.s .dhbu1 +.dhbu2: + move.l (SP)+,A0 + moveq #0,D0 + move.l old_hdv_bpb_usb,-(SP) + rts +.dhbu1: + move.l D1,-(SP) + move.l pinfo_ptype(A0,D0.l*4),D1 + and.l #0xFFFFFF,D1 + cmp.l #0x524157,D1 // RAW + beq.s .dhbu4 + cmp.l #0x81,D1 // MINIX + beq.s .dhbu4 + cmp.l #0x83,D1 // EXT2/LNX + bne.s .dhbu3 +.dhbu4: + move.l (SP)+,D1 + move.l (SP)+,A0 + moveq #0,D0 + rts +.dhbu3: + lea pinfo_bpb(A0),A0 + asl.l #5,D0 // * 32 + add.l A0,D0 +#if DEBUG_BIOS_LAYER + move.l D0,-(SP) + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.l (SP),D0 + jsr hex_long + moveq #0x20,D0 + jsr display_char + lea debug4(PC),A0 + jsr display_string + move.l (SP)+,D0 +#endif + move.l (SP)+,D1 + move.l (SP)+,A0 + rts + +det_hdv_rw_usb: + + lea -28(SP),SP + movem.l D1-D4/A0-A2,(SP) +#if DEBUG_BIOS_LAYER + lea debug3(PC),A0 + jsr display_string + move.w 4+28(SP),D0 // rwflag + jsr hex_word + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.l 6+28(SP),D0 // buffer + jsr hex_long + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.w 10+28(SP),D0 // num sectors + jsr hex_word + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.w 12+28(SP),D0 // logical sector + jsr hex_word + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.w 16+28(SP),D0 // Galvez: logical sector (lrecno) + jsr hex_long + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.w 14+28(SP),D0 // drive + jsr hex_word + moveq #13,D0 + jsr display_char + moveq #10,D0 + jsr display_char +#endif + btst #3,5+28(SP) // rwflag + bne.s .dhru8 // physical + move.l pun_ptr,A0 + moveq #0,D0 + move.w 14+28(SP),D0 // drive + cmp.l _usb_1st_disk_drive,D0 + bcs.s .dhru8 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .dhru8 + moveq #0,D4 + move.b pinfo_pun(A0,D0.l),D4 + bpl.s .dhru1 // valid +.dhru8: + movem.l (SP),D1-D4/A0-A2 + lea 28(SP),SP + moveq #0,D0 + move.l old_hdv_rw_usb,-(SP) + rts +.dhru1: + move.l D4,D2 + and.l #PUN_USB,D2 + beq.s .dhru8 // not USB + and.l #PUN_DEV,D4 + moveq #0,D2 + move.w 12+28(SP),D2 // logical sector + cmp.w #0xffff,D2 // Galvez: check recno <> -1 + bne.s .dhru6 + move.l 16+28(SP),D2 // logical sector +.dhru6: + tst.l D2 + bmi .dhru2 // negative logical sector + move.l 6+28(SP),D1 // buffer + beq .dhru4 // no buffer + move.l pinfo_pstart(A0,D0.l*4),D3 + move.l pinfo_devnum(A0,D0.l),D4 // devnum in the USB bus + lea pinfo_bpb(A0),A0 + asl.l #5,D0 // * 32 + add.l D0,A0 + move.w 14(A0),D0 // total clusters + mulu.w 2(A0),D0 // cluster size in sectors + cmp.l D0,D2 // logical sector to hight + bcc .dhru2 + moveq #0,D0 + move.w (A0),D0 // sector size + lsr.l #8,D0 + lsr.l #1,D0 // / 512 + move.l D1,A0 // buffer + move.w 10+28(SP),D1 // num sectors + beq .dhru4 // no sectors + mulu D0,D1 + mulu.l D0,D2 + add.l D3,D2 // start sector + move.l D1,D3 // count + btst #0,5+28(SP) // rwflag + beq.s .dhru7 // read + // write + tst.l D2 // logical sector + beq.s .dhru2 // root sector + move.l A0,-(SP) // buffer + move.l D3,-(SP) // blkcnt + move.l D2,-(SP) // blknr + move.l D4,-(SP) // USB devnum + jsr _usb_stor_write + bra.s .dhru5 +.dhru2: + moveq #-1,D0 // error + bra.s .dhru3 +.dhru4: + moveq #0,D0 // OK + bra.s .dhru3 +.dhru7: + move.l A0,-(SP) // buffer + move.l D3,-(SP) // blkcnt + move.l D2,-(SP) // blknr + move.l D4,-(SP) // USB devnum + jsr _usb_stor_read +.dhru5: + lea 16(SP),SP + tst.l D0 + seq.b D0 + ext.w D0 + ext.l D0 + bclr #0,D0 // OK or device not responding -2 +.dhru3: + movem.l (SP),D1-D4/A0-A2 + lea 28(SP),SP + rts + +det_hdv_mediach_usb: + + move.l A0,-(SP) + move.l pun_ptr,A0 + moveq #0,D0 + move.w 4+4(SP),D0 // drive + cmp.l _usb_1st_disk_drive,D0 + bcs.s .dhmu2 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .dhmu2 + tst.b pinfo_pun(A0,D0.l) + bpl.s .dhmu1 +.dhmu2: + move.l (SP)+,A0 + moveq #0,D0 + move.l old_hdv_mediach_usb,-(SP) + rts +.dhmu1: +#if 0 // #if DEBUG_BIOS_LAYER + move.l A0,-(SP) + lea debug5(PC),A0 + jsr display_string + move.l (SP)+,A0 +#endif + lea pinfo_flags(A0),A0 + add.l D0,A0 + add.l D0,A0 + bclr #7,1(A0) + sne.b D0 + and.l #2,D0 + move.l (SP)+,A0 + rts + + // XHDI + + dc.l 0x27011992 + +xhdi: + link A6,#0 + movem.l D1-A5,-(SP) + moveq #0,D1 + move.w 8(A6),D1 + + move.w D1,D0 +#if DEBUG_BIOS_LAYER + move.w D0, -(SP) + jsr hex_word /* Galvez: DEBUG. XHDI function */ + move.w (SP)+,D0 +#endif + moveq #-32,D0 // invalid function + cmp.l #18,d1 + bcc.s .bad_xhdi + move.w SR,D0 // supervisor only + moveq #-1,d0 // error + move.w tab_xhdi(PC,D1.l*2),D1 + jsr tab_xhdi(PC,D1.W) + +.bad_xhdi: + movem.l (SP)+,D1-A5 + unlk A6 + rts +#if DEBUG_BIOS_LAYER +debug: + lea debug138(PC),A0 + jsr display_string + rts +#endif + +tab_xhdi: + dc.w XHGetVersion-tab_xhdi // 0 + dc.w XHInqTarget-tab_xhdi // 1 + dc.w XHReserve-tab_xhdi // 2 + dc.w XHLock-tab_xhdi // 3 + dc.w XHStop-tab_xhdi // 4 + dc.w XHEject-tab_xhdi // 5 + dc.w XHDrvMap-tab_xhdi // 6 + dc.w XHInqDev-tab_xhdi // 7 + dc.w XHInqDriver-tab_xhdi // 8 + dc.w XHNewCookie-tab_xhdi // 9 + dc.w XHReadWrite-tab_xhdi // 10 + dc.w XHInqTarget2-tab_xhdi // 11 + dc.w XHInqDev2-tab_xhdi // 12 + dc.w XHDriverSpecial-tab_xhdi // 13 + dc.w XHGetCapacity-tab_xhdi // 14 + dc.w XHMediumChanged-tab_xhdi // 15 + dc.w XHMiNTInfo-tab_xhdi // 16 + dc.w XHDOSLimits-tab_xhdi // 17 + +XHGetVersion: +#if DEBUG_BIOS_LAYER + move.l A0,-(SP) + lea debug138(PC),A0 + jsr display_string + move.l (SP)+,A0 +#endif + move.l #0x120,D0 // protocol version + move.l old_xhdi_version,D1 + cmp.l D1,D0 + bcs.s .xv1 + move.l D1,D0 // minimum version +.xv1: + rts + +XHInqTarget: + + moveq #32,D2 // stringlen + bra.s .xi1 + +XHInqTarget2: + +#if DEBUG_BIOS_LAYER + move.l A0,-(SP) + lea debug133(PC),A0 + jsr display_string + move.l (SP)+,A0 +#endif + move.w 26(A6),D2 // stringlen +.xi1: + tst.w 12(A6) // minor + bne.s .xi2 + moveq #0,D0 + move.w 10(A6),D0 // major + cmp.w #PUN_USB,D0 + bcs.s .xi2 + cmp.w #PUN_USB+PUN_DEV,D0 + bls.s .xi3 +.xi2: + tst.l old_xhdi + beq.s .xi7 + moveq #-15,D0 // unknown device + rts +.xi7: + move.l old_xhdi,-(SP) + rts +.xi3: + tst.l 14(A6) + beq.s .xi8 + move.l 14(A6),A0 + move.l #512,(A0) +.xi8: + tst.l 18(A6) + beq.s .xi9 + move.l 18(A6),A0 // flags + move.l #0x00000002,(A0) // removable +.xi9: + move.l 22(A6),D1 // product_name + beq.s .xi6 // no pointer + move.l D1,A0 + + and.b #PUN_DEV,D0 + move.l product_name,A1 + move.l (A1,D0.l*4),D0 // Galvez: D0 should be the bios drive number + beq.s .xi6 // no pointer + move.l D0,A1 +.xi5: + move.b (A1)+,(A0)+ + beq.s .xi4 + subq.w #1,D2 + bpl.s .xi5 // Galvez: test +.xi4: + clr.b -1(A0) +.xi6: + moveq #0,D0 + rts + +XHReserve: +XHLock: +XHStop: +XHEject: + + tst.l old_xhdi + beq.s .xnu1 + moveq #0,D0 + rts +.xnu1: + move.l old_xhdi,-(SP) + rts + +XHDrvMap: + + move.l _drvbits,D0 + rts + +XHInqDev: + +#if DEBUG_BIOS_LAYER + lea debug134(PC),A0 + jsr display_string +#endif + + move.l pun_ptr,A0 + moveq #0,D0 + move.w 10(A6),D0 // bios_device + cmp.l _usb_1st_disk_drive,D0 + bcs.s .xd2 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .xd2 + moveq #0,D1 + move.b pinfo_pun(A0,D0.l),D1 + bpl.s .xd1 +.xd2: + + tst.l old_xhdi + beq.s .xd3 + moveq #-46,D0 // invalid drive number + + rts +.xd3: + move.l old_xhdi,-(SP) + rts +.xd1: + move.l D1,D2 + and.l #PUN_USB+PUN_DEV,D2 + beq.s .xd2 + tst.l 12(A6) + beq.s .xd4 + move.l 12(A6),A1 // major + move.w D1,(A1) +.xd4: + tst.l 16(A6) + beq.s .xd5 + move.l 16(A6),A1 // minor + clr.w (A1) +.xd5: + tst.l 20(A6) + beq.s .xd6 + move.l pinfo_pstart(A0,D0.l*4),D1 + move.l 20(A6),A1 // start_sector + move.l D1,(A1) +.xd6: + lea pinfo_bpb(A0),A0 + asl.l #5,D0 // * 32 + add.l A0,D0 + tst.l 24(A6) + beq.s .xd7 + move.l 24(A6),A1 // bpb + move.l D0,(A1) +.xd7: + moveq #0,D0 + rts + +XHInqDriver: + +#if DEBUG_BIOS_LAYER + lea debug135(PC),A0 + jsr display_string +#endif + move.l pun_ptr,A0 + moveq #0,D0 + move.w 10(A6),D0 // bios_device + cmp.l _usb_1st_disk_drive,D0 + bcs.s .xdr2 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .xdr2 + moveq #0,D1 + move.b pinfo_pun(A0,D0.l),D1 + bpl.s .xdr1 +.xdr2: + tst.l old_xhdi + beq.s .xdr8 + moveq #-46,D0 // invalid drive number + rts +.xdr8: + move.l old_xhdi,-(SP) + rts +.xdr1: + move.l D1,D0 + and.l #PUN_USB,D0 + beq.s .xdr2 + move.l 12(A6),D0 // name, 17 characters + beq.s .xdr3 + move.l D0,A1 + lea message1(PC),A0 + moveq #17,D1 +.xdr6: + move.b (A0)+,D0 + beq.s .xdr7 + move.b D0,(A1)+ + subq.l #1,D1 + bpl.s .xdr6 +.xdr7: + clr.b (A1) +.xdr3: + move.l 16(A6),D0 // version, 7 characters + beq.s .xdr4 + move.l D0,A1 + move.b #0x34,(A1)+ // ??? TOS 4.04 + move.b #0x2E,(A1)+ + move.b #0x30,(A1)+ + move.b #0x34,(A1)+ + clr.b (A1) +.xdr4: + move.l 20(A6),D0 // company, 17 characters + beq.s .xdr5 + move.l D0,A1 + clr.b (A1) +.xdr5: + move.l 24(A6),A1 // ahdi_version + move.w pinfo_vernum(A0),(A1) + move.l 28(A6),A1 // maxIPL + moveq #5,D0 + move.w D0,(A1) + moveq #0,D0 + rts + +XHReadWrite: // read / write physical sectors +#if DEBUG_BIOS_LAYER + lea debug139(PC),A0 + jsr display_string +#endif + + tst.w 12(A6) // minor + bne.s .xr4 + moveq #0,D4 + move.w 10(A6),D4 // major + cmp.l #PUN_USB,D4 + bcs.s .xr4 + cmp.l #PUN_USB+PUN_DEV,D4 + bls.s .xr1 +.xr4: + tst.l old_xhdi + beq.s .xr6 + moveq #-15,D0 // unknown device + rts +.xr6: + move.l old_xhdi,-(SP) + rts +.xr1: +#if DEBUG_BIOS_LAYER + lea debug132(PC),A0 + jsr display_string + move.w 14(A6),D0 // rwflag + jsr hex_word + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.l 24(A6),D0 // buffer + jsr hex_long + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.w 20(A6),D0 // num sectors + jsr hex_word + moveq #0x20,D0 + jsr display_char + moveq #0x30,D0 + jsr display_char + moveq #0x78,D0 + jsr display_char + move.l 16(A6),D0 // logical sector + jsr hex_long + moveq #13,D0 + jsr display_char + moveq #10,D0 + jsr display_char +#endif + move.l 22(A6),A0 // buffer + moveq #0,D3 + move.w 20(A6),D3 // count + beq .xr2 // no sectors + move.l 16(A6),D2 // start sector + btst #0,15(A6) // rwflag + beq.s .xr7 // read + // write + move.l A0,-(SP) // buffer + move.l D3,-(SP) // blkcnt + move.l D2,-(SP) // blknr + move.l D4,D0 // major + and.l #PUN_DEV,D0 + move.l pun_ptr,A0 + move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus + move.l D0,-(SP) // USB devnum + jsr _usb_stor_write + bra.s .xr5 +.xr2: + moveq #-1,D0 // error + bra.s .xr3 +.xr7: + move.l A0,-(SP) // buffer + move.l D3,-(SP) // blkcnt + move.l D2,-(SP) // blknr + move.l D4,D0 // major + and.l #PUN_DEV,D0 + move.l pun_ptr,A0 + move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus + move.l D0,-(SP) // USB devnum + jsr _usb_stor_read +.xr5: + lea 16(SP),SP + tst.l D0 + seq.b D0 + ext.w D0 + ext.l D0 + bclr #0,D0 // OK or device not responding -2 +.xr3: + rts + +XHInqDev2: + +#if DEBUG_BIOS_LAYER + lea debug136(PC),A0 + jsr display_string // Galvez: changed bsr by jsr to avoid linker error +#endif + move.l pun_ptr,A0 + moveq #0,D0 + move.w 10(A6),D0 // bios_device + cmp.l _usb_1st_disk_drive,D0 + bcs.s .xdd2 + cmp.l #MAX_LOGICAL_DRIVE,D0 + bcc.s .xdd2 + moveq #0,D1 + move.b pinfo_pun(A0,D0.l),D1 + bpl.s .xdd1 +.xdd2: + tst.l old_xhdi + beq.s .xdd4 + moveq #-46,D0 // invalid drive number + rts +.xdd4: + move.l old_xhdi,-(SP) + rts +.xdd1: + move.w D1,D2 + and.b #PUN_USB+PUN_DEV,D2 + beq.s .xdd2 + tst.l 12(A6) + beq.s .xdd5 + move.l 12(A6),A1 // major + move.w D2,(A1) +.xdd5: + tst.l 16(A6) + beq.s .xdd6 + move.l 16(A6),A1 // minor + clr.w (A1) +.xdd6: + tst.l 20(A6) + beq.s .xdd7 + move.l pinfo_pstart(A0,D0.l*4),D1 + move.l 20(A6),A1 // start_sector + move.l D1,(A1) +.xdd7: + tst.l 24(A6) + beq.s .xdd8 + lea pinfo_bpb(A0),A2 + move.l D0,D1 + asl.l #5,D1 // * 32 + add.l A2,D1 + move.l 24(A6),A1 // bpb + move.l D1,(A1) +.xdd8: + tst.l 28(A6) + beq.s .xdd9 + move.l 28(A6),A1 // blocks + lea pinfo_psize(A0),A2 + move.l (A2,D0.l*4),(A1) +.xdd9: + tst.l 32(A6) + beq.s .xdd10 + move.l 32(A6),A1 // partid + clr.l (A1) + move.b pinfo_ptype+3(A0,D0.l*4),D1 + move.w #0x0044,(A1) // NULL+ 'D' + move.b D1,2(A1) +.xdd10: + moveq #0,D0 + rts + +XHDriverSpecial: +XHGetCapacity: +XHMediumChanged: +XHMiNTInfo: +XHNewCookie: + + tst.l old_xhdi + beq.s .xn1 + moveq #-32,D0 // invalid function number + rts +.xn1: + move.l old_xhdi,-(SP) + rts + +XHDOSLimits: + + tst.l old_xhdi + bne.s .xn1 +#if DEBUG_BIOS_LAYER + lea debug137(PC),A0 + jsr display_string +#endif + moveq #0,D0 + move.w 10(A6),D0 // which + cmp.l #XH_DL_SECSIZ,D0 // maximal sector size (BIOS level) + bne.s .xl1 + move.l #0x4000,D0 + rts +.xl1: + cmp.l #XH_DL_MINFAT,D0 // minimal number of FATs + bne.s .xl2 + moveq #1,D0 + rts +.xl2: + cmp.l #XH_DL_MAXFAT,D0 // maximal number of FATs + bne.s .xl3 + moveq #2,D0 + rts +.xl3: + cmp.l #XH_DL_MINSPC,D0 // sectors per cluster minimal + bne.s .xl4 + moveq #2,D0 + rts +.xl4: + cmp.l #XH_DL_MAXSPC,D0 // sectors per cluster maximal + bne.s .xl5 +#ifdef COLDFIRE + moveq #64,D0 // for this Coldfire version of BDOS, else 2 +#else + moveq #2,D0 +#endif + rts +.xl5: + cmp.l #XH_DL_CLUSTS,D0 // maximal number of clusters of a 16 bit FAT + bne.s .xl6 + move.l #0x8000,D0 + rts +.xl6: + cmp.l #XH_DL_MAXSEC,D0 // maximal number of sectors + bne.S .xl7 +#ifdef COLDFIRE + move.l #0x200000,D0 // for this Coldfire version of BDOS, else 0x10000 +#else + move.l #0x10000,D0 +#endif + rts +.xl7: + cmp.l #XH_DL_DRIVES,D0 // maximal number of BIOS drives supported by the DOS + bne.s .xl8 + moveq #16,D0 + rts +.xl8: + moveq #-32,D0 // invalid function number + rts + + + + +#endif /* CONFIG_USB_STORAGE */ +#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */ + + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \ + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) +#ifdef CONFIG_USB_STORAGE +message1: .ascii "TOS4.04 " +message2: .asciz "USB " +message2b: .asciz ", disk installed in " +#endif +#endif + +crlf: .byte 13,10,0 +error: .asciz "No ram-disk installed, " +error1: .ascii "no enough radeon memory" + .byte 13,10,0 +error2: .ascii "all drives already used" + .byte 13,10,0 +error3: .ascii "error disk name" + .byte 13,10,0 +error4: .ascii "partition type not supported" + .byte 13,10,0 +blue: .byte 0x1B,0x62,0x34,0 +black: .byte 0x1B,0x62,0x3F,0 + + .align 2 + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \ + || defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) +#ifdef CONFIG_USB_STORAGE + + .lcomm pun_ptr_usb,4 + .lcomm user_sp,4 + + .lcomm _usb_1st_disk_drive,4 + .lcomm old_hdv_bpb_usb,4 + .lcomm old_hdv_rw_usb,4 + .lcomm old_hdv_mediach_usb,4 + .lcomm old_xhdi,4 + .lcomm old_xhdi_version,4 + .lcomm product_name,4*(PUN_DEV+1) +#endif /* CONFIG_USB_STORAGE */ +#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */ + + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/cmd_usb.c b/BaS_codewarrior/FireBee/trunk/usb/store/cmd_usb.c new file mode 100644 index 0000000..9c6b3da --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/cmd_usb.c @@ -0,0 +1,731 @@ +/* + * Modified for Atari by David Gálvez 2010 + * Modified for Atari by Didier Mequignon 2009 + * + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Most of this source has been derived from the Linux USB + * project. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + + +#include "config.h" +#include "asm-m68k/byteorder.h" +#include "usb.h" + + +//#undef RESET_START_STOP_CMDS +//#define RESET_START_STOP_CMDS + +#ifdef CONFIG_USB_STORAGE +static int usb_stor_curr_dev = -1; /* current device */ +#endif + +#ifdef PCI_XBIOS +extern short pci_init(void); +#endif + +/* some display routines (info command) */ +char *usb_get_class_desc(unsigned char dclass) +{ + switch (dclass) { + case USB_CLASS_PER_INTERFACE: + return "See Interface"; + case USB_CLASS_AUDIO: + return "Audio"; + case USB_CLASS_COMM: + return "Communication"; + case USB_CLASS_HID: + return "Human Interface"; + case USB_CLASS_PRINTER: + return "Printer"; + case USB_CLASS_MASS_STORAGE: + return "Mass Storage"; + case USB_CLASS_HUB: + return "Hub"; + case USB_CLASS_DATA: + return "CDC Data"; + case USB_CLASS_VENDOR_SPEC: + return "Vendor specific"; + default: + return ""; + } +} + +void usb_display_class_sub(unsigned char dclass, unsigned char subclass, + unsigned char proto) +{ + switch (dclass) { + case USB_CLASS_PER_INTERFACE: + printf("See Interface"); + break; + case USB_CLASS_HID: + printf("Human Interface, Subclass: "); + switch (subclass) { + case USB_SUB_HID_NONE: + printf("None"); + break; + case USB_SUB_HID_BOOT: + printf("Boot "); + switch (proto) { + case USB_PROT_HID_NONE: + printf("None"); + break; + case USB_PROT_HID_KEYBOARD: + printf("Keyboard"); + break; + case USB_PROT_HID_MOUSE: + printf("Mouse"); + break; + default: + printf("reserved"); + break; + } + break; + default: + printf("reserved"); + break; + } + break; + case USB_CLASS_MASS_STORAGE: + printf("Mass Storage, "); + switch (subclass) { + case US_SC_RBC: + printf("RBC "); + break; + case US_SC_8020: + printf("SFF-8020i (ATAPI)"); + break; + case US_SC_QIC: + printf("QIC-157 (Tape)"); + break; + case US_SC_UFI: + printf("UFI"); + break; + case US_SC_8070: + printf("SFF-8070"); + break; + case US_SC_SCSI: + printf("Transp. SCSI"); + break; + default: + printf("reserved"); + break; + } + printf(", "); + switch (proto) { + case US_PR_CB: + printf("Command/Bulk"); + break; + case US_PR_CBI: + printf("Command/Bulk/Int"); + break; + case US_PR_BULK: + printf("Bulk only"); + break; + default: + printf("reserved"); + break; + } + break; + default: + printf("%s", usb_get_class_desc(dclass)); + break; + } +} + +void usb_display_string(struct usb_device *dev, int idx) +{ + char buffer[256]; + if (idx != 0) { + if (usb_string(dev, idx, &buffer[0], 256) > 0) + printf("String: \"%s\"", buffer); + } +} + +void usb_display_desc(struct usb_device *dev) +{ + if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) { + printf("%d: %s, USB Revision %x.%x\n", dev->devnum, + usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass), + (dev->descriptor.bcdUSB>>8) & 0xff, + dev->descriptor.bcdUSB & 0xff); + + if (strlen(dev->mf) || strlen(dev->prod) || + strlen(dev->serial)) + printf(" - %s %s %s\n", dev->mf, dev->prod, + dev->serial); + if (dev->descriptor.bDeviceClass) { + printf(" - Class: "); + usb_display_class_sub(dev->descriptor.bDeviceClass, + dev->descriptor.bDeviceSubClass, + dev->descriptor.bDeviceProtocol); + printf("\n"); + } else { + printf(" - Class: (from Interface) %s\n", + usb_get_class_desc( + dev->config.if_desc[0].bInterfaceClass)); + } + printf(" - PacketSize: %d Configurations: %d\n", + dev->descriptor.bMaxPacketSize0, + dev->descriptor.bNumConfigurations); + printf(" - Vendor: 0x%04x Product 0x%04x Version %d.%d\n", + dev->descriptor.idVendor, dev->descriptor.idProduct, + (dev->descriptor.bcdDevice>>8) & 0xff, + dev->descriptor.bcdDevice & 0xff); + } + +} + +void usb_display_conf_desc(struct usb_config_descriptor *config, + struct usb_device *dev) +{ + printf(" Configuration: %d\n", config->bConfigurationValue); + printf(" - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces, + (config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ", + (config->bmAttributes & 0x20) ? "Remote Wakeup " : "", + config->MaxPower*2); + if (config->iConfiguration) { + printf(" - "); + usb_display_string(dev, config->iConfiguration); + printf("\n"); + } +} + +void usb_display_if_desc(struct usb_interface_descriptor *ifdesc, + struct usb_device *dev) +{ + printf(" Interface: %d\n", ifdesc->bInterfaceNumber); + printf(" - Alternate Setting %d, Endpoints: %d\n", + ifdesc->bAlternateSetting, ifdesc->bNumEndpoints); + printf(" - Class "); + usb_display_class_sub(ifdesc->bInterfaceClass, + ifdesc->bInterfaceSubClass, ifdesc->bInterfaceProtocol); + printf("\n"); + if (ifdesc->iInterface) { + printf(" - "); + usb_display_string(dev, ifdesc->iInterface); + printf("\n"); + } +} + +void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) +{ + printf(" - Endpoint %d %s ", epdesc->bEndpointAddress & 0xf, + (epdesc->bEndpointAddress & 0x80) ? "In" : "Out"); + switch ((epdesc->bmAttributes & 0x03)) { + case 0: + printf("Control"); + break; + case 1: + printf("Isochronous"); + break; + case 2: + printf("Bulk"); + break; + case 3: + printf("Interrupt"); + break; + } + printf(" MaxPacket %d", epdesc->wMaxPacketSize); + if ((epdesc->bmAttributes & 0x03) == 0x3) + printf(" Interval %dms", epdesc->bInterval); + printf("\n"); +} + +/* main routine to diasplay the configs, interfaces and endpoints */ +void usb_display_config(struct usb_device *dev) +{ + struct usb_config_descriptor *config; + struct usb_interface_descriptor *ifdesc; + struct usb_endpoint_descriptor *epdesc; + int i, ii; + + config = &dev->config; + usb_display_conf_desc(config, dev); + for (i = 0; i < config->no_of_if; i++) { + ifdesc = &config->if_desc[i]; + usb_display_if_desc(ifdesc, dev); + for (ii = 0; ii < ifdesc->no_of_ep; ii++) { + epdesc = &ifdesc->ep_desc[ii]; + usb_display_ep_desc(epdesc); + } + } + printf("\n"); +} + +static inline char *portspeed(int speed) +{ + if (speed == USB_SPEED_HIGH) + return "480 Mb/s"; + else if (speed == USB_SPEED_LOW) + return "1.5 Mb/s"; + else + return "12 Mb/s"; +} + +/* shows the device tree recursively */ +void usb_show_tree_graph(struct usb_device *dev, char *pre) +{ + int i, idx; + int has_child, last_child, port; + + idx = strlen(pre); + printf(" %s", pre); + /* check if the device has connected children */ + has_child = 0; + for (i = 0; i < dev->maxchild; i++) { + if (dev->children[i] != NULL) + has_child = 1; + } + /* check if we are the last one */ + last_child = 1; + if (dev->parent != NULL) { + for (i = 0; i < dev->parent->maxchild; i++) { + /* search for children */ + if (dev->parent->children[i] == dev) { + /* found our pointer, see if we have a + * little sister + */ + port = i; + while (i++ < dev->parent->maxchild) { + if (dev->parent->children[i] != NULL) { + /* found a sister */ + last_child = 0; + break; + } /* if */ + } /* while */ + } /* device found */ + } /* for all children of the parent */ + printf("\b+-"); + /* correct last child */ + if (last_child) + pre[idx-1] = ' '; + } /* if not root hub */ + else + printf(" "); + printf("%d ", dev->devnum); + pre[idx++] = ' '; + pre[idx++] = has_child ? '|' : ' '; + pre[idx] = 0; + printf(" %s (%s, %dmA)\n", usb_get_class_desc( + dev->config.if_desc[0].bInterfaceClass), + portspeed(dev->speed), + dev->config.MaxPower * 2); + if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial)) + printf(" %s %s %s %s\n", pre, dev->mf, dev->prod, dev->serial); + printf(" %s\n", pre); + if (dev->maxchild > 0) { + for (i = 0; i < dev->maxchild; i++) { + if (dev->children[i] != NULL) { + usb_show_tree_graph(dev->children[i], pre); + pre[idx] = 0; + } + } + } +} + +/* main routine for the tree command */ +void usb_show_tree(struct usb_device *dev) +{ + char preamble[32]; + + memset(preamble, 0, 32); + usb_show_tree_graph(dev, &preamble[0]); +} + + +/****************************************************************************** + * usb boot command intepreter. Derived from diskboot + */ +#if 0 +#ifdef CONFIG_USB_STORAGE +int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev, part = 1, rcode; + ulong addr, cnt; + disk_partition_t info; + image_header_t *hdr; + block_dev_desc_t *stor_dev; +#if defined(CONFIG_FIT) + const void *fit_hdr = NULL; +#endif + + switch (argc) { + case 1: + addr = CONFIG_SYS_LOAD_ADDR; + boot_device = getenv("bootdevice"); + break; + case 2: + addr = strtoul(argv[1], NULL, 16); + boot_device = getenv("bootdevice"); + break; + case 3: + addr = strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + default: +// cmd_usage(cmdtp); + return 1; + } + + if (!boot_device) { + puts("\n** No boot device **\n"); + return 1; + } + + dev = strtoul(boot_device, &ep, 16); + stor_dev = usb_stor_get_dev(dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) { + printf("\n** Device %d not available\n", dev); + return 1; + } + if (stor_dev->block_read == NULL) { + printf("storage device not initialized. Use usb scan\n"); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = strtoul(++ep, NULL, 16); + } + + if (get_partition_info(stor_dev, part, &info)) { + /* try to boot raw .... */ + strncpy((char *)&info.type[0], BOOT_PART_TYPE, + sizeof(BOOT_PART_TYPE)); + strncpy((char *)&info.name[0], "Raw", 4); + info.start = 0; + info.blksz = 0x200; + info.size = 2880; + printf("error reading partinfo...try to boot raw\n"); + } + if ((strncmp((char *)info.type, BOOT_PART_TYPE, + sizeof(info.type)) != 0) && + (strncmp((char *)info.type, BOOT_PART_COMP, + sizeof(info.type)) != 0)) { + printf("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + return 1; + } + printf("\nLoading from USB device %d, partition %d: " + "Name: %.32s Type: %.32s\n", + dev, part, info.name, info.type); + + debug("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (stor_dev->block_read(dev, info.start, 1, (ulong *)addr) != 1) { + printf("** Read error on %d:%d\n", dev, part); + return 1; + } + + switch (genimg_get_format((void *)addr)) { + case IMAGE_FORMAT_LEGACY: +// hdr = (image_header_t *)addr; + +// if (!image_check_hcrc(hdr)) { +// puts("\n** Bad Header Checksum **\n"); + return 1; + } + +// image_print_contents(hdr); + +// cnt = image_get_image_size(hdr); + break; +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + fit_hdr = (const void *)addr; + puts("Fit image detected...\n"); + + cnt = fit_get_size(fit_hdr); + break; +#endif + default: + puts("** Unknown image type\n"); + return 1; + } + + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + + if (stor_dev->block_read(dev, info.start+1, cnt, + (ulong *)(addr+info.blksz)) != cnt) { + printf("\n** Read error on %d:%d\n", dev, part); + return 1; + } + +#if defined(CONFIG_FIT) + /* This cannot be done earlier, we need complete FIT image in RAM + * first + */ + if (genimg_get_format((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format(fit_hdr)) { + puts("** Bad FIT image format\n"); + return 1; + } + fit_print_contents(fit_hdr); + } +#endif + + /* Loading ok, update default load address */ + load_addr = addr; + + flush_cache(addr, (cnt+1)*info.blksz); + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { + char *local_args[2]; + extern int do_bootm(cmd_tbl_t *, int, int, char *[]); + local_args[0] = argv[0]; + local_args[1] = NULL; + printf("Automatic boot of image at addr 0x%08lX ...\n", addr); + rcode = do_bootm(cmdtp, 0, 1, local_args); + return rcode; + } + return 0; +} +#endif +#endif /* CONFIG_USB_STORAGE */ + + +/****************************************************************************** + * usb command intepreter + */ +int do_usb(int argc, char **argv) +{ + + int i; + struct usb_device *dev = NULL; + +#ifdef CONFIG_USB_STORAGE + block_dev_desc_t *stor_dev; +#endif + extern char usb_started; + + if ((strncmp(argv[1], "reset", 5) == 0) || + (strncmp(argv[1], "start", 5) == 0)) { + usb_stop(); + printf("(Re)start USB...\n"); +#ifdef PCI_XBIOS + i = pci_init(); +#else + if (usb_init() >= 0) + i = 1; +#endif + +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i == 1) + usb_stor_curr_dev = usb_stor_scan( ); +#endif + return 0; + } + if (strncmp(argv[1], "stop", 4) == 0) { +#ifdef CONFIG_USB_KEYBOARD + if (argc == 2) { + if (usb_kbd_deregister() != 0) { + printf("USB not stopped: usbkbd still" + " using USB\n"); + return 1; + } + } else { + /* forced stop, switch console in to serial */ + usb_kbd_deregister(); + } +#endif + printf("stopping USB..\n"); + usb_stop(); + return 0; + } + if (!usb_started) { + printf("USB is stopped. Please issue 'usb start' first.\n"); + return 1; + } + + if (strncmp(argv[1], "tree", 4) == 0) { + printf("\nDevice Tree:\n"); + usb_show_tree(usb_get_dev_index(0)); + return 0; + } + if (strncmp(argv[1], "inf", 3) == 0) + { + int d1; + if (argc == 2) + { + for (d1 = 0; d1 < USB_MAX_DEVICE; d1++) { + dev = usb_get_dev_index(d1); + if (dev == NULL) + break; + usb_display_desc(dev); + usb_display_config(dev); + } + return 0; + } else + { + int d2; + + i = strtoul(argv[2], NULL, 16); + printf("config for device %d\n", i); + for (d2 = 0; d2 < USB_MAX_DEVICE; d2++) { + dev = usb_get_dev_index(d2); + if (dev == NULL) + break; + if (dev->devnum == i) + break; + } + if (dev == NULL) { + printf("*** NO Device avaiable ***\n"); + return 0; + } else { + usb_display_desc(dev); + usb_display_config(dev); + } + } + return 0; + } +#ifdef CONFIG_USB_STORAGE + if (strncmp(argv[1], "stor", 4) == 0) + return usb_stor_info(); +#if 0 + if (strncmp(argv[1], "part", 4) == 0) { + int devno, ok = 0; + if (argc == 2) { + for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) { + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) { + ok++; + if (devno) + printf("\n"); + printf("print_part of %x\n", devno); + print_part(stor_dev); + } + } + } else { + devno = strtoul(argv[2], NULL, 16); + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) { + ok++; + printf("print_part of %x\n", devno); + print_part(stor_dev); + } + } + if (!ok) { + printf("\nno USB devices available\n"); + return 1; + } + return 0; + } +#endif + if (strcmp(argv[1], "read") == 0) { + if (usb_stor_curr_dev < 0) { + printf("no current device selected\n"); + return 1; + } + if (argc == 5) { + unsigned long addr = strtoul(argv[2], NULL, 16); + unsigned long blk = strtoul(argv[3], NULL, 16); + unsigned long cnt = strtoul(argv[4], NULL, 16); + unsigned long n; + printf("\nUSB read: device %d block # %ld, count %ld" + " ... ", usb_stor_curr_dev, blk, cnt); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); + n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt, + (unsigned long *)addr); + printf("%ld blocks read: %s\n", n, + (n == cnt) ? "OK" : "ERROR"); + if (n == cnt) + return 0; + return 1; + } + } + if (strncmp(argv[1], "dev", 3) == 0) { + if (argc == 3) { + int device = (int)strtoul(argv[2], NULL, 10); + printf("\nUSB device %d: ", device); + if (device >= USB_MAX_STOR_DEV) { + printf("unknown device\n"); + return 1; + } + printf("\n Device %d: ", device); + stor_dev = usb_stor_get_dev(device); + dev_print(stor_dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) + return 1; + usb_stor_curr_dev = device; + printf("... is now current device\n"); + return 0; + } else { + printf("\nUSB device %d: ", usb_stor_curr_dev); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); + dev_print(stor_dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) + return 1; + return 0; + } + return 0; + } +#endif /* CONFIG_USB_STORAGE */ +// cmd_usage(cmdtp); + return 1; +} +#if 0 +#ifdef CONFIG_USB_STORAGE +U_BOOT_CMD( + usb, 5, 1, do_usb, + "USB sub-system", + "reset - reset (rescan) USB controller\n" + "usb stop [f] - stop USB [f]=force stop\n" + "usb tree - show USB device tree\n" + "usb info [dev] - show available USB devices\n" + "usb storage - show details of USB storage devices\n" + "usb dev [dev] - show or set current USB storage device\n" + "usb part [dev] - print partition table of one or all USB storage" + " devices\n" + "usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n" + " to memory address `addr'" +); + + +U_BOOT_CMD( + usbboot, 3, 1, do_usbboot, + "boot from USB device", + "loadAddr dev:part" +); + +#else +U_BOOT_CMD( + usb, 5, 1, do_usb, + "USB sub-system", + "reset - reset (rescan) USB controller\n" + "usb tree - show USB device tree\n" + "usb info [dev] - show available USB devices" +); +#endif +#endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/compile.txt b/BaS_codewarrior/FireBee/trunk/usb/store/compile.txt new file mode 100644 index 0000000..c14b6bd --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/compile.txt @@ -0,0 +1,6 @@ +I have used gcc 4.4.3 native version and gcc 4.4.3 cross-compiler version to +compile these sources. +There are 4 targets "make ethernat", "make netusbee", "make aranym", "make ohci-pci". +If you use cross-compiler add "CROSS=yes" to the commands above. +Before compiling "ohci-pci" target you must "make clean" if you have been compiling the other targets before. +"make all" compiles the 4 targets. diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/config.h b/BaS_codewarrior/FireBee/trunk/usb/store/config.h new file mode 100644 index 0000000..ce5464f --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/config.h @@ -0,0 +1,54 @@ +#ifndef _CONFIG_H +#define _CONFIG_H + +//#define ARCH m68k +//#define COLDFIRE /* Besides change one(first) .chip in detxbios.S 68060 or 5200 */ +//#define CONFIG_USB_ISP116X_HCD +//#define SUPERVISOR +/* Change .chip in detxbios.S 68060 or 5200 */ + +/*----- USB -----*/ +//#define CONFIG_LEGACY_USB_INIT_SEQ +#define CONFIG_USB_STORAGE +//#define CONFIG_USB_KEYBOARD +//#define CONFIG_USB_MOUSE +//#define CONFIG_USB_INTERRUPT_POLLING +#define CONFIG_USB_ARANYM_HCD +/*----- ISP116x-HCD ------*/ +#define ISP116X_HCD_USE_UDELAY +#define ISP116X_HCD_USE_EXTRA_DELAY +//#define ISP116X_HCD_SEL15kRES +//#define ISP116X_HCD_OC_ENABLE +//#define ISP116X_HCD_REMOTE_WAKEUP_ENABLE +/*----- OHCI-HCI -----*/ +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_OHCI +//#define PCI_XBIOS /* Defined in the makefile */ + + +/*----- DEBUG -----*/ +/* You should activate global debug, + * #define DEBUG_GLOBAL 1 to turn on + * #define DEBUG_GLOBAL 0 to turn off + * After global debug is enable + * you can activate the debug independently + * in each layer where debug is possible + */ + +#define DEBUG_GLOBAL 1 +#if DEBUG_GLOBAL +/* Define only one of the three debug posibilities below */ +#define DEBUG_TO_FILE 1 +#define DEBUG_TO_ARANYM 0 /* NOTE: No arguments are passed to the printf function */ +#define DEBUG_TO_CONSOLE 0 + +/* Define which local layer you want on */ +#define DEBUG_HOST_LAYER 0 +#define DEBUG_USB_LAYER 0 +#define DEBUG_HUB_LAYER 0 +#define DEBUG_STORAGE_LAYER 0 +#define DEBUG_XHDI_LAYER 0 +#define DEBUG_BIOS_LAYER 0 /* NOTE: Always to console */ + +#endif +#endif /* _CONFIG_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/debug.c b/BaS_codewarrior/FireBee/trunk/usb/store/debug.c new file mode 100644 index 0000000..a2a1a86 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/debug.c @@ -0,0 +1,64 @@ +/* + * debug.c + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "config.h" + +#include +#include +#include + + +#if DEBUG_TO_FILE +static FILE *debug_handle = NULL; + + +void +debug_init(char *file) +{ + char filename[20] = ""; + + strcpy(filename, file); + + debug_handle = fopen(filename, "a"); + + if (debug_handle != NULL) + setvbuf (debug_handle, NULL, _IONBF, 0); +} + + +void debug_exit(void) +{ + if (debug_handle != NULL && debug_handle != stdout) + fclose(debug_handle); + debug_handle = NULL; +} + + +void debug(char *FormatString, ...) +{ + va_list arg_ptr; + + va_start(arg_ptr, FormatString); + vfprintf(debug_handle, FormatString, arg_ptr); + va_end(arg_ptr); + fflush(debug_handle); + +} +#endif + + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/debug.h b/BaS_codewarrior/FireBee/trunk/usb/store/debug.h new file mode 100644 index 0000000..e64b59e --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/debug.h @@ -0,0 +1,97 @@ +/* + * debug.h + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _DEBUG_H +#define _DEBUG_H + +#include "config.h" +#include "host/aranym/nf_ops.h" + +void debug_init ( char *file); +void debug_exit ( void ); +void debug (char *FormatString, ...); + +/* You should activate global debug in config.h, uncommenting the #define DEBUG line */ +/* After global debug is enable you can activate them independly in each file */ + + +#if DEBUG_GLOBAL +#if DEBUG_TO_FILE +#define DEBUG(fmt, args...) debug_init("usb.log"); \ + debug( "%s: "fmt"\n\r" , __FUNCTION__, ##args); \ + debug_exit( ) +#endif /* DEBUG_TO_FILE */ + +#if DEBUG_TO_ARANYM +#define DEBUG(fmt, args...) nf_debug(fmt ) +#endif /* DEBUG_TO_ARANYM */ + +#if DEBUG_TO_CONSOLE +#define DEBUG(fmt, args...) printf("%s: "fmt"\n\r" , __FUNCTION__, ##args) +#endif /* DEBUG_TO_CONSOLE */ + +/* This allows control debug messages independenly for different layers */ +#if DEBUG_HOST_LAYER +#define DEBUG_HOST(fmt, args...) DEBUG(fmt, ##args) +#else +#define DEBUG_HOST(fmt, args...) {} +#endif +#if DEBUG_USB_LAYER +#define DEBUG_USB(fmt, args...) DEBUG(fmt, ##args) +#else +#define DEBUG_USB(fmt, args...) {} +#endif +#if DEBUG_HUB_LAYER +#define DEBUG_HUB(fmt, args...) DEBUG(fmt, ##args) +#else +#define DEBUG_HUB(fmt, args...) {} +#endif +#if DEBUG_STORAGE_LAYER +#define DEBUG_STORAGE(fmt, args...) DEBUG(fmt, ##args) +#else +#define DEBUG_STORAGE(fmt, args...) {} +#endif +#if DEBUG_XHDI_LAYER +#define DEBUG_XHDI(fmt, args...) DEBUG(fmt, ##args) +#else +#define DEBUG_XHDI(fmt, args...) {} +#endif + +#else +#define DEBUG(fmt, args...) {} +#if DEBUG_HOST_LAYER +#define DEBUG_HOST(fmt, args...) DEBUG(fmt, ##args) +#endif +#define DEBUG(fmt, args...) {} +#if DEBUG_USB_LAYER +#define DEBUG_USB(fmt, args...) DEBUG(fmt, ##args) +#endif +#if DEBUG_HUB_LAYER +#define DEBUG_HUB(fmt, args...) DEBUG(fmt, ##args) +#endif +#if DEBUG_STORAGE_LAYER +#define DEBUG_STORAGE(fmt, args...) DEBUG(fmt, ##args) +#endif +#if DEBUG_XHDI_LAYER +#define DEBUG_XHDI(fmt, args...) DEBUG(fmt, ##args) +#endif + +#endif /* DEBUG_GLOBAL */ + + +#endif /* _DEBUG_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/debug2.S b/BaS_codewarrior/FireBee/trunk/usb/store/debug2.S new file mode 100644 index 0000000..0c8dd8a --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/debug2.S @@ -0,0 +1,840 @@ +/* Debug the CT60 + * + * Didier Mequignon, 2003-2006, e-mail: aniplay@wanadoo.fr + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + .chip 68040 + .globl exception + +#ifdef COLDFIRE + .globl null + +#include "fire.h" +#endif + +#include "vars.h" + +#define DEBUG + +#ifdef DEBUG + .global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug +#endif + + .text + +#ifdef COLDFIRE + +null: + clr.l 0x380 // not valid + move.l SP,0x3C0 + move.l A6,0x3BC + lea 0x384,A6 + movem.l D0-D7/A0-A5,(A6) + clr.l 0x3C8 // USP + moveq #-1,D1 +#endif + +exception: + + clr.l memvalid + lea.l mess1(PC),A0 + bsr display_string +#ifdef COLDFIRE + ext.l D1 + addq.l #1,D1 + move.l D1,D7 // vector number +#else + addq.w #1,D1 + move.w D1,D7 // vector number +#endif + moveq #0,D0 + move.w D7,D0 +#ifdef COLDFIRE + .chip 68060 + divu #10,D0 + .chip 5200 + move.l D0,D1 + and.l #7,D0 + beq.s .ex1 + or.l #0x30,D0 + bsr display_char +.ex1: + swap D1 + move.w D1,D0 + or.l #0x30,D0 +#else + divu #10,D0 + and.w #7,D0 + beq.s .ex1 + or.w #0x30,D0 + bsr display_char +.ex1: + swap d0 + or.w #0x30,D0 +#endif + bsr display_char + moveq #0x3A,D0 + bsr display_char + moveq #0x20,D0 + bsr display_char + lea.l tab_mess_exc(PC),A0 + move.w D7,D0 + bsr display_tab + moveq #13,D0 + bsr display_char + moveq #10,D0 + bsr display_char +#ifdef COLDFIRE + tst.w D7 + beq .ex0 +#endif + lea.l mess2(PC),A0 // SR + bsr display_string +#ifdef COLDFIRE + move.w save_sr,D0 // SR +#else + move.l 0x3C0,A0 //SSP + move.w (A0),D0 +#endif + bsr hex_word // SR + lea.l mess3(PC),A0 + bsr display_string +#ifdef COLDFIRE + move.w save_sr,D2 // SR + and.l #0xB71F,D2 +#else + move.l 0x3C0,A0 //SSP + move.w (A0),D2 // SR + and.w #0xB71F,D2 +#endif + lea.l tab_status(PC),A1 + moveq #15,D1 +.ex5: + btst.l D1,D2 + beq.s .ex6 + moveq #0,D0 + move.b (A1,D1),D0 + move.w D0,D3 +#ifdef COLDFIRE + and.l #0xF8,D3 + cmp.l #0x30,D3 +#else + and.w #0xF8,D3 + cmp.w #0x30,D3 +#endif + bne.s .ex4 + move.w D0,-(SP) + moveq #0x49,D0 // I + bsr display_char + move.w (SP)+,D0 +.ex4: + bsr display_char + moveq #0x20,D0 + bsr display_char +.ex6: +#ifdef COLDFIRE + subq.l #1,D1 + bpl.s .ex5 +.ex0: +#else + dbf D1,.ex5 +#endif + lea.l mess4(PC),A0 // PC + bsr display_string +#ifdef COLDFIRE + move.l save_pc,D0 // PC +#else + move.l 0x3C0,A0 // SSP + move.l 2(A0),D0 // PC +#endif + bsr hex_long + lea.l mess10(PC),A0 // Basepage + bsr display_string + move.l 0x6EE4,D0 + bsr hex_long +#ifdef COLDFIRE + tst.w D7 + beq .ex2 +#endif + lea.l mess5(PC),A0 // CACR + bsr display_string +#ifdef COLDFIRE + .chip 68060 + movec.l CACR,D0 // from value stored in the CF68KLIB + .chip 5200 + bsr hex_long + cmp.l #2,D7 + bne.s .ex2 + lea.l mess6(PC),A0 // address fault + bsr display_string + move.l address_fault,D0 // from value stored in the CF68KLIB + bsr hex_long +#else /* ATARI - CT60 */ + movec.l CACR,D0 + bsr hex_long + cmp.w #2,D7 + beq.s .ex3 // Acces Fault + cmp.w #3,D7 + beq.s .ex3 // Adress Error + cmp.w #5,D7 + beq.s .ex3 // Zero Divide + cmp.w #9,D7 + bne .ex2 // <> Trace +.ex3: + lea.l mess6(PC),A0 // address fault + bsr display_string + move.l 0x3C0,A0 // SSP + move.l 8(A0),D0 // address fault + bsr hex_long + cmp.w #2,D7 + bne .ex2 // <> Acces Fault + lea.l mess7(PC),A0 // FSLW + bsr display_string + move.l 0x3C0,A0 // SSP + move.l 12(A0),D0 // FSLW + bsr hex_long + lea.l mess3(PC),A0 + bsr display_string + moveq #13,D0 + bsr display_char + moveq #10,D0 + bsr display_char + move.l 0x3C0,A0 // SSP + move.l 12(A0),D2 // FSLW + and.l #0x0BFFFFFD,D2 + lea.l tab_fslw1(PC),A1 + lea.l tab_fslw2(PC),A2 + lea.l tab_fslw3(PC),A3 + moveq #31,D1 + moveq #0,D3 +.ex13: + btst.l D1,D2 + beq.s .ex14 + moveq #0,D0 + move.b (A1,D3),D0 + bsr display_char + moveq #0,D0 + move.b (A2,D3),D0 + cmp.b #0x20,D0 + beq.s .ex12 + bsr display_char + moveq #0,D0 + move.b (A3,D3),D0 + cmp.b #0x20,D0 + beq.s .ex12 + bsr display_char +.ex12: + moveq #0x20,D0 + bsr display_char +.ex14: + addq.w #1,D3 + dbf D1,.ex13 +#endif /* COLDFIRE */ +.ex2: + lea.l mess8(PC),A0 // SSP + bsr display_string + move.l 0x3C0,D0 // SSP + bsr hex_long + lea.l mess9(PC),A0 // USP + bsr display_string + move.l 0x3C8,D0 // USP + bsr hex_long + lea.l 0x384,A1 // registers + lea.l 32(A1),A2 + moveq #7,D1 +.ex8: + moveq #13,D0 + bsr display_char + moveq #10,D0 + bsr display_char + moveq #0x44,D0 + bsr display_char + moveq #7,D0 +#ifdef COLDFIRE + sub.l D1,D0 + or.l #0x30,D0 +#else + sub.w D1,D0 + or.w #0x30,D0 +#endif + move.w D0,-(SP) + bsr display_nb + move.l (A1),D0 + bsr hex_long // data registers + moveq #0x20,D0 + bsr display_char + tst.w D1 + beq.s .ex9 + moveq #0x41,D0 + bsr display_char + move.w (SP),D0 + bsr display_nb + move.l (A2),D0 + bsr hex_long // address registers + moveq #0x20,D0 + bsr display_char +.ex9: + addq.l #2,SP + addq.l #4,A1 + addq.l #4,A2 +#ifdef COLDFIRE + subq.l #1,D1 + bpl.s .ex8 +#else + dbf D1,.ex8 +#endif + moveq #13,D0 + bsr display_char +.loop_wait_key: +#ifdef COLDFIRE +#ifdef DEBUG + move.w #1,-(SP) // AUX +#else + move.w #2,-(SP) // CON +#endif +#else + move.w #2,-(SP) // CON +#endif + move.w #2,-(SP) // Bconin + trap #13 + addq.l #4,SP + ext.l D0 + move.l D0,-(SP) + move.l #0x5F504349,D0 + lea 0xED0000,A0 // 128 KB + cmp.l (A0),D0 // _PCI + beq.s .pci_drivers + lea 0xEC0000,A0 // 192 KB + cmp.l (A0),D0 // _PCI + beq.s .pci_drivers + lea 0xEB0000,A0 // 256 KB + cmp.l (A0),D0 // _PCI + beq.s .pci_drivers + lea 0xEA0000,A0 // 320 KB + cmp.l (A0),D0 // _PCI + bne.s .no_pci_drivers +.pci_drivers: + jsr 40(A0) // drivers PCI in flash, add dbug (68k disassembler) + move.l D0,(SP) + bne .no_pci_drivers + addq.l #4,SP + bra.s .loop_wait_key +.no_pci_drivers: + move.l (SP)+,D0 +#ifdef COLDFIRE + and.l #0xFF,D0 + cmp.l #0x6D,D0 // m +#else + cmp.b #0x6D,D0 // m +#endif + beq.s .memory_dump +#ifdef COLDFIRE + cmp.l #0x70,D0 // p +#else + cmp.b #0x70,D0 // p +#endif + beq.s .patch_memory +#ifdef DEBUG +#ifdef COLDFIRE + cmp.l #0x20,D0 +#else + cmp.b #0x20,D0 +#endif + bne .loop_wait_key + lea mess14(PC),A0 + bsr display_string +#endif + rts +.memory_dump: + lea mess11(PC),A0 // memory dump + bsr display_string + bsr get_hex_value + move.l D0,A0 + bsr dump + bra .loop_wait_key +.patch_memory: + lea mess12(PC),A0 // patch memory + bsr display_string + bsr get_hex_value + move.l D0,A1 + lea mess13(PC),A0 // value + bsr display_string + bsr get_hex_value + cmp.l #0x100,D0 + bcc.s .word_value + move.b D0,(A1) + lea crlf(PC),A0 + bsr display_string + move.l A1,D0 + bsr hex_long + moveq #0x20,D0 + bsr display_char + move.b (A1),D0 + bsr hex_byte + bra .loop_wait_key +.word_value: + cmp.l #0x10000,D0 + bcc.s .long_value + move.w D0,(A1) + lea crlf(PC),A0 + bsr display_string + move.l A1,D0 + bsr hex_long + moveq #0x20,D0 + bsr display_char + move.w (A1),D0 + bsr hex_word + bra .loop_wait_key +.long_value: + move.l D0,(A1) + lea crlf(PC),A0 + bsr display_string + move.l A1,D0 + bsr hex_long + moveq #0x20,D0 + bsr display_char + move.l (A1),D0 + bsr hex_long + bra .loop_wait_key + +display_nb: + + bsr display_char + moveq #0x3A,D0 + bsr display_char + moveq #0x24,D0 + bsr display_char + rts + +display_tab: + +#ifdef COLDFIRE + move.l D1,-(SP) +#endif + move.w D0,-(SP) + moveq #0,D0 +.dt1: +#ifdef COLDFIRE + move.b (A0),D1 + extb.l D1 + cmp.l #-1,D1 + beq.s .dt3 + moveq #0,D1 + move.w (SP),D1 + cmp.l D1,D0 +#else + cmp.b #-1,(A0) + beq.s .dt3 + cmp.w (SP),D0 +#endif + beq.s .dt4 +.dt2: + tst.b (A0)+ + bne.s .dt2 +#ifdef COLDFIRE + addq.l #1,D0 +#else + addq.w #1,D0 +#endif + bra.s .dt1 +.dt4: + bsr display_string +.dt3: + + addq.l #2,SP +#ifdef COLDFIRE + move.l (SP)+,D1 +#endif + rts + +hex_long: + move.l D0,-(SP) + swap D0 + bsr.s hex_word + move.l (SP)+,D0 +hex_word: + move.w D0,-(SP) +#ifdef COLDFIRE + lsr.l #8,D0 + bsr.s hex_byte + move.w (SP)+,D0 +hex_byte: + move.w D0,-(SP) + lsr.l #4,D0 + bsr.s hex_char + move.w (SP)+,D0 +hex_char: + and.l #0xF,D0 + or.l #0x30,D0 + cmp.l #0x3A,D0 + bcs.s display_char + addq.l #7,D0 + +display_char: + and.l #0xFF,D0 +#ifdef DEBUG /* warning !!! If serial mouse */ + move.l D1,-(SP) +.wait_uart: + move.b MCF_UART_USR0,D1 + and.l #MCF_UART_USR_TXRDY,D1 + beq.s .wait_uart + move.b D0,MCF_UART_UTB0 // send the character + move.l (SP)+,D1 +#else + lea -24(SP),SP + movem.l D0-D2/A0-A2,(SP) + move.w D0,-(sp) + move.w #2,-(SP) + move.w #3,-(SP) // Bconout + trap #13 + addq.l #6,SP + movem.l (SP),D0-D2/A0-A2 + lea 24(SP),SP +#endif /* DEBUG */ + rts +#else /* ATARI */ + lsr.w #8,D0 + bsr.s hex_byte + move.w (SP)+,D0 +hex_byte: + move.w D0,-(SP) + lsr.b #4,D0 + bsr.s hex_char + move.w (SP)+,D0 +hex_char: + and.b #0xF,D0 + or.b #0x30,D0 + cmp.b #0x3A,D0 + bcs.s display_char + addq.b #7,D0 + +display_char: + and.w #0xFF,D0 + movem.l D0-D2/A0-A2,-(SP) + move.w D0,-(sp) + move.w #2,-(SP) + move.w #3,-(SP) // Bconout + trap #13 + addq.l #6,SP + movem.l (SP)+,D0-D2/A0-A2 + rts +#endif /* COLDFIRE */ + +display_string: + +#ifdef COLDFIRE + move.l D0,-(SP) + move.l A0,-(SP) +#else + movem.l D0/A0,-(SP) +#endif +.os2: + move.b (A0)+,D0 + beq.s .os1 + bsr display_char + bra.s .os2 +.os1: +#ifdef COLDFIRE + move.l (SP)+,A0 + move.l (SP)+,D0 +#else + movem.l (SP)+,D0/A0 +#endif + rts + +get_hex_value: + +#ifdef COLDFIRE + lea -56(SP),SP + movem.l D1-A5,(SP) + link A6,#-8 + moveq #0,D7 +.loop_get_value: +#ifdef DEBUG + move.w #1,-(SP) // AUX +#else + move.w #2,-(SP) // CON +#endif + move.w #2,-(SP) // Bconin + trap #13 + addq.l #4,SP + and.l #0xFF,D0 + cmp.l #13,D0 + beq.s .conv_get_value + cmp.l #8,D0 + bne.s .not_backspace + tst.w D7 + ble.s .loop_get_value + bsr display_char + subq.l #1,D7 + bra.s .loop_get_value +.not_backspace: + cmp.l #0x30,D0 + bcs.s .loop_get_value + cmp.l #0x39,D0 + bls.s .number_value + cmp.l #0x41,D0 + bcs.s .loop_get_value + cmp.l #0x46,D0 + bls.s .letter_value + cmp.l #0x61,D0 + bcs.s .loop_get_value + cmp.l #0x66,D0 + bhi.s .loop_get_value +.letter_value: + bsr display_char + and.l #0x0F,D0 + add.l #9,D0 + bra.s .store_value +.number_value: + bsr display_char + and.l #0x0F,D0 +.store_value: + move.b D0,-8(A6,D7) + addq.l #1,D7 + cmp.l #8,D7 + bcs .loop_get_value +.conv_get_value: + moveq #0,D0 + subq.l #1,D7 + bmi.s .end_get_value + moveq #0,D6 +.loop_value: + asl.l #4,D0 + moveq #0,D1 + move.b -8(A6,D6),D1 + or.l D1,D0 + addq.l #1,D6 + subq.l #1,D7 + bpl.s .loop_value +.end_get_value: + tst.l D0 + unlk A6 + movem.l (SP),D1-A5 + lea 56(SP),SP +#else /* ATARI */ + movem.l D1-A5,-(SP) + link A6,#-8 + moveq #0,D7 +.loop_get_value: + move.w #2,-(SP) // CON + move.w #2,-(SP) // Bconin + trap #13 + addq.l #4,SP + cmp.b #13,D0 + beq.s .conv_get_value + cmp.b #8,D0 + bne.s .not_backspace + tst.w D7 + ble.s .loop_get_value + bsr display_char + subq.w #1,D7 + bra.s .loop_get_value +.not_backspace: + cmp.b #0x30,D0 + bcs.s .loop_get_value + cmp.b #0x39,D0 + bls.s .number_value + cmp.b #0x41,D0 + bcs.s .loop_get_value + cmp.b #0x46,D0 + bls.s .letter_value + cmp.b #0x61,D0 + bcs.s .loop_get_value + cmp.b #0x66,D0 + bhi.s .loop_get_value +.letter_value: + bsr display_char + and.b #0x0F,D0 + add.b #9,D0 + bra.s .store_value +.number_value: + bsr display_char + and.b #0x0F,D0 +.store_value: + move.b D0,-8(A6,D7) + addq.w #1,D7 + cmp.w #8,D7 + bcs.s .loop_get_value +.conv_get_value: + moveq #0,D0 + subq.w #1,D7 + bmi.s .end_get_value + moveq #0,D6 +.loop_value: + asl.l #4,D0 + or.b -8(A6,D6),D0 + addq.w #1,D6 + dbf D7,.loop_value +.end_get_value: + tst.l D0 + unlk A6 + movem.l (SP)+,D1-A5 +#endif /* COLDFIRE */ + rts + +dump: + +#ifdef COLDFIRE + lea -20(SP),SP + movem.l D0-D2/A0-A1,(SP) +#else + movem.l D0-D2/A0-A1,-(SP) +#endif + move.l A0,A1 + moveq #3,D1 +.loop_dump1: + lea crlf(PC),A0 + bsr display_string + move.l A1,D0 + bsr hex_long + moveq #0x20,D0 + bsr display_char + moveq #15,D2 +.loop_dump2: + move.b (A1)+,D0 + bsr hex_byte + moveq #0x20,D0 + bsr display_char +#ifdef COLDFIRE + subq.l #1,D2 + bpl.s .loop_dump2 +#else + dbf D2,.loop_dump2 +#endif + lea -16(A1),A1 + moveq #15,D2 +.loop_dump3: + move.b (A1)+,D0 +#ifdef COLDFIRE + and.l #0xFF,D0 + cmp.l #0x20,D0 + bcs.s .dump_bad_char + cmp.l #0x7F,D0 +#else + cmp.b #0x20,D0 + bcs.s .dump_bad_char + cmp.b #0x7F,D0 +#endif + bcs.s .dump_ok +.dump_bad_char: + moveq #0x2E,D0 +.dump_ok: + bsr display_char +#ifdef COLDFIRE + subq.l #1,D2 + bpl.s .loop_dump3 + subq.l #1,D1 + bpl.s .loop_dump1 + movem.l (SP),D0-D2/A0-A1 + lea 20(SP),SP +#else + dbf D2,.loop_dump3 + dbf D1,.loop_dump1 + movem.l (SP)+,D0-D2/A0-A1 +#endif + rts + +crlf: .byte 13,10,0 +mess1: .byte 13,10 + .asciz "EXCEPTION PROCESSING " +mess2: .byte 13,10 + .asciz "Status Register (SR): $" +mess3: .asciz ", bits to 1: " +mess4: .byte 13,10 + .asciz "Program Counter (PC): $" +mess5: .byte 13,10 + .asciz "Cache Register (CACR): $" +mess6: .byte 13,10 + .asciz "Address Fault: $" +mess7: .byte 13,10 + .asciz "Fault Status Word (FSLW): " +mess8: .byte 13,10 + .asciz "Supervisor Stack (SSP): $" +mess9: .byte 13,10 + .asciz "User Stack (USP): $" +mess10: .byte 13,10 + .asciz "Basepage: $" +mess11: .byte 13,10 + .asciz "Memory dump (hex) ? " +mess12: .byte 13,10 + .asciz "Patch memory (hex) ? " +mess13: .byte 13,10 + .asciz "Value (hex) ? " +mess14: .byte 13,10 + .ascii "Pterm" + .byte 13,10,0 + +tab_mess_exc: +#ifdef COLDFIRE + .asciz "Null (jump or call)" +#else + .byte 0 +#endif + .byte 0 + .asciz "Access Fault" + .asciz "Address Error" + .asciz "Illegal Instruction" + .asciz "Integer Zero Divide" + .byte 0 + .byte 0 + .asciz "Privilege Violation" + .asciz "Trace" + .asciz "Line A" + .asciz "Line F" + .asciz "Emulator Interrupt" + .byte 0 + .asciz "Format Error" + .asciz "Uninitialised Interrupt" + .byte 0 + .byte 0 + .byte 0 + .byte 0 + .byte 0 + .byte 0 + .byte 0 + .byte 0 + .asciz "Spurious Interrupt" + .asciz "Interrupt level 1" + .asciz "Interrupt level 2" + .asciz "Interrupt level 3" + .asciz "Interrupt level 4" + .asciz "Interrupt level 5" + .asciz "Interrupt level 6" + .asciz "Interrupt level 7" + .asciz "Trap #0" + .asciz "Trap #1" + .asciz "Trap #2" + .asciz "Trap #3" + .asciz "Trap #4" + .asciz "Trap #5" + .asciz "Trap #6" + .asciz "Trap #7" + .asciz "Trap #8" + .asciz "Trap #9" + .asciz "Trap #10" + .asciz "Trap #11" + .asciz "Trap #12" + .asciz "Trap #13" + .asciz "Trap #14" + .asciz "Trap #15" + .byte -1 + +tab_status: .ascii "CVZNX 012 MS T" + +tab_fslw1: .ascii " M LRWSSTTTTTIPSPPIPSWTRWTB S" +tab_fslw2: .ascii " A K ZZTTMMMOBBTTLFPPWEETP S" +tab_fslw3: .ascii " 1010210 EEAB E RE E" diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c new file mode 100644 index 0000000..fe3dbb9 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c @@ -0,0 +1,150 @@ +/* + NatFeat USB host chip emulator + + ARAnyM (C) 2010 David Gálvez + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/*--- Include ---*/ + +#include +#include + +#include +#include + +#include "nf_ops.h" +#include "usbhost_nfapi.h" +#include "../../config.h" +#include "../../asm-m68k/io.h" +#include "../../usb.h" +#include "../../debug.h" + +/*--- Defines ---*/ + +#ifndef EINVFN +#define EINVFN -32 +#endif + +#ifndef DEV_CONSOLE +#define DEV_CONSOLE 2 +#endif + +#define DRIVER_NAME "ARAnyM USB host chip emulator" +#define VERSION "v0.1" + + +/*--- Functions prototypes ---*/ + +static void press_any_key(void); + + +/*--- Local variables ---*/ + +static struct nf_ops *nfOps; +static unsigned long nfUsbHostId; + + +/*--- Functions ---*/ + + +static void press_any_key(void) +{ + + (void) Cconws("- Press any key to continue -\r\n"); + while (Bconstat(DEV_CONSOLE) == 0) { }; +} + + +/* --- Transfer functions -------------------------------------------------- */ + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + int r; + + r = nfOps->call(USBHOST(USBHOST_SUBMIT_INT_MSG), dev, pipe, buffer, len, interval); + + return 0; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int r; + + r = nfOps->call(USBHOST(USBHOST_SUBMIT_CONTROL_MSG), dev, pipe, buffer, len, setup); + + return r; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int r; + + r = nfOps->call(USBHOST(USBHOST_SUBMIT_BULK_MSG), dev, pipe, buffer, len); + + return 0; +} + +/* --- Init functions ------------------------------------------------------ */ + +int usb_lowlevel_init(void) +{ + int r; + + (void) Cconws( + "\033p " DRIVER_NAME " " VERSION " \033q\r\n" + "Copyright (c) ARAnyM Development Team, " __DATE__ "\r\n" + ); + + nfOps = nf_init(); + if (!nfOps) { + (void) Cconws("__NF cookie not present on this system\r\n"); + press_any_key(); + return 0; + } + + nfUsbHostId=nfOps->get_id("USBHOST"); + if (nfUsbHostId == 0) { + (void) Cconws("NF USBHOST functions not present on this system\r\n"); + press_any_key(); + } + + /* List present devices */ + + r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_INIT)); + + if (!r) + (void) Cconws(" USB Init \r\n"); + else + (void) Cconws(" Couldn't init aranym host chip emulator \r\n"); + + return 0; + +} + +int usb_lowlevel_stop(void) +{ + int r; + + r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_STOP)); + + return 0; + +} + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat.c new file mode 100644 index 0000000..93edd30 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat.c @@ -0,0 +1,118 @@ +/* + * ARAnyM native features interface. + * (c) 2005-2008 ARAnyM development team + * + * In 2006 updated with FreeMiNT headers and code. + * In 2008 converted from "__NF" cookie to direct usage of NF instructions + * + **/ + +/* + * Copied from FreeMiNT source tree where Native Features were added recently + * + * Copyright 2003 Frank Naumann + * All rights reserved. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Author: Frank Naumann + * Started: 2003-12-13 + * + */ + +# include +# include +# include "nf_ops.h" + + +#define ARANYM 1 +# ifdef ARANYM + + +static unsigned long nf_get_id_instr = 0x73004e75UL; +static unsigned long nf_call_instr = 0x73014e75UL; + +static struct nf_ops _nf_ops = { (void*)&nf_get_id_instr, (void*)&nf_call_instr }; +static struct nf_ops *nf_ops = 0UL; + +extern int detect_native_features(void); + +struct nf_ops * +nf_init(void) +{ + if (Supexec(detect_native_features)) + { + nf_ops = &_nf_ops; + return nf_ops; + } + + return 0UL; +} + + +const char * +nf_name(void) +{ + static char buf[64] = "Unknown emulator"; + + if (nf_ops) + { + static int done = 0; + + if (!done) + { + long nfid_name = nf_ops->get_id("NF_NAME"); + + if (nfid_name) + nf_ops->call(nfid_name, buf, sizeof(buf)); + + done = 1; + } + } + + return buf; +} + +int +nf_debug(const char *msg) +{ + if (nf_ops) + { + long nfid_stderr = nf_ops->get_id("NF_STDERR"); + + if (nfid_stderr) + { + nf_ops->call(nfid_stderr, msg); + return 1; + } + } + + return 0; +} + +void +nf_shutdown(void) +{ + if (nf_ops) + { + long shutdown_id = nf_ops->get_id("NF_SHUTDOWN"); + + if (shutdown_id) + nf_ops->call(shutdown_id); + } +} + +# endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S new file mode 100644 index 0000000..e1b75b3 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S @@ -0,0 +1,76 @@ +/* + * ARAnyM native features interface. + * (c) 2005-2008 ARAnyM development team + * + * In 2006 updated with FreeMiNT headers and code. + * In 2008 converted from "__NF" cookie to direct usage of NF instructions + * + **/ + +/* + * Copied from FreeMiNT source tree where Native Features were added recently + * + * Copyright 2003 Frank Naumann + * All rights reserved. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Author: Frank Naumann + * Started: 2003-12-13 + * + * please send suggestions, patches or bug reports to me or + * the MiNT mailing list + * + */ + +#define ARANYM 1 +# ifdef ARANYM + + .text + + .globl _detect_native_features + +/* + * NatFeats test (routine retuns TRUE/FALSE (1/0) in D0) + */ +_detect_native_features: + + clr.l d0 // assume no NatFeats available + move.l sp,a1 // save the ssp + move.l (0x0010).w,a0 // illegal instruction vector + move.l #fail_natfeat,(0x0010).w + + nop // flush pipelines (for 68040+) + + pea (nf_version_name).w(pc) + subq.l #4,sp + dc.w 0x7300 // Jump to NATFEAT_ID + tst.l d0 + beq.s fail_natfeat + moveq #1,d0 // NatFeats detected + +fail_natfeat: + move.l a1,sp + move.l a0,(0x0010).w + + nop // flush pipelines (for 68040+) + + rts + +nf_version_name: + .ascii "NF_VERSION\0" + +# endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/nf_ops.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/nf_ops.h new file mode 100644 index 0000000..b8d1e79 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/nf_ops.h @@ -0,0 +1,63 @@ +/* + * $Id: nf_ops.h,v 1.2 2006-01-31 16:21:22 standa Exp $ + * + * ARAnyM Native Features suite. + * + * This file was taken from FreeMiNT. + * + * Copyright 2003 Frank Naumann + * All rights reserved. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Author: Frank Naumann + * Started: 2003-12-14 + * + * Please send suggestions, patches or bug reports to me or + * the MiNT mailing list. + * + */ + +# ifndef _m68k_nf_ops_h +# define _m68k_nf_ops_h + +#include /* for __CDECL */ + + +struct nf_ops +{ + long __CDECL (*get_id)(const char *); + long __CDECL (*call)(long id, ...); + long res[3]; +}; + + +/** + * Use this function to intialize Native Features. + * + * @return the pointer to 'struct nf_ops' or NULL when + * not available. + **/ +struct nf_ops *nf_init(void); + + +/* basic set native feature functions */ +const char *nf_name(void); +int nf_debug(const char *msg); +void nf_shutdown(void); + + +# endif /* _m68k_nf_ops_h */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h new file mode 100644 index 0000000..e8ffa2e --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h @@ -0,0 +1,40 @@ +/* + NatFeat USB Host chip emulator + + ARAnyM (C) 2010 David Gálvez + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _USBHOST_NFAPI_H +#define _USBHOST_NFAPI_H + +/* if you change anything in the enum {} below you have to increase + this ARAUSBHOST_NFAPI_VERSION! +*/ +#define ARAUSBHOST_NFAPI_VERSION 0x00000000 + +enum { + GET_VERSION = 0, /* no parameters, return NFAPI_VERSION in d0 */ + USBHOST_LOWLEVEL_INIT, + USBHOST_LOWLEVEL_STOP, + USBHOST_SUBMIT_CONTROL_MSG, + USBHOST_SUBMIT_INT_MSG, + USBHOST_SUBMIT_BULK_MSG +}; + +#define USBHOST(a) (nfUsbHostId + a) + +#endif /* _USBHOST_NFAPI_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c new file mode 100644 index 0000000..fbfa611 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c @@ -0,0 +1,1583 @@ +/* + * Modified for Atari-EtherNat by David Gálvez 2010 + * + * ISP116x HCD (Host Controller Driver) for u-boot. + * + * Copyright (C) 2006-2007 Rodolfo Giometti + * Copyright (C) 2006-2007 Eurotech S.p.A. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c" + * (original copyright message follows): + * + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This code is based on linux driver for sl811hs chip, source at + * drivers/usb/host/sl811.c: + * + * SL811 Host Controller Interface driver for USB. + * + * Copyright (c) 2003/06, Courage Co., Ltd. + * + * Based on: + * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, + * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, + * Adam Richter, Gregory P. Smith; + * 2.Original SL811 driver (hc_sl811.o) by Pei Liu + * 3.Rewrited as sl811.o by Yin Aihua + * + * [[GNU/GPL disclaimer]] + * + * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c" + * (original copyright message follows): + * + * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * [[GNU/GPL disclaimer]] + * + * Note: Part of this code has been derived from linux + */ +#include "../../config.h" +#include "../../asm-m68k/io.h" +#include "../../usb.h" +#include "../../debug.h" + +void udelay(unsigned long usec); + +//extern void boot_printf(const char *fmt, ...); + + +/* + * ISP116x chips require certain delays between accesses to its + * registers. The following timing options exist. + * + * 1. Configure your memory controller (the best) + * 2. Use ndelay (easiest, poorest). For that, enable the following macro. + * + * Value is in microseconds. + */ +#ifdef ISP116X_HCD_USE_UDELAY +#define UDELAY 1 +#endif + +/* + * On some (slowly?) machines an extra delay after data packing into + * controller's FIFOs is required, * otherwise you may get the following + * error: + * + * uboot> usb start + * (Re)start USB... + * USB: scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT + * isp116x: isp116x_submit_job: ****** FIFO not ready! ****** + * + * USB device not responding, giving up (status=4) + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * 3 USB Device(s) found + * scanning bus for storage devices... 0 Storage Device(s) found + * + * Value is in milliseconds. + */ +#ifdef ISP116X_HCD_USE_EXTRA_DELAY +#define EXTRA_DELAY 2 +#endif + +/* + * Enable the following defines if you wish enable extra debugging messages. + * Normal debug messages controlled from config.h. + */ + +//#define TRACE /* enable tracing code */ +//#define VERBOSE /* verbose debugging messages */ + +#include "isp116x.h" + +#define DRIVER_VERSION "08 Jan 2007" +static const char hcd_name[] = "isp116x-hcd"; + +struct isp116x isp116x_dev; +struct isp116x_platform_data isp116x_board; +static int got_rhsc; /* root hub status change */ +struct usb_device *devgone; /* device which was disconnected */ +static int rh_devnum; /* address of Root Hub endpoint */ + +/* ------------------------------------------------------------------------- */ + +#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL)) +#define min1_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) + +/* Galvez: added to avoid shadow warnings */ +#define min2_t(type,x,y) \ + ({ type __a = (x); type __b = (y); __a < __b ? __a : __b; }) + +/* ------------------------------------------------------------------------- */ + + +static int isp116x_reset(struct isp116x *isp116x); + +/* --- Debugging functions ------------------------------------------------- */ + +#define isp116x_show_reg(d, r) { \ + if ((r) < 0x20) { \ + DEBUG_HOST("%-12s[%02x]: %08x", #r, \ + r, isp116x_read_reg32(d, r)); \ + } else { \ + DEBUG_HOST("%-12s[%02x]: %04x", #r, \ + r, isp116x_read_reg16(d, r)); \ + } \ +} + +#define isp116x_show_regs(d) { \ + isp116x_show_reg(d, HCREVISION); \ + isp116x_show_reg(d, HCCONTROL); \ + isp116x_show_reg(d, HCCMDSTAT); \ + isp116x_show_reg(d, HCINTSTAT); \ + isp116x_show_reg(d, HCINTENB); \ + isp116x_show_reg(d, HCFMINTVL); \ + isp116x_show_reg(d, HCFMREM); \ + isp116x_show_reg(d, HCFMNUM); \ + isp116x_show_reg(d, HCLSTHRESH); \ + isp116x_show_reg(d, HCRHDESCA); \ + isp116x_show_reg(d, HCRHDESCB); \ + isp116x_show_reg(d, HCRHSTATUS); \ + isp116x_show_reg(d, HCRHPORT1); \ + isp116x_show_reg(d, HCRHPORT2); \ + isp116x_show_reg(d, HCHWCFG); \ + isp116x_show_reg(d, HCDMACFG); \ + isp116x_show_reg(d, HCXFERCTR); \ + isp116x_show_reg(d, HCuPINT); \ + isp116x_show_reg(d, HCuPINTENB); \ + isp116x_show_reg(d, HCCHIPID); \ + isp116x_show_reg(d, HCSCRATCH); \ + isp116x_show_reg(d, HCITLBUFLEN); \ + isp116x_show_reg(d, HCATLBUFLEN); \ + isp116x_show_reg(d, HCBUFSTAT); \ + isp116x_show_reg(d, HCRDITL0LEN); \ + isp116x_show_reg(d, HCRDITL1LEN); \ +} + +#if defined(TRACE) + +static int isp116x_get_current_frame_number(struct usb_device *usb_dev) +{ + struct isp116x *isp116x = &isp116x_dev; + + return isp116x_read_reg32(isp116x, HCFMNUM); +} + +static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, char *str) +{ +#if defined(VERBOSE) + int i; +#endif + DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx", + str, + isp116x_get_current_frame_number(dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe) ? 'O' : 'I', + usb_pipetype(pipe) < 2 ? + (usb_pipeint(pipe) ? + "INTR" : "ISOC") : + (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status); +#if defined(VERBOSE) + debug_init("usb.log"); + if (len > 0 && buffer) { + debug(__FILE__ ": data(%d):", len); + for (i = 0; i < 16 && i < len; i++) + debug(" %02x", ((__u8 *) buffer)[i]); + debug("%s\r\n", i < len ? "..." : ""); + } + debug_exit(); +#endif +} + +#define PTD_DIR_STR(ptd) ({char __c; \ + switch(PTD_GET_DIR(ptd)){ \ + case 0: __c = 's'; break; \ + case 1: __c = 'o'; break; \ + default: __c = 'i'; break; \ + }; __c;}) + +/* + Dump PTD info. The code documents the format + perfectly, right :) +*/ +static inline void dump_ptd(struct ptd *ptd) +{ +#if defined(VERBOSE) + int k; +#endif + + DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x", + PTD_GET_CC(ptd), + PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd), + PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), + PTD_GET_TOGGLE(ptd), + PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd)); +#if defined(VERBOSE) + debug_init("usb.log"); + debug("isp116x: %s: PTD(byte): ", __FUNCTION__); + for (k = 0; k < sizeof(struct ptd); ++k) { + debug("%02x ", ((u8 *) ptd)[k]); + } + debug("\n\r"); + debug_exit(); +#endif +} + +static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type) +{ +#if defined(VERBOSE) + int k; + + debug_init("usb.log"); + if (type == 0 /* 0ut data */ ) { + debug("isp116x: %s: out data: ", __FUNCTION__); + for (k = 0; k < PTD_GET_LEN(ptd); ++k) { + debug("%02x ", ((u8 *) buf)[k]); + } + debug("\n\r"); + } + if (type == 1 /* 1n data */ ) { + debug("isp116x: %s: in data: ", __FUNCTION__); + for (k = 0; k < PTD_GET_COUNT(ptd); ++k) { + debug("%02x ", ((u8 *) buf)[k]); + } + debug("\n\r"); + } + + debug_exit(); + + if (PTD_GET_LAST(ptd)) { + DEBUG_HOST("--- last PTD ---"); + } +#endif +} + +#else + +#define dump_msg(dev, pipe, buffer, len, str) do { } while (0) +#define dump_pkt(dev, pipe, buffer, len, setup, str, small) do {} while (0) + +#define dump_ptd(ptd) do {} while (0) +#define dump_ptd_data(ptd, buf, type) do {} while (0) + +#endif + +/* --- Virtual Root Hub ---------------------------------------------------- */ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x02, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 0x22, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'S', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'P', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '1', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '1', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '6', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'x', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* + * Hub class-specific descriptor is constructed dynamically + */ + +/* --- Virtual root hub management functions ------------------------------- */ + +static int rh_check_port_status(struct isp116x *isp116x) +{ + u32 temp, ndp, i; + int res; + + res = -1; + temp = isp116x_read_reg32(isp116x, HCRHSTATUS); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +/* --- HC management functions --------------------------------------------- */ + +/* Write len bytes to fifo, pad till 32-bit boundary + */ +static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len) +{ + u8 *dp = (u8 *) buf; + u16 *dp2 = (u16 *) buf; + u16 w; + int quot = len % 4; + +/* For EtherNat, take the raw_write out in write functions, here we don't + * like that EtherNat swap the bytes for us, so we swap them before we send + * them, then the bytes will arrive to the USB device with the correct positions + */ + if ((unsigned long)dp2 & 1) { + DEBUG_HOST("---not aligned ---"); + /* not aligned */ + for (; len > 1; len -= 2) { + w = *dp++; + w |= *dp++ << 8; + isp116x_write_data16(isp116x, w); + } + if (len) + isp116x_write_data16(isp116x, (u16) * dp); + } else { + DEBUG_HOST("---aligned ---"); + /* aligned */ + for (; len > 1; len -= 2) + isp116x_write_data16(isp116x, *dp2++); + if (len){DEBUG_HOST("write_data16\r\n"); /* GALVEZ: DEBUG */ + isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));} + } + if (quot == 1 || quot == 2) + isp116x_write_data16(isp116x, 0); +} + +/* Read len bytes from fifo and then read till 32-bit boundary + */ +static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len) +{ + u8 *dp = (u8 *) buf; + u16 *dp2 = (u16 *) buf; + u16 w; + int quot = len % 4; + +/* For EtherNAT, take the raw_read out from read functions, we want to swap the bytes + to read correct values because EtherNat swapped the bytes by hardware before we read + them */ + + if ((unsigned long)dp2 & 1) { + /* not aligned */ + DEBUG_HOST("---not aligned ---"); + for (; len > 1; len -= 2) { + w = isp116x_read_data16(isp116x); + *dp++ = w & 0xff; + *dp++ = (w >> 8) & 0xff; + } + if (len) + *dp = 0xff & isp116x_read_data16(isp116x); + } else { + /* aligned */ + DEBUG_HOST("---aligned ---"); + for (; len > 1; len -= 2) + *dp2++ = isp116x_read_data16(isp116x); + if (len) + *(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x); + } + if (quot == 1 || quot == 2) + isp116x_read_data16(isp116x); +} + +/* Write PTD's and data for scheduled transfers into the fifo ram. + * Fifo must be empty and ready */ +static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev, + unsigned long pipe, struct ptd *ptd, int n, void *data, + int len) +{ + int buflen = n * sizeof(struct ptd) + len; + int i, done; + + DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen); + + isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT); + + isp116x_write_reg16(isp116x, HCXFERCTR, buflen); + isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET); + + done = 0; + for (i = 0; i < n; i++) { + DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i])); + +/* For EtherNAT, use raw_write to don't swap bytes */ + dump_ptd(&ptd[i]); + isp116x_raw_write_data16(isp116x, ptd[i].count); + isp116x_raw_write_data16(isp116x, ptd[i].mps); + isp116x_raw_write_data16(isp116x, ptd[i].len); + isp116x_raw_write_data16(isp116x, ptd[i].faddr); + + dump_ptd_data(&ptd[i], (__u8 *) data + done, 0); + + write_ptddata_to_fifo(isp116x, + (__u8 *) data + done, + PTD_GET_LEN(&ptd[i])); + + done += PTD_GET_LEN(&ptd[i]); + } +} + +/* Read the processed PTD's and data from fifo ram back to URBs' buffers. + * Fifo must be full and done */ +static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev, + unsigned long pipe, struct ptd *ptd, int n, void *data, + int len) +{ + int buflen = n * sizeof(struct ptd) + len; + int i, done, cc, ret; + + isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT); + isp116x_write_reg16(isp116x, HCXFERCTR, buflen); + isp116x_write_addr(isp116x, HCATLPORT); + + ret = TD_CC_NOERROR; + done = 0; + for (i = 0; i < n; i++) { + /* Galvez: DEBUG */ +// DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i])); + DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i])); + /*****************/ + + /* For EtherNAT, use raw_read to don't swap bytes */ + ptd[i].count = isp116x_raw_read_data16(isp116x); + ptd[i].mps = isp116x_raw_read_data16(isp116x); + ptd[i].len = isp116x_raw_read_data16(isp116x); + ptd[i].faddr = isp116x_raw_read_data16(isp116x); + dump_ptd(&ptd[i]); + + /* when cc is 15 the data has not being touch by the HC + * so we have to read all to empty completly the buffer + */ +// if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 ) + read_ptddata_from_fifo(isp116x, + (__u8 *) data + done, + PTD_GET_LEN(&ptd[i])); + dump_ptd_data(&ptd[i], (__u8 *) data + done, 1); + + done += PTD_GET_LEN(&ptd[i]); + + cc = PTD_GET_CC(&ptd[i]); + + /* Data underrun means basically that we had more buffer space than + * the function had data. It is perfectly normal but upper levels have + * to know how much we actually transferred. + */ + if (cc == TD_NOTACCESSED || + (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN))) + ret = cc; + } + + DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd)); + + return ret; +} + +/* Interrupt handling + */ +static int isp116x_interrupt(struct isp116x *isp116x) +{ + u16 irqstat; + u32 intstat; + int ret = 0; + + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + irqstat = isp116x_read_reg16(isp116x, HCuPINT); + isp116x_write_reg16(isp116x, HCuPINT, irqstat); + DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat); + + if (irqstat & HCuPINT_ATL) { + DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<"); + udelay(500); + ret = 1; + } + + if (irqstat & HCuPINT_OPR) { + intstat = isp116x_read_reg32(isp116x, HCINTSTAT); + isp116x_write_reg32(isp116x, HCINTSTAT, intstat); + DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat); + + if (intstat & HCINT_UE) { + ERR("unrecoverable error, controller disabled"); + + /* FIXME: be optimistic, hope that bug won't repeat + * often. Make some non-interrupt context restart the + * controller. Count and limit the retries though; + * either hardware or software errors can go forever... + */ + isp116x_reset(isp116x); + ret = -1; + return -1; + } + + if (intstat & HCINT_RHSC) { + got_rhsc = 1; + ret = 1; + /* When root hub or any of its ports is going + to come out of suspend, it may take more + than 10ms for status bits to stabilize. */ + wait_ms(20); + } + + if (intstat & HCINT_SO) { + ERR("schedule overrun"); + ret = -1; + } + + irqstat &= ~HCuPINT_OPR; + } + + return ret; +} + +/* With one PTD we can transfer almost 1K in one go; + * HC does the splitting into endpoint digestible transactions + */ +struct ptd ptd[1]; + +static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe) +{ + unsigned mpck = usb_maxpacket(dev, pipe); + + /* One PTD can transfer 1023 bytes but try to always + * transfer multiples of endpoint buffer size + */ + return 1023 / mpck * mpck; +} + +/* Do an USB transfer + */ +static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, + int dir, void *buffer, int len) +{ + struct isp116x *isp116x = &isp116x_dev; + int type = usb_pipetype(pipe); + int epnum = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + int dir_out = usb_pipeout(pipe); + int speed_low = usb_pipeslow(pipe); + int i, done = 0, stat, timeout, cc; + + /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */ + int retries = 500; + + + DEBUG_HOST("------------------------------------------------"); + dump_msg(dev, pipe, buffer, len, "SUBMIT"); + DEBUG_HOST("------------------------------------------------"); + + if (len >= 1024) { + ERR("Too big job"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + if (isp116x->disabled) { + ERR("EPIPE"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + ERR("ENODEV"); + dev->status = USB_ST_CRC_ERR; + return USB_ST_CRC_ERR; + } + + if (!max) { + ERR("pipesize for pipe %lx is zero", pipe); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + if (type == PIPE_ISOCHRONOUS) { + ERR("isochronous transfers not supported"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + /* FIFO not empty? */ + if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) { + DEBUG_HOST("****** FIFO not empty! ******"); + printf("****** FIFO not empty! ******\n\r"); + dev->status = USB_ST_BUF_ERR; + return -1; + } + +retry: + isp116x_write_reg32(isp116x, HCINTSTAT, 0xff); + /* Prepare the PTD data */ + ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK | + PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); + ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK; + ptd->len = PTD_LEN(len) | PTD_DIR(dir); + ptd->faddr = PTD_FA(usb_pipedevice(pipe)); + + +retry_same: + + /* FIFO not empty? */ /* GALVEZ: DEBUG */ + if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) { + DEBUG_HOST("****** FIFO not empty! ******"); + printf("****** FIFO not empty! ******\n\r"); + dev->status = USB_ST_BUF_ERR; + return -1; + } + + /* Pack data into FIFO ram */ + pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + +#ifdef EXTRA_DELAY + wait_ms(EXTRA_DELAY); +#endif + + /* Start the data transfer */ + + /* Allow more time for a BULK device to react - some are slow */ + if (usb_pipebulk(pipe)) + timeout = 5000; /* Galvez: default = 5000 */ + else + timeout = 100; + + /* Wait for it to complete */ + for (;;) { + /* Check whether the controller is done */ + stat = isp116x_interrupt(isp116x); + + if (stat < 0) { + dev->status = USB_ST_CRC_ERR; + break; + } + if (stat > 0) + break; + + /* Check the timeout */ + if (--timeout) + udelay(1); + else { + ERR("CTL:TIMEOUT "); + printf("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + + /* We got an Root Hub Status Change interrupt */ + if (got_rhsc) { + isp116x_show_regs(isp116x); + + got_rhsc = 0; + + /* Abuse timeout */ + timeout = rh_check_port_status(isp116x); + if (timeout >= 0) { + /* + * FIXME! NOTE! AAAARGH! + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + + /* Ok, now we can read transfer status */ + + /* FIFO not ready? */ + if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) { + DEBUG_HOST("****** FIFO not ready! ******"); + printf("****** FIFO not ready! ******\n\r"); + dev->status = USB_ST_BUF_ERR; + return -1; + } + + + /* Unpack data from FIFO ram */ + cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + + i = PTD_GET_COUNT(ptd); + done += i; + buffer += i; + len -= i; + + + /* There was some kind of real problem; Prepare the PTD again + * and retry from the failed transaction on + */ + if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) { + DEBUG_HOST("PROBLEM cc: %d", cc); + if (retries >= 100) { + retries -= 100; + /* The chip will have toggled the toggle bit for the failed + * transaction too. We have to toggle it back. + */ + usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed + * the transactions from the first on for the whole frame. It may be busy and we retry + * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the + * PTD didn't make it because the function was busy or the frame ended before the PTD + * finished. We prepare the rest of the data and try again. + */ + else if ( cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) { + DEBUG_HOST("NORMAL ERROR"); + if (retries) { + --retries; + if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) { + goto retry_same; + } + usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + + + if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) { + DEBUG_HOST("****** completition code error %x ******", cc); + switch (cc) { + case TD_CC_BITSTUFFING: + dev->status = USB_ST_BIT_ERR; + break; + case TD_CC_STALL: + dev->status = USB_ST_STALLED; + break; + case TD_BUFFEROVERRUN: + case TD_BUFFERUNDERRUN: + dev->status = USB_ST_BUF_ERR; + break; + default: + dev->status = USB_ST_CRC_ERR; + } + return -cc; + } + else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + + dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)"); + + dev->status = 0; + return done; +} + +/* Adapted from au1x00_usb_ohci.c + */ +static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *cmd) +{ + struct isp116x *isp116x = &isp116x_dev; + u32 tmp = 0; + + int leni = transfer_len; + int len = 0; + int stat = 0; + u32 datab[4]; + u8 *data_buf = (u8 *) datab; + u16 bmRType_bReq; + u16 wValue; + u16 wIndex; + u16 wLength; + + if (usb_pipeint(pipe)) { + INFO("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + + DEBUG_HOST("--- HUB ----------------------------------------"); + DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d", + bmRType_bReq, wValue, wIndex, wLength); + dump_msg(dev, pipe, buffer, transfer_len, "RH"); + DEBUG_HOST("------------------------------------------------"); + + switch (bmRType_bReq) { + case RH_GET_STATUS: + DEBUG_HOST("RH_GET_STATUS"); + + *(__u16 *) data_buf = swap_16(1); + len = 2; + break; + + case RH_GET_STATUS | RH_INTERFACE: + DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_ENDPOINT: + DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_CLASS: + DEBUG_HOST("RH_GET_STATUS | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHSTATUS); + + *(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE)); + len = 4; + break; + + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1); + *(__u32 *) data_buf = swap_32(tmp); + isp116x_show_regs(isp116x); + len = 4; + break; + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT"); + + switch (wValue) { + case RH_ENDPOINT_STALL: + DEBUG_HOST("C_HUB_ENDPOINT_STALL"); + len = 0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS"); + + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + DEBUG_HOST("C_HUB_LOCAL_POWER"); + len = 0; + break; + + case RH_C_HUB_OVER_CURRENT: + DEBUG_HOST("C_HUB_OVER_CURRENT"); + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC); + len = 0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS"); + + switch (wValue) { + case RH_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_CCS); + len = 0; + break; + + case RH_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_POCI); + len = 0; + break; + + case RH_PORT_POWER: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_LSDA); + len = 0; + break; + + case RH_C_PORT_CONNECTION: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_CSC); + len = 0; + break; + + case RH_C_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PESC); + len = 0; + break; + + case RH_C_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PSSC); + len = 0; + break; + + case RH_C_PORT_OVER_CURRENT: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_POCI); + len = 0; + break; + + case RH_C_PORT_RESET: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PRSC); + len = 0; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + isp116x_show_regs(isp116x); + + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS"); + + switch (wValue) { + case RH_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PSS); + len = 0; + break; + + case RH_PORT_RESET: + /* Spin until any current reset finishes */ + while (1) { + tmp = + isp116x_read_reg32(isp116x, + HCRHPORT1 + wIndex - 1); + if (!(tmp & RH_PS_PRS)) + break; + wait_ms(1); + } + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PRS); + wait_ms(10); + + len = 0; + break; + + case RH_PORT_POWER: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PPS); + len = 0; + break; + + case RH_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PES); + len = 0; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + isp116x_show_regs(isp116x); + + break; + + case RH_SET_ADDRESS: + DEBUG_HOST("RH_SET_ADDRESS"); + + rh_devnum = wValue; + len = 0; + break; + + case RH_GET_DESCRIPTOR: + DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength); + + switch (wValue) { + case (USB_DT_DEVICE << 8): /* device descriptor */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; + break; + + case (USB_DT_CONFIG << 8): /* configuration descriptor */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; + break; + + case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + break; + + case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHDESCA); + + data_buf[0] = 0x09; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = tmp & RH_A_NDP; + data_buf[3] = 0; + if (tmp & RH_A_PSM) /* per-port power switching? */ + data_buf[3] |= 0x01; + if (tmp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf[3] |= 0x10; + else if (tmp & RH_A_OCPM) /* per-port overcurrent rep? */ + data_buf[3] |= 0x08; + + /* Corresponds to data_buf[4-7] */ + datab[1] = 0; + data_buf[5] = (tmp & RH_A_POTPGT) >> 24; + + tmp = isp116x_read_reg32(isp116x, HCRHDESCB); + + data_buf[7] = tmp & RH_B_DR; + if (data_buf[2] < 7) + data_buf[8] = 0xff; + else { + data_buf[0] += 2; + data_buf[8] = (tmp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + + len = min1_t(unsigned int, leni, + min2_t(unsigned int, data_buf[0], wLength)); + break; + + case RH_GET_CONFIGURATION: + DEBUG_HOST("RH_GET_CONFIGURATION"); + + *(__u8 *) data_buf = 0x01; + len = 1; + break; + + case RH_SET_CONFIGURATION: + DEBUG_HOST("RH_SET_CONFIGURATION"); + + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC); + len = 0; + break; + + default: + ERR("*** *** *** unsupported root hub command *** *** ***"); + stat = USB_ST_STALLED; + } + + len = min1_t(int, len, leni); + if (buffer != data_buf) + memcpy(buffer, data_buf, len); + + dev->act_len = len; + dev->status = stat; + DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status); + + dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)"); + + return stat; +} + +/* --- Transfer functions -------------------------------------------------- */ + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d", + dev, pipe, buffer, len, interval); + + return -1; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + int epnum = usb_pipeendpoint(pipe); + int max = max_transfer_len(dev, pipe); + int dir_in = usb_pipein(pipe); + int done, ret; + + + /* Control message is for the HUB? */ + if (devnum == rh_devnum) + return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup); + + /* Ok, no HUB message so send the message to the device */ + + /* Setup phase */ + DEBUG_HOST("--- SETUP PHASE --------------------------------"); + usb_settoggle(dev, epnum, 1, 0); + + + ret = isp116x_submit_job(dev, pipe, + PTD_DIR_SETUP, + setup, sizeof(struct devrequest)); + if (ret < 0) { + DEBUG_HOST("control setup phase error (ret = %d", ret); + return -1; + } + + /* Data phase */ + DEBUG_HOST("--- DATA PHASE ---------------------------------"); + done = 0; + usb_settoggle(dev, epnum, !dir_in, 1); + while (done < len) { + ret = isp116x_submit_job(dev, pipe, + dir_in ? PTD_DIR_IN : PTD_DIR_OUT, + (__u8 *) buffer + done, + max > len - done ? len - done : max); + if (ret < 0) { + DEBUG_HOST("control data phase error (ret = %d)", ret); + return -1; + } + done += ret; + + if (dir_in && ret < max) /* short packet */ + break; + } + + /* Status phase */ + DEBUG_HOST("--- STATUS PHASE -------------------------------"); + usb_settoggle(dev, epnum, !dir_in, 1); + ret = isp116x_submit_job(dev, pipe, + !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0); + if (ret < 0) { + DEBUG_HOST("control status phase error (ret = %d", ret); + return -1; + } + + dev->act_len = done; + + dump_msg(dev, pipe, buffer, len, "DEV(ret)"); + + return done; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int dir_out = usb_pipeout(pipe); + int max = max_transfer_len(dev, pipe); + int done, ret; + + DEBUG_HOST("--- BULK ---------------------------------------"); + DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d", + usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); + + done = 0; + while (done < len) { + + ret = isp116x_submit_job(dev, pipe, + !dir_out ? PTD_DIR_IN : PTD_DIR_OUT, + (__u8 *) buffer + done, + max > len - done ? len - done : max); + + if (ret < 0) { + DEBUG_HOST("error on bulk message (ret = %d)", ret); + return -1; + } + + done += ret; + + if (!dir_out && ret < max) /* short packet */ + break; + } + + dev->act_len = done; + + return 0; +} + +/* --- Basic functions ----------------------------------------------------- */ + + +#if 0 +/* GALVEZ: Test function */ +static int GALVEZ_test_function( struct isp116x *isp116x ) +{ + short rwc; + + rwc = isp116x_read_reg16(isp116x, HCCONTROL) & HCCONTROL_RWC; + if (rwc) { + INFO ("remote wake-up supported \n\r"); + } + return 0; + +} +#endif + +static int isp116x_sw_reset(struct isp116x *isp116x) +{ + int retries = 15; + int ret = 0; + + DEBUG_HOST(""); + + isp116x->disabled = 1; + + isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC); + isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR); + + while (--retries) { + /* It usually resets within 1 ms */ + /* GALVEZ: not enough for TOS, try 7 ms */ + wait_ms(7); + if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) + break; + } + + if (!retries) { + ERR("software reset timeout"); + ret = -1; + } + +#if 0 + /* GALVEZ: DEBUG SOFTWARE RESET */ + + retries = 5000; + + while (--retries){ + if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) { + INFO ("HCR: 1 retries: %d\n\r",retries); + } + } +#endif /* END DEBUG */ + + return ret; +} + +static int isp116x_reset(struct isp116x *isp116x) +{ + unsigned long t; + u16 clkrdy = 0; + int ret, timeout = 15;/* ms + * Galvez: 15 ms sometimes isn't enough, + * for EtherNat under TOS ??????? increased to 150 ms + */ + + DEBUG_HOST(""); + + ret = isp116x_sw_reset(isp116x); + + if (ret) + return ret; + + for (t = 0; t < timeout; t++) { + clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY; + if (clkrdy) + break; + wait_ms(1); + } + if (!clkrdy) { + ERR("clock not ready after %dms", timeout); + /* After sw_reset the clock won't report to be ready, if + H_WAKEUP pin is high. */ + ERR("please make sure that the H_WAKEUP pin is pulled low!"); + ret = -1; + } + return ret; +} + +static void isp116x_stop(struct isp116x *isp116x) +{ + u32 val; + + DEBUG_HOST(""); + + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + + /* Switch off ports' power, some devices don't come up + after next 'start' without this */ + val = isp116x_read_reg32(isp116x, HCRHDESCA); + val &= ~(RH_A_NPS | RH_A_PSM); + isp116x_write_reg32(isp116x, HCRHDESCA, val); + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS); + + isp116x_sw_reset(isp116x); + +#if 0 + /* EtherNAT control register, disamble interrupt for USB */ + u8 *cpld_cr, value; + p = SuperFromUser(); + cpld_cr = ETHERNAT_CPLD_CR; + value = *cpld_cr; + INFO ("ETHERNAT_CPLD_CR %x", value); + value &= 0xFB; + INFO ("ETHERNAT_CPLD_CR %x", value); + *cpld_cr = value; + SuperToUser(p); +#endif +} + +/* + * Configure the chip. The chip must be successfully reset by now. + */ +static int isp116x_start(struct isp116x *isp116x) +{ + struct isp116x_platform_data *board = isp116x->board; + u32 val; + + DEBUG_HOST(""); + + /* Clear interrupt status and disable all interrupt sources */ + isp116x_write_reg16(isp116x, HCuPINT, 0xff); + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + + isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE); + isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE); + + /* Hardware configuration */ + val = HCHWCFG_DBWIDTH(1); + + if (board->sel15Kres) + val |= HCHWCFG_15KRSEL; + /* Remote wakeup won't work without working clock */ + if (board->remote_wakeup_enable) + val |= HCHWCFG_CLKNOTSTOP; + if (board->oc_enable) + val |= HCHWCFG_ANALOG_OC; + isp116x_write_reg16(isp116x, HCHWCFG, val); + +#if 0 + /* EtherNAT control register, enable interrupt for USB */ + u8 *cpld_cr, value; + p = SuperFromUser(); + cpld_cr = ETHERNAT_CPLD_CR; + INFO ("%s: ETHERNAT_CPLD_CR reg: %x",__FUNCTION__, *cpld_cr); + value = *cpld_cr; + value |= 0x04; + Bconin(DEV_CONSOLE); + *cpld_cr = value; + Bconin(DEV_CONSOLE); + INFO ("%s: ETHERNAT_CPLD_CR reg:%x", __FUNCTION__, *cpld_cr); + SuperToUser(p); +#endif + /* --- Root hub configuration */ + val = (25 << 24) & RH_A_POTPGT; + /* AN10003_1.pdf recommends RH_A_NPS (no power switching) to + be always set. Yet, instead, we request individual port + power switching. */ + val |= RH_A_PSM; + /* Report overcurrent per port */ + val |= RH_A_OCPM; + isp116x_write_reg32(isp116x, HCRHDESCA, val); + isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA); + + val = RH_B_PPCM; + isp116x_write_reg32(isp116x, HCRHDESCB, val); + isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB); + + val = 0; + if (board->remote_wakeup_enable) + val |= RH_HS_DRWE; + isp116x_write_reg32(isp116x, HCRHSTATUS, val); + isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS); + + isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf); + + /* Go operational */ + val = HCCONTROL_USB_OPER; + if (board->remote_wakeup_enable) + val |= HCCONTROL_RWE; + isp116x_write_reg32(isp116x, HCCONTROL, val); + + /* Disable ports to avoid race in device enumeration */ + isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS); + isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS); + + isp116x_show_regs(isp116x); + + isp116x->disabled = 0; + + return 0; +} + +/* --- Init functions ------------------------------------------------------ */ + + + +int isp116x_check_id(struct isp116x *isp116x) +{ + u16 val; + + val = isp116x_read_reg16(isp116x, HCCHIPID); + DEBUG_HOST("chip ID: %04x", val); + + if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) { + printf("invalid chip ID %04x", val); + return -1; + } + + return 0; +} + + +int usb_lowlevel_init(void) +{ +// u16 val; + + struct isp116x *isp116x = &isp116x_dev; + + DEBUG_HOST(""); + + got_rhsc = rh_devnum = 0; + + /* Init device registers addr */ + isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR; + isp116x->data_reg = (u16 *) ISP116X_HCD_DATA; + + /* Setup specific board settings */ +#ifdef ISP116X_HCD_SEL15kRES + isp116x_board.sel15Kres = 1; +#endif +#ifdef ISP116X_HCD_OC_ENABLE + isp116x_board.oc_enable = 1; +#endif +#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE + isp116x_board.remote_wakeup_enable = 1; +#endif + isp116x->board = &isp116x_board; + + /* Try to get ISP116x silicon chip ID */ + if (isp116x_check_id(isp116x) < 0) + return (-1); + + isp116x->disabled = 1; + isp116x->sleeping = 0; + + isp116x_reset(isp116x); + isp116x_start(isp116x); + + return 0; +} + +int usb_lowlevel_stop(void) +{ + struct isp116x *isp116x = &isp116x_dev; + + DEBUG_HOST(""); + + if (!isp116x->disabled) + isp116x_stop(isp116x); + + return 0; +} diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x.h new file mode 100644 index 0000000..26678ba --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ethernat/isp116x.h @@ -0,0 +1,542 @@ +/* + * Modified for Atari-EtherNat by David Gálvez 2010 + * + * ISP116x register declarations and HCD data structures + * + * Copyright (C) 2007 Rodolfo Giometti + * Copyright (C) 2007 Eurotech S.p.A. + * Copyright (C) 2005 Olav Kongas + * Portions: + * Copyright (C) 2004 Lothar Wassmann + * Copyright (C) 2004 Psion Teklogix + * Copyright (C) 2004 David Brownell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ETHERNAT_ISP116X_H +#define _ETHERNAT_ISP116X_H + + +#define ERR(fmt, args...) printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args) +#define WARN(fmt, args...) printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args) +#define INFO(fmt, args...) printf("isp116x: " fmt "\n\r" , ## args) + +/* ------------------------------------------------------------------------- */ + +/* us of 1ms frame */ +#define MAX_LOAD_LIMIT 850 + +/* Full speed: max # of bytes to transfer for a single urb + at a time must be < 1024 && must be multiple of 64. + 832 allows transfering 4kiB within 5 frames. */ +#define MAX_TRANSFER_SIZE_FULLSPEED 832 + +/* Low speed: there is no reason to schedule in very big + chunks; often the requested long transfers are for + string descriptors containing short strings. */ +#define MAX_TRANSFER_SIZE_LOWSPEED 64 + +/* Bytetime (us), a rough indication of how much time it + would take to transfer a byte of useful data over USB */ +#define BYTE_TIME_FULLSPEED 1 +#define BYTE_TIME_LOWSPEED 20 + +/* Buffer sizes */ +#define ISP116x_BUF_SIZE 4096 +#define ISP116x_ITL_BUFSIZE 0 +#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE)) + +#define ISP116x_WRITE_OFFSET 0x80 + +/* --- ISP116x address registers in EtherNAT --------------------------------*/ + +#define ISP116X_HCD_ADDR 0x80000016 +#define ISP116X_HCD_DATA 0x80000012 +#define ETHERNAT_CPLD_CR 0x80000023 /* 0x80000023 - 1 */ + +/* --- ISP116x registers/bits ---------------------------------------------- */ + +#define HCREVISION 0x00 +#define HCCONTROL 0x01 +#define HCCONTROL_HCFS (3 << 6) /* host controller + functional state */ +#define HCCONTROL_USB_RESET (0 << 6) +#define HCCONTROL_USB_RESUME (1 << 6) +#define HCCONTROL_USB_OPER (2 << 6) +#define HCCONTROL_USB_SUSPEND (3 << 6) +#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */ +#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */ +#define HCCMDSTAT 0x02 +#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */ +#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */ +#define HCINTSTAT 0x03 +#define HCINT_SO (1 << 0) /* scheduling overrun */ +#define HCINT_WDH (1 << 1) /* writeback of done_head */ +#define HCINT_SF (1 << 2) /* start frame */ +#define HCINT_RD (1 << 3) /* resume detect */ +#define HCINT_UE (1 << 4) /* unrecoverable error */ +#define HCINT_FNO (1 << 5) /* frame number overflow */ +#define HCINT_RHSC (1 << 6) /* root hub status change */ +#define HCINT_OC (1 << 30) /* ownership change */ +#define HCINT_MIE (1 << 31) /* master interrupt enable */ +#define HCINTENB 0x04 +#define HCINTDIS 0x05 +#define HCFMINTVL 0x0d +#define HCFMREM 0x0e +#define HCFMNUM 0x0f +#define HCLSTHRESH 0x11 +#define HCRHDESCA 0x12 +#define RH_A_NDP (0x3 << 0) /* # downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* overcurrent protection + mode */ +#define RH_A_NOCP (1 << 12) /* no overcurrent protection */ +#define RH_A_POTPGT (0xff << 24) /* power on -> power good + time */ +#define HCRHDESCB 0x13 +#define RH_B_DR (0xffff << 0) /* device removable flags */ +#define RH_B_PPCM (0xffff << 16) /* port power control mask */ +#define HCRHSTATUS 0x14 +#define RH_HS_LPS (1 << 0) /* local power status */ +#define RH_HS_OCI (1 << 1) /* over current indicator */ +#define RH_HS_DRWE (1 << 15) /* device remote wakeup + enable */ +#define RH_HS_LPSC (1 << 16) /* local power status change */ +#define RH_HS_OCIC (1 << 17) /* over current indicator + change */ +#define RH_HS_CRWE (1 << 31) /* clear remote wakeup + enable */ +#define HCRHPORT1 0x15 +#define RH_PS_CCS (1 << 0) /* current connect status */ +#define RH_PS_PES (1 << 1) /* port enable status */ +#define RH_PS_PSS (1 << 2) /* port suspend status */ +#define RH_PS_POCI (1 << 3) /* port over current + indicator */ +#define RH_PS_PRS (1 << 4) /* port reset status */ +#define RH_PS_PPS (1 << 8) /* port power status */ +#define RH_PS_LSDA (1 << 9) /* low speed device attached */ +#define RH_PS_CSC (1 << 16) /* connect status change */ +#define RH_PS_PESC (1 << 17) /* port enable status change */ +#define RH_PS_PSSC (1 << 18) /* port suspend status + change */ +#define RH_PS_OCIC (1 << 19) /* over current indicator + change */ +#define RH_PS_PRSC (1 << 20) /* port reset status change */ +#define HCRHPORT_CLRMASK (0x1f << 16) +#define HCRHPORT2 0x16 +#define HCHWCFG 0x20 +#define HCHWCFG_15KRSEL (1 << 12) +#define HCHWCFG_CLKNOTSTOP (1 << 11) +#define HCHWCFG_ANALOG_OC (1 << 10) +#define HCHWCFG_DACK_MODE (1 << 8) +#define HCHWCFG_EOT_POL (1 << 7) +#define HCHWCFG_DACK_POL (1 << 6) +#define HCHWCFG_DREQ_POL (1 << 5) +#define HCHWCFG_DBWIDTH_MASK (0x03 << 3) +#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) +#define HCHWCFG_INT_POL (1 << 2) +#define HCHWCFG_INT_TRIGGER (1 << 1) +#define HCHWCFG_INT_ENABLE (1 << 0) +#define HCDMACFG 0x21 +#define HCDMACFG_BURST_LEN_MASK (0x03 << 5) +#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) +#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) +#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) +#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) +#define HCDMACFG_DMA_ENABLE (1 << 4) +#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) +#define HCDMACFG_CTR_SEL (1 << 2) +#define HCDMACFG_ITLATL_SEL (1 << 1) +#define HCDMACFG_DMA_RW_SELECT (1 << 0) +#define HCXFERCTR 0x22 +#define HCuPINT 0x24 +#define HCuPINT_SOF (1 << 0) +#define HCuPINT_ATL (1 << 1) +#define HCuPINT_AIIEOT (1 << 2) +#define HCuPINT_OPR (1 << 4) +#define HCuPINT_SUSP (1 << 5) +#define HCuPINT_CLKRDY (1 << 6) +#define HCuPINTENB 0x25 +#define HCCHIPID 0x27 +#define HCCHIPID_MASK 0xff00 +#define HCCHIPID_MAGIC 0x6100 +#define HCSCRATCH 0x28 +#define HCSWRES 0x29 +#define HCSWRES_MAGIC 0x00f6 +#define HCITLBUFLEN 0x2a +#define HCATLBUFLEN 0x2b +#define HCBUFSTAT 0x2c +#define HCBUFSTAT_ITL0_FULL (1 << 0) +#define HCBUFSTAT_ITL1_FULL (1 << 1) +#define HCBUFSTAT_ATL_FULL (1 << 2) +#define HCBUFSTAT_ITL0_DONE (1 << 3) +#define HCBUFSTAT_ITL1_DONE (1 << 4) +#define HCBUFSTAT_ATL_DONE (1 << 5) +#define HCRDITL0LEN 0x2d +#define HCRDITL1LEN 0x2e +#define HCITLPORT 0x40 +#define HCATLPORT 0x41 + +/* PTD accessor macros. */ +#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) +#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) +#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) +#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) +#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) +#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) +#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) +#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) +#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) +#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) +#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) +#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) +#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) +#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) +#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) +#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) +#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) +#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) +#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) +#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) +#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13) +#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK) +#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) +#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) +#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7) +#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK) + +/* Hardware transfer status codes -- CC from ptd->count */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 + /* 0x0A, 0x0B reserved for hardware */ +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D + /* 0x0E, 0x0F reserved for HCD */ +#define TD_NOTACCESSED 0x0F + +/* ------------------------------------------------------------------------- */ + +#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ +#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) + +/* Philips transfer descriptor */ +struct ptd { + u16 count; +#define PTD_COUNT_MSK (0x3ff << 0) +#define PTD_TOGGLE_MSK (1 << 10) +#define PTD_ACTIVE_MSK (1 << 11) +#define PTD_CC_MSK (0xf << 12) + u16 mps; +#define PTD_MPS_MSK (0x3ff << 0) +#define PTD_SPD_MSK (1 << 10) +#define PTD_LAST_MSK (1 << 11) +#define PTD_EP_MSK (0xf << 12) + u16 len; +#define PTD_LEN_MSK (0x3ff << 0) +#define PTD_DIR_MSK (3 << 10) +#define PTD_DIR_SETUP (0) +#define PTD_DIR_OUT (1) +#define PTD_DIR_IN (2) +#define PTD_B5_5_MSK (1 << 13) + u16 faddr; +#define PTD_FA_MSK (0x7f << 0) +#define PTD_FMT_MSK (1 << 7) +} __attribute__ ((packed, aligned(2))); + +struct isp116x_ep { + struct usb_device *udev; + struct ptd ptd; + + u8 maxpacket; + u8 epnum; + u8 nextpid; + + u16 length; /* of current packet */ + unsigned char *data; /* to databuf */ + + u16 error_count; +}; + +/* URB struct */ +#define N_URB_TD 48 +#define URB_DEL 1 +typedef struct { + struct isp116x_ep *ed; + void *transfer_buffer; /* (in) associated data buffer */ + int actual_length; /* (return) actual transfer length */ + unsigned long pipe; /* (in) pipe information */ +#if 0 + int state; +#endif +} urb_priv_t; + +struct isp116x_platform_data { + /* Enable internal resistors on downstream ports */ + unsigned sel15Kres:1; + /* On-chip overcurrent detection */ + unsigned oc_enable:1; + /* Enable wakeup by devices on usb bus (e.g. wakeup + by attachment/detachment or by device activity + such as moving a mouse). When chosen, this option + prevents stopping internal clock, increasing + thereby power consumption in suspended state. */ + unsigned remote_wakeup_enable:1; +}; + +struct isp116x { + u16 *addr_reg; + u16 *data_reg; + + struct isp116x_platform_data *board; + + struct dentry *dentry; + unsigned long stat1, stat2, stat4, stat8, stat16; + + /* Status flags */ + unsigned disabled:1; + unsigned sleeping:1; + + /* Root hub registers */ + u32 rhdesca; + u32 rhdescb; + u32 rhstatus; + u32 rhport[2]; + + /* Schedule for the current frame */ + struct isp116x_ep *atl_active; + int atl_buflen; + int atl_bufshrt; + int atl_last_dir; + int atl_finishing; +}; + +/* ------------------------------------------------- */ + +/* Inter-io delay (ns). The chip is picky about access timings; it + * expects at least: + * 150ns delay between consecutive accesses to DATA_REG, + * 300ns delay between access to ADDR_REG and DATA_REG + * OE, WE MUST NOT be changed during these intervals + */ +#if defined(UDELAY) +#define isp116x_delay(h,d) udelay(d) +#else +#define isp116x_delay(h,d) do {} while (0) +#endif + +#include "../../super.h" /* + * Functions to call supervisor mode + * Super() in TOS is buggy + */ + +u32 p; + +static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg) +{ +// p = SuperFromUser( ); + __raw_writew(reg & 0xff, isp116x->addr_reg ); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} + +static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val) +{ +// p = SuperFromUser( ); + writew(val, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} + +static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val) +{ +// p = SuperFromUser( ); + __raw_writew(val, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} + +static inline u16 isp116x_read_data16(struct isp116x *isp116x) +{ + u16 val; +// p = SuperFromUser( ); + val = readw(isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); + return val; +} + +static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x) +{ + u16 val; +// p = SuperFromUser( ); + val = __raw_readw(isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); + return val; +} + + +static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val) +{ +// p = SuperFromUser( ); + writew(val & 0xffff, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + writew(val >> 16, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} + +/* + * Added for EtherNat, to write HC registers without swaping them + * EtherNat already swap them by hardware (i suppose.....) + */ +static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val) +{ +// p = SuperFromUser( ); + __raw_writew(val & 0xffff, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + __raw_writew(val >> 16, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} +/***********************************************/ + +static inline u32 isp116x_read_data32(struct isp116x *isp116x) +{ + u32 val; +// p = SuperFromUser( ); + val = (u32) readw(isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + val |= ((u32) readw(isp116x->data_reg)) << 16; + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); + return val; +} + +/* + * Added for EtherNat, to read HC registers without swaping them + * EtherNat already swap them by hardware (i suppose.....) + */ +static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x) +{ + u32 val; +// p = SuperFromUser( ); + val = (u32) __raw_readw(isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + val |= ((u32) __raw_readw(isp116x->data_reg)) << 16; + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); + return val; +} +/*******************************************************************/ + +/* Let's keep register access functions out of line. Hint: + we wait at least 150 ns at every access. +*/ + +/* with EtherNat use raw_read to avoid swaping bytes*/ + +static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg) +{ + isp116x_write_addr(isp116x, reg); + return isp116x_raw_read_data16(isp116x); +} + +static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg) +{ + isp116x_write_addr(isp116x, reg); + return isp116x_raw_read_data32(isp116x); +} + +static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg, + unsigned val) +{ + isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); + isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff)); +} + +/* with Etehrnat used raw_write to avoid swaping bytes by software */ +static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg, + unsigned val) +{ + isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); + isp116x_raw_write_data32(isp116x, (u32) val); +} + +/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + +#endif /* _ETHERNAT_ISP116X_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c new file mode 100644 index 0000000..c26e6e1 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c @@ -0,0 +1,1561 @@ +/* + * Modified for Atari-NetUSBee by David Gálvez 2010 + * + * ISP116x HCD (Host Controller Driver) for u-boot. + * + * Copyright (C) 2006-2007 Rodolfo Giometti + * Copyright (C) 2006-2007 Eurotech S.p.A. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c" + * (original copyright message follows): + * + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This code is based on linux driver for sl811hs chip, source at + * drivers/usb/host/sl811.c: + * + * SL811 Host Controller Interface driver for USB. + * + * Copyright (c) 2003/06, Courage Co., Ltd. + * + * Based on: + * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, + * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, + * Adam Richter, Gregory P. Smith; + * 2.Original SL811 driver (hc_sl811.o) by Pei Liu + * 3.Rewrited as sl811.o by Yin Aihua + * + * [[GNU/GPL disclaimer]] + * + * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c" + * (original copyright message follows): + * + * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * [[GNU/GPL disclaimer]] + * + * Note: Part of this code has been derived from linux + */ + +#include "../../config.h" +#include "../../asm-m68k/io.h" +#include "../../usb.h" +#include "../../debug.h" + +void udelay (unsigned long usec); + +//extern void boot_printf (const char *fmt, ...); + + +/* + * ISP116x chips require certain delays between accesses to its + * registers. The following timing options exist. + * + * 1. Configure your memory controller (the best) + * 2. Use ndelay (easiest, poorest). For that, enable the following macro. + * + * Value is in microseconds. + */ +#ifdef ISP116X_HCD_USE_UDELAY +#define UDELAY 1 +#endif + +/* + * On some (slowly?) machines an extra delay after data packing into + * controller's FIFOs is required, * otherwise you may get the following + * error: + * + * uboot> usb start + * (Re)start USB... + * USB: scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT + * isp116x: isp116x_submit_job: ****** FIFO not ready! ****** + * + * USB device not responding, giving up (status=4) + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * isp116x: isp116x_submit_job: ****** FIFO not empty! ****** + * 3 USB Device(s) found + * scanning bus for storage devices... 0 Storage Device(s) found + * + * Value is in milliseconds. + */ +#ifdef ISP116X_HCD_USE_EXTRA_DELAY +#define EXTRA_DELAY 50 +#endif + +/* + * Enable the following defines if you wish enable extra debugging messages. + * Normal debug messages controlled from config.h. + */ + +//#define TRACE /* enable tracing code */ +//#define VERBOSE /* verbose debugging messages */ + +#include "isp116x.h" + +#define DRIVER_VERSION "08 Jan 2007" +static const char hcd_name[] = "isp116x-hcd"; + +struct isp116x isp116x_dev; +struct isp116x_platform_data isp116x_board; +static int got_rhsc; /* root hub status change */ +struct usb_device *devgone; /* device which was disconnected */ +static int rh_devnum; /* address of Root Hub endpoint */ + +/* ------------------------------------------------------------------------- */ + +#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL)) +#define min1_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) + +/*Galvez: added to avoid shadow warnings */ +#define min2_t(type,x,y) \ + ({ type __a = (x); type __b = (y); __a < __b ? __a : __b; }) + +/* ------------------------------------------------------------------------- */ + + +static int isp116x_reset(struct isp116x *isp116x); + +/* --- Debugging functions ------------------------------------------------- */ + +#define isp116x_show_reg(d, r) { \ + if ((r) < 0x20) { \ + DEBUG_HOST("%-12s[%02x]: %08x", #r, \ + r, isp116x_read_reg32(d, r)); \ + } else { \ + DEBUG_HOST("%-12s[%02x]: %04x", #r, \ + r, isp116x_read_reg16(d, r)); \ + } \ +} + +#define isp116x_show_regs(d) { \ + isp116x_show_reg(d, HCREVISION); \ + isp116x_show_reg(d, HCCONTROL); \ + isp116x_show_reg(d, HCCMDSTAT); \ + isp116x_show_reg(d, HCINTSTAT); \ + isp116x_show_reg(d, HCINTENB); \ + isp116x_show_reg(d, HCFMINTVL); \ + isp116x_show_reg(d, HCFMREM); \ + isp116x_show_reg(d, HCFMNUM); \ + isp116x_show_reg(d, HCLSTHRESH); \ + isp116x_show_reg(d, HCRHDESCA); \ + isp116x_show_reg(d, HCRHDESCB); \ + isp116x_show_reg(d, HCRHSTATUS); \ + isp116x_show_reg(d, HCRHPORT1); \ + isp116x_show_reg(d, HCRHPORT2); \ + isp116x_show_reg(d, HCHWCFG); \ + isp116x_show_reg(d, HCDMACFG); \ + isp116x_show_reg(d, HCXFERCTR); \ + isp116x_show_reg(d, HCuPINT); \ + isp116x_show_reg(d, HCuPINTENB); \ + isp116x_show_reg(d, HCCHIPID); \ + isp116x_show_reg(d, HCSCRATCH); \ + isp116x_show_reg(d, HCITLBUFLEN); \ + isp116x_show_reg(d, HCATLBUFLEN); \ + isp116x_show_reg(d, HCBUFSTAT); \ + isp116x_show_reg(d, HCRDITL0LEN); \ + isp116x_show_reg(d, HCRDITL1LEN); \ +} + +#if defined(TRACE) + +static int isp116x_get_current_frame_number(struct usb_device *usb_dev) +{ + struct isp116x *isp116x = &isp116x_dev; + + return isp116x_read_reg32(isp116x, HCFMNUM); +} + +static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, char *str) +{ +#if defined(VERBOSE) + int i; +#endif + DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx", + str, + isp116x_get_current_frame_number(dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe) ? 'O' : 'I', + usb_pipetype(pipe) < 2 ? + (usb_pipeint(pipe) ? + "INTR" : "ISOC") : + (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status); +#if defined(VERBOSE) + debug_init ("usb.log"); + if (len > 0 && buffer) { + debug(__FILE__ ": data(%d):", len); + for (i = 0; i < 16 && i < len; i++) + debug(" %02x", ((__u8 *) buffer)[i]); + debug("%s\r\n", i < len ? "..." : ""); + } + debug_exit ( ); +#endif +} + +#define PTD_DIR_STR(ptd) ({char __c; \ + switch(PTD_GET_DIR(ptd)){ \ + case 0: __c = 's'; break; \ + case 1: __c = 'o'; break; \ + default: __c = 'i'; break; \ + }; __c;}) + +/* + Dump PTD info. The code documents the format + perfectly, right :) +*/ +static inline void dump_ptd(struct ptd *ptd) +{ +#if defined(VERBOSE) + int k; +#endif + + DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x", + PTD_GET_CC(ptd), + PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd), + PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), + PTD_GET_TOGGLE(ptd), + PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd)); +#if defined(VERBOSE) + debug_init ("usb.log"); + debug("isp116x: %s: PTD(byte): ", __FUNCTION__); + for (k = 0; k < sizeof(struct ptd); ++k) { + debug("%02x ", ((u8 *) ptd)[k]); + } + debug("\n\r"); + debug_exit ( ); +#endif +} + +static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type) +{ +#if defined(VERBOSE) + int k; + + debug_init ("usb.log"); + if (type == 0 /* 0ut data */ ) { + debug("isp116x: %s: out data: ", __FUNCTION__); + for (k = 0; k < PTD_GET_LEN(ptd); ++k) { + debug("%02x ", ((u8 *) buf)[k]); + } + debug("\n\r"); + } + if (type == 1 /* 1n data */ ) { + debug("isp116x: %s: in data: ", __FUNCTION__); + for (k = 0; k < PTD_GET_COUNT(ptd); ++k) { + debug("%02x ", ((u8 *) buf)[k]); + } + debug("\n\r"); + } + + debug_exit ( ); + + if (PTD_GET_LAST(ptd)) { + DEBUG_HOST("--- last PTD ---"); + } +#endif +} + +#else + +#define dump_msg(dev, pipe, buffer, len, str) do { } while (0) +#define dump_pkt(dev, pipe, buffer, len, setup, str, small) do {} while (0) + +#define dump_ptd(ptd) do {} while (0) +#define dump_ptd_data(ptd, buf, type) do {} while (0) + +#endif + +/* --- Virtual Root Hub ---------------------------------------------------- */ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x02, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 0x22, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'S', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'P', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '1', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '1', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '6', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'x', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* + * Hub class-specific descriptor is constructed dynamically + */ + +/* --- Virtual root hub management functions ------------------------------- */ + +static int rh_check_port_status(struct isp116x *isp116x) +{ + u32 temp, ndp, i; + int res; + + res = -1; + temp = isp116x_read_reg32(isp116x, HCRHSTATUS); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +/* --- HC management functions --------------------------------------------- */ + +/* Write len bytes to fifo, pad till 32-bit boundary + */ +static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len) +{ + u8 *dp = (u8 *) buf; + u16 *dp2 = (u16 *) buf; + u16 w; + int quot = len % 4; + +/* For NetUSBee, take the raw_write out in write functions, here we don't + * like that NetUSBee swap the bytes for us, so we swap them before we send + * them, then the bytes will arrive to the USB device with the correct positions + */ + if ((unsigned long)dp2 & 1) { + DEBUG_HOST("---not aligned ---"); + /* not aligned */ + for (; len > 1; len -= 2) { + w = *dp++; + w |= *dp++ << 8; + isp116x_write_data16(isp116x, w); + } + if (len) + isp116x_write_data16(isp116x, (u16) * dp); + } else { + DEBUG_HOST("---aligned ---"); + /* aligned */ + for (; len > 1; len -= 2) + isp116x_write_data16(isp116x, *dp2++); + if (len){DEBUG_HOST("write_data16\r\n"); /*GALVEZ: DEBUG */ + isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));} + } + if (quot == 1 || quot == 2) + isp116x_write_data16(isp116x, 0); +} + +/* Read len bytes from fifo and then read till 32-bit boundary + */ +static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len) +{ + u8 *dp = (u8 *) buf; + u16 *dp2 = (u16 *) buf; + u16 w; + int quot = len % 4; + +/* For NetUSBee, take the raw_read out from read functions, we want to swap the bytes + to read correct values because NetUSBee swaped the bytes by hardware before we read + them */ + + if ((unsigned long)dp2 & 1) { + /* not aligned */ + DEBUG_HOST("---not aligned ---"); + for (; len > 1; len -= 2) { + w = isp116x_read_data16(isp116x); + *dp++ = w & 0xff; + *dp++ = (w >> 8) & 0xff; + } + if (len) + *dp = 0xff & isp116x_read_data16(isp116x); + } else { + /* aligned */ + DEBUG_HOST("---aligned ---"); + for (; len > 1; len -= 2) + *dp2++ = isp116x_read_data16(isp116x); + if (len) + *(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x); + } + if (quot == 1 || quot == 2) + isp116x_read_data16(isp116x); +} + +/* Write PTD's and data for scheduled transfers into the fifo ram. + * Fifo must be empty and ready */ +static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev, + unsigned long pipe, struct ptd *ptd, int n, void *data, + int len) +{ + int buflen = n * sizeof(struct ptd) + len; + int i, done; + + DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen); + + isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT); + + isp116x_write_reg16(isp116x, HCXFERCTR, buflen); + isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET); + + done = 0; + for (i = 0; i < n; i++) { + DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i])); + +/* For NetUSBee, use raw_write to don't swap bytes */ + dump_ptd(&ptd[i]); + isp116x_raw_write_data16(isp116x, ptd[i].count); + isp116x_raw_write_data16(isp116x, ptd[i].mps); + isp116x_raw_write_data16(isp116x, ptd[i].len); + isp116x_raw_write_data16(isp116x, ptd[i].faddr); + + dump_ptd_data(&ptd[i], (__u8 *) data + done, 0); + + write_ptddata_to_fifo(isp116x, + (__u8 *) data + done, + PTD_GET_LEN(&ptd[i])); + + done += PTD_GET_LEN(&ptd[i]); + } +} + +/* Read the processed PTD's and data from fifo ram back to URBs' buffers. + * Fifo must be full and done */ +static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev, + unsigned long pipe, struct ptd *ptd, int n, void *data, + int len) +{ + int buflen = n * sizeof(struct ptd) + len; + int i, done, cc, ret; + + isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT); + isp116x_write_reg16(isp116x, HCXFERCTR, buflen); + isp116x_write_addr(isp116x, HCATLPORT); + + ret = TD_CC_NOERROR; + done = 0; + for (i = 0; i < n; i++) { + /* Galvez: DEBUG */ +// DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i])); + DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i])); + /*****************/ + + /* For NetUSBee, use raw_read to don't swap bytes */ + ptd[i].count = isp116x_raw_read_data16(isp116x); + ptd[i].mps = isp116x_raw_read_data16(isp116x); + ptd[i].len = isp116x_raw_read_data16(isp116x); + ptd[i].faddr = isp116x_raw_read_data16(isp116x); + dump_ptd(&ptd[i]); + + /* when cc is 15 the data has not being touch by the HC + * so we have to read all to empty completly the buffer + */ +// if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 ) + read_ptddata_from_fifo(isp116x, + (__u8 *) data + done, + PTD_GET_LEN(&ptd[i])); + dump_ptd_data(&ptd[i], (__u8 *) data + done, 1); + + done += PTD_GET_LEN(&ptd[i]); + + cc = PTD_GET_CC(&ptd[i]); + + /* Data underrun means basically that we had more buffer space than + * the function had data. It is perfectly normal but upper levels have + * to know how much we actually transferred. + */ + if (cc == TD_NOTACCESSED || + (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN))) + ret = cc; + } + + DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd)); + + return ret; +} + +/* Interrupt handling + */ +static int isp116x_interrupt(struct isp116x *isp116x) +{ + u16 irqstat; + u32 intstat; + int ret = 0; + + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + irqstat = isp116x_read_reg16(isp116x, HCuPINT); + isp116x_write_reg16(isp116x, HCuPINT, irqstat); + DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat); + + if (irqstat & HCuPINT_ATL) { + DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<"); + udelay(500); + ret = 1; + } + + if (irqstat & HCuPINT_OPR) { + intstat = isp116x_read_reg32(isp116x, HCINTSTAT); + isp116x_write_reg32(isp116x, HCINTSTAT, intstat); + DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat); + + if (intstat & HCINT_UE) { + ERR("unrecoverable error, controller disabled"); + + /* FIXME: be optimistic, hope that bug won't repeat + * often. Make some non-interrupt context restart the + * controller. Count and limit the retries though; + * either hardware or software errors can go forever... + */ + isp116x_reset(isp116x); + ret = -1; + return -1; + } + + if (intstat & HCINT_RHSC) { + got_rhsc = 1; + ret = 1; + /* When root hub or any of its ports is going + to come out of suspend, it may take more + than 10ms for status bits to stabilize. */ + wait_ms(20); + } + + if (intstat & HCINT_SO) { + ERR("schedule overrun"); + ret = -1; + } + + irqstat &= ~HCuPINT_OPR; + } + + return ret; +} + +/* With one PTD we can transfer almost 1K in one go; + * HC does the splitting into endpoint digestible transactions + */ +struct ptd ptd[1]; + +static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe) +{ + unsigned mpck = usb_maxpacket(dev, pipe); + + /* One PTD can transfer 1023 bytes but try to always + * transfer multiples of endpoint buffer size + */ + return 1023 / mpck * mpck; +} + +/* Do an USB transfer + */ +static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, + int dir, void *buffer, int len) +{ + struct isp116x *isp116x = &isp116x_dev; + int type = usb_pipetype(pipe); + int epnum = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + int dir_out = usb_pipeout(pipe); + int speed_low = usb_pipeslow(pipe); + int i, done = 0, stat, timeout, cc; + + /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */ + int retries = 500; + + + DEBUG_HOST("------------------------------------------------"); + dump_msg(dev, pipe, buffer, len, "SUBMIT"); + DEBUG_HOST("------------------------------------------------"); + + if (len >= 1024) { + ERR("Too big job"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + if (isp116x->disabled) { + ERR("EPIPE"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + ERR("ENODEV"); + dev->status = USB_ST_CRC_ERR; + return USB_ST_CRC_ERR; + } + + if (!max) { + ERR("pipesize for pipe %lx is zero", pipe); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + if (type == PIPE_ISOCHRONOUS) { + ERR("isochronous transfers not supported"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + + /* FIFO not empty? */ + if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) { + DEBUG_HOST("****** FIFO not empty! ******"); + printf("****** FIFO not empty! ******\n\r"); + dev->status = USB_ST_BUF_ERR; + return -1; + } + +retry: + isp116x_write_reg32(isp116x, HCINTSTAT, 0xff); + /* Prepare the PTD data */ + ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK | + PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); + ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK; + ptd->len = PTD_LEN(len) | PTD_DIR(dir); + ptd->faddr = PTD_FA(usb_pipedevice(pipe)); + + +retry_same: + + /* FIFO not empty? */ /* GALVEZ: DEBUG */ + if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) { + DEBUG_HOST("****** FIFO not empty! ******"); + printf("****** FIFO not empty! ******\n\r"); +// dev->status = USB_ST_BUF_ERR; +// return -1; + } + + /* Pack data into FIFO ram */ + pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + +#ifdef EXTRA_DELAY + wait_ms(EXTRA_DELAY); +#endif + + /* Start the data transfer */ + + /* Allow more time for a BULK device to react - some are slow */ + if (usb_pipebulk(pipe)) + timeout = 5000; /* Galvez: default = 5000 */ + else + timeout = 1000; /* Galvez : netusbee : default = 100 */ + + /* Wait for it to complete */ + for (;;) { + /* Check whether the controller is done */ + stat = isp116x_interrupt(isp116x); + + if (stat < 0) { + dev->status = USB_ST_CRC_ERR; + break; + } + if (stat > 0) + break; + + /* Check the timeout */ + if (--timeout) + udelay(1); + else { + ERR("CTL:TIMEOUT "); + printf("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + + /* We got an Root Hub Status Change interrupt */ + if (got_rhsc) { + isp116x_show_regs(isp116x); + + got_rhsc = 0; + + /* Abuse timeout */ + timeout = rh_check_port_status(isp116x); + if (timeout >= 0) { + /* + * FIXME! NOTE! AAAARGH! + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + + /* Ok, now we can read transfer status */ + + /* FIFO not ready? */ + if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) { + DEBUG_HOST("****** FIFO not ready! ******"); + printf("****** FIFO not ready! ******\n\r"); + dev->status = USB_ST_BUF_ERR; + return -1; + } + + + /* Unpack data from FIFO ram */ + cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + + i = PTD_GET_COUNT(ptd); + done += i; + buffer += i; + len -= i; + + + /* There was some kind of real problem; Prepare the PTD again + * and retry from the failed transaction on + */ + if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) { + DEBUG_HOST("PROBLEM cc: %d", cc); + if (retries >= 100) { + retries -= 100; + /* The chip will have toggled the toggle bit for the failed + * transaction too. We have to toggle it back. + */ + usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed + * the transactions from the first on for the whole frame. It may be busy and we retry + * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the + * PTD didn't make it because the function was busy or the frame ended before the PTD + * finished. We prepare the rest of the data and try again. + */ + else if ( cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) { + DEBUG_HOST("NORMAL ERROR"); + if (retries) { + --retries; + if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) { + goto retry_same; + } + usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + + + if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) { + DEBUG_HOST("****** completition code error %x ******", cc); + switch (cc) { + case TD_CC_BITSTUFFING: + dev->status = USB_ST_BIT_ERR; + break; + case TD_CC_STALL: + dev->status = USB_ST_STALLED; + break; + case TD_BUFFEROVERRUN: + case TD_BUFFERUNDERRUN: + dev->status = USB_ST_BUF_ERR; + break; + default: + dev->status = USB_ST_CRC_ERR; + } + return -cc; + } + else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + + dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)"); + + dev->status = 0; + return done; +} + +/* Adapted from au1x00_usb_ohci.c + */ +static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *cmd) +{ + struct isp116x *isp116x = &isp116x_dev; + u32 tmp = 0; + + int leni = transfer_len; + int len = 0; + int stat = 0; + u32 datab[4]; + u8 *data_buf = (u8 *) datab; + u16 bmRType_bReq; + u16 wValue; + u16 wIndex; + u16 wLength; + + if (usb_pipeint(pipe)) { + INFO("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + + DEBUG_HOST("--- HUB ----------------------------------------"); + DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d", + bmRType_bReq, wValue, wIndex, wLength); + dump_msg(dev, pipe, buffer, transfer_len, "RH"); + DEBUG_HOST("------------------------------------------------"); + + switch (bmRType_bReq) { + case RH_GET_STATUS: + DEBUG_HOST("RH_GET_STATUS"); + + *(__u16 *) data_buf = swap_16(1); + len = 2; + break; + + case RH_GET_STATUS | RH_INTERFACE: + DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_ENDPOINT: + DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_CLASS: + DEBUG_HOST("RH_GET_STATUS | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHSTATUS); + + *(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE)); + len = 4; + break; + + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1); + *(__u32 *) data_buf = swap_32(tmp); + isp116x_show_regs(isp116x); + len = 4; + break; + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT"); + + switch (wValue) { + case RH_ENDPOINT_STALL: + DEBUG_HOST("C_HUB_ENDPOINT_STALL"); + len = 0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS"); + + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + DEBUG_HOST("C_HUB_LOCAL_POWER"); + len = 0; + break; + + case RH_C_HUB_OVER_CURRENT: + DEBUG_HOST("C_HUB_OVER_CURRENT"); + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC); + len = 0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS"); + + switch (wValue) { + case RH_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_CCS); + len = 0; + break; + + case RH_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_POCI); + len = 0; + break; + + case RH_PORT_POWER: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_LSDA); + len = 0; + break; + + case RH_C_PORT_CONNECTION: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_CSC); + len = 0; + break; + + case RH_C_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PESC); + len = 0; + break; + + case RH_C_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PSSC); + len = 0; + break; + + case RH_C_PORT_OVER_CURRENT: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_POCI); + len = 0; + break; + + case RH_C_PORT_RESET: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PRSC); + len = 0; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + isp116x_show_regs(isp116x); + + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS"); + + switch (wValue) { + case RH_PORT_SUSPEND: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PSS); + len = 0; + break; + + case RH_PORT_RESET: + /* Spin until any current reset finishes */ + while (1) { + tmp = + isp116x_read_reg32(isp116x, + HCRHPORT1 + wIndex - 1); + if (!(tmp & RH_PS_PRS)) + break; + wait_ms(1); + } + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PRS); + wait_ms(10); + + len = 0; + break; + + case RH_PORT_POWER: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PPS); + len = 0; + break; + + case RH_PORT_ENABLE: + isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, + RH_PS_PES); + len = 0; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + isp116x_show_regs(isp116x); + + break; + + case RH_SET_ADDRESS: + DEBUG_HOST("RH_SET_ADDRESS"); + + rh_devnum = wValue; + len = 0; + break; + + case RH_GET_DESCRIPTOR: + DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength); + + switch (wValue) { + case (USB_DT_DEVICE << 8): /* device descriptor */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; + break; + + case (USB_DT_CONFIG << 8): /* configuration descriptor */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; + break; + + case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + break; + + case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */ + len = min1_t(unsigned int, + leni, min2_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + break; + + default: + ERR("invalid wValue"); + stat = USB_ST_STALLED; + } + + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS"); + + tmp = isp116x_read_reg32(isp116x, HCRHDESCA); + + data_buf[0] = 0x09; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = tmp & RH_A_NDP; + data_buf[3] = 0; + if (tmp & RH_A_PSM) /* per-port power switching? */ + data_buf[3] |= 0x01; + if (tmp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf[3] |= 0x10; + else if (tmp & RH_A_OCPM) /* per-port overcurrent rep? */ + data_buf[3] |= 0x08; + + /* Corresponds to data_buf[4-7] */ + datab[1] = 0; + data_buf[5] = (tmp & RH_A_POTPGT) >> 24; + + tmp = isp116x_read_reg32(isp116x, HCRHDESCB); + + data_buf[7] = tmp & RH_B_DR; + if (data_buf[2] < 7) + data_buf[8] = 0xff; + else { + data_buf[0] += 2; + data_buf[8] = (tmp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + + len = min1_t(unsigned int, leni, + min2_t(unsigned int, data_buf[0], wLength)); + break; + + case RH_GET_CONFIGURATION: + DEBUG_HOST("RH_GET_CONFIGURATION"); + + *(__u8 *) data_buf = 0x01; + len = 1; + break; + + case RH_SET_CONFIGURATION: + DEBUG_HOST("RH_SET_CONFIGURATION"); + + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC); + len = 0; + break; + + default: + ERR("*** *** *** unsupported root hub command *** *** ***"); + stat = USB_ST_STALLED; + } + + len = min1_t(int, len, leni); + if (buffer != data_buf) + memcpy(buffer, data_buf, len); + + dev->act_len = len; + dev->status = stat; + DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status); + + dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)"); + + return stat; +} + +/* --- Transfer functions -------------------------------------------------- */ + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d", + dev, pipe, buffer, len, interval); + + return -1; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + int epnum = usb_pipeendpoint(pipe); + int max = max_transfer_len(dev, pipe); + int dir_in = usb_pipein(pipe); + int done, ret; + + + /* Control message is for the HUB? */ + if (devnum == rh_devnum) + return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup); + + /* Ok, no HUB message so send the message to the device */ + + /* Setup phase */ + DEBUG_HOST("--- SETUP PHASE --------------------------------"); + usb_settoggle(dev, epnum, 1, 0); + + + ret = isp116x_submit_job(dev, pipe, + PTD_DIR_SETUP, + setup, sizeof(struct devrequest)); + if (ret < 0) { + DEBUG_HOST("control setup phase error (ret = %d", ret); + return -1; + } + + /* Data phase */ + DEBUG_HOST("--- DATA PHASE ---------------------------------"); + done = 0; + usb_settoggle(dev, epnum, !dir_in, 1); + while (done < len) { + ret = isp116x_submit_job(dev, pipe, + dir_in ? PTD_DIR_IN : PTD_DIR_OUT, + (__u8 *) buffer + done, + max > len - done ? len - done : max); + if (ret < 0) { + DEBUG_HOST("control data phase error (ret = %d)", ret); + return -1; + } + done += ret; + + if (dir_in && ret < max) /* short packet */ + break; + } + + /* Status phase */ + DEBUG_HOST("--- STATUS PHASE -------------------------------"); + usb_settoggle(dev, epnum, !dir_in, 1); + ret = isp116x_submit_job(dev, pipe, + !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0); + if (ret < 0) { + DEBUG_HOST("control status phase error (ret = %d", ret); + return -1; + } + + dev->act_len = done; + + dump_msg(dev, pipe, buffer, len, "DEV(ret)"); + + return done; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int dir_out = usb_pipeout(pipe); + int max = max_transfer_len(dev, pipe); + int done, ret; + + DEBUG_HOST("--- BULK ---------------------------------------"); + DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d", + usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); + + done = 0; + while (done < len) { + + ret = isp116x_submit_job(dev, pipe, + !dir_out ? PTD_DIR_IN : PTD_DIR_OUT, + (__u8 *) buffer + done, + max > len - done ? len - done : max); + + if (ret < 0) { + DEBUG_HOST("error on bulk message (ret = %d)", ret); + return -1; + } + + done += ret; + + if (!dir_out && ret < max) /* short packet */ + break; + } + + dev->act_len = done; + + return 0; +} + +/* --- Basic functions ----------------------------------------------------- */ + + +#if 0 +/* GALVEZ: Test function */ +static int GALVEZ_test_function( struct isp116x *isp116x ) +{ + short res; + + isp116x_write_reg16(isp116x, HCSCRATCH, 0x1234); + res = isp116x_read_reg16(isp116x, HCSCRATCH); + ERR ("Scratch register read: %x\r\n",res); + return 0; + +} +#endif + +static int isp116x_sw_reset(struct isp116x *isp116x) +{ + int retries = 15; + int ret = 0; + + DEBUG_HOST(""); + + isp116x->disabled = 1; + + isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC); + isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR); + + while (--retries) { + /* It usually resets within 1 ms */ + /* GALVEZ: not enough for TOS, try 7 ms */ + wait_ms(7); + if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) + break; + } + + if (!retries) { + ERR("software reset timeout"); + ret = -1; + } + +#if 0 + /* GALVEZ: DEBUG SOFTWARE RESET */ + + retries = 5000; + + while (--retries){ + if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) { + INFO ("HCR: 1 retries: %d\n\r",retries); + } + } +#endif /* END DEBUG */ + + return ret; +} + +static int isp116x_reset(struct isp116x *isp116x) +{ + unsigned long t; + u16 clkrdy = 0; + int ret, timeout = 1000;/* ms + * Galvez: 15 ms sometimes isn't enough, + * for NetUSBee under TOS ??????? increased to 150 ms + */ + + DEBUG_HOST(""); + + ret = isp116x_sw_reset(isp116x); + + if (ret) + return ret; + + for (t = 0; t < timeout; t++) { + clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY; + if (clkrdy) + break; + wait_ms(1); + } + if (!clkrdy) { + ERR("clock not ready after %dms", timeout); + /* After sw_reset the clock won't report to be ready, if + H_WAKEUP pin is high. */ + ERR("please make sure that the H_WAKEUP pin is pulled low!"); + ret = -1; + } + return ret; +} + +static void isp116x_stop(struct isp116x *isp116x) +{ + u32 val; + + DEBUG_HOST(""); + + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + + /* Switch off ports' power, some devices don't come up + after next 'start' without this */ + val = isp116x_read_reg32(isp116x, HCRHDESCA); + val &= ~(RH_A_NPS | RH_A_PSM); + isp116x_write_reg32(isp116x, HCRHDESCA, val); + isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS); + + isp116x_sw_reset(isp116x); +} + +/* + * Configure the chip. The chip must be successfully reset by now. + */ +static int isp116x_start(struct isp116x *isp116x) +{ + struct isp116x_platform_data *board = isp116x->board; + u32 val; + + DEBUG_HOST(""); + + /* Clear interrupt status and disable all interrupt sources */ + isp116x_write_reg16(isp116x, HCuPINT, 0xff); + isp116x_write_reg16(isp116x, HCuPINTENB, 0); + + isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE); + isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE); + + /* Hardware configuration */ + val = HCHWCFG_DBWIDTH(1); + + if (board->sel15Kres) + val |= HCHWCFG_15KRSEL; + /* Remote wakeup won't work without working clock */ + if (board->remote_wakeup_enable) + val |= HCHWCFG_CLKNOTSTOP; + if (board->oc_enable) + val |= HCHWCFG_ANALOG_OC; + isp116x_write_reg16(isp116x, HCHWCFG, val); + + + /* --- Root hub configuration */ + val = (25 << 24) & RH_A_POTPGT; + /* AN10003_1.pdf recommends RH_A_NPS (no power switching) to + be always set. Yet, instead, we request individual port + power switching. */ + val |= RH_A_PSM; + /* Report overcurrent per port */ + val |= RH_A_OCPM; + isp116x_write_reg32(isp116x, HCRHDESCA, val); + isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA); + + val = RH_B_PPCM; + isp116x_write_reg32(isp116x, HCRHDESCB, val); + isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB); + + val = 0; + if (board->remote_wakeup_enable) + val |= RH_HS_DRWE; + isp116x_write_reg32(isp116x, HCRHSTATUS, val); + isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS); + + isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf); + + /* Go operational */ + val = HCCONTROL_USB_OPER; + if (board->remote_wakeup_enable) + val |= HCCONTROL_RWE; + isp116x_write_reg32(isp116x, HCCONTROL, val); + + /* Disable ports to avoid race in device enumeration */ + isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS); + isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS); + + isp116x_show_regs(isp116x); + + isp116x->disabled = 0; + + return 0; +} + +/* --- Init functions ------------------------------------------------------ */ + + + +int isp116x_check_id(struct isp116x *isp116x) +{ + u16 val; + + val = isp116x_read_reg16(isp116x, HCCHIPID); + DEBUG_HOST("chip ID: %04x", val); + printf ("chip ID: %04x", val); + + if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) { + printf("invalid chip ID %04x", val); + return -1; + } + + return 0; +} + + +int usb_lowlevel_init(void) +{ +// u16 val; + + struct isp116x *isp116x = &isp116x_dev; + + DEBUG_HOST(""); + + got_rhsc = rh_devnum = 0; + + /* Init device registers addr */ + isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR_BEE; + isp116x->data_reg = (u16 *) ISP116X_HCD_DATA_BEE; + + /* Setup specific board settings */ +#ifdef ISP116X_HCD_SEL15kRES + isp116x_board.sel15Kres = 1; +#endif +#ifdef ISP116X_HCD_OC_ENABLE + isp116x_board.oc_enable = 1; +#endif +#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE + isp116x_board.remote_wakeup_enable = 1; +#endif + isp116x->board = &isp116x_board; + + /* Try to get ISP116x silicon chip ID */ + if ( isp116x_check_id(isp116x) < 0) + return -1; + + +// GALVEZ_test_function ( isp116x ); /* Gálvez: Testing writing to registers */ + + isp116x->disabled = 1; + isp116x->sleeping = 0; + + isp116x_reset(isp116x); + isp116x_start(isp116x); + + return 0; +} + +int usb_lowlevel_stop(void) +{ + struct isp116x *isp116x = &isp116x_dev; + + DEBUG_HOST(""); + + if (!isp116x->disabled) + isp116x_stop(isp116x); + + return 0; +} diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x.h new file mode 100644 index 0000000..7d62865 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/netusbee/isp116x.h @@ -0,0 +1,596 @@ +/* + * Modified for Atari-NetUSBee by David Gálvez 2010 + * + * ISP116x register declarations and HCD data structures + * + * Copyright (C) 2007 Rodolfo Giometti + * Copyright (C) 2007 Eurotech S.p.A. + * Copyright (C) 2005 Olav Kongas + * Portions: + * Copyright (C) 2004 Lothar Wassmann + * Copyright (C) 2004 Psion Teklogix + * Copyright (C) 2004 David Brownell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NETUSBEE_ISP116X_H +#define _NETUSBEE_ISP116X_H + + +#define ERR(fmt, args...) printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args) +#define WARN(fmt, args...) printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args) +#define INFO(fmt, args...) printf("isp116x: " fmt "\n\r" , ## args) + +/* ------------------------------------------------------------------------- */ + +/* us of 1ms frame */ +#define MAX_LOAD_LIMIT 850 + +/* Full speed: max # of bytes to transfer for a single urb + at a time must be < 1024 && must be multiple of 64. + 832 allows transfering 4kiB within 5 frames. */ +#define MAX_TRANSFER_SIZE_FULLSPEED 832 + +/* Low speed: there is no reason to schedule in very big + chunks; often the requested long transfers are for + string descriptors containing short strings. */ +#define MAX_TRANSFER_SIZE_LOWSPEED 64 + +/* Bytetime (us), a rough indication of how much time it + would take to transfer a byte of useful data over USB */ +#define BYTE_TIME_FULLSPEED 1 +#define BYTE_TIME_LOWSPEED 20 + +/* Buffer sizes */ +#define ISP116x_BUF_SIZE 4096 +#define ISP116x_ITL_BUFSIZE 0 +#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE)) + +#define ISP116x_WRITE_OFFSET 0x80 + + +/* --- ISP116x address registers in Netusbee --------------------------------*/ + +#define ISP116X_HCD_ADDR_BEE 0x00FBC000 +#define ISP116X_HCD_DATA_BEE 0x00FA0000 + + +/* --- ISP116x registers/bits ---------------------------------------------- */ + +#define HCREVISION 0x00 +#define HCCONTROL 0x01 +#define HCCONTROL_HCFS (3 << 6) /* host controller + functional state */ +#define HCCONTROL_USB_RESET (0 << 6) +#define HCCONTROL_USB_RESUME (1 << 6) +#define HCCONTROL_USB_OPER (2 << 6) +#define HCCONTROL_USB_SUSPEND (3 << 6) +#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */ +#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */ +#define HCCMDSTAT 0x02 +#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */ +#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */ +#define HCINTSTAT 0x03 +#define HCINT_SO (1 << 0) /* scheduling overrun */ +#define HCINT_WDH (1 << 1) /* writeback of done_head */ +#define HCINT_SF (1 << 2) /* start frame */ +#define HCINT_RD (1 << 3) /* resume detect */ +#define HCINT_UE (1 << 4) /* unrecoverable error */ +#define HCINT_FNO (1 << 5) /* frame number overflow */ +#define HCINT_RHSC (1 << 6) /* root hub status change */ +#define HCINT_OC (1 << 30) /* ownership change */ +#define HCINT_MIE (1 << 31) /* master interrupt enable */ +#define HCINTENB 0x04 +#define HCINTDIS 0x05 +#define HCFMINTVL 0x0d +#define HCFMREM 0x0e +#define HCFMNUM 0x0f +#define HCLSTHRESH 0x11 +#define HCRHDESCA 0x12 +#define RH_A_NDP (0x3 << 0) /* # downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* overcurrent protection + mode */ +#define RH_A_NOCP (1 << 12) /* no overcurrent protection */ +#define RH_A_POTPGT (0xff << 24) /* power on -> power good + time */ +#define HCRHDESCB 0x13 +#define RH_B_DR (0xffff << 0) /* device removable flags */ +#define RH_B_PPCM (0xffff << 16) /* port power control mask */ +#define HCRHSTATUS 0x14 +#define RH_HS_LPS (1 << 0) /* local power status */ +#define RH_HS_OCI (1 << 1) /* over current indicator */ +#define RH_HS_DRWE (1 << 15) /* device remote wakeup + enable */ +#define RH_HS_LPSC (1 << 16) /* local power status change */ +#define RH_HS_OCIC (1 << 17) /* over current indicator + change */ +#define RH_HS_CRWE (1 << 31) /* clear remote wakeup + enable */ +#define HCRHPORT1 0x15 +#define RH_PS_CCS (1 << 0) /* current connect status */ +#define RH_PS_PES (1 << 1) /* port enable status */ +#define RH_PS_PSS (1 << 2) /* port suspend status */ +#define RH_PS_POCI (1 << 3) /* port over current + indicator */ +#define RH_PS_PRS (1 << 4) /* port reset status */ +#define RH_PS_PPS (1 << 8) /* port power status */ +#define RH_PS_LSDA (1 << 9) /* low speed device attached */ +#define RH_PS_CSC (1 << 16) /* connect status change */ +#define RH_PS_PESC (1 << 17) /* port enable status change */ +#define RH_PS_PSSC (1 << 18) /* port suspend status + change */ +#define RH_PS_OCIC (1 << 19) /* over current indicator + change */ +#define RH_PS_PRSC (1 << 20) /* port reset status change */ +#define HCRHPORT_CLRMASK (0x1f << 16) +#define HCRHPORT2 0x16 +#define HCHWCFG 0x20 +#define HCHWCFG_15KRSEL (1 << 12) +#define HCHWCFG_CLKNOTSTOP (1 << 11) +#define HCHWCFG_ANALOG_OC (1 << 10) +#define HCHWCFG_DACK_MODE (1 << 8) +#define HCHWCFG_EOT_POL (1 << 7) +#define HCHWCFG_DACK_POL (1 << 6) +#define HCHWCFG_DREQ_POL (1 << 5) +#define HCHWCFG_DBWIDTH_MASK (0x03 << 3) +#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) +#define HCHWCFG_INT_POL (1 << 2) +#define HCHWCFG_INT_TRIGGER (1 << 1) +#define HCHWCFG_INT_ENABLE (1 << 0) +#define HCDMACFG 0x21 +#define HCDMACFG_BURST_LEN_MASK (0x03 << 5) +#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) +#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) +#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) +#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) +#define HCDMACFG_DMA_ENABLE (1 << 4) +#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) +#define HCDMACFG_CTR_SEL (1 << 2) +#define HCDMACFG_ITLATL_SEL (1 << 1) +#define HCDMACFG_DMA_RW_SELECT (1 << 0) +#define HCXFERCTR 0x22 +#define HCuPINT 0x24 +#define HCuPINT_SOF (1 << 0) +#define HCuPINT_ATL (1 << 1) +#define HCuPINT_AIIEOT (1 << 2) +#define HCuPINT_OPR (1 << 4) +#define HCuPINT_SUSP (1 << 5) +#define HCuPINT_CLKRDY (1 << 6) +#define HCuPINTENB 0x25 +#define HCCHIPID 0x27 +#define HCCHIPID_MASK 0xff00 +#define HCCHIPID_MAGIC 0x6100 +#define HCSCRATCH 0x28 +#define HCSWRES 0x29 +#define HCSWRES_MAGIC 0x00f6 +#define HCITLBUFLEN 0x2a +#define HCATLBUFLEN 0x2b +#define HCBUFSTAT 0x2c +#define HCBUFSTAT_ITL0_FULL (1 << 0) +#define HCBUFSTAT_ITL1_FULL (1 << 1) +#define HCBUFSTAT_ATL_FULL (1 << 2) +#define HCBUFSTAT_ITL0_DONE (1 << 3) +#define HCBUFSTAT_ITL1_DONE (1 << 4) +#define HCBUFSTAT_ATL_DONE (1 << 5) +#define HCRDITL0LEN 0x2d +#define HCRDITL1LEN 0x2e +#define HCITLPORT 0x40 +#define HCATLPORT 0x41 + +/* PTD accessor macros. */ +#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) +#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) +#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) +#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) +#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) +#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) +#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) +#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) +#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) +#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) +#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) +#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) +#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) +#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) +#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) +#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) +#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) +#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) +#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) +#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) +#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13) +#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK) +#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) +#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) +#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7) +#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK) + +/* Hardware transfer status codes -- CC from ptd->count */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 + /* 0x0A, 0x0B reserved for hardware */ +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D + /* 0x0E, 0x0F reserved for HCD */ +#define TD_NOTACCESSED 0x0F + +/* ------------------------------------------------------------------------- */ + +#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ +#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) + +/* Philips transfer descriptor */ +struct ptd { + u16 count; +#define PTD_COUNT_MSK (0x3ff << 0) +#define PTD_TOGGLE_MSK (1 << 10) +#define PTD_ACTIVE_MSK (1 << 11) +#define PTD_CC_MSK (0xf << 12) + u16 mps; +#define PTD_MPS_MSK (0x3ff << 0) +#define PTD_SPD_MSK (1 << 10) +#define PTD_LAST_MSK (1 << 11) +#define PTD_EP_MSK (0xf << 12) + u16 len; +#define PTD_LEN_MSK (0x3ff << 0) +#define PTD_DIR_MSK (3 << 10) +#define PTD_DIR_SETUP (0) +#define PTD_DIR_OUT (1) +#define PTD_DIR_IN (2) +#define PTD_B5_5_MSK (1 << 13) + u16 faddr; +#define PTD_FA_MSK (0x7f << 0) +#define PTD_FMT_MSK (1 << 7) +} __attribute__ ((packed, aligned(2))); + +struct isp116x_ep { + struct usb_device *udev; + struct ptd ptd; + + u8 maxpacket; + u8 epnum; + u8 nextpid; + + u16 length; /* of current packet */ + unsigned char *data; /* to databuf */ + + u16 error_count; +}; + +/* URB struct */ +#define N_URB_TD 48 +#define URB_DEL 1 +typedef struct { + struct isp116x_ep *ed; + void *transfer_buffer; /* (in) associated data buffer */ + int actual_length; /* (return) actual transfer length */ + unsigned long pipe; /* (in) pipe information */ +#if 0 + int state; +#endif +} urb_priv_t; + +struct isp116x_platform_data { + /* Enable internal resistors on downstream ports */ + unsigned sel15Kres:1; + /* On-chip overcurrent detection */ + unsigned oc_enable:1; + /* Enable wakeup by devices on usb bus (e.g. wakeup + by attachment/detachment or by device activity + such as moving a mouse). When chosen, this option + prevents stopping internal clock, increasing + thereby power consumption in suspended state. */ + unsigned remote_wakeup_enable:1; +}; + +struct isp116x { + u16 *addr_reg; + u16 *data_reg; + + struct isp116x_platform_data *board; + + struct dentry *dentry; + unsigned long stat1, stat2, stat4, stat8, stat16; + + /* Status flags */ + unsigned disabled:1; + unsigned sleeping:1; + + /* Root hub registers */ + u32 rhdesca; + u32 rhdescb; + u32 rhstatus; + u32 rhport[2]; + + /* Schedule for the current frame */ + struct isp116x_ep *atl_active; + int atl_buflen; + int atl_bufshrt; + int atl_last_dir; + int atl_finishing; +}; + +/* ------------------------------------------------- */ + +/* Inter-io delay (ns). The chip is picky about access timings; it + * expects at least: + * 150ns delay between consecutive accesses to DATA_REG, + * 300ns delay between access to ADDR_REG and DATA_REG + * OE, WE MUST NOT be changed during these intervals + */ +#if defined(UDELAY) +#define isp116x_delay(h,d) udelay(d) +#else +#define isp116x_delay(h,d) do {} while (0) +#endif + +#include "../../super.h" /* + * Functions to call supervisor mode + * Super() in in TOS is buggy + */ + + +static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg) +{ + u16 dumm; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((reg & 0x00ff)<<1)); + dumm = __raw_readw( isp116x->data_reg ); + isp116x->addr_reg = (u16*)ISP116X_HCD_ADDR_BEE; + dumm = __raw_readw( isp116x->addr_reg ); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); +// ERR ( "data_reg: %x \n\r", isp116x->data_reg); +// ERR ( "addr_reg: %x \n\r", isp116x->addr_reg); +} + +static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val) +{ + u16 dumm; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0xff00)>>7) ); + dumm = __raw_readw(isp116x->data_reg); + isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x00ff)<<1)); + dumm = __raw_readw(isp116x->addr_reg); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); +// ERR ( "data_reg: %x \n\r", isp116x->data_reg); +// ERR ( "addr_reg: %x \n\r", isp116x->addr_reg); +} + +static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val) +{ + u16 dumm; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff)<<1)); + dumm = __raw_readw(isp116x->data_reg); + isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff00)>>7)); + dumm = __raw_readw(isp116x->addr_reg); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); +// ERR ( "data_reg: %x \n\r", isp116x->data_reg); +// ERR ( "addr_reg: %x \n\r", isp116x->addr_reg); +} + + +static inline u16 isp116x_read_data16(struct isp116x *isp116x) +{ + u16 val; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000); + val = readw(isp116x->data_reg ); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); + return val; +} + + +static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x) +{ + u16 val; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000); + val = __raw_readw(isp116x->data_reg ); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); +// ERR ( "data_reg: %x value: %x\n\r", isp116x->data_reg, val ); + return val; +} + +#if 0 /* We don't use it anymore */ +static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val) +{ +// p = SuperFromUser( ); + writew(val & 0xffff, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + writew(val >> 16, isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); +// SuperToUser( p ); +} +#endif + +/* + * Added for NetUSBee, to write HC registers without swaping them + * NetUSBee already swap them by hardware (i suppose.....) + */ +static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val) +{ + u16 dumm; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x000000ff)<<1) ); + dumm = __raw_readw(isp116x->data_reg); + isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x0000ff00)>>7)); + dumm = __raw_readw(isp116x->addr_reg); + isp116x_delay(isp116x, UDELAY); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff0000)>>15)); + dumm = __raw_readw(isp116x->data_reg); + isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff000000)>>23) ); + dumm = __raw_readw(isp116x->addr_reg); + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); +} +/***********************************************/ + +#if 0 /* We don't use it */ +static inline u32 isp116x_read_data32(struct isp116x *isp116x) +{ + u32 val; + p = SuperFromUser( ); + val = (u32) readw(isp116x->data_reg); + isp116x_delay(isp116x, UDELAY); + val |= ((u32) readw(isp116x->data_reg)) << 16; + isp116x_delay(isp116x, UDELAY); + SuperToUser( p ); + return val; +} +#endif + +/* + * Added for NetUSBee, to read HC registers without swaping them + * NetUSBee already swap them by hardware (i suppose.....) + */ +static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x) +{ + u32 val; + u32 p = 0; + if ( !(Super (SUP_INQUIRE))) + p = SuperFromUser( ); + isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000); + val = (u32) __raw_readw(isp116x->data_reg ); + isp116x_delay(isp116x, UDELAY); + val |= ((u32) __raw_readw(isp116x->data_reg )) << 16; + isp116x_delay(isp116x, UDELAY); + if ((Super (SUP_INQUIRE)) && (p)) + SuperToUser( p ); + return val; +} +/*******************************************************************/ + +/* Let's keep register access functions out of line. Hint: + we wait at least 150 ns at every access. +*/ + +/* with NetUSBee use raw_read to avoid swaping bytes*/ + +static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg) +{ + isp116x_write_addr(isp116x, reg); + return isp116x_raw_read_data16(isp116x); +} + +static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg) +{ + isp116x_write_addr(isp116x, reg); + return isp116x_raw_read_data32(isp116x); +} + +static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg, + unsigned val) +{ + isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); + isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff)); +} + +/* with NetUSBee used raw_write to avoid swaping bytes by software */ +static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg, + unsigned val) +{ + isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); + isp116x_raw_write_data32(isp116x, (u32) val); +} + +/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + +#endif /* _NETUSBEE_ISP116X_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c new file mode 100644 index 0000000..747ec55 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c @@ -0,0 +1,38 @@ +/* + * File: ltoa.c + * Purpose: Function normally found in a standard C lib. + * + * Notes: This supports ASCII only!!! + */ + +void ltoa(char *buf, long n, unsigned long base) +{ + unsigned long un; + char *tmp, ch; + un = n; + if((base == 10) && (n < 0)) + { + *buf++ = '-'; + un = -n; + } + tmp = buf; + do + { + ch = un % base; + un = un / base; + if(ch <= 9) + ch += '0'; + else + ch += 'a' - 10; + *tmp++ = ch; + } + while(un); + *tmp = '\0'; + while(tmp > buf) + { + ch = *buf; + *buf++ = *--tmp; + *tmp = ch; + } +} + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h new file mode 100644 index 0000000..8e480b5 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h @@ -0,0 +1,165 @@ +#ifndef MOD_DEVICETABLE_H +#define MOD_DEVICETABLE_H + +#define PCI_ANY_ID (~0) + +struct pci_device_id { + unsigned long vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ + unsigned long subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned long class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long driver_data; /* Data private to the driver */ +}; + +#define IEEE1394_MATCH_VENDOR_ID 0x0001 +#define IEEE1394_MATCH_MODEL_ID 0x0002 +#define IEEE1394_MATCH_SPECIFIER_ID 0x0004 +#define IEEE1394_MATCH_VERSION 0x0008 + +struct ieee1394_device_id { + unsigned long match_flags; + unsigned long vendor_id; + unsigned long model_id; + unsigned long specifier_id; + unsigned long version; + unsigned long driver_data; +}; + +/* + * Device table entry for "new style" table-driven USB drivers. + * User mode code can read these tables to choose which modules to load. + * Declare the table as a MODULE_DEVICE_TABLE. + * + * A probe() parameter will point to a matching entry from this table. + * Use the driver_info field for each match to hold information tied + * to that match: device quirks, etc. + * + * Terminate the driver's table with an all-zeroes entry. + * Use the flag values to control which fields are compared. + */ + +/** + * struct usb_device_id - identifies USB devices for probing and hotplugging + * @match_flags: Bit mask controlling of the other fields are used to match + * against new devices. Any field except for driver_info may be used, + * although some only make sense in conjunction with other fields. + * This is usually set by a USB_DEVICE_*() macro, which sets all + * other fields in this structure except for driver_info. + * @idVendor: USB vendor ID for a device; numbers are assigned + * by the USB forum to its members. + * @idProduct: Vendor-assigned product ID. + * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers. + * This is also used to identify individual product versions, for + * a range consisting of a single device. + * @bcdDevice_hi: High end of version number range. The range of product + * versions is inclusive. + * @bDeviceClass: Class of device; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Device classes specify behavior of all + * the interfaces on a devices. + * @bDeviceSubClass: Subclass of device; associated with bDeviceClass. + * @bDeviceProtocol: Protocol of device; associated with bDeviceClass. + * @bInterfaceClass: Class of interface; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Interface classes specify behavior only + * of a given interface; other interfaces may support other classes. + * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass. + * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass. + * @driver_info: Holds information used by the driver. Usually it holds + * a pointer to a descriptor understood by the driver, or perhaps + * device flags. + * + * In most cases, drivers will create a table of device IDs by using + * USB_DEVICE(), or similar macros designed for that purpose. + * They will then export it to userspace using MODULE_DEVICE_TABLE(), + * and provide it to the USB core through their usb_driver structure. + * + * See the usb_match_id() function for information about how matches are + * performed. Briefly, you will normally use one of several macros to help + * construct these entries. Each entry you provide will either identify + * one or more specific products, or will identify a class of products + * which have agreed to behave the same. You should put the more specific + * matches towards the beginning of your table, so that driver_info can + * record quirks of specific products. + */ +struct usb_device_id { + /* which fields to match against? */ + unsigned short match_flags; + + /* Used for product specific matches; range is inclusive */ + unsigned short idVendor; + unsigned short idProduct; + unsigned short bcdDevice_lo; + unsigned short bcdDevice_hi; + + /* Used for device class matches */ + unsigned char bDeviceClass; + unsigned char bDeviceSubClass; + unsigned char bDeviceProtocol; + + /* Used for interface class matches */ + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + + /* not matched against */ + unsigned long driver_info; +}; + +/* Some useful macros to use to create struct usb_device_id */ +#define USB_DEVICE_ID_MATCH_VENDOR 0x0001 +#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 +#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004 +#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 +#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010 +#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020 +#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040 +#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 +#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 +#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 + +/* s390 CCW devices */ +struct ccw_device_id { + unsigned short match_flags; /* which fields to match against */ + + unsigned short cu_type; /* control unit type */ + unsigned short dev_type; /* device type */ + unsigned char cu_model; /* control unit model */ + unsigned char dev_model; /* device model */ + + unsigned long driver_info; +}; + +#define CCW_DEVICE_ID_MATCH_CU_TYPE 0x01 +#define CCW_DEVICE_ID_MATCH_CU_MODEL 0x02 +#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE 0x04 +#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL 0x08 + + +#define PNP_ID_LEN 8 +#define PNP_MAX_DEVICES 8 + +struct pnp_device_id { + unsigned char id[PNP_ID_LEN]; + unsigned long driver_data; +}; + +struct pnp_card_device_id { + unsigned char id[PNP_ID_LEN]; + unsigned long driver_data; + struct { + unsigned char id[PNP_ID_LEN]; + } devs[PNP_MAX_DEVICES]; +}; + + +#define SERIO_ANY 0xff + +struct serio_device_id { + unsigned char type; + unsigned char extra; + unsigned char id; + unsigned char proto; +}; + + +#endif /* MOD_DEVICETABLE_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c new file mode 100644 index 0000000..8dcab45 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c @@ -0,0 +1,1953 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB and PCI bus. + * + * Interrupt support is added. Now, it has been tested + * on ULI1575 chip and works well with USB keyboard. + * + * (C) Copyright 2007 + * Zhang Wei, Freescale Semiconductor, Inc. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com - based on s3c24x0's driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTE + * this driver is intended for use with USB Mass Storage Devices + * (BBB) and USB keyboard. There is NO support for Isochronous pipes! + */ + +#include "../../config.h" +#include "../../usb.h" +#include "ohci.h" +#include "pci_ids.h" +#include "pcixbios.h" + +#include "../../debug.h" +/* Extra debug information, aside from config.h */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef SHOW_INFO +#undef OHCI_FILL_TRACE + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +/* + * e.g. PCI controllers need this + */ +#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS +# define readl(a) __swap_32(*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) +#else +# define readl(a) (*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) +#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ + +#define min_t(type, x, y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +/* Galvez: added to avoid shadow warnings */ +#define min2_t(type,x,y) \ + ({ type __a = (x); type __b = (y); __a < __b ? __a : __b; }) + +struct pci_device_id usb_pci_table[] = { + { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ULI1575 PCI OHCI module ids */ + { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NEC PCI OHCI module ids */ +// { PCI_VENDOR_ID_PHILIPS, PCI_VENDOR_ID_PHILIPS_ISP1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* Philips 1561 PCI OHCI module ids */ + /* Please add supported PCI OHCI controller ids here */ + { 0, 0, 0, 0, 0, 0, 0 } +}; + + +#define err(format, arg...) printf("ERROR: " format "\r\n", ## arg) +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\r\n", ## arg) +#else +#define info(format, arg...) do {} while (0) +#endif + +#define m16_swap(x) cpu_to_le16(x) +#define m32_swap(x) cpu_to_le32(x) + +typedef struct +{ + long ident; + union + { + long l; + short i[2]; + char c[4]; + } v; +} COOKIE; + +extern COOKIE *get_cookie(long id); +extern void udelay(long usec); +extern void ltoa(char *buf, long n, unsigned long base); + +/* global ohci_t */ +static ohci_t gohci; +/* device which was disconnected */ +struct usb_device *devgone; +char ohci_inited; + +static inline u32 roothub_a(struct ohci *hc) + { return readl(&hc->regs->roothub.a); } +static inline u32 roothub_b(struct ohci *hc) + { return readl(&hc->regs->roothub.b); } +static inline u32 roothub_status(struct ohci *hc) + { return readl(&hc->regs->roothub.status); } +static inline u32 roothub_portstatus(struct ohci *hc, int i) + { return readl(&hc->regs->roothub.portstatus[i]); } + +/* forward declaration */ +static int hc_interrupt(void); +static void td_submit_job(struct usb_device *dev, unsigned long pipe, +void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval); + +#if 0 +unsigned short cpu_to_le16(unsigned short val) +{ + extern unsigned short swap_short(unsigned short val); + if(gohci.big_endian) + return(swap_short(val)); + return(val); +} + +unsigned long cpu_to_le32(unsigned long val) +{ + extern unsigned long swap_long(unsigned long val); + if(gohci.big_endian) + return(swap_long(val)); + return(val); +} +#endif + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv(urb_priv_t *urb) +{ + int i; + struct td *td; + int last = urb->length - 1; + if(last >= 0) + { + for(i = 0; i <= last; i++) + { + td = urb->td[i]; + if(td) + { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } + usb_free(urb); +} + +/*-------------------------------------------------------------------------*/ + +#if DEBUG_HOST_LAYER +static int sohci_get_current_frame_number(struct usb_device *dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print(urb_priv_t *purb, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, + struct devrequest *setup, char *str, int small) +{ + DEBUG_HOST("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number(dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe)? 'O': 'I', + usb_pipetype(pipe) < 2 ? \ + (usb_pipeint(pipe)? "INTR": "ISOC"): \ + (usb_pipecontrol(pipe)? "CTRL": "BULK"), + (purb ? purb->actual_length : 0), + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if(!small) + { + int i, len; + if(usb_pipecontrol(pipe)) + { + DEBUG_HOST(__FILE__ ": cmd(8):"); + for(i = 0; i < 8 ; i++) + DEBUG_HOST(" %02x", ((__u8 *)setup)[i]); + DEBUG_HOST("\r\n"); + } + if(transfer_len > 0 && buffer) + { + DEBUG_HOST(__FILE__ ": data(%d/%d):", (purb ? purb->actual_length : 0), transfer_len); + len = usb_pipeout(pipe)? transfer_len : (purb ? purb->actual_length : 0); + for(i = 0; i < 16 && i < len; i++) + DEBUG_HOST(" %02x", ((__u8 *)buffer)[i]); + DEBUG_HOST("%s\r\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree + * inclusive iso eds */ +void ep_print_int_eds(ohci_t *ohci, char *str) +{ + int i, j; + __u32 *ed_p; + for(i = 0; i < 32; i++) + { + j = 5; + ed_p = &(ohci->hcca->int_table[i]); + if(*ed_p == 0) + continue; + DEBUG_HOST(__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while(*ed_p != 0 && j--) + { + ed_t *ed = (ed_t *)m32_swap((unsigned long)ed_p); + DEBUG_HOST(" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + DEBUG_HOST("\r\n"); + } +} + +static void ohci_dump_intr_mask(char *label, __u32 mask) +{ + DEBUG_HOST("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds(char *label, __u32 value) +{ + ed_t *edp; + value += gohci.dma_offset; + edp = (ed_t *)value; + if(value && (value < 0xDFFFF0)) /* STRAM */ + { + DEBUG_HOST("%s %08x", label, value); + DEBUG_HOST("%08x", edp->hwINFO); + DEBUG_HOST("%08x", edp->hwTailP); + DEBUG_HOST("%08x", edp->hwHeadP); + DEBUG_HOST("%08x", edp->hwNextED); + } +} + +static char *hcfs2string(int state) +{ + switch(state) + { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status(ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp = readl(®s->revision) & 0xff; + if(temp != 0x10) + DEBUG_HOST("spec %d.%d", (temp >> 4), (temp & 0x0f)); + temp = readl(®s->control); + DEBUG_HOST("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string(temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + temp = readl(®s->cmdstatus); + DEBUG_HOST("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); + ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); + maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent)); + maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead)); + maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent)); + maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead)); + maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent)); + maybe_print_eds("donehead", readl(®s->donehead)); +} + +static void ohci_dump_roothub(ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + if(verbose) + { + DEBUG_HOST("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b(controller); + DEBUG_HOST("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status(controller); + DEBUG_HOST("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + for(i = 0; i < ndp; i++) + { + temp = roothub_portstatus(controller, i); + DEBUG_HOST("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump(ohci_t *controller, int verbose) +{ + DEBUG_HOST("OHCI controller usb-%s state", controller->slot_name); + /* dumps some of the state we know about */ + ohci_dump_status(controller); + if(verbose) + ep_print_int_eds(controller, "hcca"); + DEBUG_HOST("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub(controller, 1); +} +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) +{ + ohci_t *ohci; + ed_t *ed; + urb_priv_t *purb_priv = urb; + int i, size = 0; + struct usb_device *dev = urb->dev; + unsigned long pipe = urb->pipe; + void *buffer = urb->transfer_buffer; + int transfer_len = urb->transfer_buffer_length; + int interval = urb->interval; + ohci = &gohci; + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if(ohci->disabled) + { + err("sohci_submit_job: EPIPE"); + return -1; + } + /* we're about to begin a new transaction here so mark the + * URB unfinished */ + urb->finished = 0; + /* every endpoint has a ed, locate and fill it */ + ed = ep_add_ed(dev, pipe, interval, 1); + if(!ed) + { + err("sohci_submit_job: ENOMEM"); + return -1; + } + /* for the private part of the URB we need the number of TDs (size) */ + switch(usb_pipetype(pipe)) + { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0) ? 2: (transfer_len - 1) / 4096 + 3; + break; + case PIPE_INTERRUPT: /* 1 TD */ + size = 1; + break; + } + ed->purb = urb; + if(size >= (N_URB_TD - 1)) + { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv->pipe = pipe; + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for(i = 0; i < size; i++) + { + purb_priv->td[i] = td_alloc(dev); + if(!purb_priv->td[i]) + { + purb_priv->length = i; + urb_free_priv(purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + if(ed->state == ED_NEW || (ed->state & ED_DEL)) + { + urb_free_priv(purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + /* link the ed into a chain if is not already */ + if(ed->state != ED_OPER) + ep_link(ohci, ed); + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + return 0; +} + +static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) +{ + struct ohci_regs *regs = hc->regs; + switch(usb_pipetype(urb->pipe)) + { + case PIPE_INTERRUPT: + /* implicitly requeued */ + if(urb->dev->irq_handle && (urb->dev->irq_act_len = urb->actual_length)) + { + writel(OHCI_INTR_WDH, ®s->intrenable); + readl(®s->intrenable); /* PCI posting flush */ + /* call interrupt device routine */ + DEBUG_HOST("irq_handle device %d", urb->dev->devnum); + urb->dev->irq_handle(urb->dev); + writel(OHCI_INTR_WDH, ®s->intrdisable); + readl(®s->intrdisable); /* PCI posting flush */ + } + urb->actual_length = 0; + td_submit_job(urb->dev, urb->pipe, urb->transfer_buffer, urb->transfer_buffer_length, NULL, urb, urb->interval); + break; + case PIPE_CONTROL: + case PIPE_BULK: + break; + default: + return 0; + } + return 1; +} + +/*-------------------------------------------------------------------------*/ + +#if DEBUG_HOST_LAYER +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number(struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + return m16_swap(ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* search for the right branch to insert an interrupt ed into the int tree + * do some load ballancing; + * returns the branch and + * sets the interval to interval = 2^integer (ld (interval)) */ + +static int ep_int_ballance(ohci_t *ohci, int interval, int load) +{ + int i, branch = 0; + /* search for the least loaded interrupt endpoint + * branch of all 32 branches + */ + for (i = 0; i < 32; i++) + if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) + branch = i; + + branch = branch % interval; + for (i = branch; i < 32; i += interval) + ohci->ohci_int_load [i] += load; + + return branch; +} + +/*-------------------------------------------------------------------------*/ + +/* 2^int( ld (inter)) */ + +static int ep_2_n_interval(int inter) +{ + int i; + for(i = 0; ((inter >> i) > 1) && (i < 5); i++); + return 1 << i; +} + +/*-------------------------------------------------------------------------*/ + +/* the int tree is a binary tree + * in order to process it sequentially the indexes of the branches have to + * be mapped the mapping reverses the bits of a word of num_bits length */ +static int ep_rev(int num_bits, int word) +{ + int i, wout = 0; + for(i = 0; i < num_bits; i++) + wout |= (((word >> i) & 1) << (num_bits - i - 1)); + return wout; +} + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link(ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + int int_branch; + int i; + int inter; + int interval; + int load; + __u32 *ed_p; + ed->state = ED_OPER; + ed->int_interval = 0; + switch(ed->type) + { + case PIPE_CONTROL: + ed->hwNextED = 0; + if(ohci->ed_controltail == NULL) + writel(ed - ohci->dma_offset, &ohci->regs->ed_controlhead); + else + ohci->ed_controltail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset); + ed->ed_prev = ohci->ed_controltail; + if(!ohci->ed_controltail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping) + { + ohci->hc_control |= OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + case PIPE_BULK: + ed->hwNextED = 0; + if(ohci->ed_bulktail == NULL) + writel(ed - ohci->dma_offset, &ohci->regs->ed_bulkhead); + else + ohci->ed_bulktail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset); + ed->ed_prev = ohci->ed_bulktail; + if(!ohci->ed_bulktail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping) + { + ohci->hc_control |= OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + case PIPE_INTERRUPT: + load = ed->int_load; + interval = ep_2_n_interval(ed->int_period); + ed->int_interval = interval; + int_branch = ep_int_ballance(ohci, interval, load); + ed->int_branch = int_branch; + for(i = 0; i < ep_rev(6, interval); i += inter) + { + inter = 1; + for(ed_p = &(ohci->hcca->int_table[ep_rev(5, i) + int_branch]); + (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval); + ed_p = &(((ed_t *)ed_p)->hwNextED)) + inter = ep_rev(6, ((ed_t *)ed_p)->int_interval); + ed->hwNextED = *ed_p; + *ed_p = m32_swap((unsigned long)ed - ohci->dma_offset); + } + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* scan the periodic table to find and unlink this ED */ +static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, + unsigned idx, unsigned period) +{ + for( ;idx < NUM_INTS; idx += period) + { + __u32 *ed_p = &ohci->hcca->int_table[idx]; + /* ED might have been unlinked through another path */ + while(*ed_p != 0) + { + if(((struct ed *)m32_swap((unsigned long)ed_p)) == ed) + { + *ed_p = ed->hwNextED; + break; + } + ed_p = &(((struct ed *)m32_swap((unsigned long)ed_p))->hwNextED); + } + } +} + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink(ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + int i; + ed->hwINFO |= m32_swap(OHCI_ED_SKIP); + switch(ed->type) + { + case PIPE_CONTROL: + if(ed->ed_prev == NULL) + { + if(!ed->hwNextED) + { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } + else + ed->ed_prev->hwNextED = ed->hwNextED; + if(ohci->ed_controltail == ed) + ohci->ed_controltail = ed->ed_prev; + else + ((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev; + break; + case PIPE_BULK: + if(ed->ed_prev == NULL) + { + if(!ed->hwNextED) + { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } + else + ed->ed_prev->hwNextED = ed->hwNextED; + if(ohci->ed_bulktail == ed) + ohci->ed_bulktail = ed->ed_prev; + else + ((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev; + break; + case PIPE_INTERRUPT: + periodic_unlink(ohci, ed, 0, 1); + for(i = ed->int_branch; i < 32; i += ed->int_interval) + ohci->ohci_int_load[i] -= ed->int_load; + break; + } + ed->state = ED_UNLINK; + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the + * usb_set_configuration command, but the USB stack is a little bit + * stateless so we do it at every transaction if the state of the ed + * is ED_NEW then a dummy td is added and the state is changed to + * ED_UNLINK in all other cases the state is left unchanged the ed + * info fields are setted anyway even though most of them should not + * change + */ +static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, int interval, int load) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + struct ohci_device *ohci_dev = gohci.ohci_dev; + ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; + if((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) + { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + if(ed->state == ED_NEW) + { + /* dummy td; end of td list for ed */ + td = td_alloc(usb_dev); + ed->hwTailP = m32_swap((unsigned long)td - gohci.dma_offset); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype(pipe); + ohci_dev->ed_cnt++; + } + ed->hwINFO = m32_swap(usb_pipedevice(pipe) + | usb_pipeendpoint(pipe) << 7 + | (usb_pipeisoc(pipe)? 0x8000: 0) + | (usb_pipecontrol(pipe)? 0: \ + (usb_pipeout(pipe)? 0x800: 0x1000)) + | usb_pipeslow(pipe) << 13 + | usb_maxpacket(usb_dev, pipe) << 16); + if(ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) + { + ed->int_period = interval; + ed->int_load = load; + } + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill(ohci_t *ohci, unsigned int info, void *data, int len, + struct usb_device *dev, int idx, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + if(idx > urb_priv->length) + { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td[idx]; + td_pt->hwNextTD = 0; + /* fill the old dummy TD */ + td = urb_priv->td[idx] = (td_t *)((m32_swap(urb_priv->ed->hwTailP) & ~0xf) + ohci->dma_offset); + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = idx; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if(usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) + { + for(i = 0; i < len; i++) + printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); + printf("\r\n"); + } +#endif + if(!len) + data = NULL; + td->hwINFO = m32_swap(info); + if(data != NULL) + { + td->hwCBP = m32_swap((unsigned long)data - ohci->dma_offset); + td->hwBE = m32_swap((unsigned long)(data + len - 1 - ohci->dma_offset)); + } + else + { + td->hwCBP = 0; + td->hwBE = 0; + } + td->hwNextTD = m32_swap((unsigned long)td_pt - ohci->dma_offset); + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +#if 0 + if(data) + { + int i; + static char buf[4096]; + char buf2[16]; + *buf = '\0'; + for(i = 0; i < len; i++) + { + ltoa(buf2, (long)*(unsigned char *)(data + i), 16); + strcat(buf, buf2); + strcat(buf, " "); + } + err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", + m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td); + err(" ... %s", buf); + } + else + err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", + m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td); +#endif +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle + * bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) + toggle = TD_T_TOGGLE; + else + { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if(data_len) + data = buffer; + else + data = NULL; + switch(usb_pipetype(pipe)) + { + case PIPE_BULK: + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) + { + td_fill(ohci, info | (cnt? TD_T_TOGGLE : toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + if(!ohci->sleeping) /* start bulk list */ + writel(OHCI_BLF, &ohci->regs->cmdstatus); + break; + case PIPE_CONTROL: + /* Setup phase */ + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill(ohci, info, setup, 8, dev, cnt++, urb); + /* Optional Data phase */ + if(data_len > 0) + { + info = usb_pipeout(pipe) ? TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + } + /* Status phase */ + info = usb_pipeout(pipe) ? TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill(ohci, info, data, 0, dev, cnt++, urb); + if(!ohci->sleeping) /* start Control list */ + writel(OHCI_CLF, &ohci->regs->cmdstatus); + break; + case PIPE_INTERRUPT: + info = usb_pipeout(urb->pipe) ? TD_CC | TD_DP_OUT | toggle : TD_CC | TD_R | TD_DP_IN | toggle; + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + break; + } + if(urb->length != cnt) + DEBUG_HOST("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t *td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = td->ed->purb; + tdINFO = m32_swap(td->hwINFO); + tdBE = m32_swap(td->hwBE); + tdCBP = m32_swap(td->hwCBP); + if(tdBE) + tdBE += gohci.dma_offset; + if(tdCBP) + tdCBP += gohci.dma_offset; + if(!(usb_pipecontrol(lurb_priv->pipe) && ((td->index == 0) || (td->index == lurb_priv->length - 1)))) + { + if(tdBE != 0) + { + if(td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ +void check_status(td_t *td_list) +{ + urb_priv_t *lurb_priv = td_list->ed->purb; + int urb_len = lurb_priv->length; + __u32 *phwHeadP = &td_list->ed->hwHeadP; + int cc = TD_CC_GET(m32_swap(td_list->hwINFO)); + if(cc) + { + err(" USB-error: %s (%x)", cc_to_string[cc], cc); + if(*phwHeadP & m32_swap(0x1)) + { + if(lurb_priv && ((td_list->index + 1) < urb_len)) + { + *phwHeadP = (lurb_priv->td[urb_len - 1]->hwNextTD & m32_swap(0xfffffff0)) | (*phwHeadP & m32_swap(0x2)); + lurb_priv->td_cnt += urb_len - td_list->index - 1; + } + else + *phwHeadP &= m32_swap(0xfffffff2); + } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif + } +} + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ +td_t *dl_reverse_done_list(ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + td_list_hc = m32_swap(ohci->hcca->done_head) & ~0xf; + if(td_list_hc) + td_list_hc += ohci->dma_offset; + ohci->hcca->done_head = 0; + while(td_list_hc) + { + td_list = (td_t *)td_list_hc; + check_status(td_list); + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap(td_list->hwNextTD) & ~0xf; + if(td_list_hc) + td_list_hc += ohci->dma_offset; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ +/*-------------------------------------------------------------------------*/ + +static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) +{ + if((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) + urb->finished = sohci_return_job(ohci, urb); + else + DEBUG_HOST("finish_urb: strange.., ED state %x, \r\n", status); +} + +/* + * Used to take back a TD from the host controller. This would normally be + * called from within dl_done_list, however it may be called directly if the + * HC no longer sees the TD and it has not appeared on the donelist (after + * two frames). This bug has been observed on ZF Micro systems. + */ +int takeback_td(ohci_t *ohci, td_t *td_list) +{ + ed_t *ed; + int cc; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + tdINFO = m32_swap(td_list->hwINFO); + ed = td_list->ed; + lurb_priv = ed->purb; + dl_transfer_length(td_list); + lurb_priv->td_cnt++; + /* error code of transfer */ + cc = TD_CC_GET(tdINFO); + if(cc) + { + err("USB-error: %s (%x)", cc_to_string[cc], cc); + stat = cc_to_error[cc]; + } + /* see if this done list makes for all TD's of current URB, + * and mark the URB finished if so */ + if(lurb_priv->td_cnt == lurb_priv->length) + finish_urb(ohci, lurb_priv, ed->state); + DEBUG_HOST("dl_done_list: processing TD %x, len %x\r\n", + lurb_priv->td_cnt, lurb_priv->length); + if(ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) + { + edHeadP = m32_swap(ed->hwHeadP) & ~0xf; + edTailP = m32_swap(ed->hwTailP); + /* unlink eds if they are not busy */ + if((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink(ohci, ed); + } + return stat; +} + +int dl_done_list(ohci_t *ohci) +{ + int stat = 0; + td_t *td_list = dl_reverse_done_list(ohci); + while(td_list) + { + td_t *td_next = td_list->next_dl_td; + stat = takeback_td(ohci, td_list); + td_list = td_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#if DEBUG_HOST_LAYER +#define WR_RH_STAT(x) {info("WR:status %#8x", (x)); writel((x), \ + &gohci.regs->roothub.status); } +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ + (x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), \ + &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res = -1; + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus(controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; +#if DEBUG_HOST_LAYER + pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else +// wait_ms(1); +#endif + if(usb_pipeint(pipe)) + { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = le16_to_cpu(cmd->value); + wIndex = le16_to_cpu(cmd->index); + wLength = le16_to_cpu(cmd->length); + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + switch(bmRType_bReq) + { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + case RH_GET_STATUS: + *(__u16 *)data_buf = cpu_to_le16(1); + OK(2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *)data_buf = cpu_to_le16(0); + OK(2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *)data_buf = cpu_to_le16(0); + OK(2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *)data_buf = cpu_to_le32(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK(4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *)data_buf = cpu_to_le32(RD_RH_PORTSTAT); + OK(4); + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch(wValue) + { + case (RH_ENDPOINT_STALL): OK(0); + } + break; + case RH_CLEAR_FEATURE | RH_CLASS: + switch(wValue) + { + case RH_C_HUB_LOCAL_POWER: OK(0); + case (RH_C_HUB_OVER_CURRENT): WR_RH_STAT(RH_HS_OCIC); OK(0); + } + break; + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch(wValue) + { + case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); + case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); + case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); + case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); + case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); + case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); + case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); + case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); + } + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch(wValue) + { + case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSS); OK(0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if(RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PRS); + OK(0); + case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_PPS); wait_ms(100); OK(0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if(RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PES); + OK(0); + } + break; + case RH_SET_ADDRESS: + gohci.rh.devnum = wValue; + OK(0); + case RH_GET_DESCRIPTOR: + switch((wValue & 0xff00) >> 8) + { + case(0x01): /* device descriptor */ + len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_dev_des), wLength)); + data_buf = root_hub_dev_des; + OK(len); + case(0x02): /* configuration descriptor */ + len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_config_des), wLength)); + data_buf = root_hub_config_des; + OK(len); + case(0x03): /* string descriptors */ + if(wValue == 0x0300) + { + len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index0), wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue == 0x0301) + { + len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index1), wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a(&gohci); + data_buf[0] = 9; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = temp & RH_A_NDP; + data_buf[3] = 0; + if(temp & RH_A_PSM) /* per-port power switching? */ + data_buf[3] |= 0x1; + if(temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf[3] |= 0x10; + else if(temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf[3] |= 0x8; + /* corresponds to data_buf[4-7] */ + datab[1] = 0; + data_buf[5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b(&gohci); + data_buf[7] = temp & RH_B_DR; + if(data_buf[2] < 7) + data_buf[8] = 0xff; + else + { + data_buf[0] += 2; + data_buf[8] = (temp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + len = min_t(unsigned int, leni, min2_t(unsigned int, data_buf [0], wLength)); + OK(len); + } + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK(1); + case RH_SET_CONFIGURATION: WR_RH_STAT(0x10000); OK(0); + default: + DEBUG_HOST("unsupported root hub command"); + stat = USB_ST_STALLED; + } +#if DEBUG_HOST_LAYER + ohci_dump_roothub(&gohci, 1); +#else +// wait_ms(1); +#endif + len = min_t(int, len, leni); + if(data != data_buf) + memcpy(data, data_buf, len); + dev->act_len = len; + dev->status = stat; +#if DEBUG_HOST_LAYER + pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else +// wait_ms(1); +#endif + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub accesses. */ + +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + urb_priv_t *urb; + urb = (urb_priv_t *)usb_malloc(sizeof(urb_priv_t)); + if(urb == NULL) + { + err("submit_common_msg malloc failed"); + return -1; + } + memset(urb, 0, sizeof(urb_priv_t)); + urb->dev = dev; + urb->pipe = pipe; + urb->transfer_buffer = buffer; + urb->transfer_buffer_length = transfer_len; + urb->interval = interval; + /* device pulled? Shortcut the action. */ + if(devgone == dev) + { + dev->status = USB_ST_CRC_ERR; + return 0; + } +#if DEBUG_HOST_LAYER + urb->actual_length = 0; + pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else +// wait_ms(1); +#endif + if(!maxsize) + { + err("submit_common_message: pipesize for pipe %lx is zero", pipe); + return -1; + } + if(sohci_submit_job(urb, setup) < 0) + { + err("sohci_submit_job failed"); + return -1; + } +#if 0 + wait_ms(10); + /* ohci_dump_status(&gohci); */ +#endif + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if(usb_pipebulk(pipe)) + timeout = BULK_TO; + else + timeout = 100; + /* wait for it to complete */ + while(1) + { + /* check whether the controller is done */ +#ifdef COLDFIRE /* no bus snooping on Coldfire */ +#ifdef NETWORK +#ifdef LWIP + extern unsigned long pxCurrentTCB, tid_TOS; + extern void flush_caches(void); + if(pxCurrentTCB != tid_TOS) + flush_caches(); + else +#endif /* LWIP */ +#endif /* NETWORK */ + asm(" .chip 68060\n cpusha DC\n .chip 5200\n"); +#endif /* COLDFIRE */ + stat = hc_interrupt(); + if(stat < 0) + { + stat = USB_ST_CRC_ERR; + break; + } + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if((stat >= 0) && (stat != 0xff) && (urb->finished)) + { + /* 0xff is returned for an SF-interrupt */ + break; + } + if(--timeout) + { + wait_ms(1); + if(!urb->finished) + DEBUG_HOST("*"); + } + else + { + err("CTL:TIMEOUT "); + DEBUG_HOST("submit_common_msg: TO status %x\r\n", stat); + urb->finished = 1; + stat = USB_ST_CRC_ERR; + break; + } + } + dev->status = stat; + dev->act_len = transfer_len; +#if DEBUG_HOST_LAYER + pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else +// wait_ms(1); +#endif + /* free TDs in urb_priv */ + if(!usb_pipeint(pipe)) + urb_free_priv(urb); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + info("submit_control_msg"); +#if DEBUG_HOST_LAYER + pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else +// wait_ms(1); +#endif + if(!maxsize) + { + err("submit_control_message: pipesize for pipe %lx is zero", pipe); + return -1; + } + if(((pipe >> 8) & 0x7f) == gohci.rh.devnum) + { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, setup); + } + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval) +{ + info("submit_int_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, interval); +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset(ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + DEBUG_HOST("%s\r\n", __FUNCTION__); + if(readl(&ohci->regs->control) & OHCI_CTRL_IR) + { + /* SMM owns the HC */ + writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */ + info("USB HC TakeOver from SMM"); + while(readl(&ohci->regs->control) & OHCI_CTRL_IR) + { + wait_ms(10); + if(--smm_timeout == 0) + { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + /* Disable HC interrupts */ + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + DEBUG_HOST("USB HC reset_hc usb-%s: ctrl = 0x%X ;\r\n", ohci->slot_name, readl(&ohci->regs->control)); + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel(ohci->hc_control, &ohci->regs->control); + /* HC Reset requires max 10 us delay */ + writel(OHCI_HCR, &ohci->regs->cmdstatus); + while((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) + { + if(--timeout == 0) + { + err("USB HC reset timed out!"); + return -1; + } + udelay(1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start(ohci_t *ohci) +{ + __u32 mask; + unsigned int fminterval; + ohci->disabled = 1; + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + writel(0, &ohci->regs->ed_controlhead); + writel(0, &ohci->regs->ed_bulkhead); + writel((__u32)ohci->hcca - ohci->dma_offset, &ohci->regs->hcca); /* a reset clears this */ + fminterval = 0x2edf; + writel((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel(fminterval, &ohci->regs->fminterval); + writel(0x628, &ohci->regs->lsthresh); + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel(ohci->hc_control, &ohci->regs->control); + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | OHCI_INTR_OC | OHCI_INTR_MIE); + writel(mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel(mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel(mask, &ohci->regs->intrenable); +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, &ohci->regs->roothub.a); + writel(RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay((roothub_a(ohci) >> 23) & 0x1fe); + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_USB_INTERRUPT_POLLING + +/* Poll USB interrupt. */ +void usb_event_poll(void) +{ + if(ohci_inited) + { +#ifdef COLDFIRE /* no bus snooping on Coldfire */ +#ifdef NETWORK +#ifdef LWIP + extern unsigned long pxCurrentTCB, tid_TOS; + extern void flush_caches(void); + if(pxCurrentTCB != tid_TOS) + flush_caches(); + else +#endif /* LWIP */ +#endif /* NETWORK */ + asm(" .chip 68060\n cpusha DC\n .chip 5200\n"); +#endif /* COLDFIRE */ + hc_interrupt(); + } +} + +#endif /* CONFIG_USB_INTERRUPT_POLLING */ + +/* an interrupt happens */ +static int hc_interrupt(void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints, stat = -1; + if((ohci->hcca->done_head != 0) && !(m32_swap(ohci->hcca->done_head) & 0x01)) + ints = OHCI_INTR_WDH; + else + { + ints = readl(®s->intrstatus); + if(ints == ~(u32)0) + { + ohci->disabled++; + err("%s device removed!", ohci->slot_name); + return -1; + } + else + { + ints &= readl(®s->intrenable); + if(ints == 0) + { +// DEBUG_HOST("hc_interrupt: returning..\r\n"); + return 0xff; + } + } + } + DEBUG_HOST("Interrupt: 0x%x frame: 0x%x", ints, le16_to_cpu(ohci->hcca->frame_no)); + if(ints & OHCI_INTR_RHSC) + { + stat = 0xff; + } + if(ints & OHCI_INTR_UE) + { + ohci->disabled++; + err("OHCI Unrecoverable Error, controller usb-%s disabled", ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ +#if DEBUG_HOST_LAYER + ohci_dump(ohci, 1); +#else +// wait_ms(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset(ohci); + return -1; + } + if(ints & OHCI_INTR_WDH) + { +// wait_ms(1); + writel(OHCI_INTR_WDH, ®s->intrdisable); + (void)readl(®s->intrdisable); /* flush */ + stat = dl_done_list(&gohci); + writel(OHCI_INTR_WDH, ®s->intrenable); + (void)readl(®s->intrdisable); /* flush */ + } + if(ints & OHCI_INTR_SO) + { + DEBUG_HOST("USB Schedule overrun\r\n"); + writel(OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if(ints & OHCI_INTR_SF) + { + unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; +// wait_ms(1); + writel(OHCI_INTR_SF, ®s->intrdisable); + if(ohci->ed_rm_list[frame] != NULL) + writel(OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + writel(ints, ®s->intrstatus); + return stat; +} + +#ifndef CONFIG_USB_INTERRUPT_POLLING + +static int handle_usb_interrupt(void) +{ +#ifdef COLDFIRE /* no bus snooping on Coldfire */ + extern void flush_caches(void); + conout_debug('.'); + flush_caches(); /* native interrupt */ +#endif /* COLDFIRE */ + gohci.irq = 0; + hc_interrupt(); + gohci.irq = -1; + return 1; /* clear interrupt, 0: disable interrupt */ +} + +void usb_enable_interrupt(int enable) +{ + ohci_t *ohci = &gohci; + if(enable) + writel(OHCI_INTR_MIE, &ohci->regs->intrenable); + else + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); +} + +#endif /* !CONFIG_USB_INTERRUPT_POLLING */ + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci(ohci_t *ohci) +{ + DEBUG_HOST("USB HC release ohci usb-%s", ohci->slot_name); + if(!ohci->disabled) + hc_reset(ohci); +} + +static void hc_free_buffers(ohci_t *ohci) +{ + if(ohci->td_unaligned != NULL) + { + usb_free(ohci->td_unaligned); + ohci->td_unaligned = NULL; + } + if(ohci->ohci_dev_unaligned != NULL) + { + usb_free(ohci->ohci_dev_unaligned); + ohci->ohci_dev_unaligned = NULL; + } + if(ohci->hcca_unaligned != NULL) + { + usb_free(ohci->hcca_unaligned); + ohci->hcca_unaligned = NULL; + } +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +int usb_lowlevel_init(long handle, const struct pci_device_id *ent) +{ + char buf[16]; + unsigned long usb_base_addr = 0xFFFFFFFF; + PCI_RSC_DESC *pci_rsc_desc; +#ifdef PCI_XBIOS + pci_rsc_desc = (PCI_RSC_DESC *)get_resource(handle); /* USB OHCI */ +#else + COOKIE *p = get_cookie('_PCI'); + PCI_COOKIE *bios_cookie = (PCI_COOKIE *)p->v.l; + if(bios_cookie == NULL) /* faster than XBIOS calls */ + return(-1); + tab_funcs_pci = &bios_cookie->routine[0]; + pci_rsc_desc = (PCI_RSC_DESC *)Get_resource(handle); /* USB OHCI */ +#endif + if(handle && (ent != NULL)) + { + memset(&gohci, 0, sizeof(ohci_t)); + gohci.handle = handle; + } + else if(!gohci.handle) /* for restart USB cmd */ + return(-1); + /* this must be aligned to a 256 byte boundary */ + gohci.hcca_unaligned = (struct ohci_hcca *)usb_malloc(sizeof(struct ohci_hcca) + 256); + if(gohci.hcca_unaligned == NULL) + { + err("HCCA malloc failed"); + return -1; + } + /* align the storage */ + gohci.hcca = (struct ohci_hcca *)(((unsigned long)gohci.hcca_unaligned + 255) & ~255); + memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); + info("aligned ghcca 0x%p", gohci.hcca); + gohci.ohci_dev_unaligned = (struct ohci_device *)usb_malloc(sizeof(struct ohci_device) + 8); + if(gohci.ohci_dev_unaligned == NULL) + { + err("EDs malloc failed"); + hc_free_buffers(&gohci); + return -1; + } + gohci.ohci_dev = (struct ohci_device *)(((unsigned long)gohci.ohci_dev_unaligned + 7) & ~7); + memset(gohci.ohci_dev, 0, sizeof(struct ohci_device)); + info("aligned EDs 0x%p", gohci.ohci_dev); + gohci.td_unaligned = (td_t *)usb_malloc(sizeof(td_t) * (NUM_TD + 1)); + if(gohci.td_unaligned == NULL) + { + err("TDs malloc failed"); + hc_free_buffers(&gohci); + return -1; + } + ptd = (td_t *)(((unsigned long)gohci.td_unaligned + 7) & ~7); + memset(ptd, 0, sizeof(td_t) * NUM_TD); + info("aligned TDs 0x%p", ptd); + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + if((long)pci_rsc_desc >= 0) + { + unsigned short flags; + do + { + DEBUG_HOST("PCI USB descriptors: flags 0x%08x start 0x%08x \r\n offset 0x%08x dmaoffset 0x%08x length 0x%08x", + pci_rsc_desc->flags, pci_rsc_desc->start, pci_rsc_desc->offset, pci_rsc_desc->dmaoffset, pci_rsc_desc->length); + if(!(pci_rsc_desc->flags & FLG_IO)) + { + if(usb_base_addr == 0xFFFFFFFF) + { + usb_base_addr = pci_rsc_desc->start; + gohci.regs = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + gohci.dma_offset = pci_rsc_desc->dmaoffset; + if((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) + gohci.big_endian = 0; /* host bridge make swapping intel -> motorola */ + else + gohci.big_endian = 1; /* driver must swapping intel -> motorola */ + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc += (unsigned long)pci_rsc_desc->next; + } + while(!(flags & FLG_LAST)); + } + else + { + hc_free_buffers(&gohci); + return(-1); /* get_resource error */ + } + if(usb_base_addr == 0xFFFFFFFF) + { + hc_free_buffers(&gohci); + return(-1); + } + if(handle && (ent != NULL)) + { + switch(ent->vendor) + { + case PCI_VENDOR_ID_AL: gohci.slot_name = "uli1575"; break; + case PCI_VENDOR_ID_NEC: gohci.slot_name = "uPD720101"; break; + case PCI_VENDOR_ID_PHILIPS: gohci.slot_name = "isp1561"; break; + default: gohci.slot_name = "generic"; break; + } + } + (void) Cconws("OHCI usb-"); + (void) Cconws(gohci.slot_name); + (void) Cconws(", regs address 0x"); + ltoa(buf, (long)gohci.regs, 16); + (void) Cconws(buf); + (void) Cconws(", PCI handle 0x"); + ltoa(buf, handle, 16); + (void) Cconws(buf); + (void) Cconws("\r\n"); + gohci.flags = 0; + if(hc_reset(&gohci) < 0) + { + err("Can't reset usb-%s", gohci.slot_name); + hc_release_ohci(&gohci); + hc_free_buffers(&gohci); + return -1; + } + if(hc_start(&gohci) < 0) + { + err("Can't start usb-%s", gohci.slot_name); + hc_release_ohci(&gohci); + hc_free_buffers(&gohci); + /* Initialization failed */ + return -1; + } +#if DEBUG_HOST_LAYER + ohci_dump(&gohci, 1); +#else +// wait_ms(1); +#endif +#ifndef CONFIG_USB_INTERRUPT_POLLING +#ifdef PCI_XBIOS + hook_interrupt(handle, handle_usb_interrupt, NULL); +#else + Hook_interrupt(handle, (void *)handle_usb_interrupt, NULL); +#endif /* PCI_BIOS */ +#endif /* CONFIG_USB_INTERRUPT_POLLING */ + ohci_inited = 1; + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if(!ohci_inited) + return 0; +#ifndef CONFIG_USB_INTERRUPT_POLLING +#ifdef PCI_XBIOS + unhook_interrupt(gohci.handle); +#else + Unhook_interrupt(gohci.handle); +#endif /* PCI_BIOS */ +#endif /* CONFIG_USB_INTERRUPT_POLLING */ + /* call hc_release_ohci() here ? */ + hc_reset(&gohci); + hc_free_buffers(&gohci); + /* This driver is no longer initialised. It needs a new low-level + * init (board/cpu) before it can be used again. */ + ohci_inited = 0; + return 0; +} diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci.h new file mode 100644 index 0000000..b07e3b2 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/ohci.h @@ -0,0 +1,457 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +static const char *cc_to_string[16] = { + "No Error", + "CRC: Last data packet from endpoint contained a CRC error.", + "BITSTUFFING: Last data packet from endpoint contained a bit stuffing violation", + "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID that did not match the expected value.", + "STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID", + "DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT)", + "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT)", + "UNEXPECTEDPID: Receive PID was not valid when encountered or PID value is not defined.", + "DATAOVERRUN: The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in MaximumPacketSize field of ED) or the remaining buffer size.", + "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer", + "reserved1", + "reserved2", + "BUFFEROVERRUN: During an IN, HC received data from endpoint faster than it could be written to system memory", + "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from system memory fast enough to keep up with data USB data rate.", + "NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(1)", + "NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(2)", +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + void *purb; + __u32 unused[2]; +} __attribute__((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute__((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ +#else + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ +#endif + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute__((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS +# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" +#endif + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; + } roothub; +} __attribute__((aligned(32))); + +/* Some EHCI controls */ +#define EHCI_USBCMD_OFF 0x20 +#define EHCI_USBCMD_HCRESET (1 << 1) + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + struct usb_device *dev; + int state; + unsigned long pipe; + void *transfer_buffer; + int transfer_buffer_length; + int interval; + int actual_length; + int finished; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + +typedef struct ohci { + long handle; /* PCI BIOS */ + int big_endian; /* PCI BIOS */ + struct ohci_hcca *hcca_unaligned; + struct ohci_hcca *hcca; /* hcca */ + td_t *td_unaligned; + struct ohci_device *ohci_dev_unaligned; + /* this allocates EDs for all possible endpoints */ + struct ohci_device *ohci_dev; + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + unsigned long dma_offset; + struct ohci_regs *regs; /* OHCI controller's memory */ + + int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe, + int interval, int load); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td *td_alloc(struct usb_device *usb_dev) +{ + int i; + struct td *td; + td = NULL; + for(i = 0; i < NUM_TD; i++) + { + if(ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + return td; +} + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +} + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h new file mode 100644 index 0000000..29ea2de --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h @@ -0,0 +1,2613 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +/* added code to find different types of USB controllers */ +#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 +#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 +#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 + +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 +#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_6010 0x6010 +#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 +#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_CISSC 0x46 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_LSI_53C1510 0x000a +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_LSI_53C895A 0x0012 +#define PCI_DEVICE_ID_LSI_53C875A 0x0013 +#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 +#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 +#define PCI_DEVICE_ID_LSI_53C1030 0x0030 +#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032 +#define PCI_DEVICE_ID_LSI_53C1035 0x0040 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f +#define PCI_DEVICE_ID_LSI_FC909 0x0621 +#define PCI_DEVICE_ID_LSI_FC929 0x0622 +#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 +#define PCI_DEVICE_ID_LSI_FC919 0x0624 +#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 +#define PCI_DEVICE_ID_LSI_FC929X 0x0626 +#define PCI_DEVICE_ID_LSI_FC939X 0x0642 +#define PCI_DEVICE_ID_LSI_FC949X 0x0640 +#define PCI_DEVICE_ID_LSI_FC919X 0x0628 +#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 +#define PCI_DEVICE_ID_LSI_61C102 0x0901 +#define PCI_DEVICE_ID_LSI_63C815 0x1000 +#define PCI_DEVICE_ID_LSI_SAS1064 0x0050 +#define PCI_DEVICE_ID_LSI_SAS1066 0x005E +#define PCI_DEVICE_ID_LSI_SAS1068 0x0054 +#define PCI_DEVICE_ID_LSI_SAS1064A 0x005C +#define PCI_DEVICE_ID_LSI_SAS1064E 0x0056 +#define PCI_DEVICE_ID_LSI_SAS1066E 0x005A +#define PCI_DEVICE_ID_LSI_SAS1068E 0x0058 +#define PCI_DEVICE_ID_LSI_SAS1078 0x0060 + +#define PCI_VENDOR_ID_ATI 0x1002 +/* Mach64 */ +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215ET222 0x4554 +/* Mach64 / Rage */ +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215XL 0x4752 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_215_IV 0x4756 +#define PCI_DEVICE_ID_ATI_215_IW 0x4757 +#define PCI_DEVICE_ID_ATI_215_IZ 0x475A +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 +#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 +#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 +#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 +#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D +#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E +#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 +#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 +#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 +/* Mach64 VT */ +#define PCI_DEVICE_ID_ATI_264VT 0x5654 +#define PCI_DEVICE_ID_ATI_264VU 0x5655 +#define PCI_DEVICE_ID_ATI_264VV 0x5656 +/* Rage128 GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 +#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 +#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247 +/* Rage128 VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b +#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c +#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345 +#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346 +#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347 +#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348 +#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b +#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c +#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d +#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e +/* Rage128 Ultra */ +#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446 +#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453 +#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454 +#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455 +/* Rage128 M3 */ +#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 +#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 +/* Rage128 M4 */ +#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46 +#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c +/* Rage128 Pro GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041 +#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042 +#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043 +#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044 +#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045 +#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 +/* Rage128 Pro VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 +#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 +#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 +#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A +#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B +#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C +#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D +#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E +#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F +#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 +#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 +#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 +#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 +#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 +#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 +#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 +#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 +/* Rage128 M4 */ +#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45 +#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46 +/* Radeon R100 */ +#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 +/* Radeon RV100 (VE) */ +#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a +/* Radeon R200 (8500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c +#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e +#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f +#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c +#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 +/* Radeon R200 (9100) */ +#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d +/* Radeon RV200 (7500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 +#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 +/* Radeon NV-100 */ +#define PCI_DEVICE_ID_ATI_RADEON_N1 0x5159 +#define PCI_DEVICE_ID_ATI_RADEON_N2 0x515a +/* Radeon RV250 (9000) */ +#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 +#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 +#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 +#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 +/* Radeon RV280 (9200) */ +#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 +#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 +/* Radeon R300 (9500) */ +#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144 +/* Radeon R300 (9700) */ +#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 +#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 +#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 +#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 +#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145 +#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146 +/* Radeon R350 (9800) */ +#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48 +#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49 +/* Radeon RV350 (9600) */ +#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150 +#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152 +/* Radeon M6 */ +#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 +#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a +/* Radeon M7 */ +#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 +#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 +/* Radeon M9 */ +#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 +#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 +#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 +#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 +/* Radeon */ +#define PCI_DEVICE_ID_ATI_RADEON_RA 0x5144 +#define PCI_DEVICE_ID_ATI_RADEON_RB 0x5145 +#define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 +#define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +/* RadeonIGP */ +#define PCI_DEVICE_ID_ATI_RS100 0xcab0 +#define PCI_DEVICE_ID_ATI_RS200 0xcab2 +#define PCI_DEVICE_ID_ATI_RS200_B 0xcbb2 +#define PCI_DEVICE_ID_ATI_RS250 0xcab3 +#define PCI_DEVICE_ID_ATI_RS300_100 0x5830 +#define PCI_DEVICE_ID_ATI_RS300_133 0x5831 +#define PCI_DEVICE_ID_ATI_RS300_166 0x5832 +#define PCI_DEVICE_ID_ATI_RS300_200 0x5833 +#define PCI_DEVICE_ID_ATI_RS350_100 0x7830 +#define PCI_DEVICE_ID_ATI_RS350_133 0x7831 +#define PCI_DEVICE_ID_ATI_RS350_166 0x7832 +#define PCI_DEVICE_ID_ATI_RS350_200 0x7833 +#define PCI_DEVICE_ID_ATI_RS400_100 0x5a30 +#define PCI_DEVICE_ID_ATI_RS400_133 0x5a31 +#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 +#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 +#define PCI_DEVICE_ID_ATI_RS480 0x5950 +/* ATI IXP Chipset */ +#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 +#define PCI_DEVICE_ID_ATI_IXP300_IDE 0x4369 +#define PCI_DEVICE_ID_ATI_IXP300_SATA 0x436e +#define PCI_DEVICE_ID_ATI_IXP400_IDE 0x4376 +#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87560_LIO 0x000e +#define PCI_DEVICE_ID_NS_87560_USB 0x0012 +#define PCI_DEVICE_ID_NS_83815 0x0020 +#define PCI_DEVICE_ID_NS_83820 0x0022 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510 +#define PCI_DEVICE_ID_NS_SC1100_SMI 0x0511 +#define PCI_DEVICE_ID_NS_SC1100_XBUS 0x0515 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_PYTHON 0x002d +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096 +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc +#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105 +#define PCI_DEVICE_ID_IBM_405GP 0x0156 +#define PCI_DEVICE_ID_IBM_SNIPE 0x0180 +#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd +#define PCI_DEVICE_ID_IBM_CITRINE 0x028C +#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166 +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031 +#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 +#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A +#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 +#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 + +#define PCI_VENDOR_ID_COMPEX2 0x101a // pci.ids says "AT&T GIS (NCR)" +#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 +#define PCI_DEVICE_ID_WD_90C 0xc24a + +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 +#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 +#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C +#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E +#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F +#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 +#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 +#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 +#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440 +# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440 +#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 +# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441 +#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 +# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 +#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445 +#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448 +# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448 +#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449 +# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449 +#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462 +#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a +#define PCI_DEVICE_ID_AMD_8111_SMBUS 0x746b +#define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d +#define PCI_DEVICE_ID_AMD_8151_0 0x7454 +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_DEVICE_ID_DELL_RACIII 0x0008 +#define PCI_DEVICE_ID_DELL_RAC4 0x0012 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_G550 0x2527 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_69000 0x00c0 +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 +#define PCI_DEVICE_ID_MIRO_DC10PLUS 0x7efe +#define PCI_DEVICE_ID_MIRO_DC30PLUS 0xd801 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_CBUS_1 0x0001 /* PCI-Cbus Bridge */ +#define PCI_DEVICE_ID_NEC_LOCAL 0x0002 /* Local Bridge */ +#define PCI_DEVICE_ID_NEC_ATM 0x0003 /* ATM LAN Controller */ +#define PCI_DEVICE_ID_NEC_R4000 0x0004 /* R4000 Bridge */ +#define PCI_DEVICE_ID_NEC_486 0x0005 /* 486 Like Peripheral Bus Bridge */ +#define PCI_DEVICE_ID_NEC_ACCEL_1 0x0006 /* Graphic Accelerator */ +#define PCI_DEVICE_ID_NEC_UXBUS 0x0007 /* UX-Bus Bridge */ +#define PCI_DEVICE_ID_NEC_ACCEL_2 0x0008 /* Graphic Accelerator */ +#define PCI_DEVICE_ID_NEC_GRAPH 0x0009 /* PCI-CoreGraph Bridge */ +#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */ +#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */ +#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */ +#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */ +#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b +#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ +#define PCI_DEVICE_ID_NEC_NILE4 0x005a +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 +#define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */ +#define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */ + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_SMBUS 0x0016 +#define PCI_DEVICE_ID_SI_LPC 0x0018 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_300 0x0300 +#define PCI_DEVICE_ID_SI_315H 0x0310 +#define PCI_DEVICE_ID_SI_315 0x0315 +#define PCI_DEVICE_ID_SI_315PRO 0x0325 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_540 0x0540 +#define PCI_DEVICE_ID_SI_550 0x0550 +#define PCI_DEVICE_ID_SI_540_VGA 0x5300 +#define PCI_DEVICE_ID_SI_550_VGA 0x5315 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_630 0x0630 +#define PCI_DEVICE_ID_SI_633 0x0633 +#define PCI_DEVICE_ID_SI_635 0x0635 +#define PCI_DEVICE_ID_SI_640 0x0640 +#define PCI_DEVICE_ID_SI_645 0x0645 +#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_648 0x0648 +#define PCI_DEVICE_ID_SI_650 0x0650 +#define PCI_DEVICE_ID_SI_651 0x0651 +#define PCI_DEVICE_ID_SI_652 0x0652 +#define PCI_DEVICE_ID_SI_655 0x0655 +#define PCI_DEVICE_ID_SI_661 0x0661 +#define PCI_DEVICE_ID_SI_730 0x0730 +#define PCI_DEVICE_ID_SI_733 0x0733 +#define PCI_DEVICE_ID_SI_630_VGA 0x6300 +#define PCI_DEVICE_ID_SI_730_VGA 0x7300 +#define PCI_DEVICE_ID_SI_735 0x0735 +#define PCI_DEVICE_ID_SI_740 0x0740 +#define PCI_DEVICE_ID_SI_741 0x0741 +#define PCI_DEVICE_ID_SI_745 0x0745 +#define PCI_DEVICE_ID_SI_746 0x0746 +#define PCI_DEVICE_ID_SI_748 0x0748 +#define PCI_DEVICE_ID_SI_750 0x0750 +#define PCI_DEVICE_ID_SI_751 0x0751 +#define PCI_DEVICE_ID_SI_752 0x0752 +#define PCI_DEVICE_ID_SI_755 0x0755 +#define PCI_DEVICE_ID_SI_760 0x0760 +#define PCI_DEVICE_ID_SI_900 0x0900 +#define PCI_DEVICE_ID_SI_961 0x0961 +#define PCI_DEVICE_ID_SI_962 0x0962 +#define PCI_DEVICE_ID_SI_963 0x0963 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5300 0x5300 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5518 0x5518 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5581 0x5581 +#define PCI_DEVICE_ID_SI_5582 0x5582 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5596 0x5596 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5598 0x5598 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_6300 0x6300 +#define PCI_DEVICE_ID_SI_6306 0x6306 +#define PCI_DEVICE_ID_SI_6326 0x6326 +#define PCI_DEVICE_ID_SI_7001 0x7001 +#define PCI_DEVICE_ID_SI_7012 0x7012 +#define PCI_DEVICE_ID_SI_7016 0x7016 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 +#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a +#define PCI_DEVICE_ID_HP_TACHYON 0x1028 +#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 +#define PCI_DEVICE_ID_HP_J2973A 0x1040 +#define PCI_DEVICE_ID_HP_J2970A 0x1042 +#define PCI_DEVICE_ID_HP_DIVA 0x1048 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A +#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B +#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054 +#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0 +#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 +#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b +#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 +#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 +#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 +#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229 +#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a +#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e +#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c +#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 +#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 +#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 +#define PCI_DEVICE_ID_HP_CISSA 0x3220 +#define PCI_DEVICE_ID_HP_CISSB 0x3230 +#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C861 0xc861 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 +#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_4450 0x8011 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#define PCI_DEVICE_ID_TI_1250 0xac16 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#define PCI_DEVICE_ID_TI_1450 0xac1b +#define PCI_DEVICE_ID_TI_1225 0xac1c +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#define PCI_DEVICE_ID_TI_1211 0xac1e +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#define PCI_DEVICE_ID_TI_4410 0xac41 +#define PCI_DEVICE_ID_TI_4451 0xac42 +#define PCI_DEVICE_ID_TI_4510 0xac44 +#define PCI_DEVICE_ID_TI_4520 0xac46 +#define PCI_DEVICE_ID_TI_1410 0xac50 +#define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1451A 0xac52 +#define PCI_DEVICE_ID_TI_1620 0xac54 +#define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 + +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_DEVICE_ID_SONY_CXD3222 0x8039 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a +#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 + +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 + +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 +#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 +#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b +#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 +#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 +#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 +#define PCI_DEVICE_ID_PROMISE_20268R 0x6268 +#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 +#define PCI_DEVICE_ID_PROMISE_20270 0x6268 +#define PCI_DEVICE_ID_PROMISE_20271 0x6269 +#define PCI_DEVICE_ID_PROMISE_20275 0x1275 +#define PCI_DEVICE_ID_PROMISE_20276 0x5275 +#define PCI_DEVICE_ID_PROMISE_20277 0x7275 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 +#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 +#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 +#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d +#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 +#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA 0x0033 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 +#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b +#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e +#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043 +#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b +#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c +#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050 +#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051 +#define PCI_DEVICE_ID_APPLE_SH_FW 0x0052 +#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058 +#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059 +#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 + +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_DEVICE_ID_YAMAHA_724 0x0004 +#define PCI_DEVICE_ID_YAMAHA_724F 0x000d +#define PCI_DEVICE_ID_YAMAHA_740 0x000a +#define PCI_DEVICE_ID_YAMAHA_740C 0x000c +#define PCI_DEVICE_ID_YAMAHA_744 0x0010 +#define PCI_DEVICE_ID_YAMAHA_754 0x0012 + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 +#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 +#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 +#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 +#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 +#define PCI_DEVICE_ID_SUN_GEM 0x2bad +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 +#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 +#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_648 0x0648 +#define PCI_DEVICE_ID_CMD_649 0x0649 +#define PCI_DEVICE_ID_CMD_670 0x0670 +#define PCI_DEVICE_ID_CMD_680 0x0680 + +#define PCI_DEVICE_ID_SII_680 0x0680 +#define PCI_DEVICE_ID_SII_3112 0x3112 +#define PCI_DEVICE_ID_SII_1210SA 0x0240 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_IOC4 0x100a +#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_R685 0x1030 +#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a +#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 +#define PCI_DEVICE_ID_PLX_1077 0x1077 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 +#define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_9030 0x9030 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C940 0x1700 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C359 0x3590 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C940B 0x80eb +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 +#define PCI_DEVICE_ID_3COM_3CR990 0x9900 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 +#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 +#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 +#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1535 0x1535 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1543 0x1543 +#define PCI_DEVICE_ID_AL_M1563 0x1563 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1632 0x1632 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1671 0x1671 +#define PCI_DEVICE_ID_AL_M1681 0x1681 +#define PCI_DEVICE_ID_AL_M1683 0x1683 +#define PCI_DEVICE_ID_AL_M1689 0x1689 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5228 0x5228 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M5243 0x5243 +#define PCI_DEVICE_ID_AL_M5451 0x5451 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN 0x002a +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036 +#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037 +#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2 0x003e +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800 0x0041 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE 0x0042 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x0045 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000 0x004E +#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS 0x0052 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2 0x0055 +#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056 +#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057 +#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS 0x0064 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 +#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066 +#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS 0x0084 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 +#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086 +#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 +#define PCI_DEVICE_ID_GEFORCE_6800A 0x00c1 +#define PCI_DEVICE_ID_GEFORCE_6800A_LE 0x00c2 +#define PCI_DEVICE_ID_GEFORCE_GO_6800 0x00c8 +#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA 0x00c9 +#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc +#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce +#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 +#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 +#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 +#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da +#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS 0x00e4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT 0x0140 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600 0x0141 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL 0x0145 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540 0x014E +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200 0x014F +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200 0x0164 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250 0x0166 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1 0x0167 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1 0x0168 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE 0x0173 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO 0x0177 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC 0x0189 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 +#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS 0x01b4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc +#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B 0x0211 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE 0x0212 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT 0x0215 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267 +#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 +#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 +#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO 0x026B +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO 0x0286 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL 0x0288 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL 0x0289 +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL 0x028C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA 0x0301 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA 0x0311 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA 0x0321 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1 0x0322 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500 0x0326 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100 0x0327 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32 0x0328 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200 0x0329 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA 0x0330 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA 0x0333 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT 0x0334 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700 0x033F +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA 0x0341 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1 0x0347 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2 0x0348 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 +#define PCI_DEVICE_ID_IMS_TT128 0x9128 +#define PCI_DEVICE_ID_IMS_TT3D 0x9135 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 +#define PCI_DEVICE_ID_INTERG_2010 0x2010 +#define PCI_DEVICE_ID_INTERG_5000 0x5000 +#define PCI_DEVICE_ID_INTERG_5050 0x5050 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8169 0x8169 + +#define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_DEVICE_ID_TURBOPAM 0x4020 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_CREATIVE 0x1102 // duplicate: ECTIVA +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 + +#define PCI_VENDOR_ID_ECTIVA 0x1102 // duplicate: CREATIVE +#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 +#define PCI_DEVICE_ID_TTI_HPT372 0x0005 +#define PCI_DEVICE_ID_TTI_HPT302 0x0006 +#define PCI_DEVICE_ID_TTI_HPT371 0x0007 +#define PCI_DEVICE_ID_TTI_HPT374 0x0008 +#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 // apparently a 372N variant? + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8763_0 0x0198 +#define PCI_DEVICE_ID_VIA_8380_0 0x0204 +#define PCI_DEVICE_ID_VIA_3238_0 0x0238 +#define PCI_DEVICE_ID_VIA_PT880 0x0258 +#define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 +#define PCI_DEVICE_ID_VIA_3269_0 0x0269 +#define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 +#define PCI_DEVICE_ID_VIA_8363_0 0x0305 +#define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_8601_0 0x0601 +#define PCI_DEVICE_ID_VIA_8605_0 0x0605 +#define PCI_DEVICE_ID_VIA_82C680 0x0680 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691_0 0x0691 +#define PCI_DEVICE_ID_VIA_82C693 0x0693 +#define PCI_DEVICE_ID_VIA_82C693_1 0x0698 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_6305 0x3044 +#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 +#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_8233_5 0x3059 +#define PCI_DEVICE_ID_VIA_8233_7 0x3065 +#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 +#define PCI_DEVICE_ID_VIA_8233_0 0x3074 +#define PCI_DEVICE_ID_VIA_8633_0 0x3091 +#define PCI_DEVICE_ID_VIA_8367_0 0x3099 +#define PCI_DEVICE_ID_VIA_8653_0 0x3101 +#define PCI_DEVICE_ID_VIA_8622 0x3102 +#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 +#define PCI_DEVICE_ID_VIA_8361 0x3112 +#define PCI_DEVICE_ID_VIA_XM266 0x3116 +#define PCI_DEVICE_ID_VIA_612X 0x3119 +#define PCI_DEVICE_ID_VIA_862X_0 0x3123 +#define PCI_DEVICE_ID_VIA_8753_0 0x3128 +#define PCI_DEVICE_ID_VIA_8233A 0x3147 +#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148 +#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_XN266 0x3156 +#define PCI_DEVICE_ID_VIA_8754C_0 0x3168 +#define PCI_DEVICE_ID_VIA_8235 0x3177 +#define PCI_DEVICE_ID_VIA_P4N333 0x3178 +#define PCI_DEVICE_ID_VIA_8385_0 0x3188 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 +#define PCI_DEVICE_ID_VIA_8378_0 0x3205 +#define PCI_DEVICE_ID_VIA_8783_0 0x3208 +#define PCI_DEVICE_ID_VIA_P4M400 0x3209 +#define PCI_DEVICE_ID_VIA_8237 0x3227 +#define PCI_DEVICE_ID_VIA_3296_0 0x0296 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_8231 0x8231 +#define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8365_1 0x8305 +#define PCI_DEVICE_ID_VIA_8371_1 0x8391 +#define PCI_DEVICE_ID_VIA_8501_1 0x8501 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 +#define PCI_DEVICE_ID_VIA_8601_1 0x8601 +#define PCI_DEVICE_ID_VIA_8505_1 0x8605 +#define PCI_DEVICE_ID_VIA_8633_1 0xB091 +#define PCI_DEVICE_ID_VIA_8367_1 0xB099 +#define PCI_DEVICE_ID_VIA_P4X266_1 0xB101 +#define PCI_DEVICE_ID_VIA_8615_1 0xB103 +#define PCI_DEVICE_ID_VIA_8361_1 0xB112 +#define PCI_DEVICE_ID_VIA_8235_1 0xB168 +#define PCI_DEVICE_ID_VIA_838X_1 0xB188 +#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 + +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 + +#define PCI_VENDOR_ID_SMC2 0x1113 +#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 +#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 +#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 + +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 +#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 + +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001 +#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 +#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003 +#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 +#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 +#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b +#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 +#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 +#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 + +#define PCI_VENDOR_ID_ZIATECH 0x1138 +#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 +#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 +#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 +#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 +#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 +#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 +#define PCI_DEVICE_ID_NEO_2DB9 0x00C8 +#define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9 +#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA +#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_XIRCOM 0x115d +#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003 +#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 +#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 +#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB +#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 + +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 +#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 +#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f +#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617 + +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180 +#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 +#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 +#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 +#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 +#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 +#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 +#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 +#define PCI_DEVICE_ID_ARTOP_8060 0x8060 +#define PCI_DEVICE_ID_ARTOP_AEC67160 0x8080 +#define PCI_DEVICE_ID_ARTOP_AEC67160_2 0x8081 +#define PCI_DEVICE_ID_ARTOP_AEC67162 0x808a + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_VENDOR_ID_FUJITSU_ME 0x119e +#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 +#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_DEVICE_ID_MARVELL_GT64011 0x4146 +#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 +#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 +#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 +#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 +#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652 +#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V961 0x0002 +#define PCI_DEVICE_ID_V3_V351 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 + +#define PCI_VENDOR_ID_NEC2 0x11c3 /* NEC (2nd) */ + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 +#define PCI_DEVICE_ID_AD1889JS 0x1889 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_SEGA 0x11db +#define PCI_DEVICE_ID_SEGA_BBA 0x1234 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RP4J 0x0007 +#define PCI_DEVICE_ID_RP8SNI 0x0008 +#define PCI_DEVICE_ID_RP16SNI 0x0009 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C +#define PCI_DEVICE_ID_RP4M 0x000D +#define PCI_DEVICE_ID_RP2_232 0x000E +#define PCI_DEVICE_ID_RP2_422 0x000F +#define PCI_DEVICE_ID_URP32INTF 0x0801 +#define PCI_DEVICE_ID_URP8INTF 0x0802 +#define PCI_DEVICE_ID_URP16INTF 0x0803 +#define PCI_DEVICE_ID_URP8OCTA 0x0805 +#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C +#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D +#define PCI_DEVICE_ID_CRP16INTF 0x0903 + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 +#define PCI_DEVICE_ID_PC300_RX_2 0x0300 +#define PCI_DEVICE_ID_PC300_RX_1 0x0301 +#define PCI_DEVICE_ID_PC300_TE_2 0x0310 +#define PCI_DEVICE_ID_PC300_TE_1 0x0311 +#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320 +#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321 + +/* Allied Telesyn */ +#define PCI_VENDOR_ID_AT 0x1259 +#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 +#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_B1 0x0700 +#define PCI_DEVICE_ID_AVM_C4 0x0800 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 +#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 +#define PCI_DEVICE_ID_AVM_C2 0x1100 +#define PCI_DEVICE_ID_AVM_T1 0x1200 + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +/* Allied Telesyn */ +#define PCI_VENDOR_ID_AT 0x1259 +#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701 +#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 +#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 +#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 +#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_TRANSMETA 0x1279 +#define PCI_DEVICE_ID_EFFICEON 0x0060 + +#define PCI_VENDOR_ID_ROCKWELL 0x127A + +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 +#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 +#define PCI_DEVICE_ID_ITE_8872 0x8872 +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 + +/* formerly Platform Tech */ +#define PCI_VENDOR_ID_ESS_OLD 0x1285 +#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_USR 0x12B9 + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 + +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 +#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003 + +#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 +#define PCI_DEVICE_ID_LML_33R10 0x8a02 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 +#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 +#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 +#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 +#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 +#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 +#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 +#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 +#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 +#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 +#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 +#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 +#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 +#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 + +#define PCI_VENDOR_ID_RADISYS 0x1331 +#define PCI_DEVICE_ID_RADISYS_ENP2611 0x0030 + +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 + +#define PCI_VENDOR_ID_QUATECH 0x135C +#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 +#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 +#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 +#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804 + +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 +#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109 + +#define PCI_VENDOR_ID_KAWASAKI 0x136b +#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 + +#define PCI_VENDOR_ID_CNET 0x1371 +#define PCI_DEVICE_ID_CNET_GIGACARD 0x434e + +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_DEVICE_ID_LMC_HSSI 0x0003 +#define PCI_DEVICE_ID_LMC_DS3 0x0004 +#define PCI_DEVICE_ID_LMC_SSI 0x0005 +#define PCI_DEVICE_ID_LMC_T1 0x0006 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a +#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a + +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 + +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_DEVICE_ID_MOXA_RC7000 0x0001 +#define PCI_DEVICE_ID_MOXA_CP102 0x1020 +#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 +#define PCI_DEVICE_ID_MOXA_CP102U 0x1022 +#define PCI_DEVICE_ID_MOXA_C104 0x1040 +#define PCI_DEVICE_ID_MOXA_CP104U 0x1041 +#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 +#define PCI_DEVICE_ID_MOXA_CT114 0x1140 +#define PCI_DEVICE_ID_MOXA_CP114 0x1141 +#define PCI_DEVICE_ID_MOXA_CP118U 0x1180 +#define PCI_DEVICE_ID_MOXA_CP132 0x1320 +#define PCI_DEVICE_ID_MOXA_CP132U 0x1321 +#define PCI_DEVICE_ID_MOXA_CP134U 0x1340 +#define PCI_DEVICE_ID_MOXA_C168 0x1680 +#define PCI_DEVICE_ID_MOXA_CP168U 0x1681 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 + +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_B000 0xb000 +#define PCI_DEVICE_ID_CCD_B006 0xb006 +#define PCI_DEVICE_ID_CCD_B007 0xb007 +#define PCI_DEVICE_ID_CCD_B008 0xb008 +#define PCI_DEVICE_ID_CCD_B009 0xb009 +#define PCI_DEVICE_ID_CCD_B00A 0xb00a +#define PCI_DEVICE_ID_CCD_B00B 0xb00b +#define PCI_DEVICE_ID_CCD_B00C 0xb00c +#define PCI_DEVICE_ID_CCD_B100 0xb100 + +#define PCI_VENDOR_ID_EXAR 0x13a8 +#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 +#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 +#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 + +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 +#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 +#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 +#define PCI_DEVICE_ID_MICROGATE_USC2 0x0210 + +#define PCI_VENDOR_ID_3WARE 0x13C1 +#define PCI_DEVICE_ID_3WARE_1000 0x1000 +#define PCI_DEVICE_ID_3WARE_7000 0x1001 +#define PCI_DEVICE_ID_3WARE_9000 0x1002 + +#define PCI_VENDOR_ID_IOMEGA 0x13ca +#define PCI_DEVICE_ID_IOMEGA_BUZ 0x4231 + +#define PCI_VENDOR_ID_ABOCOM 0x13D1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 + +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 +#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 +#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 +#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ +#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ +#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ +#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 + +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 + +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 +#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 +#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 +#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 +#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 + +#define PCI_VENDOR_ID_SAMSUNG 0x144d + +#define PCI_VENDOR_ID_AIRONET 0x14b9 +#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001 +#define PCI_DEVICE_ID_AIRONET_4800 0x4500 // values switched? see +#define PCI_DEVICE_ID_AIRONET_4500 0x4800 // drivers/net/aironet4500_card.c + +#define PCI_VENDOR_ID_TITAN 0x14D2 +#define PCI_DEVICE_ID_TITAN_010L 0x8001 +#define PCI_DEVICE_ID_TITAN_100L 0x8010 +#define PCI_DEVICE_ID_TITAN_110L 0x8011 +#define PCI_DEVICE_ID_TITAN_200L 0x8020 +#define PCI_DEVICE_ID_TITAN_210L 0x8021 +#define PCI_DEVICE_ID_TITAN_400L 0x8040 +#define PCI_DEVICE_ID_TITAN_800L 0x8080 +#define PCI_DEVICE_ID_TITAN_100 0xA001 +#define PCI_DEVICE_ID_TITAN_200 0xA005 +#define PCI_DEVICE_ID_TITAN_400 0xA003 +#define PCI_DEVICE_ID_TITAN_800B 0xA004 + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_DEVICE_ID_SP_HT 0x0010 + +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 +#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 + +#define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_DEVICE_ID_TIGON3_5752 0x1600 +#define PCI_DEVICE_ID_TIGON3_5752M 0x1601 +#define PCI_DEVICE_ID_TIGON3_5700 0x1644 +#define PCI_DEVICE_ID_TIGON3_5701 0x1645 +#define PCI_DEVICE_ID_TIGON3_5702 0x1646 +#define PCI_DEVICE_ID_TIGON3_5703 0x1647 +#define PCI_DEVICE_ID_TIGON3_5704 0x1648 +#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 +#define PCI_DEVICE_ID_NX2_5706 0x164a +#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d +#define PCI_DEVICE_ID_TIGON3_5705 0x1653 +#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5720 0x1658 +#define PCI_DEVICE_ID_TIGON3_5721 0x1659 +#define PCI_DEVICE_ID_TIGON3_5705M 0x165d +#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_TIGON3_5750 0x1676 +#define PCI_DEVICE_ID_TIGON3_5751 0x1677 +#define PCI_DEVICE_ID_TIGON3_5750M 0x167c +#define PCI_DEVICE_ID_TIGON3_5751M 0x167d +#define PCI_DEVICE_ID_TIGON3_5751F 0x167e +#define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5788 0x169c +#define PCI_DEVICE_ID_TIGON3_5789 0x169d +#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 +#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 +#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_NX2_5706S 0x16aa +#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 +#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 +#define PCI_DEVICE_ID_TIGON3_5781 0x16dd +#define PCI_DEVICE_ID_TIGON3_5753 0x16f7 +#define PCI_DEVICE_ID_TIGON3_5753M 0x16fd +#define PCI_DEVICE_ID_TIGON3_5753F 0x16fe +#define PCI_DEVICE_ID_TIGON3_5901 0x170d +#define PCI_DEVICE_ID_BCM4401B1 0x170c +#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e +#define PCI_DEVICE_ID_BCM4401 0x4401 +#define PCI_DEVICE_ID_BCM4401B0 0x4402 + +#define PCI_VENDOR_ID_TOPIC 0x151f +#define PCI_DEVICE_ID_TOPIC_TP560 0x0000 + +#define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_1211 0x1211 +#define PCI_DEVICE_ID_ENE_1225 0x1225 +#define PCI_DEVICE_ID_ENE_1410 0x1410 +#define PCI_DEVICE_ID_ENE_1420 0x1420 + +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 +#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 + +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 + +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 + +#define PCI_VENDOR_ID_MELLANOX 0x15b3 +#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 +#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 +#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 +#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c +#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 + +#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_DEVICE_ID_PDC_1841 0x1841 + +#define PCI_VENDOR_ID_MACROLINK 0x15ed +#define PCI_DEVICE_ID_MACROLINK_MCCS8 0x1000 +#define PCI_DEVICE_ID_MACROLINK_MCCS 0x1001 +#define PCI_DEVICE_ID_MACROLINK_MCCS8H 0x1002 +#define PCI_DEVICE_ID_MACROLINK_MCCSH 0x1003 +#define PCI_DEVICE_ID_MACROLINK_MCCR8 0x2000 +#define PCI_DEVICE_ID_MACROLINK_MCCR 0x2001 + +#define PCI_VENDOR_ID_FARSITE 0x1619 +#define PCI_DEVICE_ID_FARSITE_T2P 0x0400 +#define PCI_DEVICE_ID_FARSITE_T4P 0x0440 +#define PCI_DEVICE_ID_FARSITE_T1U 0x0610 +#define PCI_DEVICE_ID_FARSITE_T2U 0x0620 +#define PCI_DEVICE_ID_FARSITE_T4U 0x0640 +#define PCI_DEVICE_ID_FARSITE_TE1 0x1610 +#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 + +#define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_DEVICE_ID_BCM1250_HT 0x0002 + +#define PCI_VENDOR_ID_LINKSYS 0x1737 +#define PCI_DEVICE_ID_LINKSYS_EG1032 0x1032 +#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 + +#define PCI_VENDOR_ID_ALTIMA 0x173b +#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 +#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 +#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb + +#define PCI_VENDOR_ID_S2IO 0x17d5 +#define PCI_DEVICE_ID_S2IO_WIN 0x5731 +#define PCI_DEVICE_ID_S2IO_UNI 0x5831 +#define PCI_DEVICE_ID_HERC_WIN 0x5732 +#define PCI_DEVICE_ID_HERC_UNI 0x5832 + +#define PCI_VENDOR_ID_INFINICON 0x1820 + +#define PCI_VENDOR_ID_TOPSPIN 0x1867 + +#define PCI_VENDOR_ID_TDI 0x192E +#define PCI_DEVICE_ID_TDI_EHCI 0x0101 + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 +#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_AKS 0x416c +#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 +#define PCI_DEVICE_ID_AKS_CPC 0x0200 + +#define PCI_VENDOR_ID_REDCREEK 0x4916 +#define PCI_DEVICE_ID_RC45 0x1960 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 +#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 + +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 + +#define PCI_VENDOR_ID_GENROCO 0x5555 +#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 +#define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_82562ET 0x1031 +#define PCI_DEVICE_ID_INTEL_82801CAM 0x1038 +#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 +#define PCI_DEVICE_ID_INTEL_82815_AB 0x1131 +#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 +#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 +#define PCI_DEVICE_ID_INTEL_7505_1 0x2552 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 +#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 +#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 +#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 +#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412 +#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 +#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 +#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 +#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 +#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 +#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422 +#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 +#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 +#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 +#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 +#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442 +#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444 +#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 +#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446 +#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 +#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449 +#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a +#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b +#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 +#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452 +#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453 +#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459 +#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b +#define PCI_DEVICE_ID_INTEL_82801E_13 0x245d +#define PCI_DEVICE_ID_INTEL_82801E_14 0x245e +#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 +#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 +#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 +#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484 +#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 +#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 +#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487 +#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a +#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b +#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c +#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 +#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1 +#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2 +#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 +#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4 +#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 +#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 +#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7 +#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb +#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc +#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd +#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 +#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 +#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2 +#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 +#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4 +#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 +#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 +#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7 +#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd +#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 +#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 +#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3 +#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0 +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 +#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 +#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7 +#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9 +#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab +#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac +#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad +#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae +#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500 +#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501 +#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 +#define PCI_DEVICE_ID_INTEL_82860_HB 0x2531 +#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 +#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 +#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570 +#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 +#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578 +#define PCI_DEVICE_ID_INTEL_82875_IG 0x257b +#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580 +#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 +#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 +#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 +#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 +#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 +#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 +#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 +#define PCI_DEVICE_ID_INTEL_ICH6_3 0x2651 +#define PCI_DEVICE_ID_INTEL_ICH6_4 0x2652 +#define PCI_DEVICE_ID_INTEL_ICH6_5 0x2653 +#define PCI_DEVICE_ID_INTEL_ICH6_6 0x2658 +#define PCI_DEVICE_ID_INTEL_ICH6_7 0x2659 +#define PCI_DEVICE_ID_INTEL_ICH6_8 0x265a +#define PCI_DEVICE_ID_INTEL_ICH6_9 0x265b +#define PCI_DEVICE_ID_INTEL_ICH6_10 0x265c +#define PCI_DEVICE_ID_INTEL_ICH6_11 0x2660 +#define PCI_DEVICE_ID_INTEL_ICH6_12 0x2662 +#define PCI_DEVICE_ID_INTEL_ICH6_13 0x2664 +#define PCI_DEVICE_ID_INTEL_ICH6_14 0x2666 +#define PCI_DEVICE_ID_INTEL_ICH6_15 0x2668 +#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a +#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d +#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e +#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f +#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670 +#define PCI_DEVICE_ID_INTEL_ESB2_1 0x2680 +#define PCI_DEVICE_ID_INTEL_ESB2_2 0x2681 +#define PCI_DEVICE_ID_INTEL_ESB2_3 0x2682 +#define PCI_DEVICE_ID_INTEL_ESB2_4 0x2683 +#define PCI_DEVICE_ID_INTEL_ESB2_5 0x2688 +#define PCI_DEVICE_ID_INTEL_ESB2_6 0x2689 +#define PCI_DEVICE_ID_INTEL_ESB2_7 0x268a +#define PCI_DEVICE_ID_INTEL_ESB2_8 0x268b +#define PCI_DEVICE_ID_INTEL_ESB2_9 0x268c +#define PCI_DEVICE_ID_INTEL_ESB2_10 0x2690 +#define PCI_DEVICE_ID_INTEL_ESB2_11 0x2692 +#define PCI_DEVICE_ID_INTEL_ESB2_12 0x2694 +#define PCI_DEVICE_ID_INTEL_ESB2_13 0x2696 +#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 +#define PCI_DEVICE_ID_INTEL_ESB2_15 0x2699 +#define PCI_DEVICE_ID_INTEL_ESB2_16 0x269a +#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b +#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e +#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0 +#define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1 +#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4 +#define PCI_DEVICE_ID_INTEL_ICH7_6 0x27c5 +#define PCI_DEVICE_ID_INTEL_ICH7_7 0x27c8 +#define PCI_DEVICE_ID_INTEL_ICH7_8 0x27c9 +#define PCI_DEVICE_ID_INTEL_ICH7_9 0x27ca +#define PCI_DEVICE_ID_INTEL_ICH7_10 0x27cb +#define PCI_DEVICE_ID_INTEL_ICH7_11 0x27cc +#define PCI_DEVICE_ID_INTEL_ICH7_12 0x27d0 +#define PCI_DEVICE_ID_INTEL_ICH7_13 0x27d2 +#define PCI_DEVICE_ID_INTEL_ICH7_14 0x27d4 +#define PCI_DEVICE_ID_INTEL_ICH7_15 0x27d6 +#define PCI_DEVICE_ID_INTEL_ICH7_16 0x27d8 +#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da +#define PCI_DEVICE_ID_INTEL_ICH7_18 0x27dc +#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd +#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de +#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df +#define PCI_DEVICE_ID_INTEL_ICH7_22 0x27e0 +#define PCI_DEVICE_ID_INTEL_ICH7_23 0x27e2 +#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 +#define PCI_DEVICE_ID_INTEL_ESB2_19 0x3500 +#define PCI_DEVICE_ID_INTEL_ESB2_20 0x3501 +#define PCI_DEVICE_ID_INTEL_ESB2_21 0x3504 +#define PCI_DEVICE_ID_INTEL_ESB2_22 0x3505 +#define PCI_DEVICE_ID_INTEL_ESB2_23 0x350c +#define PCI_DEVICE_ID_INTEL_ESB2_24 0x350d +#define PCI_DEVICE_ID_INTEL_ESB2_25 0x3510 +#define PCI_DEVICE_ID_INTEL_ESB2_26 0x3511 +#define PCI_DEVICE_ID_INTEL_ESB2_27 0x3514 +#define PCI_DEVICE_ID_INTEL_ESB2_28 0x3515 +#define PCI_DEVICE_ID_INTEL_ESB2_29 0x3518 +#define PCI_DEVICE_ID_INTEL_ESB2_30 0x3519 +#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 +#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 +#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 +#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 +#define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590 +#define PCI_DEVICE_ID_INTEL_E7320_MCH 0x3592 +#define PCI_DEVICE_ID_INTEL_MCH_PA 0x3595 +#define PCI_DEVICE_ID_INTEL_MCH_PA1 0x3596 +#define PCI_DEVICE_ID_INTEL_MCH_PB 0x3597 +#define PCI_DEVICE_ID_INTEL_MCH_PB1 0x3598 +#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 +#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a +#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e +#define PCI_DEVICE_ID_INTEL_80310 0x530d +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 +#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 +#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 +#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 +#define PCI_DEVICE_ID_INTEL_82810E_IG 0x7125 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_440MX 0x7195 +#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 +#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 +#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a +#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b +#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 +#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 +#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 +#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600 +#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602 +#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603 +#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb +#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea +#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 +#define PCI_DEVICE_ID_INTEL_IXP2400 0x9001 +#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 + +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 +#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 +#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf +#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_NETMOS 0x9710 +#define PCI_DEVICE_ID_NETMOS_9705 0x9705 +#define PCI_DEVICE_ID_NETMOS_9715 0x9715 +#define PCI_DEVICE_ID_NETMOS_9735 0x9735 +#define PCI_DEVICE_ID_NETMOS_9745 0x9745 +#define PCI_DEVICE_ID_NETMOS_9755 0x9755 +#define PCI_DEVICE_ID_NETMOS_9805 0x9805 +#define PCI_DEVICE_ID_NETMOS_9815 0x9815 +#define PCI_DEVICE_ID_NETMOS_9835 0x9835 +#define PCI_DEVICE_ID_NETMOS_9845 0x9845 +#define PCI_DEVICE_ID_NETMOS_9855 0x9855 + +#define PCI_SUBVENDOR_ID_EXSYS 0xd84d +#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 +#define PCI_DEVICE_ID_TIGERJET_100 0x0002 + +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_DEVICE_ID_TTTECH_MC322 0x000A + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h new file mode 100644 index 0000000..5788130 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h @@ -0,0 +1,342 @@ +/* TOS 4.04 Xbios PCI for the CT60 board +* Didier Mequignon 2005, e-mail: aniplay@wanadoo.fr +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2.1 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _OHCI_PCI_PCIXBIOS_H +#define _OHCI_PCI_PCIXBIOS_H + +#define PCIIDR 0x00 /* PCI Configuration ID Register */ +#define PCICSR 0x04 /* PCI Command/Status Register */ +#define PCICR 0x04 /* PCI Command Register */ +#define PCISR 0x06 /* PCI Status Register */ +#define PCIREV 0x08 /* PCI Revision ID Register */ +#define PCICCR 0x09 /* PCI Class Code Register */ +#define PCICLSR 0x0C /* PCI Cache Line Size Register */ +#define PCILTR 0x0D /* PCI Latency Timer Register */ +#define PCIHTR 0x0E /* PCI Header Type Register */ +#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */ +#define PCIBAR0 0x10 /* PCI Base Address Register for Memory + Accesses to Local, Runtime, and DMA */ +#define PCIBAR1 0x14 /* PCI Base Address Register for I/O + Accesses to Local, Runtime, and DMA */ +#define PCIBAR2 0x18 /* PCI Base Address Register for Memory + Accesses to Local Address Space 0 */ +#define PCIBAR3 0x1C /* PCI Base Address Register for Memory + Accesses to Local Address Space 1 */ +#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */ +#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */ +#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/ +#define PCISVID 0x2C /* PCI Subsystem Vendor ID */ +#define PCISID 0x2E /* PCI Subsystem ID */ +#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */ +#define CAP_PTR 0x34 /* New Capability Pointer */ +#define PCIILR 0x3C /* PCI Interrupt Line Register */ +#define PCIIPR 0x3D /* PCI Interrupt Pin Register */ +#define PCIMGR 0x3E /* PCI Min_Gnt Register */ +#define PCIMLR 0x3F /* PCI Max_Lat Register */ +#define PMCAPID 0x40 /* Power Management Capability ID */ +#define PMNEXT 0x41 /* Power Management Next Capability + Pointer */ +#define PMC 0x42 /* Power Management Capabilities */ +#define PMCSR 0x44 /* Power Management Control/Status */ +#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */ +#define PMDATA 0x47 /* Power Management Data */ +#define HS_CNTL 0x48 /* Hot Swap Control */ +#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */ +#define HS_CSR 0x4A /* Hot Swap Control/Status */ +#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */ +#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next + Capability Pointer */ +#define PVPDAD 0x4E /* PCI Vital Product Data Address */ +#define PVPDATA 0x50 /* PCI VPD Data */ + +typedef struct +{ + unsigned long *subcookie; + unsigned long version; + long routine[45]; +} PCI_COOKIE; + +typedef struct /* structure of resource descriptor */ +{ + unsigned short next; /* length of the following structure */ + unsigned short flags; /* type of resource and misc. flags */ + unsigned long start; /* start-address of resource */ + unsigned long length; /* length of resource */ + unsigned long offset; /* offset PCI to phys. CPU Address */ + unsigned long dmaoffset; /* offset for DMA-transfers */ +} PCI_RSC_DESC; + +typedef struct /* structure of address conversion */ +{ + unsigned long adr; /* calculated address (CPU<->PCI) */ + unsigned long len; /* length of memory range */ +} PCI_CONV_ADR; + +/******************************************************************************/ +/* PCI-BIOS Error Codes */ +/******************************************************************************/ +#define PCI_SUCCESSFUL 0 /* everything's fine */ +#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */ +#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */ +#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */ +#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */ +#define PCI_SET_FAILED -6 /* reserved for later use */ +#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */ +#define PCI_GENERAL_ERROR -8 /* general BIOS error code */ +#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */ + +/******************************************************************************/ +/* Flags used in Resource-Descriptor */ +/******************************************************************************/ +#define FLG_IO 0x4000 /* Ressource in IO range */ +#define FLG_LAST 0x8000 /* last ressource */ +#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */ +#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */ +#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */ +#define FLG_ENDMASK 0x000F /* mask for byte ordering */ + +/******************************************************************************/ +/* Values used in FLG_ENDMASK for Byte Ordering */ +/******************************************************************************/ +#define ORD_MOTOROLA 0 /* Motorola (big endian) */ +#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */ +#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */ +#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */ + +/******************************************************************************/ +/* Status Info used in Device-Descriptor */ +/******************************************************************************/ +#define DEVICE_FREE 0 /* Device is not used */ +#define DEVICE_USED 1 /* Device is used by another driver */ +#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */ +#define DEVICE_AVAILABLE 3 /* used, not available */ +#define NO_DEVICE -1 /* no device detected */ + +/******************************************************************************/ +/* Callback-Routine */ +/******************************************************************************/ + #define GET_DRIVER_ID 0 /* CB-Routine 0: Get Driver ID */ + #define REMOVE_DRIVER 1 /* CB-Routine 1: Remove Driver */ + +/******************************************************************************/ +/* Functions */ +/******************************************************************************/ +//#ifndef OSBIND_CLOBBER_LIST +//#define OSBIND_CLOBBER_LIST +//#endif + +#ifndef trap_14_wlw +#define trap_14_wlw(n, a, b) \ +__extension__ \ +({ \ + register long retvalue __asm__("d0"); \ + long _a = (long) (a); \ + short _b = (short) (b); \ + \ + __asm__ volatile ( \ + "movw %3,sp@-\n\t" \ + "movl %2,sp@-\n\t" \ + "movw %1,sp@-\n\t" \ + "trap #14\n\t" \ + "lea sp@(8),sp" \ + : "=r"(retvalue) \ + : "g"(n), "r"(_a), "r"(_b) \ + ); \ + retvalue; \ +}) +#endif +#ifndef trap_14_wll +#define trap_14_wll(n, a, b) \ +__extension__ \ +({ \ + register long retvalue __asm__("d0"); \ + long _a = (long) (a); \ + long _b = (long) (b); \ + \ + __asm__ volatile ( \ + "movl %3,sp@-\n\t" \ + "movl %2,sp@-\n\t" \ + "movw %1,sp@-\n\t" \ + "trap #14\n\t" \ + "lea sp@(10),sp" \ + : "=r"(retvalue) \ + : "g"(n), "r"(_a), "r"(_b) \ + ); \ + retvalue; \ +}) +#endif +#ifndef trap_14_wlww +#define trap_14_wlww(n, a, b, c) \ +__extension__ \ +({ \ + register long retvalue __asm__("d0"); \ + long _a = (long) (a); \ + short _b = (short) (b); \ + short _c = (short) (c); \ + \ + __asm__ volatile ( \ + "movl %4,sp@-\n\t" \ + "movw %3,sp@-\n\t" \ + "movw %2,sp@-\n\t" \ + "movw %1,sp@-\n\t" \ + "trap #14\n\t" \ + "lea sp@(10),sp" \ + : "=r"(retvalue) \ + : "g"(n), "r"(_a), "r"(_b), "r"(_c) \ + ); \ + retvalue; \ +}) +#endif +#ifndef trap_14_wlwl +#define trap_14_wlwl(n, a, b, c) \ +__extension__ \ +({ \ + register long retvalue __asm__("d0"); \ + long _a = (long) (a); \ + short _b = (short) (b); \ + long _c = (long) (c); \ + \ + __asm__ volatile ( \ + "movl %4,sp@-\n\t" \ + "movw %3,sp@-\n\t" \ + "movl %2,sp@-\n\t" \ + "movw %1,sp@-\n\t" \ + "trap #14\n\t" \ + "lea sp@(12),sp" \ + : "=r"(retvalue) \ + : "g"(n), "r"(_a), "r"(_b), "r"(_c) \ + ); \ + retvalue; \ +}) +#endif +#ifndef trap_14_wlll +#define trap_14_wlll(n, a, b, c) \ +__extension__ \ +({ \ + register long retvalue __asm__("d0"); \ + long _a = (long) (a); \ + long _b = (long) (b); \ + long _c = (long) (c); \ + \ + __asm__ volatile ( \ + "movl %4,sp@-\n\t" \ + "movl %3,sp@-\n\t" \ + "movl %2,sp@-\n\t" \ + "movw %1,sp@-\n\t" \ + "trap #14\n\t" \ + "lea sp@(14),sp" \ + : "=r"(retvalue) \ + : "g"(n), "r"(_a), "r"(_b), "r"(_c) \ + ); \ + retvalue; \ +}) +#endif + +#define find_pci_device(id,index) (long)trap_14_wlw((short)(300),(unsigned long)(id),(unsigned short)(index)) +#define find_pci_classcode(classcode,index) (long)trap_14_wlw((short)(301),(unsigned long)(classcode),(unsigned short)(index)) +#define read_config_byte(handle,reg,address) (long)trap_14_wlwl((short)(302),(long)(handle),(unsigned short)(reg),(unsigned char *)(address)) +#define read_config_word(handle,reg,address) (long)trap_14_wlwl((short)(303),(long)(handle),(unsigned short)(reg),(unsigned short *)(address)) +#define read_config_longword(handle,reg,address) (long)trap_14_wlwl((short)(304),(long)(handle),(unsigned short)(reg),(unsigned long *)(address)) +#define fast_read_config_byte(handle,reg) (unsigned char)trap_14_wlw((short)(305),(long)(handle),(unsigned short)(reg)) +#define fast_read_config_word(handle,reg) (unsigned short)trap_14_wlw((short)(306),(long)(handle),(unsigned short)(reg)) +#define fast_read_config_longword(handle,reg) (unsigned long)trap_14_wlw((short)(307),(long)(handle),(unsigned short)(reg)) +#define write_config_byte(handle,reg,data) (long)trap_14_wlww((short)(308),(long)(handle),(unsigned short)(reg),(unsigned short)(data)) +#define write_config_word(handle,reg,data) (long)trap_14_wlww((short)(309),(long)(handle),(unsigned short)(reg),(unsigned short)(data)) +#define write_config_longword(handle,reg,data) (long)trap_14_wlwl((short)(310),(long)(handle),(unsigned short)(reg),(unsigned long)(data)) +#define hook_interrupt(handle,routine,parameter) (long)trap_14_wlll((short)(311),(long)(handle),(unsigned long *)(routine),(unsigned long *)(parameter)) +#define unhook_interrupt(handle) (long)trap_14_wl((short)(312),(long)(handle)) +#define special_cycle(bus_number,special_cycle) (long)trap_14_wwl((short)(313),(unsigned short)(bus_number),(unsigned long)(special_cycle)) +#define get_routing(handle) (long)trap_14_wl((short)(314),(long)(handle)) +#define set_interrupt(handle,mode) (long)trap_14_wlw((short)(315),(long)(handle),(short)(mode)) +#define get_resource(handle) (long)trap_14_wl((short)(316),(long)(handle)) +#define get_card_used(handle,callback) (long)trap_14_wll((short)(317),(long)(handle),(long *)(address)) +#define set_card_used(handle,callback) (long)trap_14_wll((short)(318),(long)(handle),(long *)(callback)) +#define read_mem_byte(handle,offset,address) (long)trap_14_wlll((short)(319),(long)(handle),(unsigned long)(offset),(unsigned char *)(address)) +#define read_mem_word(handle,offset,address) (long)trap_14_wlll((short)(320),(unsigned long)(offset),(unsigned short *)(address)) +#define read_mem_longword(handle,offset,address) (long)trap_14_wlll((short)(321),(unsigned long)(offset),(unsigned long *)(address)) +#define fast_read_mem_byte(handle,offset) (unsigned char)trap_14_wll((short)(322),(long)(handle),(unsigned long)(offset)) +#define fast_read_mem_word(handle,offset) (unsigned short)trap_14_wll((short)(323),(long)(handle),(unsigned long)(offset)) +#define fast_read_mem_longword(handle,offset) (unsigned long)trap_14_wll((short)(324),(long)(handle),(unsigned long)(offset)) +#define write_mem_byte(handle,offset,data) (long)trap_14_wllw((short)(325),(long)(handle),(unsigned long)(offset),(unsigned short)(data)) +#define write_mem_word(handle,offset,data) (long)trap_14_wllw((short)(326),(long)(handle),(unsigned long)(offset),(unsigned short)(data)) +#define write_mem_longword(handle,offset,data) (long)trap_14_wlll((short)(327),(long)(handle),(unsigned long)(offset),(unsigned long)(data)) +#define read_io_byte(handle,offset,address) (long)trap_14_wlll((short)(328),(long)(handle),(unsigned long)(offset),(unsigned char *)(address)) +#define read_io_word(handle,offset,address) (long)trap_14_wlll((short)(329),(long)(handle),(unsigned long)(offset),(unsigned short *)(address)) +#define read_io_longword(handle,offset,address) (long)trap_14_wlll((short)(330),(long)(handle),(unsigned long)(offset),(unsigned long *)(address)) +#define fast_read_io_byte(handle,offset) (unsigned char)trap_14_wll((short)(331),(long)(handle),(unsigned long)(offset)) +#define fast_read_io_word(handle,offset) (unsigned short)trap_14_wll((short)(332),(long)(handle),(unsigned long)(offset)) +#define fast_read_io_longword(handle,offset) (unsigned long)trap_14_wll((short)(333),(long)(handle),(unsigned long)(offset)) +#define write_io_byte(handle,offset,data) (long)trap_14_wllw((short)(334),(long)(handle),(unsigned long)(offset),(unsigned short)(data)) +#define write_io_word(handle,offset,data) (long)trap_14_wllw((short)(335),(long)(handle),(unsigned long)(offset),(unsigned short)(data)) +#define write_io_longword(handle,offset,data) (long)trap_14_wlll((short)(336),(long)(handle),(unsigned long)(offset),(unsigned long)(data)) +#define get_machine_id() (long)trap_14_w((short)(337)) +#define get_pagesize() (long)trap_14_w((short)(338)) +#define virt_to_bus(handle,address,pointer) (long)trap_14_wlll((short)(339),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer)) +#define bus_to_virt(handle,address,pointer) (long)trap_14_wlll((short)(340),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer)) +#define virt_to_phys(address,pointer) (long)trap_14_wll((short)(341),(unsigned long)(address),(unsigned long *)(pointer)) +#define phys_to_virt(address,pointer) (long)trap_14_wll((short)(342),(unsigned long)(address),(unsigned long *)(pointer)) +#define dma_setbuffer(pci_address,local_address,size) (long)trap_14_wlll((short)(350),(unsigned long)(pci_address),(unsigned long)(local_address),(unsigned long)(size)) +#define dma_buffoper(mode) (long)trap_14_ww((short)(351),(short)(mode)) +#define read_mailbox(mailbox,pointer) (long)trap_14_wwl((short)(352),(short)(mailbox),(unsigned long *)(pointer)) +#define write_mailbox(mailbox,data) (long)trap_14_wwl((short)(353),(short)(mailbox),(unsigned long)(data)) + +extern long Find_pci_device(unsigned long id, unsigned short index); +extern long Find_pci_classcode(unsigned long class, unsigned short index); +extern long Read_config_byte(long handle, unsigned short reg, unsigned char *address); +extern long Read_config_word(long handle, unsigned short reg, unsigned short *address); +extern long Read_config_longword(long handle, unsigned short reg, unsigned long *address); +extern unsigned char Fast_read_config_byte(long handle, unsigned short reg); +extern unsigned short Fast_read_config_word(long handle, unsigned short reg); +extern unsigned long Fast_read_config_longword(long handle, unsigned short reg); +extern long Write_config_byte(long handle, unsigned short reg, unsigned short val); +extern long Write_config_word(long handle, unsigned short reg, unsigned short val); +extern long Write_config_longword(long handle, unsigned short reg, unsigned long val); +extern long Hook_interrupt(long handle, unsigned long *routine, unsigned long *parameter); +extern long Unhook_interrupt(long handle); +extern long Special_cycle(unsigned short bus, unsigned long data); +extern long Get_routing(long handle); +extern long Set_interrupt(long handle); +extern long Get_resource(long handle); +extern long Get_card_used(long handle, unsigned long *address); +extern long Set_card_used(long handle, unsigned long *callback); +extern long Read_mem_byte(long handle, unsigned long offset, unsigned char *address); +extern long Read_mem_word(long handle, unsigned long offset, unsigned short *address); +extern long Read_mem_longword(long handle, unsigned long offset, unsigned long *address); +extern unsigned char Fast_read_mem_byte(long handle, unsigned long offset); +extern unsigned short Fast_read_mem_word(long handle, unsigned long offset); +extern unsigned long Fast_read_mem_longword(long handle, unsigned long offset); +extern long Write_mem_byte(long handle, unsigned long offset, unsigned short val); +extern long Write_mem_word(long handle, unsigned long offset, unsigned short val); +extern long Write_mem_longword(long handle, unsigned long offset, unsigned long val); +extern long Read_io_byte(long handle, unsigned long offset, unsigned char *address); +extern long Read_io_word(long handle, unsigned long offset, unsigned short *address); +extern long Read_io_longword(long handle, unsigned long offset, unsigned long *address); +extern unsigned char Fast_read_io_byte(long handle, unsigned long offset); +extern unsigned short Fast_read_io_word(long handle, unsigned long offset); +extern unsigned long Fast_read_io_longword(long handle, unsigned long offset); +extern long Write_io_byte(long handle, unsigned long offset, unsigned short val); +extern long Write_io_word(long handle, unsigned long offset, unsigned short val); +extern long Write_io_longword(long handle, unsigned long offset, unsigned long val); +extern long Get_machine_id(void); +extern long Get_pagesize(void); +extern long Virt_to_bus(long handle, unsigned long address, PCI_CONV_ADR *pointer); +extern long Bus_to_virt(long handle, unsigned long address, PCI_CONV_ADR *pointer); +extern long Virt_to_phys(unsigned long address, PCI_CONV_ADR *pointer); +extern long Phys_to_virt(unsigned long address, PCI_CONV_ADR *pointer); + +#endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/main.c b/BaS_codewarrior/FireBee/trunk/usb/store/main.c new file mode 100644 index 0000000..32d7f4b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/main.c @@ -0,0 +1,206 @@ +/* + * David Galvez. 2010, e-mail: dgalvez75@gmail.com + * PCI code taken from FireTos by Didier Mequignon + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "config.h" +#include "usb.h" +#include "super.h" +#include "debug.h" +#ifdef PCI_XBIOS +#include "host/ohci-pci/pci_ids.h" +#include "host/ohci-pci/pcixbios.h" +#endif +#include +#include + +extern long install_usb_stor(int dev_num, unsigned long part_type, + unsigned long part_offset, unsigned long part_size, + char *vendor, char *revision, char *product); +extern int do_usb(int argc, char **argv); +extern unsigned long _PgmSize; +extern long __mint; +#ifdef PCI_XBIOS +extern struct pci_device_id usb_pci_table[]; /* ohci-hcd.c */ +#endif + +int usb_stor_curr_dev; +unsigned long usb_1st_disk_drive; +short max_logical_drive; + +#ifdef PCI_XBIOS +short pci_init(void) +{ +/* PCI devices detection */ + struct pci_device_id *board; + long handle; + short usb_found; + + short idx; + long err; + unsigned long class; + + usb_found = 0; + idx = 0; + do { + handle = find_pci_device(0x0000FFFFL, idx++); +printf("idx %d PCI handle: %lx\n", idx -1, handle); /* Galvez: Debug */ + if(handle >= 0) { + unsigned long id = 0; + err = read_config_longword(handle, PCIIDR, &id); + + if((err >= 0) && !usb_found) { + if(read_config_longword(handle, PCIREV, &class) >= 0 + && ((class >> 16) == PCI_CLASS_SERIAL_USB)) { + if((class >> 8) == PCI_CLASS_SERIAL_USB_UHCI) + (void) Cconws("UHCI USB controller found\r\n"); + else if((class >> 8) == PCI_CLASS_SERIAL_USB_OHCI) { + (void) Cconws("OHCI USB controller found\r\n"); +#ifdef CONFIG_USB_OHCI + board = usb_pci_table; /* compare table */ + while(board->vendor) { + if((board->vendor == (id & 0xFFFF)) + && (board->device == (id >> 16))) { + if(usb_init(handle, board) >= 0) + usb_found = 1; + break; + } + board++; + } +#endif /* CONFIG_USB_OHCI */ + } + else if((class >> 8) == PCI_CLASS_SERIAL_USB_EHCI) + (void) Cconws("EHCI USB controller found\r\n"); + } + } + } + } + while(handle >= 0); + return usb_found; +} +#endif /* PCI_XBIOS */ + +int main(int argc, char **argv) +{ +#ifdef CONFIG_USB_STORAGE + long p = 0; + int r; + + if (__mint) + max_logical_drive = 24; + else max_logical_drive = 16; + + if (argc == 1) { + short usb_found = 0; + + usb_stor_curr_dev = -1; + usb_1st_disk_drive = 0; + + usb_stop(); +#ifdef PCI_XBIOS + usb_found = pci_init(); +#else + if (usb_init() >= 0) + usb_found = 1; +#endif /* PCI_XBIOS */ + if (usb_found) { + /* Scan and get info from all the storage devices found */ + usb_stor_curr_dev = usb_stor_scan(); + /* it doesn't really return current device * + * only 0 if it has found any store device * + * -1 otherwise */ + if (usb_stor_curr_dev != -1) { + int dev_num = usb_stor_curr_dev; + block_dev_desc_t *stor_dev; + + while ((stor_dev = usb_stor_get_dev(dev_num)) != NULL) { + int part_num = 1; + unsigned long part_type, part_offset, part_size; + /* Now find partitions in this storage device */ + while (!fat_register_device(stor_dev, part_num, &part_type, + &part_offset, &part_size)) { + if (!(Super(SUP_INQUIRE))) { + p = SuperFromUser (); + } + + /* install partition */ + r = install_usb_stor(dev_num, part_type, part_offset, + part_size, stor_dev->vendor, + stor_dev->revision, stor_dev->product); + if (r == -1) + printf("unable to install storage device\n"); + + if (p) + SuperToUser(p); + + part_num++; + } + dev_num++; + } + + } +#if 0 + long *drvbits; + long value; + + p = SuperFromUser(); + + drvbits = 0x000004c2; + + value = *drvbits; + printf("\ndrvbits: %x \n", (unsigned)value); + SuperToUser(p); +#endif + + } + + if (!__mint) { + printf(" Press any key"); + Bconin(DEV_CONSOLE); + } + Ptermres( _PgmSize, 0); + } +#endif /* CONFIG_USB_STORAGE */ + + if (strncmp(argv[1], "tree", 4) == 0) { + argc = 2; + argv[1] = "start"; + do_usb(argc, argv); + + argv[1] = "inf"; + do_usb(argc, argv); + + argv[1] = "tree"; + do_usb(argc, argv); + + argv[1] = "storage"; + do_usb(argc, argv); + +// argc = 3; +// argv[1] = "dev"; +// argv[2] = "0"; +// do_usb(argc, argv); + +// argc = 2; + argv[1] = "stop"; + do_usb (argc, argv); + + printf(" Press any key\r\n"); + Bconin(DEV_CONSOLE); + } + return 0; +} diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/makefile b/BaS_codewarrior/FireBee/trunk/usb/store/makefile new file mode 100644 index 0000000..2164391 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/makefile @@ -0,0 +1,85 @@ + +ifeq ($(CROSS),yes) +CC = m68k-atari-mint-gcc +STRIP = m68k-atari-mint-strip +STACK = m68k-atari-mint-stack +INCLUDE_GEM_PATH = /usr/local/cross-mint/m68k-atari-mint/include +LIB_GEM_PATH = /usr/local/cross-mint/m68k-atari-mint/lib +else +CC = gcc +STRIP = /usr/bin/strip +STACK = stack +COMPRESS = upx +INCLUDE_GEM_PATH = /usr/GEM/include +LIB_GEM_PATH = /usr/GEM/lib +endif + + +ifeq ($(MAKECMDGOALS), aranym) +HCD_S = ./host/aranym/natfeat_asm.S +HCD_C = ./host/aranym/aranym-hcd.c ./host/aranym/natfeat.c +HCD_H = ./host/aranym/nf_ops.h ./host/aranym/usbhost_nfapi.h +PROGRAM = stor_ara.tos +endif +ifeq ($(MAKECMDGOALS), netusbee) +HCD_C = ./host/netusbee/isp116x-hcd.c +HCD_H = ./host/netusbee/isp116x.h +PROGRAM = stor_ntu.tos +endif +ifeq ($(MAKECMDGOALS), ethernat) +HCD_C = ./host/ethernat/isp116x-hcd.c +HCD_H = ./host/ethernat/isp116x.h +PROGRAM = stor_etn.tos +endif +ifeq ($(MAKECMDGOALS), ohci-pci) +HCD_C = ./host/ohci-pci/ohci-hcd.c ./host/ohci-pci/ltoa.c +HCD_H = ./host/ohci-pci/ohci.h ./host/ohci-pci/pcixbios.h +DEFS = -DPCI_XBIOS +PROGRAM = stor_pci.tos +endif + +STACKSIZE = 64k +OPTIMISATION = -O -fomit-frame-pointer +CPU = -m68020-60 +LIB = +ASFLAGS = $(CPU) +CFLAGS = $(CPU) $(OPTIMISATION) -Wall -Wshadow -I$(INCLUDE_GEM_PATH) $(DEFS) -g +LFLAGS = -L$(LIB_GEM_PATH) +COBJS = main.c udelay.c cmd_usb.c usb.c usb_mem.c usb_storage.c debug.c $(HCD_C) +SOBJS = debug2.S bios.S $(HCD_S) +HSRC = config.h debug.h part.h scsi.h super.h usb.h usb_defs.h vars.h $(HCD_H) +COBJECTS = $(COBJS:.c=.o) +SOBJECTS = $(SOBJS:.S=.o) + +all: + make ethernat + make netusbee + make aranym + rm -f *.o + make ohci-pci + +ethernat: $(PROGRAM) + +aranym: $(PROGRAM) + +netusbee: $(PROGRAM) + +ohci-pci: $(PROGRAM) + +$(PROGRAM): $(COBJECTS) $(SOBJECTS) $(HSRC) + $(CC) -o $@ $(COBJECTS) $(SOBJECTS) + +strip: + $(STRIP) $(PROGRAM) + +stack: + $(STACK) -S $(STACKSIZE) $(PROGRAM) + +compress: + $(COMPRESS) $(PROGRAM) + +clean: + rm -f *.tos *.log + find ./ -type f -name "*.o" -exec rm -f {} \; + + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/part.h b/BaS_codewarrior/FireBee/trunk/usb/store/part.h new file mode 100644 index 0000000..96ae888 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/part.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PART_H +#define _PART_H + +typedef unsigned long long uint64_t; +typedef unsigned long lbaint_t; + +typedef struct block_dev_desc { + int if_type; /* type of the interface */ + int dev; /* device number */ + unsigned char part_type; /* partition type */ + unsigned char target; /* target SCSI ID */ + unsigned char lun; /* target LUN */ + unsigned char type; /* device type */ + unsigned char removable; /* removable device */ +#ifdef CONFIG_LBA48 + unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */ +#endif + lbaint_t lba; /* number of blocks */ + unsigned long blksz; /* block size */ + char vendor [40+1]; /* IDE model, SCSI Vendor */ + char product[20+1]; /* IDE Serial no, SCSI product */ + char revision[8+1]; /* firmware revision */ + unsigned long (*block_read)(int dev, unsigned long start, lbaint_t blkcnt, void *buffer); + unsigned long (*block_write)(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer); + void *priv; /* driver private struct pointer */ +}block_dev_desc_t; + +/* Interface types: */ +#define IF_TYPE_UNKNOWN 0 +#define IF_TYPE_IDE 1 +#define IF_TYPE_SCSI 2 +#define IF_TYPE_ATAPI 3 +#define IF_TYPE_USB 4 +#define IF_TYPE_DOC 5 +#define IF_TYPE_MMC 6 +#define IF_TYPE_SD 7 +#define IF_TYPE_SATA 8 + +/* Part types */ +#define PART_TYPE_UNKNOWN 0x00 +#define PART_TYPE_MAC 0x01 +#define PART_TYPE_DOS 0x02 +#define PART_TYPE_ISO 0x03 +#define PART_TYPE_AMIGA 0x04 +#define PART_TYPE_EFI 0x05 + +/* + * Type string for U-Boot bootable partitions + */ +#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */ +#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */ + +/* device types */ +#define DEV_TYPE_UNKNOWN 0xff /* not connected */ +#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ +#define DEV_TYPE_TAPE 0x01 /* Tape */ +#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ +#define DEV_TYPE_OPDISK 0x07 /* optical disk */ + +void print_part(block_dev_desc_t *dev_desc); +void init_part(block_dev_desc_t *dev_desc); +void dev_print(block_dev_desc_t *dev_desc); + +int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size); + +#endif /* _PART_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/readme.txt b/BaS_codewarrior/FireBee/trunk/usb/store/readme.txt new file mode 100644 index 0000000..a1de9ad --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/readme.txt @@ -0,0 +1,68 @@ +This application allows you to mount an USB mass storage device though +the Ethernat hardware or the Aranym USB Natfeat, read or copy files from/to this device. +It's derived from the work done by Didier Mequignon for FireTOS. + +This is still quite experimental so i am not responsable for any data loss +or corruption, play with it at your own risk. Please backup your data ;-) + +**** Binaries **** + +stor_etn.tos ---> EtherNat +stor_ara.tos ---> Aranym +stor_ntu.tos ---> NetUSBee +stor_pci.tos ---> PCI-OHCI + +Note that NetUSBee and PCI-OHCI don't work yet + +**** How it works ***** + +Depending on your hardware run stor_etn.tos or stor_ara.tos application from your desktop, +if everything goes well you can use the "install partition" option in your desktop menu to +access the new partitions. + +It has been tested it under CT060 TOS and MiNT 1.16.3. +Teted in Aranym with MiNT 1.17.0 beta and TOS 4.04. + +**** Limits/Problems ***** + +- The supported partitions are the supported partitions by the OS. +It has been tested with FAT16 in TOS4.04, with FAT16, FAT32 and ext2 with MiNT. + +- There is still no handle for mounting/unmounting partitions. Neither detection for +devices already plugged, so when you mount one device you can't unmount it. +If you run the application several times with the same USB stick plugged, it +will mount the device again as a new different logical partition. + +- It's VERY VERY slow, for now the transfer rate it's quite ridiculous. I hope +to solve this soon. Under Aranym it can be better. + +- I don't think that it works together with umouse from Jan Thomas. + +- This is only a start don't expect too much. + +- Thing desktop crashes when inquiring to show info about the device. + +For feedback, suggestions or tips mail me at dgalvez75@gmail.com + +**** Histoy **** +* 5/10/2010 (alfa 05) + - XHDI working (assembler version). + - Under MiNT FAT32 and ext2 partitions can be accesed. + - Introduced NetUSBee sources (not working yet) + - Introduced OHCI-PCI sources (to be tested) +* 27/8/2010 (alfa 04) + - Start XHDI translation to C. + - Support for Aranym HCD. +* 19/5/2010 (alfa 03) + - Killed a bug that could produce some corruption in the pun_info struct. +* 26/4/2010 (alfa 02) + - Under MiNT if the number of partitions was greater than 16, the driver wasn't installed. + - Wait for a key pess before retuning the desktop under TOS when driver is loaded. + - Resolved big bug that produced that data written/read above the first 16 MB to be corrupted. +* 1/3/2010 (alfa 01) + - Initial release + +David Galvez 05/10/2010 +Version: alfa 05 + + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/scsi.h b/BaS_codewarrior/FireBee/trunk/usb/store/scsi.h new file mode 100644 index 0000000..a42c0a3 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/scsi.h @@ -0,0 +1,209 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + #ifndef _SCSI_H + #define _SCSI_H + +typedef struct SCSI_cmd_block{ + unsigned char cmd[16]; /* command */ + unsigned char sense_buf[64]; /* for request sense */ + unsigned char status; /* SCSI Status */ + unsigned char target; /* Target ID */ + unsigned char lun; /* Target LUN */ + unsigned char cmdlen; /* command len */ + unsigned long datalen; /* Total data length */ + unsigned char * pdata; /* pointer to data */ + unsigned char msgout[12]; /* Messge out buffer (NOT USED) */ + unsigned char msgin[12]; /* Message in buffer */ + unsigned char sensecmdlen; /* Sense command len */ + unsigned long sensedatalen; /* Sense data len */ + unsigned char sensecmd[6]; /* Sense command */ + unsigned long contr_stat; /* Controller Status */ + unsigned long trans_bytes; /* tranfered bytes */ + + unsigned int priv; +}ccb; + +/*----------------------------------------------------------- +** +** SCSI constants. +** +**----------------------------------------------------------- +*/ + +/* +** Messages +*/ + +#define M_COMPLETE (0x00) +#define M_EXTENDED (0x01) +#define M_SAVE_DP (0x02) +#define M_RESTORE_DP (0x03) +#define M_DISCONNECT (0x04) +#define M_ID_ERROR (0x05) +#define M_ABORT (0x06) +#define M_REJECT (0x07) +#define M_NOOP (0x08) +#define M_PARITY (0x09) +#define M_LCOMPLETE (0x0a) +#define M_FCOMPLETE (0x0b) +#define M_RESET (0x0c) +#define M_ABORT_TAG (0x0d) +#define M_CLEAR_QUEUE (0x0e) +#define M_INIT_REC (0x0f) +#define M_REL_REC (0x10) +#define M_TERMINATE (0x11) +#define M_SIMPLE_TAG (0x20) +#define M_HEAD_TAG (0x21) +#define M_ORDERED_TAG (0x22) +#define M_IGN_RESIDUE (0x23) +#define M_IDENTIFY (0x80) + +#define M_X_MODIFY_DP (0x00) +#define M_X_SYNC_REQ (0x01) +#define M_X_WIDE_REQ (0x03) +#define M_X_PPR_REQ (0x04) + + +/* +** Status +*/ + +#define S_GOOD (0x00) +#define S_CHECK_COND (0x02) +#define S_COND_MET (0x04) +#define S_BUSY (0x08) +#define S_INT (0x10) +#define S_INT_COND_MET (0x14) +#define S_CONFLICT (0x18) +#define S_TERMINATED (0x20) +#define S_QUEUE_FULL (0x28) +#define S_ILLEGAL (0xff) +#define S_SENSE (0x80) + +/* + * Sense_keys + */ + +#define SENSE_NO_SENSE 0x0 +#define SENSE_RECOVERED_ERROR 0x1 +#define SENSE_NOT_READY 0x2 +#define SENSE_MEDIUM_ERROR 0x3 +#define SENSE_HARDWARE_ERROR 0x4 +#define SENSE_ILLEGAL_REQUEST 0x5 +#define SENSE_UNIT_ATTENTION 0x6 +#define SENSE_DATA_PROTECT 0x7 +#define SENSE_BLANK_CHECK 0x8 +#define SENSE_VENDOR_SPECIFIC 0x9 +#define SENSE_COPY_ABORTED 0xA +#define SENSE_ABORTED_COMMAND 0xB +#define SENSE_VOLUME_OVERFLOW 0xD +#define SENSE_MISCOMPARE 0xE + + +#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_COPY 0x18 /* Copy (O) */ +#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */ +#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */ +#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */ +#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */ +#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */ +#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */ +#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */ +#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */ +#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */ +#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */ +#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */ +#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */ +/*************************************************************************** + * %%% Commands Unique to Direct Access Devices %%% + ***************************************************************************/ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */ +#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */ +#define SCSI_PREFETCH 0x34 /* Prefetch (O) */ +#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */ +#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ +#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ +#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ +#define SCSI_READ_LONG 0x3E /* Read Long (O) */ +#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ +#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */ +#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */ +#define SCSI_REZERO 0x01 /* Rezero Unit (O) */ +#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */ +#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */ +#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */ +#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */ +#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */ +#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */ +#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */ +#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */ +#define SCSI_VERIFY 0x2F /* Verify (O) */ +#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */ +#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */ +#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */ +#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */ +#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */ + +#if 0 +/**************************************************************************** + * decleration of functions which have to reside in the LowLevel Part Driver + */ + +void scsi_print_error(ccb *pccb); +int scsi_exec(ccb *pccb); +void scsi_bus_reset(void); +void scsi_low_level_init(int busdevfunc); + + +/*************************************************************************** + * functions residing inside cmd_scsi.c + */ +void scsi_init(void); + +#endif + +#define SCSI_IDENTIFY 0xC0 /* not used */ + +/* Hardware errors */ +#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */ +#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */ +#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */ +#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */ + +#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ + + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* _SCSI_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/super.h b/BaS_codewarrior/FireBee/trunk/usb/store/super.h new file mode 100644 index 0000000..017beb9 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/super.h @@ -0,0 +1,58 @@ +/* + * super.h + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _SUPER_H +#define _SUPER_H + +static inline +long SuperFromUser() +{ + register long retvalue __asm__("d0"); + + __asm__ volatile + ( + "clr.l -(%%sp)\n\t" + "move.w #0x20,-(%%sp)\n\t" + "trap #1\n\t" + "addq.l #6,%%sp" + : "=r"(retvalue) /* outputs */ + : /* inputs */ + : "d1", "d2", "a0", "a1", "a2" /* clobbered regs */ + ); + + return retvalue; +} + +static inline +void SuperToUser(long ssp) +{ + register long spbackup; + + __asm__ volatile + ( + "move.l sp,%0\n\t" + "move.l %1,-(%%sp)\n\t" + "move.w #0x20,-(%%sp)\n\t" + "trap #1\n\t" + "move.l %0,sp" + : "=&r"(spbackup) /* outputs */ + : "g"(ssp) /* inputs */ + : "d0", "d1", "d2", "a0", "a1", "a2" /* clobbered regs */ + ); +} +#endif /* _SUPER_H */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/udelay.c b/BaS_codewarrior/FireBee/trunk/usb/store/udelay.c new file mode 100644 index 0000000..d685aad --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/udelay.c @@ -0,0 +1,39 @@ +/* + * David Galvez. 2010, e-mail: dgalvez75@gmail.com + * Modified from MiNTlib + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define USEC_PER_TICK (1000000L / ((unsigned long)CLOCKS_PER_SEC)) +#define USEC_TO_CLOCK_TICKS(us) ((us) / USEC_PER_TICK ) + +/* + * Galvez: We should use usleep POSIX function in MiNTlib, but it gives problems related with + * Fselect system call, until we trace where the problems come from we are using this function + */ + +void udelay(unsigned long usec) +{ + long stop; + + stop = _clock() + USEC_TO_CLOCK_TICKS(usec); + while (_clock() < stop); +} diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/usb.c b/BaS_codewarrior/FireBee/trunk/usb/store/usb.c new file mode 100644 index 0000000..6b3335d --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/usb.c @@ -0,0 +1,1422 @@ +/* + * Modified for Atari by David Gálvez 2010 + * Modified for Atari by Didier Mequignon 2009 + * + * Most of this source has been derived from the Linux USB + * project: + * (C) Copyright Linus Torvalds 1999 + * (C) Copyright Johannes Erdfelt 1999-2001 + * (C) Copyright Andreas Gal 1999 + * (C) Copyright Gregory P. Smith 1999 + * (C) Copyright Deti Fliegl 1999 (new USB architecture) + * (C) Copyright Randy Dunlap 2000 + * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id) + * (C) Copyright Yggdrasil Computing, Inc. 2000 + * (usb_device_id matching changes by Adam J. Richter) + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * How it works: + * + * Since this is a bootloader, the devices will not be automatic + * (re)configured on hotplug, but after a restart of the USB the + * device should work. + * + * For each transfer (except "Interrupt") we wait for completion. + */ +#include "config.h" +#include "debug.h" +#include "usb.h" + +#ifdef CONFIG_4xx +#include +#endif + +#include + +#define DEBUG_USB_LOCAL 1 +#ifndef DEBUG_USB_LOCAL +#define DEBUG_USB(fmt, args...) +#endif + +#define USB_BUFSIZ 512 + +void udelay(unsigned long usec); + +static struct usb_device usb_dev[USB_MAX_DEVICE]; +static int dev_index; +static int running; +static int asynch_allowed; +static struct devrequest setup_packet; + +char usb_started; /* flag for the started/stopped USB status */ + +/********************************************************************** + * some forward declerations... + */ +void usb_scan_devices(void); + +int usb_hub_probe(struct usb_device *dev, int ifnum); +void usb_hub_reset(void); +static int hub_port_reset(struct usb_device *dev, int port, + unsigned short *portstat); + +/*********************************************************************** + * wait_ms + */ + +inline void wait_ms(unsigned long ms) +{ + udelay( ms * 1000); +} + +/*************************************************************************** + * Init USB Device + */ + +#ifndef PCI_XBIOS +int usb_init(void) +#else +int usb_init(long handle, const struct pci_device_id *ent) +#endif +{ + int result; + + running = 0; + dev_index = 0; + asynch_allowed = 1; + usb_hub_reset(); + + /* Added by Didier */ + if(usb_mem_init()) + { + usb_started = 0; + return -1; /* out of memoy */ + } + + /* init low_level USB */ + printf("USB: "); +#ifndef PCI_XBIOS + result = usb_lowlevel_init( ); +#else + result = usb_lowlevel_init(0,NULL); +#endif + /* if lowlevel init is OK, scan the bus for devices + * i.e. search HUBs and configure them */ + if (result == 0) { + printf("scanning bus for devices... "); + running = 1; + usb_scan_devices(); + usb_started = 1; + return 0; + } else { + printf("Error, couldn't init Lowlevel part\n"); + usb_started = 0; + return -1; + } +} + +/****************************************************************************** + * Stop USB this stops the LowLevel Part and deregisters USB devices. + */ +int usb_stop(void) +{ + int res = 0; + + if (usb_started) { + asynch_allowed = 1; + usb_started = 0; + usb_hub_reset(); + res = usb_lowlevel_stop(); + } + return res; +} + +/* + * disables the asynch behaviour of the control message. This is used for data + * transfers that uses the exclusiv access to the control and bulk messages. + */ +void usb_disable_asynch(int disable) +{ +#if 0 +/* Added by Didier */ +#ifndef CONFIG_USB_INTERRUPT_POLLING + if(!asynch_allowed && !disable) + { + DEBUG_USB("Enable interrupts\r\n"); + usb_enable_interrupt(1); + } + else if(asynch_allowed && disable) + { + DEBUG_USB("Disable interrupts\r\n"); + usb_enable_interrupt(0); + } +#endif +#endif + asynch_allowed = !disable; +} + + +/*------------------------------------------------------------------- + * Message wrappers. + * + */ + +/* + * submits an Interrupt Message + */ +int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, int interval) +{ + return submit_int_msg(dev, pipe, buffer, transfer_len, interval); +} + +/* + * submits a control message and waits for comletion (at least timeout * 1ms) + * If timeout is 0, we don't wait for completion (used as example to set and + * clear keyboards LEDs). For data transfers, (storage transfers) we don't + * allow control messages with 0 timeout, by previousely resetting the flag + * asynch_allowed (usb_disable_asynch(1)). + * returns the transfered length if OK or -1 if error. The transfered length + * and the current status are stored in the dev->act_len and dev->status. + */ +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short idx, + void *data, unsigned short size, int timeout) +{ + if ((timeout == 0) && (!asynch_allowed)) { + /* request for a asynch control pipe is not allowed */ + return -1; + } + + /* set setup command */ + setup_packet.requesttype = requesttype; + setup_packet.request = request; + setup_packet.value = __cpu_to_le16(value); + setup_packet.index = __cpu_to_le16(idx); + setup_packet.length = __cpu_to_le16(size); + DEBUG_USB("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \ + "value 0x%X idx 0x%X length 0x%X\n", + request, requesttype, value, idx, size); + dev->status = USB_ST_NOT_PROC; /*not yet processed */ + + submit_control_msg(dev, pipe, data, size, &setup_packet); + if (timeout == 0){ + DEBUG_USB("size %d \r\n", size); + return (int)size; + } + + if (dev->status != 0) { + /* + * Let's wait a while for the timeout to elapse. + * It has no real use, but it keeps the interface happy. + */ + DEBUG_USB("status %ld \n\r", dev->status); + wait_ms(timeout); + return -1; + } + return dev->act_len; +} + +/*------------------------------------------------------------------- + * submits bulk message, and waits for completion. returns 0 if Ok or + * -1 if Error. + * synchronous behavior + */ +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout) +{ + if (len < 0) + return -1; + dev->status = USB_ST_NOT_PROC; /*not yet processed */ + submit_bulk_msg(dev, pipe, data, len); + while (timeout--) { + if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) + break; + wait_ms(1); + } + + *actual_length = dev->act_len; + if (dev->status == 0) + return 0; + else + return -1; +} + + +/*------------------------------------------------------------------- + * Max Packet stuff + */ + +/* + * returns the max packet size, depending on the pipe direction and + * the configurations values + */ +int usb_maxpacket(struct usb_device *dev, unsigned long pipe) +{ + /* direction is out -> use emaxpacket out */ + if ((pipe & USB_DIR_IN) == 0) + return dev->epmaxpacketout[((pipe>>15) & 0xf)]; + else + return dev->epmaxpacketin[((pipe>>15) & 0xf)]; +} + +/* The routine usb_set_maxpacket_ep() is extracted from the loop of routine + * usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine + * when it is inlined in 1 single routine. What happens is that the register r3 + * is used as loop-count 'i', but gets overwritten later on. + * This is clearly a compiler bug, but it is easier to workaround it here than + * to update the compiler (Occurs with at least several GCC 4.{1,2},x + * CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM) + */ +static void __attribute__((noinline)) +usb_set_maxpacket_ep(struct usb_device *dev, struct usb_endpoint_descriptor *ep) +{ + int b; + + b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + + if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_CONTROL) { + /* Control => bidirectional */ + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + dev->epmaxpacketin[b] = ep->wMaxPacketSize; + DEBUG_USB("##Control EP epmaxpacketout/in[%d] = %d\n", + b, dev->epmaxpacketin[b]); + } else { + if ((ep->bEndpointAddress & 0x80) == 0) { + /* OUT Endpoint */ + if (ep->wMaxPacketSize > dev->epmaxpacketout[b]) { + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + DEBUG_USB("##EP epmaxpacketout[%d] = %d\n", + b, dev->epmaxpacketout[b]); + } + } else { + /* IN Endpoint */ + if (ep->wMaxPacketSize > dev->epmaxpacketin[b]) { + dev->epmaxpacketin[b] = ep->wMaxPacketSize; + DEBUG_USB("##EP epmaxpacketin[%d] = %d\n", + b, dev->epmaxpacketin[b]); + } + } /* if out */ + } /* if control */ +} + +/* + * set the max packed value of all endpoints in the given configuration + */ +int usb_set_maxpacket(struct usb_device *dev) +{ + int i, ii; + + for (i = 0; i < dev->config.bNumInterfaces; i++) + for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++) + usb_set_maxpacket_ep(dev, + &dev->config.if_desc[i].ep_desc[ii]); + + return 0; +} + +/******************************************************************************* + * Parse the config, located in buffer, and fills the dev->config structure. + * Note that all little/big endian swapping are done automatically. + */ +int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) +{ + struct usb_descriptor_header *head; + int idx, ifno, epno, curr_if_num; + int i; + unsigned char *ch; + + ifno = -1; + epno = -1; + curr_if_num = -1; + + dev->configno = cfgno; + head = (struct usb_descriptor_header *) &buffer[0]; + if (head->bDescriptorType != USB_DT_CONFIG) { + printf(" ERROR: NOT USB_CONFIG_DESC %x\n", + head->bDescriptorType); + return -1; + } + memcpy(&dev->config, buffer, buffer[0]); + __le16_to_cpus(&(dev->config.wTotalLength)); + dev->config.no_of_if = 0; + + idx = dev->config.bLength; + /* Ok the first entry must be a configuration entry, + * now process the others */ + head = (struct usb_descriptor_header *) &buffer[idx]; + while (idx + 1 < dev->config.wTotalLength) { + switch (head->bDescriptorType) { + case USB_DT_INTERFACE: + if (((struct usb_interface_descriptor *) \ + &buffer[idx])->bInterfaceNumber != curr_if_num) { + /* this is a new interface, copy new desc */ + ifno = dev->config.no_of_if; + dev->config.no_of_if++; + memcpy(&dev->config.if_desc[ifno], + &buffer[idx], buffer[idx]); + dev->config.if_desc[ifno].no_of_ep = 0; + dev->config.if_desc[ifno].num_altsetting = 1; + curr_if_num = + dev->config.if_desc[ifno].bInterfaceNumber; + } else { + /* found alternate setting for the interface */ + dev->config.if_desc[ifno].num_altsetting++; + } + break; + case USB_DT_ENDPOINT: + epno = dev->config.if_desc[ifno].no_of_ep; + /* found an endpoint */ + dev->config.if_desc[ifno].no_of_ep++; + memcpy(&dev->config.if_desc[ifno].ep_desc[epno], + &buffer[idx], buffer[idx]); + __le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].\ + wMaxPacketSize)); + DEBUG_USB("if %d, ep %d\n", ifno, epno); + break; + default: + if (head->bLength == 0) + return 1; + + DEBUG_USB("unknown Description Type : %x\n", + head->bDescriptorType); + + { + ch = (unsigned char *)head; + for (i = 0; i < head->bLength; i++) + DEBUG_USB("%02X ", *ch++); + DEBUG_USB("\n\n\n"); + } + break; + } + idx += head->bLength; + head = (struct usb_descriptor_header *)&buffer[idx]; + } + return 1; +} + +/*********************************************************************** + * Clears an endpoint + * endp: endpoint number in bits 0-3; + * direction flag in bit 7 (1 = IN, 0 = OUT) + */ +int usb_clear_halt(struct usb_device *dev, int pipe) +{ + int result; + int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7); + + result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, + endp, NULL, 0, USB_CNTL_TIMEOUT * 3); + + /* don't clear if failed */ + if (result < 0) + return result; + + /* + * NOTE: we do not get status and verify reset was successful + * as some devices are reported to lock up upon this check.. + */ + + usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + /* toggle is reset on clear */ + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0); + return 0; +} + + +/********************************************************************** + * get_descriptor type + */ +int usb_get_descriptor(struct usb_device *dev, unsigned char type, + unsigned char idx, void *buf, int size) +{ + int res; +DEBUG_USB( "%s\n",__FUNCTION__); + res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (type << 8) + idx, 0, + buf, size, USB_CNTL_TIMEOUT); + return res; +} + +/********************************************************************** + * gets configuration cfgno and store it in the buffer + */ +int usb_get_configuration_no(struct usb_device *dev, + unsigned char *buffer, int cfgno) +{ + int result; + unsigned int tmp; + struct usb_config_descriptor *config; + + + config = (struct usb_config_descriptor *)&buffer[0]; + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9); + if (result < 9) { + if (result < 0) + printf("unable to get descriptor, error %lX\n", + dev->status); + else + printf("config descriptor too short " \ + "(expected %i, got %i)\n", 9, result); + return -1; + } + tmp = __le16_to_cpu(config->wTotalLength); + + if (tmp > USB_BUFSIZ) { + DEBUG_USB("usb_get_configuration_no: failed to get " \ + "descriptor - too long: %d\n", tmp); + return -1; + } + + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp); + DEBUG_USB("get_conf_no %d Result %d, wLength %d\n", + cfgno, result, tmp); + return result; +} + +/******************************************************************** + * set address of a device to the value in dev->devnum. + * This can only be done by addressing the device via the default address (0) + */ +int usb_set_address(struct usb_device *dev) +{ + int res; + + DEBUG_USB("set address %d\n", dev->devnum); + res = usb_control_msg(dev, usb_snddefctrl(dev), + USB_REQ_SET_ADDRESS, 0, + (dev->devnum), 0, + NULL, 0, USB_CNTL_TIMEOUT); + return res; +} + +/******************************************************************** + * set interface number to interface + */ +int usb_set_interface(struct usb_device *dev, int interface, int alternate) +{ + struct usb_interface_descriptor *if_face = NULL; + int ret, i; + + for (i = 0; i < dev->config.bNumInterfaces; i++) { + if (dev->config.if_desc[i].bInterfaceNumber == interface) { + if_face = &dev->config.if_desc[i]; + break; + } + } + if (!if_face) { + printf("selecting invalid interface %d", interface); + return -1; + } + /* + * We should return now for devices with only one alternate setting. + * According to 9.4.10 of the Universal Serial Bus Specification + * Revision 2.0 such devices can return with a STALL. This results in + * some USB sticks timeouting during initialization and then being + * unusable in U-Boot. + */ + if (if_face->num_altsetting == 1) + return 0; + + ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, + alternate, interface, NULL, 0, + USB_CNTL_TIMEOUT * 5); + if (ret < 0) + return ret; + + return 0; +} + +/******************************************************************** + * set configuration number to configuration + */ +int usb_set_configuration(struct usb_device *dev, int configuration) +{ + int res; + DEBUG_USB("set configuration %d\n", configuration); + /* set setup command */ + res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_CONFIGURATION, 0, + configuration, 0, + NULL, 0, USB_CNTL_TIMEOUT); + if (res == 0) { + dev->toggle[0] = 0; + dev->toggle[1] = 0; + return 0; + } else + return -1; +} + +/******************************************************************** + * set protocol to protocol + */ +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_PROTOCOL, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + protocol, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * set idle + */ +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_IDLE, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (duration << 8) | report_id, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get report + */ +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, + unsigned char id, void *buf, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_REPORT, + USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get class descriptor + */ +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get string index in buffer + */ +int usb_get_string(struct usb_device *dev, unsigned short langid, + unsigned char idx, void *buf, int size) +{ + int i; + int result; + + for (i = 0; i < 3; ++i) { + /* some devices are flaky */ + result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (USB_DT_STRING << 8) + idx, langid, buf, size, + USB_CNTL_TIMEOUT); + + if (result > 0) + break; + } + + return result; +} + + +static void usb_try_string_workarounds(unsigned char *buf, int *length) +{ + int newlength, oldlength = *length; + + for (newlength = 2; newlength + 1 < oldlength; newlength += 2) + { + char c = buf[newlength]; + if ((c < ' ') || (c >= 127) || buf[newlength + 1]) + break; + } + if (newlength > 2) { + buf[0] = newlength; + *length = newlength; + } +} + + +static int usb_string_sub(struct usb_device *dev, unsigned int langid, + unsigned int idx, unsigned char *buf) +{ + int rc; + + /* Try to read the string descriptor by asking for the maximum + * possible number of bytes */ + rc = usb_get_string(dev, langid, idx, buf, 255); + + /* If that failed try to read the descriptor length, then + * ask for just that many bytes */ + if (rc < 2) { + rc = usb_get_string(dev, langid, idx, buf, 2); + if (rc == 2) + rc = usb_get_string(dev, langid, idx, buf, buf[0]); + } + + if (rc >= 2) { + if (!buf[0] && !buf[1]) + usb_try_string_workarounds(buf, &rc); + + /* There might be extra junk at the end of the descriptor */ + if (buf[0] < rc) + rc = buf[0]; + + rc = rc - (rc & 1); /* force a multiple of two */ + } + + if (rc < 2) + rc = -1; + + return rc; +} + + +/******************************************************************** + * usb_string: + * Get string index and translate it to ascii. + * returns string length (> 0) or error (< 0) + */ +int usb_string(struct usb_device *dev, int idx, char *buf, size_t size) +{ + unsigned char mybuf[USB_BUFSIZ]; + unsigned char *tbuf; + int err; + unsigned int u, idx2; + + if (size <= 0 || !buf || !idx) + return -1; + buf[0] = 0; + tbuf = &mybuf[0]; + + /* get langid for strings if it's not yet known */ + if (!dev->have_langid) { + err = usb_string_sub(dev, 0, 0, tbuf); + if (err < 0) { + DEBUG_USB("error getting string descriptor 0 " \ + "(error=%lx)\n", dev->status); + return -1; + } else if (tbuf[0] < 4) { + DEBUG_USB("string descriptor 0 too short\n"); + return -1; + } else { + dev->have_langid = -1; + dev->string_langid = tbuf[2] | (tbuf[3] << 8); + /* always use the first langid listed */ + DEBUG_USB("USB device number %d default " \ + "language ID 0x%x\n", + dev->devnum, dev->string_langid); + } + } + + err = usb_string_sub(dev, dev->string_langid, idx, tbuf); + if (err < 0) + return err; + + size--; /* leave room for trailing NULL char in output buffer */ + for (idx2 = 0, u = 2; u < err; u += 2) { + if (idx2 >= size) + break; + if (tbuf[u+1]) /* high byte */ + buf[idx2++] = '?'; /* non-ASCII character */ + else + buf[idx2++] = tbuf[u]; + } + buf[idx2] = 0; + err = idx2; + return err; +} + + +/******************************************************************** + * USB device handling: + * the USB device are static allocated [USB_MAX_DEVICE]. + */ + + +/* returns a pointer to the device with the index [idx]. + * if the device is not assigned (dev->devnum==-1) returns NULL + */ +struct usb_device *usb_get_dev_index(int idx) +{ + if (usb_dev[idx].devnum == -1) + return NULL; + else + return &usb_dev[idx]; +} + + +/* returns a pointer of a new device structure or NULL, if + * no device struct is available + */ +struct usb_device *usb_alloc_new_device(void) +{ + int i; + DEBUG_USB("New Device %d\n", dev_index); + if (dev_index == USB_MAX_DEVICE) { + printf("ERROR, too many USB Devices, max=%d\n", USB_MAX_DEVICE); + return NULL; + } + /* default Address is 0, real addresses start with 1 */ + usb_dev[dev_index].devnum = dev_index + 1; + usb_dev[dev_index].maxchild = 0; + for (i = 0; i < USB_MAXCHILDREN; i++) + usb_dev[dev_index].children[i] = NULL; + usb_dev[dev_index].parent = NULL; + dev_index++; + return &usb_dev[dev_index - 1]; +} + + +/* + * By the time we get here, the device has gotten a new device ID + * and is in the default state. We need to identify the thing and + * get the ball rolling.. + * + * Returns 0 for success, != 0 for error. + */ +int usb_new_device(struct usb_device *dev) +{ + int addr, err; + int tmp; + unsigned char tmpbuf[USB_BUFSIZ]; + + /* We still haven't set the Address yet */ + addr = dev->devnum; + dev->devnum = 0; + + +#ifdef CONFIG_LEGACY_USB_INIT_SEQ + /* this is the old and known way of initializing devices, it is + * different than what Windows and Linux are doing. Windows and Linux + * both retrieve 64 bytes while reading the device descriptor + * Several USB stick devices report ERR: CTL_TIMEOUT, caused by an + * invalid header while reading 8 bytes as device descriptor. */ + dev->descriptor.bMaxPacketSize0 = 8; /* Start off at 8 bytes */ + dev->maxpacketsize = PACKET_SIZE_8; + dev->epmaxpacketin[0] = 8; + dev->epmaxpacketout[0] = 8; + + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8); + if (err < 8) { + printf("\n USB device not responding, " \ + "giving up (status=%lX)\n", dev->status); + return 1; + } + +#else + /* This is a Windows scheme of initialization sequence, with double + * reset of the device (Linux uses the same sequence) + * Some equipment is said to work only with such init sequence; this + * patch is based on the work by Alan Stern: + * http://sourceforge.net/mailarchive/forum.php? + * thread_id=5729457&forum_id=5398 + */ + + struct usb_device_descriptor *desc; + int port = -1; + struct usb_device *parent = dev->parent; + unsigned short portstatus; + + /* send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is + * only 18 bytes long, this will terminate with a short packet. But if + * the maxpacket size is 8 or 16 the device may be waiting to transmit + * some more, or keeps on retransmitting the 8 byte header. */ + + desc = (struct usb_device_descriptor *)tmpbuf; + dev->descriptor.bMaxPacketSize0 = 64; /* Start off at 64 bytes */ + /* Default to 64 byte max packet size */ + dev->maxpacketsize = PACKET_SIZE_64; + dev->epmaxpacketin[0] = 64; + dev->epmaxpacketout[0] = 64; + + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); + if (err < 0) { + DEBUG_USB("usb_new_device: usb_get_descriptor() failed\n"); + return 1; + } + + dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; + + /* find the port number we're at */ + if (parent) { + int j; + + for (j = 0; j < parent->maxchild; j++) { + if (parent->children[j] == dev) { + port = j; + break; + } + } + if (port < 0) { + printf("usb_new_device:cannot locate device's port.\n"); + return 1; + } + + /* reset the port for the second time */ + err = hub_port_reset(dev->parent, port, &portstatus); + if (err < 0) { + printf("\n Couldn't reset port %i\n", port); + return 1; + } + } +#endif + + dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; + switch (dev->descriptor.bMaxPacketSize0) { + case 8: + dev->maxpacketsize = PACKET_SIZE_8; + break; + case 16: + dev->maxpacketsize = PACKET_SIZE_16; + break; + case 32: + dev->maxpacketsize = PACKET_SIZE_32; + break; + case 64: + dev->maxpacketsize = PACKET_SIZE_64; + break; + } + dev->devnum = addr; + + err = usb_set_address(dev); /* set address */ + + if (err < 0) { + printf("\n USB device not accepting new address " \ + "(error=%lX)\n", dev->status); + return 1; + } + + wait_ms(10); /* Let the SET_ADDRESS settle */ + + tmp = sizeof(dev->descriptor); + + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, + &dev->descriptor, sizeof(dev->descriptor)); + if (err < tmp) { + if (err < 0) + printf("unable to get device descriptor (error=%d)\n", + err); + else + printf("USB device descriptor short read " \ + "(expected %i, got %i)\n", tmp, err); + return 1; + } + /* correct le values */ + __le16_to_cpus(&dev->descriptor.bcdUSB); + __le16_to_cpus(&dev->descriptor.idVendor); + __le16_to_cpus(&dev->descriptor.idProduct); + __le16_to_cpus(&dev->descriptor.bcdDevice); + /* only support for one config for now */ + usb_get_configuration_no(dev, &tmpbuf[0], 0); + usb_parse_config(dev, &tmpbuf[0], 0); + usb_set_maxpacket(dev); + /* we set the default configuration here */ + if (usb_set_configuration(dev, dev->config.bConfigurationValue)) { + printf("failed to set default configuration " \ + "len %d, status %lX\n", dev->act_len, dev->status); + return -1; + } + DEBUG_USB("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n", + dev->descriptor.iManufacturer, dev->descriptor.iProduct, + dev->descriptor.iSerialNumber); + memset(dev->mf, 0, sizeof(dev->mf)); + memset(dev->prod, 0, sizeof(dev->prod)); + memset(dev->serial, 0, sizeof(dev->serial)); + if (dev->descriptor.iManufacturer) + usb_string(dev, dev->descriptor.iManufacturer, + dev->mf, sizeof(dev->mf)); + if (dev->descriptor.iProduct) + usb_string(dev, dev->descriptor.iProduct, + dev->prod, sizeof(dev->prod)); + if (dev->descriptor.iSerialNumber) + usb_string(dev, dev->descriptor.iSerialNumber, + dev->serial, sizeof(dev->serial)); + DEBUG_USB("Manufacturer %s\n", dev->mf); + DEBUG_USB("Product %s\n", dev->prod); + DEBUG_USB("SerialNumber %s\n", dev->serial); + /* now probe if the device is a hub */ + usb_hub_probe(dev, 0); + return 0; +} + + +/* build device Tree */ +void usb_scan_devices(void) +{ + int i; + struct usb_device *dev; + + /* first make all devices unknown */ + for (i = 0; i < USB_MAX_DEVICE; i++) { + memset(&usb_dev[i], 0, sizeof(struct usb_device)); + usb_dev[i].devnum = -1; + } + dev_index = 0; + /* device 0 is always present (root hub, so let it analyze) */ + dev = usb_alloc_new_device(); + if (usb_new_device(dev)) + printf("No USB Device found\n"); + else + printf("%d USB Device(s) found\n", dev_index); + /* insert "driver" if possible */ +#ifdef CONFIG_USB_KEYBOARD + drv_usb_kbd_init(); + DEBUG_USB("scan end\n"); +#endif + +#ifdef CONFIG_USB_MOUSE + drv_usb_mouse_init(); + DEBUG_USB("scan end\n"); +#endif +} + + +/**************************************************************************** + * HUB "Driver" + * Probes device for being a hub and configurate it + */ + +static struct usb_hub_device hub_dev[USB_MAX_HUB]; +static int usb_hub_index; + + +int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB, + USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT); +} + +int usb_clear_hub_feature(struct usb_device *dev, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RT_HUB, feature, + 0, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_clear_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature, + port, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_set_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_FEATURE, USB_RT_PORT, feature, + port, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_get_hub_status(struct usb_device *dev, void *data) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB, 0, 0, + data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); +} + +int usb_get_port_status(struct usb_device *dev, int port, void *data) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port, + data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); +} + + +static void usb_hub_power_on(struct usb_hub_device *hub) +{ + int i; + struct usb_device *dev; + + dev = hub->pusb_dev; + /* Enable power to the ports */ + DEBUG_HUB("enabling power on all ports\n"); + for (i = 0; i < dev->maxchild; i++) { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); + DEBUG_HUB("port %d returns %lX\n", i + 1, dev->status); + wait_ms(hub->desc.bPwrOn2PwrGood * 2); + } +} + +void usb_hub_reset(void) +{ + usb_hub_index = 0; +} + +struct usb_hub_device *usb_hub_allocate(void) +{ + if (usb_hub_index < USB_MAX_HUB) + return &hub_dev[usb_hub_index++]; + + printf("ERROR: USB_MAX_HUB (%d) reached\n", USB_MAX_HUB); + return NULL; +} + +#define MAX_TRIES 5 + +static inline char *portspeed(int portstatus) +{ + if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED)) + return "480 Mb/s"; + else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED)) + return "1.5 Mb/s"; + else + return "12 Mb/s"; +} + +static int hub_port_reset(struct usb_device *dev, int port, + unsigned short *portstat) +{ + int tries; + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + DEBUG_HUB("hub_port_reset: resetting port %d...\n", port); + for (tries = 0; tries < MAX_TRIES; tries++) { + + usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); + wait_ms(200); + + if (usb_get_port_status(dev, port + 1, &portsts) < 0) { + DEBUG_HUB("get_port_status failed status %lX\n", + dev->status); + return -1; + } + portstatus = __le16_to_cpu(portsts.wPortStatus); + portchange = __le16_to_cpu(portsts.wPortChange); + + DEBUG_HUB("portstatus %x, change %x, %s\n", + portstatus, portchange, + portspeed(portstatus)); + + DEBUG_HUB("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \ + " USB_PORT_STAT_ENABLE %d\n", + (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); + + if ((portchange & USB_PORT_STAT_C_CONNECTION) || + !(portstatus & USB_PORT_STAT_CONNECTION)) + return -1; + + if (portstatus & USB_PORT_STAT_ENABLE) + break; + + wait_ms(200); + } + + if (tries == MAX_TRIES) { + DEBUG_HUB("Cannot enable port %i after %i retries, " \ + "disabling port.\n", port + 1, MAX_TRIES); + DEBUG_HUB("Maybe the USB cable is bad?\n"); + return -1; + } + + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET); + *portstat = portstatus; + return 0; +} + + +void usb_hub_port_connect_change(struct usb_device *dev, int port) +{ + struct usb_device *usb; + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + /* Check status */ + if (usb_get_port_status(dev, port + 1, &portsts) < 0) { + DEBUG_HUB("get_port_status failed\n"); + return; + } + + portstatus = __le16_to_cpu(portsts.wPortStatus); + portchange = __le16_to_cpu(portsts.wPortChange); + DEBUG_HUB("portstatus %x, change %x, %s\n", + portstatus, portchange, portspeed(portstatus)); + + /* Clear the connection change status */ + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION); + + /* Disconnect any existing devices under this port */ + if (((!(portstatus & USB_PORT_STAT_CONNECTION)) && + (!(portstatus & USB_PORT_STAT_ENABLE))) || (dev->children[port])) { + DEBUG_HUB("usb_disconnect(&hub->children[port]);\n"); + /* Return now if nothing is connected */ + if (!(portstatus & USB_PORT_STAT_CONNECTION)) + return; + } + wait_ms(200); + + /* Reset the port */ + if (hub_port_reset(dev, port, &portstatus) < 0) { + printf("cannot reset port %i!?\n", port + 1); + return; + } + + wait_ms(200); + + /* Allocate a new device struct for it */ + usb = usb_alloc_new_device(); + if (portstatus & USB_PORT_STAT_HIGH_SPEED) + usb->speed = USB_SPEED_HIGH; + else if (portstatus & USB_PORT_STAT_LOW_SPEED) + usb->speed = USB_SPEED_LOW; + else + usb->speed = USB_SPEED_FULL; + + dev->children[port] = usb; + usb->parent = dev; + /* Run it through the hoops (find a driver, etc) */ + if (usb_new_device(usb)) { + /* Woops, disable the port */ + DEBUG_HUB("hub: disabling port %d\n", port + 1); + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE); + } +} + + +int usb_hub_configure(struct usb_device *dev) +{ + unsigned char buffer[USB_BUFSIZ], *bitmap; + struct usb_hub_descriptor *descriptor; + struct usb_hub_status *hubsts; + int i; + struct usb_hub_device *hub; + + /* "allocate" Hub device */ + hub = usb_hub_allocate(); + if (hub == NULL) + return -1; + hub->pusb_dev = dev; + /* Get the the hub descriptor */ + if (usb_get_hub_descriptor(dev, buffer, 4) < 0) { + DEBUG_HUB("usb_hub_configure: failed to get hub " \ + "descriptor, giving up %lX\n", dev->status); + return -1; + } + descriptor = (struct usb_hub_descriptor *)buffer; + + /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */ + i = descriptor->bLength; + if (i > USB_BUFSIZ) { + DEBUG_HUB("usb_hub_configure: failed to get hub " \ + "descriptor - too long: %d\n", + descriptor->bLength); + return -1; + } + + if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) { + DEBUG_HUB("usb_hub_configure: failed to get hub " \ + "descriptor 2nd giving up %lX\n", dev->status); + return -1; + } + memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength); + /* adjust 16bit values */ + hub->desc.wHubCharacteristics = + __le16_to_cpu(descriptor->wHubCharacteristics); + + /* set the bitmap */ + bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0]; + /* devices not removable by default */ + memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); + bitmap = (unsigned char *)&hub->desc.PortPowerCtrlMask[0]; + memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */ + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++) + hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i]; + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++) + hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i]; + + dev->maxchild = descriptor->bNbrPorts; + DEBUG_HUB("%d ports detected\n", dev->maxchild); + + switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) { + case 0x00: + DEBUG_HUB("ganged power switching\n"); + break; + case 0x01: + DEBUG_HUB("individual port power switching\n"); + break; + case 0x02: + case 0x03: + DEBUG_HUB("unknown reserved power switching mode\n"); + break; + } + + if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) { + DEBUG_HUB("part of a compound device\n"); + } + else { + DEBUG_HUB("standalone hub\n"); + } + + switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) { + case 0x00: + DEBUG_HUB("global over-current protection\n"); + break; + case 0x08: + DEBUG_HUB("individual port over-current protection\n"); + break; + case 0x10: + case 0x18: + DEBUG_HUB("no over-current protection\n"); + break; + } + + DEBUG_HUB("power on to power good time: %dms\n", + descriptor->bPwrOn2PwrGood * 2); + DEBUG_HUB("hub controller current requirement: %dmA\n", + descriptor->bHubContrCurrent); + + for (i = 0; i < dev->maxchild; i++) + DEBUG_HUB("port %d is%s removable\n", i + 1, + hub->desc.DeviceRemovable[(i + 1) / 8] & \ + (1 << ((i + 1) % 8)) ? " not" : ""); + + if (sizeof(struct usb_hub_status) > USB_BUFSIZ) { + DEBUG_HUB("usb_hub_configure: failed to get Status - " \ + "too long: %d\n", descriptor->bLength); + return -1; + } + + if (usb_get_hub_status(dev, buffer) < 0) { + DEBUG_HUB("usb_hub_configure: failed to get Status %lX\n", + dev->status); + return -1; + } + + hubsts = (struct usb_hub_status *)buffer; + DEBUG_HUB("get_hub_status returned status %X, change %X\n", + __le16_to_cpu(hubsts->wHubStatus), + __le16_to_cpu(hubsts->wHubChange)); + DEBUG_HUB("local power source is %s\n", + (__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \ + "lost (inactive)" : "good"); + DEBUG_HUB("%sover-current condition exists\n", + (__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \ + "" : "no "); + usb_hub_power_on(hub); + + + + for (i = 0; i < dev->maxchild; i++) { + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + wait_ms (100); /* GALVEZ: add delay for MiNT/TOS */ + + if (usb_get_port_status(dev, i + 1, &portsts) < 0) { + DEBUG_HUB("get_port_status failed\n"); + continue; + } + + portstatus = __le16_to_cpu(portsts.wPortStatus); + portchange = __le16_to_cpu(portsts.wPortChange); + DEBUG_HUB("Port %d Status %X Change %X\n", + i + 1, portstatus, portchange); + + if (portchange & USB_PORT_STAT_C_CONNECTION) { + DEBUG_HUB("port %d connection change\n", i + 1); + usb_hub_port_connect_change(dev, i); + } + + if (portchange & USB_PORT_STAT_C_ENABLE) { + DEBUG_HUB("port %d enable change, status %x\n", + i + 1, portstatus); + usb_clear_port_feature(dev, i + 1, + USB_PORT_FEAT_C_ENABLE); + + /* EM interference sometimes causes bad shielded USB + * devices to be shutdown by the hub, this hack enables + * them again. Works at least with mouse driver */ + if (!(portstatus & USB_PORT_STAT_ENABLE) && + (portstatus & USB_PORT_STAT_CONNECTION) && + ((dev->children[i]))) { + DEBUG_HUB("already running port %i " \ + "disabled by hub (EMI?), " \ + "re-enabling...\n", i + 1); + usb_hub_port_connect_change(dev, i); + } + } + if (portstatus & USB_PORT_STAT_SUSPEND) { + DEBUG_HUB("port %d suspend change\n", i + 1); + usb_clear_port_feature(dev, i + 1, + USB_PORT_FEAT_SUSPEND); + } + + if (portchange & USB_PORT_STAT_C_OVERCURRENT) { + DEBUG_HUB("port %d over-current change\n", i + 1); + usb_clear_port_feature(dev, i + 1, + USB_PORT_FEAT_C_OVER_CURRENT); + usb_hub_power_on(hub); + } + + if (portchange & USB_PORT_STAT_C_RESET) { + DEBUG_HUB("port %d reset change\n", i + 1); + usb_clear_port_feature(dev, i + 1, + USB_PORT_FEAT_C_RESET); + } + } /* end for i all ports */ + return 0; +} + +int usb_hub_probe(struct usb_device *dev, int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int ret; + + iface = &dev->config.if_desc[ifnum]; + /* Is it a hub? */ + if (iface->bInterfaceClass != USB_CLASS_HUB) + return 0; + /* Some hubs have a subclass of 1, which AFAICT according to the */ + /* specs is not defined, but it works */ + if ((iface->bInterfaceSubClass != 0) && + (iface->bInterfaceSubClass != 1)) + return 0; + /* Multiple endpoints? What kind of mutant ninja-hub is this? */ + if (iface->bNumEndpoints != 1) + return 0; + ep = &iface->ep_desc[0]; + /* Output endpoint? Curiousier and curiousier.. */ + if (!(ep->bEndpointAddress & USB_DIR_IN)) + return 0; + /* If it's not an interrupt endpoint, we'd better punt! */ + if ((ep->bmAttributes & 3) != 3) + return 0; + /* We found a hub */ + DEBUG_HUB("USB hub found\n"); + ret = usb_hub_configure(dev); + + return ret; +} + +/* EOF */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/usb.h b/BaS_codewarrior/FireBee/trunk/usb/store/usb.h new file mode 100644 index 0000000..ce2cd93 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/usb.h @@ -0,0 +1,470 @@ +/* + * Modified for Atari by David Gálvez 2010 + * Modified for Atari by Didier Mequignon 2009 + * + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_H_ +#define _USB_H_ + +#include +#include +#include +#include +#include + +#include "host/ohci-pci/mod_devicetable.h" +#include "usb_defs.h" +#include "asm-m68k/types.h" +#include "asm-m68k/byteorder.h" +#include "part.h" + +#ifdef PCI_XBIOS + +#define in8(addr) fast_read_mem_byte(usb_handle,addr) +#define in16r(addr) fast_read_mem_word(usb_handle,addr) +#define in32r(addr) fast_read_mem_longword(usb_handle,addr) +#define out8(addr,val) write_mem_byte(usb_handle,addr,val) +#define out16r(addr,val) write_mem_word(usb_handle,addr,val) +#define out32r(addr,val) write_mem_longword(usb_handle,addr,val) + +#else /* !PCI_XBIOS */ + +extern long *tab_funcs_pci; + +#define in8(addr) Fast_read_mem_byte(usb_handle,addr) +#define in16r(addr) Fast_read_mem_word(usb_handle,addr) +#define in32r(addr) Fast_read_mem_longword(usb_handle,addr) +#define out8(addr,val) Write_mem_byte(usb_handle,addr,val) +#define out16r(addr,val) Write_mem_word(usb_handle,addr,val) +#define out32r(addr,val) Write_mem_longword(usb_handle,addr,val) + +#endif /* PCI_XBIOS */ + + +/* Everything is aribtrary */ +#define USB_ALTSETTINGALLOC 4 +#define USB_MAXALTSETTING 128 /* Hard limit */ + +#define USB_MAX_DEVICE 32 +#define USB_MAXCONFIG 8 +#define USB_MAXINTERFACES 8 +#define USB_MAXENDPOINTS 16 +#define USB_MAXCHILDREN 8 /* This is arbitrary */ +#define USB_MAX_HUB 16 + +#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ + +/* String descriptor */ +struct usb_string_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wData[1]; +} __attribute__ ((packed)); + +/* device request (setup) */ +struct devrequest { + unsigned char requesttype; + unsigned char request; + unsigned short value; + unsigned short index; + unsigned short length; +} __attribute__ ((packed)); + +/* All standard descriptors have these 2 fields in common */ +struct usb_descriptor_header { + unsigned char bLength; + unsigned char bDescriptorType; +} __attribute__ ((packed)); + +/* Device descriptor */ +struct usb_device_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short bcdUSB; + unsigned char bDeviceClass; + unsigned char bDeviceSubClass; + unsigned char bDeviceProtocol; + unsigned char bMaxPacketSize0; + unsigned short idVendor; + unsigned short idProduct; + unsigned short bcdDevice; + unsigned char iManufacturer; + unsigned char iProduct; + unsigned char iSerialNumber; + unsigned char bNumConfigurations; +} __attribute__ ((packed)); + +/* Endpoint descriptor */ +struct usb_endpoint_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bEndpointAddress; + unsigned char bmAttributes; + unsigned short wMaxPacketSize; + unsigned char bInterval; + unsigned char bRefresh; + unsigned char bSynchAddress; +} __attribute__ ((packed)) __attribute__ ((aligned(2))); + +/* Interface descriptor */ +struct usb_interface_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bInterfaceNumber; + unsigned char bAlternateSetting; + unsigned char bNumEndpoints; + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + unsigned char iInterface; + + unsigned char no_of_ep; + unsigned char num_altsetting; + unsigned char act_altsetting; + + struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; +} __attribute__ ((packed)); + + +/* Configuration descriptor information.. */ +struct usb_config_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wTotalLength; + unsigned char bNumInterfaces; + unsigned char bConfigurationValue; + unsigned char iConfiguration; + unsigned char bmAttributes; + unsigned char MaxPower; + + unsigned char no_of_if; /* number of interfaces */ + struct usb_interface_descriptor if_desc[USB_MAXINTERFACES]; +} __attribute__ ((packed)); + +enum { + /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */ + PACKET_SIZE_8 = 0, + PACKET_SIZE_16 = 1, + PACKET_SIZE_32 = 2, + PACKET_SIZE_64 = 3, +}; + +struct usb_device { + int devnum; /* Device number on USB bus */ + int speed; /* full/low/high */ + char mf[32]; /* manufacturer */ + char prod[32]; /* product */ + char serial[32]; /* serial number */ + + /* Maximum packet size; one of: PACKET_SIZE_* */ + int maxpacketsize; + /* one bit for each endpoint ([0] = IN, [1] = OUT) */ + unsigned int toggle[2]; + /* endpoint halts; one bit per endpoint # & direction; + * [0] = IN, [1] = OUT + */ + unsigned int halted[2]; + int epmaxpacketin[16]; /* INput endpoint specific maximums */ + int epmaxpacketout[16]; /* OUTput endpoint specific maximums */ + + int configno; /* selected config number */ + struct usb_device_descriptor descriptor; /* Device Descriptor */ + struct usb_config_descriptor config; /* config descriptor */ + + int have_langid; /* whether string_langid is valid yet */ + int string_langid; /* language ID for strings */ + int (*irq_handle)(struct usb_device *dev); + unsigned long irq_status; + int irq_act_len; /* transfered bytes */ + void *privptr; + /* + * Child devices - if this is a hub device + * Each instance needs its own set of data structures. + */ + unsigned long status; + int act_len; /* transfered bytes */ + int maxchild; /* Number of ports if hub */ + int portnr; + struct usb_device *parent; + struct usb_device *children[USB_MAXCHILDREN]; +}; + +/********************************************************************** + * this is how the lowlevel part communicate with the outer world + */ + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ + defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ + defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \ + defined(CONFIG_USB_ARANYM_HCD) + +#ifdef PCI_XBIOS +int usb_lowlevel_init(long handle, const struct pci_device_id *ent); +#else +int usb_lowlevel_init(void); +#endif + +int usb_lowlevel_stop(void); +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len); +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup); +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval); + +#ifdef CONFIG_USB_INTERRUPT_POLLING +void usb_event_poll(void); +#else +void usb_enable_interrupt(int enable); +#endif + +/* Defines */ +#define USB_UHCI_VEND_ID 0x8086 +#define USB_UHCI_DEV_ID 0x7112 + +#else +#error USB Lowlevel not defined +#endif + +#ifdef CONFIG_USB_STORAGE + +#define USB_MAX_STOR_DEV 2 /* GALVEZ: DEFAULT 5 */ +block_dev_desc_t *usb_stor_get_dev(int idx); +int usb_stor_scan(void); +int usb_stor_info(void); + +#endif + +#ifdef CONFIG_USB_MOUSE +int drv_usb_mouse_init(void); +int usb_mouse_deregister(void); +#endif + + +#ifdef CONFIG_USB_KEYBOARD +int drv_usb_kbd_init(void); +int usb_kbd_deregister(void); +#endif + +/* memory */ +void *usb_malloc(long amount); +int usb_free(void *addr); +int usb_mem_init(void); +void usb_mem_stop(void); + + +/* routines */ +#ifdef PCI_XBIOS +int usb_init(long handle, const struct pci_device_id *ent); /* initialize the USB Controller */ +#else +int usb_init(void); /* initialize the USB Controller */ +#endif +int usb_stop(void); /* stop the USB Controller */ + + +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol); +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, + int report_id); +struct usb_device *usb_get_dev_index(int idx); +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short idx, + void *data, unsigned short size, int timeout); +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout); +int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, int interval); +void usb_disable_asynch(int disable); +int usb_maxpacket(struct usb_device *dev, unsigned long pipe); +inline void wait_ms(unsigned long ms); +int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer, + int cfgno); +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, + unsigned char id, void *buf, int size); +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, + int size); +int usb_clear_halt(struct usb_device *dev, int pipe); +int usb_string(struct usb_device *dev, int idx, char *buf, size_t size); +int usb_set_interface(struct usb_device *dev, int interface, int alternate); + +/* big endian -> little endian conversion */ +/* some CPUs are already little endian e.g. the ARM920T */ +#define __swap_16(x) \ + ({ unsigned short x_ = (unsigned short)x; \ + (unsigned short)( \ + ((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \ + }) +#define __swap_32(x) \ + ({ unsigned long x_ = (unsigned long)x; \ + (unsigned long)( \ + ((x_ & 0x000000FFUL) << 24) | \ + ((x_ & 0x0000FF00UL) << 8) | \ + ((x_ & 0x00FF0000UL) >> 8) | \ + ((x_ & 0xFF000000UL) >> 24)); \ + }) + +#ifdef __LITTLE_ENDIAN +# define swap_16(x) (x) +# define swap_32(x) (x) +#else +# define swap_16(x) __swap_16(x) +# define swap_32(x) __swap_32(x) +#endif + +/* + * Calling this entity a "pipe" is glorifying it. A USB pipe + * is something embarrassingly simple: it basically consists + * of the following information: + * - device number (7 bits) + * - endpoint number (4 bits) + * - current Data0/1 state (1 bit) + * - direction (1 bit) + * - speed (2 bits) + * - max packet size (2 bits: 8, 16, 32 or 64) + * - pipe type (2 bits: control, interrupt, bulk, isochronous) + * + * That's 18 bits. Really. Nothing more. And the USB people have + * documented these eighteen bits as some kind of glorious + * virtual data structure. + * + * Let's not fall in that trap. We'll just encode it as a simple + * unsigned int. The encoding is: + * + * - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64) + * - direction: bit 7 (0 = Host-to-Device [Out], + * (1 = Device-to-Host [In]) + * - device: bits 8-14 + * - endpoint: bits 15-18 + * - Data0/1: bit 19 + * - speed: bit 26 (0 = Full, 1 = Low Speed, 2 = High) + * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, + * 10 = control, 11 = bulk) + * + * Why? Because it's arbitrary, and whatever encoding we select is really + * up to us. This one happens to share a lot of bit positions with the UHCI + * specification, so that much of the uhci driver can just mask the bits + * appropriately. + */ +/* Create various pipes... */ +#define create_pipe(dev,endpoint) \ + (((dev)->devnum << 8) | (endpoint << 15) | \ + ((dev)->speed << 26) | (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->speed << 26) + +#define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | \ + default_pipe(dev)) +#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | \ + default_pipe(dev) | \ + USB_DIR_IN) + +/* The D0/D1 toggle bits */ +#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1) +#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep)) +#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \ + ((dev)->toggle[out] & \ + ~(1 << ep)) | ((bit) << ep)) + +/* Endpoint halt control/status */ +#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1) +#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep))) +#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep))) +#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep))) + +#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : \ + USB_PID_OUT) + +#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1) +#define usb_pipein(pipe) (((pipe) >> 7) & 1) +#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f) +#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) +#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) +#define usb_pipedata(pipe) (((pipe) >> 19) & 1) +#define usb_pipespeed(pipe) (((pipe) >> 26) & 3) +#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW) +#define usb_pipetype(pipe) (((pipe) >> 30) & 3) +#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) +#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) +#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL) +#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK) + + +/************************************************************************* + * Hub Stuff + */ +struct usb_port_status { + unsigned short wPortStatus; + unsigned short wPortChange; +} __attribute__ ((packed)); + +struct usb_hub_status { + unsigned short wHubStatus; + unsigned short wHubChange; +} __attribute__ ((packed)); + + +/* Hub descriptor */ +struct usb_hub_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bNbrPorts; + unsigned short wHubCharacteristics; + unsigned char bPwrOn2PwrGood; + unsigned char bHubContrCurrent; + unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8]; + unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8]; + /* DeviceRemovable and PortPwrCtrlMask want to be variable-length + bitmaps that hold max 255 entries. (bit0 is ignored) */ +} __attribute__ ((packed)); + + +struct usb_hub_device { + struct usb_device *pusb_dev; + struct usb_hub_descriptor desc; +}; + +#endif /*_USB_H_ */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/usb_defs.h b/BaS_codewarrior/FireBee/trunk/usb/store/usb_defs.h new file mode 100644 index 0000000..8032e57 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/usb_defs.h @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_DEFS_H_ +#define _USB_DEFS_H_ + +/* USB constants */ + +/* Device and/or Interface Class codes */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_DATA 10 +#define USB_CLASS_VENDOR_SPEC 0xff + +/* some HID sub classes */ +#define USB_SUB_HID_NONE 0 +#define USB_SUB_HID_BOOT 1 + +/* some UID Protocols */ +#define USB_PROT_HID_NONE 0 +#define USB_PROT_HID_KEYBOARD 1 +#define USB_PROT_HID_MOUSE 2 + + +/* Sub STORAGE Classes */ +#define US_SC_RBC 1 /* Typically, flash devices */ +#define US_SC_8020 2 /* CD-ROM */ +#define US_SC_QIC 3 /* QIC-157 Tapes */ +#define US_SC_UFI 4 /* Floppy */ +#define US_SC_8070 5 /* Removable media */ +#define US_SC_SCSI 6 /* Transparent */ +#define US_SC_MIN US_SC_RBC +#define US_SC_MAX US_SC_SCSI + +/* STORAGE Protocols */ +#define US_PR_CB 1 /* Control/Bulk w/o interrupt */ +#define US_PR_CBI 0 /* Control/Bulk/Interrupt */ +#define US_PR_BULK 0x50 /* bulk only */ + +/* USB types */ +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* USB recipients */ +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* USB directions */ +#define USB_DIR_OUT 0 +#define USB_DIR_IN 0x80 + +/* USB device speeds */ +#define USB_SPEED_FULL 0x0 /* 12Mbps */ +#define USB_SPEED_LOW 0x1 /* 1.5Mbps */ +#define USB_SPEED_HIGH 0x2 /* 480Mbps */ +#define USB_SPEED_RESERVED 0x3 + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +#define USB_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_DT_HUB (USB_TYPE_CLASS | 0x09) + +/* Descriptor sizes per descriptor type */ +#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +#define USB_DT_HUB_NONVAR_SIZE 7 +#define USB_DT_HID_SIZE 9 + +/* Endpoints */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 + +/* USB Packet IDs (PIDs) */ +#define USB_PID_UNDEF_0 0xf0 +#define USB_PID_OUT 0xe1 +#define USB_PID_ACK 0xd2 +#define USB_PID_DATA0 0xc3 +#define USB_PID_UNDEF_4 0xb4 +#define USB_PID_SOF 0xa5 +#define USB_PID_UNDEF_6 0x96 +#define USB_PID_UNDEF_7 0x87 +#define USB_PID_UNDEF_8 0x78 +#define USB_PID_IN 0x69 +#define USB_PID_NAK 0x5a +#define USB_PID_DATA1 0x4b +#define USB_PID_PREAMBLE 0x3c +#define USB_PID_SETUP 0x2d +#define USB_PID_STALL 0x1e +#define USB_PID_UNDEF_F 0x0f + +/* Standard requests */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +/* HID requests */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + + +/* "pipe" definitions */ + +#define PIPE_ISOCHRONOUS 0 +#define PIPE_INTERRUPT 1 +#define PIPE_CONTROL 2 +#define PIPE_BULK 3 +#define PIPE_DEVEP_MASK 0x0007ff00 + +#define USB_ISOCHRONOUS 0 +#define USB_INTERRUPT 1 +#define USB_CONTROL 2 +#define USB_BULK 3 + +/* USB-status codes: */ +#define USB_ST_ACTIVE 0x1 /* TD is active */ +#define USB_ST_STALLED 0x2 /* TD is stalled */ +#define USB_ST_BUF_ERR 0x4 /* buffer error */ +#define USB_ST_BABBLE_DET 0x8 /* Babble detected */ +#define USB_ST_NAK_REC 0x10 /* NAK Received*/ +#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */ +#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */ +#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */ + + +/************************************************************************* + * Hub defines + */ + +/* + * Hub request types + */ + +#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE) +#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER) + +/* + * Hub Class feature numbers + */ +#define C_HUB_LOCAL_POWER 0 +#define C_HUB_OVER_CURRENT 1 + +/* + * Port feature numbers + */ +#define USB_PORT_FEAT_CONNECTION 0 +#define USB_PORT_FEAT_ENABLE 1 +#define USB_PORT_FEAT_SUSPEND 2 +#define USB_PORT_FEAT_OVER_CURRENT 3 +#define USB_PORT_FEAT_RESET 4 +#define USB_PORT_FEAT_POWER 8 +#define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_HIGHSPEED 10 +#define USB_PORT_FEAT_C_CONNECTION 16 +#define USB_PORT_FEAT_C_ENABLE 17 +#define USB_PORT_FEAT_C_SUSPEND 18 +#define USB_PORT_FEAT_C_OVER_CURRENT 19 +#define USB_PORT_FEAT_C_RESET 20 + +/* wPortStatus bits */ +#define USB_PORT_STAT_CONNECTION 0x0001 +#define USB_PORT_STAT_ENABLE 0x0002 +#define USB_PORT_STAT_SUSPEND 0x0004 +#define USB_PORT_STAT_OVERCURRENT 0x0008 +#define USB_PORT_STAT_RESET 0x0010 +#define USB_PORT_STAT_POWER 0x0100 +#define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */ +#define USB_PORT_STAT_SPEED \ + (USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED) + +/* wPortChange bits */ +#define USB_PORT_STAT_C_CONNECTION 0x0001 +#define USB_PORT_STAT_C_ENABLE 0x0002 +#define USB_PORT_STAT_C_SUSPEND 0x0004 +#define USB_PORT_STAT_C_OVERCURRENT 0x0008 +#define USB_PORT_STAT_C_RESET 0x0010 + +/* wHubCharacteristics (masks) */ +#define HUB_CHAR_LPSM 0x0003 +#define HUB_CHAR_COMPOUND 0x0004 +#define HUB_CHAR_OCPM 0x0018 + +/* + *Hub Status & Hub Change bit masks + */ +#define HUB_STATUS_LOCAL_POWER 0x0001 +#define HUB_STATUS_OVERCURRENT 0x0002 + +#define HUB_CHANGE_LOCAL_POWER 0x0001 +#define HUB_CHANGE_OVERCURRENT 0x0002 + +#endif /*_USB_DEFS_H_ */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/usb_mem.c b/BaS_codewarrior/FireBee/trunk/usb/store/usb_mem.c new file mode 100644 index 0000000..7397d12 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/usb_mem.c @@ -0,0 +1,220 @@ +/* + * usb_mem.c + * + * based from Emutos / BDOS + * + * Copyright (c) 2001 Lineo, Inc. + * + * Authors: Karl T. Braun, Martin Doering, Laurent Vogel + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. + */ + +#include +#include +#include + +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + +#define USB_BUFFER_SIZE 0x10000 + +static void *usb_buffer; + +/* MD - Memory Descriptor */ + +#define MD struct _md_ + +MD +{ + MD *m_link; + long m_start; + long m_length; +}; + +/* MPB - Memory Partition Block */ + +#define MPB struct _mpb + +MPB +{ + MD *mp_mfl; + MD *mp_mal; + MD *mp_rover; +}; + +#define MAXMD 100 + +static int count_md; +static MD tab_md[MAXMD]; +static MPB pmd; + +static MD *ffit(long amount, MPB *mp) +{ + MD *p,*q,*p1; /* free list is composed of MD's */ + int maxflg; + long maxval; + if(amount != -1) + { + amount += 15; /* 16 bytes alignment */ + amount &= 0xFFFFFFF0; + } + if((q = mp->mp_rover) == 0) /* get rotating pointer */ + return(0) ; + maxval = 0; + maxflg = (amount == -1 ? TRUE : FALSE) ; + p = q->m_link; /* start with next MD */ + do /* search the list for an MD with enough space */ + { + if(p == 0) + { + /* at end of list, wrap back to start */ + q = (MD *) &mp->mp_mfl; /* q => mfl field */ + p = q->m_link; /* p => 1st MD */ + } + if((!maxflg) && (p->m_length >= amount)) + { + /* big enough */ + if(p->m_length == amount) + q->m_link = p->m_link; /* take the whole thing */ + else + { + /* break it up - 1st allocate a new + MD to describe the remainder */ + if(count_md >= MAXMD) + return(0); + p1 = &tab_md[count_md++]; + /* init new MD */ + p1->m_length = p->m_length - amount; + p1->m_start = p->m_start + amount; + p1->m_link = p->m_link; + p->m_length = amount; /* adjust allocated block */ + q->m_link = p1; + } + /* link allocate block into allocated list, + mark owner of block, & adjust rover */ + p->m_link = mp->mp_mal; + mp->mp_mal = p; + mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q); + return(p); /* got some */ + } + else if(p->m_length > maxval) + maxval = p->m_length; + p = ( q=p )->m_link; + } + while(q != mp->mp_rover); + /* return either the max, or 0 (error) */ + if(maxflg) + { + maxval -= 15; /* 16 bytes alignment */ + if(maxval < 0) + maxval = 0; + else + maxval &= 0xFFFFFFF0; + } + return(maxflg ? (MD *) maxval : 0); +} + +static void freeit(MD *m, MPB *mp) +{ + MD *p, *q; + q = 0; + for(p = mp->mp_mfl; p ; p = (q=p) -> m_link) + { + if(m->m_start <= p->m_start) + break; + } + m->m_link = p; + if(q) + q->m_link = m; + else + mp->mp_mfl = m; + if(!mp->mp_rover) + mp->mp_rover = m; + if(p) + { + if(m->m_start + m->m_length == p->m_start) + { /* join to higher neighbor */ + m->m_length += p->m_length; + m->m_link = p->m_link; + if(p == mp->mp_rover) + mp->mp_rover = m; + if(count_md>=0) + count_md--; + } + } + if(q) + { + if(q->m_start + q->m_length == m->m_start) + { /* join to lower neighbor */ + q->m_length += m->m_length; + q->m_link = m->m_link; + if(m == mp->mp_rover) + mp->mp_rover = q; + if(count_md>=0) + count_md--; + } + } +} + +int usb_free(void *addr) +{ + MD *p,**q; + MPB *mpb; + mpb = &pmd; + if(usb_buffer == NULL) + return(EFAULT); + for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link)) + { + if((long)addr == p->m_start) + break; + } + if(!p) + return(EFAULT); + *q = p->m_link; + freeit(p,mpb); + return(0); +} + +void *usb_malloc(long amount) +{ + MD *m; + if(usb_buffer == NULL) + return(NULL); + if(amount == -1L) + return((void *)ffit(-1L,&pmd)); + if(amount <= 0 ) + return(0); + if((amount & 1)) + amount++; + m = ffit(amount,&pmd); + if(m == NULL) + return(NULL); + return((void *)m->m_start); +} + +int usb_mem_init(void) +{ + usb_buffer = (void *)Mxalloc(USB_BUFFER_SIZE + 16, 0); /* STRAM - cache in writethough */ + if(usb_buffer == NULL) + return(-1); + pmd.mp_mfl = pmd.mp_rover = &tab_md[0]; + tab_md[0].m_link = (MD *)NULL; + tab_md[0].m_start = ((long)usb_buffer + 15) & ~15; + tab_md[0].m_length = USB_BUFFER_SIZE; + pmd.mp_mal = (MD *)NULL; + count_md = 1; + return(0); +} + +void usb_mem_stop(void) +{ + if(usb_buffer != NULL) + Mfree(usb_buffer); +} + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/usb_storage.c b/BaS_codewarrior/FireBee/trunk/usb/store/usb_storage.c new file mode 100644 index 0000000..e48724e --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/usb_storage.c @@ -0,0 +1,1632 @@ +/* + * Modified for Atari by David Gálvez 2010 + * Modified for Atari by Didier Mequignon 2009 + * + * Most of this source has been derived from the Linux USB + * project: + * (c) 1999-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net) + * (c) 2000 David L. Brown, Jr. (usb-storage@davidb.org) + * (c) 1999 Michael Gee (michael@linuxspecific.com) + * (c) 2000 Yggdrasil Computing, Inc. + * + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * For BBB support (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * BBB support based on /sys/dev/usb/umass.c from + * FreeBSD. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Note: + * Currently only the CBI transport protocoll has been implemented, and it + * is only tested with a TEAC USB Floppy. Other Massstorages with CBI or CB + * transport protocoll may work as well. + */ +/* + * New Note: + * Support for USB Mass Storage Devices (BBB) has been added. It has + * only been tested with USB memory sticks. + */ + +#include "config.h" +#include "usb.h" +#include "scsi.h" +#include "super.h" +#include "debug.h" + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \ + || defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) +#ifdef CONFIG_USB_STORAGE + +/* + * Extra debug to the one availble in config.h + * These three extra debug levels go always to the log file + * uncomment them if you want them on + */ +//#define USB_STOR_DEBUG +//#define BBB_COMDAT_TRACE +//#define BBB_XPORT_TRACE + + +extern void udelay(long usec); +extern void ltoa(char *buf, long n, unsigned long base); + +/* direction table -- this indicates the direction of the data + * transfer for each command code -- a 1 indicates input + */ +unsigned char us_direction[256/8] = { + 0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77, + 0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +#define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1) + +static unsigned char *usb_stor_buf; +static ccb usb_ccb; + +/* + * CBI style + */ + +#define US_CBI_ADSC 0 + +/* + * BULK only + */ +#define US_BBB_RESET 0xff +#define US_BBB_GET_MAX_LUN 0xfe + +/* Command Block Wrapper */ +typedef struct { + __u32 dCBWSignature; +# define CBWSIGNATURE 0x43425355 + __u32 dCBWTag; + __u32 dCBWDataTransferLength; + __u8 bCBWFlags; +# define CBWFLAGS_OUT 0x00 +# define CBWFLAGS_IN 0x80 + __u8 bCBWLUN; + __u8 bCDBLength; +# define CBWCDBLENGTH 16 + __u8 CBWCDB[CBWCDBLENGTH]; +} umass_bbb_cbw_t; +#define UMASS_BBB_CBW_SIZE 31 +static __u32 CBWTag; + +/* Command Status Wrapper */ +typedef struct { + __u32 dCSWSignature; +# define CSWSIGNATURE 0x53425355 + __u32 dCSWTag; + __u32 dCSWDataResidue; + __u8 bCSWStatus; +# define CSWSTATUS_GOOD 0x0 +# define CSWSTATUS_FAILED 0x1 +# define CSWSTATUS_PHASE 0x2 +} umass_bbb_csw_t; +#define UMASS_BBB_CSW_SIZE 13 + +//#define USB_MAX_STOR_DEV 5 /* GALVEZ: Defined in usb.h */ +static int usb_max_devs; /* number of highest available usb device */ + +static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV]; + +struct us_data; +typedef int (*trans_cmnd)(ccb *cb, struct us_data *data); +typedef int (*trans_reset)(struct us_data *data); + +struct us_data { + struct usb_device *pusb_dev; /* this usb_device */ + + unsigned int flags; /* from filter initially */ + unsigned char ifnum; /* interface number */ + unsigned char ep_in; /* in endpoint */ + unsigned char ep_out; /* out ....... */ + unsigned char ep_int; /* interrupt . */ + unsigned char subclass; /* as in overview */ + unsigned char protocol; /* .............. */ + unsigned char attention_done; /* force attn on first cmd */ + unsigned short ip_data; /* interrupt data */ + int action; /* what to do */ + int ip_wanted; /* needed */ + int *irq_handle; /* for USB int requests */ + unsigned int irqpipe; /* pipe for release_irq */ + unsigned char irqmaxp; /* max packed for irq Pipe */ + unsigned char irqinterval; /* Intervall for IRQ Pipe */ + ccb *srb; /* current srb */ + trans_reset transport_reset; /* reset routine */ + trans_cmnd transport; /* transport routine */ +}; + +static struct us_data usb_stor[USB_MAX_STOR_DEV]; + +#define USB_STOR_TRANSPORT_GOOD 0 +#define USB_STOR_TRANSPORT_FAILED -1 +#define USB_STOR_TRANSPORT_ERROR -2 + +#define DEFAULT_SECTOR_SIZE 512 + +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 +#define DOS_MBR 0 +#define DOS_PBR 1 +#define DOS_FS_TYPE_OFFSET 0x36 + +typedef struct dos_partition { + unsigned char boot_ind; /* 0x80 - active */ + unsigned char head; /* starting head */ + unsigned char sector; /* starting sector */ + unsigned char cyl; /* starting cylinder */ + unsigned char sys_ind; /* What partition type */ + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ + unsigned char start4[4]; /* starting sector counting from 0 */ + unsigned char size4[4]; /* nr of sectors in partition */ +} dos_partition_t; + +typedef struct disk_partition { + unsigned long type; + unsigned long start; /* # of first block in partition */ + unsigned long size; /* number of blocks in partition */ + unsigned long blksz; /* block size in bytes */ +} disk_partition_t; + +//extern unsigned long swap_long(unsigned long val); +#define le32_to_int(a) swap_32(*(unsigned long *)a) + +int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss); +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer); +unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer); +struct usb_device * usb_get_dev_index(int index); +void uhci_show_temp_int_td(void); + +block_dev_desc_t *usb_stor_get_dev(int idx) +{ + return(idx < USB_MAX_STOR_DEV) ? &usb_dev_desc[idx] : NULL; +} + +void init_part(block_dev_desc_t *dev_desc) +{ + unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE); + if(buffer == NULL) + return; + if((dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1) + || (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa)) + { + usb_free(buffer); + return; + } + dev_desc->part_type = PART_TYPE_DOS; + DEBUG_STORAGE("DOS partition table found\r\n"); +#ifdef USB_STOR_DEBUG + { + debug_init("usb.log"); + int j; + for(j = 0; j < 512; j++) + { + if((j & 15) == 0) + debug("\r\n%04X ", j); + debug("%02X ", buffer[j]); + if((j & 15) == 15) + { + int k; + for(k = j-15; k <= j; k++) + { + if(buffer[k] < ' ' || buffer[k] >= 127) + debug("."); + else + debug("%c", buffer[k]); + } + } + } + debug("\r\n"); + debug_exit(); + } +#endif + usb_free(buffer); +} + +static inline int is_extended(int part_type) +{ + return(part_type == 0x5 || part_type == 0xf || part_type == 0x85); +} + +/* Print a partition that is relative to its Extended partition table + */ +static int get_partition_info_extended(block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num, int which_part, disk_partition_t *info) +{ + dos_partition_t *pt; + int i; + unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE); + + if(buffer == NULL) + return -1; + if(dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (unsigned long *)buffer) != 1) + { + DEBUG_STORAGE("Can't read partition table on %d:%d\r\n", dev_desc->dev, ext_part_sector); + usb_free(buffer); + return -1; + } + if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) + { + DEBUG_STORAGE("bad MBR sector signature 0x%02x%02x\n", buffer[DOS_PART_MAGIC_OFFSET], buffer[DOS_PART_MAGIC_OFFSET + 1]); + usb_free(buffer); + return -1; + } + /* Print all primary/logical partitions */ + pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET); + for(i = 0; i < 4; i++, pt++) + { + /* fdisk does not show the extended partitions that are not in the MBR */ + if((pt->sys_ind != 0) && (part_num == which_part) && (is_extended(pt->sys_ind) == 0)) + { + info->type = (unsigned long)pt->sys_ind; + info->blksz = 512; + info->start = ext_part_sector + le32_to_int(pt->start4); + info->size = le32_to_int(pt->size4); + DEBUG_STORAGE("DOS partition at offset 0x%lx, size 0x%lx, type 0x%x %s\r\n", + info->start, info->size, pt->sys_ind, + (is_extended(pt->sys_ind) ? " Extd" : "")); + usb_free(buffer); + return 0; + } + /* Reverse engr the fdisk part# assignment rule! */ + if((ext_part_sector == 0) || (pt->sys_ind != 0 && !is_extended (pt->sys_ind))) + part_num++; + } + /* Follows the extended partitions */ + pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET); + for(i = 0; i < 4; i++, pt++) + { + if(is_extended(pt->sys_ind)) + { + int lba_start = le32_to_int(pt->start4) + relative; + usb_free(buffer); + return get_partition_info_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, part_num, which_part, info); + } + } + usb_free(buffer); + return -1; +} + +int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size) +{ + unsigned char *buffer; + disk_partition_t info; + + if(!dev_desc->block_read) + return -1; + + buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE); + if(buffer == NULL) + return -1; + /* check if we have a MBR (on floppies we have only a PBR) */ + + if(dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1) + { + DEBUG_STORAGE("Can't read from device %d\r\n", dev_desc->dev); + usb_free(buffer); + return -1; + } + + if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) + { + /* no signature found */ + usb_free(buffer); + return -1; + } + + /* First we assume, there is a MBR */ + if(!get_partition_info_extended(dev_desc, 0, 0, 1, part_no, &info)) + { + *part_type = info.type; + *part_offset = info.start; + *part_size = info.size; + } + else if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) + { + /* ok, we assume we are on a PBR only */ + *part_type = 0; + *part_offset = 0; + *part_size = 0; + } + else + { + DEBUG_STORAGE("Partition %d not valid on device %d\r\n", part_no, dev_desc->dev); + usb_free(buffer); + return -1; + } + usb_free(buffer); + return 0; +} + +#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD) + +void dev_print(block_dev_desc_t *dev_desc) +{ +#ifdef CONFIG_LBA48 + uint64_t lba512; /* number of blocks if 512bytes block size */ +#else + lbaint_t lba512; +#endif + if(dev_desc->type == DEV_TYPE_UNKNOWN) + { + printf("not available\r\n"); + DEBUG_STORAGE("not available\r\n"); + return; + } + DEBUG_STORAGE("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product); + DEBUG_STORAGE("\r\n"); + printf("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product); + printf("\r\n"); + if((dev_desc->lba * dev_desc->blksz) > 0L) + { + unsigned long mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; + lbaint_t lba = dev_desc->lba; + lba512 = (lba * (dev_desc->blksz / 512)); + mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ + /* round to 1 digit */ + mb_quot = mb / 10; + mb_rem = mb - (10 * mb_quot); + gb = mb / 1024; + gb_quot = gb / 10; + gb_rem = gb - (10 * gb_quot); +#ifdef CONFIG_LBA48 + if(dev_desc->lba48) + printf("Supports 48-bit addressing\r\n"); +#endif + DEBUG_STORAGE("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz); + printf("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz); + } + else { + DEBUG_STORAGE("Capacity: not available\r\n"); + printf("Capacity: not available\r\n"); + } +} + +/******************************************************************************* + * show info on storage devices; 'usb start/init' must be invoked earlier + * as we only retrieve structures populated during devices initialization + */ +int usb_stor_info(void) +{ + int i; + if(usb_max_devs > 0) + { + for(i = 0; i < usb_max_devs; i++) + { + DEBUG_STORAGE("Device %d: ", i); + printf("Device %d: ", i); + dev_print(&usb_dev_desc[i]); + } + return 0; + } + DEBUG_STORAGE("No storage devices\r\n"); + printf("No storage devices\r\n"); + return 1; +} + +#endif /* CONFIG_USB_OHCI */ + +/******************************************************************************* + * scan the usb and reports device info to the user + * returns current device or -1 if no + */ +int usb_stor_scan(void) +{ + unsigned char i; + struct usb_device *dev; + DEBUG_STORAGE("usb_stor_scan()"); /* Galvez: Debug trace */ + if(usb_stor_buf == NULL) + usb_stor_buf = (unsigned char *)usb_malloc(512); + if(usb_stor_buf == NULL) + return -1; + memset(usb_stor_buf, 0, sizeof(usb_stor_buf)); + usb_disable_asynch(1); /* asynch transfer not allowed */ + for(i = 0; i < USB_MAX_STOR_DEV; i++) + { + memset(&usb_dev_desc[i], 0, sizeof(block_dev_desc_t)); + usb_dev_desc[i].target = 0xff; + usb_dev_desc[i].if_type = IF_TYPE_USB; + usb_dev_desc[i].dev = i; + usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + usb_dev_desc[i].block_read = usb_stor_read; + usb_dev_desc[i].block_write = usb_stor_write; + } + usb_max_devs = 0; + for(i = 0; i < USB_MAX_DEVICE; i++) + { + dev = usb_get_dev_index(i); /* get device */ + if(dev == NULL) + break; /* no more devices avaiable */ + DEBUG_STORAGE("Device %d\r\n", i); + if(usb_storage_probe(dev, 0, &usb_stor[usb_max_devs])) + { + /* ok, it is a storage devices + * get info and fill it in + */ + if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs])) + usb_max_devs++; + } + /* if storage device */ + if(usb_max_devs == USB_MAX_STOR_DEV) + { + printf("Max USB Storage Device reached: %d stopping\r\n", usb_max_devs); + break; + } + } /* for */ + usb_disable_asynch(0); /* asynch transfer allowed */ + DEBUG_STORAGE("%d Storage Device(s) found\r\n", usb_max_devs); + printf("%d Storage Device(s) found\r\n", usb_max_devs); + if(usb_max_devs > 0) + return 0; + return -1; +} + +static int usb_stor_irq(struct usb_device *dev) +{ + struct us_data *us; + us = (struct us_data *)dev->privptr; + if(us->ip_wanted) + us->ip_wanted = 0; + return 0; +} + +#ifdef USB_STOR_DEBUG + +static void usb_show_srb(ccb *pccb) +{ + int i; + debug_init("usb.log"); + debug("SRB: len %d datalen 0x%lX\r\n ", pccb->cmdlen, pccb->datalen); + for (i = 0; i < 12; i++) + debug("%02X ", pccb->cmd[i]); + debug("\r\n"); + debug_exit(); +} + +static void display_int_status(unsigned long tmp) +{ + debug_init("usb.log"); + debug("Status: %s %s %s %s %s %s %s\r\n", + (tmp & USB_ST_ACTIVE) ? "Active" : "", + (tmp & USB_ST_STALLED) ? "Stalled" : "", + (tmp & USB_ST_BUF_ERR) ? "Buffer Error" : "", + (tmp & USB_ST_BABBLE_DET) ? "Babble Det" : "", + (tmp & USB_ST_NAK_REC) ? "NAKed" : "", + (tmp & USB_ST_CRC_ERR) ? "CRC Error" : "", + (tmp & USB_ST_BIT_ERR) ? "Bitstuff Error" : ""); + debug_exit(); +} + +#endif + +/*********************************************************************** + * Data transfer routines + ***********************************************************************/ + +static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) +{ + int max_size; + int this_xfer; + int result; + int partial; + int maxtry; + int stat; + /* determine the maximum packet size for these transfers */ + max_size = usb_maxpacket(us->pusb_dev, pipe) * 16; + /* while we have data left to transfer */ + while(length) + { + /* calculate how long this will be -- maximum or a remainder */ + this_xfer = length > max_size ? max_size : length; + length -= this_xfer; + /* setup the retry counter */ + maxtry = 10; + /* set up the transfer loop */ + do + { + /* transfer the data */ + DEBUG_STORAGE("Bulk xfer 0x%x(%d) try #%d\r\n", (unsigned int)buf, this_xfer, 11 - maxtry); + result = usb_bulk_msg(us->pusb_dev, pipe, buf, this_xfer, &partial, USB_CNTL_TIMEOUT * 5); + DEBUG_STORAGE("bulk_msg returned %d xferred %d/%d\r\n", result, partial, this_xfer); + if(us->pusb_dev->status != 0) + { + /* if we stall, we need to clear it before we go on */ +#ifdef USB_STOR_DEBUG + display_int_status(us->pusb_dev->status); +#endif + if(us->pusb_dev->status & USB_ST_STALLED) + { + DEBUG_STORAGE("stalled ->clearing endpoint halt for pipe 0x%x\r\n", pipe); + stat = us->pusb_dev->status; + usb_clear_halt(us->pusb_dev, pipe); + us->pusb_dev->status = stat; + if(this_xfer == partial) + { + DEBUG_STORAGE("bulk transferred with error %lX, but data ok\r\n", us->pusb_dev->status); + return 0; + } + else + return result; + } + if(us->pusb_dev->status & USB_ST_NAK_REC) + { + DEBUG_STORAGE("Device NAKed bulk_msg\r\n"); + return result; + } + DEBUG_STORAGE("bulk transferred with error"); + if(this_xfer == partial) + { + DEBUG_STORAGE(" %ld, but data ok\r\n", us->pusb_dev->status); + return 0; + } + /* if our try counter reaches 0, bail out */ + DEBUG_STORAGE(" %ld, data %d\r\n", us->pusb_dev->status, partial); + if(!maxtry--) + return result; + } + /* update to show what data was transferred */ + this_xfer -= partial; + buf += partial; + /* continue until this transfer is done */ + } while (this_xfer); + } + /* if we get here, we're done and successful */ + return 0; +} + +static int usb_stor_BBB_reset(struct us_data *us) +{ + int result; + unsigned int pipe; + /* + * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class) + * + * For Reset Recovery the host shall issue in the following order: + * a) a Bulk-Only Mass Storage Reset + * b) a Clear Feature HALT to the Bulk-In endpoint + * c) a Clear Feature HALT to the Bulk-Out endpoint + * + * This is done in 3 steps. + * + * If the reset doesn't succeed, the device should be port reset. + * + * This comment stolen from FreeBSD's /sys/dev/usb/umass.c. + */ + DEBUG_STORAGE("BBB_reset\r\n"); + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5); + if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) + { + DEBUG_STORAGE("RESET:stall\r\n"); + return -1; + } + /* long wait for reset */ + wait_ms(150); + DEBUG_STORAGE("BBB_reset result %d: status %lX reset\r\n", result, us->pusb_dev->status); + pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + result = usb_clear_halt(us->pusb_dev, pipe); + /* long wait for reset */ + wait_ms(150); + DEBUG_STORAGE("BBB_reset result %d: status %lX clearing IN endpoint\r\n", result, us->pusb_dev->status); + /* long wait for reset */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + result = usb_clear_halt(us->pusb_dev, pipe); + wait_ms(150); + DEBUG_STORAGE("BBB_reset result %d: status %lX clearing OUT endpoint\r\n", result, us->pusb_dev->status); + DEBUG_STORAGE("BBB_reset done\r\n"); + return 0; +} + +/* FIXME: this reset function doesn't really reset the port, and it + * should. Actually it should probably do what it's doing here, and + * reset the port physically + */ +static int usb_stor_CB_reset(struct us_data *us) +{ + unsigned char cmd[12]; + int result; + DEBUG_STORAGE("CB_reset\r\n"); + memset(cmd, 0xff, sizeof(cmd)); + cmd[0] = SCSI_SEND_DIAG; + cmd[1] = 4; + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, cmd, sizeof(cmd), USB_CNTL_TIMEOUT * 5); + /* long wait for reset */ + wait_ms(1500); + DEBUG_STORAGE("CB_reset result %d: status %lX clearing endpoint halt\r\n", result, us->pusb_dev->status); + usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in)); + usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out)); + DEBUG_STORAGE("CB_reset done\r\n"); + return 0; +} + +/* + * Set up the command for a BBB device. Note that the actual SCSI + * command is copied into cbw.CBWCDB. + */ +int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) +{ + int result; + int actlen; + int dir_in; + unsigned int pipe; + umass_bbb_cbw_t *cbw = (umass_bbb_cbw_t *)usb_malloc(sizeof(umass_bbb_cbw_t)); + if(cbw == NULL) + { + DEBUG_STORAGE("usb_stor_BBB_comdat: out of memory\r\n"); + return -1; + } + dir_in = US_DIRECTION(srb->cmd[0]); + DEBUG_STORAGE("usb_stor_BBB_comdat: dir_in: %d\r\n",dir_in); +#ifdef BBB_COMDAT_TRACE + debug_init ("usb.log"); + debug("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\r\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata); + if(srb->cmdlen) + { + for(result = 0; result < srb->cmdlen; result++) + debug("cmd[%d] %#x ", result, srb->cmd[result]); + debug("\r\n"); + } + debug_exit( ); +#endif + /* sanity checks */ + if(!(srb->cmdlen <= CBWCDBLENGTH)) + { + DEBUG_STORAGE("usb_stor_BBB_comdat: cmdlen too large\r\n"); + usb_free(cbw); + return -1; + } + /* always OUT to the ep */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + cbw->dCBWSignature = cpu_to_le32(CBWSIGNATURE); + cbw->dCBWTag = cpu_to_le32(CBWTag++); + cbw->dCBWDataTransferLength = cpu_to_le32(srb->datalen); + cbw->bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT); + cbw->bCBWLUN = srb->lun; + cbw->bCDBLength = srb->cmdlen; + /* copy the command data into the CBW command data buffer */ + /* DST SRC LEN!!! */ + memcpy(&cbw->CBWCDB, srb->cmd, srb->cmdlen); + + result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT * 5); + if(result < 0) + { DEBUG_STORAGE("usb_stor_BBB_comdat:usb_bulk_msg error\r\n");} + usb_free(cbw); + return result; +} + +/* FIXME: we also need a CBI_command which sets up the completion + * interrupt, and waits for it + */ +int usb_stor_CB_comdat(ccb *srb, struct us_data *us) +{ + int result = 0; + int dir_in, retry; + unsigned int pipe; + unsigned long status; + retry = 5; + dir_in = US_DIRECTION(srb->cmd[0]); + if(dir_in) + pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + else + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + while(retry--) + { + DEBUG_STORAGE("CBI gets a command: Try %d\r\n", 5 - retry); +#ifdef USB_STOR_DEBUG + usb_show_srb(srb); +#endif + /* let's send the command via the control pipe */ + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev , 0), + US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, srb->cmd, srb->cmdlen, USB_CNTL_TIMEOUT * 5); + DEBUG_STORAGE("CB_transport: control msg returned %d, status %lX\r\n", result, us->pusb_dev->status); + /* check the return code for the command */ + if(result < 0) + { + if(us->pusb_dev->status & USB_ST_STALLED) + { + status = us->pusb_dev->status; + DEBUG_STORAGE(" stall during command found, clear pipe\r\n"); + usb_clear_halt(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0)); + us->pusb_dev->status = status; + } + DEBUG_STORAGE(" error during command %02X Stat = %lX\r\n", srb->cmd[0], us->pusb_dev->status); + return result; + } + /* transfer the data payload for this command, if one exists*/ + DEBUG_STORAGE("CB_transport: control msg returned %d, direction is %s to go 0x%lx\r\n", result, dir_in ? "IN" : "OUT", srb->datalen); + if(srb->datalen) + { + result = us_one_transfer(us, pipe, (char *)srb->pdata, srb->datalen); + DEBUG_STORAGE("CBI attempted to transfer data, result is %d status %lX, len %d\r\n", result, us->pusb_dev->status, us->pusb_dev->act_len); + if(!(us->pusb_dev->status & USB_ST_NAK_REC)) + break; + } /* if(srb->datalen) */ + else + break; + } + /* return result */ + return result; +} + +int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) +{ + int timeout; + us->ip_wanted = 1; + submit_int_msg(us->pusb_dev, us->irqpipe, (void *) &us->ip_data, us->irqmaxp, us->irqinterval); + timeout = 1000; + while(timeout--) + { + if((volatile int *) us->ip_wanted == 0) + break; + wait_ms(10); + } + if(us->ip_wanted) + { + DEBUG_STORAGE("Did not get interrupt on CBI\r\n"); + printf("Did not get interrupt on CBI\r\n"); + us->ip_wanted = 0; + return USB_STOR_TRANSPORT_ERROR; + } + DEBUG_STORAGE("Got interrupt data 0x%x, transfered %d status 0x%lX\r\n", us->ip_data, us->pusb_dev->irq_act_len, us->pusb_dev->irq_status); + /* UFI gives us ASC and ASCQ, like a request sense */ + if(us->subclass == US_SC_UFI) + { + if(srb->cmd[0] == SCSI_REQ_SENSE || srb->cmd[0] == SCSI_INQUIRY) + return USB_STOR_TRANSPORT_GOOD; /* Good */ + else if(us->ip_data) + return USB_STOR_TRANSPORT_FAILED; + else + return USB_STOR_TRANSPORT_GOOD; + } + /* otherwise, we interpret the data normally */ + switch(us->ip_data) + { + case 0x0001: return USB_STOR_TRANSPORT_GOOD; + case 0x0002: return USB_STOR_TRANSPORT_FAILED; + default: return USB_STOR_TRANSPORT_ERROR; + } + return USB_STOR_TRANSPORT_ERROR; +} + +#define USB_TRANSPORT_UNKNOWN_RETRY 5 +#define USB_TRANSPORT_NOT_READY_RETRY 10 + +/* clear a stall on an endpoint - special for BBB devices */ +int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt) +{ + int result; + /* ENDPOINT_HALT = 0, so set value to 0 */ + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5); + return result; +} + +int usb_stor_BBB_transport(ccb *srb, struct us_data *us) +{ + int result, retry; + int dir_in; + int actlen, data_actlen; + unsigned int pipe, pipein, pipeout; +// DEBUG_STORAGE ( ); /* GALVEZ: DEBUG */ +#ifdef BBB_XPORT_TRACE + unsigned char *ptr; + int idx; +#endif + umass_bbb_csw_t *csw = (umass_bbb_csw_t *)usb_malloc(sizeof(umass_bbb_csw_t)); + if(csw == NULL) + { + DEBUG_STORAGE("out of memory\r\n"); + return USB_STOR_TRANSPORT_FAILED; + } + dir_in = US_DIRECTION(srb->cmd[0]); + /* COMMAND phase */ + DEBUG_STORAGE("COMMAND phase\n"); + result = usb_stor_BBB_comdat(srb, us); + if(result < 0) + { + DEBUG_STORAGE("failed to send CBW status %ld\r\n", us->pusb_dev->status); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + wait_ms(5); + pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + /* DATA phase + error handling */ + data_actlen = 0; + /* no data, go immediately to the STATUS phase */ + if(srb->datalen == 0) + goto st; + DEBUG_STORAGE("DATA phase\n"); + if(dir_in) + pipe = pipein; + else + pipe = pipeout; + result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5); + /* special handling of STALL in DATA phase */ + if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) + { + DEBUG_STORAGE("DATA:stall\r\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, dir_in ? us->ep_in : us->ep_out); + if(result >= 0) + /* continue on to STATUS phase */ + goto st; + } + if(result < 0) + { + DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } +#ifdef BBB_XPORT_TRACE + debug_init("usb.log"); + for(idx = 0; idx < data_actlen; idx++) + debug("pdata[%d] %#x ", idx, srb->pdata[idx]); + debug("\r\n"); + debug_exit( ); +#endif + /* STATUS phase + error handling */ +st: + retry = 0; +again: + DEBUG_STORAGE("STATUS phase\n"); + result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5); + /* special handling of STALL in STATUS phase */ + + if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) + { + DEBUG_STORAGE("STATUS:stall\r\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in); + if(result >= 0 && (retry++ < 1)) + /* do a retry */ + goto again; + } + + if(result < 0) + { + DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } +#ifdef BBB_XPORT_TRACE + debug_init("usb.log"); + ptr = (unsigned char *)csw; + for(idx = 0; idx < UMASS_BBB_CSW_SIZE; idx++) + debug("ptr[%d] %#x ", idx, ptr[idx]); + debug("\r\n"); + debug_exit( ); +#endif + /* misuse pipe to get the residue */ + pipe = le32_to_cpu(csw->dCSWDataResidue); + if(pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0) + pipe = srb->datalen - data_actlen; + if(CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature)) + { + DEBUG_STORAGE("!CSWSIGNATURE\r\n"); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + else if((CBWTag - 1) != le32_to_cpu(csw->dCSWTag)) + { + DEBUG_STORAGE("!Tag\r\n"); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + else if(csw->bCSWStatus > CSWSTATUS_PHASE) + { + DEBUG_STORAGE(">PHASE\r\n"); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + else if(csw->bCSWStatus == CSWSTATUS_PHASE) + { + DEBUG_STORAGE("=PHASE\r\n"); + usb_stor_BBB_reset(us); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + else if(data_actlen > srb->datalen) + { + DEBUG_STORAGE("transferred %dB instead of %ldB\r\n", data_actlen, srb->datalen); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + else if(csw->bCSWStatus == CSWSTATUS_FAILED) + { +// printf("FAILED\r\n"); /* GALVEZ: DEBUG */ + DEBUG_STORAGE("FAILED\r\n"); + usb_free(csw); + return USB_STOR_TRANSPORT_FAILED; + } + usb_free(csw);; + return result; +} + +int usb_stor_CB_transport(ccb *srb, struct us_data *us) +{ + int result, status; + ccb *psrb; + ccb reqsrb; + int retry, notready; + psrb = &reqsrb; + status = USB_STOR_TRANSPORT_GOOD; + retry = 0; + notready = 0; + /* issue the command */ +do_retry: + result = usb_stor_CB_comdat(srb, us); + DEBUG_STORAGE("command / Data returned %d, status %lX\r\n", result, us->pusb_dev->status); + /* if this is an CBI Protocol, get IRQ */ + if(us->protocol == US_PR_CBI) + { + status = usb_stor_CBI_get_status(srb, us); + /* if the status is error, report it */ + if(status == USB_STOR_TRANSPORT_ERROR) + { + DEBUG_STORAGE(" USB CBI Command Error\r\n"); + return status; + } + srb->sense_buf[12] = (unsigned char)(us->ip_data >> 8); + srb->sense_buf[13] = (unsigned char)(us->ip_data & 0xff); + if(!us->ip_data) + { + /* if the status is good, report it */ + if(status == USB_STOR_TRANSPORT_GOOD) + { + DEBUG_STORAGE(" USB CBI Command Good\r\n"); + return status; + } + } + } + /* do we have to issue an auto request? */ + /* HERE we have to check the result */ + if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) + { + DEBUG_STORAGE("ERROR %lX\r\n", us->pusb_dev->status); + us->transport_reset(us); + return USB_STOR_TRANSPORT_ERROR; + } + if((us->protocol == US_PR_CBI) && ((srb->cmd[0] == SCSI_REQ_SENSE) || (srb->cmd[0] == SCSI_INQUIRY))) + { + /* do not issue an autorequest after request sense */ + DEBUG_STORAGE("No auto request and good\r\n"); + return USB_STOR_TRANSPORT_GOOD; + } + /* issue an request_sense */ + memset(&psrb->cmd[0], 0, 12); + psrb->cmd[0] = SCSI_REQ_SENSE; + psrb->cmd[1] = srb->lun << 5; + psrb->cmd[4] = 18; + psrb->datalen = 18; + psrb->pdata = &srb->sense_buf[0]; + psrb->cmdlen = 12; + /* issue the command */ + result = usb_stor_CB_comdat(psrb, us); + DEBUG_STORAGE("auto request returned %d\r\n", result); + /* if this is an CBI Protocol, get IRQ */ + if(us->protocol == US_PR_CBI) + status = usb_stor_CBI_get_status(psrb, us); + if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) + { + DEBUG_STORAGE(" AUTO REQUEST ERROR %ld\r\n", us->pusb_dev->status); + return USB_STOR_TRANSPORT_ERROR; + } + DEBUG_STORAGE("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); + /* Check the auto request result */ + if((srb->sense_buf[2] == 0) && (srb->sense_buf[12] == 0) && (srb->sense_buf[13] == 0)) + { + /* ok, no sense */ + return USB_STOR_TRANSPORT_GOOD; + } + /* Check the auto request result */ + switch(srb->sense_buf[2]) + { + case 0x01: + /* Recovered Error */ + return USB_STOR_TRANSPORT_GOOD; + case 0x02: /* Not Ready */ + if(notready++ > USB_TRANSPORT_NOT_READY_RETRY) + { + DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\r\n", srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); + return USB_STOR_TRANSPORT_FAILED; + } + else + { + wait_ms(100); + goto do_retry; + } + break; + default: + if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY) + { + DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", + srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2], + srb->sense_buf[12], srb->sense_buf[13]); + return USB_STOR_TRANSPORT_FAILED; + } + else + goto do_retry; + break; + } + return USB_STOR_TRANSPORT_FAILED; +} + +static int usb_inquiry(ccb *srb, struct us_data *ss) +{ + DEBUG_STORAGE ("usb_inquiry()"); /* GALVEZ: DEBUG */ + + int retry, i; + retry = 5; + do + { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_INQUIRY; + srb->cmd[4] = 36; + srb->datalen = 36; + srb->cmdlen = 12; + i = ss->transport(srb, ss); + DEBUG_STORAGE("inquiry returns %d\r\n", i); + if(i == 0) + break; + } + while(retry--); + if(!retry) + { + DEBUG_STORAGE("error in inquiry\r\n"); + printf("error in inquiry\r\n"); + return -1; + } + return 0; +} + +static int usb_request_sense(ccb *srb, struct us_data *ss) +{ + DEBUG_STORAGE("usb_request_sense()"); /* GALVEZ: DEBUG */ + char *ptr; + ptr = (char *)srb->pdata; + memset(&srb->cmd[0], 0, /*12*/6); /* GALVEZ: DEBUG: DEFAULT 12 */ + srb->cmd[0] = SCSI_REQ_SENSE; + srb->cmd[4] = 18; + srb->datalen = 18; + srb->pdata = &srb->sense_buf[0]; + srb->cmdlen = /*12*/6; /* GALVEZ: DEBUG: DEFAULT 12 */ + ss->transport(srb, ss); + DEBUG_STORAGE("Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); + srb->pdata = (unsigned char *)ptr; + return 0; +} + +static int usb_test_unit_ready(ccb *srb, struct us_data *ss) +{ + int retries = 10; + DEBUG_STORAGE("usb_test_unit_ready()"); /* GALVEZ: DEBUG */ + do + { + memset(&srb->cmd[0], 0, /*12*/ 6); /* GALVEZ: DEBUG: DEFAULT 12 */ + srb->cmd[0] = SCSI_TST_U_RDY; + srb->datalen = 0; + srb->cmdlen = /*12*/ 6; /* GALVEZ: DEBUG: DEFAULT 12 */ + if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) + return 0; + usb_request_sense(srb, ss); + wait_ms(100); + } + while(retries--); + return -1; +} + +static int usb_read_capacity(ccb *srb, struct us_data *ss) +{ + int retry; + /* XXX retries */ + retry = 3; + DEBUG_STORAGE("usb_read_capacity()"); /* GALVEZ: DEBUG */ + do + { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_RD_CAPAC; + srb->datalen = 8; + srb->cmdlen = 12; + if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) + return 0; + } + while(retry--); + return -1; +} + +static int usb_read_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks) +{ + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_READ10; + srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff; + srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff; + srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff; + srb->cmd[5] = ((unsigned char) (start)) & 0xff; + srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff; + srb->cmd[8] = (unsigned char) blocks & 0xff; + srb->cmdlen = 12; + DEBUG_STORAGE("read10: start %lx blocks %x\r\n", start, blocks); + return ss->transport(srb, ss); +} + +static int usb_write_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks) +{ + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_WRITE10; + srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff; + srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff; + srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff; + srb->cmd[5] = ((unsigned char) (start)) & 0xff; + srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff; + srb->cmd[8] = (unsigned char) blocks & 0xff; + srb->cmdlen = 12; + DEBUG_STORAGE("write10: start %lx blocks %x\r\n", start, blocks); + return ss->transport(srb, ss); +} + +#ifdef CONFIG_USB_BIN_FIXUP +/* + * Some USB storage devices queried for SCSI identification data respond with + * binary strings, which if output to the console freeze the terminal. The + * workaround is to modify the vendor and product strings read from such + * device with proper values (as reported by 'usb info'). + * + * Vendor and product length limits are taken from the definition of + * block_dev_desc_t in include/part.h. + */ +static void usb_bin_fixup(struct usb_device_descriptor descriptor, unsigned char vendor[], unsigned char product[]) +{ + const unsigned char max_vendor_len = 40; + const unsigned char max_product_len = 20; + if(descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) + { + strncpy((char *)vendor, "SMSC", max_vendor_len); + strncpy((char *)product, "Flash Media Cntrller", max_product_len); + } +} +#endif /* CONFIG_USB_BIN_FIXUP */ + +#define USB_MAX_READ_BLK 20 + +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) +{ + unsigned long start, blks, buf_addr; + unsigned short smallblks; + struct usb_device *dev; + int retry, i; + ccb *srb = &usb_ccb; + + + if(blkcnt == 0) + return 0; + device &= 0xff; + /* Setup device */ +// printf ("blknr: %x\n\r", blknr); /* Galvez: Debug */ + DEBUG_STORAGE("usb_read: dev %d \r\n", device); + dev = NULL; +#ifdef SUPERVISOR + int p = 0; + /* GALVEZ: Acces to register in Supervisor */ + if (!(Super(SUP_INQUIRE))){ + p = SuperFromUser(); + } +#endif + + for(i = 0; i < USB_MAX_DEVICE; i++) + { + dev = usb_get_dev_index(i); + if(dev == NULL){ +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)){ + SuperToUser(p); + } +#endif + return 0; + } + if(dev->devnum == usb_dev_desc[device].target) + break; + } + usb_disable_asynch(1); /* asynch transfer not allowed */ + srb->lun = usb_dev_desc[device].lun; + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; + + if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) + { + DEBUG_STORAGE("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); + printf("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)){ + SuperToUser(p); + } +#endif + return 0; + } + + DEBUG_STORAGE("usb_read: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr); + do + { + /* XXX need some comment here */ + retry = 2; + srb->pdata = (unsigned char *)buf_addr; + if(blks > USB_MAX_READ_BLK) + smallblks = USB_MAX_READ_BLK; + else + smallblks = (unsigned short) blks; +retry_it: + srb->datalen = usb_dev_desc[device].blksz * smallblks; + srb->pdata = (unsigned char *)buf_addr; + if(usb_read_10(srb, (struct us_data *)dev->privptr, start, smallblks)) + { + DEBUG_STORAGE("Read ERROR\r\n"); + usb_request_sense(srb, (struct us_data *)dev->privptr); + if(retry--) + goto retry_it; + blkcnt -= blks; + break; + } + start += smallblks; + blks -= smallblks; + buf_addr += srb->datalen; + } + while(blks != 0); + DEBUG_STORAGE("usb_read: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr); + usb_disable_asynch(0); /* asynch transfer allowed */ +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)){ + SuperToUser(p); + } +#endif + return blkcnt; +} + +unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer) +{ + unsigned long start, blks, buf_addr; + unsigned short smallblks; + struct usb_device *dev; + int retry, i; + ccb *srb = &usb_ccb; + + if(blkcnt == 0) + return 0; + device &= 0xff; + /* Setup device */ + DEBUG_STORAGE("usb_write: dev %d \r\n", device); +#ifdef SUPERVISOR + int p = 0; + /* GALVEZ: Acces to register in Supervisor */ + if ( !(Super(SUP_INQUIRE))){ + p = SuperFromUser(); + } +#endif + + dev = NULL; + for(i = 0; i < USB_MAX_DEVICE; i++) + { + dev = usb_get_dev_index(i); + if(dev == NULL){ +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)) + SuperToUser(p); +#endif + return 0; + } + if(dev->devnum == usb_dev_desc[device].target) + break; + } + usb_disable_asynch(1); /* asynch transfer not allowed */ + srb->lun = usb_dev_desc[device].lun; + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; +//#if 1 /* GALVEZ: DEBUG */ + if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) + { + DEBUG_STORAGE("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); + printf("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)) + SuperToUser(p); +#endif + return 0; + } +//#endif + DEBUG_STORAGE("usb_write: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr); + do + { + /* XXX need some comment here */ + retry = 2; + srb->pdata = (unsigned char *)buf_addr; + if(blks > USB_MAX_READ_BLK) + smallblks = USB_MAX_READ_BLK; + else + smallblks = (unsigned short)blks; +retry_it: + srb->datalen = usb_dev_desc[device].blksz * smallblks; + srb->pdata = (unsigned char *)buf_addr; + if(usb_write_10(srb, (struct us_data *)dev->privptr, start, smallblks)) + { + DEBUG_STORAGE("Write ERROR\r\n"); + usb_request_sense(srb, (struct us_data *)dev->privptr); + if(retry--) + goto retry_it; + blkcnt -= blks; + break; + } + start += smallblks; + blks -= smallblks; + buf_addr += srb->datalen; + } + while(blks != 0); + DEBUG_STORAGE("usb_write: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr); + usb_disable_asynch(0); /* asynch transfer allowed */ +#ifdef SUPERVISOR + /* GALVEZ: come back to user mode */ + if ((Super(SUP_INQUIRE)) && (p)) + SuperToUser(p); +#endif + return blkcnt; +} + +/* Probe to see if a new device is actually a Storage device */ +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss) +{ + struct usb_interface_descriptor *iface; + int i; + unsigned int flags = 0; + int protocol = 0; + int subclass = 0; + + DEBUG_STORAGE("usb_storage_probe()"); + + /* let's examine the device now */ + iface = &dev->config.if_desc[ifnum]; +#if 0 + DEBUG_STORAGE("iVendor 0x%X iProduct 0x%X\r\n", dev->descriptor.idVendor, dev->descriptor.idProduct); + /* this is the place to patch some storage devices */ + if((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103) + { + DEBUG_STORAGE("patched for E-USB\r\n"); + protocol = US_PR_CB; + subclass = US_SC_UFI; /* an assumption */ + } +#endif + if(dev->descriptor.bDeviceClass != 0 || iface->bInterfaceClass != USB_CLASS_MASS_STORAGE + || iface->bInterfaceSubClass < US_SC_MIN || iface->bInterfaceSubClass > US_SC_MAX) + /* if it's not a mass storage, we go no further */ + return 0; + memset(ss, 0, sizeof(struct us_data)); + /* At this point, we know we've got a live one */ + DEBUG_STORAGE("\r\n\r\nUSB Mass Storage device detected\r\n"); + DEBUG_STORAGE("Protocol: %x SubClass: %x", iface->bInterfaceProtocol, /* GALVEZ: DEBUG */ + iface->bInterfaceSubClass ); + /* Initialize the us_data structure with some useful info */ + ss->flags = flags; + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->attention_done = 0; + /* If the device has subclass and protocol, then use that. Otherwise, + * take data from the specific interface. + */ + if(subclass) + { + ss->subclass = subclass; + ss->protocol = protocol; + } + else + { + ss->subclass = iface->bInterfaceSubClass; + ss->protocol = iface->bInterfaceProtocol; + } + /* set the handler pointers based on the protocol */ + DEBUG_STORAGE("Transport: "); + switch(ss->protocol) + { + case US_PR_CB: + DEBUG_STORAGE("Control/Bulk\r\n"); + ss->transport = usb_stor_CB_transport; + ss->transport_reset = usb_stor_CB_reset; + break; + case US_PR_CBI: + DEBUG_STORAGE("Control/Bulk/Interrupt\r\n"); + ss->transport = usb_stor_CB_transport; + ss->transport_reset = usb_stor_CB_reset; + break; + case US_PR_BULK: + DEBUG_STORAGE("Bulk/Bulk/Bulk\r\n"); + ss->transport = usb_stor_BBB_transport; + ss->transport_reset = usb_stor_BBB_reset; + break; + default: + printf("USB Storage Transport unknown / not yet implemented\r\n"); + return 0; + break; + } + /* + * We are expecting a minimum of 2 endpoints - in and out (bulk). + * An optional interrupt is OK (necessary for CBI protocol). + * We will ignore any others. + */ + DEBUG_STORAGE("Number of endpoints: %d\r\n", iface->bNumEndpoints); + for(i = 0; i < iface->bNumEndpoints; i++) + { + /* is it an BULK endpoint? */ + if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) + { + if(iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) + ss->ep_in = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + else + ss->ep_out = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + } + /* is it an interrupt endpoint? */ + if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) + { + ss->ep_int = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + ss->irqinterval = iface->ep_desc[i].bInterval; + } + } + DEBUG_STORAGE("Endpoints In %d Out %d Int %d\r\n", ss->ep_in, ss->ep_out, ss->ep_int); + /* Do some basic sanity checks, and bail if we find a problem */ + if(usb_set_interface(dev, iface->bInterfaceNumber, 0) || !ss->ep_in || !ss->ep_out + || (ss->protocol == US_PR_CBI && ss->ep_int == 0)) + { + DEBUG_STORAGE("Problems with device\r\n"); + return 0; + } + /* set class specific stuff */ + /* We only handle certain protocols. Currently, these are + * the only ones. + * The SFF8070 accepts the requests used in u-boot + */ + if(ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && ss->subclass != US_SC_8070) + { + DEBUG_STORAGE("Sorry, protocol %d not yet supported.\r\n", ss->subclass); + printf("Sorry, protocol %d not yet supported.\r\n", ss->subclass); + return 0; + } + if(ss->ep_int) + { + /* we had found an interrupt endpoint, prepare irq pipe + * set up the IRQ pipe and handler + */ + ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255; + ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int); + ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe); + dev->irq_handle = usb_stor_irq; + } + dev->privptr = (void *)ss; + return 1; +} + +int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, block_dev_desc_t *dev_desc) +{ + unsigned char perq, modi; + unsigned long cap[2]; + unsigned long *capacity, *blksz; + ccb *pccb = &usb_ccb; + DEBUG_STORAGE("usb_stor_ger_info()"); + /* for some reasons a couple of devices would not survive this reset */ + if( + /* Sony USM256E */ + (dev->descriptor.idVendor == 0x054c && dev->descriptor.idProduct == 0x019e) + /* USB007 Mini-USB2 Flash Drive */ + || (dev->descriptor.idVendor == 0x066f && dev->descriptor.idProduct == 0x2010) + /* SanDisk Corporation Cruzer Micro 20044318410546613953 */ + || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5151) + /* SanDisk Corporation U3 Cruzer Micro 1/4GB Flash Drive 000016244373FFB4 */ + || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5406) + ) + { DEBUG_STORAGE("usb_stor_get_info: skipping RESET..\r\n");} + else + ss->transport_reset(ss); + pccb->pdata = usb_stor_buf; + dev_desc->target = dev->devnum; + pccb->lun = dev_desc->lun; + DEBUG_STORAGE(" address %d\r\n", dev_desc->target); + if(usb_inquiry(pccb, ss)) + return -1; + perq = usb_stor_buf[0]; + modi = usb_stor_buf[1]; + if((perq & 0x1f) == 0x1f) + /* skip unknown devices */ + return 0; + if((modi&0x80) == 0x80) + /* drive is removable */ + dev_desc->removable = 1; + memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8); + memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16); + memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4); + dev_desc->vendor[8] = 0; + dev_desc->product[16] = 0; + dev_desc->revision[4] = 0; +#ifdef CONFIG_USB_BIN_FIXUP + usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product); +#endif /* CONFIG_USB_BIN_FIXUP */ + DEBUG_STORAGE("ISO Vers %X, Response Data %X\r\n", usb_stor_buf[2], usb_stor_buf[3]); + if(usb_test_unit_ready(pccb, ss)) + { + DEBUG_STORAGE("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]); + printf("Device NOT ready\r\n Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]); + if(dev_desc->removable == 1) + { + dev_desc->type = perq; + return 1; + } + return 0; + } + pccb->pdata = (unsigned char *)&cap[0]; + memset(pccb->pdata, 0, 8); + if(usb_read_capacity(pccb, ss) != 0) + { + printf("READ_CAP ERROR\r\n"); + cap[0] = 2880; + cap[1] = 0x200; + } + DEBUG_STORAGE("Read Capacity returns: 0x%lx, 0x%lx\r\n", cap[0], cap[1]); +#if 0 + if(cap[0] > (0x200000 * 10)) /* greater than 10 GByte */ + cap[0] >>= 16; +#endif + cap[0] = cpu_to_be32(cap[0]); + cap[1] = cpu_to_be32(cap[1]); + /* this assumes bigendian! */ + cap[0] += 1; + capacity = &cap[0]; + blksz = &cap[1]; + DEBUG_STORAGE("Capacity = 0x%lx, blocksz = 0x%lx\r\n", *capacity, *blksz); + dev_desc->lba = *capacity; + dev_desc->blksz = *blksz; + dev_desc->type = perq; + DEBUG_STORAGE(" address %d\r\n", dev_desc->target); + DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type); + init_part(dev_desc); + DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type); + return 1; +} + +#endif /* CONFIG_USB_STORAGE */ +#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI */ diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/vars.h b/BaS_codewarrior/FireBee/trunk/usb/store/vars.h new file mode 100644 index 0000000..b6e626b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/vars.h @@ -0,0 +1,83 @@ +/* +* Modified by David Gálvez 2010. +* +* TOS 4.04 Xbios vars for the CT60 board +* Didier Mequignon 2002-2005, e-mail: aniplay@wanadoo.fr +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2.1 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _VARS_H +#define _VARS_H + + +#define etv_timer 0x400 +#define etv_critic 0x404 +#define memvalid 0x420 +#define memctrl 0x424 +#define resvalid 0x426 +#define resvector 0x42A +#define phystop 0x42E +#define _memtop 0x436 +#define memval2 0x43A +#define flock 0x43E +#define _timer_ms 0x442 +#define _bootdev 0x446 +#define sshiftmd 0x44C +#define _v_bas_ad 0x44E +#define vblsem 0x452 +#define nvbls 0x454 +#define _vblqueue 0x456 +#define colorptr 0x45A +#define _vbclock 0x462 +#define _frclock 0x466 +#define hdv_init 0x46A +#define HDV_BPB 0x472 +#define hdv_bpb 0x472 +#define HDV_RW 0x476 +#define hdv_rw 0x476 +#define hdv_boot 0x47A +#define HDV_MEDIACH 0x47E +#define hdv_mediach 0x47E +#define _cmdload 0x482 +#define conterm 0x484 +#define trp14ret 0x486 +#define __md 0x49E +#define savptr 0x4A2 +#define _nflops 0x4A6 +#define con_state 0x4A8 +#define save_row 0x4AC +#define _hz_200 0x4BA +#define _DRVBITS 0x4C2 +#define _drvbits 0x4C2 +#define DSKBUFP 0x4C6 +#define _dskbufp 0x4C6 +#define _dumpflg 0x4EE +#define _sysbase 0x4F2 +#define exec_os 0x4FE +#define dump_vec 0x502 +#define ptr_stat 0x506 +#define ptr_vec 0x50A +#define aux_sta 0x50E +#define aux_vec 0x512 +#define PUN_PTR 0x516 +#define memval3 0x51A +#define proc_type 0x59E +#define COOKIE 0x5A0 +#define cookie 0x5A0 + + + +#endif diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.c b/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.c new file mode 100644 index 0000000..3be2bfa --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.c @@ -0,0 +1,391 @@ +/***************** NOT READY YET ***********************/ +/**************** ONLY EXPERIMENTAL ********************/ + +/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards + * and USB-disk / Ram-Disk utility + * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr + * + * Translation to C by David Galvez. 2010, e-mail: dgalvez75@gmail.com + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include + +#include "config.h" +#include "vars.h" +#include "xhdi.h" +#include "debug.h" + +long *drvbits = (long *)_DRVBITS; + +struct pun_info *old_pun_ptr = (struct pun_info *)0x512; +struct usb_pun_info pun_ptr_usb; + +XBRA xbra_hdv_bpb; +XBRA xbra_hdv_rw; +XBRA xbra_hdv_mediach; + +extern long usb_1st_disk_drive; +extern short max_logical_drive; + +extern unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer); + +void drive_full_usb(void) +{ + DEBUG_XHDI("\n"); +} + +long __CDECL hdv_bpb_usb(void) +{ + unsigned short dev; + long r; + + __asm__ volatile /* get arguments from the stack */ + ( + "move.w 12(%%sp),%0\n\t" + + :/*outputs*/ "=m" (dev) + :/*inputs*/ + ); + + __asm__ volatile /* call old vector */ + ( + "movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t" /* important to save register */ + "move.l %1,%%a0\n\t" + "move.w #0,-(%%sp)\n\t" + "move.w %2,-(%%sp)\n\t" + "jsr (%%a0)\n\t" + "addq.l #4,%%sp\n\t" + "move.l %%d0,%0\n\t" + "movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t" + :/*outputs*/ "=r" (r) + :/*inputs*/ "m" (xbra_hdv_bpb.xb_oldvec), "m" (dev) + :"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" /*clobbered regs*/ + ); + return r; +} + +long __CDECL hdv_rw_usb(void) +{ + void *buf; + short count, recno, dev, mode; + long lrecno; + + long r = 0; + + __asm__ volatile /* get arguments from the stack */ + ( + "move.l 18(%%sp),%0\n\t" + "move.w 14(%%sp),%1\n\t" + "move.w 12(%%sp),%2\n\t" + "move.w 10(%%sp),%3\n\t" + "move.l 8(%%sp),%4\n\t" + "move.w 4(%%sp),%5\n\t" + :/*outputs*/ "=r" (lrecno), "=r" (dev) ,"=r" (recno), "=r" (count), "=r" (buf), "=r" (mode) + :/*inputs*/ + ); + + DEBUG_XHDI("lrecno %lx dev %d recno %x count %d mode %x\n", + lrecno, dev, recno, count, mode); + + DEBUG_XHDI("\n"); + DEBUG_XHDI("rw\n"); + + __asm__ volatile /* call old vector */ + ( + "movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t" + "move.l %1,%%a0\n\t" + "move.l (%%a0),%%d0\n\t" + "move.w #0,-(%%sp)\n\t" + "move.l %2,-(%%sp)\n\t" + "move.w %3,-(%%sp)\n\t" + "move.w %4,-(%%sp)\n\t" + "move.w %5,-(%%sp)\n\t" + "move.l %6,-(%%sp)\n\t" + "move.w %7,-(%%sp)\n\t" + "move.l %%d0,%%a0\n\t" + "jsr (%%a0)\n\t" + "addq.l #4,%%sp\n\t" + "move.l %%d0,%0\n\t" + "movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t" + :/*outputs*/ "=r" (r) + :/*inputs*/ "r" (xbra_hdv_rw.xb_oldvec), "r" (lrecno), "r" (dev) ,"r" (recno), "r" (count), "r" (buf), "r" (mode) + :"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/ + ); + +// r = (*xbra_hdv_rw.xb_oldvec)(mode, buf, num, recno, dev, l); + DEBUG_XHDI (" r %lx \n", r); + + return r; +} + +long __CDECL hdv_mediach_usb(void) +{ + DEBUG_XHDI("\n"); + DEBUG_XHDI("mediach\n"); + + short dev, dev1, dev2; + long r; + + __asm__ volatile /* get arguments from the stack */ + ( + "move.w 2(%%sp),%0\n\t" + "move.w 4(%%sp),%1\n\t" + "move.w 6(%%sp),%2\n\t" + :/*outputs*/ "=r" (dev), "=r" (dev1), "=r" (dev2) + :/*inputs*/ + ); + + DEBUG_XHDI (" dev(2) %x dev(4) %x dev(6) %x\n", dev, dev1, dev2); + + __asm__ volatile /* call old vector */ + ( + "movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t" + "move.l %1,%%a0\n\t" + "move.l (%%a0),%%d0\n\t" + "move.w #0,-(%%sp)\n\t" + "move.w %2,-(%%sp)\n\t" + "move.l %%d0,%%a0\n\t" + "jsr (%%a0)\n\t" + "addq.l #4,%%sp\n\t" + "move.l %%d0,%0\n\t" + "movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t" + :/*outputs*/ "=r" (r) + :/*inputs*/ "r" (xbra_hdv_mediach.xb_oldvec), "r" (dev) + :"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/ + ); +// printf (" r %lx \n", r); +// r = (*xbra_hdv_mediach.xb_oldvec)(d); +// DEBUG_XHDI("Calling vector: %x\n", xbra_hdv_mediach.xb_oldvec); +// r = (*xbra_hdv_mediach.xb_oldvec)(5); + DEBUG_XHDI(" r %lx \n", r); + + return r; +} + +void install_xbra(XBRA *xbra_hd, long id, long old_vec, long (*handle)()) +{ + DEBUG_XHDI("\n"); +#define XBRA_MAGIC 0x58425241L /* "XBRA" */ +#define JMP_OPCODE 0x4EF9 + + xbra_hd->xb_magic = XBRA_MAGIC; + xbra_hd->xb_id = id; + xbra_hd->xb_oldvec = *((Func *)old_vec); + xbra_hd->jump = JMP_OPCODE; + xbra_hd->handle = (Func) handle; + + *((Func *)old_vec) = xbra_hd->handle; + + DEBUG_XHDI("id: %x xbra_hd->xb_oldvec %x old_vec %x old_vec (*) %x old_vec (&) %x\n", + xbra_hd->xb_id, xbra_hd->xb_oldvec, old_vec, *((Func *)old_vec), &old_vec); + + __asm__ volatile /* clean cache ??? */ + ( + "cpusha BC\n\t" + :/*outputs*/ + :/*inputs*/ + ); +} + +void usb_drive_ok(void) +{ + DEBUG_XHDI("\n"); + +} + + +long install_usb_partition(unsigned char drive, int dev_num, unsigned long part_type, + unsigned long part_offset, unsigned long part_size) +{ + DEBUG_XHDI("\n"); + + int *dskbufp = (int *)DSKBUFP; + unsigned short status_register; + + long old_hdv_bpb; + long old_hdv_rw; + long old_hdv_mediach; + + if (drive < 16) { + (pun_ptr_usb.puns)++; + pun_ptr_usb.pun[drive] = dev_num | PUN_USB; + pun_ptr_usb.pstart[drive] = part_offset; + pun_ptr_usb.ptype[drive] = part_type; + pun_ptr_usb.psize[drive] = part_size; + /* flags B15:swap, B7:change, B0:bootable */ +#define BOOTABLE 0x0001 +#define CHANGE 0x0080 +#define SWAP 0x8000 + pun_ptr_usb.flags[drive] = CHANGE; + } + + if (drive < 16) { + old_pun_ptr->puns++; + old_pun_ptr->pun[drive] = dev_num | PUN_USB; + } + + if (usb_stor_read (dev_num, part_offset, 1, (void *)(*dskbufp)) == 0) + return -1; + + if (usb_1st_disk_drive) + usb_drive_ok(); + + usb_1st_disk_drive = drive; + + long r; + r = (long)Getbpb (2); + DEBUG_XHDI("Before int. Getbpb return: %x \n", r); + + + __asm__ volatile /* mask interrupts */ + ( + "move.w %%sr,%%d0\n\t" + "move.w %%d0,%0\n\t" + "or.l #0x700,%%d0\n\t" + "move.w %%d0,%%sr\n\t" + :/*outputs*/ "=r" (status_register) + :/*inputs*/ + :"d0" /*clobbered regs*/ + ); + +#define _USB 0x5F555342 /* _USB */ + long id = _USB; + old_hdv_bpb = (long)HDV_BPB; + + DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", + id, old_hdv_bpb, *((Func *)old_hdv_bpb), hdv_bpb_usb); + install_xbra(&xbra_hdv_bpb, id, old_hdv_bpb, hdv_bpb_usb); + DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", + xbra_hdv_bpb.xb_id, xbra_hdv_bpb.xb_oldvec, *((Func *)xbra_hdv_bpb.xb_oldvec), xbra_hdv_bpb.handle); +#if 0 + old_hdv_rw = (long)HDV_RW; + DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", + id, old_hdv_rw, *((Func *)old_hdv_rw), hdv_rw_usb); + install_xbra(&xbra_hdv_rw, id, old_hdv_rw, hdv_rw_usb); + DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", + xbra_hdv_rw.xb_id, xbra_hdv_rw.xb_oldvec, *((Func *)xbra_hdv_rw.xb_oldvec), xbra_hdv_rw.handle); + + old_hdv_mediach = (long)HDV_MEDIACH; + DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", + id, old_hdv_mediach, *((Func *)old_hdv_mediach), hdv_mediach_usb); + install_xbra(&xbra_hdv_mediach, id, old_hdv_mediach, hdv_mediach_usb); + DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", + xbra_hdv_mediach.xb_id, xbra_hdv_mediach.xb_oldvec, *((Func *)xbra_hdv_mediach.xb_oldvec), xbra_hdv_mediach.handle); +#endif + + r = (long)Getbpb (4); + + DEBUG_XHDI("Before int. Getbpb return: %x \n", r); + +// Bconin(DEV_CONSOLE); + __asm__ volatile /* restore interrupts */ + ( + "move.w %%sr,%%d0\n\t" + "and.w %0,%%d0\n\t" + "move.w %%d0,%%sr\n\t" + :/*outputs*/ + :/*inputs*/ "r" (status_register) + :"d0" + ); + DEBUG_XHDI("after restore interrups\n"); +// Bconin(DEV_CONSOLE); + return 0; +} + +unsigned char search_empty_drive(int dev_num, unsigned long part_type, + unsigned long part_offset, unsigned long part_size) +{ + DEBUG_XHDI("\n"); + + unsigned char drive = 2; + + DEBUG_XHDI("drvbits: %x\n", *drvbits); + while (drive < MAX_LOGICAL_DRIVE) { + if (!(*drvbits & (0x00000001 << drive))) { + DEBUG_XHDI("drive: %d\n", drive); + if (install_usb_partition(drive, dev_num, part_type, part_offset, part_size) == -1) { + DEBUG_XHDI("Couldn't install USB partition\n"); + return -1; + } + else return drive; + } + drive++; + } + printf("all drives already used!\n\r"); + + return -1; +} + +unsigned char add_partition(int dev_num, unsigned long part_type, + unsigned long part_offset, unsigned long part_size) +{ + DEBUG_XHDI("\n"); + + unsigned char i; + unsigned char drive; + + pun_ptr_usb.puns = 0x0000; + pun_ptr_usb.version_num = 0x0300; + pun_ptr_usb.max_sect_siz = 0x4000; + + for (i=0; i<16; i++) + pun_ptr_usb.pun[i] = 0xff; + + if ((drive = search_empty_drive(dev_num, part_type, part_offset, part_size)) == -1) + return -1; + return drive; +} + +int install_usb_stor(int dev_num, unsigned long part_type, + unsigned long part_offset, unsigned long part_size, + char *vendor, char *revision, char *product ) +{ + DEBUG_XHDI("\n"); + unsigned char part_num; + + if (dev_num <= PUN_DEV) { /* Max. of 32 USB storage devices */ + switch (part_type) { /* Although real limit is 16 of pinfo struct */ + case GEM: + break; + case BGM: + break; + case RAW: + break; + case FAT16_32MB: + break; + case FAT16: + break; + case FAT16_WIN95: + break; + case FAT32: + break; + case FAT32_II: + break; + default: + printf("Invalid partition type (0x%08lx)\r\n", part_type); + return -1; + } + if ((part_num = add_partition(dev_num, part_type, part_offset, part_size)) == -1) + return -1; + else return 0; + } + printf("Maxim number(%d) of USB storage device reached \n\r", dev_num); + return -1; +} + + diff --git a/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.h b/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.h new file mode 100644 index 0000000..d8f20bb --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/usb/store/xhdi.h @@ -0,0 +1,101 @@ +/* + * David Galvez. 2010, e-mail: dgalvez75@gmail.com + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _XHDI_H +#define _XHDI_H + +typedef long __CDECL (*Func)(); + +//#define old_pun_ptr 0x516 + +#undef PUN_PTR +//#define pun_ptr pun_ptr_usb + +#define MAX_LOGICAL_DRIVE max_logical_drive + +/* AHDI */ + +#define PUN_DEV 0x1F /* device number of HD */ +#define PUN_UNIT 0x07 /* Unit number */ +#define PUN_SCSI 0x08 /* 1=SCSI 0=ACSI */ +#define PUN_IDE 0x10 /* Falcon IDE */ +#define PUN_USB 0x20 /* USB */ +#define PUN_REMOVABLE 0x40 /* Removable media */ +#define PUN_VALID 0x80 /* zero if valid */ + +#define PINFO_PUNS 0 // 2 bytes +#define PINFO_PUN 2 // 16 bytes +#define PINFO_PSTART 18 // 16 x 4 bytes +#define PINFO_COOKIE 82 // 4 bytes +#define PINFO_COOKPTR 86 // 4 bytes +#define PINFO_VERNUM 90 // 2 bytes +#define PINFO_MAXSIZE 92 // 2 bytes +#define PINFO_PTYPE 94 // 16 x 4 bytes +#define PINFO_PSIZE 158 // 16 x 4 bytes +#define PINFO_FLAGS 222 // 16 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable +#define PINFO_BPB 256 // 16 x 32 bytes +#define PINFO_SIZE 768 + +struct pun_info +{ + short puns; /* Number of HD's */ + char pun [16]; /* AND with masks below: */ + long pstart [16]; + long cookie; /* 'AHDI' if following valid */ + long *cook_ptr; /* Points to 'cookie' */ + unsigned short version_num; /* AHDI version */ + unsigned short max_sect_siz; /* Max logical sec size */ + long reserved[16]; /* Reserved */ +}; + +struct usb_pun_info +{ + short puns; /* Number of HD's */ + char pun [16]; /* AND with masks below: */ + long pstart [16]; + long cookie; /* 'AHDI' if following valid */ + long *cook_ptr; /* Points to 'cookie' */ + unsigned short version_num; /* AHDI version */ + unsigned short max_sect_siz; /* Max logical sec size */ + long reserved[16]; /* Reserved */ + long ptype[16]; + long psize[16]; + unsigned short flags[16]; +}; + +/* PARTITIONS TYPES */ +#define GEM 0x47454D // GEM up to 16 MB +#define BGM 0x42474D // BGM over 16 MB +#define RAW 0x524157 // RAW +#define FAT16_32MB 0x4 // DOS FAT16 up to 32 MB +#define FAT16 0x6 // DOS FAT16 over 32 MB +#define FAT16_WIN95 0xE // WIN95 FAT16 +#define FAT32 0xB // FAT32 +#define FAT32_II 0xC // FAT32 + +typedef struct xbra XBRA; +struct xbra { + long xb_magic; /* "XBRA" = 0x58425241 */ + long xb_id; /* ID of four ASCII characters */ + Func xb_oldvec; /* Old value of the vectors */ + short jump; + Func handle; +}; + + +#endif /* _XHDI_H */ diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/asm.sh b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/asm.sh new file mode 100644 index 0000000..58c4f53 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/asm.sh @@ -0,0 +1,6 @@ +#!/bin/bash +export DSP_PATH=~/.wine/drive_c/Programme/Motorola/DSP56300/clas + +wine $DSP_PATH/asm56300.exe -b -g -l $1.asm +wine $DSP_PATH/dsplnk.exe $1.cln +wine $DSP_PATH/cldlod.exe $1.cld > $1.lod diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm new file mode 100644 index 0000000..ff0d2b6 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm @@ -0,0 +1,13 @@ + + move #1,n1 + move #10,r1 + nop + move (r1)+n1 + move #15,m1 + rep #10 + move (r1)+n1 + move #10,n1 + rep #10 + move (r1)+n1 + + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm new file mode 100644 index 0000000..9e400e8 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm @@ -0,0 +1,12 @@ + +; clear CCR + andi #$00,CCR + move #>0.25,a + abs a + move #>-0.25,a + abs a + move #>0,a + abs a + move #>$80,a2 + abs a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm new file mode 100644 index 0000000..0589a4e --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm @@ -0,0 +1,11 @@ + move #>0,y0 + move #>1,y1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + adc y,b + move #>$800000,y1 + move #>$80,b2 + adc y,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm new file mode 100644 index 0000000..ba12582 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm @@ -0,0 +1,11 @@ + move #>0,y0 + move #>1,y1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + add y,b + move #>$800000,y1 + move #>$80,b2 + add y,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm new file mode 100644 index 0000000..dd80cb5 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm @@ -0,0 +1,9 @@ + move #>$55,a + clr b + move #>$55,b0 + andi #$00,ccr + addl a,b + move #>$AA,a + addl a,b + move #>$80,b2 + addl a,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm new file mode 100644 index 0000000..7be3b44 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm @@ -0,0 +1,9 @@ + move #>$55,a + clr b + move #>$55,b0 + andi #$00,ccr + addr a,b + move #>$AA,a + addr a,b + move #>$80,b2 + addr a,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm new file mode 100644 index 0000000..72aba75 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm @@ -0,0 +1,12 @@ + move #>$000FFF,y0 + move #>$FFFFFF,b + andi #$00,ccr + and y0,b + move #>$FFF000,y0 + move #>$FFFFFF,b + andi #$00,ccr + and y0,b + move #>$000000,y0 + move #>$FFFFFF,b + andi #$00,ccr + and y0,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm new file mode 100644 index 0000000..9a7244b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm @@ -0,0 +1,8 @@ +; move #>0,y0 +; move #>1,y1 + clr b + move #>$A5,b0 + move #>$A5,b1 + move #>$A5,b2 + andi #$00,ccr + asl b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm new file mode 100644 index 0000000..c37a0cc --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm @@ -0,0 +1,8 @@ +; move #>0,y0 +; move #>1,y1 + clr b + move #>$A5,b0 + move #>$A5,b1 + move #>$A5,b2 + andi #$00,ccr + asr b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm new file mode 100644 index 0000000..2fe6ff5 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm @@ -0,0 +1,20 @@ + clr a + clr b + andi #$00,ccr + move #>$7F,a2 + move #>$7F,b2 + add a,b + + clr a + clr b + andi #$00,ccr + move #>$80,a2 + move #>$7F,b2 + add a,b + + clr a + clr b + andi #$00,ccr + move #>$80,a2 + move #>$80,b2 + add a,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm new file mode 100644 index 0000000..6b2083d --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm @@ -0,0 +1,9 @@ + +; clear CCR + andi #$00,CCR + move #>0.25,a + clr a + move #>-0.25,a + andi #$00,CCR + ori #$01,CCR + clr a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm new file mode 100644 index 0000000..978933f --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm @@ -0,0 +1,20 @@ + move #$20,b + move #$24,y0 + andi #$00,ccr + cmp y0,b + move #$20,b + move #$20,y0 + andi #$00,ccr + cmp y0,b + move #$24,b + move #$20,y0 + andi #$00,ccr + cmp y0,b + move #$800AAA,b + move #$20,y0 + andi #$00,ccr + cmp y0,b + move #$800AAA,y0 + move #$20,b + andi #$00,ccr + cmp y0,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm new file mode 100644 index 0000000..a63a0d4 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm @@ -0,0 +1,20 @@ + move #$20,b + move #$24,y0 + andi #$00,ccr + cmpm y0,b + move #$20,b + move #$20,y0 + andi #$00,ccr + cmpm y0,b + move #$24,b + move #$20,y0 + andi #$00,ccr + cmpm y0,b + move #$800AAA,b + move #$20,y0 + andi #$00,ccr + cmpm y0,b + move #$800AAA,y0 + move #$20,b + andi #$00,ccr + cmpm y0,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm new file mode 100644 index 0000000..381c5dc --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm @@ -0,0 +1,8 @@ + move #>$000FFF,y0 + move #>$FF00FF,b + andi #$00,ccr + eor y0,b + move #>$FFFFFF,y0 + move #>$FFFFFF,b + andi #$00,ccr + eor y0,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm new file mode 100644 index 0000000..51e845f --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm @@ -0,0 +1,7 @@ + + andi #$00,CCR + move #>0.25,a + move #>$AAAAAA,a + move #>$BCDEFA,a0 + rep #24 + lsl a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm new file mode 100644 index 0000000..87177a9 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm @@ -0,0 +1,7 @@ + + andi #$00,CCR + move #>0.25,a + move #>$AAAAAA,a + move #>$BCDEFA,a0 + rep #24 + lsr a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm new file mode 100644 index 0000000..b97fb6a --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm @@ -0,0 +1,17 @@ + + andi #$00,CCR + clr a + move #$80,a2 + move #>0.25,x0 + move #>0.50,y0 + mac -x0,y0,a + move #>-0.25,x0 + move #>-0.55,y0 + mac x0,y0,a + move #>-0.20,x0 + move #>+0.55,y0 + mac x0,y0,a + move #>-0.20,x0 + move #>+0.55,y0 + mac -x0,y0,a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm new file mode 100644 index 0000000..ebbfdf5 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm @@ -0,0 +1,17 @@ + + andi #$00,CCR + clr a + move #$100000,a + move #>$123456,x0 + move #>$123456,y0 + macr x0,y0,a + move #$100001,a + move #>$123456,x0 + move #>$123456,y0 + macr x0,y0,a + move #$100000,a + move #$800000,a0 + move #>$123456,x0 + move #>$123456,y0 + macr x0,y0,a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm new file mode 100644 index 0000000..afde500 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm @@ -0,0 +1,15 @@ + + andi #$00,CCR + move #>0.25,x0 + move #>0.50,y0 + mpy x0,y0,a + move #>-0.25,x0 + move #>-0.55,y0 + mpy x0,y0,a + move #>-0.20,x0 + move #>+0.55,y0 + mpy x0,y0,a + move #>-0.20,x0 + move #>+0.55,y0 + mpy -x0,y0,a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm new file mode 100644 index 0000000..847bccf --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm @@ -0,0 +1,5 @@ + + andi #$00,CCR + move #>$654321,y0 + mpyr -y0,y0,a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm new file mode 100644 index 0000000..9fbc708 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm @@ -0,0 +1,10 @@ + + andi #$00,CCR + move #>$654321,a + neg a + clr a + move #>$80,a2 + neg a + move #>$800000,a + neg a + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm new file mode 100644 index 0000000..50749fe --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm @@ -0,0 +1,14 @@ + clr a + move #$000001,a1 + tst a + rep #$2F + norm R3,a + clr a + move #$FF0000,a + move #$84,a2 + tst a + rep #$2F + norm R1,a + clr a + rep #$2F + norm R2,a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm new file mode 100644 index 0000000..997fb45 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm @@ -0,0 +1,8 @@ + move #>$000FFF,y0 + move #>$7F00FF,b + andi #$00,ccr + not b + move #>$000000,y0 + move #>$FFFFFF,b + andi #$00,ccr + not b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm new file mode 100644 index 0000000..025991f --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm @@ -0,0 +1,8 @@ + move #>$000FFF,y0 + move #>$FF00FF,b + andi #$00,ccr + or y0,b + move #>$000000,y0 + move #>$000000,b + andi #$00,ccr + or y0,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm new file mode 100644 index 0000000..9c7f4bb --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm @@ -0,0 +1,11 @@ + + andi #$00,CCR + move #>$123456,a1 + move #>$789ABC,a0 + rnd a + move #>$123456,a1 + move #>$800000,a0 + rnd a + move #>$123455,a1 + move #>$800000,a0 + rnd a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm new file mode 100644 index 0000000..4f69ef6 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm @@ -0,0 +1,6 @@ + + andi #$00,CCR + move #>$AAAAAA,a + move #>$BCDEFA,a0 + rep #24 + rol a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm new file mode 100644 index 0000000..4fcca89 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm @@ -0,0 +1,6 @@ + + andi #$00,CCR + move #>$AAAAAA,a + move #>$BCDEFA,a0 + rep #24 + ror a diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm new file mode 100644 index 0000000..7beb742 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm @@ -0,0 +1,15 @@ + move #>0,y0 + move #>1,y1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + sbc y,b + move #>$800000,y1 + move #>$80,b2 + sbc y,b + clr b + move #>$80,b2 + move #>$1,y1 + sbc y,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm new file mode 100644 index 0000000..fa69320 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm @@ -0,0 +1,15 @@ + move #>0,y0 + move #>1,y1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + sub y,b + move #>$800000,y1 + move #>$80,b2 + sub y,b + clr b + move #>$80,b2 + move #>$1,y1 + sub y1,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm new file mode 100644 index 0000000..4d4a601 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm @@ -0,0 +1,15 @@ + move #>0,a0 + move #>1,a1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + subl a,b + move #>$800000,a1 + move #>$80,b2 + subl a,b + clr b + move #>$80,b2 + move #>$1,a1 + subl a,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm new file mode 100644 index 0000000..989ff9a --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm @@ -0,0 +1,15 @@ + move #>0,a0 + move #>1,a1 + clr b + move #>1,b0 +; set only carry bit + andi #$00,ccr + ori #$01,ccr + subr a,b + move #>$800000,a1 + move #>$80,b2 + subr a,b + clr b + move #>$80,b2 + move #>$1,a1 + subr a,b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm new file mode 100644 index 0000000..dd471b3 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm @@ -0,0 +1,10 @@ + move #20,r1 + move #$ABCDEF,x0 + move #$123456,b + andi #$00,ccr + tcs x0,a r1,r3 + tcc x0,b r1,r2 + ; set Zero Flag + ori #$04,ccr + teq x0,a r1,r3 + tne x0,b r1,r2 diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm new file mode 100644 index 0000000..26fa4c1 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm @@ -0,0 +1,7 @@ + move #$ABCDEF,a + move #$123456,b + tfr a,b b,a + move #$555555,x0 + move #$AAAAAA,y1 + tfr x0,a a,x0 + tfr y1,b b,y0 diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm new file mode 100644 index 0000000..b86e4a4 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm @@ -0,0 +1,9 @@ + clr b + tst b +; set only carry bit + andi #$00,ccr + ori #$01,ccr + move #>$80,b2 + tst b + move #>$7F,b2 + tst b diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm new file mode 100644 index 0000000..17599e4 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm @@ -0,0 +1,8 @@ + + move #4,r0 + move #20,r1 + move r1,x:(r0) + move x:(r0),a + move r1,y:(r0) + move l:(r0)+,ab + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm new file mode 100644 index 0000000..821d39b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm @@ -0,0 +1,21 @@ + + move #>$10,x0 + move #>$11,x1 + move #11,a1 + move #-3,a2 + jclr #0,a,blubb + bset #0,x:(r0)+ + move #>$26,y0 + move #>$27,y1 + move x,L:(r0)+ + move y,L:(r0)+ + move x,L:$0A + move y,L:$1F + move y,L:$00A0 + move x,L:$004F + move L:-(r0),x + move L:-(r0),y + move L:$0A,x + move L:$1F,y +blubb + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/doc/Change.log b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/doc/Change.log new file mode 100644 index 0000000..1dc8d5b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/doc/Change.log @@ -0,0 +1,185 @@ +Done: +02.01.09 + - Started work on pipeline (FE, FE2, DC, AG, EX) + - Program counter counts linearly + - Initial program memory holds program data + - Started work on instruction decoder +03.01.09 + - Jump instructions work (with flushing of the pipeline) + - First version of AGU implemented + - Detection of double word instructions + - Initial version of global register file +04.01.09 + - Included hardware stack + - Finished support for JSR and JSCC instructions + - RTI/RTS work + - ANDI/ORI work + - Initial work on REP instruction +10.01.09 + - Initial suppurt for X memory accesses. One stall cycle is introduced when + accessing the X memory. + - Finished implementation of REP instruction. Reading number of loops from + registers is still missing. + - Initial support for DO loops. + - Preventing to write the R registers when stalling occurs or a jump is + performed +11.01.09 + - Finished implementation of DO loops (stop looping at the end) + - Nested loops work + - Single instruction loops work + - ENDDO instruction implemented (very much the same as usual end of the loop) +12.01.09 + - Included Y memory and its addressing modes for REP and DO instruction. + - Setup of a sheet showing which types of which instructions have been + implemented and how many clock cycles are needed. +16.01.09 + - Integration of LUA instruction. +24.01.09 + - Integrated different addressing schemes (immediate short, immediate long, + absolute address) + - Integration and test of MOVE(C) instruction. Some modes missing (writing to + memory) + - Testing of Y memory read accesses. +26.01.09 + - Continued testing of different addressing modes. + - Decoding for first parallel move operations. +01.02.09 + - Moved memory components to an extra entity (memory_management) + - Writing to internal X and Y memory supported. Problems are possible for + reading the same address one instruction after writing at the same address! + - Included ALU registers (x,y,a,b) into register file + - Integration of x/y/l bus started +03.02.09 + - Continued testing of parallel moves (there are quite a few cases!) +07.02.09 + - Fixed REP instruction for instructions that are causing a stall due to + a memory read + - Fixed fetching from program data when stalling. + - Fixed detection of double word instruction, when previous instruction + used the AGU as well (forgot instruction word in sensitivity list). + - Continued testing of parallel moves. + - First synthesis run: Changed RAM description to map to BRAMs, removed + latches, and many things are still missing, post-synthesis results: + - Xilinx Spartan3A, Speed-Grade -4 + - 1488 FFs + - 4657 4-Input LUTs + - 3 BRAMs + - 71.08 MHz +08.02.09 + - Implemented second address generation unit in order to access X and Y + memory at the same time + - Implemented reverse carry addressing modes for FFT addressing + - Started implementation of modulo addressing. + - Set M0-M7 to -1 in reset. + - Downloaded the assembler for DSP56300. I hope to use it in order to + generate the content of the program memory automatically, which will + boost the testing speed... + - Encoding each instruction to test by hand just sucks. I think I will + integrate some bootloader in order to use the LOD files from the + assembler to initiate the RAMs. + - Implementation of data shifter and limiter (when accessing a or b and + giving the result to XDB or YDB). Needs testing. + - Integration for L: addressing modes. Needs nesting. +10.02.09 + - Fixed decoding of X: and Y: adressing mode (collided with L: adressing) + - L: adressing modes are working +14.02.09 + - Implemented BCHG,BCLR,BSET,BTST,JCLR,JSCLR,JSET,JSSET. A lot of testing + is still needed. Peripheral register accesses are still missing. + - Second synthesis run: Removed new latches again. + , many things are still missing, post-synthesis results: + - Xilinx Spartan3A, Speed-Grade -4 + - 1519 FFs + - 6210 4-Input LUTs + - 3 BRAMs + - 51.68 MHz + * Critical path for JSCLR/JSSET=> read limited a/b, go through bit modify + unit, test whether condition met, push data to stack. Reading of + limited A/B is probably a bug (DSP56001 UM says CCR is not changed, + in DSP56300 simulator the flag is set when reading a/b!!). +15.02.09 + - Started implementing the ALU. + - ABS works. + - MPY(R), MAC(R) implemented, rounding is missing. + - Clock frequency dropped to 41 MHz, but the critical path is not caused by + the MAC in the ALU! The multiplier is composed of four 18x18 multipliers + and still seems to be very fast! +16.02.09 + - Implemented decoding and controlling of ALU for + ADC, ADD, ADDL, ADDR, AND, ASL, ASR, CLR, CMP, CMPM, EOR, NEG, NOT, OR + Still missing ALU instructions: + DIV, NORM, RND, ROL, ROR, SBC, SUB, SUBL, SUBR, Tcc, TFR, TST + Except for DIV and NORM this will be straight forward. + - Other things that need to be done : + * Adress Generation Unit does not support modulo addressing. + * MOVEP/MOVEM/STOP/WAIT/ILLEGAL/RESET/SWI + * Interrupts + * External memory accesses + * Peripheral devices (SCI, SSI, Host port) +17.02.09 + - Implemented decoding and controlling of ALU instructions for + RND, ROL, ROR, SBC, SUB, SUBL, SUBR, TFR, TST + Still missing ALU instructions: + DIV, NORM, Tcc +08.03.09 + - Forgot integration of LSR and LSL instructions. TBD. + - Started integration of Condition flag generation in ALU. + - New synthesis run with ALU, register balancing: + - Xilinx Spartan3A, Speed-Grade -4 + - 3115 FFs + - 7417 4-Input LUTs + - 3 BRAMs + - 39.47 MHz +13.03.09 + - Integrated decoding of LSL/LSR instructions. + - Integrated rotating function into ALU. + - Included convergent rounding functionality into ALU. + - Implemented Tcc instruction. + - Implemented DIV instruction. +15.03.09 + - Tested ABS,ADC,ADD,ADDL,ADDR,AND,ASL,ASR,CLR,CMP,CMPM,DIV,EOR, + LSL,LSR,MPY,MPYR,MAC,MACR,NEG,NOT,OR + - Bugs fixed: + - Detection of overflow corrected when negating most negative + value $80 000000 000000. + - Decoding of ADC and TFR clarified. + - Overflow flag generation when left shifting of 56 bit values. + - For logical operations the flag generation relied on the adder + output which was wrong. Now relies on the Logical unit output. + - Decoding of CMPM clarified in order not to conflict with NOT. + - Shifter was used for CMP(M) instructions, which is wrong. + - Hopefully calculation of carry and overflow flag work correctly now... + - MPY/MAC write result back. + - Limit Flag is not cleared by the ALU anymore (has to be reset by the + user!). +16.03.09 + - Tested RND + - Bugs fixed: + - Simulator seems to misunderstand the X"1000000" where the first digit + represents a single bit. Comparing against this value fixed! RND works. + +17.03.09 + - Tested ROR,ROL,SBC,SUB,SUBL,SUBR,TCC,TFR,TST,NORM + - Integrated logic for NORM instruction support. + - ALU is complete now! + - Bugs fixed: + - Fixed setting of CCR for ROL/ROR + - TCC didn't read register through ALU + - Known bugs: + - Carry calculation for SBC is still buggy + - New synthesis run with ALU, register balancing: + - Xilinx Spartan3A, Speed-Grade -4 + - 1801 FFs + - 7407 4-Input LUTs + - 3 BRAMs + - 30.84 MHz + Critical path is in the ALU (multiplication, adding, rounding, zero-flag + calculation). I wonder why the values changed like that since the + last synthesis run. +26.03.09 + - Included support for modulo addressing in AGUs. This allows for the + integration of ring buffers. Now 7900 LUTs. +18.05.10 + - Commenting of code. + - Added second memory port for p-mem (needed for movem-instruction) + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd new file mode 100644 index 0000000..df96c27 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd @@ -0,0 +1,291 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Address generation logic +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity adgen_stage is port( + activate_adgen : in std_logic; + activate_x_mem : in std_logic; + activate_y_mem : in std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type +); +end entity; + + +architecture rtl of adgen_stage is + + signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0); + + signal r_reg_local_x : unsigned(BW_ADDRESS-1 downto 0); + signal n_reg_local_x : unsigned(BW_ADDRESS-1 downto 0); + signal m_reg_local_x : unsigned(BW_ADDRESS-1 downto 0); + + signal r_reg_local_y : unsigned(BW_ADDRESS-1 downto 0); + signal n_reg_local_y : unsigned(BW_ADDRESS-1 downto 0); + signal m_reg_local_y : unsigned(BW_ADDRESS-1 downto 0); + + function calculate_modulo_bitmask(m_reg_local : in unsigned ) return std_logic_vector is + variable modulo_bitmask_intern : std_logic_vector(BW_ADDRESS-1 downto 0); + begin + modulo_bitmask_intern(BW_ADDRESS-1) := m_reg_local(BW_ADDRESS-1); + for i in BW_ADDRESS-2 downto 0 loop + modulo_bitmask_intern(i) := modulo_bitmask_intern(i+1) or m_reg_local(i); + end loop; + + return modulo_bitmask_intern; + end function calculate_modulo_bitmask; + + function calculate_new_r_reg(new_r_reg_intermediate, r_reg_local, m_reg_local: in unsigned; + modulo_bitmask: in std_logic_vector ) return unsigned is + variable modulo_result : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg_intern : unsigned(BW_ADDRESS-1 downto 0); + begin + -- cut out the bits we are interested in + -- for modulo addressing + for i in 0 to BW_ADDRESS-1 loop + if modulo_bitmask(i) = '1' then + modulo_result(i) := new_r_reg_intermediate(i); + else + modulo_result(i) := '0'; + end if; + end loop; + -- compare whether an overflow occurred and we + -- have to renormalize the result + if modulo_result > m_reg_local then + modulo_result := modulo_result - m_reg_local; + end if; + + -- linear addressing + if m_reg_local = 2**BW_ADDRESS-1 then + new_r_reg_intern := new_r_reg_intermediate; + -- bit reverse operation + elsif m_reg_local = 0 then + for i in 0 to BW_ADDRESS-1 loop + new_r_reg_intern(BW_ADDRESS - 1 - i) := new_r_reg_intermediate(i); + end loop; + -- modulo arithmetic / linear addressing + else + -- only update the bits that are part of the bitmask! + for i in 0 to BW_ADDRESS-1 loop + if modulo_bitmask(i) = '1' then + new_r_reg_intern(i) := modulo_result(i); + else + new_r_reg_intern(i) := r_reg_local(i); + end if; + end loop; + end if; + return new_r_reg_intern; + end function calculate_new_r_reg; + + procedure set_operands(r_reg_local, m_reg_local, addr_mod : in unsigned; op1, op2 : out unsigned) is + begin + -- bit reverse operation + if m_reg_local = 0 then + -- reverse the input to the adder bit wise + -- so we just need to use a single adder + for i in 0 to BW_ADDRESS-1 loop + op1(BW_ADDRESS - 1 - i) := r_reg_local(i); + op2(BW_ADDRESS - 1 - i) := addr_mod(i); + end loop; + -- modulo arithmetic / linear addressing + else + op1 := r_reg_local; + op2 := addr_mod; + end if; + end procedure set_operands; + +begin + + address_out_x <= address_out_x_int; + + r_reg_local_x <= register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8)))); + n_reg_local_x <= register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8)))); + m_reg_local_x <= register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8)))); + + r_reg_local_y <= register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + n_reg_local_y <= register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + m_reg_local_y <= register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + + address_generator_X: process(activate_adgen, instr_word, adgen_mode_a, r_reg_local_x, n_reg_local_x, m_reg_local_x) is + variable op1 : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable addr_mod : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0); + variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0); + variable modulo_result : unsigned(BW_ADDRESS-1 downto 0); + begin + + -- select the operands for the calculation + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => addr_mod := unsigned(- signed(n_reg_local_x)); + -- (Rn) + Nn + when POST_PLUS_N => addr_mod := n_reg_local_x; + -- (Rn)- + when POST_MIN_1 => addr_mod := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when NOP => addr_mod := (others => '0'); + -- (Rn + Nn) + when INDEXED_N => addr_mod := n_reg_local_x; + -- -(Rn) + when PRE_MIN_1 => addr_mod := (others => '1'); -- - 1 + -- absolute address (appended to instruction word) + when ABSOLUTE => addr_mod := (others => '0'); + when IMMEDIATE => addr_mod := (others => '0'); + end case; + + ------------------------------------------------ + -- set op1 and op2 according to modulo register + ------------------------------------------------ + set_operands(r_reg_local_x, m_reg_local_x, addr_mod, op1, op2); + + ------------------------- + -- Calculate new address + ------------------------- + new_r_reg_interm := op1 + op2; + + ---------------------------------- + -- Calculate new register content + ----------------------------------- + modulo_bitmask := calculate_modulo_bitmask(m_reg_local_x); + new_r_reg := calculate_new_r_reg(new_r_reg_interm, r_reg_local_x, m_reg_local_x, modulo_bitmask); + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + -- LUA instructions DO NOT UPDATE the source register!! + if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then + wr_R_port_A_valid <= '0'; + else + wr_R_port_A_valid <= '1'; + end if; + wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8)); + wr_R_port_A.reg_value <= new_r_reg; + + -- select the output of the AGU + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => address_out_x_int <= r_reg_local_x; + -- (Rn) + Nn + when POST_PLUS_N => address_out_x_int <= r_reg_local_x; + -- (Rn)- + when POST_MIN_1 => address_out_x_int <= r_reg_local_x; + -- (Rn)+ + when POST_PLUS_1 => address_out_x_int <= r_reg_local_x; + -- (Rn) + when NOP => address_out_x_int <= r_reg_local_x; + -- (Rn + Nn) + when INDEXED_N => address_out_x_int <= new_r_reg; + -- -(Rn) + when PRE_MIN_1 => address_out_x_int <= new_r_reg; + -- absolute address (appended to instruction word) + when ABSOLUTE => address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0)); + when IMMEDIATE => address_out_x_int <= r_reg_local_x; -- Done externally, value never used + end case; + -- LUA instructions only use the updated address! + if instr_array = INSTR_LUA then + address_out_x_int <= new_r_reg; + end if; + + end process address_generator_X; + + + --------------------------------------------------------- + -- Second address generator + -- Used when accessing X and Y memory at the same time + --------------------------------------------------------- + address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word, + register_file, adgen_mode_b, address_out_x_int, r_reg_local_y, n_reg_local_y, m_reg_local_y) is + variable op1 : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable addr_mod : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0); + variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0); + variable modulo_result : unsigned(BW_ADDRESS-1 downto 0); + begin + + -- select the operands for the calculation + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => addr_mod := n_reg_local_y; + -- (Rn)- + when POST_MIN_1 => addr_mod := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when others => addr_mod := (others => '0'); + end case; + + ------------------------------------------------ + -- set op1 and op2 according to modulo register + ------------------------------------------------ + set_operands(r_reg_local_y, m_reg_local_y, addr_mod, op1, op2); + + ------------------------- + -- Calculate new address + ------------------------- + new_r_reg_interm := op1 + op2; + + ---------------------------------- + -- Calculate new register content + ----------------------------------- + modulo_bitmask := calculate_modulo_bitmask(m_reg_local_y); + new_r_reg := calculate_new_r_reg(new_r_reg_interm, r_reg_local_y, m_reg_local_y, modulo_bitmask); + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + if adgen_mode_b = NOP then + wr_R_port_B_valid <= '0'; + else + wr_R_port_B_valid <= '1'; + end if; + wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13)); + wr_R_port_B.reg_value <= new_r_reg; + + -- the address for the y memory is calculated in the first AGU if the x memory is not accessed! + -- so use the other output as address output for the y memory! + -- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!) + if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then + address_out_y <= address_out_x_int; + -- in any other case use the locally computed value + else + -- select the output of the AGU + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => address_out_y <= r_reg_local_y; + -- (Rn)- + when POST_MIN_1 => address_out_y <= r_reg_local_y; + -- (Rn)+ + when POST_PLUS_1 => address_out_y <= r_reg_local_y; + -- (Rn) + when others => address_out_y <= r_reg_local_y; + end case; + end if; + end process address_generator_Y; + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd new file mode 100644 index 0000000..c84a406 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief General constants for decoding pipeline. +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +package constants_pkg is + + + ------------------------- + -- Flags in CCR register + ------------------------- + + constant C_FLAG : natural := 0; + constant V_FLAG : natural := 1; + constant Z_FLAG : natural := 2; + constant N_FLAG : natural := 3; + constant U_FLAG : natural := 4; + constant E_FLAG : natural := 5; + constant L_FLAG : natural := 6; + constant S_FLAG : natural := 7; + + + ------------------- + -- Pipeline stages + ------------------- + + constant ST_FE_FE2 : natural := 0; + constant ST_FE2_DEC : natural := 1; + constant ST_DEC_ADG : natural := 2; + constant ST_ADG_EX : natural := 3; + + + ---------------------- + -- Activation signals + ---------------------- + + constant ACT_ADGEN : natural := 0; -- Run the address generator + constant ACT_ALU : natural := 1; -- Activation of ALU results in modification of the status register + constant ACT_EXEC_BRA : natural := 2; -- Branch (in execute stage) + constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage) + constant ACT_EXEC_LOOP : natural := 4; -- Loop instruction (REP, DO) + constant ACT_X_MEM_RD : natural := 5; -- Init read from X memory + constant ACT_Y_MEM_RD : natural := 6; -- Init read from Y memory + constant ACT_P_MEM_RD : natural := 7; -- Init read from P memory + constant ACT_X_MEM_WR : natural := 8; -- Init write to X memory + constant ACT_Y_MEM_WR : natural := 9; -- Init write to Y memory + constant ACT_P_MEM_WR : natural := 10; -- Init write to P memory + constant ACT_REG_RD : natural := 11; -- Read from register (6 bit addressing) + constant ACT_REG_WR : natural := 12; -- Write to register (6 bit addressing) + constant ACT_IMM_8BIT : natural := 13; -- 8 bit immediate operand (in instruction word) + constant ACT_IMM_12BIT : natural := 14; -- 12 bit immediate operand (in instruction word) + constant ACT_IMM_LONG : natural := 15; -- 24 bit immediate operant (in optional instruction word) + constant ACT_X_BUS_RD : natural := 16; -- Read data via X-bus (from x0,x1,a,b) + constant ACT_X_BUS_WR : natural := 17; -- Write data via X-bus (to x0,x1,a,b) + constant ACT_Y_BUS_RD : natural := 18; -- Read data via Y-bus (from y0,y1,a,b) + constant ACT_Y_BUS_WR : natural := 19; -- Write data via Y-bus (to y0,y1,a,b) + constant ACT_L_BUS_RD : natural := 20; -- Read data via L-bus (from a10, b10,x,y,a,b,ab,ba) + constant ACT_L_BUS_WR : natural := 21; -- Write data via L-bus (to a10, b10,x,y,a,b,ab,ba) + constant ACT_BIT_MOD_WR : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG) + constant ACT_REG_WR_CC : natural := 23; -- Write to register file conditionally (Tcc) + constant ACT_ALU_WR_CC : natural := 24; -- Write ALU result conditionally (Tcc) + constant ACT_NORM : natural := 25; -- NORM instruction needs special handling + +end package constants_pkg; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd new file mode 100644 index 0000000..0725c6b --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd @@ -0,0 +1,1226 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Instruction Decoder +--! +--! @details This entity generates multiple flags depending on the instruction +--! word. The flags are used for activation of certain logic units within the +--! subsequent pipeline stages (ALU, AGU, bit modifications, ...). Also the +--! decoder checks whether currently we are processing a double word +--! instruction. +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type +); +end entity; + + +architecture rtl of decode_stage is + + signal instr_array_int : instructions_type; +-- signal activate_pm_int : std_logic; + type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y); + -- SINGLE_X : MMMRRR + -- SINGLE_X_SHORT : MMRRR + -- DOUBLE_X_Y : mmrrMMRRR + signal adgen_bittype : adgen_bittype_type; + + signal ea_extension_available : std_logic; + + signal alu_tcc_decoded : std_logic; + signal alu_div_decoded : std_logic; + signal alu_norm_decoded : std_logic; + +begin + + + -- output the decoded instruction + instr_array <= instr_array_int; + + -- calculate whether this is a double word instruction + dble_word_instr <= '1' when ea_extension_available = '1' or + instr_array_int = INSTR_DO or + instr_array_int = INSTR_JCLR or + instr_array_int = INSTR_JSCLR or + instr_array_int = INSTR_JSET or + instr_array_int = INSTR_JSSET else + '0'; + + alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded, + alu_div_decoded, alu_norm_decoded) is + variable instr_word_var : std_logic_vector(23 downto 0); + begin + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + alu_ctrl.mul_op1 <= (others => '0'); + alu_ctrl.mul_op2 <= (others => '0'); + alu_ctrl.rotate <= '0'; + alu_ctrl.div_instr <= '0'; + alu_ctrl.norm_instr <= '0'; + alu_ctrl.shift_src <= '0'; + alu_ctrl.shift_src_sign <= (others => '0'); + alu_ctrl.shift_mode <= ZEROS; + alu_ctrl.add_src_stage_1 <= (others => '0'); + alu_ctrl.add_src_stage_2 <= (others => '0'); + alu_ctrl.add_src_sign <= (others => '0'); + alu_ctrl.logic_function <= (others => '0'); + alu_ctrl.word_24_update <= '0'; + alu_ctrl.rounding_used <= (others => '0'); + alu_ctrl.store_result <= '0'; + for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C) + alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH; + end loop; + alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations + + -- check wether instruction that allows parallel moves + -- has to be decoded, then it is an ALU operation in the 8 LSBs + -- Only exceptions are DIV, NORM, and Tcc + if instr_word_var(23 downto 20) /= "0000" then + -- ABS + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- source/dst are the same register + alu_ctrl.shift_src_sign <= "10"; -- the sign of the operand depends on the operand + -- negative operand will negate the content of the accu as + -- needed by the ABS instruction + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags but carry + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "10"; -- add carry to result of addition + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADD + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- AND / OR / EOR + if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and + instr_word_var(2 downto 0) = "010" or -- or + instr_word_var(2 downto 0) = "011") then -- eor + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not + alu_ctrl.word_24_update <= '1'; -- only accumulator bits 47 downto 24 affected? + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- ASL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ASR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CLR + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- CMP + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CMPM + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "111" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "10"; -- with the sign dependant sign (magnitude!) + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "10"; -- with sign dependant sign (magnitude!) + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- MPY, MPYR, MAC, MACR + if instr_word_var(7) = '1' then + case instr_word_var(6 downto 4) is + when "000" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0 + when "001" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0 + when "010" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0 + when "011" => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0 + when "100" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1 + when "101" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0 + when "110" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0 + when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1 + end case; + alu_ctrl.store_result <= '1'; -- store result in accu + alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder! + alu_ctrl.add_src_sign <= '0' & instr_word_var(2); -- select +/- + alu_ctrl.rounding_used <= '0' & instr_word_var(0); -- rounding is determined by that bit! + if instr_word_var(1) = '0' then -- MPY(R) + alu_ctrl.shift_mode <= ZEROS; + else -- MAC(R) + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + end if; + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NEG + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; +-- alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to +-- alu_ctrl.shift_src_sign <= "01"; -- with negative sign + -- Read Accu + alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register + alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NOT + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- select not operation + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- RND + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "01"; -- normal rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ROL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- ROR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- SBC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "11"; -- subtract carry + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUB + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- TFR + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then + -- do not read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- do not set any flag at all! + end if; + -- TST + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then + -- do not read accu + alu_ctrl.shift_mode <= NO_SHIFT; -- no shift + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.shift_src_sign <= "00"; -- sign unchanged + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '0'; -- do not store the result + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + end if; -- Parallel move ALU instructions + + -- Tcc + if alu_tcc_decoded = '1' then + -- Read source + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + -- The .store_result flag is generated in the execute stage + -- depending on the condition codes + -- do not set any flag at all! + end if; +--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--shift_src : std_logic; -- a,b +--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved +--shift_mode : alu_shift_mode; +--add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b +--add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved +--add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction! +--logic_function : std_logic_vector(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not +--word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? +--rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry +--store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator +--dst_accu : std_logic; -- 0: a, 1: b + -- DIV + if alu_div_decoded = '1' then + alu_ctrl.store_result <= '1'; -- do store the result + -- shifter operation + alu_ctrl.shift_mode <= SHIFT_LEFT; -- shift left + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.div_instr <= '1'; -- this is THE div instruction, special handling needed + -- source operand loading + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + alu_ctrl.add_src_sign <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] + -- if 1: positive, if 0: negative + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY; + end if; + -- NORM + if alu_norm_decoded = '1' then + -- set all alu-ctrl signals to ASL/ASR already here + -- depending on the condition code registers the flags + -- will be completed in the execute stage + alu_ctrl.norm_instr <= '1'; + -- Read accu + --alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + + end if; + end process; + + + instruction_decoder: process(instr_word, activate_dec) is + variable instr_word_var : std_logic_vector(23 downto 0); + procedure activate_AGU is + begin + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + end procedure activate_AGU; + begin + instr_array_int <= INSTR_NOP; + act_array <= (others => '0'); + adgen_bittype <= NOP; + reg_rd_addr <= (others => '0'); + reg_wr_addr <= (others => '0'); + x_bus_rd_addr <= (others => '0'); + x_bus_wr_addr <= (others => '0'); + y_bus_rd_addr <= (others => '0'); + y_bus_wr_addr <= (others => '0'); + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + + alu_tcc_decoded <= '0'; + alu_div_decoded <= '0'; + alu_norm_decoded <= '0'; + + -- in case the decoding is not activated we insert a nop + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + if instr_word_var(23 downto 16) = X"00" then + case instr_word_var(15 downto 0) is + when X"0000" => instr_array_int <= INSTR_NOP; + when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1'; + when X"0005" => instr_array_int <= INSTR_ILLEGAL; + when X"0006" => instr_array_int <= INSTR_SWI; + when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1'; + when X"0084" => instr_array_int <= INSTR_RESET; + when X"0086" => instr_array_int <= INSTR_WAIT; + when X"0087" => instr_array_int <= INSTR_STOP; + when X"008C" => instr_array_int <= INSTR_ENDDO; + act_array(ACT_EXEC_LOOP) <= '1'; + when others => + act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register + if instr_word_var(7 downto 2) = "101110" then + instr_array_int <= INSTR_ANDI; + elsif instr_word_var(7 downto 2) = "111110" then + instr_array_int <= INSTR_ORI; + end if; + end case; + end if; + --------------------------------------------------------- + -- DIV and NORM + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"01" then + -- DIV + if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then + alu_div_decoded <= '1'; + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- NORM + if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and + instr_word_var(2 downto 0) = "101" then + alu_norm_decoded <= '1'; + act_array(ACT_NORM) <= '1'; -- NORM instruction decoded, + -- special handling in exec-stage is caused + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + end if; + end if; + --------------------------------------------------------- + -- Tcc + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and + instr_word_var(2 downto 0) = "000" then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and + instr_word_var(7) = '0' then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + act_array(ACT_REG_WR_CC) <= '1'; + reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn + reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn + end if; + end if; + --------------------------------------------------------- + -- MOVEC and LUA instruction with registers + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"04" then + act_array(ACT_REG_WR) <= '1'; + -- LUA instruction + if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then + instr_array_int <= INSTR_LUA; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + -- MOVEC instruction (S1, D2) or (S2, D1) + if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_REG_RD) <= '1'; + -- Write D1 + if instr_word_var(15) = '1' then + reg_wr_addr <= instr_word_var(5 downto 0); + reg_rd_addr <= instr_word_var(13 downto 8); + -- Read S1 + else + reg_wr_addr <= instr_word_var(13 downto 8); + reg_rd_addr <= instr_word_var(5 downto 0); + end if; + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with memory access/absolute address + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and + instr_word_var(7) = '0' and instr_word_var(5) = '1' then + + instr_array_int <= INSTR_MOVEC; + -- read from memory, write to register + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + -- X Memory read? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- write to memory, read register + else + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + -- X Memory write? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with immediate + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + --------------------------------- + -- REP or DO loop? + --------------------------------- + if instr_word_var(23 downto 16) = X"06" then + -- Instruction encoding is the same for both except of this bit + if instr_word_var(5) = '1' then + instr_array_int <= INSTR_REP; + else + instr_array_int <= INSTR_DO; + end if; + act_array(ACT_EXEC_LOOP) <= '1'; + -- Init reading of loop counter from memory + if instr_word_var(15) = '0' and instr_word_var(7) = '0' then + -- X/Y: ea? + if instr_word_var(14) = '1' then + act_array(ACT_ADGEN) <= '1'; + end if; + -- X/Y: aa? + -- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not! + -- If not the absolute address stored in the instruction word is used. + ------- + -- only a single memory access is required + adgen_bittype <= SINGLE_X; + -- X/Y as source? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then + -- S (register as source) + reg_rd_addr <= instr_word_var(13 downto 8); + act_array(ACT_REG_RD) <= '1'; + -- #xxx ,12 bit immediate + elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then + act_array(ACT_IMM_12BIT) <= '1'; + end if; + end if; + -------------------------------- + -- MOVEM (Program memory move) + -------------------------------- + if instr_word_var(23 downto 16) = X"07" then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_RD) <= '1'; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_WR) <= '1'; + end if; + -- AGU needed? + if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -------------------------------- + -- MOVEP (Peripheral memory move) + -------------------------------- + if instr_word_var(23 downto 16) = "0000100-" then + -- TODO?? Why parallel moves in software model?? + case instr_word_var(15 downto 0) is +-- when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1'; + when others => + end case; + end if; + -- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR + if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then + + reg_rd_addr <= instr_word_var(13 downto 8); + reg_wr_addr <= instr_word_var(13 downto 8); + + if instr_word_var(16) = '0' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCLR; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BSET; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSET; + end if; + elsif instr_word_var(16) = '1' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCHG; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BTST; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JSCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSSET; + end if; + end if; + if instr_word_var(7) = '1' then + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + -- memory access? + if instr_word_var(15) = '0' then + -- X: + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_X_MEM_WR) <= '1'; + end if; + -- Y: + else + act_array(ACT_Y_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + end if; + + case instr_word_var(15 downto 14) is + -- X:/Y: aa + when "00" => + + -- X:/Y: ea + when "01" => + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + + -- X:/Y: pp + -- TODO! + when "10" => + + when others => -- "11" + if instr_word_var(7 downto 0) = "10000000" then + -- JMP/JSR ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JMP; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSR; + end if; + elsif instr_word_var(7 downto 4) = "1010" then + -- JCC/JSCC ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JCC; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSCC; + end if; + -- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D + else + act_array(ACT_REG_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_REG_WR) <= '1'; + end if; + end if; + end case; + end if; + -- JMP xxx (absoulute short) + if instr_word_var(23 downto 16) = X"0C" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JMP; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JSR xxx (absolute short) + if instr_word_var(23 downto 16) = X"0D" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JSR; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0E" then + instr_array_int <= INSTR_JCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + -- JSCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0F" then + instr_array_int <= INSTR_JSCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + ------------------------------------------------ + -- PARALLEL MOVE SECTION!! + ------------------------------------------------ + -- Here are the ALU operations that allow for parallel moves + if instr_word_var(23 downto 20) /= "0000" then + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- PM: I + if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(20 downto 16); + end if; + -- PM: R + if instr_word_var(23 downto 18) = "001000" then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(12 downto 8); + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(17 downto 13); + end if; + -- PM: U + if instr_word_var(23 downto 13) = "00100000010" then + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + end if; + -- PM: X or PM:Y + if instr_word_var(23 downto 22) = "01" and + -- Check whether L: type parallel move. If so do not enter this branch! + not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory read? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory write? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -- PM: X:R or R:Y (Class I) + if instr_word_var(23 downto 20) = "0001" then + adgen_bittype <= SINGLE_X; + -- X:R + if instr_word_var(14) = '0' then + x_bus_rd_addr <= instr_word_var(19 downto 18); + x_bus_wr_addr <= instr_word_var(19 downto 18); + y_bus_rd_addr <= '1' & instr_word_var(17); + y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs! + -- S2,D2 in any case! + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_X_BUS_RD) <= '1'; + end if; + -- R:Y + elsif instr_word_var(14) = '1' then + x_bus_rd_addr <= '1' & instr_word_var(19); + x_bus_wr_addr <= '0' & instr_word_var(18); + y_bus_rd_addr <= instr_word_var(17 downto 16); + y_bus_wr_addr <= instr_word_var(17 downto 16); + -- S1,D1 in any case! + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_Y_MEM_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_Y_MEM_WR) <= '1'; + act_array(ACT_Y_BUS_RD) <= '1'; + end if; + + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: X:R or R:Y (Class II) + if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then + act_array(ACT_REG_RD) <= '1'; + -- X:R + if instr_word_var(15) = '0' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory + x_bus_rd_addr <= "00"; -- read x0 + x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- R:Y + elsif instr_word_var(15) = '1' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory + y_bus_rd_addr <= "00"; -- read y0 + y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: L: + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then + -- Read S? + if instr_word_var(15) = '0' then + act_array(ACT_L_BUS_RD) <= '1'; + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_Y_MEM_WR) <= '1'; + else -- Write D + act_array(ACT_L_BUS_WR) <= '1'; + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + if instr_word_var(14) = '1' then + adgen_bittype <= SINGLE_X; + activate_AGU; + else + -- L:aa automatically performed in ADGEN stage + end if; + end if; + -- PM: X: Y: + if instr_word_var(23) = '1' then + adgen_bittype <= DOUBLE_X_Y; + -- No immediate value allowed, so activate in any case! + act_array(ACT_ADGEN) <= '1'; + -- S1, X: + if instr_word_var(15) = '0' then + act_array(ACT_X_BUS_RD) <= '1'; + x_bus_rd_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_WR) <= '1'; + -- X:, D1 + else + act_array(ACT_X_BUS_WR) <= '1'; + x_bus_wr_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_RD) <= '1'; + end if; + -- S2, Y: + if instr_word_var(22) = '0' then + act_array(ACT_Y_BUS_RD) <= '1'; + y_bus_rd_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_WR) <= '1'; + -- Y:, D2 + else + act_array(ACT_Y_BUS_WR) <= '1'; + y_bus_wr_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + end if; + end process; + + adgen_decoder: process(adgen_bittype, instr_word) is + begin + adgen_mode_a <= NOP; + adgen_mode_b <= NOP; + ea_extension_available <= '0'; + + case adgen_bittype is + when SINGLE_X => + case instr_word(13 downto 11) is + when "000" => adgen_mode_a <= POST_MIN_N; + when "001" => adgen_mode_a <= POST_PLUS_N; + when "010" => adgen_mode_a <= POST_MIN_1; + when "011" => adgen_mode_a <= POST_PLUS_1; + when "100" => adgen_mode_a <= NOP; + when "101" => adgen_mode_a <= INDEXED_N; + when "111" => adgen_mode_a <= PRE_MIN_1; + when "110" => + if instr_word(10 downto 8) = "000" then + adgen_mode_a <= ABSOLUTE; + ea_extension_available <= '1'; + elsif instr_word(10 downto 8) = "100" then + adgen_mode_a <= IMMEDIATE; + ea_extension_available <= '1'; + else + adgen_mode_a <= NOP; -- INVALID OPCODE! + end if; + when others => + end case; + when SINGLE_X_SHORT => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= POST_MIN_N; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + when DOUBLE_X_Y => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= NOP; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + case instr_word(21 downto 20) is + when "00" => adgen_mode_b <= NOP; + when "01" => adgen_mode_b <= POST_PLUS_N; + when "10" => adgen_mode_b <= POST_MIN_1; + when "11" => adgen_mode_b <= POST_PLUS_1; + when others => + end case; + when others => + end case; + end process adgen_decoder; + +end architecture rtl; + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd new file mode 100644 index 0000000..c8be35c --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Top entity of DSP +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity dsp56k is port ( + clk, rst : in std_logic; + -- put register file here for synthesis! + register_file : out register_file_type +-- port_a_in : in port_a_in_type; +-- port_a_out : out port_a_out_type; +-- port_b_in : in port_b_in_type; +-- port_b_out : out port_b_out_type; +-- port_c_in : in port_c_in_type; +-- port_c_out : out port_c_out_type; + +); +end dsp56k; + + +architecture rtl of dsp56k is + + component pipeline is port ( + clk, rst : in std_logic; + register_file_out : out register_file_type; + stall_flags_out : out std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : in std_logic; + data_rom_enable: out std_logic; + pmem_ctrl_in : out mem_ctrl_type_in; + pmem_ctrl_out : in mem_ctrl_type_out; + pmem2_ctrl_in : out mem_ctrl_type_in; + pmem2_ctrl_out : in mem_ctrl_type_out; + xmem_ctrl_in : out mem_ctrl_type_in; + xmem_ctrl_out : in mem_ctrl_type_out; + ymem_ctrl_in : out mem_ctrl_type_in; + ymem_ctrl_out : in mem_ctrl_type_out + + ); + end component pipeline; + + component memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + pmem2_ctrl_in : in mem_ctrl_type_in; + pmem2_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out + ); + end component memory_management; + + signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + signal memory_stall : std_logic; + signal data_rom_enable : std_logic; + signal pmem_ctrl_in : mem_ctrl_type_in; + signal pmem_ctrl_out : mem_ctrl_type_out; + signal pmem2_ctrl_in : mem_ctrl_type_in; + signal pmem2_ctrl_out : mem_ctrl_type_out; + signal xmem_ctrl_in : mem_ctrl_type_in; + signal xmem_ctrl_out : mem_ctrl_type_out; + signal ymem_ctrl_in : mem_ctrl_type_in; + signal ymem_ctrl_out : mem_ctrl_type_out; + +begin + + pipeline_inst : pipeline port map( + clk => clk, + rst => rst, + register_file_out => register_file, + stall_flags_out => stall_flags, + memory_stall => memory_stall, + data_rom_enable => data_rom_enable, + pmem_ctrl_in => pmem_ctrl_in, + pmem_ctrl_out => pmem_ctrl_out, + pmem2_ctrl_in => pmem2_ctrl_in, + pmem2_ctrl_out => pmem2_ctrl_out, + xmem_ctrl_in => xmem_ctrl_in, + xmem_ctrl_out => xmem_ctrl_out, + ymem_ctrl_in => ymem_ctrl_in, + ymem_ctrl_out => ymem_ctrl_out + ); + + --------------------- + -- MEMORY MANAGEMENT + --------------------- + MMU_inst: memory_management port map ( + clk => clk, + rst => rst, + stall_flags => stall_flags, + memory_stall => memory_stall, + data_rom_enable => data_rom_enable, + pmem_ctrl_in => pmem_ctrl_in, + pmem_ctrl_out => pmem_ctrl_out, + pmem2_ctrl_in => pmem2_ctrl_in, + pmem2_ctrl_out => pmem2_ctrl_out, + xmem_ctrl_in => xmem_ctrl_in, + xmem_ctrl_out => xmem_ctrl_out, + ymem_ctrl_in => ymem_ctrl_in, + ymem_ctrl_out => ymem_ctrl_out + ); + +end architecture rtl; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd new file mode 100644 index 0000000..249be3c --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd @@ -0,0 +1,611 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief ALU, including shifter, MAC unit, etc. +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + +architecture rtl of exec_stage_alu is + + signal alu_shifter_out : signed(55 downto 0); + signal alu_shifter_carry_out : std_logic; + signal alu_shifter_overflow_out : std_logic; + + signal alu_logic_conj : signed(55 downto 0); + signal alu_multiplier_out : signed(55 downto 0); + signal alu_src_op : signed(55 downto 0); + signal alu_add_result : signed(56 downto 0); + signal alu_add_carry_out : std_logic; + signal alu_post_adder_result : signed(56 downto 0); + + signal scaling_mode : std_logic_vector(1 downto 0); + + signal modified_accu_int : signed(55 downto 0); + + signal norm_instr_asl : std_logic; + signal norm_instr_asr : std_logic; + signal norm_instr_nop : std_logic; + signal norm_update_ccr : std_logic; + +begin + + + -- store calculated value? + modify_accu <= alu_ctrl.store_result; + modified_accu <= modified_accu_int; + -- for the norm instruction we first need to determine whether we have to + -- update the CCR register or not + modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else + norm_update_ccr; + dst_accu <= alu_ctrl.dst_accu; + + scaling_mode <= register_file.sr(11 downto 10); + + + calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out, + alu_post_adder_result, modified_accu_int, alu_add_carry_out) is + begin + -- by default do not modify the flags in the status register + modified_sr <= register_file.sr; + + -- Carry flag generation + ------------------------- + case alu_ctrl.ccr_flags_ctrl(C_FLAG) is + when CLEAR => modified_sr(C_FLAG) <= '0'; + when SET => modified_sr(C_FLAG) <= '1'; + when MODIFY => + -- the carry flag can stem from the shifter or from the post adder + -- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR) + -- take the carry flag from the shifter, else from the post adder + if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and + alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting? + modified_sr(C_FLAG) <= alu_shifter_carry_out; + elsif alu_ctrl.div_instr = '1' then + modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55)); + else +-- modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57)); + modified_sr(C_FLAG) <= alu_add_carry_out; + end if; + when others => -- Don't touch + end case; + + -- Overflow flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(V_FLAG) is + when CLEAR => modified_sr(V_FLAG) <= '0'; + when SET => modified_sr(V_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(V_FLAG) <= '1'; + else + modified_sr(V_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Zero flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is + when CLEAR => modified_sr(Z_FLAG) <= '0'; + when SET => modified_sr(Z_FLAG) <= '1'; + when MODIFY => + -- in case the result is zero set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or + (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto 0) = 0) then + modified_sr(Z_FLAG) <= '1'; + else + modified_sr(Z_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Negative flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(N_FLAG) is + when CLEAR => modified_sr(N_FLAG) <= '0'; + when SET => modified_sr(N_FLAG) <= '1'; + when MODIFY => + -- in case the result is negative set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if alu_ctrl.word_24_update = '1' then + modified_sr(N_FLAG) <= std_logic(modified_accu_int(47)); + else + modified_sr(N_FLAG) <= std_logic(modified_accu_int(55)); + end if; + when others => -- Don't touch + end case; + + -- Unnormalized flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(U_FLAG) is + when CLEAR => modified_sr(U_FLAG) <= '0'; + when SET => modified_sr(U_FLAG) <= '1'; + when MODIFY => + -- Set unnormalized bit according to the scaling mode + if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or + (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or + (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then + modified_sr(U_FLAG) <= '1'; + else + modified_sr(U_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Extension flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(E_FLAG) is + when CLEAR => modified_sr(E_FLAG) <= '0'; + when SET => modified_sr(E_FLAG) <= '1'; + when MODIFY => + -- Set extension flag by default + modified_sr(E_FLAG) <= '1'; + -- Clear extension flag according to the scaling mode + case scaling_mode is + when "00" => + if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "01" => + if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "10" => + if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when others => + modified_sr(E_FLAG) <= '0'; + end case; + when others => -- Don't touch + end case; + + -- Limit flag generation (equals overflow flag generaton!) + -- Clearing of the Limit flag has to be done by the user! + ----------------------------------------------------------- + case alu_ctrl.ccr_flags_ctrl(L_FLAG) is + when CLEAR => modified_sr(L_FLAG) <= '0'; + when SET => modified_sr(L_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(L_FLAG) <= '1'; + end if; + when others => -- Don't touch + end case; + + -- Scaling flag generation (DSP56002 and up) + -------------------------------------------- + -- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB + + end process; + + + src_operand_select: process(register_file, alu_ctrl) is + begin + -- decoding according similar to JJJ representation + case alu_ctrl.add_src_stage_1 is + when "000" => + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.a; + else + alu_src_op <= register_file.b; + end if; + when "001" => -- A,B or B,A + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.b; + else + alu_src_op <= register_file.a; + end if; + when "010" => -- X + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 0) <= register_file.x1 & register_file.x0; + when "011" => -- Y + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 0) <= register_file.y1 & register_file.y0; + when "100" => -- x0 + alu_src_op(55 downto 48) <= (others => register_file.x0(23)); + alu_src_op(47 downto 24) <= register_file.x0; + alu_src_op(23 downto 0) <= (others => '0'); + when "101" => -- y0 + alu_src_op(55 downto 48) <= (others => register_file.y0(23)); + alu_src_op(47 downto 24) <= register_file.y0; + alu_src_op(23 downto 0) <= (others => '0'); + when "110" => -- x1 + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 24) <= register_file.x1; + alu_src_op(23 downto 0) <= (others => '0'); + when "111" => -- y1 + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 24) <= register_file.y1; + alu_src_op(23 downto 0) <= (others => '0'); + when others => + end case; + end process; + + alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is + begin + alu_logic_conj <= alu_shifter_out; + case alu_ctrl.logic_function is + when "110" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24); + when "010" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or alu_src_op(47 downto 24); + when "011" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24); + when "111" => + alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24); + when others => + end case; + end process; + + alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is + variable add_src_op_1 : signed(56 downto 0); + variable add_src_op_2 : signed(56 downto 0); + variable carry_const : signed(56 downto 0); + variable alu_shifter_out_57 : signed(56 downto 0); + variable alu_add_result_58 : signed(57 downto 0); + variable alu_add_result_interm : signed(56 downto 0); + variable invert_carry_flag : std_logic; + begin + + -- by default do not invert the carry + invert_carry_flag := '0'; + + -- determine whether to use multiplier output, the operand defined above, or zeros! + -- resizing is done here already. Like that we can see whether an overflow + -- occurs due to negating the source operand + case alu_ctrl.add_src_stage_2 is + when "00" => add_src_op_1 := (others => '0'); + when "10" => add_src_op_1 := resize(alu_multiplier_out, 57); + when others => add_src_op_1 := resize(alu_src_op, 57); + end case; + + -- determine the sign for the 1st operand! + case alu_ctrl.add_src_sign is + -- normal operation + when "00" => add_src_op_1 := add_src_op_1; + -- negative sign + when "01" => add_src_op_1 := - add_src_op_1; + invert_carry_flag := not invert_carry_flag; + -- change according to sign + -- performs - | accu | for the CMPM instruction + when "10" => + -- we subtract in any case, so invert the carry! + invert_carry_flag := not invert_carry_flag; + if add_src_op_1(55) = '0' then + add_src_op_1 := - add_src_op_1; + else + add_src_op_1 := add_src_op_1; + end if; + -- div instruction! + -- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative + -- add_src_op_1 holds S[23] (sign extension!) + when others => + if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or + (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then + add_src_op_1 := add_src_op_1; + else + add_src_op_1 := - add_src_op_1; +-- invert_carry_flag := not invert_carry_flag; + end if; + end case; + + alu_shifter_out_57 := resize(alu_shifter_out, 57); + + -- determine the sign for the 2nd operand (coming from the shifter)! + case alu_ctrl.shift_src_sign is + -- negative sign + when "01" => + add_src_op_2 := - alu_shifter_out_57; + -- change according to sign + -- this allows to build the magnitude (ABS, CMPM) + when "10" => + if alu_shifter_out(55) = '1' then + add_src_op_2 := - alu_shifter_out_57; + else + add_src_op_2 := alu_shifter_out_57; + end if; + when others => + add_src_op_2 := alu_shifter_out_57; + end case; + + -- determine whether carry flag has to be added or subtracted + if alu_ctrl.rounding_used = "10" then + carry_const := (others => '0'); + -- add carry flag + carry_const(0) := register_file.sr(C_FLAG); + elsif alu_ctrl.rounding_used = "11" then + -- subtract carry flag + carry_const := (others => register_file.sr(0)); -- carry flag + else + carry_const := (others => '0'); + end if; + + -- add the values and calculate the carry bit + alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + + ('0' & add_src_op_2(55 downto 0)) + + ('0' & carry_const(55 downto 0)); + + -- here pops the new carry out of the adder + if invert_carry_flag = '0' then + alu_add_carry_out <= alu_add_result_interm(56); + else + alu_add_carry_out <= not alu_add_result_interm(56); + end if; + + -- calculate the last bit (56), in order to test for overflow later on + alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0); +-- alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56); + alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) + xor carry_const(56) xor alu_add_result_interm(56); + + end process alu_adder; + + + -- Adder after the normal arithmetic adder + -- This adder is responsible for +-- -- 1) carry addition +-- -- 2) carry subtration + -- 3) convergent rounding + alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is + variable post_adder_constant : signed(56 downto 0); + variable testing_constant : signed(24 downto 0); + begin + -- by default add nothing + post_adder_constant := (others => '0'); + + case alu_ctrl.rounding_used is + -- rounding dependant on scaling bits + when "01" => + case scaling_mode is + -- no scaling + when "00" => testing_constant := alu_add_result(23 downto 0) & '0'; + -- scale down + when "01" => testing_constant := alu_add_result(24 downto 0); + -- scale up + when "10" => testing_constant := alu_add_result(22 downto 0) & "00"; + when others => + testing_constant := alu_add_result(23 downto 0) & '0'; + end case; + + -- Special case! + if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then + -- add depending on bit left to the rounding position + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := alu_add_result(24); + -- scale down + when "01" => post_adder_constant(24) := alu_add_result(25); + -- scale up + when "10" => post_adder_constant(22) := alu_add_result(23); + when others => + end case; + else -- testing_constant /= X"1000000" + -- add rounding constant depending on scaling mode + -- results in round up if MSB of testing constant is set, else nothing happens + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := '1'; + -- scale down + when "01" => post_adder_constant(24) := '1'; + -- scale up + when "10" => post_adder_constant(22) := '1'; + when others => + end case; + end if; + -- no rounding + when others => + post_adder_constant := (others => '0'); + + end case; + + -- Add the result of the first adder to the constant (e.g., carry flag) + alu_post_adder_result <= alu_add_result + post_adder_constant; + + -- When rounding is used set 24 LSBs to zero! + if alu_ctrl.rounding_used = "01" then + alu_post_adder_result(23 downto 0) <= (others => '0'); + end if; + end process; + + + + alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is + begin + if alu_ctrl.logic_function /= "000" then + modified_accu_int <= alu_logic_conj; + else + modified_accu_int <= alu_post_adder_result(55 downto 0); + end if; + end process; + + + -- contains the 24*24 bit fractional multiplier + alu_multiplier : process(register_file, alu_ctrl) is + variable src_op1: signed(23 downto 0); + variable src_op2: signed(23 downto 0); + variable mul_result_interm : signed(47 downto 0); + begin + -- select source operands for multiplication + case alu_ctrl.mul_op1 is + when "00" => src_op1 := register_file.x0; + when "01" => src_op1 := register_file.x1; + when "10" => src_op1 := register_file.y0; + when others => src_op1 := register_file.y1; + end case; + case alu_ctrl.mul_op2 is + when "00" => src_op2 := register_file.x0; + when "01" => src_op2 := register_file.x1; + when "10" => src_op2 := register_file.y0; + when others => src_op2 := register_file.y1; + end case; + + -- perform integer multiplication + mul_result_interm := src_op1 * src_op2; + + -- sign extension of result + alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47)); + -- convert from two's complement representation to fractional format + -- signed integer multiplication delivers twice the sign bit, but only one is needed for the + -- fractional multiplication, so remove one and append a zero to the result + alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0'; + + end process alu_multiplier; + + + -- contains the data shifter + alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is + variable src_accu : signed(55 downto 0); + variable shift_to_perform : alu_shift_mode; + begin + -- read source accumulator + if alu_ctrl.shift_src = '0' then + src_accu := register_file.a; + else + src_accu := register_file.b; + end if; + + alu_shifter_carry_out <= '0'; + alu_shifter_overflow_out <= '0'; + + -- NORM instruction determines the shift value just + -- in time, so overwrite the flag from the alu_ctrl + -- for this instruction by the calculated value + if alu_ctrl.norm_instr = '0' then + shift_to_perform := alu_ctrl.shift_mode; + else + if norm_instr_asl = '1' then + shift_to_perform := SHIFT_LEFT; + elsif norm_instr_asr = '1' then + shift_to_perform := SHIFT_RIGHT; + else + shift_to_perform := NO_SHIFT; + end if; + end if; + + case shift_to_perform is + when NO_SHIFT => + alu_shifter_out <= src_accu; + when SHIFT_LEFT => + -- ASL, ADDL, DIV? + if alu_ctrl.word_24_update = '0' then + -- special handling for div instruction required + if alu_ctrl.div_instr = '1' then + alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG); + else + alu_shifter_out <= src_accu(54 downto 0) & '0'; + end if; + alu_shifter_carry_out <= src_accu(55); + -- detect overflow that results from left shifting + -- Needed for ASL, ADDL, DIV instructions + if src_accu(55) /= src_accu(54) then + alu_shifter_overflow_out <= '1'; + end if; + -- LSL/ROL? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(47); + if alu_ctrl.rotate = '0' then -- LSL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0'; + else -- ROL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG); + end if; + end if; + when SHIFT_RIGHT => + -- ASR? + if alu_ctrl.word_24_update = '0' then + alu_shifter_out <= src_accu(55) & src_accu(55 downto 1); + alu_shifter_carry_out <= src_accu(0); + -- LSR/ROR? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(24); + if alu_ctrl.rotate = '0' then -- LSR + alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25); + else -- ROR + alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25); + end if; + end if; + when ZEROS => + alu_shifter_out <= (others => '0'); + end case; + end process alu_shifter; + + + -- Special handling for NORM instruction + -- Determine which case occurs (see User's Manual for more information) + norm_instr_logic: process(register_file, addr_r_in) is + begin + norm_instr_asl <= '0'; + norm_instr_asr <= '0'; + + -- Either left shift + if register_file.sr(E_FLAG) = '0' and + register_file.sr(U_FLAG) = '1' and + register_file.sr(Z_FLAG) = '0' then + norm_instr_asl <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in - 1; + -- Or right shift + elsif register_file.sr(E_FLAG) = '1' then + norm_instr_asr <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in + 1; + -- Or do nothing! + else + norm_update_ccr <= '0'; + addr_r_out <= addr_r_in; + end if; + end process; + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd new file mode 100644 index 0000000..0bd69cd --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd @@ -0,0 +1,86 @@ +----------------------------------------------------------------------------- +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Bit modify (BCLR, BSET, J(S)CLR, J(S)SET) +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_bit_modify is + + signal operand_bit : std_logic; + signal src_operand_32 : std_logic_vector(31 downto 0); + +begin + + -- this is just a helper signal to prevent the simulator + -- to stop when accessing a bit > 23. + src_operand_32 <= "00000000" & src_operand; + -- read the bit we want to test (and modify) + operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0)))); + + -- modify the Carry flag only for the bit modify instructions! + modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0'; + modified_sr <= register_file.sr(15 downto 1) & operand_bit; + + bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is + variable new_bit : std_logic; + begin + -- do nothing by default! + dst_operand <= src_operand; + bit_cond_met <= '0'; + + -- determine which bit to write + if instr_array = INSTR_BCLR then + new_bit := '0'; + elsif instr_array = INSTR_BSET then + new_bit := '1'; + else -- BCHG + new_bit := not operand_bit; + end if; + + if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then + dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit; + end if; + + + -- check for the jump instructions whether condition is met or not! + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then + if operand_bit = '0' then + bit_cond_met <= '1'; + else + bit_cond_met <= '0'; + end if; + end if; + if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + if operand_bit = '0' then + bit_cond_met <= '0'; + else + bit_cond_met <= '1'; + end if; + end if; + + end process; + + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd new file mode 100644 index 0000000..f59cc09 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd @@ -0,0 +1,124 @@ +----------------------------------------------------------------------------- +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Branch control +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_branch is + + signal branch_condition_met : std_logic; + signal modify_pc_int : std_logic; + +begin + + modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0'; + modify_pc <= modify_pc_int; + + calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met) + begin + branch_condition_met <= '0'; + + -- unconditional jumps + if instr_array = INSTR_JMP or + instr_array = INSTR_JSR or + instr_array = INSTR_RTI or + instr_array = INSTR_RTS then + -- jump always + branch_condition_met <= '1'; + end if; + -- then see whether the branch condition is satisfied + if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then + branch_condition_met <= cc_flag_set; + end if; + -- jmp that is executed according to a certain bit condition + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or + instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + branch_condition_met <= bit_cond_met; + end if; + end process calculate_branch_condition; + + + calculate_branch_target : process(instr_array, instr_word, jump_address) + begin + modified_pc <= jump_address; + + -- address calculation is the same for the following instructions + if instr_array = INSTR_JMP or + instr_array = INSTR_JCC or + instr_array = INSTR_JSCC or + instr_array = INSTR_JSR then + if instr_word(18) = '1' then + -- short jump address included in opcode (bits 11 downto 0) + modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0)); + elsif instr_word(18) = '0' then + -- effective address defined by opcode and coming from address generator unit + modified_pc <= jump_address; + end if; + end if; + + -- jump address contains the obligatory address of the second + -- instruction word + if instr_array = INSTR_JCLR or + instr_array = INSTR_JSET or + instr_array = INSTR_JSCLR or + instr_array = INSTR_JSSET then + modified_pc <= jump_address; + end if; + + -- target address is stored on the stack + if instr_array = INSTR_RTS or + instr_array = INSTR_RTI then + modified_pc <= unsigned(register_file.current_ssh); + end if; + end process calculate_branch_target; + + -- Subroutine functions need to store PC and SR on the stack + push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC or instr_array = INSTR_JSR or + instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0'; + push_stack.content <= PC_AND_SR; + -- pc is set externally! + push_stack.pc <= (others => '0'); + + -- RTI/RTS instructions need to read from the stack + pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0'; + + -- some instructions require to set the SR + calculate_status_register : process(instr_array) + begin + modify_sr <= '0'; + modified_sr <= (others => '0'); + if instr_array = INSTR_RTI then + modify_sr <= '1'; + modified_sr <= register_file.current_ssl; + end if; + end process calculate_status_register; + + +end architecture rtl; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd new file mode 100644 index 0000000..2f69230 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd @@ -0,0 +1,82 @@ +----------------------------------------------------------------------------- +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Calculate whether cc flag condition is true +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic +); +end entity; + + +architecture rtl of exec_stage_cc_flag_calc is + + +begin + + calculate_cc_flag : process(instr_word, instr_array, register_file) + + variable cc_select : std_logic_vector(3 downto 0); + + procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is + variable c_flag : std_logic := register_file.ccr(0); + variable v_flag : std_logic := register_file.ccr(1); + variable z_flag : std_logic := register_file.ccr(2); + variable n_flag : std_logic := register_file.ccr(3); + variable u_flag : std_logic := register_file.ccr(4); + variable e_flag : std_logic := register_file.ccr(5); + variable l_flag : std_logic := register_file.ccr(6); + + begin + if (cc = "0000" and c_flag = '0') or -- CC: carry clear + (cc = "1000" and c_flag = '1') or -- CS: carry set + (cc = "0101" and e_flag = '0') or -- EC: extension clear + (cc = "1010" and z_flag = '1') or -- EQ: equal + (cc = "1101" and e_flag = '1') or -- ES: extension set + (cc = "0001" and (n_flag = v_flag)) or -- GE: greater than or equal + (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0') or -- GT: greater than + (cc = "0110" and l_flag = '0') or -- LC: limit clear + (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1') or -- LE: less or equal + (cc = "1110" and l_flag = '1') or -- LS: limit set + (cc = "1001" and (n_flag /= v_flag)) or -- LT: less than + (cc = "1011" and n_flag = '1') or -- MI: minus + (cc = "0010" and z_flag = '0') or -- NE: not equal + (cc = "1100" and (( not u_flag and not e_flag) or z_flag) = '1') or -- NR: normalized + (cc = "0011" and n_flag = '0') or -- PL: plus + (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0') -- NN: not normalized + then + cc_flag_set <= '1'; + end if; + end procedure; + + begin + + cc_flag_set <= '0'; + + -- Rip the flags we have to test for from the instruction word + if (instr_array = INSTR_JCC and instr_word(18) = '0') or + (instr_array = INSTR_JSCC) then + cc_select := instr_word(3 downto 0); + else + cc_select := instr_word(15 downto 12); + end if; + + calculate_cc_flag(cc_select); + + end process; + + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd new file mode 100644 index 0000000..2465125 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd @@ -0,0 +1,79 @@ +----------------------------------------------------------------------------- +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cr_mod is port ( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) +); +end exec_stage_cr_mod; + + +architecture rtl of exec_stage_cr_mod is + +begin + + process(activate_exec_cr_mod, instr_word, instr_array, register_file) is + variable imm8 : std_logic_vector(7 downto 0); + variable op8 : std_logic_vector(7 downto 0); + variable res8 : std_logic_vector(7 downto 0); + begin + modify_sr <= '0'; + modify_omr <= '0'; + modified_sr <= (others => '0'); + modified_omr <= (others => '0'); + + imm8 := instr_word(15 downto 8); + if instr_word(1 downto 0) = "00" then + -- read MR + op8 := register_file.mr; + elsif instr_word(1 downto 0) = "01" then + -- read CCR + op8 := register_file.ccr; + else -- instr_word(1 downto 0) = "10" + -- read OMR + op8 := register_file.omr; + end if; + + if instr_array = INSTR_ANDI then + res8 := imm8 and op8; + else -- instr_array = INSTR_ORI + res8 := imm8 or op8; + end if; + + -- only write the result when activated + if activate_exec_cr_mod = '1' then + if instr_word(1 downto 0) = "00" then + -- update MR + modify_sr <= '1'; + modified_sr <= res8 & register_file.ccr; + elsif instr_word(1 downto 0) = "01" then + -- update CCR + modify_sr <= '1'; + modified_sr <= register_file.mr & res8; + elsif instr_word(1 downto 0) = "10" then + -- update OMR + modify_omr <= '1'; + modified_omr <= res8; + end if; + end if; + end process; + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd new file mode 100644 index 0000000..3472636 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd @@ -0,0 +1,207 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Loop control (REP, DO, ENDDO) +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_loop is + + signal rep_loop_polling : std_logic; + signal do_loop_polling : std_logic; + signal enddo_polling : std_logic; + signal lc_temp : unsigned(15 downto 0); + signal rf_lc_eq_1 : std_logic; + signal memory_stall_t : std_logic; + +begin + + modified_pc <= loop_start_address; + + + -- loop counter in register file equal to 1? + rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0'; + + process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo, + rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is + begin + stall_rep <= '0'; + stall_do <= '0'; + + modify_la <= '0'; + modify_lc <= '0'; + modify_pc <= '0'; + modify_sr <= '0'; + modified_la <= loop_address; + modified_lc <= loop_iterations; -- default + -- set the loop flag LF (bit 15) of Status register + modified_sr(15) <= '1'; + modified_sr(14 downto 0) <= register_file.sr(14 downto 0); + + push_stack.valid <= '0'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= LA_AND_LC; + + pop_stack.valid <= '0'; + decrement_lc <= '0'; + ------------------ + -- DO instruction + ------------------ + if activate_exec_loop = '1' and instr_array = INSTR_DO then + -- first instruction of the do loop instruction? + if do_loop_polling = '0' then + stall_do <= '1'; + modify_lc <= '1'; -- store the new loop counter + modify_la <= '1'; -- store the new loop address + push_stack.valid <= '1'; -- push LA and LC on the stack + push_stack.content <= LA_AND_LC; + else -- second clock cycle of the do loop instruction ? + push_stack.valid <= '1'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= PC_AND_SR; + -- set the PC to the first instruction of the loop + -- the already fetched instruction are flushed from the pipeline + -- this prevents problems, when the loop consists of only one or two instructions + modify_pc <= '1'; + -- set the loop flag + modify_sr <= '1'; + end if; + end if; + ----------------------------------------------- + -- ENDDO instruction / loop end in fetch stage + ----------------------------------------------- + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then + pop_stack.valid <= '1'; + if enddo_polling = '0' then + -- only restore the LF from the stack + modified_sr(15) <= register_file.current_ssl(15); + modify_sr <= '1'; + stall_do <= '1'; -- stall one clock cycle + else + -- restore loop counter and loop address in second clock cycle + modified_lc <= unsigned(register_file.current_ssl); + modify_lc <= '1'; + modified_la <= unsigned(register_file.current_ssh); + modify_la <= '1'; + end if; + end if; + ------------------- + -- REP instruction + ------------------- + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + stall_rep <= '1'; -- stall the fetch and decode stages + modify_lc <= '1'; -- store the loop counter + modified_lc <= loop_iterations - 1; + end if; + end if; + + -- keep processing the single instruction + if rep_loop_polling = '1' then + stall_rep <= '1'; + -- if the REP instruction caused a stall do not modify the lc! + if memory_stall_t = '0' then + if rf_lc_eq_1 = '0' then + decrement_lc <= '1'; + -- when the instruction to repeat caused a memory stall + -- do not continue! + else + -- finish the REP instruction by restoring the LC + stall_rep <= '0'; + modify_lc <= '1'; + modified_lc <= lc_temp; + end if; + end if; + end if; + end process; + + + -- process that allows to remember that we are processing a REP/DO instruction + -- even though the REP instruction is not available in the pipeline anymore + -- also store the old loop counter + process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + rep_loop_polling <= '0'; + do_loop_polling <= '0'; + enddo_polling <= '0'; + lc_temp <= (others => '0'); + memory_stall_t <= '0'; + else + memory_stall_t <= memory_stall; + + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + rep_loop_polling <= '1'; + lc_temp <= register_file.lc; + end if; + end if; + -- test whether the REP instruction has been executed + if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0' then + rep_loop_polling <= '0'; + end if; + + -- do loop execution takes two clock cycles + -- in the first clock cycle we store loop address and loop counter on the stack + -- in the second clock cycle we store programm counter and status register on the stack + if activate_exec_loop = '1' and instr_array = INSTR_DO then + do_loop_polling <= '1'; + end if; + -- clear the flag immediately again (only two cycles execution time!) + if do_loop_polling = '1' then + do_loop_polling <= '0'; + end if; + + -- ENDDO instructions take two clock cycles as well! + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then + enddo_polling <= '1'; + end if; + if enddo_polling = '1' then + enddo_polling <= '0'; + end if; + end if; + end if; + end process; + +end architecture; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd new file mode 100644 index 0000000..0848bf8 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd @@ -0,0 +1,67 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Fetching from program memory +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +entity fetch_stage is port( + + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + +); +end fetch_stage; + + +architecture rtl of fetch_stage is + + +begin + + pc_calculation: process(pc_old, modify_pc, modified_pc, register_file) is + begin + decrement_lc <= '0'; + perform_enddo <= '0'; + + -- by default increment pc by one + pc_new <= pc_old + 1; + if modify_pc = '1' then + pc_new <= modified_pc; + end if; + -- Loop Flag set? + if register_file.sr(15) = '1' then + if register_file.la = pc_old then + -- Loop not finished? + -- => start from the beginning if necessary + if register_file.lc /= 1 then + -- if the last address was LA and the loop is not finished yet, we have to + -- read now from the beginning of the loop again + pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0)); + -- decrement loop counter + decrement_lc <= '1'; + else + -- loop done! + -- => tell the loop controller in the exec stage to perform the enddo operation + -- (without flushing of the pipeline!) + perform_enddo <= '1'; + end if; + end if; + end if; + end process pc_calculation; + +end architecture rtl; + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd new file mode 100644 index 0000000..02c70eb --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd @@ -0,0 +1,1543 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Internal DSP RAM +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + +entity mem_control is + generic( + mem_type : memory_type := P_MEM + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); +end entity mem_control; + + +architecture rtl of mem_control is + + signal int_mem_rd_addr : std_logic_vector(7 downto 0); + type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0); + signal int_mem : int_mem_type; + signal int_pmem : int_mem_type := ( +-- AGU testing +X"390100", +X"310A00", +X"000000", +X"204900", +X"050FA1", +X"060AA0", +X"204900", +X"390A00", +X"060AA0", +X"204900", +X"000000", +X"000000", +X"000000", +X"000000", +-- AGU testing + +-- ABS begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200026", +--X"56F400", +--X"E00000", +--X"200026", +--X"56F400", +--X"000000", +--X"200026", +--X"52F400", +--X"000080", +--X"200026", +-- ABS end + +-- ADC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200039", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200039", +-- ADC end + +-- ADD begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200038", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200038", +-- ADD end + +-- ADDL begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20001A", +--X"56F400", +--X"0000AA", +--X"20001A", +--X"53F400", +--X"000080", +--X"20001A", +-- ADDL end + +-- ADDR begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20000A", +--X"56F400", +--X"0000AA", +--X"20000A", +--X"53F400", +--X"000080", +--X"20000A", +-- ADDR end + +-- AND begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"FFF000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +-- AND end + +-- EOR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005B", +--X"46F400", +--X"FFFFFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005B", +-- EOR end + +-- OR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005A", +--X"46F400", +--X"000000", +--X"57F400", +--X"000000", +--X"0000B9", +--X"20005A", +-- OR end + +-- NOT begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"7F00FF", +--X"0000B9", +--X"20001F", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20001F", +-- NOT end + +-- ASL begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20003A", +-- ASL end + +-- ASR begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20002A", +-- ASR end + +-- CLR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200013", +--X"56F400", +--X"E00000", +--X"0000B9", +--X"0001F9", +--X"200013", +-- CLR end + +-- CMP begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005D", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005D", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005D", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005D", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005D", +-- CMP end + +-- CMPM begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005F", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005F", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005F", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005F", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005F", +-- CMPM end + +-- DIV begin +--X"00FEB9", +--X"44F400", +--X"600000", +--X"56F400", +--X"200000", +--X"0618A0", +--X"018040", +--X"210E00", +-- DIV end + +-- LSL begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200033", +-- LSL end + +-- LSR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200023", +-- LSR end + +-- MPY begin +--X"0000B9", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D0", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D4", +-- MPY end + +-- MAC begin +--X"0000B9", +--X"200013", +--X"2A8000", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D6", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D6", +-- MAC end + +-- MACR begin +--X"0000B9", +--X"200013", +--X"2E1000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"56F400", +--X"100001", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"2E1000", +--X"50F400", +--X"800000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +-- MACR end + +-- MPYR begin +--X"0000B9", +--X"46F400", +--X"654321", +--X"200095", +-- MPYR end + +-- NEG begin +--X"0000B9", +--X"56F400", +--X"654321", +--X"200036", +--X"200013", +--X"52F400", +--X"000080", +--X"200036", +--X"56F400", +--X"800000", +--X"200036", +-- NEG end + +-- NORM begin +--X"200013", +--X"2C0100", +--X"200003", +--X"062FA0", +--X"01DB15", +--X"200013", +--X"2EFF00", +--X"2A8400", +--X"200003", +--X"062FA0", +--X"01D915", +--X"200013", +--X"062FA0", +--X"01DA15", +-- NORM end + +-- RND begin +--X"0000B9", +--X"54F400", +--X"123456", +--X"50F400", +--X"789ABC", +--X"200011", +--X"54F400", +--X"123456", +--X"50F400", +--X"800000", +--X"200011", +--X"54F400", +--X"123455", +--X"50F400", +--X"800000", +--X"200011", +-- RND end + +-- ROR begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200027", +-- ROR end + +-- ROL begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200037", +-- ROL end + + +-- SUB begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003C", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003C", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20007C", +-- SUB end + +-- SUBL begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20001E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20001E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20001E", +-- SUBL end + +-- SUBR begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20000E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20000E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20000E", +-- SUBR end + +-- SBC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003D", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003D", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20003D", +-- SBC end + +-- TCC begin +--X"311400", +--X"44F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"0000B9", +--X"038143", +--X"03014A", +--X"0004F9", +--X"03A143", +--X"03214A", +-- TCC end + +-- TFR begin +--X"56F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"21EE09", +--X"44F400", +--X"555555", +--X"47F400", +--X"AAAAAA", +--X"21C441", +--X"21E679", +-- TFR end + +-- TST begin +--X"20001B", +--X"20000B", +--X"0000B9", +--X"0001F9", +--X"53F400", +--X"000080", +--X"20000B", +--X"53F400", +--X"00007F", +--X"20000B", +-- TST end + + +--X"2AFF00", +--X"54F400", +--X"FFFFFF", +--X"50F400", +--X"FFFFF2", +--X"200026", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +--X"44F400", +--X"100010", +--X"45F400", +--X"100011", +--X"0B5880", +--X"000017", +--X"46F400", +--X"100026", +--X"47F400", +--X"100027", +--X"425800", +--X"435800", +--X"420A00", +--X"431F00", +--X"437000", +--X"0000A0", +--X"427000", +--X"00004F", +-- X"42F800", +-- X"43F800", +-- X"428A00", +-- X"439F00", +-- "001100000100100000000000", -- 0 move #72,r0 +-- "001110000000100000000000", -- 1 move #8,n0 +-- "000001010000000010100000", -- 2 move #0,m0 +-- "000001010001000010100001", -- 3 move #16,m1 +-- "000001101110000100100000", -- 4 rep m1 +-- "010001001100100000000000", -- 5 move x:(r0)+n0,x0 +-- "000000000000000000000000", -- 6 +-- "000000000000000000000000", -- 7 +-- "000000000000000000000000", -- 8 +-- "000000000000000000000000", -- 9 +-- "000000000000000000000000", -- 10 +-- "000000000000000000000000", -- 11 +-- "000000000000000000000000", -- 12 +-- "000000000000000000000000", -- 13 +-- "000000000000000000000000", -- 14 +-- "000000000000000000000000", -- 15 +-- "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 +-- "000000000000000000000000", -- 18 +-- "000000000000000000000000", -- 19 +-- "000010101101101010000000", -- 20 -- JMP (r2)+ +-- "000000000000000000000000", -- 20 +-- "000000000000000000000000", -- 21 +-- "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_xmem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000001100", -- 0 -- REP + "000000000000000000000101", -- 1 -- ORI #$0E, MR + "000000000000111011111010", -- 2 -- ORI #$0E, OMR + "000000000000100010111010", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000000", -- 4 + "000000000000000000000000", -- 5 + "000000000000000000000000", -- 6 + "000000000000000000000000", -- 7 + "000000000000000000000000", -- 8 + "000000000000000000000000", -- 9 + "000000000000000000000000", -- 10 + "000000000000000000000000", -- 11 + "000000000000000000000000", -- 12 + "000000000000000000000000", -- 13 + "000000000000000000000000", -- 14 + "000000000000000000000000", -- 15 + "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_ymem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000000001", -- 0 -- REP + "000000000000000000000010", -- 1 -- ORI #$0E, MR + "000000000000000000000011", -- 2 -- ORI #$0E, OMR + "000000000000000000000100", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000101", -- 4 + "000000000000000000000110", -- 5 + "000000000000000000000111", -- 6 + "000000000000000000001000", -- 7 + "000000000000000000001001", -- 8 + "000000000000000000001010", -- 9 + "000000000000000000001011", -- 10 + "000000000000000000001100", -- 11 + "000000000000000000001101", -- 12 + "000000000000000000001110", -- 13 + "000000000000000000001111", -- 14 + "000000000000000000010000", -- 15 + "000000000000000000010001", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + +begin + +-- int_mem <= int_pmem when mem_type = P_MEM else +-- int_xmem when mem_type = X_MEM else +-- int_ymem when mem_type = Y_MEM; + + wr_accomplished <= wr_en; + + PMEM_GEN: if mem_type = P_MEM generate + data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_pmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + XMEM_GEN: if mem_type = X_MEM generate + data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_xmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + YMEM_GEN: if mem_type = Y_MEM generate + data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_ymem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; +-- process(clk, rst) is +-- begin +-- if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else +-- int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); +-- data_out_valid <= rd_en; +-- if wr_en = '1' then +-- if mem_type = P_MEM then +-- int_pmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = X_MEM then +-- int_xmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = Y_MEM then +-- int_ymem(to_integer(wr_addr)) <= data_in; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; + +end architecture rtl; + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd new file mode 100644 index 0000000..215fe66 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd @@ -0,0 +1,223 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Memory controller +--! +--! @details This entity contains the internal memories. These are: +--! - pmem +--! - xmem +--! - ymem +--! - ROM tables +--! - Bootup code +--! All memory requests are collected here. Only when they are all finished +--! the memory_stall-flag is released. External memory accesses are given to +--! the external interface. +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + pmem2_ctrl_in : in mem_ctrl_type_in; + pmem2_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out +); +end memory_management; + + +architecture rtl of memory_management is + + component mem_control is + generic( + mem_type : memory_type + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); + end component mem_control; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + + signal pmem_rd_addr : unsigned(BW_ADDRESS-1 downto 0); + signal pmem_rd_en : std_logic; + + signal xmem_rd_en : std_logic; + signal xmem_data_out : std_logic_vector(23 downto 0); + signal xmem_data_out_valid : std_logic; + signal xmem_rd_polling : std_logic; + + signal ymem_rd_en : std_logic; + signal ymem_data_out : std_logic_vector(23 downto 0); + signal ymem_data_out_valid : std_logic; + signal ymem_rd_polling : std_logic; + + signal pmem_stall_buffer : std_logic_vector(23 downto 0); + signal pmem_stall_buffer_valid : std_logic; + signal xmem_stall_buffer : std_logic_vector(23 downto 0); + signal ymem_stall_buffer : std_logic_vector(23 downto 0); + + signal stall_flags_d : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + +begin + + -- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall + -- when the pipeline wakes up, this temporal result is inserted into the pipeline + stall_buffer: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + pmem_stall_buffer <= (others => '0'); + pmem_stall_buffer_valid <= '0'; + xmem_stall_buffer <= (others => '0'); + ymem_stall_buffer <= (others => '0'); + stall_flags_d <= (others => '0'); + else + stall_flags_d <= stall_flags; + if stall_flags(ST_FE2_DEC) = '1' and stall_flags_d(ST_FE2_DEC) = '0' then + if pmem_data_out_valid = '1' then + pmem_stall_buffer <= pmem_data_out; + pmem_stall_buffer_valid <= '1'; + end if; + end if; + if stall_flags(ST_FE2_DEC) = '0' and stall_flags_d(ST_FE2_DEC) = '1' then + pmem_stall_buffer_valid <= '0'; + end if; + + end if; + end if; + end process stall_buffer; + + memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or + ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else + '0'; + + ------------------------------- + -- PMEM CONTROLLER + ------------------------------- + inst_pmem_ctrl : mem_control + generic map( + mem_type => P_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => pmem_ctrl_in.rd_addr, + rd_en => pmem_ctrl_in.rd_en, + data_out => pmem_data_out, + data_out_valid => pmem_data_out_valid, + wr_addr => pmem_ctrl_in.wr_addr, + wr_en => pmem_ctrl_in.wr_en, + data_in => pmem_ctrl_in.data_in + ); + + -- In case we wake up from a stall use the buffered value + pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FE2_DEC) = '0' and + stall_flags_d(ST_FE2_DEC) = '1' and + pmem_stall_buffer_valid = '1' else + pmem_data_out; + + pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FE2_DEC) = '0' and + stall_flags_d(ST_FE2_DEC) = '1' else + '0' when stall_flags(ST_FE2_DEC) = '1' else + pmem_data_out_valid; + + ------------------------------- + -- XMEM CONTROLLER + ------------------------------- + inst_xmem_ctrl : mem_control + generic map( + mem_type => X_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => xmem_ctrl_in.rd_addr, + rd_en => xmem_rd_en, + data_out => xmem_data_out, + data_out_valid => xmem_data_out_valid, + wr_addr => xmem_ctrl_in.wr_addr, + wr_en => xmem_ctrl_in.wr_en, + data_in => xmem_ctrl_in.data_in + ); + + xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0'; + + xmem_ctrl_out.data_out <= xmem_data_out; + xmem_ctrl_out.data_out_valid <= xmem_data_out_valid; + + ------------------------------- + -- YMEM CONTROLLER + ------------------------------- + inst_ymem_ctrl : mem_control + generic map( + mem_type => Y_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => ymem_ctrl_in.rd_addr, + rd_en => ymem_rd_en, + data_out => ymem_data_out, + data_out_valid => ymem_data_out_valid, + wr_addr => ymem_ctrl_in.wr_addr, + wr_en => ymem_ctrl_in.wr_en, + data_in => ymem_ctrl_in.data_in + ); + + ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0'; + + ymem_ctrl_out.data_out <= ymem_data_out; + ymem_ctrl_out.data_out_valid <= ymem_data_out_valid; + + mem_stall_control: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + xmem_rd_polling <= '0'; + ymem_rd_polling <= '0'; + else + if xmem_rd_en = '1' then + xmem_rd_polling <= '1'; + end if; + + if xmem_data_out_valid = '1' then + xmem_rd_polling <= '0'; + end if; + + if ymem_rd_en = '1' then + ymem_rd_polling <= '1'; + end if; + + if ymem_data_out_valid = '1' then + ymem_rd_polling <= '0'; + end if; + + end if; + end if; + end process; +end architecture; + diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd new file mode 100644 index 0000000..f06c000 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Global parameters +--! +------------------------------------------------------------------------------ + +package parameter_pkg is + + constant BW_ADDRESS : natural := 16; + + -- number of pipeline register stages + constant PIPELINE_DEPTH : natural := 4; + + constant NUM_ACT_SIGNALS : natural := 26; + +end package; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd new file mode 100644 index 0000000..f00db65 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd @@ -0,0 +1,1007 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief DSP 56k pipeline +--! +--! @details This is the computational part of the DSP core. The pipeline +--! consists of five stages: +--! - FE : Initiate read access to program memory +--! - FE2: Retrieve data from program memory +--! - DEC: Instruction decode +--! - ADG: Address generation units - also inits of xmem, ymem, and pmem reads +--! - EX : Execute stage, contains ALU, loop controls, writes to xmem, ymem, +--! pmem +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity pipeline is port ( + clk, rst : in std_logic; + register_file_out : out register_file_type; + stall_flags_out : out std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : in std_logic; + data_rom_enable: out std_logic; + pmem_ctrl_in : out mem_ctrl_type_in; + pmem_ctrl_out : in mem_ctrl_type_out; + pmem2_ctrl_in : out mem_ctrl_type_in; + pmem2_ctrl_out : in mem_ctrl_type_out; + xmem_ctrl_in : out mem_ctrl_type_in; + xmem_ctrl_out : in mem_ctrl_type_out; + ymem_ctrl_in : out mem_ctrl_type_in; + ymem_ctrl_out : in mem_ctrl_type_out + +); +end pipeline; + +-- TODOs: +-- External memory accesses +-- ROM tables +-- Reading from SSH flag has to modify stack pointer +-- Memory access (x,y,p) and stalling accordingly + +-- List of known BUGS: +-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!! +-- - SBC instruction has errorneous carry flag calculation + +-- List of probable issues: +-- - Reading from XMEM/YMEM with stalls probably results in corrupted data +-- - ENDDO instruction probably has to flush the pipeline afterwards +-- - Writing to memory occurs twice, when stalls occur + +-- Things to optimize: +-- - RTS/RTI could be executed in the ADGEN Stage already +-- - DO loops always flush the pipeline. This is necessary in case we have a very short loop. +-- The single instruction of the loop then has passed the fetch stage already without the branch + + +architecture rtl of pipeline is + + signal pipeline_regs : pipeline_type; + signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + + component fetch_stage is port( + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + ); + end component fetch_stage; + + signal pc_old, pc_new : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_modify_pc : std_logic; + signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_perform_enddo: std_logic; + signal fetch_decrement_lc: std_logic; + + + component decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type + ); + end component decode_stage; + + signal dec_activate : std_logic; + signal dec_instr_word : std_logic_vector(23 downto 0); + signal dec_dble_word_instr : std_logic; + signal dec_instr_array : instructions_type; + signal dec_act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + signal dec_reg_wr_addr : std_logic_vector(5 downto 0); + signal dec_reg_rd_addr : std_logic_vector(5 downto 0); + signal dec_x_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_x_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_l_bus_addr : std_logic_vector(2 downto 0); + signal dec_adgen_mode_a : adgen_mode_type; + signal dec_adgen_mode_b : adgen_mode_type; + signal dec_alu_ctrl : alu_ctrl_type; + + component adgen_stage is port( + activate_adgen : in std_logic; + activate_x_mem : in std_logic; + activate_y_mem : in std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type + ); + end component adgen_stage; + + signal adgen_activate : std_logic; + signal adgen_activate_x_mem : std_logic; + signal adgen_activate_y_mem : std_logic; + signal adgen_activate_l_mem : std_logic; + signal adgen_instr_word : std_logic_vector(23 downto 0); + signal adgen_instr_array : instructions_type; + signal adgen_optional_ea_word : std_logic_vector(23 downto 0); + signal adgen_register_file : register_file_type; + signal adgen_mode_a : adgen_mode_type; + signal adgen_mode_b : adgen_mode_type; + signal adgen_address_out_x : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_address_out_y : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_wr_R_port_A_valid : std_logic; + signal adgen_wr_R_port_A : addr_wr_port_type; + signal adgen_wr_R_port_B_valid : std_logic; + signal adgen_wr_R_port_B : addr_wr_port_type; + + component exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_bit_modify; + + signal exec_bit_modify_instr_word : std_logic_vector(23 downto 0); + signal exec_bit_modify_instr_array : instructions_type; + signal exec_bit_modify_src_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_dst_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_bit_cond_met : std_logic; + signal exec_bit_modify_modify_sr : std_logic; + signal exec_bit_modify_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_branch; + + signal exec_bra_activate : std_logic; + signal exec_bra_instr_word : std_logic_vector(23 downto 0); + signal exec_bra_instr_array : instructions_type; + signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_bit_cond_met : std_logic; + signal exec_bra_push_stack : push_stack_type; + signal exec_bra_pop_stack : pop_stack_type; + signal exec_bra_modify_pc : std_logic; + signal exec_bra_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_modify_sr : std_logic; + signal exec_bra_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_cr_mod is port( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) + ); + end component exec_stage_cr_mod; + + signal exec_cr_mod_activate : std_logic; + signal exec_cr_mod_instr_word : std_logic_vector(23 downto 0); + signal exec_cr_mod_instr_array : instructions_type; + signal exec_cr_mod_modify_sr : std_logic; + signal exec_cr_mod_modified_sr : std_logic_vector(15 downto 0); + signal exec_cr_mod_modify_omr : std_logic; + signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0); + + component exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_loop; + + signal exec_loop_activate : std_logic; + signal exec_loop_instr_word : std_logic_vector(23 downto 0); + signal exec_loop_instr_array : instructions_type; + signal exec_loop_iterations : unsigned(15 downto 0); + signal exec_loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_register_file : register_file_type; + signal exec_loop_push_stack : push_stack_type; + signal exec_loop_pop_stack : pop_stack_type; + signal exec_loop_stall_rep : std_logic; + signal exec_loop_stall_do : std_logic; + signal exec_loop_decrement_lc : std_logic; + signal exec_loop_modify_lc : std_logic; + signal exec_loop_modified_lc : unsigned(15 downto 0); + signal exec_loop_modify_la : std_logic; + signal exec_loop_modified_la : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_pc : std_logic; + signal exec_loop_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_sr : std_logic; + signal exec_loop_modified_sr : std_logic_vector(BW_ADDRESS-1 downto 0); + + component exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_alu; + + signal exec_alu_activate : std_logic; + signal exec_alu_instr_word : std_logic_vector(23 downto 0); + signal exec_alu_ctrl : alu_ctrl_type; + signal exec_alu_addr_r_in : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_addr_r_out : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_modify_accu : std_logic; + signal exec_alu_dst_accu : std_logic; + signal exec_alu_modified_accu : signed(55 downto 0); + signal exec_alu_modify_sr : std_logic; + signal exec_alu_modified_sr : std_logic_vector(15 downto 0); + + signal exec_imm_8bit : std_logic_vector(23 downto 0); + signal exec_imm_12bit : std_logic_vector(23 downto 0); + signal exec_src_operand : std_logic_vector(23 downto 0); + signal exec_dst_operand : std_logic_vector(23 downto 0); + + component exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic + ); + end component exec_stage_cc_flag_calc; + + signal exec_cc_flag_calc_instr_word : std_logic_vector(23 downto 0); + signal exec_cc_flag_calc_instr_array : instructions_type; + signal exec_cc_flag_set : std_logic; + + component reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + dec_lc : in std_logic; + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) + ); + end component reg_file; + + signal register_file : register_file_type; + signal rf_wr_R_port_A_valid : std_logic; + signal rf_wr_R_port_B_valid : std_logic; + signal rf_reg_wr_addr : std_logic_vector(5 downto 0); + signal rf_reg_wr_addr_valid : std_logic; + signal rf_reg_wr_data : std_logic_vector(23 downto 0); + signal rf_reg_rd_addr : std_logic_vector(5 downto 0); + signal rf_reg_rd_data : std_logic_vector(23 downto 0); + signal rf_X_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_data_out : std_logic_vector(23 downto 0); + signal rf_X_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_wr_valid : std_logic; + signal rf_X_bus_data_in : std_logic_vector(23 downto 0); + signal rf_Y_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_data_out : std_logic_vector(23 downto 0); + signal rf_Y_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_wr_valid : std_logic; + signal rf_Y_bus_data_in : std_logic_vector(23 downto 0); + signal rf_L_bus_rd_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_rd_valid : std_logic; + signal rf_L_bus_wr_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_wr_valid : std_logic; + signal push_stack : push_stack_type; + signal pop_stack : pop_stack_type; + signal rf_set_sr : std_logic; + signal rf_new_sr : std_logic_vector(15 downto 0); + signal rf_set_omr : std_logic; + signal rf_new_omr : std_logic_vector(7 downto 0); + signal rf_dec_lc : std_logic; + signal rf_set_lc : std_logic; + signal rf_new_lc : unsigned(15 downto 0); + signal rf_set_la : std_logic; + signal rf_new_la : unsigned(BW_ADDRESS-1 downto 0); + signal rf_alu_wr_valid : std_logic; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + signal pmem2_data_out : std_logic_vector(23 downto 0); + signal pmem2_data_out_valid : std_logic; + +begin + + register_file_out <= register_file; + stall_flags_out <= stall_flags; + + -- merge all stall sources + stall_flags(ST_FE_FE2) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_FE2_DEC) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_DEC_ADG) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_ADG_EX) <= exec_loop_stall_do; + + + shift_pipeline: process(clk, rst) is + procedure flush_pipeline_stage(stage: natural) is + begin + pipeline_regs(stage).pc <= (others => '1'); + pipeline_regs(stage).instr_word <= (others => '0'); + pipeline_regs(stage).act_array <= (others => '0'); + pipeline_regs(stage).instr_array <= INSTR_NOP; + pipeline_regs(stage).dble_word_instr <= '0'; + pipeline_regs(stage).dec_activate <= '0'; + pipeline_regs(stage).adgen_mode_a <= NOP; + pipeline_regs(stage).adgen_mode_b <= NOP; + pipeline_regs(stage).reg_wr_addr <= (others => '0'); + pipeline_regs(stage).reg_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).y_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).y_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).l_bus_addr <= (others => '0'); + pipeline_regs(stage).adgen_address_x <= (others => '0'); + pipeline_regs(stage).adgen_address_y <= (others => '0'); + pipeline_regs(stage).RAM_out_x <= (others => '0'); + pipeline_regs(stage).RAM_out_y <= (others => '0'); + pipeline_regs(stage).alu_ctrl.store_result <= '0'; + end procedure flush_pipeline_stage; + begin + if rising_edge(clk) then + if rst = '1' then + for i in 0 to PIPELINE_DEPTH-1 loop + flush_pipeline_stage(i); + end loop; + else + -- shift the pipeline registers when no stall applies + for i in 1 to PIPELINE_DEPTH-1 loop + if stall_flags(i) = '0' then + -- The following situations have to be considered: + -- 1) Do not copy the pipeline registers from a stalled pipeline stage. + -- Instead insert NOPs into the pipeline, except for the REP instruction. + -- 2) Flushing of the ST_ADG_EX-stage is required when a memory access causes + -- a stall. In this case the EX-stage will perform its task and the pipeline + -- stage has to be flushed. Otherwise the instruction would be executed twice. +-- TODO: +-- What happens when memory writes cause a stall? => Flushing of ST_ADG_EX not allowed!? + if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or + (i = ST_ADG_EX and memory_stall = '1' and exec_loop_stall_rep = '1') then + flush_pipeline_stage(i); + else + pipeline_regs(i) <= pipeline_regs(i-1); + end if; + end if; + end loop; + -- FE_FE2 Pipeline Registers + if stall_flags(ST_FE_FE2) = '0' then + pipeline_regs(ST_FE_FE2).pc <= pc_new; + pipeline_regs(ST_FE_FE2).dec_activate <= '1'; + end if; + + -- FE2_DEC Pipeline Registers + if stall_flags(ST_FE2_DEC) = '0' then + -- Normal pipeline operation? + -- Buffering of RAM output when stalling is performed in the memory management + if pmem_data_out_valid = '1' then + pipeline_regs(ST_FE2_DEC).instr_word <= pmem_data_out; + end if; + end if; + + -- DEC_ADG Pipeline registers + if stall_flags(ST_DEC_ADG) = '0' then + pipeline_regs(ST_DEC_ADG).act_array <= dec_act_array; + pipeline_regs(ST_DEC_ADG).instr_array <= dec_instr_array; + pipeline_regs(ST_DEC_ADG).dble_word_instr <= dec_dble_word_instr; + pipeline_regs(ST_DEC_ADG).reg_wr_addr <= dec_reg_wr_addr; + pipeline_regs(ST_DEC_ADG).reg_rd_addr <= dec_reg_rd_addr; + pipeline_regs(ST_DEC_ADG).x_bus_wr_addr <= dec_x_bus_wr_addr; + pipeline_regs(ST_DEC_ADG).x_bus_rd_addr <= dec_x_bus_rd_addr; + pipeline_regs(ST_DEC_ADG).y_bus_wr_addr <= dec_y_bus_wr_addr; + pipeline_regs(ST_DEC_ADG).y_bus_rd_addr <= dec_y_bus_rd_addr; + pipeline_regs(ST_DEC_ADG).l_bus_addr <= dec_l_bus_addr; + pipeline_regs(ST_DEC_ADG).adgen_mode_a <= dec_adgen_mode_a; + pipeline_regs(ST_DEC_ADG).adgen_mode_b <= dec_adgen_mode_b; + pipeline_regs(ST_DEC_ADG).alu_ctrl <= dec_alu_ctrl; + end if; + + -- ADG_EX Pipeline registers + if stall_flags(ST_ADG_EX) = '0' then + pipeline_regs(ST_ADG_EX).adgen_address_x <= adgen_address_out_x; + pipeline_regs(ST_ADG_EX).adgen_address_y <= adgen_address_out_y; + end if; + +-- TODO: memory_stall neu eingebaut, noch nicht getestet. Hier evtl. wie oben direkt auf +-- stall_flags zugreifen (ST_ADG_EX)? + -- Copying to the pipeline register should only happen, when the stall is released. + -- Otherwise the content could be deleted before it is actually used (when x and y + -- content are not valid at the same time). + if xmem_ctrl_out.data_out_valid = '1' and memory_stall = '0' then + pipeline_regs(ST_ADG_EX).RAM_out_x <= xmem_ctrl_out.data_out; + end if; + if ymem_ctrl_out.data_out_valid = '1'and memory_stall = '0' then + pipeline_regs(ST_ADG_EX).RAM_out_y <= ymem_ctrl_out.data_out; + end if; + + -- EXECUTE Pipeline stuff + if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then + -- clear the following pipeline stages, + -- since we modified the pc. + -- Do not flush ST_FE_FE2 - it will hold the correct pc. + flush_pipeline_stage(ST_FE2_DEC); + flush_pipeline_stage(ST_DEC_ADG); + flush_pipeline_stage(ST_ADG_EX); + end if; + end if; + end if; + end process shift_pipeline; + + + ------------------------------- + -- FETCH STAGE INSTANTIATION + ------------------------------- + + inst_fetch_stage: fetch_stage port map( + pc_old => pc_old, + pc_new => pc_new, + modify_pc => fetch_modify_pc, + modified_pc => fetch_modified_pc, + register_file => register_file, + decrement_lc => fetch_decrement_lc, + perform_enddo => fetch_perform_enddo + ); + + pc_old <= pipeline_regs(ST_FE_FE2).pc; + + fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0'; + fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else + exec_loop_modified_pc; + + + ------------------------------- + -- DECODE STAGE INSTANTIATION + ------------------------------- + + inst_decode_stage : decode_stage port map( + activate_dec => dec_activate, + instr_word => dec_instr_word, + dble_word_instr => dec_dble_word_instr, + instr_array => dec_instr_array, + act_array => dec_act_array, + reg_wr_addr => dec_reg_wr_addr, + reg_rd_addr => dec_reg_rd_addr, + x_bus_wr_addr => dec_x_bus_wr_addr, + x_bus_rd_addr => dec_x_bus_rd_addr, + y_bus_wr_addr => dec_y_bus_wr_addr, + y_bus_rd_addr => dec_y_bus_rd_addr, + l_bus_addr => dec_l_bus_addr, + adgen_mode_a => dec_adgen_mode_a, + adgen_mode_b => dec_adgen_mode_b, + alu_ctrl => dec_alu_ctrl + ); + + dec_instr_word <= pipeline_regs(ST_FE2_DEC).instr_word; + -- do not decode, when we have no valid instruction. This can happen when + -- 1) the pipeline just started its operation + -- 2) the pipeline was flushed due to a jump + -- 3) we are processing an instruction that consists of two words + dec_activate <= '1' when pipeline_regs(ST_FE2_DEC).dec_activate = '1' and pipeline_regs(ST_DEC_ADG).dble_word_instr = '0' else '0'; + + + ------------------------------- + -- AGU STAGE INSTANTIATION + ------------------------------- + + inst_adgen_stage: adgen_stage port map( + activate_adgen => adgen_activate, + activate_x_mem => adgen_activate_x_mem, + activate_y_mem => adgen_activate_y_mem, + activate_l_mem => adgen_activate_l_mem, + instr_word => adgen_instr_word, + instr_array => adgen_instr_array, + optional_ea_word => adgen_optional_ea_word, + register_file => register_file, + adgen_mode_a => adgen_mode_a, + adgen_mode_b => adgen_mode_b, + address_out_x => adgen_address_out_x, + address_out_y => adgen_address_out_y, + wr_R_port_A_valid => adgen_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => adgen_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B + ); + + adgen_activate <= pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN); + adgen_activate_x_mem <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_RD) = '1' or + pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_WR) = '1' else '0'; + adgen_activate_y_mem <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_RD) = '1' or + pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_WR) = '1' else '0'; + adgen_activate_l_mem <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_L_BUS_RD) = '1' or + pipeline_regs(ST_DEC_ADG).act_array(ACT_L_BUS_WR) = '1' else '0'; + adgen_instr_word <= pipeline_regs(ST_DEC_ADG).instr_word; + adgen_instr_array <= pipeline_regs(ST_DEC_ADG).instr_array; + adgen_optional_ea_word <= pipeline_regs(ST_DEC_ADG-1).instr_word; + adgen_mode_a <= pipeline_regs(ST_DEC_ADG).adgen_mode_a; + adgen_mode_b <= pipeline_regs(ST_DEC_ADG).adgen_mode_b; + + + ------------------------------- + -- EXECUTE STAGE INSTANTIATIONS + ------------------------------- + + -- Data ALU (MPY, MAC, ADD, shift, ...) + inst_exec_stage_alu: exec_stage_alu port map( + alu_activate => exec_alu_activate, + instr_word => exec_alu_instr_word, + alu_ctrl => exec_alu_ctrl, + register_file => register_file, + addr_r_in => exec_alu_addr_r_in, + addr_r_out => exec_alu_addr_r_out, + modify_accu => exec_alu_modify_accu, + dst_accu => exec_alu_dst_accu, + modified_accu => exec_alu_modified_accu, + modify_sr => exec_alu_modify_sr, + modified_sr => exec_alu_modified_sr + ); + + exec_alu_activate <= pipeline_regs(ST_ADG_EX).act_array(ACT_ALU); + exec_alu_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_alu_ctrl <= pipeline_regs(ST_ADG_EX).alu_ctrl; + + exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0)); + + -- Bit modification unit (BCLR, BSET, BCHG, ...) + inst_exec_stage_bit_modify: exec_stage_bit_modify port map( + instr_word => exec_bit_modify_instr_word, + instr_array => exec_bit_modify_instr_array, + src_operand => exec_bit_modify_src_operand, + register_file => register_file, + dst_operand => exec_bit_modify_dst_operand, + bit_cond_met => exec_bit_modify_bit_cond_met, + modify_sr => exec_bit_modify_modify_sr, + modified_sr => exec_bit_modify_modified_sr + ); + + exec_bit_modify_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_bit_modify_instr_array <= pipeline_regs(ST_ADG_EX).instr_array; + exec_bit_modify_src_operand <= exec_src_operand; + + -- Writing to the register file using the 6 bit addressing scheme + -- sources are: + -- 1) X-RAM output + -- 2) Y-RAM output + -- 3) register file itself + -- 4) short immediate value (8 bit stored in instruction word) + -- 5) long immediate value (from optional effective address extension) + -- 6) address generated by the address generation unit (LUA instr) + exec_src_operand <= pipeline_regs(ST_ADG_EX).RAM_out_x when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_RD) = '1' else + pipeline_regs(ST_ADG_EX).RAM_out_y when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_RD) = '1' else + rf_reg_rd_data when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_RD) = '1' else + exec_imm_8bit when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_8BIT) = '1' else + exec_imm_12bit when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_12BIT) = '1' else + pipeline_regs(ST_ADG_EX-1).instr_word when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_LONG) = '1' else + std_logic_vector(resize(pipeline_regs(ST_ADG_EX).adgen_address_x, 24)); -- for LUA instr. + + -- Destination for the register file using the 6 bit addressing scheme. + -- Either read the bit modified version of the read value + -- or the output of a p-memory read + -- or use the modified Rn in case of a NORM instruction + exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_ADG_EX).act_array(ACT_NORM) = '0' else + pmem2_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_P_MEM_RD) = '1' else + std_logic_vector(resize(exec_alu_addr_r_out,24)); + + -- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true + inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map( + instr_word => exec_cc_flag_calc_instr_word, + instr_array => exec_cc_flag_calc_instr_array, + register_file => register_file, + cc_flag_set => exec_cc_flag_set + ); + + exec_cc_flag_calc_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_cc_flag_calc_instr_array <= pipeline_regs(ST_ADG_EX).instr_array; + + -- Branch calculation unit + inst_exec_stage_branch : exec_stage_branch port map( + activate_exec_bra => exec_bra_activate, + instr_word => exec_bra_instr_word, + instr_array => exec_bra_instr_array, + register_file => register_file, + jump_address => exec_bra_jump_address, + bit_cond_met => exec_bra_bit_cond_met, + cc_flag_set => exec_cc_flag_set, + push_stack => exec_bra_push_stack, + pop_stack => exec_bra_pop_stack, + modify_pc => exec_bra_modify_pc, + modified_pc => exec_bra_modified_pc, + modify_sr => exec_bra_modify_sr, + modified_sr => exec_bra_modified_sr + ); + + exec_bra_activate <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_BRA); + exec_bra_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_bra_instr_array <= pipeline_regs(ST_ADG_EX).instr_array; + exec_bra_jump_address <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).dble_word_instr = '0' else + unsigned(pipeline_regs(ST_ADG_EX-1).instr_word(BW_ADDRESS-1 downto 0)); + exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met; + + -- Control register modifications + inst_exec_stage_cr_mod : exec_stage_cr_mod port map( + activate_exec_cr_mod => exec_cr_mod_activate, + instr_word => exec_cr_mod_instr_word, + instr_array => exec_cr_mod_instr_array, + register_file => register_file, + modify_sr => exec_cr_mod_modify_sr, + modified_sr => exec_cr_mod_modified_sr, + modify_omr => exec_cr_mod_modify_omr, + modified_omr => exec_cr_mod_modified_omr + ); + + exec_cr_mod_activate <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_CR_MOD); + exec_cr_mod_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_cr_mod_instr_array <= pipeline_regs(ST_ADG_EX).instr_array; + + -- Loop control + inst_exec_stage_loop: exec_stage_loop port map( + clk => clk, + rst => rst, + activate_exec_loop => exec_loop_activate, + instr_word => exec_loop_instr_word, + instr_array => exec_loop_instr_array, + loop_iterations => exec_loop_iterations, + loop_address => exec_loop_address, + loop_start_address => exec_loop_start_address, + register_file => register_file, + fetch_perform_enddo=> fetch_perform_enddo, + memory_stall => memory_stall, + push_stack => exec_loop_push_stack, + pop_stack => exec_loop_pop_stack, + stall_rep => exec_loop_stall_rep, + stall_do => exec_loop_stall_do, + modify_lc => exec_loop_modify_lc, + decrement_lc => exec_loop_decrement_lc, + modified_lc => exec_loop_modified_lc, + modify_la => exec_loop_modify_la, + modified_la => exec_loop_modified_la, + modify_pc => exec_loop_modify_pc, + modified_pc => exec_loop_modified_pc, + modify_sr => exec_loop_modify_sr, + modified_sr => exec_loop_modified_sr + ); + + exec_loop_activate <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_LOOP); + exec_loop_instr_word <= pipeline_regs(ST_ADG_EX).instr_word; + exec_loop_instr_array <= pipeline_regs(ST_ADG_EX).instr_array; + exec_loop_iterations <= unsigned(exec_src_operand(15 downto 0)); + + -- Loop address is given by the second instruction word of the DO instruction. + -- This address is available one previous stage within the pipeline + exec_loop_address <= unsigned(pipeline_regs(ST_ADG_EX-1).instr_word(BW_ADDRESS-1 downto 0)) - 1; + -- one more stage before we find the programm counter of the first instruction to be executed in a DO loop + exec_loop_start_address <= unsigned(pipeline_regs(ST_ADG_EX-2).pc); + + -- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest) + exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else + pipeline_regs(ST_ADG_EX).instr_word(15 downto 8); + exec_imm_8bit(15 downto 8) <= (others => '0'); + exec_imm_8bit( 7 downto 0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else + pipeline_regs(ST_ADG_EX).instr_word(15 downto 8); + -- The 12 bit immediate stems from the instruction word + exec_imm_12bit(23 downto 12) <= (others => '0'); + exec_imm_12bit(11 downto 0) <= pipeline_regs(ST_ADG_EX).instr_word(3 downto 0) & pipeline_regs(ST_ADG_EX).instr_word(15 downto 8); + + + ----------------- + -- REGISTER FILE + ----------------- + + inst_reg_file: reg_file port map( + clk => clk, + rst => rst, + + -- Output for reading when needed + register_file => register_file, + + -- AGU write ports + wr_R_port_A_valid => rf_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => rf_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B, + + -- register read/write port + reg_wr_addr => rf_reg_wr_addr, + reg_wr_addr_valid => rf_reg_wr_addr_valid, + reg_wr_data => rf_reg_wr_data, + reg_rd_addr => rf_reg_rd_addr, + reg_rd_data => rf_reg_rd_data, + + -- ALU result write port + alu_wr_valid => rf_alu_wr_valid, + alu_wr_addr => exec_alu_dst_accu, + alu_wr_data => exec_alu_modified_accu, + + -- Bus read and write ports (X/Y/L) + X_bus_rd_addr => rf_X_bus_rd_addr, + X_bus_data_out => rf_X_bus_data_out, + X_bus_wr_addr => rf_X_bus_wr_addr , + X_bus_wr_valid => rf_X_bus_wr_valid, + X_bus_data_in => rf_X_bus_data_in , + Y_bus_rd_addr => rf_Y_bus_rd_addr , + Y_bus_data_out => rf_Y_bus_data_out, + Y_bus_wr_addr => rf_Y_bus_wr_addr , + Y_bus_wr_valid => rf_Y_bus_wr_valid, + Y_bus_data_in => rf_Y_bus_data_in , + L_bus_rd_addr => rf_L_bus_rd_addr , + L_bus_rd_valid => rf_L_bus_rd_valid, + L_bus_wr_addr => rf_L_bus_wr_addr , + L_bus_wr_valid => rf_L_bus_wr_valid, + + -- Stack modifications + push_stack => push_stack, + pop_stack => pop_stack, + + -- Control register modifications + set_sr => rf_set_sr, + new_sr => rf_new_sr, + set_omr => rf_set_omr, + new_omr => rf_new_omr, + set_la => rf_set_la, + new_la => rf_new_la, + dec_lc => rf_dec_lc, + set_lc => rf_set_lc, + new_lc => rf_new_lc + ); + + -- writing to the R registers within the ADGEN stage has to be prevented when + -- 1) a jump is currently being executed (which is detected in the exec stage) + -- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling. + -- 3) a memory access results in a stall (e.g. caused by the instruction to REP) + rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADG_EX) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_A_valid; + rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADG_EX) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_B_valid; + + + rf_reg_wr_addr <= pipeline_regs(ST_ADG_EX).reg_wr_addr; + -- can be set due to + -- 1) normal write operation (e.g., move) + -- 2) conditional move (Tcc) + rf_reg_wr_addr_valid <= '1' when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_WR) = '1' else + exec_cc_flag_set when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_WR_CC) = '1' else '0'; + rf_reg_wr_data <= exec_dst_operand; + + rf_reg_rd_addr <= pipeline_regs(ST_ADG_EX).reg_rd_addr; + + -- Writing from the ALU can depend on the condition code (Tcc) instruction + rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_ADG_EX).act_array(ACT_ALU_WR_CC) = '1' else + exec_alu_modify_accu; + + push_stack.valid <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0'; + push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else + exec_loop_push_stack.content; + -- for jump to subroutine store the pc of the subsequent instruction + push_stack.pc <= pipeline_regs(ST_ADG_EX-1).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_ADG_EX).dble_word_instr = '0' else + pipeline_regs(ST_ADG_EX-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_ADG_EX).dble_word_instr = '1' else + exec_loop_push_stack.pc when exec_loop_push_stack.valid = '1' else + (others => '0'); + + pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0'; + + rf_set_sr <= '1' when exec_bra_modify_sr = '1' or + exec_cr_mod_modify_sr = '1' or + exec_loop_modify_sr = '1' or + exec_alu_modify_sr = '1' or + exec_bit_modify_modify_sr = '1' else '0'; + rf_new_sr <= exec_bra_modified_sr when exec_bra_modify_sr = '1' else + exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else + exec_loop_modified_sr when exec_loop_modify_sr = '1' else + exec_alu_modified_sr when exec_alu_modify_sr = '1' else + exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else + + rf_set_omr <= exec_cr_mod_modify_omr; + rf_new_omr <= exec_cr_mod_modified_omr; + rf_set_lc <= exec_loop_modify_lc; + rf_new_lc <= exec_loop_modified_lc; + rf_set_la <= exec_loop_modify_la; + rf_new_la <= exec_loop_modified_la; + + rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0'; + + ----------------- + -- BUSES (X,Y,L) + ----------------- + + rf_X_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_WR); + rf_X_bus_wr_addr <= pipeline_regs(ST_ADG_EX).x_bus_wr_addr; + rf_X_bus_rd_addr <= pipeline_regs(ST_ADG_EX).x_bus_rd_addr; + rf_X_bus_data_in <= rf_X_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_RD) = '1' else + pipeline_regs(ST_ADG_EX).RAM_out_x; -- when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_RD) = '1' else + + rf_Y_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_WR); + rf_Y_bus_wr_addr <= pipeline_regs(ST_ADG_EX).y_bus_wr_addr; + rf_Y_bus_rd_addr <= pipeline_regs(ST_ADG_EX).y_bus_rd_addr; + rf_Y_bus_data_in <= rf_Y_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_RD) = '1' else + pipeline_regs(ST_ADG_EX).RAM_out_y; -- when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_RD) = '1' else + + rf_L_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_WR); + rf_L_bus_rd_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD); + rf_L_bus_wr_addr <= pipeline_regs(ST_ADG_EX).l_bus_addr; -- equal to bits in instruction word + rf_L_bus_rd_addr <= pipeline_regs(ST_ADG_EX).l_bus_addr; -- could be simplified by taking these bits.. + + + data_rom_enable <= register_file.omr(2); + + + ------------------------- + -- Program Memory Port 1 + -------------------------- + + -- pmem port 1 is only for instruction fetch + pmem_ctrl_in.rd_addr <= pc_new; + pmem_ctrl_in.rd_en <= '1' when stall_flags(ST_FE_FE2) = '0' else '0'; + + -- never write to this port + pmem_ctrl_in.wr_addr <= (others => '0'); + pmem_ctrl_in.wr_en <= '0'; + pmem_ctrl_in.data_in <= (others => '0'); + + pmem_data_out <= pmem_ctrl_out.data_out; + pmem_data_out_valid <= pmem_ctrl_out.data_out_valid; + + + ------------------------- + -- Program Memory Port 2 + -------------------------- +-- TODO: This is untested! + + -- pmem port 2 is for movem instructions + + -- take x memory address as address + pmem2_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8)); + pmem2_ctrl_in.rd_en <= pipeline_regs(ST_DEC_ADG).act_array(ACT_P_MEM_RD); + + + -- Either take the result of the AGU or use the absolute value stored in the instruction word + pmem2_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8)); + pmem2_ctrl_in.wr_en <= pipeline_regs(ST_ADG_EX).act_array(ACT_P_MEM_WR); + + -- only the register file read value is allowed here + pmem2_ctrl_in.data_in <= rf_reg_rd_data; + + pmem2_data_out <= pmem2_ctrl_out.data_out; + pmem2_data_out_valid <= pmem2_ctrl_out.data_out_valid; + + ------------------ + -- X Memory + ------------------ + + -- Either take the result of the AGU or use the short absolute value stored in the instruction word + xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8)); + xmem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + xmem_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8)); + xmem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_WR) = '1' else '0'; + xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_RD) = '1' or + pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + + + ------------------ + -- Y Memory + ------------------ + + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8)); + ymem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_y when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8)); + ymem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_WR) = '1' else '0'; + ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_RD) = '1' or + pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + +end architecture rtl; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd new file mode 100644 index 0000000..afeeda0 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd @@ -0,0 +1,686 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Global register file, including scaler and limiter +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + dec_lc : in std_logic; + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) +); +end entity; + + +architecture rtl of reg_file is + + signal addr_r : addr_array; + signal addr_m : addr_array; + signal addr_n : addr_array; + + signal loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal loop_counter : unsigned(15 downto 0); + + -- condition code register + signal ccr : std_logic_vector(7 downto 0); + -- mode register + signal mr : std_logic_vector(7 downto 0); + -- status register = mode register + condition code register + signal sr : std_logic_vector(15 downto 0); + -- operation mode register + signal omr : std_logic_vector(7 downto 0); + + signal stack_pointer : unsigned(5 downto 0); + signal system_stack_ssh : stack_array_type; + signal system_stack_ssl : stack_array_type; + + signal x0 : signed(23 downto 0); + signal x1 : signed(23 downto 0); + signal y0 : signed(23 downto 0); + signal y1 : signed(23 downto 0); + + signal a0 : signed(23 downto 0); + signal a1 : signed(23 downto 0); + signal a2 : signed(7 downto 0); + + signal b0 : signed(23 downto 0); + signal b1 : signed(23 downto 0); + signal b2 : signed(7 downto 0); + + signal limited_a1 : signed(23 downto 0); + signal limited_b1 : signed(23 downto 0); + signal limited_a0 : signed(23 downto 0); + signal limited_b0 : signed(23 downto 0); + signal set_limiting_flag : std_logic; + signal X_bus_rd_limited_a : std_logic; + signal X_bus_rd_limited_b : std_logic; + signal Y_bus_rd_limited_a : std_logic; + signal Y_bus_rd_limited_b : std_logic; + signal reg_rd_limited_a : std_logic; + signal reg_rd_limited_b : std_logic; + signal rd_limited_a : std_logic; + signal rd_limited_b : std_logic; + +begin + + + + sr <= mr & ccr; + + register_file.addr_r <= addr_r; + register_file.addr_n <= addr_n; + register_file.addr_m <= addr_m; + register_file.lc <= loop_counter; + register_file.la <= loop_address; + register_file.ccr <= ccr; + register_file.mr <= mr; + register_file.sr <= sr; + register_file.omr <= omr; + register_file.stack_pointer <= stack_pointer; + register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0))); + register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0))); + register_file.a <= a2 & a1 & a0; + register_file.b <= b2 & b1 & b0; + register_file.x0 <= x0; + register_file.x1 <= x1; + register_file.y0 <= y0; + register_file.y1 <= y1; + + + global_register_file: process(clk) is + variable stack_pointer_plus_1 : unsigned(3 downto 0); + variable reg_addr : integer range 0 to 7; + begin + if rising_edge(clk) then + if rst = '1' then + addr_r <= (others => (others => '0')); + addr_n <= (others => (others => '0')); + addr_m <= (others => (others => '1')); + ccr <= (others => '0'); + mr <= (others => '0'); + omr <= (others => '0'); + system_stack_ssl <= (others => (others => '0')); + system_stack_ssh <= (others => (others => '0')); + stack_pointer <= (others => '0'); + loop_counter <= (others => '0'); + loop_address <= (others => '0'); + x0 <= (others => '0'); + x1 <= (others => '0'); + y0 <= (others => '0'); + y1 <= (others => '0'); + a0 <= (others => '0'); + a1 <= (others => '0'); + a2 <= (others => '0'); + b0 <= (others => '0'); + b1 <= (others => '0'); + b2 <= (others => '0'); + else + reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0))); + ----------------------------------------------------------------------- + -- General write port to register file using 6 bit addressing scheme + ----------------------------------------------------------------------- + if reg_wr_addr_valid = '1' then + case reg_wr_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_wr_addr(2 downto 0) is + when "100" => + x0 <= signed(reg_wr_data); + when "101" => + x1 <= signed(reg_wr_data); + when "110" => + y0 <= signed(reg_wr_data); + when "111" => + y1 <= signed(reg_wr_data); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_wr_addr(2 downto 0) is + when "000" => + a0 <= signed(reg_wr_data); + when "001" => + b0 <= signed(reg_wr_data); + when "010" => + a2 <= signed(reg_wr_data(7 downto 0)); + when "011" => + b2 <= signed(reg_wr_data(7 downto 0)); + when "100" => + a1 <= signed(reg_wr_data); + when "101" => + b1 <= signed(reg_wr_data); + when "110" => + a2 <= (others => reg_wr_data(23)); + a1 <= signed(reg_wr_data); + a0 <= (others => '0'); + when "111" => + b2 <= (others => reg_wr_data(23)); + b1 <= signed(reg_wr_data); + b0 <= (others => '0'); + when others => + end case; + + -- R0-R7 + when "010" => + addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- N0-N7 + when "011" => + addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- M0-M7 + when "100" => + addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + mr <= reg_wr_data(15 downto 8); + ccr <= reg_wr_data( 7 downto 0); + + -- OMR + when "010" => + omr <= reg_wr_data(7 downto 0); + + -- SP + when "011" => + stack_pointer <= unsigned(reg_wr_data(5 downto 0)); + + -- SSH + when "100" => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + + -- SSL + when "101" => + system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + + -- LA + when "110" => + loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- LC + when "111" => + loop_counter <= unsigned(reg_wr_data(15 downto 0)); + + when others => + end case; + when others => + end case; + end if; + + ---------------- + -- X BUS Write + ---------------- + if X_bus_wr_valid = '1' then + case X_bus_wr_addr is + when "00" => + x0 <= signed(X_bus_data_in); + when "01" => + x1 <= signed(X_bus_data_in); + when "10" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ---------------- + -- Y BUS Write + ---------------- + if Y_bus_wr_valid = '1' then + case Y_bus_wr_addr is + when "00" => + y0 <= signed(Y_bus_data_in); + when "01" => + y1 <= signed(Y_bus_data_in); + when "10" => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ------------------ + -- L BUS Write + ------------------ + if L_bus_wr_valid = '1' then + case L_bus_wr_addr is + -- A10 + when "000" => + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B10 + when "001" => + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- X + when "010" => + x1 <= signed(X_bus_data_in); + x0 <= signed(Y_bus_data_in); + -- Y + when "011" => + y1 <= signed(X_bus_data_in); + y0 <= signed(Y_bus_data_in); + -- A + when "100" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B + when "101" => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- AB + when "110" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + -- BA + when others => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + + --------------------- + -- STATUS REGISTERS + --------------------- + if set_sr = '1' then + ccr <= new_sr( 7 downto 0); + mr <= new_sr(15 downto 8); + end if; + if set_omr = '1' then + omr <= new_omr; + end if; + -- data limiter active? + -- listing this statement after the set_sr test results + -- in the correct behaviour for ALU operations with parallel move + if set_limiting_flag = '1' then + ccr(6) <= '1'; + end if; + + -------------------- + -- LOOP REGISTERS + -------------------- + if set_la = '1' then + loop_address <= new_la; + end if; + if set_lc = '1' then + loop_counter <= new_lc; + end if; + if dec_lc = '1' then + loop_counter <= loop_counter - 1; + end if; + + --------------------- + -- ADDRESS REGISTER + --------------------- + if wr_R_port_A_valid = '1' then + addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value; + end if; + if wr_R_port_B_valid = '1' then + addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value; + end if; + + ------------------------- + -- ALU ACCUMULATOR WRITE + ------------------------- + if alu_wr_valid = '1' then + if alu_wr_addr = '0' then + a2 <= alu_wr_data(55 downto 48); + a1 <= alu_wr_data(47 downto 24); + a0 <= alu_wr_data(23 downto 0); + else + b2 <= alu_wr_data(55 downto 48); + b1 <= alu_wr_data(47 downto 24); + b0 <= alu_wr_data(23 downto 0); + end if; + end if; + + --------------------- + -- STACK CONTROLLER + --------------------- + stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1; + if push_stack.valid = '1' then + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + case push_stack.content is + when PC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + + when PC_AND_SR => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR; + + when LA_AND_LC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter); + + end case; + end if; + + -- decrease stack pointer + if pop_stack.valid = '1' then + stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1; + -- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE) + if stack_pointer(3 downto 0) = "0000" then + stack_pointer(5) <= '1'; + stack_pointer(4) <= '1'; + end if; + end if; + end if; + end if; + end process; + + + x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,y1) is + begin + X_bus_rd_limited_a <= '0'; + X_bus_rd_limited_b <= '0'; + case X_bus_rd_addr is + when "00" => X_bus_data_out <= std_logic_vector(x0); + when "01" => X_bus_data_out <= std_logic_vector(x1); + when "10" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => X_bus_data_out <= std_logic_vector(a1); + when "001" => X_bus_data_out <= std_logic_vector(b1); + when "010" => X_bus_data_out <= std_logic_vector(x1); + when "011" => X_bus_data_out <= std_logic_vector(y1); + when "100" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when "101" => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + when "110" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + end if; + end process x_bus_rd_port; + + y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is + begin + Y_bus_rd_limited_a <= '0'; + Y_bus_rd_limited_b <= '0'; + case Y_bus_rd_addr is + when "00" => Y_bus_data_out <= std_logic_vector(y0); + when "01" => Y_bus_data_out <= std_logic_vector(y1); + when "10" => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => Y_bus_data_out <= std_logic_vector(a0); + when "001" => Y_bus_data_out <= std_logic_vector(b0); + when "010" => Y_bus_data_out <= std_logic_vector(x0); + when "011" => Y_bus_data_out <= std_logic_vector(y0); + when "100" => Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1'; + when "101" => Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1'; + when "110" => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + end case; + end if; + end process y_bus_rd_port; + + + reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2, + omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer, + loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is + variable reg_addr : integer range 0 to 7; + begin + reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0))); + reg_rd_data <= (others => '0'); + reg_rd_limited_a <= '0'; + reg_rd_limited_b <= '0'; + + case reg_rd_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_rd_addr(2 downto 0) is + when "100" => + reg_rd_data <= std_logic_vector(x0); + when "101" => + reg_rd_data <= std_logic_vector(x1); + when "110" => + reg_rd_data <= std_logic_vector(y0); + when "111" => + reg_rd_data <= std_logic_vector(y1); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_rd_addr(2 downto 0) is + when "000" => + reg_rd_data <= std_logic_vector(a0); + when "001" => + reg_rd_data <= std_logic_vector(b0); + when "010" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(a2); + when "011" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(b2); + when "100" => + reg_rd_data <= std_logic_vector(a1); + when "101" => + reg_rd_data <= std_logic_vector(b1); + when "110" => + reg_rd_data <= std_logic_vector(limited_a1); + reg_rd_limited_a <= '1'; + when "111" => + reg_rd_data <= std_logic_vector(limited_b1); + reg_rd_limited_b <= '1'; + when others => + end case; + + -- R0-R7 + when "010" => + reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24)); + + -- N0-N7 + when "011" => + reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24)); + + -- M0-M7 + when "100" => + reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + reg_rd_data(23 downto 16) <= (others => '0'); + reg_rd_data(15 downto 0) <= mr & ccr; + + -- OMR + when "010" => + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data( 7 downto 0) <= omr; + + -- SP + when "011" => + reg_rd_data(23 downto 6) <= (others => '0'); + reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer); + + -- SSH + when "100" => +-- TODO! +-- system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); +-- -- increase stack after writing +-- stack_pointer(3 downto 0) <= stack_pointer_plus_1; +-- -- test whether stack is full, if so set the stack error flag (SE) +-- if stack_pointer(3 downto 0) = "1111" then +-- stack_pointer(4) <= '1'; +-- end if; + + -- SSL + when "101" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer))); + + -- LA + when "110" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address); + + -- LC + when "111" => + reg_rd_data <= (others => '0'); + reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter); + + when others => + end case; + when others => + end case; + end process; + + rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0'; + rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0'; + + data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is + variable scaled_a : signed(55 downto 0); + variable scaled_b : signed(55 downto 0); + begin + + set_limiting_flag <= '0'; + ----------------- + -- DATA SCALING + ----------------- + -- test against scaling bits S1, S0 + case sr(11 downto 10) is + -- scale down (right shift) + when "01" => + scaled_a := a2(7) & a2 & a1 & a0(23 downto 1); + scaled_b := b2(7) & b2 & b1 & b0(23 downto 1); + -- scale up (arithmetic left shift) + when "10" => + scaled_a := a2(6 downto 0) & a1 & a0 & '0'; + scaled_b := b2(6 downto 0) & b1 & b0 & '0'; + -- "00" do not scale! + when others => + scaled_a := a2 & a1 & a0; + scaled_b := b2 & b1 & b0; + end case; + + -- only sign extension stored in a2? + -- Yes: No limiting needed! + if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then + limited_a1 <= scaled_a(47 downto 24); + limited_a0 <= scaled_a(23 downto 0); + else + -- positive value in a? + if scaled_a(55) = '0' then + limited_a1 <= X"7FFFFF"; + limited_a0 <= X"FFFFFF"; + -- negative value in a? + else + limited_a1 <= X"800000"; + limited_a0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_a = '1' then + set_limiting_flag <= '1'; + end if; + end if; + -- only sign extension stored in b2? + -- Yes: No limiting needed! + if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then + limited_b1 <= scaled_b(47 downto 24); + limited_b0 <= scaled_b(23 downto 0); + else + -- positive value in b? + if scaled_b(55) = '0' then + limited_b1 <= X"7FFFFF"; + limited_b0 <= X"FFFFFF"; + -- negative value in b? + else + limited_b1 <= X"800000"; + limited_b0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_b = '1' then + set_limiting_flag <= '1'; + end if; + end if; + + end process; + + +end architecture rtl; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd new file mode 100644 index 0000000..f0f1175 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +--! @file +--! @author Matthias Alles +--! @date 01/2009 +--! @brief Global types +--! +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; + + + +package types_pkg is + + -- the different addressing modes + type ADGen_mode_type is (NOP, + POST_MIN_N, + POST_PLUS_N, + POST_MIN_1, + POST_PLUS_1, + INDEXED_N, + PRE_MIN_1, + ABSOLUTE, + IMMEDIATE); + + ------------------------ + -- Decoded instructions + ------------------------ + type instructions_type is ( + INSTR_NOP , + INSTR_RTI , + INSTR_ILLEGAL , + INSTR_SWI , + INSTR_RTS , + INSTR_RESET , + INSTR_WAIT , + INSTR_STOP , + INSTR_ENDDO , + INSTR_ANDI , + INSTR_ORI , + INSTR_DIV , + INSTR_NORM , + INSTR_LUA , + INSTR_MOVEC , + INSTR_REP , + INSTR_DO , + INSTR_MOVEM , + INSTR_MOVEP , + INSTR_PM_MOVEM, + INSTR_BCLR , + INSTR_BSET , + INSTR_JCLR , + INSTR_JSET , + INSTR_JMP , + INSTR_JCC , + INSTR_BCHG , + INSTR_BTST , + INSTR_JSCLR , + INSTR_JSSET , + INSTR_JSR , + INSTR_JSCC ); + + type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0); + + type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS); + type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET); + type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag; + + type alu_ctrl_type is record + mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + shift_src : std_logic; -- a,b + shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + shift_mode : alu_shift_mode; + rotate : std_logic; -- 0: logical shift, 1: rotate shift + add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b + add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved + add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + logic_function : std_logic_vector(2 downto 0); -- 000: none, 001: and, 010: or, 011: eor, 100: not + word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? + rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry + store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator + dst_accu : std_logic; -- 0: a, 1: b + div_instr : std_logic; -- DIV instruction? Special ALU operations needed! + norm_instr : std_logic; -- NORM instruction? Special ALU operations needed! + ccr_flags_ctrl : alu_ccr_flag_array; + end record; + + type pipeline_signals is record + instr_word: std_logic_vector(23 downto 0); + pc : unsigned(BW_ADDRESS-1 downto 0); + dble_word_instr : std_logic; + instr_array : instructions_type; + act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + dec_activate : std_logic; + adgen_mode_a : adgen_mode_type; + adgen_mode_b : adgen_mode_type; + reg_wr_addr : std_logic_vector(5 downto 0); + reg_rd_addr : std_logic_vector(5 downto 0); + x_bus_rd_addr : std_logic_vector(1 downto 0); + x_bus_wr_addr : std_logic_vector(1 downto 0); + y_bus_rd_addr : std_logic_vector(1 downto 0); + y_bus_wr_addr : std_logic_vector(1 downto 0); + l_bus_addr : std_logic_vector(2 downto 0); + adgen_address_x : unsigned(BW_ADDRESS-1 downto 0); + adgen_address_y : unsigned(BW_ADDRESS-1 downto 0); + RAM_out_x : std_logic_vector(23 downto 0); + RAM_out_y : std_logic_vector(23 downto 0); + alu_ctrl : alu_ctrl_type; + end record; + + type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals; + + + type register_file_type is record + a : signed(55 downto 0); + b : signed(55 downto 0); + x0 : signed(23 downto 0); + x1 : signed(23 downto 0); + y0 : signed(23 downto 0); + y1 : signed(23 downto 0); + la : unsigned(BW_ADDRESS-1 downto 0); + lc : unsigned(15 downto 0); + addr_r : addr_array; + addr_n : addr_array; + addr_m : addr_array; + ccr : std_logic_vector(7 downto 0); + mr : std_logic_vector(7 downto 0); + sr : std_logic_vector(15 downto 0); + omr : std_logic_vector(7 downto 0); + stack_pointer : unsigned(5 downto 0); +-- system_stack_ssh : stack_array_type; +-- system_stack_ssl : stack_array_type; + current_ssh : std_logic_vector(BW_ADDRESS-1 downto 0); + current_ssl : std_logic_vector(BW_ADDRESS-1 downto 0); + + end record; + + type addr_wr_port_type is record +-- write_valid : std_logic; + reg_number : unsigned(2 downto 0); + reg_value : unsigned(15 downto 0); + end record; + + type mem_ctrl_type_in is record + rd_addr : unsigned(BW_ADDRESS-1 downto 0); + rd_en : std_logic; + wr_addr : unsigned(BW_ADDRESS-1 downto 0); + wr_en : std_logic; + data_in : std_logic_vector(23 downto 0); + end record; + + type mem_ctrl_type_out is record + data_out : std_logic_vector(23 downto 0); + data_out_valid : std_logic; + end record; + + type memory_type is (X_MEM, Y_MEM, P_MEM); + --------------- + -- STACK TYPES + --------------- + type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0); + + type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC); + + type push_stack_type is record + valid : std_logic; + pc : unsigned(BW_ADDRESS-1 downto 0); + content : push_stack_content_type; + end record; + + +-- type pop_stack_type is std_logic; + type pop_stack_type is record + valid : std_logic; +-- content : pop_stack_content_type; + end record; + +end package types_pkg; diff --git a/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd new file mode 100644 index 0000000..e4ed829 --- /dev/null +++ b/BaS_codewarrior/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + +entity tb_pipeline is generic ( + clk_period : time := 10 ns + ); + + +end entity tb_pipeline; + + +architecture uut of tb_pipeline is + + signal clk : std_logic := '0'; + signal rst : std_logic; + + component pipeline is port( + clk, rst : std_logic + ); + end component pipeline; + +begin + + + + uut: pipeline port map( + clk => clk, + rst => rst + ); + + clk_gen: process + begin + wait for clk_period/2; + clk <= not clk; + end process clk_gen; + + rst_gen : process + begin + rst <= '1'; + wait for 10 * clk_period; + rst <= '0'; + wait; + end process rst_gen; + +end architecture uut; diff --git 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b/BaS_codewarrior/firebeeV1/bin/DDRAM.elf.xMAP new file mode 100644 index 0000000..a677e37 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/bin/DDRAM.elf.xMAP @@ -0,0 +1,80 @@ + + +#>1FE00000 ___Bas_base (linker command file) +#>E0000000 ___BOOT_FLASH (linker command file) +#>00800000 ___BOOT_FLASH_SIZE (linker command file) +#>00000000 ___SDRAM (linker command file) +#>20000000 ___SDRAM_SIZE (linker command file) +#>FF000000 ___MBAR (linker command file) +#>FF040000 ___MMUBAR (linker command file) +#>FF100000 ___RAMBAR0 (linker command file) +#>00001000 ___RAMBAR0_SIZE (linker command file) +#>FF100FFC ___SUP_SP (linker command file) +#>FF101000 ___RAMBAR1 (linker command file) +#>00001000 ___RAMBAR1_SIZE (linker command file) +#>FF100800 _rt_mod (linker command file) +#>FF100804 _rt_ssp (linker command file) +#>FF100808 _rt_usp (linker command file) +#>FF10080C _rt_vbr (linker command file) +#>FF100810 _rt_cacr (linker command file) +#>FF100814 _rt_asid (linker command file) +#>FF100818 _rt_acr0 (linker command file) +#>FF10081C _rt_acr1 (linker command file) +#>FF100820 _rt_acr2 (linker command file) +#>FF100824 _rt_acr3 (linker command file) +#>FF100828 _rt_mmubar (linker command file) +#>FF100844 _rt_mbar (linker command file) +#>FF100848 _d0_save (linker command file) +#>FF10084C _a7_save (linker command file) +#>FF010000 ___SYS_SRAM (linker command file) +#>00008000 ___SYS_SRAM_SIZE (linker command file) + +# .userram + +# .code + +# .text + 1FE00000 0000005C .text _startup (startcf.c) + 1FE0005C 00000208 .text BaS (BaS.c) + 1FE00264 000001CC .text .text (mmu.s) + 1FE00264 00000000 .text mmu_init (mmu.s) + 1FE00264 000001CC .text @DummyFn3 (mmu.s) + 1FE003F8 00000000 .text mmutr_miss (mmu.s) + 1FE00430 0000072E .text @DummyFn1 (exceptions.s) + 1FE00430 00000000 .text vec_init (exceptions.s) + 1FE00430 0000072E .text .text (exceptions.s) + 1FE00B60 00000000 .text privileg_violation (supervisor.s) + 1FE00B60 000005BC .text .text (supervisor.s) + 1FE0111C 00000188 .text .text (illegal_instruction.s) + 1FE0111C 00000188 .text @DummyFn2 (illegal_instruction.s) + 1FE012A2 00000000 .text illegal_instruction (illegal_instruction.s) + 1FE012A2 00000000 .text illegal_table_make (illegal_instruction.s) + 1FE012A4 0000003C .text init_slt (sysinit.c) + 1FE012E0 00000068 .text init_gpio (sysinit.c) + 1FE01348 000001C4 .text init_seriel (sysinit.c) + 1FE0150C 000000F4 .text init_ddram (sysinit.c) + 1FE01600 000000DC .text init_fbcs (sysinit.c) + 1FE016DC 000000E0 .text init_fpga (sysinit.c) + 1FE017BC 00000028 .text warte_200us (sysinit.c) + 1FE017E4 00000058 .text init_video_ddr (sysinit.c) + 1FE0183C 0000009C .text init_PCI (sysinit.c) + 1FE018D8 0000007C .text test_upd720101 (sysinit.c) + 1FE01954 00000324 .text vdi_on (sysinit.c) + 1FE01C78 0000023C .text init_ac97 (sysinit.c) + 1FE01EB4 00000094 .text __initialize_hardware (sysinit.c) +#>1FE01F48 ___ROM_AT (linker command file) +#>1FE01F48 ___DATA_ROM (linker command file) + +# .data + 00000000 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+ +#>1FE00000 ___Bas_base (linker command file) +#>E0000000 ___BOOT_FLASH (linker command file) +#>00800000 ___BOOT_FLASH_SIZE (linker command file) +#>00000000 ___SDRAM (linker command file) +#>20000000 ___SDRAM_SIZE (linker command file) +#>60000000 ___VRAM (linker command file) +#>FF000000 ___MBAR (linker command file) +#>FF040000 ___MMUBAR (linker command file) +#>FF100000 ___RAMBAR0 (linker command file) +#>00001000 ___RAMBAR0_SIZE (linker command file) +#>FF100FFC ___SUP_SP (linker command file) +#>FF101000 ___RAMBAR1 (linker command file) +#>00001000 ___RAMBAR1_SIZE (linker command file) +#>FF100800 _rt_mod (linker command file) +#>FF100804 _rt_ssp (linker command file) +#>FF100808 _rt_usp (linker command file) +#>FF10080C _rt_vbr (linker command file) +#>FF100810 _rt_cacr (linker command file) +#>FF100814 _rt_asid (linker command file) +#>FF100818 _rt_acr0 (linker command file) +#>FF10081C _rt_acr1 (linker command file) +#>FF100820 _rt_acr2 (linker command file) +#>FF100824 _rt_acr3 (linker command file) +#>FF100828 _rt_mmubar (linker command file) +#>FF10082C _rt_sr (linker command file) +#>FF100830 _d0_save (linker command file) +#>FF100834 _a7_save (linker command file) +#>FF100838 _video_tlb (linker command file) +#>FF10083C _video_sbt (linker command file) +#>FF100844 _rt_mbar (linker command file) +#>FF010000 ___SYS_SRAM (linker command file) +#>00008000 ___SYS_SRAM_SIZE (linker command file) + +# .code + +# .text + E0000000 0000005C .text _startup (startcf.c) + E000005C 0000003C .text init_slt (sysinit.c) + E0000098 00000068 .text init_gpio (sysinit.c) + E0000100 000001C4 .text init_seriel (sysinit.c) + E00002C4 000000F4 .text init_ddram (sysinit.c) + E00003B8 000000DC .text init_fbcs (sysinit.c) + E0000494 00000178 .text init_fpga (sysinit.c) + E000060C 00000058 .text init_video_ddr (sysinit.c) + E0000664 0000009C .text init_PCI (sysinit.c) + E0000700 00000070 .text test_upd720101 (sysinit.c) + E0000770 000003AC .text vdi_on (sysinit.c) + E0000B1C 00000248 .text init_ac97 (sysinit.c) + E0000D64 00000098 .text __initialize_hardware (sysinit.c) + E0000DFC 0000001C .text warte_10ms (BaS.c) + E0000E18 0000001C .text warte_1ms (BaS.c) + E0000E34 0000001C .text warte_100us (BaS.c) + E0000E50 0000001C .text warte_50us (BaS.c) + E0000E6C 0000001C .text warte_10us (BaS.c) + E0000E88 000001FC .text BaS (BaS.c) + E0001084 0000001C .text wait_10ms (sd_card.c) + E00010A0 00000018 .text sd_com (sd_card.c) + E00010B8 00000014 .text sd_get_status (sd_card.c) + E00010CC 00000020 .text sd_rcv_info (sd_card.c) + E00010EC 00000060 .text sd_card_idle (sd_card.c) + E000114C 000004A0 .text sd_card_init (sd_card.c) + E00015EC 000001B0 .text .text (mmu.s) + E00015EC 00000000 .text mmu_init (mmu.s) + E00015EC 000001B0 .text @DummyFn1 (mmu.s) + E0001760 00000000 .text mmutr_miss (mmu.s) + E000179C 000009D4 .text @DummyFn1 (exceptions.s) + E000179C 00000000 .text vec_init (exceptions.s) + E000179C 000009D4 .text .text (exceptions.s) + E0002170 00000000 .text privileg_violation (supervisor.s) + E0002170 000005CA .text .text (supervisor.s) + E00026F2 00000000 .text cpusha (supervisor.s) + E000273C 0000000A .text .text (illegal_instruction.s) + E000273C 0000000A .text @DummyFn3 (illegal_instruction.s) + E0002744 00000000 .text illegal_instruction (illegal_instruction.s) + E0002744 00000000 .text illegal_table_make (illegal_instruction.s) + E0002748 00000004 .text copy_end (last.c) + + +# Memory map: + v_addr p_addr size name + E0000000 E0000000 00000000 .code code + E0000000 E0000000 0000274C .text code + +# Link start time: Sat Aug 14 02:56:27 2010 +# Link end time: Sat Aug 14 02:56:27 2010 diff --git a/BaS_codewarrior/firebeeV1/cfg/DDRAM.cfg b/BaS_codewarrior/firebeeV1/cfg/DDRAM.cfg new file mode 100644 index 0000000..7545850 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/cfg/DDRAM.cfg @@ -0,0 +1,57 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +;writemem.l 0xFF000108 0x73611730; SDCFG1 +writemem.l 0xFF000108 0x53611730; SDCFG1 +;writemem.l 0xFF00010C 0x46770000; SDCFG2 +writemem.l 0xFF00010C 0x24730000; SDCFG2 + +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x04890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x00890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) +writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_codewarrior/firebeeV1/cfg/DDRAM.mem b/BaS_codewarrior/firebeeV1/cfg/DDRAM.mem new file mode 100644 index 0000000..1bc400b --- /dev/null +++ b/BaS_codewarrior/firebeeV1/cfg/DDRAM.mem @@ -0,0 +1,47 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 0x5FFFFFFF + +range 0x60000000 0x7FFFFFFF 4 ReadWrite + +range 0x80000000 0xCFFFFFFF 4 ReadWrite + +range 0xD0000000 0xFBFFFFFF 4 ReadWrite + +reserved 0xFC000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM + +range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF +reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1) + + diff --git a/BaS_codewarrior/firebeeV1/cfg/flash.cfg b/BaS_codewarrior/firebeeV1/cfg/flash.cfg new file mode 100644 index 0000000..cfa2772 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/cfg/flash.cfg @@ -0,0 +1,11 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + + +;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xFE000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + diff --git a/BaS_codewarrior/firebeeV1/cfg/mem.cfg b/BaS_codewarrior/firebeeV1/cfg/mem.cfg new file mode 100644 index 0000000..20830c0 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/cfg/mem.cfg @@ -0,0 +1,48 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00001180; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +writemem.l 0xFF000108 0x53722938; SDCFG1 +writemem.l 0xFF00010C 0x24330000; SDCFG2 + +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +writemem.l 0xFF000100 0x05890000; SDRM (write to LMR) +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh) +writemem.l 0xFF000100 0x01890000; SDMR (write to LMR) +writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_codewarrior/firebeeV1/cfg/mem.mem b/BaS_codewarrior/firebeeV1/cfg/mem.mem new file mode 100644 index 0000000..46bda65 --- /dev/null +++ b/BaS_codewarrior/firebeeV1/cfg/mem.mem @@ -0,0 +1,38 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM +reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF + + $MMUBAR_BASE $MMUBAR_BASE+0x001B +reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 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