initial import after removal of FPGA_quartus
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Markus Fröschle
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vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd
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vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd
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----------------------------------------------------------------------
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---- ----
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---- ATARI MFP compatible IP Core ----
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---- ----
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---- This file is part of the SUSKA ATARI clone project. ----
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---- http://www.experiment-s.de ----
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---- ----
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---- Description: ----
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---- MC68901 compatible multi function port core. ----
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---- ----
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---- This are the SUSKA MFP IP core's general purpose I/Os. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006 - 2011 Wolfgang Foerster ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K6A 2006/06/03 WF
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-- Initial Release.
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-- Revision 2K6B 2006/11/07 WF
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-- Modified Source to compile with the Xilinx ISE.
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-- Revision 2K8A 2008/07/14 WF
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-- Minor changes.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity WF68901IP_GPIO is
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port ( -- System control:
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CLK : in bit;
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RESETn : in bit;
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-- Asynchronous bus control:
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DSn : in bit;
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CSn : in bit;
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RWn : in bit;
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-- Data and Adresses:
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RS : in bit_vector(5 downto 1);
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DATA_IN : in bit_vector(7 downto 0);
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DATA_OUT : out bit_vector(7 downto 0);
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DATA_OUT_EN : out bit;
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-- Timer controls:
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AER_4 : out bit;
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AER_3 : out bit;
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GPIP_IN : in bit_vector(7 downto 0);
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GPIP_OUT : out bit_vector(7 downto 0);
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GPIP_OUT_EN : buffer bit_vector(7 downto 0);
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GP_INT : out bit_vector(7 downto 0)
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);
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end entity WF68901IP_GPIO;
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architecture BEHAVIOR of WF68901IP_GPIO is
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signal GPDR : bit_vector(7 downto 0);
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signal DDR : bit_vector(7 downto 0);
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signal AER : bit_vector(7 downto 0);
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signal GPDR_I : bit_vector(7 downto 0);
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begin
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-- These two bits control the timers A and B pulse width operation and the
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-- timers A and B event count operation.
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AER_4 <= AER(4);
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AER_3 <= AER(3);
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-- This statement provides 8 XOR units setting the desired interrupt polarity.
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-- While the level control is done here, the edge triggering is provided by
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-- the interrupt control hardware. The level control is individually for each
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-- GPIP port pin. The interrupt edge trigger unit must operate in any case on
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-- the low to high transistion of the respective port pin.
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GP_INT <= AER xnor GPIP_IN;
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GPIO_REGISTERS: process(RESETn, CLK)
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begin
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if RESETn = '0' then
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GPDR <= (others => '0');
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DDR <= (others => '0');
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AER <= (others => '0');
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elsif CLK = '1' and CLK' event then
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if CSn = '0' and DSn = '0' and RWn = '0' then
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case RS is
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when "00000" => GPDR <= DATA_IN;
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when "00001" => AER <= DATA_IN;
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when "00010" => DDR <= DATA_IN;
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when others => null;
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end case;
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end if;
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end if;
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end process GPIO_REGISTERS;
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GPIP_OUT <= GPDR; -- Port outputs.
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GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP.
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DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0';
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DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else
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AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else
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GPDR_I when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00000" else (others => '0');
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P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR)
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-- Read back control: Read the port pins, if the data direction is configured as input.
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-- Read the respective GPDR register bit, if the data direction is configured as output.
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begin
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for i in 7 downto 0 loop
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if GPIP_OUT_EN(i) = '1' then -- Port is configured output.
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GPDR_I(i) <= GPDR(i);
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else
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GPDR_I(i) <= GPIP_IN(i); -- Port is configured input.
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end if;
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end loop;
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end process P_GPDR;
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end architecture BEHAVIOR;
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