initial import after removal of FPGA_quartus
This commit is contained in:
Markus Fröschle
174
vhdl/backend/Altera/Firebee/altpll4.mif
Normal file
174
vhdl/backend/Altera/Firebee/altpll4.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2012 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
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||||
-- Device Family: Cyclone III
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||||
-- Device Part: -
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||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
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-- File Name: D:/WF/Projects/VHDL-Designs/Firebee-WF/rtl/vhdl/Firebee_V1//altpll4.mif
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-- Generated: Tue Jul 17 11:06:24 2012
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||||
WIDTH=1;
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||||
DEPTH=144;
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||||
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||||
ADDRESS_RADIX=UNS;
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DATA_RADIX=UNS;
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||||
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||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
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||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
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||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
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||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
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||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
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||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
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||||
37 : 0; -- M counter: High Count = 16 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 1;
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||||
41 : 0;
|
||||
42 : 0;
|
||||
43 : 0;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 16 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 1;
|
||||
50 : 0;
|
||||
51 : 0;
|
||||
52 : 0;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 6 (8 bit(s))
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||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
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60 : 1;
|
||||
61 : 1;
|
||||
62 : 0;
|
||||
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 5 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 0;
|
||||
71 : 1;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
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||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
30
vhdl/backend/Altera/Firebee/firebee.qpf
Executable file
30
vhdl/backend/Altera/Firebee/firebee.qpf
Executable file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 11:04:08 May 31, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
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||||
DATE = "11:04:08 May 31, 2014"
|
||||
|
||||
# Revisions
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||||
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||||
PROJECT_REVISION = "firebee"
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||||
673
vhdl/backend/Altera/Firebee/firebee.qsf
Executable file
673
vhdl/backend/Altera/Firebee/firebee.qsf
Executable file
@@ -0,0 +1,673 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 11:04:08 May 31, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
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||||
#
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||||
# 1) The default values for assignments are stored in the file:
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||||
# firebee_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
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||||
set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C40F484C6
|
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set_global_assignment -name TOP_LEVEL_ENTITY firebee
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||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
|
||||
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ddr_ctlr_tb -section_id eda_simulation
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
set_location_assignment PIN_Y3 -to FB_AD[0]
|
||||
set_location_assignment PIN_Y6 -to FB_AD[1]
|
||||
set_location_assignment PIN_AA3 -to FB_AD[2]
|
||||
set_location_assignment PIN_AB3 -to FB_AD[3]
|
||||
set_location_assignment PIN_W6 -to FB_AD[4]
|
||||
set_location_assignment PIN_V7 -to FB_AD[5]
|
||||
set_location_assignment PIN_AA4 -to FB_AD[6]
|
||||
set_location_assignment PIN_AB4 -to FB_AD[7]
|
||||
set_location_assignment PIN_AA5 -to FB_AD[8]
|
||||
set_location_assignment PIN_AB5 -to FB_AD[9]
|
||||
set_location_assignment PIN_W7 -to FB_AD[10]
|
||||
set_location_assignment PIN_Y7 -to FB_AD[11]
|
||||
set_location_assignment PIN_U9 -to FB_AD[12]
|
||||
set_location_assignment PIN_V8 -to FB_AD[13]
|
||||
set_location_assignment PIN_W8 -to FB_AD[14]
|
||||
set_location_assignment PIN_AA7 -to FB_AD[15]
|
||||
set_location_assignment PIN_AB7 -to FB_AD[16]
|
||||
set_location_assignment PIN_Y8 -to FB_AD[17]
|
||||
set_location_assignment PIN_V9 -to FB_AD[18]
|
||||
set_location_assignment PIN_V10 -to FB_AD[19]
|
||||
set_location_assignment PIN_T10 -to FB_AD[20]
|
||||
set_location_assignment PIN_U10 -to FB_AD[21]
|
||||
set_location_assignment PIN_AA8 -to FB_AD[22]
|
||||
set_location_assignment PIN_AB8 -to FB_AD[23]
|
||||
set_location_assignment PIN_T11 -to FB_AD[24]
|
||||
set_location_assignment PIN_AA9 -to FB_AD[25]
|
||||
set_location_assignment PIN_AB9 -to FB_AD[26]
|
||||
set_location_assignment PIN_U11 -to FB_AD[27]
|
||||
set_location_assignment PIN_V11 -to FB_AD[28]
|
||||
set_location_assignment PIN_W10 -to FB_AD[29]
|
||||
set_location_assignment PIN_Y10 -to FB_AD[30]
|
||||
set_location_assignment PIN_AA10 -to FB_AD[31]
|
||||
set_location_assignment PIN_R7 -to FB_ALE
|
||||
set_location_assignment PIN_N19 -to LED_FPGA_OK
|
||||
set_location_assignment PIN_R5 -to TIN0
|
||||
set_location_assignment PIN_W20 -to VA[0]
|
||||
set_location_assignment PIN_W22 -to VA[1]
|
||||
set_location_assignment PIN_W21 -to VA[2]
|
||||
set_location_assignment PIN_Y22 -to VA[3]
|
||||
set_location_assignment PIN_AA22 -to VA[4]
|
||||
set_location_assignment PIN_Y21 -to VA[5]
|
||||
set_location_assignment PIN_AA21 -to VA[6]
|
||||
set_location_assignment PIN_AA20 -to VA[7]
|
||||
set_location_assignment PIN_AB20 -to VA[8]
|
||||
set_location_assignment PIN_AB19 -to VA[9]
|
||||
set_location_assignment PIN_V21 -to VA[10]
|
||||
set_location_assignment PIN_U19 -to VA[11]
|
||||
set_location_assignment PIN_AA18 -to VA[12]
|
||||
set_location_assignment PIN_U15 -to VCKE
|
||||
set_location_assignment PIN_M22 -to VD[0]
|
||||
set_location_assignment PIN_M21 -to VD[1]
|
||||
set_location_assignment PIN_P22 -to VD[2]
|
||||
set_location_assignment PIN_R20 -to VD[3]
|
||||
set_location_assignment PIN_P21 -to VD[4]
|
||||
set_location_assignment PIN_R17 -to VD[5]
|
||||
set_location_assignment PIN_R19 -to VD[6]
|
||||
set_location_assignment PIN_U21 -to VD[7]
|
||||
set_location_assignment PIN_V22 -to VD[8]
|
||||
set_location_assignment PIN_R18 -to VD[9]
|
||||
set_location_assignment PIN_P17 -to VD[10]
|
||||
set_location_assignment PIN_R21 -to VD[11]
|
||||
set_location_assignment PIN_N17 -to VD[12]
|
||||
set_location_assignment PIN_P20 -to VD[13]
|
||||
set_location_assignment PIN_R22 -to VD[14]
|
||||
set_location_assignment PIN_N20 -to VD[15]
|
||||
set_location_assignment PIN_T12 -to VD[16]
|
||||
set_location_assignment PIN_Y13 -to VD[17]
|
||||
set_location_assignment PIN_AA13 -to VD[18]
|
||||
set_location_assignment PIN_V14 -to VD[19]
|
||||
set_location_assignment PIN_U13 -to VD[20]
|
||||
set_location_assignment PIN_V15 -to VD[21]
|
||||
set_location_assignment PIN_W14 -to VD[22]
|
||||
set_location_assignment PIN_AB16 -to VD[23]
|
||||
set_location_assignment PIN_AB15 -to VD[24]
|
||||
set_location_assignment PIN_AA14 -to VD[25]
|
||||
set_location_assignment PIN_AB14 -to VD[26]
|
||||
set_location_assignment PIN_V13 -to VD[27]
|
||||
set_location_assignment PIN_W13 -to VD[28]
|
||||
set_location_assignment PIN_AB13 -to VD[29]
|
||||
set_location_assignment PIN_V12 -to VD[30]
|
||||
set_location_assignment PIN_U12 -to VD[31]
|
||||
set_location_assignment PIN_AA16 -to VDM[0]
|
||||
set_location_assignment PIN_V16 -to VDM[1]
|
||||
set_location_assignment PIN_U20 -to VDM[2]
|
||||
set_location_assignment PIN_T17 -to VDM[3]
|
||||
set_location_assignment PIN_G18 -to VB[0]
|
||||
set_location_assignment PIN_H17 -to VB[1]
|
||||
set_location_assignment PIN_C22 -to VB[2]
|
||||
set_location_assignment PIN_C21 -to VB[3]
|
||||
set_location_assignment PIN_B22 -to VB[4]
|
||||
set_location_assignment PIN_B21 -to VB[5]
|
||||
set_location_assignment PIN_C20 -to VB[6]
|
||||
set_location_assignment PIN_D20 -to VB[7]
|
||||
set_location_assignment PIN_H19 -to VG[0]
|
||||
set_location_assignment PIN_E22 -to VG[1]
|
||||
set_location_assignment PIN_E21 -to VG[2]
|
||||
set_location_assignment PIN_H18 -to VG[3]
|
||||
set_location_assignment PIN_J17 -to VG[4]
|
||||
set_location_assignment PIN_H16 -to VG[5]
|
||||
set_location_assignment PIN_D22 -to VG[6]
|
||||
set_location_assignment PIN_D21 -to VG[7]
|
||||
set_location_assignment PIN_J22 -to VR[0]
|
||||
set_location_assignment PIN_J21 -to VR[1]
|
||||
set_location_assignment PIN_H22 -to VR[2]
|
||||
set_location_assignment PIN_H21 -to VR[3]
|
||||
set_location_assignment PIN_K17 -to VR[4]
|
||||
set_location_assignment PIN_K18 -to VR[5]
|
||||
set_location_assignment PIN_J18 -to VR[6]
|
||||
set_location_assignment PIN_F22 -to VR[7]
|
||||
set_location_assignment PIN_M6 -to ACSI_A1
|
||||
set_location_assignment PIN_B1 -to ACSI_D[0]
|
||||
set_location_assignment PIN_G5 -to ACSI_D[1]
|
||||
set_location_assignment PIN_E3 -to ACSI_D[2]
|
||||
set_location_assignment PIN_C2 -to ACSI_D[3]
|
||||
set_location_assignment PIN_C1 -to ACSI_D[4]
|
||||
set_location_assignment PIN_D2 -to ACSI_D[5]
|
||||
set_location_assignment PIN_H7 -to ACSI_D[6]
|
||||
set_location_assignment PIN_H6 -to ACSI_D[7]
|
||||
set_location_assignment PIN_L6 -to ACSI_DIR
|
||||
set_location_assignment PIN_N1 -to AMKB_TX
|
||||
set_location_assignment PIN_F15 -to DSA_D
|
||||
set_location_assignment PIN_D15 -to DTR
|
||||
set_location_assignment PIN_A11 -to DVI_INT
|
||||
set_location_assignment PIN_G21 -to E0_INT
|
||||
set_location_assignment PIN_M5 -to IDE_RES
|
||||
set_location_assignment PIN_F7 -to LP_D[0]
|
||||
set_location_assignment PIN_C4 -to LP_D[1]
|
||||
set_location_assignment PIN_C3 -to LP_D[2]
|
||||
set_location_assignment PIN_E7 -to LP_D[3]
|
||||
set_location_assignment PIN_D6 -to LP_D[4]
|
||||
set_location_assignment PIN_B3 -to LP_D[5]
|
||||
set_location_assignment PIN_A3 -to LP_D[6]
|
||||
set_location_assignment PIN_G8 -to LP_D[7]
|
||||
set_location_assignment PIN_E6 -to LP_STR
|
||||
set_location_assignment PIN_H5 -to MIDI_OLR
|
||||
set_location_assignment PIN_B2 -to MIDI_TLR
|
||||
set_location_assignment PIN_AA2 -to PIC_INT
|
||||
set_location_assignment PIN_B18 -to RTS
|
||||
set_location_assignment PIN_J6 -to SCSI_D[0]
|
||||
set_location_assignment PIN_E1 -to SCSI_D[1]
|
||||
set_location_assignment PIN_F2 -to SCSI_D[2]
|
||||
set_location_assignment PIN_F1 -to SCSI_D[3]
|
||||
set_location_assignment PIN_G4 -to SCSI_D[4]
|
||||
set_location_assignment PIN_G3 -to SCSI_D[5]
|
||||
set_location_assignment PIN_L8 -to SCSI_D[6]
|
||||
set_location_assignment PIN_K8 -to SCSI_D[7]
|
||||
set_location_assignment PIN_J7 -to SCSI_DIR
|
||||
set_location_assignment PIN_M7 -to SCSI_PAR
|
||||
set_location_assignment PIN_C15 -to SD_CLK
|
||||
set_location_assignment PIN_E14 -to SD_CMD_D1
|
||||
set_location_assignment PIN_A18 -to TxD
|
||||
set_location_assignment PIN_A17 -to YM_QA
|
||||
set_location_assignment PIN_G13 -to YM_QB
|
||||
set_location_assignment PIN_E15 -to YM_QC
|
||||
set_location_assignment PIN_M19 -to SD_WP
|
||||
set_location_assignment PIN_H15 -to RxD
|
||||
set_location_assignment PIN_B19 -to RI
|
||||
set_location_assignment PIN_L7 -to PIC_AMKB_RX
|
||||
set_location_assignment PIN_E12 -to MIDI_IN
|
||||
set_location_assignment PIN_G7 -to LP_BUSY
|
||||
set_location_assignment PIN_Y1 -to IDE_RDY
|
||||
set_location_assignment PIN_G22 -to IDE_INT
|
||||
set_location_assignment PIN_A19 -to DCD
|
||||
set_location_assignment PIN_H14 -to CTS
|
||||
set_location_assignment PIN_Y2 -to AMKB_RX
|
||||
set_location_assignment PIN_W19 -to BA[0]
|
||||
set_location_assignment PIN_AA19 -to BA[1]
|
||||
|
||||
set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK" -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[0]" -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[1]" -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[2]" -section_id fast
|
||||
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[3]" -section_id fast
|
||||
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK"
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[0]"
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[1]"
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[2]"
|
||||
set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[3]"
|
||||
set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
|
||||
set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
|
||||
set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
|
||||
set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
|
||||
set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[16]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[17]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[18]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[19]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[20]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[21]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[22]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[23]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[24]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[25]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[26]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[27]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[28]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[29]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[30]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[31]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[0]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[1]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[2]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[3]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[0]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[1]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[2]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[3]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[4]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[5]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[6]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[7]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[8]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[9]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[10]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[11]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[12]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[13]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[14]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[15]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[16]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[17]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[18]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[19]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[20]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[21]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[22]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[23]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[24]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[25]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[26]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[27]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[28]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[29]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[30]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[31]
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS ON
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION ON
|
||||
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.5
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_location_assignment PIN_AB12 -to CLK_33M
|
||||
set_location_assignment PIN_G2 -to CLK_MAIN
|
||||
set_location_assignment PIN_AB10 -to CLK_24M576
|
||||
set_location_assignment PIN_J1 -to CLK_USB
|
||||
set_location_assignment PIN_T4 -to CLK_25M
|
||||
set_location_assignment PIN_U8 -to FB_SIZE[0]
|
||||
set_location_assignment PIN_Y4 -to FB_SIZE[1]
|
||||
set_location_assignment PIN_T3 -to FB_BURSTn
|
||||
set_location_assignment PIN_T8 -to FB_CSn[1]
|
||||
set_location_assignment PIN_T9 -to FB_CSn[2]
|
||||
set_location_assignment PIN_V6 -to FB_CSn[3]
|
||||
set_location_assignment PIN_R6 -to FB_OEn
|
||||
set_location_assignment PIN_G14 -to FB_WRn
|
||||
set_location_assignment PIN_T21 -to MASTERn
|
||||
set_location_assignment PIN_E11 -to DREQ1n
|
||||
set_location_assignment PIN_A12 -to DACK1n
|
||||
set_location_assignment PIN_B12 -to DACK0n
|
||||
set_location_assignment PIN_T22 -to TOUT0n
|
||||
set_location_assignment PIN_AA17 -to CLK_DDR_OUT
|
||||
set_location_assignment PIN_AB17 -to CLK_DDR_OUTn
|
||||
set_location_assignment PIN_AB18 -to VCASn
|
||||
set_location_assignment PIN_T18 -to VCSn
|
||||
set_location_assignment PIN_W17 -to VRASn
|
||||
set_location_assignment PIN_Y17 -to VWEn
|
||||
set_location_assignment PIN_AA15 -to VD_QS[0]
|
||||
set_location_assignment PIN_W15 -to VD_QS[1]
|
||||
set_location_assignment PIN_U22 -to VD_QS[2]
|
||||
set_location_assignment PIN_T16 -to VD_QS[3]
|
||||
set_location_assignment PIN_V1 -to PD_VGAn
|
||||
set_location_assignment PIN_A8 -to DSP_IO[0]
|
||||
set_location_assignment PIN_A7 -to DSP_IO[1]
|
||||
set_location_assignment PIN_B7 -to DSP_IO[2]
|
||||
set_location_assignment PIN_A6 -to DSP_IO[3]
|
||||
set_location_assignment PIN_B6 -to DSP_IO[4]
|
||||
set_location_assignment PIN_E9 -to DSP_IO[5]
|
||||
set_location_assignment PIN_C8 -to DSP_IO[6]
|
||||
set_location_assignment PIN_C7 -to DSP_IO[7]
|
||||
set_location_assignment PIN_G10 -to DSP_IO[8]
|
||||
set_location_assignment PIN_A15 -to DSP_IO[9]
|
||||
set_location_assignment PIN_B15 -to DSP_IO[10]
|
||||
set_location_assignment PIN_C13 -to DSP_IO[11]
|
||||
set_location_assignment PIN_D13 -to DSP_IO[12]
|
||||
set_location_assignment PIN_E13 -to DSP_IO[13]
|
||||
set_location_assignment PIN_A14 -to DSP_IO[14]
|
||||
set_location_assignment PIN_B14 -to DSP_IO[15]
|
||||
set_location_assignment PIN_A13 -to DSP_IO[16]
|
||||
set_location_assignment PIN_B13 -to DSP_IO[17]
|
||||
set_location_assignment PIN_M4 -to ACSI_ACKn
|
||||
set_location_assignment PIN_M2 -to ACSI_CSn
|
||||
set_location_assignment PIN_M1 -to ACSI_RESETn
|
||||
set_location_assignment PIN_W2 -to CF_CSn[0]
|
||||
set_location_assignment PIN_W1 -to CF_CSn[1]
|
||||
set_location_assignment PIN_T7 -to FB_TAn
|
||||
set_location_assignment PIN_R2 -to IDE_CSn[0]
|
||||
set_location_assignment PIN_R1 -to IDE_CSn[1]
|
||||
set_location_assignment PIN_P1 -to IDE_RDn
|
||||
set_location_assignment PIN_P2 -to IDE_WRn
|
||||
set_location_assignment PIN_F21 -to IRQn[2]
|
||||
set_location_assignment PIN_H20 -to IRQn[3]
|
||||
set_location_assignment PIN_F20 -to IRQn[4]
|
||||
set_location_assignment PIN_P5 -to IRQn[5]
|
||||
set_location_assignment PIN_P7 -to IRQn[6]
|
||||
set_location_assignment PIN_N7 -to IRQn[7]
|
||||
set_location_assignment PIN_AA1 -to PCI_INTAn
|
||||
set_location_assignment PIN_V4 -to PCI_INTBn
|
||||
set_location_assignment PIN_V3 -to PCI_INTCn
|
||||
set_location_assignment PIN_P6 -to PCI_INTDn
|
||||
set_location_assignment PIN_P3 -to ROM3n
|
||||
set_location_assignment PIN_U2 -to ROM4n
|
||||
set_location_assignment PIN_N5 -to RP_LDSn
|
||||
set_location_assignment PIN_P4 -to RP_UDSn
|
||||
set_location_assignment PIN_N2 -to SCSI_ACKn
|
||||
set_location_assignment PIN_M3 -to SCSI_ATNn
|
||||
set_location_assignment PIN_N8 -to SCSI_BUSYn
|
||||
set_location_assignment PIN_N6 -to SCSI_RSTn
|
||||
set_location_assignment PIN_M8 -to SCSI_SELn
|
||||
set_location_assignment PIN_B20 -to FDD_SDSELn
|
||||
set_location_assignment PIN_B4 -to DSP_SRBHEn
|
||||
set_location_assignment PIN_A4 -to DSP_SRBLEn
|
||||
set_location_assignment PIN_B8 -to DSP_SRCSn
|
||||
set_location_assignment PIN_F11 -to DSP_SROEn
|
||||
set_location_assignment PIN_F8 -to DSP_SRWEn
|
||||
set_location_assignment PIN_D17 -to FDD_WR_GATE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS[3]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD_QS[0]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD_QS[1]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD_QS[2]
|
||||
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD_QS[3]
|
||||
set_instance_assignment -name CKN_CK_PAIR ON -from CLK_DDR_OUTn -to CLK_DDR_OUT
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to ACSI_DRQn
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to ACSI_INTn
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DETECT
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D2
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D1
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D0
|
||||
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D3
|
||||
set_location_assignment PIN_J4 -to ACSI_INTn
|
||||
set_location_assignment PIN_K7 -to ACSI_DRQn
|
||||
set_location_assignment PIN_F16 -to FDD_HD_DD
|
||||
set_location_assignment PIN_E16 -to FDD_INDEXn
|
||||
set_location_assignment PIN_K21 -to HSYNC
|
||||
set_location_assignment PIN_K19 -to VSYNC
|
||||
set_location_assignment PIN_G17 -to BLANKn
|
||||
set_location_assignment PIN_F19 -to CLK_PIXEL
|
||||
set_location_assignment PIN_F17 -to SYNCn
|
||||
set_location_assignment PIN_G15 -to FDD_STEP_DIR
|
||||
set_location_assignment PIN_F14 -to FDD_STEP
|
||||
set_location_assignment PIN_G16 -to FDD_MOT_ON
|
||||
set_location_assignment PIN_E5 -to LP_DIR
|
||||
set_location_assignment PIN_B11 -to RSTO_MCFn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD_QS
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VWEn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VRASn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCSn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCASn
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to CLK_PIXEL
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to BLANKn
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SYNCn
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQn[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQn[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQn[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCSn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VWEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VRASn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCASn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to CLK_PIXEL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to BLANKn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to PD_VGAn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SYNCn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SRD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_IO
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SRWEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SROEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SRCSn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SRBLEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DSP_SRBHEn
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK_24M576
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK_USB
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK_25M
|
||||
set_location_assignment PIN_F13 -to SD_D3
|
||||
set_location_assignment PIN_A5 -to DSP_SRD[1]
|
||||
set_location_assignment PIN_C6 -to DSP_SRD[2]
|
||||
set_location_assignment PIN_G11 -to DSP_SRD[3]
|
||||
set_location_assignment PIN_C10 -to DSP_SRD[4]
|
||||
set_location_assignment PIN_F9 -to DSP_SRD[5]
|
||||
set_location_assignment PIN_E10 -to DSP_SRD[6]
|
||||
set_location_assignment PIN_H11 -to DSP_SRD[7]
|
||||
set_location_assignment PIN_B9 -to DSP_SRD[8]
|
||||
set_location_assignment PIN_A10 -to DSP_SRD[9]
|
||||
set_location_assignment PIN_A9 -to DSP_SRD[10]
|
||||
set_location_assignment PIN_B10 -to DSP_SRD[11]
|
||||
set_location_assignment PIN_D10 -to DSP_SRD[12]
|
||||
set_location_assignment PIN_F10 -to DSP_SRD[13]
|
||||
set_location_assignment PIN_G9 -to DSP_SRD[14]
|
||||
set_location_assignment PIN_H10 -to DSP_SRD[15]
|
||||
set_location_assignment PIN_B17 -to SD_D2
|
||||
set_location_assignment PIN_A16 -to SD_D1
|
||||
set_location_assignment PIN_B16 -to SD_D0
|
||||
set_location_assignment PIN_M20 -to SD_CARD_DETECT
|
||||
set_location_assignment PIN_A20 -to FDD_RDn
|
||||
set_location_assignment PIN_B5 -to DSP_SRD[0]
|
||||
set_location_assignment PIN_T1 -to CF_WP
|
||||
set_location_assignment PIN_C19 -to FDD_TRACK00
|
||||
set_location_assignment PIN_C17 -to FDD_DCHGn
|
||||
set_location_assignment PIN_D19 -to FDD_WPn
|
||||
set_location_assignment PIN_H2 -to SCSI_MSGn
|
||||
set_location_assignment PIN_J3 -to SCSI_IOn
|
||||
set_location_assignment PIN_U1 -to SCSI_DRQn
|
||||
set_location_assignment PIN_H1 -to SCSI_CDn
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
|
||||
|
||||
set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation
|
||||
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id ddr_ctlr_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr_ctlr_tb -section_id ddr_ctlr_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[1]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[2]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[3]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll2:I_PLL2|altpll:altpll_component|clk[0]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll2:I_PLL2|altpll:altpll_component|clk[1]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll2:I_PLL2|altpll:altpll_component|clk[2]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll2:I_PLL2|altpll:altpll_component|clk[3]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll3:I_PLL3|altpll:altpll_component|clk[0]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll3:I_PLL3|altpll:altpll_component|clk[1]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll3:I_PLL3|altpll:altpll_component|clk[2]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll3:I_PLL3|altpll:altpll_component|clk[3]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[0]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[1]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[2]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[3]"
|
||||
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[0]"
|
||||
set_global_assignment -name SDC_FILE firebee.sdc
|
||||
set_global_assignment -name SOURCE_FILE firebee.qsf
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/Video_Top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/RTC/rtc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_soc_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_registers.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF5380/wf5380_control.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_transmit.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_receive.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_registers.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_FDC1772_IP/wf1772ip_am_detector.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_wave.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/WF_SND2149_IP/wf2149ip_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DSP/DSP.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/fbee_dma.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Blitter/Blitter_WF.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Interrupt/interrupt.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/VIDEO_CTRL.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DMA/dcfifo0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.vhd
|
||||
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifoDZ.cmp
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.vhd
|
||||
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Video/lpm_fifo_dc0.cmp
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll4.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll3.vhd
|
||||
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll3.cmp
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll2.vhd
|
||||
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll2.cmp
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd
|
||||
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
|
||||
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
868
vhdl/backend/Altera/Firebee/firebee.sdc
Executable file
868
vhdl/backend/Altera/Firebee/firebee.sdc
Executable file
@@ -0,0 +1,868 @@
|
||||
## Generated SDC file "firebee.sdc"
|
||||
|
||||
## Copyright (C) 1991-2013 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
|
||||
|
||||
## DATE "Mon Jun 9 15:23:23 2014"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C40F484C6"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {CLK_MAIN} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK_MAIN}]
|
||||
create_clock -name {CLK_33M} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK_33M}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]} -source [get_pins {I_PLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 215 -master_clock {CLK_MAIN} [get_pins {I_PLL1|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[1]} -source [get_pins {I_PLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 32 -divide_by 43 -master_clock {CLK_MAIN} [get_pins {I_PLL1|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
create_generated_clock -name {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[2]} -source [get_pins {I_PLL1|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 16 -divide_by 11 -master_clock {CLK_MAIN} [get_pins {I_PLL1|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
create_generated_clock -name {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]} -source [get_pins {I_PLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 97 -divide_by 1600 -master_clock {CLK_MAIN} [get_pins {I_PLL3|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]} -source [get_pins {I_PLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 97 -divide_by 200 -master_clock {CLK_MAIN} [get_pins {I_PLL3|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
create_generated_clock -name {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]} -source [get_pins {I_PLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 97 -divide_by 128 -master_clock {CLK_MAIN} [get_pins {I_PLL3|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
create_generated_clock -name {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]} -source [get_pins {I_PLL3|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 97 -divide_by 6416 -master_clock {CLK_MAIN} [get_pins {I_PLL3|altpll_component|auto_generated|pll1|clk[3]}]
|
||||
create_generated_clock -name {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]} -source [get_pins {I_PLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 240.000 -master_clock {CLK_MAIN} [get_pins {I_PLL2|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
create_generated_clock -name {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]} -source [get_pins {I_PLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {CLK_MAIN} [get_pins {I_PLL2|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
create_generated_clock -name {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]} -source [get_pins {I_PLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 180.000 -master_clock {CLK_MAIN} [get_pins {I_PLL2|altpll_component|auto_generated|pll1|clk[2]}]
|
||||
create_generated_clock -name {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]} -source [get_pins {I_PLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 105.000 -master_clock {CLK_MAIN} [get_pins {I_PLL2|altpll_component|auto_generated|pll1|clk[3]}]
|
||||
create_generated_clock -name {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]} -source [get_pins {I_PLL2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -phase 270.000 -master_clock {CLK_MAIN} [get_pins {I_PLL2|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
create_generated_clock -name {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]} -source [get_pins {I_PLL4|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 32 -divide_by 11 -master_clock {CLK_MAIN} [get_pins {I_PLL4|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_33M}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_33M}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {CLK_MAIN}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {CLK_MAIN}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_33M}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {CLK_MAIN}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {CLK_MAIN}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -setup 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -hold 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {CLK_MAIN}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.030
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.030
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.160
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.160
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.030
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.030
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.160
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.160
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[1]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -setup 0.110
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_33M}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[4]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[2]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[3]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -hold 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.150
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.030
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.030
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] -hold 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll2:I_PLL2|altpll:altpll_component|altpll_da13:auto_generated|clk[0]}] 0.150
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.030
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2]}] 0.030
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -setup 0.100
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] -hold 0.070
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -rise_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] -fall_to [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[1]}] 0.020
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[2]}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[2]}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[1]}] -rise_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[1]}] -fall_to [get_clocks {CLK_33M}] 0.040
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.090
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -rise_to [get_clocks {CLK_MAIN}] -hold 0.090
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -setup 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {altpll1:I_PLL1|altpll:altpll_component|altpll_dnn2:auto_generated|clk[0]}] -fall_to [get_clocks {CLK_MAIN}] -hold 0.090
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_DRQn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_INTn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {AMKB_RX}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CF_WP}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_33M}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_MAIN}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CTS}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DACK0n}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DACK1n}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DCD}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[8]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[9]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[10]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[11]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[12]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[13]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[14]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[15]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[16]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[17]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[8]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[9]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[10]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[11]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[12]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[13]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[14]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[15]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DVI_INT}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {E0_INT}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[8]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[9]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[10]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[11]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[12]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[13]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[14]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[15]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[16]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[17]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[18]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[19]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[20]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[21]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[22]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[23]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[24]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[25]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[26]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[27]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[28]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[29]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[30]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[31]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_ALE}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_BURSTn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_CSn[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_CSn[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_CSn[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_OEn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_SIZE[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_SIZE[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_WRn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_DCHGn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_HD_DD}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_INDEXn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_RDn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_TRACK00}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_WPn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_INT}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_RDY}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_BUSY}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {MASTERn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {MIDI_IN}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PCI_INTAn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PCI_INTBn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PCI_INTCn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PCI_INTDn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PIC_AMKB_RX}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PIC_INT}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RI}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RSTO_MCFn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RxD}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_BUSYn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_CDn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_DRQn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_IOn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_MSGn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_PAR}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_RSTn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_SELn}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_CARD_DETECT}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_CMD_D1}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_D0}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_D1}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_D2}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_D3}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_WP}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {TOUT0n}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[0]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[1]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[2]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[3]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[4]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[5]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[6]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[7]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[8]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[9]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[10]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[11]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[12]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[13]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[14]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[15]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[16]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[17]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[18]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[19]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[20]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[21]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[22]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[23]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[24]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[25]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[26]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[27]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[28]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[29]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[30]}]
|
||||
set_input_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[31]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_A1}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_ACKn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_CSn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_DIR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_D[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ACSI_RESETn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {AMKB_TX}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {BA[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {BA[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {BLANKn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CF_CSn[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CF_CSn[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_24M576}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_25M}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_DDR_OUT}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_DDR_OUTn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_PIXEL}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {CLK_USB}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DREQ1n}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSA_D}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[8]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[9]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[10]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[11]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[12]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[13]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[14]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[15]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[16]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_IO[17]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRBHEn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRBLEn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRCSn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[8]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[9]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[10]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[11]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[12]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[13]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[14]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRD[15]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SROEn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DSP_SRWEn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {DTR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[8]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[9]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[10]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[11]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[12]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[13]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[14]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[15]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[16]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[17]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[18]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[19]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[20]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[21]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[22]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[23]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[24]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[25]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[26]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[27]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[28]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[29]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[30]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_AD[31]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FB_TAn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_MOT_ON}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_SDSELn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_STEP}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_STEP_DIR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_WDn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {FDD_WR_GATE}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {HSYNC}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_CSn[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_CSn[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_RDn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_RES}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IDE_WRn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {IRQn[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LED_FPGA_OK}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_DIR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_D[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {LP_STR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {MIDI_OLR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {MIDI_TLR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {PD_VGAn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RESERVED_1}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ROM3n}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {ROM4n}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RP_LDSn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RP_UDSn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {RTS}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_ACKn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_ATNn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_BUSYn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_DIR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_D[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_PAR}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_RSTn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SCSI_SELn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_CLK}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_CMD_D1}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SD_D3}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {SYNCn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {TIN0}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {TxD}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[8]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[9]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[10]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[11]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VA[12]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VB[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VCASn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VCKE}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VCSn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VDM[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VDM[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VDM[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VDM[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[8]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[9]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[10]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[11]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[12]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[13]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[14]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[15]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[16]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[17]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[18]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[19]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[20]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[21]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[22]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[23]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[24]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[25]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[26]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[27]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[28]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[29]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[30]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD[31]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD_QS[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD_QS[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD_QS[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VD_QS[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VG[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VRASn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[0]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[1]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[2]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[3]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[4]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[5]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[6]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VR[7]}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VSYNC}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {VWEn}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {YM_QA}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {YM_QB}]
|
||||
set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports {YM_QC}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
|
||||
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
|
||||
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
|
||||
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
|
||||
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
|
||||
set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
|
||||
set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
692
vhdl/backend/Altera/Firebee/firebee_assignment_defaults.qdf
Normal file
692
vhdl/backend/Altera/Firebee/firebee_assignment_defaults.qdf
Normal file
@@ -0,0 +1,692 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 21:25:10 June 05, 2014
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus II software and is used
|
||||
# to preserve global assignments across Quartus II versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name SMART_RECOMPILE Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name REVISION_TYPE Base
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone IV GX"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name SYNTHESIS_SEED 1
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN On
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name VREF_MODE EXTERNAL
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS Off
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
Reference in New Issue
Block a user