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Markus Fröschle
2013-08-02 22:12:26 +00:00
parent 8fbc2c9dba
commit 6ef41225b0
1 changed files with 13 additions and 13 deletions
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26
BaS_gcc/sources/mmu.S
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@@ -183,19 +183,19 @@ _mmu_init:
rts rts
/* /*
* MMU table search * MMU table add on miss
*/ */
_mmutr_miss: _mmutr_miss:
bsr cpusha bsr cpusha // clear caches
and.l #0xFFF00000,d0 and.l #0xFFF00000,d0 // d0 is the address not found (MMUAR at the time of the exception)
or.l #std_mmutr,d0 or.l #std_mmutr,d0 // mark shared and valid
move.l d0,MCF_MMU_MMUTR move.l d0,MCF_MMU_MMUTR // add to TLB
and.l #0xFFF00000,d0 and.l #0xFFF00000,d0 // mask out page
or.l #copyback_mmudr,d0 or.l #copyback_mmudr,d0 // 1MB page size, cachable copyback, read, write, execute
move.l d0,MCF_MMU_MMUDR move.l d0,MCF_MMU_MMUDR // add to TLB
moveq.l #mmuord_d,d0 // MMU update data moveq.l #mmuord_d,d0 // MMU update data
move.l d0,MCF_MMU_MMUOR // set move.l d0,MCF_MMU_MMUOR // set
moveq.l #mmuord_i,d0 // MMU update instruction moveq.l #mmuord_i,d0 // MMU update instruction
move.l d0,MCF_MMU_MMUOR // set move.l d0,MCF_MMU_MMUOR // set
move.l (sp)+,d0 move.l (sp)+,d0 // restore register saved in acess
rte rte