removed debug printout
incorporated EmuTOS byte swap routines for PCI access
This commit is contained in:
@@ -85,9 +85,11 @@ void init_fpga(void)
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uint8_t *fpga_data;
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uint8_t *fpga_data;
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int i;
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int i;
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/*
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xprintf("MCF_FBCS0_CSAR: %08x\r\n", MCF_FBCS0_CSAR);
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xprintf("MCF_FBCS0_CSAR: %08x\r\n", MCF_FBCS0_CSAR);
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xprintf("MCF_FBCS0_CSCR: %08x\r\n", MCF_FBCS0_CSCR);
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xprintf("MCF_FBCS0_CSCR: %08x\r\n", MCF_FBCS0_CSCR);
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xprintf("MCF_FBCS0_CSMR: %08x\r\n", MCF_FBCS0_CSMR);
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xprintf("MCF_FBCS0_CSMR: %08x\r\n", MCF_FBCS0_CSMR);
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*/
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xprintf("FPGA load config... ");
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xprintf("FPGA load config... ");
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@@ -39,7 +39,7 @@
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
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/*MCF_DSPI_DCTAR_PBR_1CLK | */ /* 3 clock baudrate prescaler */ \
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MCF_DSPI_DCTAR_PBR_1CLK | /* 3 clock baudrate prescaler */ \
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MCF_DSPI_DCTAR_CSSCK(1) | /* delay scaler * 4 */\
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MCF_DSPI_DCTAR_CSSCK(1) | /* delay scaler * 4 */\
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MCF_DSPI_DCTAR_ASC(0b0001) | /* 2 */ \
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MCF_DSPI_DCTAR_ASC(0b0001) | /* 2 */ \
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MCF_DSPI_DCTAR_DT(0b0010) | /* 2 */ \
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MCF_DSPI_DCTAR_DT(0b0010) | /* 2 */ \
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@@ -459,11 +459,13 @@ DSTATUS disk_initialize(uint8_t drv)
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CardType = card_type; /* Card type */
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CardType = card_type; /* Card type */
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res = disk_ioctl(0, MMC_GET_CSD, buff);
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res = disk_ioctl(0, MMC_GET_CSD, buff);
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/*
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if (res == RES_OK)
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if (res == RES_OK)
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{
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{
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xprintf("CSD of card:\r\n");
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xprintf("CSD of card:\r\n");
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hexdump(buff, 16);
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hexdump(buff, 16);
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}
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}
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*/
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deselect();
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deselect();
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if (card_type)
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if (card_type)
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@@ -474,11 +476,13 @@ DSTATUS disk_initialize(uint8_t drv)
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Stat &= ~STA_NOINIT; /* Clear STA_NOINIT flag */
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Stat &= ~STA_NOINIT; /* Clear STA_NOINIT flag */
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xprintf("card type: %d\r\n", card_type);
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xprintf("card type: %d\r\n", card_type);
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res = disk_ioctl(0, MMC_GET_CSD, buff);
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res = disk_ioctl(0, MMC_GET_CSD, buff);
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/*
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if (res == RES_OK)
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if (res == RES_OK)
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{
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{
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xprintf("CSD of card now:\r\n");
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xprintf("CSD of card now:\r\n");
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hexdump(buff, 16);
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hexdump(buff, 16);
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}
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}
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*/
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deselect();
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deselect();
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}
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}
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@@ -30,15 +30,82 @@
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#include "bas_printf.h"
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#include "bas_printf.h"
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#include "util.h"
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#include "util.h"
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uint32_t pci_read_config_longword(uint16_t slot, uint16_t function, uint16_t offset)
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uint16_t pci_read_config_word(uint16_t slot, uint16_t function, uint16_t offset)
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{
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{
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return 0;
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uint16_t value;
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/* initiate PCI configuration access to device */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
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MCF_PCI_PCICAR_DEVNUM(slot + 10) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset);
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value = * (volatile uint16_t *) PCI_IO_OFFSET; /* access device */
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/* finish config cycle */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_DEVNUM(slot + 10) |
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MCF_PCI_PCICAR_FUNCNUM(function) |
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MCF_PCI_PCICAR_DWORD(0);
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swpw(value);
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return value;
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}
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}
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uint16_t pci_read_config_word(uint16_t slot, uint16_t function, uint16_t offset)
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uint32_t pci_read_config_longword(uint16_t bus, uint16_t slot, uint16_t function, uint16_t offset)
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{
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{
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return 0;
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uint32_t value;
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/* initiate PCI configuration access to device */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
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MCF_PCI_PCICAR_DEVNUM(slot + 10) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset);
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value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
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/* finish config cycle */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_DEVNUM(slot + 10) |
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MCF_PCI_PCICAR_FUNCNUM(function) |
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MCF_PCI_PCICAR_DWORD(0);
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swpl(value);
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return value;
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}
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void pci_scan(void)
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{
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uint16_t bus;
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uint16_t slot;
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uint16_t function;
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xprintf("PCI bus scan\r\n");
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for (bus = 0; bus < 1; bus++)
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{
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for (slot = 0; slot < 16; slot++)
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{
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for (function = 0; function < 8; function++)
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{
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uint32_t value;
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value = pci_read_config_longword(bus, slot, function, 0);
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if (value != 0xffffffff)
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{
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xprintf("[%02x] [%02x] [%02x]: %08x\r\n", bus, slot, function, value);
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}
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/* test for multi-function device to avoid ghost device detects */
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value = pci_read_config_longword(bus, slot, function, 0x0c);
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if (!(((value & 0xff00) >> 16) & 0x80)) /* no multi function device */
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function = 8;
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}
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}
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}
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xprintf("finished\r\n");
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}
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}
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/* start of PCI initialization code */
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/* start of PCI initialization code */
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@@ -106,5 +173,7 @@ void init_pci(void)
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MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
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MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
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xprintf("finished\r\n");
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xprintf("finished\r\n");
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pci_scan();
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}
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}
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@@ -945,9 +945,9 @@ void initialize_hardware(void) {
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init_slt();
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init_slt();
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init_fbcs();
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init_fbcs();
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init_ddram();
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init_ddram();
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init_pci();
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init_eport();
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init_eport();
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init_xlbus_arbiter();
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init_xlbus_arbiter();
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init_pci();
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init_fpga();
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init_fpga();
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init_pll();
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init_pll();
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init_video_ddr();
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init_video_ddr();
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