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modified init_gpio() to use symbolic values for initialization and added comments

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This commit is contained in:
Markus Fröschle
2013-08-12 15:23:26 +00:00
parent 45e6f56554
commit 66efc34bdb
1 changed files with 27 additions and 14 deletions
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41
BaS_gcc/sources/sysinit.c
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@@ -158,25 +158,38 @@ void init_gpio(void)
MCF_PAD_PAR_PSC0_PAR_RXD0 | MCF_PAD_PAR_PSC0_PAR_RXD0 |
MCF_PAD_PAR_PSC0_PAR_TXD0; MCF_PAD_PAR_PSC0_PAR_TXD0;
MCF_PAD_PAR_DSPI = 0b0001111111111111; /* DSPI NORMAL */ /*
* Configure all DSPI pins on the GPIO module for there primary function
*/
MCF_PAD_PAR_DSPI = MCF_PAD_PAR_DSPI_PAR_SOUT(MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT) |
MCF_PAD_PAR_DSPI_PAR_SIN(MCF_PAD_PAR_DSPI_PAR_SIN_SIN) |
MCF_PAD_PAR_DSPI_PAR_SCK(MCF_PAD_PAR_DSPI_PAR_SCK_SCK) |
MCF_PAD_PAR_DSPI_PAR_CS0(MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0) |
MCF_PAD_PAR_DSPI_PAR_CS2(MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2) |
MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3) |
MCF_PAD_PAR_DSPI_PAR_CS5;
MCF_PAD_PAR_TIMER = 0b00101101; /* TIN3..2=#IRQ3..2;TOUT3..2=NORMAL */ MCF_PAD_PAR_TIMER = MCF_PAD_PAR_TIMER_PAR_TIN3(MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3) |
MCF_PAD_PAR_TIMER_PAR_TOUT3 |
MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) |
MCF_PAD_PAR_TIMER_PAR_TOUT2;
// MCF_PAD_PAR_TIMER = 0b00101101; /* TIN3..2=#IRQ3..2;TOUT3..2=NORMAL */
// ALLE OUTPUTS NORMAL LOW // ALLE OUTPUTS NORMAL LOW
// ALLE DIR NORMAL INPUT = 0 // ALLE DIR NORMAL INPUT = 0
MCF_GPIO_PDDR_FEC1L = 0b00011110; /* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */ /*
* Configure GPIO FEC1L port directions
#define FPGA_STATUS (1 << 0) */
#define FPGA_CLOCK (1 << 1) MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
#define FPGA_CONFIG (1 << 2) 0 | /* bit 6 = input */
#define FPGA_DATA0 (1 << 3) 0 | /* bit 5 = input */
#define FPGA_CONF_DONE (1 << 5) MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
/* pull FPGA config to low as early as possible */ MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */ 0; /* bit 0 => input */
} }
/* /*