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merged fixes from 0.8.6.1 (errornous skip of FPGA load)

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This commit is contained in:
Markus Fröschle
2014-12-26 09:36:45 +00:00
parent 732956830f f871794760
commit 645aca7228
6 changed files with 1177 additions and 1165 deletions
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2
bas.lk.in
View File

@@ -239,6 +239,8 @@ SECTIONS
*/ */
__FPGA_JTAG_LOADED = __RAMBAR1; __FPGA_JTAG_LOADED = __RAMBAR1;
__FPGA_JTAG_VALID = __RAMBAR1 + 4; __FPGA_JTAG_VALID = __RAMBAR1 + 4;
/* system variables */
/* system variables */ /* system variables */
/* RAMBAR0 0 to 0x7FF -> exception vectors */ /* RAMBAR0 0 to 0x7FF -> exception vectors */

2
net/fecbd.c
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@@ -11,7 +11,7 @@
#include "bas_printf.h" #include "bas_printf.h"
#include <stddef.h> #include <stddef.h>
#define DBG_FECBD //#define DBG_FECBD
#ifdef DBG_FECBD #ifdef DBG_FECBD
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else #else

5
net/ip.c
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@@ -12,7 +12,7 @@
#include "bas_string.h" #include "bas_string.h"
#define IP_DEBUG //#define IP_DEBUG
#if defined(IP_DEBUG) #if defined(IP_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else #else
@@ -296,9 +296,6 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
return; return;
} }
pNbuf->offset += (IP_IHL(ipframe) * 4);
pNbuf->length = (uint16_t)(IP_LENGTH(ipframe) - (IP_IHL(ipframe) * 4));
/* /*
* Call the appriopriate handler * Call the appriopriate handler
*/ */

6
sys/exceptions.S
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@@ -591,6 +591,12 @@ acsi_dma: // atari dma
move.l a1,-(sp) move.l a1,-(sp)
move.l d1,-(sp) move.l d1,-(sp)
//lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr
// mchar move.l, 'D,'M','A,'\ ,(a1)
//move.l #"DMA ",(a1)
// mchar move.l,'I,'N,'T,'!,(a1)
// move.l #'INT!',(a1)
lea 0xf0020110,a5 // fifo daten lea 0xf0020110,a5 // fifo daten
acsi_dma_start: acsi_dma_start:
move.l -12(a5),a1 // dma adresse move.l -12(a5),a1 // dma adresse

11
sys/init_fpga.c
View File

@@ -47,11 +47,14 @@ extern uint8_t _FPGA_CONFIG_SIZE[];
/* /*
* flag located in processor SRAM1 that indicates that the FPGA configuration has * flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through JTAG. init_fpga() will honour this and not overwrite config. * been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/ */
extern bool _FPGA_JTAG_LOADED; extern bool _FPGA_JTAG_LOADED;
extern long _FPGA_JTAG_VALID; extern long _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe #define VALID_JTAG 0xaffeaffe
extern int32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void) void config_gpio_for_fpga_config(void)
{ {
@@ -100,6 +103,8 @@ bool init_fpga(void)
/* reset the flag so that next boot will load config again from flash */ /* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0; _FPGA_JTAG_LOADED = 0;
_FPGA_JTAG_VALID = 0;
return true; return true;
} }
start = MCF_SLT0_SCNT; start = MCF_SLT0_SCNT;
@@ -114,7 +119,8 @@ bool init_fpga(void)
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */ MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */ while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
; /* wait until status becomes high */
/* /*
* excerpt from an Altera configuration manual: * excerpt from an Altera configuration manual:
@@ -180,5 +186,6 @@ bool init_fpga(void)
} }
xprintf("FAILED!\r\n"); xprintf("FAILED!\r\n");
config_gpio_for_jtag_config(); config_gpio_for_jtag_config();
return false; return false;
} }