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added testbench files

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This commit is contained in:
Markus Fröschle
2014-12-23 18:25:15 +00:00
parent 5eac75430e
commit 63c0a2f167
3 changed files with 6 additions and 4 deletions
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6
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -688,12 +688,12 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd
set_global_assignment -name VHDL_FILE ../../../testbenches/firebee_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_NAME firebee_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -102,8 +102,10 @@ ENTITY firebee IS
clk_24m576 : OUT STD_LOGIC; --
clk_25m : OUT STD_LOGIC;
clk_ddr_out : OUT STD_LOGIC;
clk_ddr_out_n : OUT STD_LOGIC;
clk_usb : OUT STD_LOGIC;
fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);