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renamed files, fixed testbench

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This commit is contained in:
Markus Fröschle
2014-12-23 18:20:11 +00:00
parent 5cc8c3bbbf
commit 5eac75430e
3 changed files with 5167 additions and 11 deletions
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20
vhdl/testbenches/ddr2_ram_model.vhd → vhdl/testbenches/ddr_ram_model.vhd
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@@ -4,8 +4,8 @@ LIBRARY IEEE;
LIBRARY work; LIBRARY work;
PACKAGE ddr2_ram_model_pkg IS PACKAGE ddr_ram_model_pkg IS
-- DDR2 RAM timing constants -- DDR RAM timing constants
CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value
CONSTANT TRFC_MAX : TIME := 70000000 ps; -- refresh to refresh command maximum value CONSTANT TRFC_MAX : TIME := 70000000 ps; -- refresh to refresh command maximum value
@@ -20,7 +20,7 @@ PACKAGE ddr2_ram_model_pkg IS
CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator
COMPONENT ddr2_ram_model IS COMPONENT ddr_ram_model IS
GENERIC GENERIC
( (
VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
@@ -54,9 +54,9 @@ PACKAGE ddr2_ram_model_pkg IS
END COMPONENT; END COMPONENT;
END PACKAGE; END PACKAGE;
PACKAGE BODY ddr2_ram_model_pkg IS PACKAGE BODY ddr_ram_model_pkg IS
END PACKAGE BODY ddr2_ram_model_pkg; END PACKAGE BODY ddr_ram_model_pkg;
--------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE; LIBRARY IEEE;
@@ -64,9 +64,9 @@ LIBRARY IEEE;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
LIBRARY work; LIBRARY work;
USE work.ddr2_ram_model_pkg.ALL; USE work.ddr_ram_model_pkg.ALL;
ENTITY ddr2_ram_model IS ENTITY ddr_ram_model IS
GENERIC GENERIC
( (
VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
@@ -96,10 +96,10 @@ ENTITY ddr2_ram_model IS
rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
odt : IN STD_LOGIC odt : IN STD_LOGIC
); );
END ENTITY ddr2_ram_model; END ENTITY ddr_ram_model;
ARCHITECTURE rtl OF ddr2_ram_model IS ARCHITECTURE rtl OF ddr_ram_model IS
-- DDR2 RAM size constants -- DDR RAM size constants
CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024 CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all
CONSTANT TDLLK : INTEGER := 200; CONSTANT TDLLK : INTEGER := 200;

17
vhdl/testbenches/firebee_tb.vhd
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@@ -1,6 +1,6 @@
LIBRARY work; LIBRARY work;
USE work.firebee_pkg.ALL; USE work.firebee_pkg.ALL;
-- USE work.ddr2_ram_model_pkg.ALL; USE work.ddr_ram_model_pkg.ALL;
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
@@ -465,4 +465,19 @@ BEGIN
IDE_RDn => ide_rdn, IDE_RDn => ide_rdn,
IDE_CSn => ide_csn IDE_CSn => ide_csn
); );
I_DDR_1 : ddr_ram_model
PORT MAP
(
ck => clk_ddr_out,
ck_n => clk_ddr_out_n,
cke => vcke,
cs_n => vcs_n,
ras_n => vras_n,
cas_n => vcas_n,
we_n => vwe_n,
ba => UNSIGNED(ba),
addr => UNSIGNED(va),
odt => '1'
);
END beh; END beh;

5141
vhdl/testbenches/k4h560438e_a2_0501.v Normal file
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