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reverted to byte operation

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This commit is contained in:
Markus Fröschle
2012-10-30 20:34:45 +00:00
parent 8f26c2a99a
commit 5d7b06d53f
1 changed files with 6 additions and 6 deletions
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12
BaS_GNU/BaS_GNU/sources/init_fpga.c
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@@ -24,7 +24,7 @@ extern void wait_10ms();
*/ */
void init_fpga(void) void init_fpga(void)
{ {
register uint32_t *fpga_data; register uint8_t *fpga_data;
register int i; register int i;
xprintf("FPGA load data...\r\n"); xprintf("FPGA load data...\r\n");
@@ -56,17 +56,17 @@ void init_fpga(void)
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
* configuration is complete and initialization of the device can begin. * configuration is complete and initialization of the device can begin.
*/ */
fpga_data = (uint32_t *) FPGA_FLASH_DATA; fpga_data = (uint8_t *) FPGA_FLASH_DATA;
do do
{ {
uint32_t value = *fpga_data++; uint8_t value = *fpga_data++;
if (((int) fpga_data % 0x100) == 0) { if (((int) fpga_data % 0x100) == 0) {
xprintf("%08x ", fpga_data); xprintf("%08x ", fpga_data);
display_progress(); display_progress();
} }
for (i = 0; i < 32; i++, value >>= 1) for (i = 0; i < 8; i++, value >>= 1)
{ {
if (value & 1) if (value & 1)
@@ -83,9 +83,9 @@ void init_fpga(void)
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK; MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
} }
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint32_t *) FPGA_FLASH_DATA_END)); } while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) || (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END));
if (fpga_data < (uint32_t *) FPGA_FLASH_DATA_END) if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)
{ {
for (i = 0; i < 4000; i++) for (i = 0; i < 4000; i++)
{ {