Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed type inconistencies

Browse Source
This commit is contained in:
Markus Fröschle
2014-12-23 16:44:21 +00:00
parent c197609be6
commit 5cc8c3bbbf
4 changed files with 32 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
vhdl/backend/Altera/Firebee/firebee.qsf
View File

@@ -688,7 +688,6 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4] set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/io_register.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE ../../../testbenches/firebee_tb.vhd set_global_assignment -name VHDL_FILE ../../../testbenches/firebee_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
@@ -697,3 +696,4 @@ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME firebee_tb -section_id fire
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 s" -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME firebee_tb -section_id firebee_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/firebee_tb.vhd -section_id firebee_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

28
vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd
View File

@@ -107,26 +107,26 @@ PACKAGE firebee_pkg IS
COMPONENT VIDEO_CTRL COMPONENT VIDEO_CTRL
PORT( PORT(
clk_main : IN STD_LOGIC; clk_main : IN STD_LOGIC;
fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); fb_cs_n : IN STD_LOGIC_VECTOR (2 DOWNTO 1);
fb_wr_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC;
fb_oe_n : IN STD_LOGIC; fb_oe_n : IN STD_LOGIC;
fb_size : IN STD_LOGIC_VECTOR(1 DOWNTO 0); fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk33m : IN STD_LOGIC; clk33m : IN STD_LOGIC;
clk25m : IN STD_LOGIC; clk25m : IN STD_LOGIC;
blitter_run : IN STD_LOGIC; blitter_run : IN STD_LOGIC;
clk_video : IN STD_LOGIC; clk_video : IN STD_LOGIC;
vr_d : IN STD_LOGIC_VECTOR(8 DOWNTO 0); vr_d : IN UNSIGNED (8 DOWNTO 0);
vr_busy : IN STD_LOGIC; vr_busy : IN STD_LOGIC;
color8 : OUT STD_LOGIC; color8 : OUT STD_LOGIC;
fbee_clut_rd : OUT STD_LOGIC; fbee_clut_rd : OUT STD_LOGIC;
color1 : OUT STD_LOGIC; color1 : OUT STD_LOGIC;
falcon_clut_rdh : OUT STD_LOGIC; falcon_clut_rdh : OUT STD_LOGIC;
falcon_clut_rdl : OUT STD_LOGIC; falcon_clut_rdl : OUT STD_LOGIC;
falcon_clut_wr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); falcon_clut_wr : OUT UNSIGNED(3 DOWNTO 0);
clut_st_rd : OUT STD_LOGIC; clut_st_rd : OUT STD_LOGIC;
clut_st_wr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); clut_st_wr : OUT UNSIGNED (1 DOWNTO 0);
clut_mux_adr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); clut_mux_adr : OUT UNSIGNED (3 DOWNTO 0);
hsync : OUT STD_LOGIC; hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC;
blank_n : OUT STD_LOGIC; blank_n : OUT STD_LOGIC;
@@ -136,21 +136,21 @@ PACKAGE firebee_pkg IS
COLOR2 : OUT STD_LOGIC; COLOR2 : OUT STD_LOGIC;
COLOR4 : OUT STD_LOGIC; COLOR4 : OUT STD_LOGIC;
CLK_PIXEL : OUT STD_LOGIC; CLK_PIXEL : OUT STD_LOGIC;
CLUT_OFF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLUT_OFF : OUT UNSIGNED (3 DOWNTO 0);
blitter_on : OUT STD_LOGIC; blitter_on : OUT STD_LOGIC;
video_ram_ctr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); video_ram_ctr : OUT UNSIGNED (15 DOWNTO 0);
video_mod_ta : OUT STD_LOGIC; video_mod_ta : OUT STD_LOGIC;
CCR : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); CCR : OUT UNSIGNED (23 DOWNTO 0);
CCSEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); CCSEL : OUT UNSIGNED (2 DOWNTO 0);
FBEE_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); FBEE_CLUT_WR : OUT UNSIGNED (3 DOWNTO 0);
INTER_ZEI : OUT STD_LOGIC; INTER_ZEI : OUT STD_LOGIC;
DOP_FIFO_CLR : OUT STD_LOGIC; DOP_FIFO_CLR : OUT STD_LOGIC;
video_reconfig : OUT STD_LOGIC; video_reconfig : OUT STD_LOGIC;
VR_WR : OUT STD_LOGIC; VR_WR : OUT STD_LOGIC;
VR_RD : OUT STD_LOGIC; VR_RD : OUT STD_LOGIC;
fifo_clr : OUT STD_LOGIC; fifo_clr : OUT STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DATA_IN : IN UNSIGNED (31 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); DATA_OUT : OUT UNSIGNED (31 DOWNTO 0);
DATA_EN_H : OUT STD_LOGIC; DATA_EN_H : OUT STD_LOGIC;
DATA_EN_L : OUT STD_LOGIC DATA_EN_L : OUT STD_LOGIC
); );

6
vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
View File

@@ -49,11 +49,11 @@ LIBRARY IEEE;
ENTITY VIDEO_CTRL IS ENTITY VIDEO_CTRL IS
PORT( PORT(
clk_main : IN STD_LOGIC; clk_main : IN STD_LOGIC;
fb_cs_n : IN UNSIGNED (2 DOWNTO 1); fb_cs_n : IN STD_LOGIC_VECTOR (2 DOWNTO 1);
fb_wr_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC;
fb_oe_n : IN STD_LOGIC; fb_oe_n : IN STD_LOGIC;
fb_size : IN UNSIGNED (1 DOWNTO 0); fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
fb_adr : IN UNSIGNED (31 DOWNTO 0); fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk33m : IN STD_LOGIC; clk33m : IN STD_LOGIC;
clk25m : IN STD_LOGIC; clk25m : IN STD_LOGIC;
blitter_run : IN STD_LOGIC; blitter_run : IN STD_LOGIC;

26
vhdl/rtl/vhdl/Video/Video_Top.vhd
View File

@@ -96,7 +96,7 @@ ENTITY VIDEO_SYSTEM IS
vd_vz : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); vd_vz : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
sr_fifo_wre : IN STD_LOGIC; sr_fifo_wre : IN STD_LOGIC;
sr_vdmp : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sr_vdmp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
fifo_mw : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); fifo_mw : OUT UNSIGNED (8 DOWNTO 0);
vdm_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); vdm_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
video_ram_ctr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); video_ram_ctr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
fifo_clr : OUT STD_LOGIC; fifo_clr : OUT STD_LOGIC;
@@ -484,7 +484,7 @@ BEGIN
wrreq => fifo_wre, wrreq => fifo_wre,
q => fifo_d_out_512, q => fifo_d_out_512,
--rdempty =>, -- Not d. --rdempty =>, -- Not d.
wrusedw => fifo_mw UNSIGNED(wrusedw) => fifo_mw
); );
I_FIFO_DZ: lpm_fifoDZ I_FIFO_DZ: lpm_fifoDZ
@@ -511,17 +511,17 @@ BEGIN
CLK25M => clk_25m, CLK25M => clk_25m,
blitter_run => blitter_run, blitter_run => blitter_run,
clk_video => clk_video, clk_video => clk_video,
vr_d => vr_d, vr_d => UNSIGNED(vr_d),
vr_busy => vr_busy, vr_busy => vr_busy,
color8 => color8, color8 => color8,
FBEE_CLUT_RD => clut_fbee_rd, FBEE_CLUT_RD => clut_fbee_rd,
COLOR1 => COLOR1, COLOR1 => COLOR1,
FALCON_CLUT_RDH => clut_fa_rdh, FALCON_CLUT_RDH => clut_fa_rdh,
FALCON_CLUT_RDL => clut_fa_rdl, FALCON_CLUT_RDL => clut_fa_rdl,
FALCON_CLUT_WR => clut_fa_wr, STD_LOGIC_VECTOR(FALCON_CLUT_WR) => clut_fa_wr,
clut_st_rd => clut_st_rd, clut_st_rd => clut_st_rd,
clut_st_wr => clut_st_wr, STD_LOGIC_VECTOR(clut_st_wr) => clut_st_wr,
CLUT_MUX_ADR => clut_adr_mux, STD_LOGIC_VECTOR(CLUT_MUX_ADR) => clut_adr_mux,
hsync => hsync, hsync => hsync,
vsync => vsync, vsync => vsync,
blank_n => blank_n, blank_n => blank_n,
@@ -531,21 +531,21 @@ BEGIN
color2 => color2, color2 => color2,
color4 => color4, color4 => color4,
clk_pixel => clk_pixel_i, clk_pixel => clk_pixel_i,
clut_off => clut_off, STD_LOGIC_VECTOR(clut_off) => clut_off,
blitter_on => blitter_on, blitter_on => blitter_on,
video_ram_ctr => video_ram_ctr, STD_LOGIC_VECTOR(video_ram_ctr) => video_ram_ctr,
video_mod_ta => video_mod_ta, video_mod_ta => video_mod_ta,
ccr => ccr, STD_LOGIC_VECTOR(ccr) => ccr,
CCSEL => CC_SEL, STD_LOGIC_VECTOR(CCSEL) => CC_SEL,
FBEE_CLUT_WR => clut_fbee_wr, STD_LOGIC_VECTOR(FBEE_CLUT_WR) => clut_fbee_wr,
inter_zei => inter_zei, inter_zei => inter_zei,
dop_fifo_clr => dop_fifo_clr, dop_fifo_clr => dop_fifo_clr,
video_reconfig => video_reconfig, video_reconfig => video_reconfig,
vr_wr => vr_wr, vr_wr => vr_wr,
vr_rd => vr_rd, vr_rd => vr_rd,
fifo_clr => fifo_clr_i, fifo_clr => fifo_clr_i,
DATA_IN => fb_ad_in, DATA_IN => UNSIGNED(fb_ad_in),
DATA_OUT => data_out_video_ctrl, STD_LOGIC_VECTOR(DATA_OUT) => data_out_video_ctrl,
DATA_EN_H => data_en_h_video_ctrl, DATA_EN_H => data_en_h_video_ctrl,
DATA_EN_L => data_en_l_video_ctrl DATA_EN_L => data_en_l_video_ctrl
); );