diff --git a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd index c072dbb..bed309f 100644 --- a/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd +++ b/vhdl/rtl/vhdl/Blitter/Blitter_WF.vhd @@ -44,57 +44,57 @@ -- Initial Release of the second edition. -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.ALL; -entity FBEE_BLITTER is - port( - reset_n : in std_logic; - CLK_MAIN : in std_logic; - CLK_DDR0 : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - FB_ALE : in std_logic; - FB_SIZE1 : in std_logic; - FB_SIZE0 : in std_logic; - fb_cs_n : in std_logic_vector(3 downto 1); - fb_oe_n : in std_logic; - fb_wr_n : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_EN : out std_logic; - BLITTER_ON : in std_logic; - BLITTER_DIN : in std_logic_vector(127 downto 0); - BLITTER_DACK_SR : in std_logic; - BLITTER_RUN : out std_logic; - BLITTER_DOUT : out std_logic_vector(127 downto 0); - BLITTER_ADR : out std_logic_vector(31 downto 0); - BLITTER_SIG : out std_logic; - BLITTER_WR : out std_logic; - BLITTER_TA : out std_logic - ); -end entity FBEE_BLITTER; +ENTITY fbee_blitter IS + PORT( + reset_n : IN std_logic; + clk_main : IN std_logic; + clk_ddr0 : IN std_logic; + fb_adr : IN std_logic_vector(31 DOWNTO 0); + fb_ale : IN std_logic; + fb_size1 : IN std_logic; + fb_size0 : IN std_logic; + fb_cs_n : IN std_logic_vector(3 DOWNTO 1); + fb_oe_n : IN std_logic; + fb_wr_n : IN std_logic; + data_in : IN std_logic_vector(31 DOWNTO 0); + data_out : OUT std_logic_vector(31 DOWNTO 0); + data_en : OUT std_logic; + blitter_on : IN std_logic; + blitter_din : IN std_logic_vector(127 DOWNTO 0); + blitter_dack_sr : IN std_logic; + blitter_run : OUT std_logic; + blitter_dout : OUT std_logic_vector(127 DOWNTO 0); + blitter_adr : OUT std_logic_vector(31 DOWNTO 0); + blitter_sig : OUT std_logic; + blitter_wr : OUT std_logic; + blitter_ta : OUT std_logic + ); +END ENTITY fbee_blitter; architecture BEHAVIOUR of FBEE_BLITTER is - signal BLITTER_DACK : std_logic_vector(4 downto 0); - signal BLITTER_DIN_I : std_logic_vector(127 downto 0); -begin - P_BLITTER_DACK: process - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 downto 1); - if BLITTER_DACK(0) = '1' then - BLITTER_DIN_I <= BLITTER_DIN; - end if; - end process P_BLITTER_DACK; + signal BLITTER_DACK : std_logic_vector(4 DOWNTO 0); + signal BLITTER_DIN_I : std_logic_vector(127 DOWNTO 0); +begIN + P_BLITTER_DACK: process + begIN + wait until CLK_DDR0 = '1' and CLK_DDR0' event; + BLITTER_DACK <= BLITTER_DACK_SR & BLITTER_DACK(4 DOWNTO 1); + if BLITTER_DACK(0) = '1' then + BLITTER_DIN_I <= BLITTER_DIN; + end if; + end process P_BLITTER_DACK; - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - DATA_OUT <= x"FEDCBA98"; - BLITTER_ADR <= x"76543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; - BLITTER_TA <= '0'; - DATA_EN <= '0'; + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + DATA_OUT <= x"FEDCBA98"; + BLITTER_ADR <= x"76543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + DATA_EN <= '0'; END BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index fece08a..f1c8735 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -185,7 +185,7 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL ba_p : unsigned(1 DOWNTO 0); BEGIN --------------------------------------------------------------------------------------------------------------------------------------------------------------- - ------------------------------------ ddr_access_cpu READ (REG DDR => ddr_access_cpu) AND WRITE (ddr_access_cpu => REG DDR) --------------------------------------------------------------------- + ------------------------------------ ddr_access cpu read (REG DDR => ddr_access_cpu) AND write (ddr_access_cpu => REG DDR) --------------------------------------------------------------------- fbctrl_reg : PROCESS VARIABLE aw : access_width_t; @@ -257,7 +257,7 @@ BEGIN END IF; WHEN fr_s2 => - IF ddr_cs = '1' AND bus_cyc = '0' AND access_width = long_access AND fb_wr_n = '0' THEN -- wait during long_access word_access access if needed + IF ddr_cs = '1' AND bus_cyc = '0' AND access_width = long_access AND fb_wr_n = '0' THEN -- wait during longword access if needed fb_regddr_next <= fr_s2; ELSIF ddr_cs = '1' THEN fb_regddr_next <= fr_s3; @@ -304,7 +304,7 @@ BEGIN END PROCESS ddr_state_reg; ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, vmem_config_enable, fb_wr_n, ddr_access, blitter_wr, fifo_req, fifo_bank_ok, - fifo_mw, cpu_req, video_adr_cnt, ddr_sel, data_in, fifo_ba, ddr_refresh_sig) + fifo_mw, cpu_req, video_adr_cnt, ddr_sel, data_in, fifo_ba, ddr_refresh_sig) BEGIN CASE ddr_state IS WHEN ds_t1 => diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index 4813736..071c060 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -62,7 +62,7 @@ ENTITY video_ctrl IS vr_busy : IN std_logic; color8 : OUT std_logic; fbee_clut_rd : OUT std_logic; - COLOR1 : OUT std_logic; + color1 : OUT std_logic; falcon_clut_rdh : OUT std_logic; falcon_clut_rdl : OUT std_logic; falcon_clut_wr : OUT unsigned(3 DOWNTO 0); @@ -130,13 +130,13 @@ ARCHITECTURE behaviour OF video_ctrl IS SIGNAL sys_ctr_cs : std_logic; SIGNAL vdl_lof : unsigned(15 DOWNTO 0); SIGNAL vdl_lof_cs : std_logic; - SIGNAL VDL_LWD : unsigned(15 DOWNTO 0); - SIGNAL VDL_LWD_CS : std_logic; + SIGNAL vdl_lwd : unsigned(15 DOWNTO 0); + SIGNAL vdl_lwd_cs : std_logic; -- Miscellaneous control registers: SIGNAL clut_ta : std_logic; -- Requires one wait state. SIGNAL hsync_i : unsigned(7 DOWNTO 0); - SIGNAL hsync_len : unsigned(7 DOWNTO 0); -- Length of a hsync pulse IN clk_pixel cycles. + SIGNAL hsync_len : unsigned(7 DOWNTO 0); -- Length of a hsync pulse IN clk_pixel cycles. SIGNAL hsync_start : std_logic; SIGNAL last : std_logic; -- Last pixel of a line indicator. SIGNAL vsync_start : std_logic; @@ -245,29 +245,29 @@ BEGIN vr_rd <= vr_rd_i; clk_pixel <= clk_pixel_i; - -- Byte selectors: + -- Byte selectORs: fb_b(0) <= '1' WHEN fb_adr(1 DOWNTO 0) = "00" ELSE '0'; -- Byte 0. - fb_b(1) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '0' ELSE -- High word. - '1' WHEN fb_adr(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. + fb_b(1) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long wORd. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '0' ELSE -- High wORd. + '1' WHEN fb_adr(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. - fb_b(2) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_adr(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. + fb_b(2) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long wORd. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_adr(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. - fb_b(3) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long word. - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '1' ELSE -- Low word. - '1' WHEN fb_adr(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. + fb_b(3) <= '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE -- Long wORd. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- Long. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' AND fb_adr(1) = '1' ELSE -- Low wORd. + '1' WHEN fb_adr(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. - -- 16 bit selectors: + -- 16 bit selectORs: fb_16b(0) <= NOT fb_adr(0); fb_16b(1) <= '1'WHEN fb_adr(0) = '1' ELSE - '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- No byte. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' ELSE -- No byte. - '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE '0'; -- No byte. + '1' WHEN fb_size(1) = '0' AND fb_size(0) = '0' ELSE -- No byte. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '0' ELSE -- No byte. + '1' WHEN fb_size(1) = '1' AND fb_size(0) = '1' ELSE '0'; -- No byte. -- Firebee CLUT: fbee_clut_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 10) = "000000000000000000" ELSE '0'; -- 0-3FF/1024 @@ -276,7 +276,7 @@ BEGIN p_clut_ta : PROCESS BEGIN - WAIT UNTIL clk_main = '1' AND clk_main' EVENT; + WAIT UNTIL rising_edge(clk_main); IF video_mod_ta_i = '0' AND fbee_clut_cs = '1' THEN clut_ta <= '1'; ELSIF video_mod_ta_i = '0' AND falcon_clut_cs = '1' THEN @@ -290,8 +290,8 @@ BEGIN --Falcon CLUT: falcon_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 10) = "1111100110" ELSE '0'; -- $F9800/$400 - falcon_clut_rdh <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '0' ELSE '0'; -- High word. - falcon_clut_rdl <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '1' ELSE '0'; -- Low word. + falcon_clut_rdh <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '0' ELSE '0'; -- High wORd. + falcon_clut_rdl <= '1' WHEN falcon_clut_cs = '1' AND fb_oe_n = '0' AND fb_adr(1) = '1' ELSE '0'; -- Low wORd. falcon_clut_wr(1 DOWNTO 0) <= fb_16b WHEN fb_adr(1) = '0' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; falcon_clut_wr(3 DOWNTO 2) <= fb_16b WHEN fb_adr(1) = '1' AND falcon_clut_cs = '1' AND fb_wr_n = '0' ELSE "00"; @@ -322,11 +322,19 @@ BEGIN END IF; -- Firebee VIDEO CONTROL: - -- Bit 0 = FBEE VIDEO ON, 1 = POWER ON VIDEO DAC, 2 = FBEE 24BIT, - -- Bit 3 = FBEE 16BIT, 4 = FBEE 8BIT, 5 = FBEE 1BIT, - -- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency, - -- Bit 15 = SYNC ALLOWED, 31..16 = video_ram_ctr, - -- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS. + -- Bit 0 = FBEE VIDEO ON, + -- Bit 1 = POWER ON VIDEO DAC, + -- Bit 2 = FBEE 24BIT, + -- Bit 3 = FBEE 16BIT, + -- Bit 4 = FBEE 8BIT, + -- Bit 5 = FBEE 1BIT, + -- Bit 6 = FALCON SHIFT MODE, + -- Bit 7 = ST SHIFT MODE, + -- Bit 9..8 = VCLK frequency, + -- Bit 15 = SYNC ALLOWED, + -- Bit 31..16 = video_ram_ctr, + -- Bit 25 = enable border color, + -- Bit 26 = STANDARD ATARI SYNCS. IF fbee_vctr_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN fbee_vctr(31 DOWNTO 24) <= data_in(31 DOWNTO 24); ELSIF fbee_vctr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN @@ -337,7 +345,7 @@ BEGIN fbee_vctr(5 DOWNTO 0) <= data_in(5 DOWNTO 0); END IF; - -- ST or Falcon shift mode: assert WHEN X..shift register: + -- ST or Falcon shift mode: assert when X..shift register: IF falcon_shift_mode_cs = '1' AND fb_wr_n = '0' THEN fbee_vctr(7) <= falcon_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; fbee_vctr(6) <= st_shift_mode_cs AND NOT fb_wr_n AND NOT fbee_video_on; @@ -414,13 +422,13 @@ BEGIN '1' WHEN fbee_video_on = '1' AND fbee_vctr(3 DOWNTO 2) = "10" ELSE '0'; -- Firebee mode. color24_i <= '1' WHEN fbee_video_on = '1' AND fbee_vctr(2) = '1' ELSE '0'; -- Firebee mode. - COLOR1 <= color1_i; + color1 <= color1_i; color2 <= color2_i; color4 <= color4_i; color8 <= color8_i; -- VIDEO PLL config AND reconfig: - video_pll_config_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_b(1) = '1' AND fb_adr(27 DOWNTO 9) = "0000000000000000011" ELSE '0'; -- $(F)000'0600-7FF -> 6/2 word AND long only. + video_pll_config_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_b(1) = '1' AND fb_adr(27 DOWNTO 9) = "0000000000000000011" ELSE '0'; -- $(F)000'0600-7FF -> 6/2 wORd AND long only. video_pll_reconfig_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_b(0) = '1' AND fb_adr(27 DOWNTO 0) = x"0000800" ELSE '0'; -- $(F)000'0800. vr_rd_i <= '1' WHEN video_pll_config_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' ELSE '0'; @@ -446,7 +454,7 @@ BEGIN IF video_pll_reconfig_cs = '1' AND fb_wr_n = '0' AND vr_busy = '0' AND lock = false THEN video_reconfig_i <= '1'; -- This is a strobe. lock := true; - ELSIF video_pll_reconfig_cs = '0' or fb_wr_n = '1' or vr_busy = '1' THEN + ELSIF video_pll_reconfig_cs = '0' OR fb_wr_n = '1' OR vr_busy = '1' THEN video_reconfig_i <= '0'; lock := false; ELSE @@ -457,7 +465,7 @@ BEGIN video_ram_ctr <= fbee_vctr(31 DOWNTO 16); -- Firebee colour modi: - fbee_clut <= '1' WHEN fbee_video_on = '1' AND (color1_i = '1' or color8_i = '1') ELSE + fbee_clut <= '1' WHEN fbee_video_on = '1' AND (color1_i = '1' OR color8_i = '1') ELSE '1' WHEN st_video = '1' AND color1_i = '1'; falcon_video <= fbee_vctr(7); @@ -467,14 +475,14 @@ BEGIN -- Several (video)-registers: ccr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr = x"f0000404" ELSE '0'; -- $F0000404 - Firebee video border color - sys_ctr_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8008" ELSE '0'; -- $FF8006 - Falcon monitor type register + sys_ctr_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8008" ELSE '0'; -- $FF8006 - Falcon monitOR type register vdl_lof_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff820e" ELSE '0'; -- $FF820E/F - line-width hi/lo. - VDL_LWD_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8210" ELSE '0'; -- $FF8210/1 - vertical wrap hi/lo. - vdl_hht_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8282" ELSE '0'; -- $FF8282/3 - horizontal hold timer hi/lo. - vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - horizontal border END hi/lo. - vdl_hdb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8288" ELSE '0'; -- $FF8288/9 - horizontal display BEGIN hi/lo. - vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - horizontal display END hi/lo. - vdl_hbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8284" ELSE '0'; -- $FF8284/5 - horizontal border BEGIN hi/lo. + vdl_lwd_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8210" ELSE '0'; -- $FF8210/1 - vertical wrap hi/lo. + vdl_hht_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8282" ELSE '0'; -- $FF8282/3 - hORizontal hold timer hi/lo. + vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - hORizontal border END hi/lo. + vdl_hdb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8288" ELSE '0'; -- $FF8288/9 - hORizontal display BEGIN hi/lo. + vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - hORizontal display END hi/lo. + vdl_hbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8284" ELSE '0'; -- $FF8284/5 - hORizontal border BEGIN hi/lo. vdl_hss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828c" ELSE '0'; -- $FF828C/D - position hsync (HSS). vdl_vft_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a2" ELSE '0'; -- $FF82A2/3 - video frequency timer (VFT). vdl_vbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a4" ELSE '0'; -- $FF82A4/5 - vertical blank on (IN half line steps). @@ -510,14 +518,14 @@ BEGIN vdl_lof(7 DOWNTO 0) <= data_in(23 DOWNTO 16); END IF; - --VDL_LWD - IF VDL_LWD_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN - VDL_LWD(15 DOWNTO 8) <= data_in(31 DOWNTO 24); - ELSIF VDL_LWD_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN - VDL_LWD(7 DOWNTO 0) <= data_in(23 DOWNTO 16); + --vdl_lwd + IF vdl_lwd_CS = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + vdl_lwd(15 DOWNTO 8) <= data_in(31 DOWNTO 24); + ELSIF vdl_lwd_CS = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + vdl_lwd(7 DOWNTO 0) <= data_in(23 DOWNTO 16); END IF; - -- Horizontal: + -- HORizontal: -- vdl_hht: IF vdl_hht_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN vdl_hht(11 DOWNTO 8) <= data_in(27 DOWNTO 24); @@ -620,51 +628,51 @@ BEGIN -- Register OUT: data_out(31 DOWNTO 16) <= "000000" & st_shift_mode & x"00" WHEN st_shift_mode_cs = '1' ELSE - "00000" & falcon_shift_mode WHEN falcon_shift_mode_cs = '1' ELSE - "100000000" & sys_ctr(6 DOWNTO 4) & NOT blitter_run & sys_ctr(2 DOWNTO 0) WHEN sys_ctr_cs = '1' ELSE - vdl_lof WHEN vdl_lof_cs = '1' ELSE - VDL_LWD WHEN VDL_LWD_CS = '1' ELSE - x"0" & vdl_hbe WHEN vdl_hbe_cs = '1' ELSE - x"0" & vdl_hdb WHEN vdl_hdb_cs = '1' ELSE - x"0" & VDL_HDE WHEN vdl_hde_cs = '1' ELSE - x"0" & vdl_hbb WHEN vdl_hbb_cs = '1' ELSE - x"0" & vdl_hss WHEN vdl_hss_cs = '1' ELSE - x"0" & vdl_hht WHEN vdl_hht_cs = '1' ELSE - "00000" & vdl_vbe WHEN vdl_vbe_cs = '1' ELSE - "00000" & vdl_vdb WHEN VDL_VDB_CS = '1' ELSE - "00000" & vdl_vde WHEN vdl_vde_cs = '1' ELSE - "00000" & vdl_vbb WHEN vdl_vbb_cs = '1' ELSE - "00000" & vdl_vss WHEN vdl_vss_cs = '1' ELSE - "00000" & vdl_vft WHEN vdl_vft_cs = '1' ELSE - "0000000" & vdl_vct WHEN vdl_vct_cs = '1' ELSE - x"000" & vdl_vmd WHEN vdl_vmd_cs = '1' ELSE - fbee_vctr(31 DOWNTO 16) WHEN fbee_vctr_cs = '1' ELSE - atari_hh(31 DOWNTO 16) WHEN atari_hh_cs = '1' ELSE - atari_vh(31 DOWNTO 16) WHEN atari_vh_cs = '1' ELSE - atari_hl(31 DOWNTO 16) WHEN atari_hl_cs = '1' ELSE - atari_vl(31 DOWNTO 16) WHEN atari_vl_cs = '1' ELSE - x"00" & ccr_i(23 DOWNTO 16) WHEN ccr_cs = '1' ELSE - "0000000" & vr_dout WHEN video_pll_config_cs = '1' ELSE - vr_busy & "0000" & vr_wr_i & vr_rd_i & video_reconfig_i & x"FA" WHEN video_pll_reconfig_cs = '1' ELSE (OTHERS => '0'); + "00000" & falcon_shift_mode WHEN falcon_shift_mode_cs = '1' ELSE + "100000000" & sys_ctr(6 DOWNTO 4) & NOT blitter_run & sys_ctr(2 DOWNTO 0) WHEN sys_ctr_cs = '1' ELSE + vdl_lof WHEN vdl_lof_cs = '1' ELSE + vdl_lwd WHEN vdl_lwd_CS = '1' ELSE + x"0" & vdl_hbe WHEN vdl_hbe_cs = '1' ELSE + x"0" & vdl_hdb WHEN vdl_hdb_cs = '1' ELSE + x"0" & VDL_HDE WHEN vdl_hde_cs = '1' ELSE + x"0" & vdl_hbb WHEN vdl_hbb_cs = '1' ELSE + x"0" & vdl_hss WHEN vdl_hss_cs = '1' ELSE + x"0" & vdl_hht WHEN vdl_hht_cs = '1' ELSE + "00000" & vdl_vbe WHEN vdl_vbe_cs = '1' ELSE + "00000" & vdl_vdb WHEN VDL_VDB_CS = '1' ELSE + "00000" & vdl_vde WHEN vdl_vde_cs = '1' ELSE + "00000" & vdl_vbb WHEN vdl_vbb_cs = '1' ELSE + "00000" & vdl_vss WHEN vdl_vss_cs = '1' ELSE + "00000" & vdl_vft WHEN vdl_vft_cs = '1' ELSE + "0000000" & vdl_vct WHEN vdl_vct_cs = '1' ELSE + x"000" & vdl_vmd WHEN vdl_vmd_cs = '1' ELSE + fbee_vctr(31 DOWNTO 16) WHEN fbee_vctr_cs = '1' ELSE + atari_hh(31 DOWNTO 16) WHEN atari_hh_cs = '1' ELSE + atari_vh(31 DOWNTO 16) WHEN atari_vh_cs = '1' ELSE + atari_hl(31 DOWNTO 16) WHEN atari_hl_cs = '1' ELSE + atari_vl(31 DOWNTO 16) WHEN atari_vl_cs = '1' ELSE + x"00" & ccr_i(23 DOWNTO 16) WHEN ccr_cs = '1' ELSE + "0000000" & vr_dout WHEN video_pll_config_cs = '1' ELSE + vr_busy & "0000" & vr_wr_i & vr_rd_i & video_reconfig_i & x"FA" WHEN video_pll_reconfig_cs = '1' ELSE (OTHERS => '0'); data_out(15 DOWNTO 0) <= fbee_vctr(15 DOWNTO 0) WHEN fbee_vctr_cs = '1' ELSE - atari_hh(15 DOWNTO 0) WHEN atari_hh_cs = '1' ELSE - atari_vh(15 DOWNTO 0) WHEN atari_vh_cs = '1' ELSE - atari_hl(15 DOWNTO 0) WHEN atari_hl_cs = '1' ELSE - atari_vl(15 DOWNTO 0) WHEN atari_vl_cs = '1' ELSE - ccr_i(15 DOWNTO 0) WHEN ccr_cs = '1' ELSE (OTHERS => '0'); + atari_hh(15 DOWNTO 0) WHEN atari_hh_cs = '1' ELSE + atari_vh(15 DOWNTO 0) WHEN atari_vh_cs = '1' ELSE + atari_hl(15 DOWNTO 0) WHEN atari_hl_cs = '1' ELSE + atari_vl(15 DOWNTO 0) WHEN atari_vl_cs = '1' ELSE + ccr_i(15 DOWNTO 0) WHEN ccr_cs = '1' ELSE (OTHERS => '0'); - data_en_h <= (st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or ccr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or - vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or - atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or video_pll_config_cs or video_pll_reconfig_cs or - vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs) AND NOT fb_oe_n; + data_en_h <= (st_shift_mode_cs OR falcon_shift_mode_cs OR fbee_vctr_cs OR ccr_cs OR sys_ctr_cs OR vdl_lof_cs OR vdl_lwd_CS OR + vdl_hbe_cs OR vdl_hdb_cs OR vdl_hde_cs OR vdl_hbb_cs OR vdl_hss_cs OR vdl_hht_cs OR + atari_hh_cs OR atari_vh_cs OR atari_hl_cs OR atari_vl_cs OR video_pll_config_cs OR video_pll_reconfig_cs OR + vdl_vbe_cs OR VDL_VDB_CS OR vdl_vde_cs OR vdl_vbb_cs OR vdl_vss_cs OR vdl_vft_cs OR vdl_vct_cs OR vdl_vmd_cs) AND NOT fb_oe_n; - data_en_l <= (fbee_vctr_cs or ccr_cs or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs ) AND NOT fb_oe_n; + data_en_l <= (fbee_vctr_cs OR ccr_cs OR atari_hh_cs OR atari_vh_cs OR atari_hl_cs OR atari_vl_cs ) AND NOT fb_oe_n; - video_mod_ta_i <= clut_ta or st_shift_mode_cs or falcon_shift_mode_cs or fbee_vctr_cs or sys_ctr_cs or vdl_lof_cs or VDL_LWD_CS or - vdl_hbe_cs or vdl_hdb_cs or vdl_hde_cs or vdl_hbb_cs or vdl_hss_cs or vdl_hht_cs or - atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs or - vdl_vbe_cs or VDL_VDB_CS or vdl_vde_cs or vdl_vbb_cs or vdl_vss_cs or vdl_vft_cs or vdl_vct_cs or vdl_vmd_cs; + video_mod_ta_i <= clut_ta OR st_shift_mode_cs OR falcon_shift_mode_cs OR fbee_vctr_cs OR sys_ctr_cs OR vdl_lof_cs OR vdl_lwd_CS OR + vdl_hbe_cs OR vdl_hdb_cs OR vdl_hde_cs OR vdl_hbb_cs OR vdl_hss_cs OR vdl_hht_cs OR + atari_hh_cs OR atari_vh_cs OR atari_hl_cs OR atari_vl_cs OR + vdl_vbe_cs OR VDL_VDB_CS OR vdl_vde_cs OR vdl_vbb_cs OR vdl_vss_cs OR vdl_vft_cs OR vdl_vct_cs OR vdl_vmd_cs; p_clk_16m5 : PROCESS BEGIN @@ -678,68 +686,68 @@ BEGIN clk13m <= NOT clk13m; END PROCESS p_clk_12m5; - clk_pixel_i <= clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' ELSE - clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' ELSE - clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' ELSE - clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' ELSE - clk25m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' ELSE - clk33m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' ELSE + clk_pixel_i <= clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' ELSE + clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' ELSE + clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' ELSE + clk17m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' ELSE + clk25m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' ELSE + clk33m WHEN fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' ELSE clk25m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" ELSE clk33m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" ELSE clk_video WHEN fbee_video_on = '1' AND fbee_vctr(9) = '1' ELSE '0'; p_hsyn_len : PROCESS - -- Horizontal SYNC IN clk_pixel: + -- horizontal sync IN clk_pixel: BEGIN WAIT UNTIL rising_edge(clk_main); - IF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' THEN + IF fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' THEN hsync_len <= 8D"14"; - ELSIF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' THEN + ELSIF fbee_video_on = '0' AND (falcon_video = '1' OR st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' THEN hsync_len <= 8D"14"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' THEN + ELSIF fbee_video_on = '0' AND (falcon_video OR st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' THEN hsync_len <= 8D"16"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' THEN + ELSIF fbee_video_on = '0' AND (falcon_video OR st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' THEN hsync_len <= 8D"16"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' THEN + ELSIF fbee_video_on = '0' AND (falcon_video OR st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' THEN hsync_len <= 8D"28"; - ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' THEN + ELSIF fbee_video_on = '0' AND (falcon_video OR st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' THEN hsync_len <= 8D"32"; ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" THEN hsync_len <= 8D"28"; ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" THEN hsync_len <= 8D"32"; ELSIF fbee_video_on = '1' AND fbee_vctr(9) = '1' THEN - hsync_len <= 8D"16" + vr_frq / 2; -- hsync pulse length IN pixels = frequency/500ns. + hsync_len <= 8D"16" + vr_frq / 2; -- hsync pulse length in pixels = frequency/500ns. ELSE hsync_len <= x"00"; END IF; END PROCESS p_hsyn_len; - mulf <= "000010" WHEN st_video = '0' AND vdl_vmd(2) = '1' ELSE -- Multiplier. + mulf <= "000010" WHEN st_video = '0' AND vdl_vmd(2) = '1' ELSE -- multiplier. "000100" WHEN st_video = '0' AND vdl_vmd(2) = '0' ELSE "010000" WHEN st_video = '1' AND vdl_vmd(2) = '1' ELSE "100000" WHEN st_video = '1' AND vdl_vmd(2) = '0' ELSE "000000"; - hdis_len <= x"140" WHEN vdl_vmd(2) = '1' ELSE x"280"; -- Width IN pixels (320 / 640). + hdis_len <= x"140" WHEN vdl_vmd(2) = '1' ELSE x"280"; -- width in pixels (320 / 640). p_double_line_1 : PROCESS BEGIN WAIT UNTIL rising_edge(clk_main); - dop_zei <= vdl_vmd(0) AND st_video; -- Line doubling on off. + dop_zei <= vdl_vmd(0) AND st_video; -- line doubling on off. END PROCESS p_double_line_1; p_double_line_2 : PROCESS BEGIN WAIT UNTIL rising_edge(clk_pixel_i); IF dop_zei = '1' AND vvcnt(0) /= vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt < hdis_end - 1 THEN - inter_zei_i <= '1'; -- Switch insertion line to "double". Line zero due to SYNC. + inter_zei_i <= '1'; -- Switch insertion line to "double". Line zero due to sync. ELSIF dop_zei = '1' AND vvcnt(0) = vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt > hdis_end - 10 THEN - inter_zei_i <= '1'; -- Switch insertion mode to "normal". Lines AND line zero due to SYNC. + inter_zei_i <= '1'; -- Switch insertion mode to "normal". Lines and line zero due to sync. ELSE inter_zei_i <= '0'; END IF; -- - dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the END of a double line AND at main FIFO start. + dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the end of a double line and at main fifo start. END PROCESS p_double_line_2; -- The following multiplications change every time the video resolution is changed. @@ -748,32 +756,32 @@ BEGIN mul3 <= RESIZE(vdl_hht + 10 * mulf(5 DOWNTO 1), mul3'LENGTH); border_left <= vdl_hbe WHEN fbee_video_on = '1' ELSE - x"015" WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - x"02A" WHEN atari_sync = '1' ELSE mul1(16 DOWNTO 5); + x"015" WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + x"02A" WHEN atari_sync = '1' ELSE mul1(16 DOWNTO 5); hdis_start <= vdl_hdb WHEN fbee_video_on = '1' ELSE border_left + 1; hdis_end <= VDL_HDE WHEN fbee_video_on = '1' ELSE border_left + hdis_len; border_right <= vdl_hbb WHEN fbee_video_on = '1' ELSE hdis_end + 1; hs_start <= vdl_hss WHEN fbee_video_on = '1' ELSE - atari_hl(11 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_hh(11 DOWNTO 0) WHEN vdl_vmd(2) = '1' ELSE mul2(16 DOWNTO 5); + atari_hl(11 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_hh(11 DOWNTO 0) WHEN vdl_vmd(2) = '1' ELSE mul2(16 DOWNTO 5); h_total <= vdl_hht WHEN fbee_video_on = '1' ELSE - atari_hl(27 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_hh(27 DOWNTO 16) WHEN atari_sync = '1' ELSE mul3(16 DOWNTO 5); + atari_hl(27 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_hh(27 DOWNTO 16) WHEN atari_sync = '1' ELSE mul3(16 DOWNTO 5); border_top <= vdl_vbe WHEN fbee_video_on = '1' ELSE - "00000011111" WHEN atari_sync = '1' ELSE '0' & vdl_vbe(10 DOWNTO 1); + "00000011111" WHEN atari_sync = '1' ELSE '0' & vdl_vbe(10 DOWNTO 1); vdis_start <= vdl_vdb WHEN fbee_video_on = '1' ELSE - "00000100000" WHEN atari_sync = '1' ELSE '0' & vdl_vdb(10 DOWNTO 1); + "00000100000" WHEN atari_sync = '1' ELSE '0' & vdl_vdb(10 DOWNTO 1); vdis_end <= vdl_vde WHEN fbee_video_on = '1' ELSE - "00110101111" WHEN atari_sync = '1' AND st_video = '1' ELSE -- 431. - "00111111111" WHEN atari_sync = '1' ELSE '0' & vdl_vde(10 DOWNTO 1); -- 511. + "00110101111" WHEN atari_sync = '1' AND st_video = '1' ELSE -- 431. + "00111111111" WHEN atari_sync = '1' ELSE '0' & vdl_vde(10 DOWNTO 1); -- 511. border_bottom <= vdl_vbb WHEN fbee_video_on = '1' ELSE - vdis_end + 1 WHEN atari_sync = '1' ELSE ('0' & vdl_vbb(10 DOWNTO 1) + 1); + vdis_end + 1 WHEN atari_sync = '1' ELSE ('0' & vdl_vbb(10 DOWNTO 1) + 1); vs_start <= vdl_vss WHEN fbee_video_on = '1' ELSE - atari_vl(10 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_vh(10 DOWNTO 0) WHEN atari_sync = '1' ELSE '0' & vdl_vss(10 DOWNTO 1); + atari_vl(10 DOWNTO 0) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_vh(10 DOWNTO 0) WHEN atari_sync = '1' ELSE '0' & vdl_vss(10 DOWNTO 1); v_total <= vdl_vft WHEN fbee_video_on = '1' ELSE - atari_vl(26 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE - atari_vh(26 DOWNTO 16) WHEN atari_sync = '1' ELSE '0' & vdl_vft(10 DOWNTO 1); + atari_vl(26 DOWNTO 16) WHEN atari_sync = '1' AND vdl_vmd(2) = '1' ELSE + atari_vh(26 DOWNTO 16) WHEN atari_sync = '1' ELSE '0' & vdl_vft(10 DOWNTO 1); last <= '1' WHEN vhcnt = h_total - 10 ELSE '0'; @@ -781,7 +789,7 @@ BEGIN BEGIN WAIT UNTIL rising_edge(clk_pixel_i); IF st_clut = '1' THEN - ccsel <= "000"; -- For information only. + ccsel <= "000"; -- for information only. ELSIF falcon_clut = '1' THEN ccsel <= "001"; ELSIF fbee_clut = '1' THEN @@ -825,7 +833,7 @@ BEGIN dpo_off <= '0'; END IF; - disp_on <= (disp_on AND NOT dpo_off) or (dpo_on AND dpo_zl); + disp_on <= (disp_on AND NOT dpo_off) OR (dpo_on AND dpo_zl); -- Data transfer on/off: IF vhcnt = hdis_start - 1 THEN @@ -841,14 +849,14 @@ BEGIN END IF; IF last = '1' AND vvcnt >= vdis_start - 1 AND vvcnt < vdis_end THEN - vdo_zl <= '1'; -- Take over at the END of the line. + vdo_zl <= '1'; -- Take over at the END of the line. ELSIF last = '1' THEN - vdo_zl <= '0'; -- 1 ZEILE DAVOR ON OFF + vdo_zl <= '0'; -- 1 ZEILE DAVOR ON OFF END IF; - vdtron <= (vdtron AND NOT vdo_off) or (vdo_on AND vdo_zl); + vdtron <= (vdtron AND NOT vdo_off) OR (vdo_on AND vdo_zl); - -- Delay AND SYNC + -- Delay and sync IF vhcnt = hs_start - 11 THEN hsync_start <= '1'; ELSE @@ -867,15 +875,15 @@ BEGIN vsync_start <= '0'; END IF; - IF last = '1' AND vsync_start = '1' THEN -- Start at the END of the line before vsync. - vsync_i <= "011"; -- 3 lines vsync length. + IF last = '1' AND vsync_start = '1' THEN -- Start at the end of the line before vsync. + vsync_i <= "011"; -- 3 lines vsync length. ELSIF last = '1' AND vsync_i > "000" THEN vsync_i <= vsync_i - 1; -- Count down. END IF; IF fbee_vctr(15) = '1' AND vdl_vct(5) = '1' AND vsync_i = "000" THEN verz_2 <= verz_2(8 DOWNTO 0) & '1'; - ELSIF (fbee_vctr(15) = '0' or vdl_vct(5) = '0') AND vsync_i /= "000" THEN + ELSIF (fbee_vctr(15) = '0' OR vdl_vct(5) = '0') AND vsync_i /= "000" THEN verz_2 <= verz_2(8 DOWNTO 0) & '1'; ELSE verz_2 <= verz_2(8 DOWNTO 0) & '0'; @@ -892,7 +900,7 @@ BEGIN blank_n <= verz_0(8); hsync <= verz_1(9); vsync <= verz_2(9); - sync_n <= NOT(verz_2(9) or verz_1(9)); + sync_n <= NOT(verz_2(9) OR verz_1(9)); -- border colours: border <= border(5 DOWNTO 0) & (disp_on AND NOT vdtron AND fbee_vctr(25)); @@ -946,7 +954,7 @@ BEGIN fifo_rde <= '1'; ELSIF vdtron = '1' AND sub_pixel_cnt(1 DOWNTO 0) = "01" AND color24_i = '1' THEN fifo_rde <= '1'; - ELSIF sync_pix = '1' or sync_pix1 = '1' or sync_pix2 = '1' THEN + ELSIF sync_pix = '1' OR sync_pix1 = '1' OR sync_pix2 = '1' THEN fifo_rde <= '1'; -- 3 CLOCK ZUS�TZLICH F�R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION ELSE fifo_rde <= '0'; diff --git a/vhdl/rtl/vhdl/io_register.vhd b/vhdl/rtl/vhdl/io_register.vhd index cf07b1f..7251096 100644 --- a/vhdl/rtl/vhdl/io_register.vhd +++ b/vhdl/rtl/vhdl/io_register.vhd @@ -3,18 +3,19 @@ LIBRARY IEEE; USE IEEE.numeric_std.ALL; PACKAGE io_register_pkg IS - TYPE access_width_t IS (LONGWORD, WORD, BYTE); + TYPE access_type_t IS (LONGWORD_ACCESS, WORD_ACCESS, BYTE_ACCESS); COMPONENT io_register IS GENERIC ( - address : IN UNSIGNED (31 DOWNTO 0); - address_mask : IN UNSIGNED (31 DOWNTO 0) + sensitive : IN unsigned (31 DOWNTO 0); + address_mask : IN unsigned (31 DOWNTO 0) ); PORT ( - address_bus : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - access_type : IN access_width_t + address : IN std_logic_vector (31 DOWNTO 0); + access_type : IN access_type_t; + chip_select : OUT std_logic ); END COMPONENT; END PACKAGE; @@ -29,13 +30,14 @@ LIBRARY work; ENTITY io_register IS GENERIC ( - address : IN UNSIGNED (31 DOWNTO 0); - address_mask : IN UNSIGNED (31 DOWNTO 0) + sensitive : IN unsigned (31 DOWNTO 0); + address_mask : IN unsigned (31 DOWNTO 0) ); PORT ( - address_bus : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - access_type : IN access_width_t + address : IN std_logic_vector (31 DOWNTO 0); + access_type : IN access_type_t; + chip_select : OUT std_logic ); END ENTITY io_register; @@ -44,8 +46,8 @@ ARCHITECTURE rtl OF io_register IS BEGIN register_select : PROCESS BEGIN - /* IF (address_bus AND address_mask) = (address AND address_mask) THEN + /* IF (address AND address_mask) = (address AND address_mask) THEN sel <= '1'; END IF; */ END PROCESS register_select; -END rtl; \ No newline at end of file +END rtl; diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd index 4a0935e..bca7d61 100644 --- a/vhdl/testbenches/ddr_ctlr_tb.vhd +++ b/vhdl/testbenches/ddr_ctlr_tb.vhd @@ -14,47 +14,47 @@ END ddr_ctlr_tb; ARCHITECTURE beh OF ddr_ctlr_tb IS - SIGNAL clock : STD_LOGIC := '0'; -- main clock - SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock + SIGNAL clock : std_logic := '0'; -- main clock + SIGNAL ddr_clk : std_logic := '0'; -- ddr clock - SIGNAL fb_adr : UNSIGNED(31 DOWNTO 0); - SIGNAL ddr_sync_66m : STD_LOGIC := '0'; - SIGNAL fb_cs1_n : STD_LOGIC; - SIGNAL fb_oe_n : STD_LOGIC := '1'; -- only write cycles for now - SIGNAL fb_size0 : STD_LOGIC := '1'; - SIGNAL fb_size1 : STD_LOGIC := '1'; -- long word access - SIGNAL fb_ale : STD_LOGIC := 'Z'; -- defined reset state - SIGNAL fb_wr_n : STD_LOGIC; - SIGNAL fifo_clr : STD_LOGIC; - SIGNAL video_ram_ctr : UNSIGNED(15 DOWNTO 0); - SIGNAL blitter_adr : UNSIGNED(31 DOWNTO 0); - SIGNAL blitter_sig : STD_LOGIC; - SIGNAL blitter_wr : STD_LOGIC; - SIGNAL ddrclk0 : STD_LOGIC; - SIGNAL clk_33m : STD_LOGIC := '0'; - SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0'); - SIGNAL va : UNSIGNED(12 DOWNTO 0); - SIGNAL vwe_n : STD_LOGIC; - SIGNAL vras_n : STD_LOGIC; - SIGNAL vcs_n : STD_LOGIC; - SIGNAL vcke : STD_LOGIC; - SIGNAL vcas_n : STD_LOGIC; - SIGNAL fb_le : UNSIGNED(3 DOWNTO 0); - SIGNAL fb_vdoe : UNSIGNED(3 DOWNTO 0); - SIGNAL sr_fifo_wre : STD_LOGIC; - SIGNAL sr_ddr_fb : STD_LOGIC; - SIGNAL sr_ddr_wr : STD_LOGIC; - SIGNAL sr_ddrwr_d_sel : STD_LOGIC; - SIGNAL sr_vdmp : UNSIGNED(7 DOWNTO 0); - SIGNAL video_ddr_ta : STD_LOGIC; - SIGNAL sr_blitter_dack : STD_LOGIC; - SIGNAL ba : UNSIGNED(1 DOWNTO 0); - SIGNAL ddrwr_d_sel1 : STD_LOGIC; - SIGNAL vdm_sel : UNSIGNED(3 DOWNTO 0); - SIGNAL data_in : UNSIGNED(31 DOWNTO 0); - SIGNAL data_out : UNSIGNED(31 DOWNTO 16); - SIGNAL data_en_h : STD_LOGIC; - SIGNAL data_en_l : STD_LOGIC; + SIGNAL fb_adr : unsigned(31 DOWNTO 0); + SIGNAL ddr_sync_66m : std_logic := '0'; + SIGNAL fb_cs1_n : std_logic; + SIGNAL fb_oe_n : std_logic := '1'; -- only write cycles for now + SIGNAL fb_size0 : std_logic := '1'; + SIGNAL fb_size1 : std_logic := '1'; -- long word access + SIGNAL fb_ale : std_logic := 'Z'; -- defined reset state + SIGNAL fb_wr_n : std_logic; + SIGNAL fifo_clr : std_logic; + SIGNAL video_ram_ctr : unsigned(15 DOWNTO 0); + SIGNAL blitter_adr : unsigned(31 DOWNTO 0); + SIGNAL blitter_sig : std_logic; + SIGNAL blitter_wr : std_logic; + SIGNAL ddrclk0 : std_logic; + SIGNAL clk_33m : std_logic := '0'; + SIGNAL fifo_mw : unsigned (8 DOWNTO 0) := (OTHERS => '0'); + SIGNAL va : unsigned(12 DOWNTO 0); + SIGNAL vwe_n : std_logic; + SIGNAL vras_n : std_logic; + SIGNAL vcs_n : std_logic; + SIGNAL vcke : std_logic; + SIGNAL vcas_n : std_logic; + SIGNAL fb_le : unsigned(3 DOWNTO 0); + SIGNAL fb_vdoe : unsigned(3 DOWNTO 0); + SIGNAL sr_fifo_wre : std_logic; + SIGNAL sr_ddr_fb : std_logic; + SIGNAL sr_ddr_wr : std_logic; + SIGNAL sr_ddrwr_d_sel : std_logic; + SIGNAL sr_vdmp : unsigned(7 DOWNTO 0); + SIGNAL video_ddr_ta : std_logic; + SIGNAL sr_blitter_dack : std_logic; + SIGNAL ba : unsigned(1 DOWNTO 0); + SIGNAL ddrwr_d_sel1 : std_logic; + SIGNAL vdm_sel : unsigned(3 DOWNTO 0); + SIGNAL data_in : unsigned(31 DOWNTO 0); + SIGNAL data_out : unsigned(31 DOWNTO 16); + SIGNAL data_en_h : std_logic; + SIGNAL data_en_l : std_logic; TYPE bus_state_t IS (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual SIGNAL bus_state : bus_state_t := S0; @@ -188,7 +188,7 @@ BEGIN END process; stimulate : process - VARIABLE adr : UNSIGNED (31 DOWNTO 0) := x"00000000"; + VARIABLE adr : unsigned (31 DOWNTO 0) := x"00000000"; BEGIN WAIT UNTIL RISING_EDGE(clock); CASE bus_state IS diff --git a/vhdl/testbenches/ddr_ram_model.vhd b/vhdl/testbenches/ddr_ram_model.vhd index e269e5b..f1093ec 100644 --- a/vhdl/testbenches/ddr_ram_model.vhd +++ b/vhdl/testbenches/ddr_ram_model.vhd @@ -23,19 +23,19 @@ PACKAGE ddr_ram_model_pkg IS ); PORT ( - dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0); - ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0); - ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0); - rasb : IN STD_LOGIC; - casb : IN STD_LOGIC; - web : IN STD_LOGIC; - clk : IN STD_LOGIC; - clkb : IN STD_LOGIC; - cke : IN STD_LOGIC; - csb : IN STD_LOGIC; - dm : IN UNSIGNED (NDM - 1 DOWNTO 0); - dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0); - qfc : OUT STD_LOGIC + dqi : INOUT std_logic_vector (B - 1 DOWNTO 0); + ba : IN unsigned (NBANK / 2 - 1 DOWNTO 0); + ad : IN std_logic_vector (ADDRTOP DOWNTO 0); + rasb : IN std_logic; + casb : IN std_logic; + web : IN std_logic; + clk : IN std_logic; + clkb : IN std_logic; + cke : IN std_logic; + csb : IN std_logic; + dm : IN unsigned (NDM - 1 DOWNTO 0); + dqs : INOUT std_logic_vector (NDQS - 1 DOWNTO 0); + qfc : OUT std_logic ); END COMPONENT; @@ -60,151 +60,249 @@ ENTITY ddr_ram_model IS CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick - NBANK : INTEGER := 4; - ADDRTOP : INTEGER := 12; - A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10 - B : INTEGER := 16; -- number of bit (x16) - NCOL : INTEGER := 10; -- top column address is CA9 (NCOL - 1) - PAGEDEPTH : INTEGER := 1024; - NDM : INTEGER := 2; - NDQS : INTEGER := 2 + NBANK : INTEGER := 4; + ADDRTOP : INTEGER := 12; + A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10 + B : INTEGER := 16; -- number of bit (x16) + NCOL : INTEGER := 10; -- top column address is CA9 (NCOL - 1) + PAGEDEPTH : INTEGER := 1024; + NDM : INTEGER := 2; + NDQS : INTEGER := 2 ); PORT ( - dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0); - ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0); - ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0); - rasb : IN STD_LOGIC; - casb : IN STD_LOGIC; - web : IN STD_LOGIC; - clk : IN STD_LOGIC; - clkb : IN STD_LOGIC; - cke : IN STD_LOGIC; - csb : IN STD_LOGIC; - dm : IN UNSIGNED (NDM - 1 DOWNTO 0); - dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0); - qfc : OUT STD_LOGIC + dqi : INOUT std_logic_vector (B - 1 DOWNTO 0); + ba : IN unsigned (NBANK / 2 - 1 DOWNTO 0); + ad : IN std_logic_vector (ADDRTOP DOWNTO 0); + rasb : IN std_logic; + casb : IN std_logic; + web : IN std_logic; + clk : IN std_logic; + clkb : IN std_logic; + cke : IN std_logic; + csb : IN std_logic; + dm : IN unsigned (NDM - 1 DOWNTO 0); + dqs : INOUT std_logic_vector (NDQS - 1 DOWNTO 0); + qfc : OUT std_logic ); END ENTITY ddr_ram_model; ARCHITECTURE rtl OF ddr_ram_model IS -- DDR RAM timing constants - CONSTANT TRC : TIME := 65 ps; -- row cycle time (min) - CONSTANT TRFC : TIME := 115 ps; -- Refresh Row cycle time (min) - CONSTANT TRASMIN : TIME := 45 ps; -- Row active minimum time - CONSTANT TRASMAX : TIME := 120000 ps; -- Row active maximum time - CONSTANT TRCD : TIME := 20 ps; -- Ras to cas delay (min) - CONSTANT TRP : TIME := 20 ps; -- Row precharge time (min) - CONSTANT TRRD : TIME := 15 ps; -- Row to row delay (min) + CONSTANT TRC : TIME := 65 ps; -- row cycle time (min) + CONSTANT TRFC : TIME := 115 ps; -- Refresh Row cycle time (min) + CONSTANT TRASMIN : TIME := 45 ps; -- Row active minimum time + CONSTANT TRASMAX : TIME := 120000 ps; -- Row active maximum time + CONSTANT TRCD : TIME := 20 ps; -- Ras to cas delay (min) + CONSTANT TRP : TIME := 20 ps; -- Row precharge time (min) + CONSTANT TRRD : TIME := 15 ps; -- Row to row delay (min) - CONSTANT TCCD : TIME := CLOCK_TICK; -- Col. address to col. address delay: 1 clk + CONSTANT TCCD : TIME := CLOCK_TICK; -- Col. address to col. address delay: 1 clk - CONSTANT TCKMIN : TIME := 7.5 ps; -- Clock minimum cycle time - CONSTANT TCKMAX : TIME := 12 ps; -- Clock maximum cycle time - CONSTANT TCK15 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=1.5 - CONSTANT TCK2 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=2 - CONSTANT TCK25 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=2.5 - CONSTANT TCK3 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=3 - CONSTANT TCHMIN : TIME := 0.45 ps; -- Clock high pulse width (min. 0.45 tCK, max: 0.55 tCK) - CONSTANT TCHMAX : TIME := 0.55 ps; - CONSTANT TCLMIN : TIME := 0.45 ps; -- Clock low pulse width (min. 0.45 tCK, max: 0.55 tCK) - CONSTANT TCLMAX : TIME := 0.55 ps; - CONSTANT TIS : TIME := 0.9 ps; -- input setup time (old Tss) - CONSTANT TIH : TIME := 0.9 ps; -- input hold time (old Tsh) - CONSTANT TWR : TIME := 15 ps; -- write recovery time - CONSTANT TDS : TIME := 0.5 ps; -- Data in & DQM setup time - CONSTANT TDH : TIME := 0.5 ps; -- Data in & DQM hold time - CONSTANT TDQSH : TIME := 0.6 ps; -- DQS-in high level width (min. 0.4 tCK, max. 0.6 tCK) - CONSTANT TDQSL : TIME := 0.6 ps; -- - CONSTANT TDSC : TIME := 1 ps; -- DQS-in cycle time tCIC changed following tDSC - CONSTANT TPDEX : TIME := 7.5 ps; -- Power down exit time - CONSTANT TSREX : TIME := 200 ps; -- Self refresh exit time : 200 clk - CONSTANT THZQ : TIME := 0.75 ps; -- Data out active to High-Z (min:-0.75, max: +0.75) - CONSTANT TDQSCK : TIME := 0.75 ps; -- DQS out edge to clock edge - CONSTANT TAC : TIME := 0.75 ps; -- Output data access time from CK/CKB (min: -0.75, max: +0.75) - CONSTANT TQCSW : TIME := 3.5 ps; -- Delay from the clock edge of write command to QFC out on writes (max: 4ns) - CONSTANT TQCHW : TIME := 0.5 ps; -- QFC hold time on writes (min 1.25 ns, max: 0.5 tCK) - CONSTANT TQCH : TIME := 0.4 ps; -- QFC hold time on reads (min 0.4 tCK, max 0.6 tCK) - CONSTANT TQCS : TIME := 0.9 ps; -- QFC setup time on reads (min: 0.9 tCK, max 1.1 tCK) + CONSTANT TCKMIN : TIME := 7.5 ps; -- Clock minimum cycle time + CONSTANT TCKMAX : TIME := 12 ps; -- Clock maximum cycle time + CONSTANT TCK15 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=1.5 + CONSTANT TCK2 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=2 + CONSTANT TCK25 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=2.5 + CONSTANT TCK3 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=3 + CONSTANT TCHMIN : TIME := 0.45 ps; -- Clock high pulse width (min. 0.45 tCK, max: 0.55 tCK) + CONSTANT TCHMAX : TIME := 0.55 ps; + CONSTANT TCLMIN : TIME := 0.45 ps; -- Clock low pulse width (min. 0.45 tCK, max: 0.55 tCK) + CONSTANT TCLMAX : TIME := 0.55 ps; + CONSTANT TIS : TIME := 0.9 ps; -- input setup time (old Tss) + CONSTANT TIH : TIME := 0.9 ps; -- input hold time (old Tsh) + CONSTANT TWR : TIME := 15 ps; -- write recovery time + CONSTANT TDS : TIME := 0.5 ps; -- Data in & DQM setup time + CONSTANT TDH : TIME := 0.5 ps; -- Data in & DQM hold time + CONSTANT TDQSH : TIME := 0.6 ps; -- DQS-in high level width (min. 0.4 tCK, max. 0.6 tCK) + CONSTANT TDQSL : TIME := 0.6 ps; -- + CONSTANT TDSC : TIME := 1 ps; -- DQS-in cycle time tCIC changed following tDSC + CONSTANT TPDEX : TIME := 7.5 ps; -- Power down exit time + CONSTANT TSREX : TIME := 200 ps; -- Self refresh exit time : 200 clk + CONSTANT THZQ : TIME := 0.75 ps; -- Data out active to High-Z (min:-0.75, max: +0.75) + CONSTANT TDQSCK : TIME := 0.75 ps; -- DQS out edge to clock edge + CONSTANT TAC : TIME := 0.75 ps; -- Output data access time from CK/CKB (min: -0.75, max: +0.75) + CONSTANT TQCSW : TIME := 3.5 ps; -- Delay from the clock edge of write command to QFC out on writes (max: 4ns) + CONSTANT TQCHW : TIME := 0.5 ps; -- QFC hold time on writes (min 1.25 ns, max: 0.5 tCK) + CONSTANT TQCH : TIME := 0.4 ps; -- QFC hold time on reads (min 0.4 tCK, max 0.6 tCK) + CONSTANT TQCS : TIME := 0.9 ps; -- QFC setup time on reads (min: 0.9 tCK, max 1.1 tCK) - CONSTANT K1 : INTEGER := 1024; - CONSTANT M1 : INTEGER := 1048576; - CONSTANT BYTE : INTEGER := 8; + CONSTANT K1 : INTEGER := 1024; + CONSTANT M1 : INTEGER := 1048576; + CONSTANT BYTE : INTEGER := 8; - CONSTANT TBITS : INTEGER := 512 * M1; + CONSTANT TBITS : INTEGER := 512 * M1; - --SIGNAL BITs : UNSIGNED (B - 1 DOWNTO 0); - CONSTANT BIT_C : INTEGER := NCOL - 1; - CONSTANT NWORD : INTEGER := TBITS / B / NBANK; - CONSTANT BIT_T : INTEGER := NCOL + ADDRTOP; - CONSTANT WORD : INTEGER := NWORD - 1; + --SIGNAL BITs : unsigned (B - 1 DOWNTO 0); + CONSTANT BIT_C : INTEGER := NCOL - 1; + CONSTANT NWORD : INTEGER := TBITS / B / NBANK; + CONSTANT BIT_T : INTEGER := NCOL + ADDRTOP; + CONSTANT WORD : INTEGER := NWORD - 1; - CONSTANT HB : INTEGER := B / 2; + CONSTANT HB : INTEGER := B / 2; - CONSTANT PWRUP_TIME : INTEGER := 0; - CONSTANT PWUP_CHECK : STD_LOGIC := '1'; + CONSTANT PWRUP_TIME : INTEGER := 0; + CONSTANT PWUP_CHECK : std_logic := '1'; - CONSTANT INITIAL : INTEGER := 0; - CONSTANT HIGH : INTEGER := 1; - CONSTANT LOW : INTEGER := 0; + CONSTANT INITIAL : INTEGER := 0; + CONSTANT HIGH : INTEGER := 1; + CONSTANT LOW : INTEGER := 0; - SIGNAL addr : STD_LOGIC_VECTOR (NBANK / 2 + ADDRTOP DOWNTO 0); + SIGNAL addr : std_logic_vector (NBANK / 2 + ADDRTOP DOWNTO 0); - TYPE mem_array_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(B - 1 DOWNTO 0); - SIGNAL mem_a : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of a bank - SIGNAL mem_b : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of b bank - SIGNAL mem_c : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of c bank - SIGNAL mem_d : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of d bank + TYPE mem_array_t IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(B - 1 DOWNTO 0); + SIGNAL mem_a : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of a bank + SIGNAL mem_b : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of b bank + SIGNAL mem_c : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of c bank + SIGNAL mem_d : mem_array_t (NWORD - 1 DOWNTO 0); -- memory cell array of d bank - SIGNAL t_dqi : UNSIGNED (B - 1 DOWNTO 0); - SIGNAL dqsi : UNSIGNED (NDQS - 1 DOWNTO 0); - SIGNAL dqsi_n : UNSIGNED (NDQS - 1 DOWNTO 0); + SIGNAL t_dqi : unsigned (B - 1 DOWNTO 0); + SIGNAL dqsi : unsigned (NDQS - 1 DOWNTO 0); + SIGNAL dqsi_n : unsigned (NDQS - 1 DOWNTO 0); - SIGNAL dqo : UNSIGNED (B - 1 DOWNTO 0); -- output temp register declaration - SIGNAL t_tqo : UNSIGNED (B - 1 DOWNTO 0); + SIGNAL dqo : unsigned (B - 1 DOWNTO 0); -- output temp register declaration + SIGNAL t_tqo : unsigned (B - 1 DOWNTO 0); - TYPE r_addr_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (NBANK - 1 DOWNTO 0); + TYPE r_addr_t IS ARRAY (NATURAL RANGE <>) OF unsigned (NBANK - 1 DOWNTO 0); SIGNAL r_addr_n : r_addr_t (ADDRTOP DOWNTO 0); - SIGNAL r_addr : UNSIGNED (ADDRTOP DOWNTO 0); - SIGNAL c_addr : UNSIGNED (BIT_C DOWNTO 0); - SIGNAL c_addr_delay : UNSIGNED (BIT_C DOWNTO 0); - SIGNAL c_addr_delay_bf : UNSIGNED (BIT_C DOWNTO 0); - SIGNAL m_addr : UNSIGNED (BIT_T DOWNTO 0); -- merge row and column address - SIGNAL m1_addr : UNSIGNED (BIT_T DOWNTO 0); -- merge row and column address pseudo + SIGNAL r_addr : unsigned (ADDRTOP DOWNTO 0); + SIGNAL c_addr : unsigned (BIT_C DOWNTO 0); + SIGNAL c_addr_delay : unsigned (BIT_C DOWNTO 0); + SIGNAL c_addr_delay_bf : unsigned (BIT_C DOWNTO 0); + SIGNAL m_addr : unsigned (BIT_T DOWNTO 0); -- merge row and column address + SIGNAL m1_addr : unsigned (BIT_T DOWNTO 0); -- merge row and column address pseudo - TYPE d_reg_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (PAGEDEPTH DOWNTO 0); - SIGNAL dout_reg : UNSIGNED (B - 1 DOWNTO 0); - SIGNAL din_reg : UNSIGNED (B - 1 DOWNTO 0); - SIGNAL clk_dq : UNSIGNED (B - 1 DOWNTO 0); - SIGNAL ptr : STD_LOGIC; - SIGNAL zdata : UNSIGNED(B - 1 DOWNTO 0); - SIGNAL zbyte : UNSIGNED(7 DOWNTO 0); + TYPE d_reg_t IS ARRAY (NATURAL RANGE <>) OF unsigned (PAGEDEPTH DOWNTO 0); + SIGNAL dout_reg : unsigned (B - 1 DOWNTO 0); + SIGNAL din_reg : unsigned (B - 1 DOWNTO 0); + SIGNAL clk_dq : unsigned (B - 1 DOWNTO 0); + SIGNAL ptr : std_logic; + SIGNAL zdata : unsigned(B - 1 DOWNTO 0); + SIGNAL zbyte : unsigned(7 DOWNTO 0); -- we know the phase of external signal by examining the state of its flag - SIGNAL r_bank_addr : STD_LOGIC; - SIGNAL c_bank_addr : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag - SIGNAL c_bank_addr_delay : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag - SIGNAL c_bank_addr_delay_bf : UNSIGNED (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag - SIGNAL prech_reg : UNSIGNED (NBANK / 2 DOWNTO 0); -- precharge mode (addr (13 DOWNTO 12) AND (addr(10)) + SIGNAL r_bank_addr : std_logic; + SIGNAL c_bank_addr : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag + SIGNAL c_bank_addr_delay : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag + SIGNAL c_bank_addr_delay_bf : unsigned (NBANK / 2 - 1 DOWNTO 0); -- column bank check flag + SIGNAL prech_reg : unsigned (NBANK / 2 DOWNTO 0); -- precharge mode (addr (13 DOWNTO 12) AND (addr(10)) - SIGNAL auto_flag : UNSIGNED (NBANK - 1 DOWNTO 0); - SIGNAL burst_type : STD_LOGIC; -- burst type flag - SIGNAL auto_flagx : STD_LOGIC; -- auto refresh flag - SIGNAL self_flag : STD_LOGIC; -- self refresh flag + SIGNAL auto_flag : BOOLEAN_VECTOR (NBANK - 1 DOWNTO 0); + SIGNAL burst_type : std_logic; -- burst type flag + SIGNAL auto_flagx : BOOLEAN; -- auto refresh flag + SIGNAL self_flag : BOOLEAN; -- self refresh flag SIGNAL kill_bank : INTEGER; SIGNAL k : INTEGER; - SIGNAL precharge_flag : UNSIGNED (NBANK - 1 DOWNTO 0); -- precharge bank check flag - SIGNAL autoprech_reg : UNSIGNED (1 DOWNTO 0); - SIGNAL pwrup_done : STD_LOGIC; - SIGNAL first_pre : UNSIGNED (NBANK - 1 DOWNTO 0); + SIGNAL precharge_flag : unsigned (NBANK - 1 DOWNTO 0); -- precharge bank check flag + SIGNAL autoprech_reg : unsigned (1 DOWNTO 0); + SIGNAL pwrup_done : BOOLEAN; + SIGNAL first_pre : BOOLEAN_VECTOR (NBANK - 1 DOWNTO 0); SIGNAL auto_cnt : INTEGER; SIGNAL i : INTEGER; - SIGNAL rfu : UNSIGNED (6 DOWNTO 0); -BEGIN - addr <= STD_LOGIC_VECTOR(ba) & ad; - rfu <= UNSIGNED(addr(14 DOWNTO 9)) & UNSIGNED(addr(7 DOWNTO 7)); + SIGNAL rfu : unsigned (6 DOWNTO 0); + + SIGNAL mode : unsigned (NBANK - 1 DOWNTO 0); + SIGNAL prdl : unsigned (NBANK - 1 DOWNTO 0); + SIGNAL ignore_rdl : unsigned (NBANK - 1 DOWNTO 0); + + SIGNAL bl : INTEGER; -- burst_length + SIGNAL wbl : INTEGER; + + SIGNAL cl : INTEGER; -- CAS latency + SIGNAL cl_tmp : INTEGER; + SIGNAL cl_org : INTEGER; + SIGNAL cl_tmp2 : INTEGER; + + SIGNAL write_event : BOOLEAN; + SIGNAL autoprecharge_WIRevent : BOOLEAN; + SIGNAL write_mode_flag : BOOLEAN; + SIGNAL dqsi_flag : BOOLEAN; + SIGNAL dqsi_flag_u : BOOLEAN; + SIGNAL write_start : BOOLEAN; + + SIGNAL tdss_min : INTEGER; + SIGNAL tdss_max : INTEGER; + + SIGNAL tshz : INTEGER; -- clk to output in hi-z + SIGNAL tsac : INTEGER; -- clk to valid output + + SIGNAL reautoprecharge : BOOLEAN; + + TYPE event_record_t IS RECORD + kkk_event : BOOLEAN; + read_event : BOOLEAN; + write_event : BOOLEAN; + write_pre_event : BOOLEAN; + write_mode_event : BOOLEAN; + write_mode_del_event : BOOLEAN; + write_task_event : BOOLEAN; + flush_write_event : BOOLEAN; + precharge_event : BOOLEAN; + autoprecharge_event : BOOLEAN; + autoprecharge_a_event : BOOLEAN; + autoprecharge_b_event : BOOLEAN; + autoprecharge_c_event : BOOLEAN; + autoprecharge_d_event : BOOLEAN; + autoprecharge_write_event : BOOLEAN; + autoprecharge_write_a_event : BOOLEAN; + autoprecharge_write_b_event : BOOLEAN; + autoprecharge_write_c_event : BOOLEAN; + autoprecharge_write_d_event : BOOLEAN; + autoprecharge_write_int_event : BOOLEAN; + autoprecharge_write_int2_event : BOOLEAN; + precharge_start_event : BOOLEAN; + precharge_start_kill_event : BOOLEAN; + autorefresh_event : BOOLEAN; + autostart_event : BOOLEAN; + selfrefresh_event : BOOLEAN; + selfexit_event : BOOLEAN; + rdl_start_a_event : BOOLEAN; + rdl_start_b_event : BOOLEAN; + rdl_start_c_event : BOOLEAN; + rdl_start_d_event : BOOLEAN; + END RECORD; + + SIGNAL events : event_record_t; +BEGIN + p_initial : PROCESS + BEGIN + FOR i IN 0 TO NDQS - 1 LOOP + dqs(i) <= '1'; + END LOOP; + + FOR i IN 0 TO NBANK LOOP + auto_flag(i) <= FALSE; + END LOOP; + + auto_flagx <= FALSE; + reautoprecharge <= FALSE; + self_flag <= FALSE; + events.write_event <= FALSE; + autoprecharge_WIRevent <= FALSE; + write_mode_flag <= FALSE; + pwrup_done <= FALSE; + dqsi_flag <= FALSE; + dqsi_flag_u <= FALSE; + mode <= TO_UNSIGNED(0, mode'LENGTH) OR TO_UNSIGNED(NBANK, 3)(0); + prdl <= TO_UNSIGNED(0, mode'LENGTH) OR TO_UNSIGNED(NBANK, 3)(0); + + FOR i IN 0 TO NBANK LOOP + first_pre(i) <= FALSE; + precharge_flag(i) <= FALSE; + END LOOP; + zbyte <= (OTHERS => 'Z'); + + FOR i IN 0 TO B LOOP + zdata(i) <= '1'; + END LOOP; + + WAIT; + END PROCESS p_initial; + + addr <= std_logic_vector(ba) & ad; + rfu <= unsigned(addr(14 DOWNTO 9)) & unsigned(addr(7 DOWNTO 7)); END rtl; diff --git a/vhdl/testbenches/firebee_tb.vhd b/vhdl/testbenches/firebee_tb.vhd index b44b2f4..bc20f15 100644 --- a/vhdl/testbenches/firebee_tb.vhd +++ b/vhdl/testbenches/firebee_tb.vhd @@ -16,319 +16,319 @@ END firebee_tb; ARCHITECTURE beh OF firebee_tb IS COMPONENT firebee IS PORT( - rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire - clk_33m : IN STD_LOGIC; -- 33 MHz clock - clk_main : IN STD_LOGIC; -- 33 MHz clock + rsto_mcf_n : IN std_logic; -- reset SIGNAL from Coldfire + clk_33m : IN std_logic; -- 33 MHz clock + clk_main : IN std_logic; -- 33 MHz clock - clk_24m576 : OUT STD_LOGIC; -- - clk_25m : OUT STD_LOGIC; - clk_ddr_out : OUT STD_LOGIC; - clk_ddr_out_n : OUT STD_LOGIC; - clk_usb : OUT STD_LOGIC; + clk_24m576 : OUT std_logic; -- + clk_25m : OUT std_logic; + clk_ddr_out : OUT std_logic; + clk_ddr_out_n : OUT std_logic; + clk_usb : OUT std_logic; - fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); - fb_ale : IN STD_LOGIC; - fb_burst_n : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1); - fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - fb_oe_n : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; - fb_ta_n : OUT STD_LOGIC; + fb_ad : INOUT std_logic_vector (31 DOWNTO 0); + fb_ale : IN std_logic; + fb_burst_n : IN std_logic; + fb_cs_n : IN std_logic_vector (3 DOWNTO 1); + fb_size : IN std_logic_vector (1 DOWNTO 0); + fb_oe_n : IN std_logic; + fb_wr_n : IN std_logic; + fb_ta_n : OUT std_logic; - dack1_n : IN STD_LOGIC; - dreq1_n : OUT STD_LOGIC; + dack1_n : IN std_logic; + dreq1_n : OUT std_logic; - master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. - tout0_n : IN STD_LOGIC; -- Not used so far. + master_n : IN std_logic; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. + tout0_n : IN std_logic; -- Not used so far. - led_fpga_ok : OUT STD_LOGIC; - reserved_1 : OUT STD_LOGIC; + led_fpga_ok : OUT std_logic; + reserved_1 : OUT std_logic; - va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); - ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - vwe_n : OUT STD_LOGIC; - vcas_n : OUT STD_LOGIC; - vras_n : OUT STD_LOGIC; - vcs_n : OUT STD_LOGIC; + va : OUT std_logic_vector (12 DOWNTO 0); + ba : OUT std_logic_vector (1 DOWNTO 0); + vwe_n : OUT std_logic; + vcas_n : OUT std_logic; + vras_n : OUT std_logic; + vcs_n : OUT std_logic; - clk_pixel : OUT STD_LOGIC; - sync_n : OUT STD_LOGIC; - vsync : OUT STD_LOGIC; - hsync : OUT STD_LOGIC; - blank_n : OUT STD_LOGIC; + clk_pixel : OUT std_logic; + sync_n : OUT std_logic; + vsync : OUT std_logic; + hsync : OUT std_logic; + blank_n : OUT std_logic; - vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - vb : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + vr : OUT std_logic_vector (7 DOWNTO 0); + vg : OUT std_logic_vector (7 DOWNTO 0); + vb : OUT std_logic_vector (7 DOWNTO 0); - vdm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + vdm : OUT std_logic_vector (3 DOWNTO 0); - vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); - vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + vd : INOUT std_logic_vector (31 DOWNTO 0); + vd_qs : OUT std_logic_vector (3 DOWNTO 0); - pd_vga_n : OUT STD_LOGIC; - vcke : OUT STD_LOGIC; - pic_int : IN STD_LOGIC; - e0_int : IN STD_LOGIC; - dvi_int : IN STD_LOGIC; - pci_inta_n : IN STD_LOGIC; - pci_intb_n : IN STD_LOGIC; - pci_intc_n : IN STD_LOGIC; - pci_intd_n : IN STD_LOGIC; + pd_vga_n : OUT std_logic; + vcke : OUT std_logic; + pic_int : IN std_logic; + e0_int : IN std_logic; + dvi_int : IN std_logic; + pci_inta_n : IN std_logic; + pci_intb_n : IN std_logic; + pci_intc_n : IN std_logic; + pci_intd_n : IN std_logic; - irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2); - tin0 : OUT STD_LOGIC; + irq_n : OUT std_logic_vector (7 DOWNTO 2); + tin0 : OUT std_logic; - ym_qa : OUT STD_LOGIC; - ym_qb : OUT STD_LOGIC; - ym_qc : OUT STD_LOGIC; + ym_qa : OUT std_logic; + ym_qb : OUT std_logic; + ym_qc : OUT std_logic; - lp_d : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); - lp_dir : OUT STD_LOGIC; + lp_d : INOUT std_logic_vector (7 DOWNTO 0); + lp_dir : OUT std_logic; - dsa_d : OUT STD_LOGIC; - lp_str : OUT STD_LOGIC; - dtr : OUT STD_LOGIC; - rts : OUT STD_LOGIC; - cts : IN STD_LOGIC; - ri : IN STD_LOGIC; - dcd : IN STD_LOGIC; - lp_busy : IN STD_LOGIC; - rxd : IN STD_LOGIC; - txd : OUT STD_LOGIC; - midi_in : IN STD_LOGIC; - midi_olr : OUT STD_LOGIC; - midi_tlr : OUT STD_LOGIC; - pic_amkb_rx : IN STD_LOGIC; - amkb_rx : IN STD_LOGIC; - amkb_tx : OUT STD_LOGIC; - dack0_n : IN STD_LOGIC; -- Not used. + dsa_d : OUT std_logic; + lp_str : OUT std_logic; + dtr : OUT std_logic; + rts : OUT std_logic; + cts : IN std_logic; + ri : IN std_logic; + dcd : IN std_logic; + lp_busy : IN std_logic; + rxd : IN std_logic; + txd : OUT std_logic; + midi_in : IN std_logic; + midi_olr : OUT std_logic; + midi_tlr : OUT std_logic; + pic_amkb_rx : IN std_logic; + amkb_rx : IN std_logic; + amkb_tx : OUT std_logic; + dack0_n : IN std_logic; -- Not used. - scsi_drqn : IN STD_LOGIC; - SCSI_MSGn : IN STD_LOGIC; - SCSI_CDn : IN STD_LOGIC; - SCSI_IOn : IN STD_LOGIC; - SCSI_ACKn : OUT STD_LOGIC; - SCSI_ATNn : OUT STD_LOGIC; - SCSI_SELn : INOUT STD_LOGIC; - SCSI_BUSYn : INOUT STD_LOGIC; - SCSI_RSTn : INOUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SCSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); - SCSI_PAR : INOUT STD_LOGIC; + scsi_drqn : IN std_logic; + SCSI_MSGn : IN std_logic; + SCSI_CDn : IN std_logic; + SCSI_IOn : IN std_logic; + SCSI_ACKn : OUT std_logic; + SCSI_ATNn : OUT std_logic; + SCSI_SELn : INOUT std_logic; + SCSI_BUSYn : INOUT std_logic; + SCSI_RSTn : INOUT std_logic; + SCSI_DIR : OUT std_logic; + SCSI_D : INOUT std_logic_vector (7 DOWNTO 0); + SCSI_PAR : INOUT std_logic; - ACSI_DIR : OUT STD_LOGIC; - ACSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); - ACSI_CSn : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - ACSI_reset_n : OUT STD_LOGIC; - ACSI_ACKn : OUT STD_LOGIC; - ACSI_DRQn : IN STD_LOGIC; - ACSI_INTn : IN STD_LOGIC; + ACSI_DIR : OUT std_logic; + ACSI_D : INOUT std_logic_vector (7 DOWNTO 0); + ACSI_CSn : OUT std_logic; + ACSI_A1 : OUT std_logic; + ACSI_reset_n : OUT std_logic; + ACSI_ACKn : OUT std_logic; + ACSI_DRQn : IN std_logic; + ACSI_INTn : IN std_logic; - FDD_DCHGn : IN STD_LOGIC; - FDD_SDSELn : OUT STD_LOGIC; - FDD_HD_DD : IN STD_LOGIC; - FDD_RDn : IN STD_LOGIC; - FDD_TRACK00 : IN STD_LOGIC; - FDD_INDEXn : IN STD_LOGIC; - FDD_WPn : IN STD_LOGIC; - FDD_MOT_ON : OUT STD_LOGIC; - FDD_WR_GATE : OUT STD_LOGIC; - FDD_WDn : OUT STD_LOGIC; - FDD_STEP : OUT STD_LOGIC; - FDD_STEP_DIR : OUT STD_LOGIC; + FDD_DCHGn : IN std_logic; + FDD_SDSELn : OUT std_logic; + FDD_HD_DD : IN std_logic; + FDD_RDn : IN std_logic; + FDD_TRACK00 : IN std_logic; + FDD_INDEXn : IN std_logic; + FDD_WPn : IN std_logic; + FDD_MOT_ON : OUT std_logic; + FDD_WR_GATE : OUT std_logic; + FDD_WDn : OUT std_logic; + FDD_STEP : OUT std_logic; + FDD_STEP_DIR : OUT std_logic; - ROM4n : OUT STD_LOGIC; - ROM3n : OUT STD_LOGIC; + ROM4n : OUT std_logic; + ROM3n : OUT std_logic; - RP_UDSn : OUT STD_LOGIC; - RP_ldsn : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - SD_D3 : INOUT STD_LOGIC; - SD_CMD_D1 : INOUT STD_LOGIC; - SD_D0 : IN STD_LOGIC; - SD_D1 : IN STD_LOGIC; - SD_D2 : IN STD_LOGIC; - SD_caRD_DETECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; + RP_UDSn : OUT std_logic; + RP_ldsn : OUT std_logic; + SD_CLK : OUT std_logic; + SD_D3 : INOUT std_logic; + SD_CMD_D1 : INOUT std_logic; + SD_D0 : IN std_logic; + SD_D1 : IN std_logic; + SD_D2 : IN std_logic; + SD_caRD_DETECT : IN std_logic; + SD_WP : IN std_logic; - CF_WP : IN STD_LOGIC; - CF_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + CF_WP : IN std_logic; + CF_CSn : OUT std_logic_vector (1 DOWNTO 0); - DSP_IO : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0); - DSP_SRD : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); - DSP_SRCSn : OUT STD_LOGIC; - DSP_SRBLEn : OUT STD_LOGIC; - DSP_SRBHEn : OUT STD_LOGIC; - DSP_SRWEn : OUT STD_LOGIC; - DSP_SROEn : OUT STD_LOGIC; + DSP_IO : INOUT std_logic_vector (17 DOWNTO 0); + DSP_SRD : INOUT std_logic_vector (15 DOWNTO 0); + DSP_SRCSn : OUT std_logic; + DSP_SRBLEn : OUT std_logic; + DSP_SRBHEn : OUT std_logic; + DSP_SRWEn : OUT std_logic; + DSP_SROEn : OUT std_logic; - ide_int : IN STD_LOGIC; - ide_rdy : IN STD_LOGIC; - ide_res : OUT STD_LOGIC; - IDE_WRn : OUT STD_LOGIC; - IDE_RDn : OUT STD_LOGIC; - IDE_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ide_int : IN std_logic; + ide_rdy : IN std_logic; + ide_res : OUT std_logic; + IDE_WRn : OUT std_logic; + IDE_RDn : OUT std_logic; + IDE_CSn : OUT std_logic_vector (1 DOWNTO 0) ); END COMPONENT firebee; - SIGNAL rsto_mcf_n : STD_LOGIC := '0'; -- reset SIGNAL from Coldfire - SIGNAL clk_33m : STD_LOGIC := '0'; -- 33 MHz clock - SIGNAL clk_main : STD_LOGIC := '0'; -- 33 MHz clock + SIGNAL rsto_mcf_n : std_logic := '0'; -- reset SIGNAL from Coldfire + SIGNAL clk_33m : std_logic := '0'; -- 33 MHz clock + SIGNAL clk_main : std_logic := '0'; -- 33 MHz clock - SIGNAL clk_24m576 : STD_LOGIC; -- - SIGNAL clk_25m : STD_LOGIC; - SIGNAL clk_ddr_out : STD_LOGIC; - SIGNAL clk_ddr_out_n : STD_LOGIC; - SIGNAL clk_usb : STD_LOGIC; + SIGNAL clk_24m576 : std_logic; -- + SIGNAL clk_25m : std_logic; + SIGNAL clk_ddr_out : std_logic; + SIGNAL clk_ddr_out_n : std_logic; + SIGNAL clk_usb : std_logic; - SIGNAL fb_ad : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL fb_ale : STD_LOGIC; - SIGNAL fb_burst_n : STD_LOGIC := '1'; - SIGNAL fb_cs_n : STD_LOGIC_VECTOR (3 DOWNTO 1) := "111"; - SIGNAL fb_size : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - SIGNAL fb_oe_n : STD_LOGIC := '1'; - SIGNAL fb_wr_n : STD_LOGIC := '1'; - SIGNAL fb_ta_n : STD_LOGIC := '1'; + SIGNAL fb_ad : std_logic_vector (31 DOWNTO 0); + SIGNAL fb_ale : std_logic; + SIGNAL fb_burst_n : std_logic := '1'; + SIGNAL fb_cs_n : std_logic_vector (3 DOWNTO 1) := "111"; + SIGNAL fb_size : std_logic_vector (1 DOWNTO 0) := "00"; + SIGNAL fb_oe_n : std_logic := '1'; + SIGNAL fb_wr_n : std_logic := '1'; + SIGNAL fb_ta_n : std_logic := '1'; - SIGNAL dack1_n : STD_LOGIC; - SIGNAL dreq1_n : STD_LOGIC; + SIGNAL dack1_n : std_logic; + SIGNAL dreq1_n : std_logic; - SIGNAL master_n : STD_LOGIC := '0'; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. - SIGNAL tout0_n : STD_LOGIC; -- Not used so far. + SIGNAL master_n : std_logic := '0'; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far. + SIGNAL tout0_n : std_logic; -- Not used so far. - SIGNAL led_fpga_ok : STD_LOGIC; - SIGNAL reserved_1 : STD_LOGIC; + SIGNAL led_fpga_ok : std_logic; + SIGNAL reserved_1 : std_logic; - SIGNAL va : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL ba : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL vwe_n : STD_LOGIC; - SIGNAL vcas_n : STD_LOGIC; - SIGNAL vras_n : STD_LOGIC; - SIGNAL vcs_n : STD_LOGIC; + SIGNAL va : std_logic_vector (12 DOWNTO 0); + SIGNAL ba : std_logic_vector (1 DOWNTO 0); + SIGNAL vwe_n : std_logic; + SIGNAL vcas_n : std_logic; + SIGNAL vras_n : std_logic; + SIGNAL vcs_n : std_logic; - SIGNAL clk_pixel : STD_LOGIC; - SIGNAL sync_n : STD_LOGIC; - SIGNAL vsync : STD_LOGIC; - SIGNAL hsync : STD_LOGIC; - SIGNAL blank_n : STD_LOGIC; + SIGNAL clk_pixel : std_logic; + SIGNAL sync_n : std_logic; + SIGNAL vsync : std_logic; + SIGNAL hsync : std_logic; + SIGNAL blank_n : std_logic; - SIGNAL vr : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL vg : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL vb : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL vr : std_logic_vector (7 DOWNTO 0); + SIGNAL vg : std_logic_vector (7 DOWNTO 0); + SIGNAL vb : std_logic_vector (7 DOWNTO 0); - SIGNAL vdm : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL vdm : std_logic_vector (3 DOWNTO 0); - SIGNAL vd : STD_LOGIC_VECTOR (31 DOWNTO 0); - SIGNAL vd_qs : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL vd : std_logic_vector (31 DOWNTO 0); + SIGNAL vd_qs : std_logic_vector (3 DOWNTO 0); - SIGNAL pd_vga_n : STD_LOGIC; - SIGNAL vcke : STD_LOGIC; - SIGNAL pic_int : STD_LOGIC; - SIGNAL e0_int : STD_LOGIC; - SIGNAL dvi_int : STD_LOGIC; - SIGNAL pci_inta_n : STD_LOGIC; - SIGNAL pci_intb_n : STD_LOGIC; - SIGNAL pci_intc_n : STD_LOGIC; - SIGNAL pci_intd_n : STD_LOGIC; + SIGNAL pd_vga_n : std_logic; + SIGNAL vcke : std_logic; + SIGNAL pic_int : std_logic; + SIGNAL e0_int : std_logic; + SIGNAL dvi_int : std_logic; + SIGNAL pci_inta_n : std_logic; + SIGNAL pci_intb_n : std_logic; + SIGNAL pci_intc_n : std_logic; + SIGNAL pci_intd_n : std_logic; - SIGNAL irq_n : STD_LOGIC_VECTOR (7 DOWNTO 2); - SIGNAL tin0 : STD_LOGIC; + SIGNAL irq_n : std_logic_vector (7 DOWNTO 2); + SIGNAL tin0 : std_logic; - SIGNAL ym_qa : STD_LOGIC; - SIGNAL ym_qb : STD_LOGIC; - SIGNAL ym_qc : STD_LOGIC; + SIGNAL ym_qa : std_logic; + SIGNAL ym_qb : std_logic; + SIGNAL ym_qc : std_logic; - SIGNAL lp_d : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL lp_dir : STD_LOGIC; + SIGNAL lp_d : std_logic_vector (7 DOWNTO 0); + SIGNAL lp_dir : std_logic; - SIGNAL dsa_d : STD_LOGIC; - SIGNAL lp_str : STD_LOGIC; - SIGNAL dtr : STD_LOGIC; - SIGNAL rts : STD_LOGIC; - SIGNAL cts : STD_LOGIC; - SIGNAL ri : STD_LOGIC; - SIGNAL dcd : STD_LOGIC; - SIGNAL lp_busy : STD_LOGIC; - SIGNAL rxd : STD_LOGIC; - SIGNAL txd : STD_LOGIC; - SIGNAL midi_in : STD_LOGIC; - SIGNAL midi_olr : STD_LOGIC; - SIGNAL midi_tlr : STD_LOGIC; - SIGNAL pic_amkb_rx : STD_LOGIC; - SIGNAL amkb_rx : STD_LOGIC; - SIGNAL amkb_tx : STD_LOGIC; - SIGNAL dack0_n : STD_LOGIC; -- Not used. + SIGNAL dsa_d : std_logic; + SIGNAL lp_str : std_logic; + SIGNAL dtr : std_logic; + SIGNAL rts : std_logic; + SIGNAL cts : std_logic; + SIGNAL ri : std_logic; + SIGNAL dcd : std_logic; + SIGNAL lp_busy : std_logic; + SIGNAL rxd : std_logic; + SIGNAL txd : std_logic; + SIGNAL midi_in : std_logic; + SIGNAL midi_olr : std_logic; + SIGNAL midi_tlr : std_logic; + SIGNAL pic_amkb_rx : std_logic; + SIGNAL amkb_rx : std_logic; + SIGNAL amkb_tx : std_logic; + SIGNAL dack0_n : std_logic; -- Not used. - SIGNAL scsi_drqn : STD_LOGIC; - SIGNAL SCSI_MSGn : STD_LOGIC; - SIGNAL SCSI_CDn : STD_LOGIC; - SIGNAL SCSI_IOn : STD_LOGIC; - SIGNAL SCSI_ACKn : STD_LOGIC; - SIGNAL SCSI_ATNn : STD_LOGIC; - SIGNAL SCSI_SELn : STD_LOGIC; - SIGNAL SCSI_BUSYn : STD_LOGIC; - SIGNAL SCSI_RSTn : STD_LOGIC; - SIGNAL SCSI_DIR : STD_LOGIC; - SIGNAL SCSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL SCSI_PAR : STD_LOGIC; + SIGNAL scsi_drqn : std_logic; + SIGNAL SCSI_MSGn : std_logic; + SIGNAL SCSI_CDn : std_logic; + SIGNAL SCSI_IOn : std_logic; + SIGNAL SCSI_ACKn : std_logic; + SIGNAL SCSI_ATNn : std_logic; + SIGNAL SCSI_SELn : std_logic; + SIGNAL SCSI_BUSYn : std_logic; + SIGNAL SCSI_RSTn : std_logic; + SIGNAL SCSI_DIR : std_logic; + SIGNAL SCSI_D : std_logic_vector (7 DOWNTO 0); + SIGNAL SCSI_PAR : std_logic; - SIGNAL ACSI_DIR : STD_LOGIC; - SIGNAL ACSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL ACSI_CSn : STD_LOGIC; - SIGNAL ACSI_A1 : STD_LOGIC; - SIGNAL ACSI_reset_n : STD_LOGIC; - SIGNAL ACSI_ACKn : STD_LOGIC; - SIGNAL ACSI_DRQn : STD_LOGIC; - SIGNAL ACSI_INTn : STD_LOGIC; + SIGNAL ACSI_DIR : std_logic; + SIGNAL ACSI_D : std_logic_vector (7 DOWNTO 0); + SIGNAL ACSI_CSn : std_logic; + SIGNAL ACSI_A1 : std_logic; + SIGNAL ACSI_reset_n : std_logic; + SIGNAL ACSI_ACKn : std_logic; + SIGNAL ACSI_DRQn : std_logic; + SIGNAL ACSI_INTn : std_logic; - SIGNAL FDD_DCHGn : STD_LOGIC; - SIGNAL FDD_SDSELn : STD_LOGIC; - SIGNAL FDD_HD_DD : STD_LOGIC; - SIGNAL FDD_RDn : STD_LOGIC; - SIGNAL FDD_TRACK00 : STD_LOGIC; - SIGNAL FDD_INDEXn : STD_LOGIC; - SIGNAL FDD_WPn : STD_LOGIC; - SIGNAL FDD_MOT_ON : STD_LOGIC; - SIGNAL FDD_WR_GATE : STD_LOGIC; - SIGNAL FDD_WDn : STD_LOGIC; - SIGNAL FDD_STEP : STD_LOGIC; - SIGNAL FDD_STEP_DIR : STD_LOGIC; + SIGNAL FDD_DCHGn : std_logic; + SIGNAL FDD_SDSELn : std_logic; + SIGNAL FDD_HD_DD : std_logic; + SIGNAL FDD_RDn : std_logic; + SIGNAL FDD_TRACK00 : std_logic; + SIGNAL FDD_INDEXn : std_logic; + SIGNAL FDD_WPn : std_logic; + SIGNAL FDD_MOT_ON : std_logic; + SIGNAL FDD_WR_GATE : std_logic; + SIGNAL FDD_WDn : std_logic; + SIGNAL FDD_STEP : std_logic; + SIGNAL FDD_STEP_DIR : std_logic; - SIGNAL ROM4n : STD_LOGIC; - SIGNAL ROM3n : STD_LOGIC; + SIGNAL ROM4n : std_logic; + SIGNAL ROM3n : std_logic; - SIGNAL RP_UDSn : STD_LOGIC; - SIGNAL RP_ldsn : STD_LOGIC; - SIGNAL SD_CLK : STD_LOGIC; - SIGNAL SD_D3 : STD_LOGIC; - SIGNAL SD_CMD_D1 : STD_LOGIC; - SIGNAL SD_D0 : STD_LOGIC; - SIGNAL SD_D1 : STD_LOGIC; - SIGNAL SD_D2 : STD_LOGIC; - SIGNAL SD_caRD_DETECT : STD_LOGIC; - SIGNAL SD_WP : STD_LOGIC; + SIGNAL RP_UDSn : std_logic; + SIGNAL RP_ldsn : std_logic; + SIGNAL SD_CLK : std_logic; + SIGNAL SD_D3 : std_logic; + SIGNAL SD_CMD_D1 : std_logic; + SIGNAL SD_D0 : std_logic; + SIGNAL SD_D1 : std_logic; + SIGNAL SD_D2 : std_logic; + SIGNAL SD_caRD_DETECT : std_logic; + SIGNAL SD_WP : std_logic; - SIGNAL CF_WP : STD_LOGIC; - SIGNAL CF_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL CF_WP : std_logic; + SIGNAL CF_CSn : std_logic_vector (1 DOWNTO 0); - SIGNAL DSP_IO : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL DSP_SRD : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL DSP_SRCSn : STD_LOGIC; - SIGNAL DSP_SRBLEn : STD_LOGIC; - SIGNAL DSP_SRBHEn : STD_LOGIC; - SIGNAL DSP_SRWEn : STD_LOGIC; - SIGNAL DSP_SROEn : STD_LOGIC; + SIGNAL DSP_IO : std_logic_vector (17 DOWNTO 0); + SIGNAL DSP_SRD : std_logic_vector (15 DOWNTO 0); + SIGNAL DSP_SRCSn : std_logic; + SIGNAL DSP_SRBLEn : std_logic; + SIGNAL DSP_SRBHEn : std_logic; + SIGNAL DSP_SRWEn : std_logic; + SIGNAL DSP_SROEn : std_logic; - SIGNAL ide_int : STD_LOGIC; - SIGNAL ide_rdy : STD_LOGIC; - SIGNAL ide_res : STD_LOGIC; - SIGNAL IDE_WRn : STD_LOGIC; - SIGNAL IDE_RDn : STD_LOGIC; - SIGNAL IDE_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL ide_int : std_logic; + SIGNAL ide_rdy : std_logic; + SIGNAL ide_res : std_logic; + SIGNAL IDE_WRn : std_logic; + SIGNAL IDE_RDn : std_logic; + SIGNAL IDE_CSn : std_logic_vector (1 DOWNTO 0); - SIGNAL a : UNSIGNED (31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL a : unsigned (31 DOWNTO 0) := (OTHERS => '0'); BEGIN I_FIREBEE : firebee @@ -476,10 +476,10 @@ BEGIN rasb => vras_n, casb => vcas_n, web => vwe_n, - ba => UNSIGNED(ba), + ba => unsigned(ba), ad => va (12 DOWNTO 0), dqi => vd (30 DOWNTO 15), - dm => UNSIGNED(vdm (3 DOWNTO 2)), + dm => unsigned(vdm (3 DOWNTO 2)), dqs => vd_qs (3 DOWNTO 2) ); @@ -500,7 +500,7 @@ BEGIN stimulate_bus : PROCESS BEGIN WAIT UNTIL RISING_EDGE(clk_main); - fb_ad <= STD_LOGIC_VECTOR (a); -- put something (rather meaningless) on the FlexBus + fb_ad <= std_logic_vector (a); -- put something (rather meaningless) on the FlexBus a <= a + 1; fb_ale <= a(0); -- just toggle for now END PROCESS;