diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index a38c22d..6d0cad7 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -67,7 +67,7 @@ ENTITY DDR_CTRL IS clk_33m : IN STD_LOGIC; fifo_mw : IN UNSIGNED (8 DOWNTO 0); - va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips + va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips vwe_n : OUT STD_LOGIC; -- video memory write enable vras_n : OUT STD_LOGIC; -- video memory RAS vcs_n : OUT STD_LOGIC; -- video memory chip SELECT @@ -101,14 +101,18 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS CONSTANT FIFO_MWM : INTEGER := 200; -- medium water mark CONSTANT FIFO_HWM : INTEGER := 500; -- high water mark - -- constants for bits in video_control_register - CONSTANT vrcr_vcke : INTEGER := 0; - CONSTANT VRCR_REFRESH_ON : INTEGER := 2; - CONSTANT VRCR_CONFIG_ON : INTEGER := 3; - CONSTANT vrcr_vcs : INTEGER := 1; - -- - CONSTANT VRCR_FIFO_ON : INTEGER := 24; - CONSTANT VRCR_BORDER_ON : INTEGER := 25; + -- DDR2 RAM controller bits: + -- $F0000400: + -- BIT 0: vcke; + -- 1: NOT nVC + -- 2: REFRESH ON (0=ddr_access_fifo AND CNT CLEAR); + -- 3: CONFIG + -- 8: vmem_fifo_enable + ALIAS vmem_clock_enable IS video_control_register(0); + ALIAS vmem_cs_enable IS video_control_register(1); + ALIAS vmem_refresh_enable IS video_control_register(2); + ALIAS vmem_config_enable IS video_control_register(3); + ALIAS vmem_fifo_enable IS video_control_register(8); TYPE access_width_t IS (long_access, word_access, byte_access); TYPE ddr_access_t IS (ddr_access_cpu, ddr_access_fifo, ddr_access_blitter, ddr_access_none); @@ -146,12 +150,10 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL cpu_req : STD_LOGIC; SIGNAL ddr_sel : STD_LOGIC; SIGNAL ddr_cs : STD_LOGIC; - SIGNAL ddr_config : STD_LOGIC; SIGNAL fifo_req : STD_LOGIC; SIGNAL fifo_row_adr : UNSIGNED (12 DOWNTO 0); SIGNAL fifo_ba : UNSIGNED (1 DOWNTO 0); SIGNAL fifo_col_adr : UNSIGNED(9 DOWNTO 0); - SIGNAL fifo_active : STD_LOGIC; SIGNAL fifo_clr_sync : STD_LOGIC; SIGNAL vdm_sel_i : UNSIGNED (3 DOWNTO 0); SIGNAL clear_fifo_cnt : STD_LOGIC; @@ -268,11 +270,11 @@ BEGIN -- fb_vdoe # VIDEO_OE. -- Write access for video data: - fb_vdoe(0) <= '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND access_width = long_access ELSE - '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND access_width /= long_access AND clk_33m = '0' ELSE '0'; - fb_vdoe(1) <= '1' WHEN fb_regddr = fr_s1 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' ELSE '0'; - fb_vdoe(2) <= '1' WHEN fb_regddr = fr_s2 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' ELSE '0'; - fb_vdoe(3) <= '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND clk_33m = '0' ELSE '0'; + fb_vdoe(0) <= '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' AND fb_oe_n = '0' AND vmem_config_enable = '0' AND access_width = long_access ELSE + '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' AND fb_oe_n = '0' AND vmem_config_enable = '0' AND access_width /= long_access AND clk_33m = '0' ELSE '0'; + fb_vdoe(1) <= '1' WHEN fb_regddr = fr_s1 AND ddr_cs = '1' AND fb_oe_n = '0' AND vmem_config_enable = '0' ELSE '0'; + fb_vdoe(2) <= '1' WHEN fb_regddr = fr_s2 AND ddr_cs = '1' AND fb_oe_n = '0' AND vmem_config_enable = '0' ELSE '0'; + fb_vdoe(3) <= '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' AND fb_oe_n = '0' AND vmem_config_enable = '0' AND clk_33m = '0' ELSE '0'; bus_cyc_end <= '1' WHEN fb_regddr = fr_s0 AND ddr_cs = '1' AND access_width /= long_access ELSE '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0'; @@ -285,14 +287,14 @@ BEGIN ddr_state <= ddr_next_state; END PROCESS ddr_state_reg; - ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, ddr_config, fb_wr_n, ddr_access, blitter_wr, fifo_req, fifo_bank_ok, + ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, vmem_config_enable, fb_wr_n, ddr_access, blitter_wr, fifo_req, fifo_bank_ok, fifo_mw, cpu_req, video_adr_cnt, ddr_sel, tsiz, data_in, fifo_ba, ddr_refresh_sig) BEGIN CASE ddr_state IS WHEN ds_t1 => IF ddr_refresh_req = '1' THEN ddr_next_state <= ds_r2; - ELSIF cpu_ddr_sync = '1' AND ddr_config = '1' THEN -- Synchronous start. + ELSIF cpu_ddr_sync = '1' AND vmem_config_enable = '1' THEN -- Synchronous start. ddr_next_state <= ds_c2; ELSIF cpu_ddr_sync = '1' AND cpu_req = '1' THEN -- Synchronous start. ddr_next_state <= ds_t2b; @@ -482,26 +484,26 @@ BEGIN sr_ddrwr_d_sel <= '0'; mcs <= mcs(0) & clk_33m; -- sync on clk_33m - - blitter_req <= blitter_sig AND NOT - video_control_register(VRCR_CONFIG_ON) AND - video_control_register(vrcr_vcke) AND - video_control_register(vrcr_vcs); + + blitter_req <= blitter_sig AND + (NOT vmem_config_enable) AND + vmem_clock_enable AND + vmem_cs_enable; fifo_clr_sync <= fifo_clr; - clear_fifo_cnt <= fifo_clr_sync OR NOT fifo_active; + clear_fifo_cnt <= fifo_clr_sync OR NOT vmem_fifo_enable; stop <= fifo_clr_sync OR clear_fifo_cnt; IF fifo_mw < fifo_mwm THEN fifo_req <= '1'; ELSIF fifo_mw < FIFO_HWM AND fifo_req = '1' THEN fifo_req <= '1'; - ELSIF fifo_active = '1' AND + ELSIF vmem_fifo_enable = '1' AND clear_fifo_cnt = '0' AND stop = '0' AND - ddr_config = '0' AND - video_control_register(vrcr_vcke) = '1' AND - video_control_register(vrcr_vcs) = '1' THEN + vmem_config_enable = '0' AND + vmem_clock_enable = '1' AND + vmem_cs_enable = '1' THEN fifo_req <= '1'; ELSE fifo_req <= '1'; @@ -513,13 +515,13 @@ BEGIN video_adr_cnt <= video_adr_cnt + 1; END IF; - IF mcs = "10" AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN + IF mcs = "10" AND vmem_clock_enable = '1' AND vmem_cs_enable = '1' THEN cpu_ddr_sync <= '1'; ELSE cpu_ddr_sync <= '0'; END IF; - IF ddr_refresh_sig /= x"0" AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' AND need_refresh = '1' THEN + IF ddr_refresh_sig /= x"0" AND vmem_refresh_enable = '1' AND vmem_config_enable = '0' AND need_refresh = '1' THEN ddr_refresh_req <= '1'; ELSE ddr_refresh_req <= '0'; @@ -531,9 +533,9 @@ BEGIN need_refresh <= '0'; END IF; - IF need_refresh = '1' AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' THEN + IF need_refresh = '1' AND vmem_refresh_enable = '1' AND vmem_config_enable = '0' THEN ddr_refresh_sig <= x"9"; - ELSIF ddr_state = ds_r6 AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' THEN + ELSIF ddr_state = ds_r6 AND vmem_refresh_enable = '1' AND vmem_config_enable = '0' THEN ddr_refresh_sig <= ddr_refresh_sig - 1; ELSE ddr_refresh_sig <= x"0"; @@ -576,14 +578,12 @@ BEGIN va_s(10) <= '1'; ddr_access <= ddr_access_cpu; ELSIF ddr_state = ds_t2a THEN - -- ?? mfro - va_s(10) <= NOT (fifo_active AND fifo_req); + va_s(10) <= NOT (vmem_fifo_enable AND fifo_req); ddr_access <= ddr_access_fifo; - fifo_bank_ok <= fifo_active AND fifo_req; + fifo_bank_ok <= vmem_fifo_enable AND fifo_req; IF ddr_access = ddr_access_blitter AND blitter_req = '1' THEN ddr_access <= ddr_access_blitter; END IF; - -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE AND blitter_req; ELSIF ddr_state = ds_t2b THEN fifo_bank_ok <= '0'; ELSIF ddr_state = ds_t3 THEN @@ -591,7 +591,7 @@ BEGIN IF (fb_wr_n = '0' AND ddr_access = ddr_access_cpu) OR (blitter_wr = '1' AND ddr_access = ddr_access_blitter) THEN va_s(9 DOWNTO 0) <= cpu_col_adr; ba_s <= cpu_ba; - ELSIF fifo_active = '1' THEN + ELSIF vmem_fifo_enable = '1' THEN va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_access = ddr_access_blitter THEN @@ -705,7 +705,7 @@ BEGIN p_ddr_cs: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(clk_33m); + WAIT UNTIL RISING_EDGE(clk_main); IF fb_ale = '1' THEN ddr_cs <= ddr_sel; END IF; @@ -715,11 +715,11 @@ BEGIN BEGIN WAIT UNTIL RISING_EDGE(ddr_sync_66m); - IF ddr_sel = '1' AND fb_wr_n = '1' AND ddr_config = '0' THEN + IF ddr_sel = '1' AND fb_wr_n = '1' AND vmem_config_enable = '0' THEN cpu_req <= '1'; - ELSIF ddr_sel = '1' AND access_width /= long_access AND ddr_config = '0' THEN -- Start when not config and not longword access. + ELSIF ddr_sel = '1' AND access_width /= long_access AND vmem_config_enable = '0' THEN -- Start when not config and not longword access. cpu_req <= '1'; - ELSIF ddr_sel = '1' AND ddr_config = '1' THEN -- Config, start immediately. + ELSIF ddr_sel = '1' AND vmem_config_enable = '1' THEN -- Config, start immediately. cpu_req <= '1'; ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Longword write later. cpu_req <= '1'; @@ -780,13 +780,8 @@ BEGIN '1' WHEN ddr_state = ds_cb8 ELSE '1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE '0'; - -- DDR controller: - -- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR) - -- $F0000400: BIT 0: vcke; 1: NOT nVCS ;2:REFRESH ON , (0=ddr_access_fifo AND CNT CLEAR); - -- 3: CONFIG; 8: fifo_active; - vcs_n <= NOT(video_control_register(VRCR_REFRESH_ON)); - ddr_config <= video_control_register(3); - fifo_active <= video_control_register(8); + vcs_n <= NOT(vmem_cs_enable); + vcke <= vmem_clock_enable; cpu_row_adr <= fb_adr(26 DOWNTO 14); cpu_ba <= fb_adr(13 DOWNTO 12); diff --git a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd index e0d5a09..cb8891a 100644 --- a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd +++ b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd @@ -1,45 +1,45 @@ ---------------------------------------------------------------------- ---- ---- ----- ThIS file IS part of the 'Firebee' project. ---- ----- http://acp.atari.ORg ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- ---- ---- ---- Description: ---- ----- ThIS design unit provides the DMA controller of the 'Firebee'---- ----- computer. It IS optimized fOR the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). ThIS IP-CORe IS based on the first edi- ---- ----- tion of the Firebee configware ORigINally provided by Fredi ---- ----- AshwANDen AND Wolfgang Förster. ThIS release IS IN compa- ---- ----- rISion to the first edition completely written IN VHDL. ---- +---- This design unit provides the DMA controller of the 'Firebee'---- +---- computer. It is optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- tion of the Firebee configware originally provided by Fredi ---- +---- Aschwanden and Wolfgang Förster. This release is in compa- ---- +---- rision to the first edition completely written in VHDL. ---- ---- ---- ----- AuthOR(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@INventronik.de ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2012 Fredi AschwANDen, Wolfgang Förster ---- +---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- ---- ---- ----- ThIS source file IS free software; you can redIStribute it ---- +---- This source file is free software; you can redistribute it ---- ---- AND/OR modIFy it under the terms of the GNU General Public ---- ----- License as publIShed by the Free Software Foundation; either ---- +---- License as published by the Free Software Foundation; either ---- ---- version 2 of the License, OR (at your option) any later ---- ---- version. ---- ---- ---- ----- ThIS program IS dIStributed IN the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; withOUT even the implied ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License fOR mORe ---- +---- PURPOSE. See the GNU General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ----- License along with thIS program; IF NOT, write to the Free ---- ----- Software Foundation, Inc., 51 FranklIN Street, FIFth FloOR, ---- +---- License along with this program; If not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ---- Boston, MA 02110-1301, USA. ---- ---- ---- ---------------------------------------------------------------------- -- --- RevISion HIStORy +-- Revision History -- --- RevISion 2K12B 20120801 WF +-- Revision 2K12B 20120801 WF -- Initial Release of the second edition. LIBRARY IEEE; @@ -55,9 +55,9 @@ ENTITY FBEE_DMA IS FB_ADR : IN STD_LOGIC_VECTOR(26 DOWNTO 0); FB_ALE : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - fb_oe_n : IN STD_LOGIC; - FB_WRn : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_EN_31_24 : OUT STD_LOGIC; @@ -194,7 +194,7 @@ ARCHITECTURE BEHAVIOUR of FBEE_DMA IS SIGNAL FB_B0 : STD_LOGIC; SIGNAL WRF_DOUT : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL FB_AD_I : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL d : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL d : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN LONG <= '1' WHEN FB_SIZE(1) = '0' AND FB_SIZE(0) = '0' ELSE '0'; BYTE <= '1' WHEN FB_SIZE(1) = '0' AND FB_SIZE(0) = '1' ELSE '0'; @@ -258,7 +258,7 @@ BEGIN INBUFFER: PROCESS(CLK_MAIN) BEGIN IF RISING_EDGE(CLK_MAIN) THEN - IF FB_WRn = '0' THEN + IF fb_wr_n = '0' THEN FB_AD_I <= FB_AD_IN(23 DOWNTO 16); END IF; END IF; @@ -295,7 +295,7 @@ BEGIN fcf_aph <= '1' WHEN FB_ALE = '1' AND FB_AD_IN(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY RDF_DIN <= DATA_IN_FDC WHEN dma_mode(7) = '1' ELSE DATA_IN_SCSI; - RDF_RDE <= '1' WHEN fcf_aph = '1' AND FB_WRn = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE + RDF_RDE <= '1' WHEN fcf_aph = '1' AND fb_wr_n = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE DATA_OUT_FDC_SCSI <= WRF_DOUT WHEN dma_active = '1' AND dma_mode(8) = '1' ELSE FB_AD_I; -- BEI DMA WRITE <-FIFO SONST <-FB @@ -304,16 +304,16 @@ BEGIN CA_I(2) <= '1' WHEN dma_active = '1' ELSE dma_mode(2); CA <= CA_I; - FDC_WRn <= (NOT dma_mode(8)) WHEN dma_active = '1' ELSE FB_WRn; + FDC_WRn <= (NOT dma_mode(8)) WHEN dma_active = '1' ELSE fb_wr_n; dma_mode_REGISTER: PROCESS(RESET, CLK_MAIN) BEGIN IF RESET = '1' THEN dma_mode <= x"0000"; ELSIF RISING_EDGE(CLK_MAIN) THEN - IF dma_mode_cs = '1' AND FB_WRn = '0' AND FB_B0 = '1' THEN + IF dma_mode_cs = '1' AND fb_wr_n = '0' AND FB_B0 = '1' THEN dma_mode(15 DOWNTO 8) <= FB_AD_IN(31 DOWNTO 24); - ELSIF dma_mode_cs = '1' AND FB_WRn = '0' AND FB_B1 = '1' THEN + ELSIF dma_mode_cs = '1' AND fb_wr_n = '0' AND FB_B1 = '1' THEN dma_mode(7 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 16); END IF; END IF; @@ -324,11 +324,11 @@ BEGIN IF RESET = '1' OR CLR_FIFO = '1' THEN dma_bytecnt <= x"00000000"; ELSIF RISING_EDGE(CLK_MAIN) THEN - IF dma_data_cs = '1' AND FB_WRn = '0' AND dma_mode(4) = '1' AND FB_B1 = '1' THEN + IF dma_data_cs = '1' AND fb_wr_n = '0' AND dma_mode(4) = '1' AND FB_B1 = '1' THEN dma_bytecnt(31 DOWNTO 17) <= "000000000000000"; dma_bytecnt(16 DOWNTO 9) <= FB_AD_IN(23 DOWNTO 16); dma_bytecnt(8 DOWNTO 0) <= "000000000"; - ELSIF dma_bytecnt_cs = '1' AND FB_WRn = '0' THEN + ELSIF dma_bytecnt_cs = '1' AND fb_wr_n = '0' THEN dma_bytecnt <= FB_AD_IN; END IF; END IF; @@ -339,7 +339,7 @@ BEGIN IF RESET = '1' THEN WDC_BSL <= "00"; ELSIF RISING_EDGE(CLK_MAIN) THEN - IF WDC_BSL_CS = '1' AND FB_WRn = '0' AND FB_B0 = '1' THEN + IF WDC_BSL_CS = '1' AND fb_wr_n = '0' AND FB_B0 = '1' THEN WDC_BSL <= FB_AD_IN(25 DOWNTO 24); END IF; WDC_BSL0 <= WDC_BSL(0); @@ -367,20 +367,20 @@ BEGIN dma_mid <= x"00"; dma_low <= x"00"; ELSIF RISING_EDGE(CLK_MAIN) THEN - IF FB_WRn = '0' AND (dma_top_cs = '1' OR dma_adr_cs = '1') THEN + IF fb_wr_n = '0' AND (dma_top_cs = '1' OR dma_adr_cs = '1') THEN dma_top <= FB_AD_IN(31 DOWNTO 24); END IF; - IF FB_WRn = '0' AND (dma_high_cs = '1' OR dma_adr_cs = '1') THEN + IF fb_wr_n = '0' AND (dma_high_cs = '1' OR dma_adr_cs = '1') THEN dma_high <= FB_AD_IN(23 DOWNTO 16); END IF; - IF FB_WRn = '0' AND dma_mid_cs = '1' THEN + IF fb_wr_n = '0' AND dma_mid_cs = '1' THEN dma_mid <= FB_AD_IN(23 DOWNTO 16); - ELSIF FB_WRn = '0' AND dma_adr_cs = '1' THEN + ELSIF fb_wr_n = '0' AND dma_adr_cs = '1' THEN dma_mid <= FB_AD_IN(15 DOWNTO 8); END IF; - IF FB_WRn = '0' AND dma_low_cs = '1' THEN + IF fb_wr_n = '0' AND dma_low_cs = '1' THEN dma_low <= FB_AD_IN(23 DOWNTO 16); - ELSIF FB_WRn = '0' AND dma_adr_cs = '1' THEN + ELSIF fb_wr_n = '0' AND dma_adr_cs = '1' THEN dma_low <= FB_AD_IN(7 DOWNTO 0); END IF; END IF; @@ -424,7 +424,7 @@ BEGIN IF RESET = '1' THEN WRF_WRE <= '0'; ELSIF RISING_EDGE(CLK_MAIN) THEN - IF fcf_aph = '1' AND FB_WRn = '0' THEN + IF fcf_aph = '1' AND fb_wr_n = '0' THEN WRF_WRE <= '1'; ELSE WRF_WRE <= '0'; @@ -462,27 +462,27 @@ BEGIN SNDENDLO <= x"00"; SNDMODE <= x"00"; ELSIF CLK_MAIN = '1' AND CLK_MAIN' event THEN - IF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND FB_WRn = '0' AND FB_B1 ='1' THEN + IF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDMACTL <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDBASHI <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDBASMI <= FB_AD_IN(23DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDBASLO <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDADRHI <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDADRMI <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDADRLO <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDENDHI <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDENDMI <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDENDLO <= FB_AD_IN(23 DOWNTO 16); - ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND FB_WRn = '0' AND FB_B1 ='1' THEN + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND fb_wr_n = '0' AND FB_B1 ='1' THEN SNDMODE <= FB_AD_IN(23 DOWNTO 16); END IF; END IF; diff --git a/vhdl/rtl/vhdl/Firebee/Firebee.vhd b/vhdl/rtl/vhdl/Firebee/Firebee.vhd index 78690de..810dd0f 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee.vhd @@ -914,135 +914,135 @@ BEGIN blitter_run => blitter_run ); --- I_INTHANDLER: INTHANDLER --- PORT MAP( --- clk_main => clk_main, --- resetn => reset_n, --- fb_adr => fb_adr, --- fb_cs_n => fb_cs_n(2 DOWNTO 1), --- fb_oe_n => fb_oe_n, --- fb_size0 => fb_size(0), --- fb_size1 => fb_size(1), --- fb_wr_n => fb_wr_n, --- fb_ad_IN => fb_ad, --- fb_ad_OUT => fb_ad_out_ih, --- fb_ad_EN_31_24 => fb_ad_en_31_24_ih, --- fb_ad_EN_23_16 => fb_ad_en_23_16_ih, --- fb_ad_EN_15_8 => fb_ad_en_15_8_ih, --- fb_ad_EN_7_0 => fb_ad_en_7_0_ih, --- pic_int => pic_int, --- e0_int => e0_int, --- dvi_int => dvi_int, --- pci_inta_n => pci_inta_n, --- pci_intb_n => pci_intb_n, --- pci_intc_n => pci_intc_n, --- pci_intd_n => pci_intd_n, --- mfp_intn => mfp_int_n, --- dsp_int => dsp_int, --- vsync => vsync_i, --- hsync => hsync_i, --- drq_dma => drq_dma, --- irq_n => irq_n, --- int_handler_ta => int_handler_ta, --- fbee_conf => fbee_conf, --- tin0 => tin0 --- ); + I_INTHANDLER: INTHANDLER + PORT MAP( + clk_main => clk_main, + reset_n => reset_n, + fb_adr => fb_adr, + fb_cs_n => fb_cs_n(2 DOWNTO 1), + fb_oe_n => fb_oe_n, + fb_size0 => fb_size(0), + fb_size1 => fb_size(1), + fb_wr_n => fb_wr_n, + fb_ad_IN => fb_ad, + fb_ad_OUT => fb_ad_out_ih, + fb_ad_EN_31_24 => fb_ad_en_31_24_ih, + fb_ad_EN_23_16 => fb_ad_en_23_16_ih, + fb_ad_EN_15_8 => fb_ad_en_15_8_ih, + fb_ad_EN_7_0 => fb_ad_en_7_0_ih, + pic_int => pic_int, + e0_int => e0_int, + dvi_int => dvi_int, + pci_inta_n => pci_inta_n, + pci_intb_n => pci_intb_n, + pci_intc_n => pci_intc_n, + pci_intd_n => pci_intd_n, + mfp_int_n => mfp_int_n, + dsp_int => dsp_int, + vsync => vsync_i, + hsync => hsync_i, + drq_dma => drq_dma, + irq_n => irq_n, + int_handler_ta => int_handler_ta, + fbee_conf => fbee_conf, + tin0 => tin0 + ); --- I_DMA: FBEE_DMA --- PORT MAP( --- RESET => NOT reset_n, --- clk_main => clk_main, --- clk_fdc => clk_fdc, --- --- fb_adr => fb_adr(26 DOWNTO 0), --- fb_ale => fb_ale, --- fb_size => fb_size, --- fb_cs_n => fb_cs_n(2 DOWNTO 1), --- fb_oe_n => fb_oe_n, --- fb_wr_n => fb_wr_n, --- fb_ad_IN => fb_ad, --- fb_ad_OUT => fb_ad_out_dma, --- fb_ad_EN_31_24 => fb_ad_en_31_24_dma, --- fb_ad_EN_23_16 => fb_ad_en_23_16_dma, --- fb_ad_EN_15_8 => fb_ad_en_15_8_dma, --- fb_ad_EN_7_0 => fb_ad_en_7_0_dma, --- --- ACSI_DIR => ACSI_DIR, --- ACSI_D_IN => ACSI_D, --- acsi_d_out => acsi_d_out, --- acsi_d_en => acsi_d_en, --- ACSI_CSn => ACSI_CSn, --- ACSI_A1 => ACSI_A1, --- ACSI_resetn => ACSI_reset_n, --- ACSI_DRQn => ACSI_DRQn, --- ACSI_ACKn => ACSI_ACKn, --- --- DATA_IN_FDC => data_out_fdc, --- DATA_IN_SCSI => data_out_scsi, --- data_out_fdc_SCSI => data_in_fdc_scsi, --- --- DMA_DRQ_IN => drq_fdc, --- DMA_DRQ_OUT => drq_dma, --- DMA_DRQ11 => drq11_dma, --- --- scsi_drq => scsi_drq, --- scsi_dackn => scsi_dack_n, --- scsi_int => scsi_int, --- scsi_csn => scsi_csn, --- scsi_cs => scsi_cs, --- --- ca => ca, --- FLOPPY_HD_DD => FDD_HD_DD, --- wdc_bsl0 => wdc_bsl0, --- fdc_csn => fdc_cs_n, --- fdc_wrn => fdc_wr_n, --- fd_int => fd_int, --- ide_int => ide_int, --- dma_cs => dma_cs --- ); + I_DMA: FBEE_DMA + PORT MAP( + RESET => NOT reset_n, + clk_main => clk_main, + clk_fdc => clk_fdc, --- I_IDE_CF_SD_ROM: IDE_CF_SD_ROM --- PORT MAP( --- RESET => NOT reset_n, --- clk_main => clk_main, --- --- fb_adr => fb_adr(19 DOWNTO 5), --- FB_CS1n => fb_cs_n(1), --- fb_wr_n => fb_wr_n, --- fb_b0 => fb_b0, --- fb_b1 => fb_b1, --- --- fbee_conf => fbee_conf(31 DOWNTO 30), --- --- RP_UDSn => RP_UDSn, --- RP_ldsn => RP_ldsn, --- --- SD_CLK => SD_CLK, --- SD_D0 => SD_D0, --- SD_D1 => SD_D1, --- SD_D2 => SD_D2, --- SD_CD_D3_IN => SD_D3, --- sd_cd_d3_out => sd_cd_d3_out, --- sd_cd_d3_en => sd_cd_d3_en, --- SD_CMD_D1_IN => SD_CMD_D1, --- sd_cmd_d1_out => sd_cmd_d1_out, --- sd_cmd_d1_en => sd_cmd_d1_en, --- SD_caRD_DETECT => SD_caRD_DETECT, --- SD_WP => SD_WP, --- --- ide_rdy => ide_rdy, --- IDE_WRn => IDE_WRn, --- IDE_RDn => IDE_RDn, --- IDE_CSn => IDE_CSn, --- -- IDE_DRQn =>, -- Not used. --- ide_cf_ta => ide_cf_ta, --- --- ROM4n => ROM4n, --- ROM3n => ROM3n, --- --- CF_WP => CF_WP, --- CF_CSn => CF_CSn --- ); + fb_adr => fb_adr(26 DOWNTO 0), + fb_ale => fb_ale, + fb_size => fb_size, + fb_cs_n => fb_cs_n(2 DOWNTO 1), + fb_oe_n => fb_oe_n, + fb_wr_n => fb_wr_n, + fb_ad_IN => fb_ad, + fb_ad_OUT => fb_ad_out_dma, + fb_ad_EN_31_24 => fb_ad_en_31_24_dma, + fb_ad_EN_23_16 => fb_ad_en_23_16_dma, + fb_ad_EN_15_8 => fb_ad_en_15_8_dma, + fb_ad_EN_7_0 => fb_ad_en_7_0_dma, + + ACSI_DIR => ACSI_DIR, + ACSI_D_IN => ACSI_D, + acsi_d_out => acsi_d_out, + acsi_d_en => acsi_d_en, + ACSI_CSn => ACSI_CSn, + ACSI_A1 => ACSI_A1, + ACSI_resetn => ACSI_reset_n, + ACSI_DRQn => ACSI_DRQn, + ACSI_ACKn => ACSI_ACKn, + + DATA_IN_FDC => data_out_fdc, + DATA_IN_SCSI => data_out_scsi, + data_out_fdc_SCSI => data_in_fdc_scsi, + + DMA_DRQ_IN => drq_fdc, + DMA_DRQ_OUT => drq_dma, + DMA_DRQ11 => drq11_dma, + + scsi_drq => scsi_drq, + scsi_dackn => scsi_dack_n, + scsi_int => scsi_int, + scsi_csn => scsi_csn, + scsi_cs => scsi_cs, + + ca => ca, + FLOPPY_HD_DD => FDD_HD_DD, + wdc_bsl0 => wdc_bsl0, + fdc_csn => fdc_cs_n, + fdc_wrn => fdc_wr_n, + fd_int => fd_int, + ide_int => ide_int, + dma_cs => dma_cs + ); + + I_IDE_CF_SD_ROM: IDE_CF_SD_ROM + PORT MAP( + RESET => NOT reset_n, + clk_main => clk_main, + + fb_adr => fb_adr(19 DOWNTO 5), + FB_CS1n => fb_cs_n(1), + fb_wr_n => fb_wr_n, + fb_b0 => fb_b0, + fb_b1 => fb_b1, + + fbee_conf => fbee_conf(31 DOWNTO 30), + + RP_UDSn => RP_UDSn, + RP_ldsn => RP_ldsn, + + SD_CLK => SD_CLK, + SD_D0 => SD_D0, + SD_D1 => SD_D1, + SD_D2 => SD_D2, + SD_CD_D3_IN => SD_D3, + sd_cd_d3_out => sd_cd_d3_out, + sd_cd_d3_en => sd_cd_d3_en, + SD_CMD_D1_IN => SD_CMD_D1, + sd_cmd_d1_out => sd_cmd_d1_out, + sd_cmd_d1_en => sd_cmd_d1_en, + SD_caRD_DETECT => SD_caRD_DETECT, + SD_WP => SD_WP, + + ide_rdy => ide_rdy, + IDE_WRn => IDE_WRn, + IDE_RDn => IDE_RDn, + IDE_CSn => IDE_CSn, + -- IDE_DRQn =>, -- Not used. + ide_cf_ta => ide_cf_ta, + + ROM4n => ROM4n, + ROM3n => ROM3n, + + CF_WP => CF_WP, + CF_CSn => CF_CSn + ); -- I_DSP: DSP -- PORT MAP( @@ -1054,7 +1054,7 @@ BEGIN -- FB_CS2n => fb_cs_n(2), -- fb_size0 => fb_size(0), -- fb_size1 => fb_size(1), --- fb_burst_n => fb_burst_n, +-- fb_burst_n => fb_burst_n, -- fb_adr => fb_adr, -- resetn => reset_n, -- FB_CS3n => fb_cs_n(3), @@ -1076,41 +1076,41 @@ BEGIN -- SRD_EN => dsp_srd_en -- ); --- I_SOUND: WF2149IP_TOP_SOC --- PORT MAP( --- SYS_CLK => clk_main, --- resetn => reset_n, --- --- WAV_CLK => clk_2m0, --- SELn => '1', --- --- BDIR => sndir_i, --- BC2 => '1', --- BC1 => sndcs_i, --- --- A9n => '0', --- A8 => '1', --- DA_IN => fb_ad(31 DOWNTO 24), --- DA_OUT => da_out_x, --- --- IO_A_IN => x"00", -- All port pINs are dedicated OUTputs. --- IO_A_OUT(7) => ide_res_i, --- IO_A_OUT(6) => lp_dir_x, --- IO_A_OUT(5) => lp_str, --- IO_A_OUT(4) => dtr, --- IO_A_OUT(3) => rts, --- IO_A_OUT(2) => reserved_1, --- IO_A_OUT(1) => dsa_d, --- IO_A_OUT(0) => FDD_SDSELn, --- -- IO_A_EN => tout0_n, -- Not required. --- IO_B_IN => lp_d, --- IO_B_OUT => lp_d_x, --- -- IO_B_EN => -- Not used. --- --- OUT_A => ym_qa, --- OUT_B => ym_qb, --- OUT_C => ym_qc --- ); + I_SOUND: WF2149IP_TOP_SOC + PORT MAP( + SYS_CLK => clk_main, + resetn => reset_n, + + WAV_CLK => clk_2m0, + SELn => '1', + + BDIR => sndir_i, + BC2 => '1', + BC1 => sndcs_i, + + A9n => '0', + A8 => '1', + DA_IN => fb_ad(31 DOWNTO 24), + DA_OUT => da_out_x, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => ide_res_i, + IO_A_OUT(6) => lp_dir_x, + IO_A_OUT(5) => lp_str, + IO_A_OUT(4) => dtr, + IO_A_OUT(3) => rts, + IO_A_OUT(2) => reserved_1, + IO_A_OUT(1) => dsa_d, + IO_A_OUT(0) => FDD_SDSELn, + -- IO_A_EN => tout0_n, -- Not required. + IO_B_IN => lp_d, + IO_B_OUT => lp_d_x, + -- IO_B_EN => -- Not used. + + OUT_A => ym_qa, + OUT_B => ym_qb, + OUT_C => ym_qc + ); I_MFP: WF68901IP_TOP_SOC PORT MAP( @@ -1135,8 +1135,8 @@ BEGIN gpip_in(2) => NOT cts, gpip_in(1) => NOT dcd, gpip_in(0) => lp_busy, - -- GPIP_OUT =>, -- Not used; all GPIPs are direction INput. - -- GPIP_EN =>, -- Not used; all GPIPs are direction INput. + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction in put. -- Interrupt control: IACKn => NOT mfp_intack, IEIn => '0', diff --git a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd index 73bd268..0551586 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd @@ -208,7 +208,7 @@ PACKAGE firebee_pkg IS COMPONENT INTHANDLER PORT( clk_main : IN STD_LOGIC; - RESETn : IN STD_LOGIC; + reset_n : IN STD_LOGIC; fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); fb_size0 : IN STD_LOGIC; diff --git a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd index 417c9aa..ee9c578 100644 --- a/vhdl/rtl/vhdl/Interrupt/interrupt.vhd +++ b/vhdl/rtl/vhdl/Interrupt/interrupt.vhd @@ -1,15 +1,15 @@ ---------------------------------------------------------------------- ---- ---- ----- This file is part of the 'Firebee' project. ---- +---- This file is part OF the 'Firebee' project. ---- ---- http://acp.atari.org ---- ---- ---- ---- Description: ---- ----- This design unit provides the interruptlogic of the 'Firebee'---- ----- computer. It is optimized for the use of an Altera Cyclone ---- +---- This design unit provides the interruptlogic OF the 'Firebee'---- +---- computer. It is optimized FOR the use of an Altera Cyclone ---- ---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- +---- tion OF the Firebee configware originally provided by Fredi ---- +---- Aschwanden AND Wolfgang Förster. This release is in compa- ---- +---- rision TO the first edition completely written in VHDL. ---- ---- ---- ---- Author(s): ---- ---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- @@ -19,19 +19,19 @@ ---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- +---- AND/or modify it under the terms OF the GNU General Public ---- ---- License as published by the Free Software Foundation; either ---- ---- version 2 of the License, or (at your option) any later ---- ---- version. ---- ---- ---- ----- This program is distributed in the hope that it will be ---- +---- This program IS distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- +---- warranty OF MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License FOR more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- +---- License along with this program; IF NOT, write TO the Free ---- ---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ---- Boston, MA 02110-1301, USA. ---- ---- ---- @@ -40,267 +40,267 @@ -- Revision History -- -- Revision 2K12B 20120801 WF --- Initial Release of the second edition. +-- Initial Release OF the second edition. -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; --- use ieee.std_logic_arith.all; +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.all; +-- USE ieee.std_logic_arith.ALL; -entity INTHANDLER is - port( - CLK_MAIN : in std_logic; - RESETn : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - fb_cs_n : in std_logic_vector(2 downto 1); - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_WRn : in std_logic; - fb_oe_n : in std_logic; - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN_31_24 : out std_logic; - FB_AD_EN_23_16 : out std_logic; - FB_AD_EN_15_8 : out std_logic; - FB_AD_EN_7_0 : out std_logic; - PIC_INT : in std_logic; - E0_INT : in std_logic; - DVI_INT : in std_logic; - PCI_INTAn : in std_logic; - PCI_INTBn : in std_logic; - PCI_INTCn : in std_logic; - PCI_INTDn : in std_logic; - MFP_INTn : in std_logic; - DSP_INT : in std_logic; - VSYNC : in std_logic; - HSYNC : in std_logic; - DRQ_DMA : in std_logic; - irq_n : out std_logic_vector(7 downto 2); - INT_HANDLER_TA : out std_logic; - FBEE_CONF : out std_logic_vector(31 downto 0); - TIN0 : out std_logic +ENTITY inthandler IS + PORT( + clk_main : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; + fb_ad_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fb_ad_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fb_ad_en_31_24 : OUT STD_LOGIC; + fb_ad_en_23_16 : OUT STD_LOGIC; + fb_ad_en_15_8 : OUT STD_LOGIC; + fb_ad_en_7_0 : OUT STD_LOGIC; + pic_int : IN STD_LOGIC; + e0_int : IN STD_LOGIC; + dvi_int : IN STD_LOGIC; + pci_inta_n : IN STD_LOGIC; + pci_intb_n : IN STD_LOGIC; + pci_intc_n : IN STD_LOGIC; + pci_intd_n : IN STD_LOGIC; + mfp_int_n : IN STD_LOGIC; + dsp_int : IN STD_LOGIC; + vsync : IN STD_LOGIC; + hsync : IN STD_LOGIC; + drq_dma : IN STD_LOGIC; + irq_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); + int_handler_ta : OUT STD_LOGIC; + fbee_conf : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + tin0 : OUT STD_LOGIC ); -end entity INTHANDLER; +END ENTITY inthandler; -architecture BEHAVIOUR of INTHANDLER is - type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0); - signal INT_LA : INT_LA_TYPE; - signal FB_B : std_logic_vector(3 downto 0); - signal INT_CTR : std_logic_vector(31 downto 0); - signal INT_CTR_CS : std_logic; - signal INT_LATCH : std_logic_vector(31 downto 0); - signal INT_LATCH_CS : std_logic; - signal INT_CLEAR : std_logic_vector(31 downto 0); - signal INT_CLEAR_CS : std_logic; - signal INT_IN : std_logic_vector(31 downto 0); - signal INT_ENA : std_logic_vector(31 downto 0); - signal INT_ENA_CS : std_logic; - signal INT_L : std_logic_vector(9 downto 0); - signal FBEE_CONF_REG : std_logic_vector(31 downto 0); - signal FBEE_CONF_CS : std_logic; - signal PSEUDO_BUS_ERROR : std_logic; -begin +ARCHITECTURE BEHAVIOUR OF inthandler IS + type int_la_t IS array(9 DOWNTO 0) OF STD_LOGIC_VECTOR(3 DOWNTO 0); + signal int_la : int_la_t; + signal fb_b : STD_LOGIC_VECTOR(3 DOWNTO 0); + signal int_ctr : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal int_ctr_cs : STD_LOGIC; + signal int_latch : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal int_latch_cs : STD_LOGIC; + signal int_clear : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal int_clear_cs : STD_LOGIC; + signal int_in : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal int_ena : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal int_ena_cs : STD_LOGIC; + signal int_l : STD_LOGIC_VECTOR(9 DOWNTO 0); + signal fbee_conf_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal fbee_conf_cs : STD_LOGIC; + signal pseudo_bus_error : STD_LOGIC; +BEGIN -- Byte selectors: - FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + fb_b(0) <= '1' WHEN fb_size1 = '1' AND fb_size0 = '0' AND fb_adr(1) = '0' ELSE -- High word. + '1' WHEN fb_size1 = '0' AND fb_size0 = '1' AND fb_adr(1 DOWNTO 0) = "00" ELSE -- HH Byte. + '1' WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE -- Long. + '1' WHEN fb_size1 = '1' AND fb_size0 = '1' ELSE '0';-- Line. - FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + fb_b(1) <= '1' WHEN fb_size1 = '1' AND fb_size0 = '0' AND fb_adr(1) = '0' ELSE -- High word. + '1' WHEN fb_size1 = '0' AND fb_size0 = '1' AND fb_adr(1 DOWNTO 0) = "01" ELSE -- HL Byte. + '1' WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE -- Long. + '1' WHEN fb_size1 = '1' AND fb_size0 = '1' ELSE '0';-- Line. - FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + fb_b(2) <= '1' WHEN fb_size1 = '1' AND fb_size0 = '0' AND fb_adr(1) = '1' ELSE -- Low word. + '1' WHEN fb_size1 = '0' AND fb_size0 = '1' AND fb_adr(1 DOWNTO 0) = "10" ELSE -- LH Byte. + '1' WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE -- Long. + '1' WHEN fb_size1 = '1' AND fb_size0 = '1' ELSE '0';-- Line. - FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte. - '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long. - '1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line. + fb_b(3) <= '1' WHEN fb_size1 = '1' AND fb_size0 = '0' AND fb_adr(1) = '1' ELSE -- Low word. + '1' WHEN fb_size1 = '0' AND fb_size0 = '1' AND fb_adr(1 DOWNTO 0) = "11" ELSE -- LL Byte. + '1' WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE -- Long. + '1' WHEN fb_size1 = '1' AND fb_size0 = '1' ELSE '0';-- Line. - INT_CTR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4; - INT_ENA_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4; - INT_CLEAR_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4; - INT_LATCH_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4; + int_ctr_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000100000000000000" ELSE '0'; -- $10000/4; + int_ena_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000100000000000001" ELSE '0'; -- $10004/4; + int_clear_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000100000000000010" ELSE '0'; -- $10008/4; + int_latch_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000000000100000000000011" ELSE '0'; -- $1000C/4; - P_INT_CTRL : process + P_INT_CTRL : PROCESS -- Interrupt control register: -- BIT0 = INT5, Bit1 = INT7. -- Interrupt enabe register: -- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2 - -- The interrupt clear register is write only; 1 = interrupt clear. - begin - wait until rising_edge(CLK_MAIN); - if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; + -- The interrupt clear register IS write only; 1 = interrupt clear. + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + IF int_ctr_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + int_ctr(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24); + ELSIF int_ctr_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + int_ctr(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16); + ELSIF int_ctr_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + int_ctr(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8); + ELSIF int_ctr_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + int_ctr(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0); + END IF; -- - if RESETn = '0' then - INT_ENA <= (others => '0'); - elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; + IF reset_n = '0' THEN + int_ena <= (OTHERS => '0'); + ELSIF int_ena_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + int_ena(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24); + ELSIF int_ena_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + int_ena(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16); + ELSIF int_ena_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + int_ena(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8); + ELSIF int_ena_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + int_ena(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0); + END IF; -- - if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - end process P_INT_CTRL; + IF int_clear_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + int_clear(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24); + ELSIF int_clear_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + int_clear(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16); + ELSIF int_clear_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + int_clear(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8); + ELSIF int_clear_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + int_clear(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0); + END IF; + END PROCESS P_INT_CTRL; -- Interrupt latch register: read only. - irq_n(2) <= '0' when HSYNC = '1' and INT_ENA(26) = '1' else '1'; - irq_n(3) <= '0' when INT_CTR(0) = '1' and INT_ENA(27) = '1' else '1'; - irq_n(4) <= '0' when VSYNC = '1' and INT_ENA(28) = '1' else '1'; - irq_n(5) <= '0' when INT_LATCH /= x"00000000" and INT_ENA(29) = '1' else '1'; - irq_n(6) <= '0' when MFP_INTn = '0' and INT_ENA(30) = '1' else '1'; - irq_n(7) <= '0' when PSEUDO_BUS_ERROR = '1' and INT_ENA(31) = '1' else '1'; + irq_n(2) <= '0' WHEN hsync = '1' AND int_ena(26) = '1' ELSE '1'; + irq_n(3) <= '0' WHEN int_ctr(0) = '1' AND int_ena(27) = '1' ELSE '1'; + irq_n(4) <= '0' WHEN vsync = '1' AND int_ena(28) = '1' ELSE '1'; + irq_n(5) <= '0' WHEN int_latch /= x"00000000" AND int_ena(29) = '1' ELSE '1'; + irq_n(6) <= '0' WHEN mfp_int_n = '0' AND int_ena(30) = '1' ELSE '1'; + irq_n(7) <= '0' WHEN pseudo_bus_error = '1' AND int_ena(31) = '1' ELSE '1'; - PSEUDO_BUS_ERROR <= '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F8C8" else -- SCC - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2 - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2 - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2 - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR - '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND - -- '1' when fb_cs_n(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND + pseudo_bus_error <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F8C8" ELSE -- SCC + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F8E0" ELSE -- VME + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F920" ELSE -- PADDLE + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F921" ELSE -- PADDLE + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F922" ELSE -- PADDLE + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFA8" ELSE -- MFP2 + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFA9" ELSE -- MFP2 + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFAA" ELSE -- MFP2 + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFA8" ELSE -- MFP2 + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 8) = x"F87" ELSE -- TT SCSI + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFC2" ELSE -- ST UHR + '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"FFC3" ELSE '0'; -- ST UHR + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F890" ELSE -- DMA SOUND + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F891" ELSE -- DMA SOUND + -- '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 4) = x"F892" ELSE '0'; -- DMA SOUND -- IF video ADR changes: - TIN0 <= '1' when fb_cs_n(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = 19x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2. + tin0 <= '1' WHEN fb_cs_n(1) = '0' AND fb_wr_n = '0' AND fb_adr(19 DOWNTO 1) = 19x"7C100" ELSE '0'; -- Write video base address high 0xFFFF8201/2. - P_INT_LATCH : process - begin - wait until rising_edge(CLK_MAIN); - if RESETn = '0' then - INT_L <= (others => '0'); - else - INT_L(0) <= PIC_INT and INT_ENA(0); - INT_L(1) <= E0_INT and INT_ENA(1); - INT_L(2) <= DVI_INT and INT_ENA(2); - INT_L(3) <= not PCI_INTAn and INT_ENA(3); - INT_L(4) <= not PCI_INTBn and INT_ENA(4); - INT_L(5) <= not PCI_INTCn and INT_ENA(5); - INT_L(6) <= not PCI_INTDn and INT_ENA(6); - INT_L(7) <= DSP_INT and INT_ENA(7); - INT_L(8) <= VSYNC and INT_ENA(8); - INT_L(9) <= HSYNC and INT_ENA(9); - end if; + P_INT_LATCH : PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + IF reset_n = '0' THEN + int_l <= (OTHERS => '0'); + ELSE + int_l(0) <= pic_int AND int_ena(0); + int_l(1) <= e0_int AND int_ena(1); + int_l(2) <= dvi_int AND int_ena(2); + int_l(3) <= NOT pci_inta_n AND int_ena(3); + int_l(4) <= NOT pci_intb_n AND int_ena(4); + int_l(5) <= NOT pci_intc_n AND int_ena(5); + int_l(6) <= NOT pci_intd_n AND int_ena(6); + int_l(7) <= dsp_int AND int_ena(7); + int_l(8) <= vsync AND int_ena(8); + int_l(9) <= hsync AND int_ena(9); + END IF; - for i in 0 to 9 loop - if INT_ENA(i) = '1' and RESETn = '1' then - INT_LA(i) <= x"0"; - elsif INT_L(i) = '1' and INT_LA(i) < x"7" then - INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1); - elsif INT_L(i) = '0' and INT_LA(i) > x"8" then - INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1); - elsif INT_L(i) = '1' and INT_LA(i) > x"6" then - INT_LA(i) <= x"F"; - elsif INT_L(i) = '0' and INT_LA(i) > x"9" then - INT_LA(i) <= x"0"; - end if; - end loop; + FOR i IN 0 TO 9 LOOP + IF int_ena(i) = '1' AND reset_n = '1' THEN + int_la(i) <= x"0"; + ELSIF int_l(i) = '1' AND int_la(i) < x"7" THEN + int_la(i) <= STD_LOGIC_VECTOR(UNSIGNED(int_la(i)) + 1); + ELSIF int_l(i) = '0' AND int_la(i) > x"8" THEN + int_la(i) <= STD_LOGIC_VECTOR(UNSIGNED(int_la(i)) - 1); + ELSIF int_l(i) = '1' AND int_la(i) > x"6" THEN + int_la(i) <= x"F"; + ELSIF int_l(i) = '0' AND int_la(i) > x"9" THEN + int_la(i) <= x"0"; + END IF; + END LOOP; - for i in 0 to 31 loop - if INT_CLEAR(i) = '0' and RESETn = '1' then - INT_LATCH(i) <= '0'; - end if; - end loop; + FOR i IN 0 TO 31 LOOP + IF int_clear(i) = '0' AND reset_n = '1' THEN + int_latch(i) <= '0'; + END IF; + END LOOP; - for i in 0 to 9 loop - if INT_LA(i)(3) = '1' then - INT_LATCH(i) <= '1'; - end if; - end loop; - end process P_INT_LATCH; + FOR i IN 0 TO 9 LOOP + IF int_la(i)(3) = '1' THEN + int_latch(i) <= '1'; + END IF; + END LOOP; + END PROCESS P_INT_LATCH; - -- INT_IN: - INT_IN(0) <= PIC_INT; - INT_IN(1) <= E0_INT; - INT_IN(2) <= DVI_INT; - INT_IN(3) <= not PCI_INTAn; - INT_IN(4) <= not PCI_INTBn; - INT_IN(5) <= not PCI_INTCn; - INT_IN(6) <= not PCI_INTDn; - INT_IN(7) <= DSP_INT; - INT_IN(8) <= VSYNC; - INT_IN(9) <= HSYNC; - INT_IN(25 downto 10) <= x"0000"; - INT_IN(26) <= HSYNC; - INT_IN(27) <= INT_CTR(0); - INT_IN(28) <= VSYNC; - INT_IN(29) <= '1' when INT_LATCH /= x"00000000"; - INT_IN(30) <= not MFP_INTn; - INT_IN(31) <= DRQ_DMA; + -- int_in: + int_in(0) <= pic_int; + int_in(1) <= e0_int; + int_in(2) <= dvi_int; + int_in(3) <= NOT pci_inta_n; + int_in(4) <= NOT pci_intb_n; + int_in(5) <= NOT pci_intc_n; + int_in(6) <= NOT pci_intd_n; + int_in(7) <= dsp_int; + int_in(8) <= vsync; + int_in(9) <= hsync; + int_in(25 DOWNTO 10) <= x"0000"; + int_in(26) <= hsync; + int_in(27) <= int_ctr(0); + int_in(28) <= vsync; + int_in(29) <= '1' WHEN int_latch /= x"00000000"; + int_in(30) <= NOT mfp_int_n; + int_in(31) <= drq_dma; - FBEE_CONF_CS <= '1' when fb_cs_n(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4. + fbee_conf_cs <= '1' WHEN fb_cs_n(2) = '0' AND fb_adr(27 DOWNTO 2) = "00000001000000000000000000" ELSE '0'; -- $40000/4. - P_FBEE_CONFIG : process + p_fbee_config : PROCESS -- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE - begin - wait until rising_edge(CLK_MAIN); - if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24); - elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16); - elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8); - elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then - FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0); - end if; - FBEE_CONF <= FBEE_CONF_REG; - end process P_FBEE_CONFIG; + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + IF fbee_conf_cs = '1' AND fb_b(0) = '1' AND fb_wr_n = '0' THEN + fbee_conf_reg(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24); + ELSIF fbee_conf_cs = '1' AND fb_b(1) = '1' AND fb_wr_n = '0' THEN + fbee_conf_reg(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16); + ELSIF fbee_conf_cs = '1' AND fb_b(2) = '1' AND fb_wr_n = '0' THEN + fbee_conf_reg(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8); + ELSIF fbee_conf_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN + fbee_conf_reg(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0); + END IF; + fbee_conf <= fbee_conf_reg; + END PROCESS p_fbee_config; - -- Data out multiplexers: - FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; - FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; - FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; - FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not fb_oe_n; + -- Data OUT multiplexers: + fb_ad_en_31_24 <= (int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs or fbee_conf_cs) AND NOT fb_oe_n; + fb_ad_en_23_16 <= (int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs or fbee_conf_cs) AND NOT fb_oe_n; + fb_ad_en_15_8 <= (int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs or fbee_conf_cs) AND NOT fb_oe_n; + fb_ad_en_7_0 <= (int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs or fbee_conf_cs) AND NOT fb_oe_n; - FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else - INT_ENA(31 downto 24) when INT_ENA_CS = '1' else - INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else - INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24); + fb_ad_out(31 DOWNTO 24) <= int_ctr(31 DOWNTO 24) WHEN int_ctr_cs = '1' ELSE + int_ena(31 DOWNTO 24) WHEN int_ena_cs = '1' ELSE + int_latch(31 DOWNTO 24) WHEN int_latch_cs = '1' ELSE + int_in(31 DOWNTO 24) WHEN int_clear_cs = '1' ELSE fbee_conf_reg(31 DOWNTO 24); - FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else - INT_ENA(23 downto 16) when INT_ENA_CS = '1' else - INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else - INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16); + fb_ad_out(23 DOWNTO 16) <= int_ctr(23 DOWNTO 16) WHEN int_ctr_cs = '1' ELSE + int_ena(23 DOWNTO 16) WHEN int_ena_cs = '1' ELSE + int_latch(23 DOWNTO 16) WHEN int_latch_cs = '1' ELSE + int_in(23 DOWNTO 16) WHEN int_clear_cs = '1' ELSE fbee_conf_reg(23 DOWNTO 16); - FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else - INT_ENA(15 downto 8) when INT_ENA_CS = '1' else - INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else - INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8); + fb_ad_out(15 DOWNTO 8) <= int_ctr(15 DOWNTO 8) WHEN int_ctr_cs = '1' ELSE + int_ena(15 DOWNTO 8) WHEN int_ena_cs = '1' ELSE + int_latch(15 DOWNTO 8) WHEN int_latch_cs = '1' ELSE + int_clear(15 DOWNTO 8) WHEN int_clear_cs = '1' ELSE fbee_conf_reg(15 DOWNTO 8); - FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else - INT_ENA(7 downto 0) when INT_ENA_CS = '1' else - INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else - INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0); + fb_ad_out(7 DOWNTO 0) <= int_ctr(7 DOWNTO 0) WHEN int_ctr_cs = '1' ELSE + int_ena(7 DOWNTO 0) WHEN int_ena_cs = '1' ELSE + int_latch(7 DOWNTO 0) WHEN int_latch_cs = '1' ELSE + int_clear(7 DOWNTO 0) WHEN int_clear_cs = '1' ELSE fbee_conf_reg(7 DOWNTO 0); - INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS; -end architecture BEHAVIOUR; + int_handler_ta <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs; +END ARCHITECTURE BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd index 399a13b..93800b0 100644 --- a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd +++ b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd @@ -53,7 +53,7 @@ entity IDE_CF_SD_ROM is FB_ADR : in std_logic_vector(19 downto 5); FB_CS1n : in std_logic; - FB_WRn : in std_logic; + fb_wr_n : in std_logic; FB_B0 : in std_logic; FB_B1 : in std_logic; @@ -100,10 +100,10 @@ architecture BEHAVIOUR of IDE_CF_SD_ROM is signal NEXT_IDE_RDn : std_logic; signal NEXT_IDE_WRn : std_logic; begin - ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = "101" else '0'; -- FFF A'0000/2'0000 + ROM_CS <= '1' when FB_CS1n = '0' and fb_wr_n = '1' and FB_ADR(19 downto 17) = "101" else '0'; -- FFF A'0000/2'0000 - RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; - RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; + RP_UDSn <= '0' when fb_wr_n = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; + RP_LDSn <= '0' when fb_wr_n = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = 13x"1" else '0'; -- FFF0'0000/80 @@ -130,14 +130,14 @@ begin end if; end process IDE_CMD_REG; - IDE_CMD_DECODER: process(CMD_STATE, IDE_CF_CS, FB_WRn, IDE_RDY) + IDE_CMD_DECODER: process(CMD_STATE, IDE_CF_CS, fb_wr_n, IDE_RDY) begin case CMD_STATE is when IDLE => IDE_CF_TA <= '0'; if IDE_CF_CS = '1' then - NEXT_IDE_RDn <= not FB_WRn; - NEXT_IDE_WRn <= FB_WRn; + NEXT_IDE_RDn <= not fb_wr_n; + NEXT_IDE_WRn <= fb_wr_n; NEXT_CMD_STATE <= T1; else NEXT_IDE_RDn <= '1'; @@ -146,8 +146,8 @@ begin end if; when T1 => IDE_CF_TA <= '0'; - NEXT_IDE_RDn <= not FB_WRn; - NEXT_IDE_WRn <= FB_WRn; + NEXT_IDE_RDn <= not fb_wr_n; + NEXT_IDE_WRn <= fb_wr_n; NEXT_CMD_STATE <= T6; when T6 => IF IDE_RDY = '1' then @@ -157,8 +157,8 @@ begin NEXT_CMD_STATE <= T7; else IDE_CF_TA <= '0'; - NEXT_IDE_RDn <= not FB_WRn; - NEXT_IDE_WRn <= FB_WRn; + NEXT_IDE_RDn <= not fb_wr_n; + NEXT_IDE_WRn <= fb_wr_n; NEXT_CMD_STATE <= T6; end if; when T7 => @@ -175,6 +175,6 @@ begin SD_CMD_D1_OUT <= '0'; SD_CMD_D1_EN <= '0'; - ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000 - ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000 + ROM4n <= '0' when FB_CS1n = '0' and fb_wr_n = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000 + ROM3n <= '0' when FB_CS1n = '0' and fb_wr_n = '1' and FB_ADR(19 downto 17) = 3x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000 end architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/io_register.vhd b/vhdl/rtl/vhdl/io_register.vhd index 37c3afe..cf07b1f 100644 --- a/vhdl/rtl/vhdl/io_register.vhd +++ b/vhdl/rtl/vhdl/io_register.vhd @@ -44,8 +44,8 @@ ARCHITECTURE rtl OF io_register IS BEGIN register_select : PROCESS BEGIN - IF address_bus AND address_mask = address AND address_mask THEN + /* IF (address_bus AND address_mask) = (address AND address_mask) THEN sel <= '1'; - END IF; + END IF; */ END PROCESS register_select; END rtl; \ No newline at end of file