diff --git a/vhdl/testbenches/ddr2_ram_model.vhd b/vhdl/testbenches/ddr2_ram_model.vhd
index bd07421..1b51922 100644
--- a/vhdl/testbenches/ddr2_ram_model.vhd
+++ b/vhdl/testbenches/ddr2_ram_model.vhd
@@ -24,7 +24,9 @@ PACKAGE ddr2_ram_model_pkg IS
         GENERIC
         (
             VERBOSE         : BOOLEAN := TRUE;          -- define if you want additional debug output
-        
+
+            CLOCK_TICK  : TIME := (1000000 / 132000) * 1 ps;     -- time for one clock tick
+
             BA_BITS         : INTEGER := 2;             -- number of banks
             ADDR_BITS       : INTEGER := 13;            -- number of address bits
             DM_BITS         : INTEGER := 2;             -- number of data mask bits
diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd
index 362d931..a4bf7c6 100644
--- a/vhdl/testbenches/ddr_ctlr_tb.vhd
+++ b/vhdl/testbenches/ddr_ctlr_tb.vhd
@@ -108,6 +108,9 @@ BEGIN
     GENERIC MAP
     (
         VERBOSE     => TRUE,          -- define if you want additional debug output
+
+        CLOCK_TICK  => (1000000 / 132000) * 1 ps,     -- time for one clock tick
+
         BA_BITS     => 2,             -- number of banks
         ADDR_BITS   => 13,            -- number of address bits
         DM_BITS     => 2,             -- number of data mask bits