added interrupt controller initialization for PCI error interrupts
This commit is contained in:
Markus Fröschle
@@ -78,10 +78,10 @@ extern uint8_t _EMUTOS_SIZE[];
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*/
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static inline bool pic_txready(void)
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{
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
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return true;
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
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return true;
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return false;
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return false;
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}
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/*
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@@ -89,84 +89,84 @@ static inline bool pic_txready(void)
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*/
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static inline bool pic_rxready(void)
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{
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
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return true;
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if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
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return true;
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return false;
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return false;
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}
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void write_pic_byte(uint8_t value)
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{
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/* Wait until the transmitter is ready or 1000us are passed */
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waitfor(1000, pic_txready);
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/* Wait until the transmitter is ready or 1000us are passed */
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waitfor(1000, pic_txready);
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/* Transmit the byte */
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*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
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/* Transmit the byte */
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*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
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}
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uint8_t read_pic_byte(void)
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{
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/* Wait until a byte has been received or 1000us are passed */
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waitfor(1000, pic_rxready);
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/* Wait until a byte has been received or 1000us are passed */
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waitfor(1000, pic_rxready);
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/* Return the received byte */
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return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
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/* Return the received byte */
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return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
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}
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void pic_init(void)
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{
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char answer[4] = "OLD";
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char answer[4] = "OLD";
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xprintf("initialize the PIC: ");
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xprintf("initialize the PIC: ");
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/* Send the PIC initialization string */
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write_pic_byte('A');
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write_pic_byte('C');
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write_pic_byte('P');
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write_pic_byte('F');
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/* Send the PIC initialization string */
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write_pic_byte('A');
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write_pic_byte('C');
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write_pic_byte('P');
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write_pic_byte('F');
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/* Read the 3-char answer string. Should be "OK!". */
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answer[0] = read_pic_byte();
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answer[1] = read_pic_byte();
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answer[2] = read_pic_byte();
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answer[3] = '\0';
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/* Read the 3-char answer string. Should be "OK!". */
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answer[0] = read_pic_byte();
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answer[1] = read_pic_byte();
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answer[2] = read_pic_byte();
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answer[3] = '\0';
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if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
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{
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dbg("PIC initialization failed. Already initialized?\r\n");
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}
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else
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{
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xprintf("%s\r\n", answer);
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}
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if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
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{
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dbg("PIC initialization failed. Already initialized?\r\n");
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}
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else
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{
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xprintf("%s\r\n", answer);
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}
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}
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void nvram_init(void)
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{
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int i;
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int i;
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xprintf("Restore the NVRAM data: ");
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xprintf("Restore the NVRAM data: ");
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/* Request for NVRAM backup data */
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write_pic_byte(0x01);
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/* Request for NVRAM backup data */
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write_pic_byte(0x01);
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/* Check answer type */
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if (read_pic_byte() != 0x81)
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{
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// FIXME: PIC protocol error
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xprintf("FAILED\r\n");
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return;
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}
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/* Check answer type */
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if (read_pic_byte() != 0x81)
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{
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// FIXME: PIC protocol error
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xprintf("FAILED\r\n");
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return;
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}
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/* Restore the NVRAM backup to the FPGA */
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for (i = 0; i < 64; i++)
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{
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uint8_t data = read_pic_byte();
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*(volatile uint8_t*)0xffff8961 = i;
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*(volatile uint8_t*)0xffff8963 = data;
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}
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/* Restore the NVRAM backup to the FPGA */
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for (i = 0; i < 64; i++)
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{
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uint8_t data = read_pic_byte();
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*(volatile uint8_t*)0xffff8961 = i;
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*(volatile uint8_t*)0xffff8963 = data;
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}
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xprintf("finished\r\n");
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xprintf("finished\r\n");
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}
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#define KBD_ACIA_CONTROL ((uint8_t *) 0xfffffc00)
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@@ -176,77 +176,77 @@ void nvram_init(void)
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void acia_init()
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{
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xprintf("init ACIA: ");
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/* init ACIA */
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* KBD_ACIA_CONTROL = 3; /* master reset */
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NOP();
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xprintf("init ACIA: ");
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/* init ACIA */
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* KBD_ACIA_CONTROL = 3; /* master reset */
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NOP();
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* MIDI_ACIA_CONTROL = 3; /* master reset */
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NOP();
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* MIDI_ACIA_CONTROL = 3; /* master reset */
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NOP();
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* KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
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NOP();
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* KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
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NOP();
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* MFP_INTR_IN_SERVICE_A = -1;
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NOP();
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* MFP_INTR_IN_SERVICE_A = -1;
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NOP();
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* MFP_INTR_IN_SERVICE_B = -1;
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NOP();
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* MFP_INTR_IN_SERVICE_B = -1;
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NOP();
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xprintf("finished\r\n");
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xprintf("finished\r\n");
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}
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void enable_coldfire_interrupts()
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{
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xprintf("enable interrupts: ");
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xprintf("enable interrupts: ");
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#if defined(MACHINE_FIREBEE)
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*FPGA_INTR_CONTROL = 0L; /* disable all interrupts */
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*FPGA_INTR_CONTROL = 0L; /* disable all interrupts */
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#endif /* MACHINE_FIREBEE */
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MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
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MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
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#if defined(MACHINE_FIREBEE)
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/*
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* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
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* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
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*/
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MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
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MCF_GPT_GMS_IEN |
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MCF_GPT_GMS_TMS(1);
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/* route GPT0 interrupt on interrupt controller */
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MCF_INTC_ICR62 = 0x3f; /* interrupt level 7, interrupt priority 7 */
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/*
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* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
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* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
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*/
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MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
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MCF_GPT_GMS_IEN |
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MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
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MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
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MCF_INTC_ICR_IP(7); /* interrupt level 7, interrupt priority 7 */
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MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
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MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
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MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
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MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
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*FPGA_INTR_ENABLE = FPGA_INTR_INT_IRQ7 |
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FPGA_INTR_INT_MFP_IRQ6 |
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FPGA_INTR_INT_FPGA_IRQ5 |
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FPGA_INTR_INT_VSYNC_IRQ4 |
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FPGA_INTR_INT_CTR0_IRQ3 |
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FPGA_INTR_INT_HSYNC_IRQ2 |
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FPGA_INTR_PCI_INTA |
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FPGA_INTR_PCI_INTB |
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FPGA_INTR_PCI_INTC |
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FPGA_INTR_PCI_INTD |
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FPGA_INTR_ETHERNET;
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MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
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MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
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MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
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MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
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*FPGA_INTR_ENABLE = FPGA_INTR_INT_IRQ7 |
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FPGA_INTR_INT_MFP_IRQ6 |
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FPGA_INTR_INT_FPGA_IRQ5 |
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FPGA_INTR_INT_VSYNC_IRQ4 |
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FPGA_INTR_INT_CTR0_IRQ3 |
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FPGA_INTR_INT_HSYNC_IRQ2 |
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FPGA_INTR_PCI_INTA |
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FPGA_INTR_PCI_INTB |
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FPGA_INTR_PCI_INTC |
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FPGA_INTR_PCI_INTD |
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FPGA_INTR_ETHERNET;
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#endif
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xprintf("finished\r\n");
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xprintf("finished\r\n");
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}
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void disable_coldfire_interrupts()
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{
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#if defined(MACHINE_FIREBEE)
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*FPGA_INTR_ENABLE = 0; /* disable all interrupts */
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*FPGA_INTR_ENABLE = 0; /* disable all interrupts */
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#endif /* MACHINE_FIREBEE */
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MCF_EPORT_EPIER = 0x0;
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MCF_EPORT_EPFR = 0x0;
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MCF_INTC_IMRL = 0xfffffffe;
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MCF_INTC_IMRH = 0xffffffff;
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MCF_EPORT_EPIER = 0x0;
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MCF_EPORT_EPFR = 0x0;
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MCF_INTC_IMRL = 0xfffffffe;
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MCF_INTC_IMRH = 0xffffffff;
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}
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@@ -261,175 +261,181 @@ NIF nif2;
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*/
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void init_isr(void)
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{
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isr_init(); /* need to call that explicitely, otherwise isr table might be full */
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isr_init(); /* need to call that explicitely, otherwise isr table might be full */
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/*
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* register the FEC interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
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{
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dbg("unable to register isr for FEC0\r\n");
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return;
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}
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/*
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* register the FEC interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
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{
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dbg("unable to register isr for FEC0\r\n");
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return;
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}
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/*
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* Register the DMA interrupt handler
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*/
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/*
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* Register the DMA interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
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{
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dbg("Error: Unable to register isr for DMA\r\n");
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return;
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}
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if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
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{
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dbg("Error: Unable to register isr for DMA\r\n");
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return;
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}
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dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */
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dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */
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/*
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* register the PIC interrupt handler
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*/
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if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register ISR for PSC3\r\n");
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return;
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}
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/*
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* register the PIC interrupt handler
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*/
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if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register ISR for PSC3\r\n");
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return;
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}
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/*
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* register the XLB PCI interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for XLB PIC interrupts\r\n");
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return;
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}
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MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
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MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
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MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
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MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
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MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
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MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
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MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
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/*
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* register the XLB PCI interrupt handler
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*/
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if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, xlbpci_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
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return;
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}
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MCF_INTC_ICR43 = MCF_INTC_ICR_IL(5) | /* level 5, priority 1 */
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MCF_INTC_ICR_IP(1);
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if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for PCIARB interrupts\r\n");
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MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
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MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
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MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
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MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
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MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
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MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
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MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
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return;
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}
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
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MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
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if (!isr_register_handler(64 + INT_SOURCE_PCIARB, pciarb_interrupt_handler, NULL, NULL))
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{
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dbg("Error: unable to register isr for PCIARB interrupts\r\n");
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return;
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}
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MCF_INTC_ICR41 = MCF_INTC_ICR_IL(5) | /* level 5, priority 0 */
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MCF_INTC_ICR_IP(0);
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
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MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
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}
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void BaS(void)
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{
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uint8_t *src;
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uint8_t *dst = (uint8_t *) TOS;
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uint8_t *src;
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uint8_t *dst = (uint8_t *) TOS;
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#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
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pic_init();
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nvram_init();
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pic_init();
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nvram_init();
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#endif /* MACHINE_FIREBEE */
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xprintf("copy EmuTOS: ");
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xprintf("copy EmuTOS: ");
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/* copy EMUTOS */
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src = (uint8_t *) EMUTOS;
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dma_memcpy(dst, src, EMUTOS_SIZE);
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xprintf("finished\r\n");
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/* copy EMUTOS */
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src = (uint8_t *) EMUTOS;
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dma_memcpy(dst, src, EMUTOS_SIZE);
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xprintf("finished\r\n");
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xprintf("initialize MMU: ");
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mmu_init();
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xprintf("finished\r\n");
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xprintf("initialize MMU: ");
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mmu_init();
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xprintf("finished\r\n");
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xprintf("initialize exception vector table: ");
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vec_init();
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xprintf("finished\r\n");
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xprintf("initialize exception vector table: ");
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vec_init();
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xprintf("finished\r\n");
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xprintf("flush caches: ");
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flush_and_invalidate_caches();
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xprintf("finished\r\n");
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xprintf("enable MMU: ");
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MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
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NOP(); /* force pipeline sync */
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xprintf("finished\r\n");
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xprintf("flush caches: ");
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flush_and_invalidate_caches();
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xprintf("finished\r\n");
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xprintf("enable MMU: ");
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MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
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NOP(); /* force pipeline sync */
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xprintf("finished\r\n");
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#ifdef MACHINE_FIREBEE
|
||||
xprintf("IDE reset: ");
|
||||
/* IDE reset */
|
||||
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
|
||||
wait(1);
|
||||
#ifdef MACHINE_FIREBEE
|
||||
xprintf("IDE reset: ");
|
||||
/* IDE reset */
|
||||
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
|
||||
wait(1);
|
||||
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
|
||||
|
||||
xprintf("finished\r\n");
|
||||
xprintf("enable video: ");
|
||||
/*
|
||||
* video setup (25MHz)
|
||||
*/
|
||||
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
|
||||
xprintf("finished\r\n");
|
||||
xprintf("enable video: ");
|
||||
/*
|
||||
* video setup (25MHz)
|
||||
*/
|
||||
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
|
||||
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
|
||||
|
||||
/* fifo on, refresh on, ddrcs and cke on, video dac on */
|
||||
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
|
||||
/* fifo on, refresh on, ddrcs and cke on, video dac on */
|
||||
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
|
||||
|
||||
xprintf("finished\r\n");
|
||||
xprintf("finished\r\n");
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
sd_card_init();
|
||||
sd_card_init();
|
||||
|
||||
/*
|
||||
* memory setup
|
||||
*/
|
||||
memset((void *) 0x400, 0, 0x400);
|
||||
/*
|
||||
* memory setup
|
||||
*/
|
||||
memset((void *) 0x400, 0, 0x400);
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/* set Falcon bus control register */
|
||||
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
|
||||
/* set Falcon bus control register */
|
||||
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
|
||||
|
||||
* (volatile uint8_t *) 0xffff8007 = 0x48;
|
||||
* (volatile uint8_t *) 0xffff8007 = 0x48;
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
/* ST RAM */
|
||||
/* ST RAM */
|
||||
|
||||
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
|
||||
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
|
||||
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
|
||||
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
|
||||
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
|
||||
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
|
||||
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
|
||||
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
|
||||
|
||||
/* TT-RAM */
|
||||
/* TT-RAM */
|
||||
|
||||
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
|
||||
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
|
||||
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
|
||||
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
|
||||
|
||||
#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
|
||||
acia_init();
|
||||
acia_init();
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
srec_execute("BASFLASH.S19");
|
||||
srec_execute("BASFLASH.S19");
|
||||
|
||||
/* Jump into the OS */
|
||||
typedef void void_func(void);
|
||||
struct rom_header
|
||||
{
|
||||
void *initial_sp;
|
||||
void_func *initial_pc;
|
||||
};
|
||||
/* Jump into the OS */
|
||||
typedef void void_func(void);
|
||||
struct rom_header
|
||||
{
|
||||
void *initial_sp;
|
||||
void_func *initial_pc;
|
||||
};
|
||||
|
||||
xprintf("BaS initialization finished, enable interrupts\r\n");
|
||||
init_isr();
|
||||
enable_coldfire_interrupts();
|
||||
init_pci();
|
||||
video_init();
|
||||
set_ipl(0); /* enable interrupts */
|
||||
xprintf("BaS initialization finished, enable interrupts\r\n");
|
||||
init_isr();
|
||||
enable_coldfire_interrupts();
|
||||
init_pci();
|
||||
video_init();
|
||||
set_ipl(0); /* enable interrupts */
|
||||
|
||||
/* initialize USB devices */
|
||||
init_usb();
|
||||
/* initialize USB devices */
|
||||
init_usb();
|
||||
|
||||
//set_ipl(7); /* disable interrupts */
|
||||
//set_ipl(7); /* disable interrupts */
|
||||
|
||||
xprintf("call EmuTOS\r\n");
|
||||
struct rom_header *os_header = (struct rom_header *) TOS;
|
||||
os_header->initial_pc();
|
||||
xprintf("call EmuTOS\r\n");
|
||||
struct rom_header *os_header = (struct rom_header *) TOS;
|
||||
os_header->initial_pc();
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user