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@@ -45,15 +45,17 @@
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MCF_DSPI_DCTAR_DT(0b0010) | /* 2 */ \
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MCF_DSPI_DCTAR_BR(0b0000); } /* clock / 2 */
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#define SPICLK_SLOW() { MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */ \
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
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MCF_DSPI_DCTAR_PBR_3CLK | /* 1 clock baudrate prescaler */ \
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MCF_DSPI_DCTAR_CSSCK(8) | /* delay scaler * 512 */\
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MCF_DSPI_DCTAR_ASC(8) | /* 2 */ \
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MCF_DSPI_DCTAR_DT(9) | /* 2 */ \
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MCF_DSPI_DCTAR_BR(7); }
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#define SPICLK_SLOW() { \
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MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */ \
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
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MCF_DSPI_DCTAR_PBR_3CLK | /* 1 clock baudrate prescaler */ \
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MCF_DSPI_DCTAR_CSSCK(8) | /* delay scaler * 512 */\
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MCF_DSPI_DCTAR_ASC(8) | /* 2 */ \
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MCF_DSPI_DCTAR_DT(9) | /* 2 */ \
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MCF_DSPI_DCTAR_BR(7); \
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}
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@@ -93,10 +95,7 @@ static volatile DSTATUS Stat = 0 /* STA_NOINIT */; /* Physical drive status */
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static uint8_t CardType; /* Card type flags */
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static uint32_t dspi_fifo_val = // MCF_DSPI_DTFR_CONT | /* enable continous chip select */
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/* CTAS use DCTAR0 for clock and attributes */
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MCF_DSPI_DTFR_CTCNT;
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static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
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/*-----------------------------------------------------------------------*/
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/* Send/Receive data to the MMC (Platform dependent) */
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@@ -211,6 +210,8 @@ static int select(void) /* 1:OK, 0:Timeout */
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*/
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static void power_on(void) /* Enable SSP module */
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{
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MCF_PAD_PAR_DSPI = 0x1fff; /* configure all DSPI GPIO pins for DSPI usage */
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dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
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/*
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* initialize DSPI module configuration register
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*/
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@@ -466,7 +467,13 @@ DSTATUS disk_status(uint8_t drv)
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return Stat; /* Return disk status */
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}
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DSTATUS disk_reset(uint8_t drv)
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{
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if (drv) return STA_NOINIT;
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deselect();
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disk_initialize(0);
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}
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/*-----------------------------------------------------------------------*/
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/* Read sector(s) */
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@@ -474,8 +481,23 @@ DSTATUS disk_status(uint8_t drv)
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DRESULT disk_read(uint8_t drv, uint8_t *buff, uint32_t sector, uint8_t count)
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{
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if (drv || !count) return RES_PARERR; /* Check parameter */
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if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check if drive is ready */
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if (drv)
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{
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xprintf("wrong drive in disk_read()\r\n");
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return RES_PARERR; /* Check parameter */
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}
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if (! count)
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{
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xprintf("wrong coung in disk_read()\r\n");
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return RES_PARERR;
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}
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if (Stat & STA_NOINIT)
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{
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xprintf("drive not ready in disk_read()\r\n");
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return RES_NOTRDY; /* Check if drive is ready */
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}
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if (!(CardType & CT_BLOCK)) sector *= 512; /* LBA or BA conversion (byte addressing cards) */
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@@ -555,8 +577,10 @@ DRESULT disk_write(uint8_t drv, const uint8_t *buff, uint32_t sector, uint8_t co
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}
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deselect();
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if (count)
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if (count) /* we had an error, try a reinit */
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{
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xprintf("disk_write() failed (count=%d)\r\n", count);
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}
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return count ? RES_ERROR : RES_OK; /* Return result */
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}
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@@ -592,18 +616,18 @@ DRESULT disk_ioctl(uint8_t drv, uint8_t ctrl, void *buff)
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if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
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if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */
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csize = csd[9] + ((uint16_t)csd[8] << 8) + ((uint32_t)(csd[7] & 63) << 16) + 1;
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*(uint32_t*)buff = csize << 10;
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* (uint32_t*) buff = csize << 10;
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} else { /* SDC ver 1.XX or MMC ver 3 */
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n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
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csize = (csd[8] >> 6) + ((uint16_t)csd[7] << 2) + ((uint16_t)(csd[6] & 3) << 10) + 1;
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*(uint32_t*)buff = csize << (n - 9);
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* (uint32_t*) buff = csize << (n - 9);
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}
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res = RES_OK;
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}
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break;
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case GET_SECTOR_SIZE : /* Get sector size in unit of byte (WORD) */
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*(uint16_t*)buff = 512;
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* (uint32_t*) buff = 512;
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res = RES_OK;
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break;
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