rename video registers to their Falcon names
This commit is contained in:
Markus Fröschle
@@ -93,15 +93,15 @@ VARIABLE
|
||||
ACP_VIDEO_ON :NODE;
|
||||
SYS_CTR[6..0] :DFFE;
|
||||
SYS_CTR_CS :NODE;
|
||||
VDL_LOF[15..0] :DFFE;
|
||||
VDL_LOF_CS :NODE;
|
||||
VDL_LWD[15..0] :DFFE;
|
||||
VDL_LWD_CS :NODE;
|
||||
LOF[15..0] :DFFE;
|
||||
LOF_CS :NODE;
|
||||
LWD[15..0] :DFFE;
|
||||
LWD_CS :NODE;
|
||||
-- DIV. CONTROL REGISTER
|
||||
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
|
||||
HSYNC :DFF;
|
||||
HSYNC_I[7..0] :DFF;
|
||||
HSY_LEN[7..0] :DFF; -- L<EFBFBD>NGE HSYNC PULS IN PIXEL_CLK
|
||||
HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK
|
||||
HSYNC_START :DFF;
|
||||
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
|
||||
VSYNC :DFF;
|
||||
@@ -113,9 +113,9 @@ VARIABLE
|
||||
DPO_ON :DFF;
|
||||
DPO_OFF :DFF;
|
||||
VDTRON :DFF;
|
||||
VDO_ZL :DFFE;
|
||||
VDO_ON :DFF;
|
||||
VDO_OFF :DFF;
|
||||
VCO_ZL :DFFE;
|
||||
VCO_ON :DFF;
|
||||
VCO_OFF :DFF;
|
||||
VHCNT[11..0] :DFF;
|
||||
SUB_PIXEL_CNT[6..0] :DFFE;
|
||||
VVCNT[10..0] :DFFE;
|
||||
@@ -150,18 +150,18 @@ VARIABLE
|
||||
H_TOTAL[11..0] :NODE;
|
||||
HDIS_LEN[11..0] :NODE;
|
||||
MULF[5..0] :NODE;
|
||||
VDL_HHT[11..0] :DFFE;
|
||||
VDL_HHT_CS :NODE;
|
||||
VDL_HBE[11..0] :DFFE;
|
||||
VDL_HBE_CS :NODE;
|
||||
VDL_HDB[11..0] :DFFE;
|
||||
VDL_HDB_CS :NODE;
|
||||
VDL_HDE[11..0] :DFFE;
|
||||
VDL_HDE_CS :NODE;
|
||||
VDL_HBB[11..0] :DFFE;
|
||||
VDL_HBB_CS :NODE;
|
||||
VDL_HSS[11..0] :DFFE;
|
||||
VDL_HSS_CS :NODE;
|
||||
HHT[11..0] :DFFE;
|
||||
HHT_CS :NODE;
|
||||
HBE[11..0] :DFFE;
|
||||
HBE_CS :NODE;
|
||||
HDB[11..0] :DFFE;
|
||||
HDB_CS :NODE;
|
||||
HDE[11..0] :DFFE;
|
||||
HDE_CS :NODE;
|
||||
HBB[11..0] :DFFE;
|
||||
HBB_CS :NODE;
|
||||
HSS[11..0] :DFFE;
|
||||
HSS_CS :NODE;
|
||||
-- VERTIKAL
|
||||
RAND_OBEN[10..0] :NODE;
|
||||
VDIS_START[10..0] :NODE;
|
||||
@@ -175,22 +175,22 @@ VARIABLE
|
||||
DOP_ZEI :DFF;
|
||||
DOP_FIFO_CLR :DFF;
|
||||
|
||||
VDL_VBE[10..0] :DFFE;
|
||||
VDL_VBE_CS :NODE;
|
||||
VDL_VDB[10..0] :DFFE;
|
||||
VDL_VDB_CS :NODE;
|
||||
VDL_VDE[10..0] :DFFE;
|
||||
VDL_VDE_CS :NODE;
|
||||
VDL_VBB[10..0] :DFFE;
|
||||
VDL_VBB_CS :NODE;
|
||||
VDL_VSS[10..0] :DFFE;
|
||||
VDL_VSS_CS :NODE;
|
||||
VDL_VFT[10..0] :DFFE;
|
||||
VDL_VFT_CS :NODE;
|
||||
VDL_VCT[8..0] :DFFE;
|
||||
VDL_VCT_CS :NODE;
|
||||
VDL_VMD[3..0] :DFFE;
|
||||
VDL_VMD_CS :NODE;
|
||||
VBE[10..0] :DFFE;
|
||||
VBE_CS :NODE;
|
||||
VDB[10..0] :DFFE;
|
||||
VDB_CS :NODE;
|
||||
VDE[10..0] :DFFE;
|
||||
VDE_CS :NODE;
|
||||
VBB[10..0] :DFFE;
|
||||
VBB_CS :NODE;
|
||||
VSS[10..0] :DFFE;
|
||||
VSS_CS :NODE;
|
||||
VFT[10..0] :DFFE;
|
||||
VFT_CS :NODE;
|
||||
VCO[8..0] :DFFE;
|
||||
VCO_CS :NODE;
|
||||
VCNTRL[3..0] :DFFE;
|
||||
VCNTRL_CS :NODE;
|
||||
|
||||
BEGIN
|
||||
-- BYT SELECT 32 BIT
|
||||
@@ -242,7 +242,21 @@ BEGIN
|
||||
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
|
||||
|
||||
-- ACP VIDEO CONTROL
|
||||
-- BIT 0 = ACP VIDEO ON
|
||||
-- BIT 1 = POWER ON VIDEO DAC
|
||||
-- BIT 2 = ACP 24BIT
|
||||
-- BIT 3 = ACP 16BIT
|
||||
-- BIT 4 = ACP 8BIT
|
||||
-- BIT 5 = ACP 1BIT
|
||||
-- BIT 6 = FALCON SHIFT MODE
|
||||
-- BIT 7 = ST SHIFT MODE
|
||||
-- BIT 9..8 = VCLK FREQUENZ
|
||||
-- BIT 15 =-SYNC ALLOWED
|
||||
-- BIT 31..16 = VIDEO_RAM_CTR
|
||||
-- BIT 25 = RANDFARBE EINSCHALTEN
|
||||
-- BIT 26 = STANDARD ATARI SYNCS
|
||||
ACP_VCTR[].CLK = MAIN_CLK;
|
||||
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4
|
||||
ACP_VCTR[31..8] = FB_AD[31..8];
|
||||
@@ -254,41 +268,46 @@ BEGIN
|
||||
ACP_VIDEO_ON = ACP_VCTR0;
|
||||
nPD_VGA = ACP_VCTR1;
|
||||
-- ATARI MODUS
|
||||
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<EFBFBD>SUNG
|
||||
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG
|
||||
|
||||
-- HORIZONTAL TIMING 640x480
|
||||
ATARI_HH[].CLK = MAIN_CLK;
|
||||
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
|
||||
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2] == H"104"; -- $410/4
|
||||
ATARI_HH[] = FB_AD[];
|
||||
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
|
||||
|
||||
-- VERTIKAL TIMING 640x480
|
||||
ATARI_VH[].CLK = MAIN_CLK;
|
||||
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
|
||||
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2] == H"105"; -- $414/4
|
||||
ATARI_VH[] = FB_AD[];
|
||||
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
|
||||
|
||||
-- HORIZONTAL TIMING 320x240
|
||||
ATARI_HL[].CLK = MAIN_CLK;
|
||||
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
|
||||
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2] == H"106"; -- $418/4
|
||||
ATARI_HL[] = FB_AD[];
|
||||
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
|
||||
|
||||
-- VERTIKAL TIMING 320x240
|
||||
ATARI_VL[].CLK = MAIN_CLK;
|
||||
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
|
||||
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2] == H"107"; -- $41C/4
|
||||
ATARI_VL[] = FB_AD[];
|
||||
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
|
||||
|
||||
-- VIDEO PLL CONFIG
|
||||
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
|
||||
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9] == H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
|
||||
VR_WR.CLK = MAIN_CLK;
|
||||
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
|
||||
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
|
||||
@@ -296,10 +315,11 @@ BEGIN
|
||||
VR_DOUT[].ENA = !VR_BUSY;
|
||||
VR_DOUT[] = VR_D[];
|
||||
VR_FRQ[].CLK = MAIN_CLK;
|
||||
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
|
||||
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0] == H"04";
|
||||
VR_FRQ[] = FB_AD[23..16];
|
||||
|
||||
-- VIDEO PLL RECONFIG
|
||||
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
|
||||
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0] == H"800" & FB_B0; -- $(F)000'0800
|
||||
VIDEO_RECONFIG.CLK = MAIN_CLK;
|
||||
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
|
||||
------------------------------------------------------------------------------------------------------------------------
|
||||
@@ -310,6 +330,7 @@ BEGIN
|
||||
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
|
||||
|
||||
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
|
||||
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
|
||||
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
|
||||
@@ -325,6 +346,7 @@ BEGIN
|
||||
# B"101" & COLOR16
|
||||
# B"110" & COLOR24
|
||||
# B"111" & RAND_ON;
|
||||
|
||||
-- DIVERSE (VIDEO)-REGISTER ----------------------------
|
||||
-- RANDFARBE
|
||||
CCR[].CLK = MAIN_CLK;
|
||||
@@ -333,282 +355,351 @@ BEGIN
|
||||
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
|
||||
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
|
||||
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
|
||||
--SYS CTR
|
||||
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
|
||||
|
||||
-- System Config Register
|
||||
-- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi
|
||||
-- ||||||||
|
||||
-- |||||||+- RAM Wait Status
|
||||
-- ||||||| 0 = 1 Wait (default)
|
||||
-- ||||||| 1 = 0 Wait
|
||||
-- ||||||+-- Video Bus Width
|
||||
-- |||||| 0 = 16 Bit
|
||||
-- |||||| 1 = 32 Bit (default)
|
||||
-- ||||++--- ROM Wait Status
|
||||
-- |||| 00 = reserved
|
||||
-- |||| 01 = 2 Wait (default)
|
||||
-- |||| 10 = 1 Wait
|
||||
-- |||| 11 = 0 Wait
|
||||
-- ||++----- Main Memory Size
|
||||
-- || 01 = 4 MB
|
||||
-- || 10 = 16 MB
|
||||
-- ++------- Monitor Type
|
||||
-- 00 Monochrome
|
||||
-- 01 RGB
|
||||
-- 10 VGA
|
||||
-- 11 TV
|
||||
|
||||
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C003"; -- $8006/2
|
||||
SYS_CTR[].CLK = MAIN_CLK;
|
||||
SYS_CTR[6..0] = FB_AD[22..16];
|
||||
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
|
||||
BLITTER_ON = !SYS_CTR3;
|
||||
--VDL_LOF
|
||||
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
|
||||
VDL_LOF[].CLK = MAIN_CLK;
|
||||
VDL_LOF[] = FB_AD[31..16];
|
||||
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
|
||||
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
|
||||
--VDL_LWD
|
||||
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
|
||||
VDL_LWD[].CLK = MAIN_CLK;
|
||||
VDL_LWD[] = FB_AD[31..16];
|
||||
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
|
||||
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- LOF
|
||||
LOF_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C107"; -- $820E/2
|
||||
LOF[].CLK = MAIN_CLK;
|
||||
LOF[] = FB_AD[31..16];
|
||||
LOF[15..8].ENA = LOF_CS & !nFB_WR & FB_B2;
|
||||
LOF[7..0].ENA = LOF_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- LWD
|
||||
LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
|
||||
LWD[].CLK = MAIN_CLK;
|
||||
LWD[] = FB_AD[31..16];
|
||||
LWD[15..8].ENA = LWD_CS & !nFB_WR & FB_B0;
|
||||
LWD[7..0].ENA = LWD_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- HORIZONTAL
|
||||
-- VDL_HHT
|
||||
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
|
||||
VDL_HHT[].CLK = MAIN_CLK;
|
||||
VDL_HHT[] = FB_AD[27..16];
|
||||
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
|
||||
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HBE
|
||||
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
|
||||
VDL_HBE[].CLK = MAIN_CLK;
|
||||
VDL_HBE[] = FB_AD[27..16];
|
||||
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
|
||||
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HDB
|
||||
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
|
||||
VDL_HDB[].CLK = MAIN_CLK;
|
||||
VDL_HDB[] = FB_AD[27..16];
|
||||
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
|
||||
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_HDE
|
||||
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
|
||||
VDL_HDE[].CLK = MAIN_CLK;
|
||||
VDL_HDE[] = FB_AD[27..16];
|
||||
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
|
||||
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HBB
|
||||
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
|
||||
VDL_HBB[].CLK = MAIN_CLK;
|
||||
VDL_HBB[] = FB_AD[27..16];
|
||||
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
|
||||
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_HSS
|
||||
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
|
||||
VDL_HSS[].CLK = MAIN_CLK;
|
||||
VDL_HSS[] = FB_AD[27..16];
|
||||
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
|
||||
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
|
||||
-- HHT
|
||||
HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
|
||||
HHT[].CLK = MAIN_CLK;
|
||||
HHT[] = FB_AD[27..16];
|
||||
HHT[11..8].ENA = HHT_CS & !nFB_WR & FB_B2;
|
||||
HHT[7..0].ENA = HHT_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- HBE
|
||||
HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
|
||||
HBE[].CLK = MAIN_CLK;
|
||||
HBE[] = FB_AD[27..16];
|
||||
HBE[11..8].ENA = HBE_CS & !nFB_WR & FB_B2;
|
||||
HBE[7..0].ENA = HBE_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- HDB
|
||||
HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
|
||||
HDB[].CLK = MAIN_CLK;
|
||||
HDB[] = FB_AD[27..16];
|
||||
HDB[11..8].ENA = HDB_CS & !nFB_WR & FB_B0;
|
||||
HDB[7..0].ENA = HDB_CS & !nFB_WR & FB_B1;
|
||||
-- HDE
|
||||
HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
|
||||
HDE[].CLK = MAIN_CLK;
|
||||
HDE[] = FB_AD[27..16];
|
||||
HDE[11..8].ENA = HDE_CS & !nFB_WR & FB_B2;
|
||||
HDE[7..0].ENA = HDE_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- HBB
|
||||
HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
|
||||
HBB[].CLK = MAIN_CLK;
|
||||
HBB[] = FB_AD[27..16];
|
||||
HBB[11..8].ENA = HBB_CS & !nFB_WR & FB_B0;
|
||||
HBB[7..0].ENA = HBB_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- HSS
|
||||
HSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C146"; -- Videl HSYNC start register $828C / 2
|
||||
HSS[].CLK = MAIN_CLK;
|
||||
HSS[] = FB_AD[27..16];
|
||||
HSS[11..8].ENA = HSS_CS & !nFB_WR & FB_B0;
|
||||
HSS[7..0].ENA = HSS_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- VERTIKAL
|
||||
-- VDL_VBE
|
||||
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
|
||||
VDL_VBE[].CLK = MAIN_CLK;
|
||||
VDL_VBE[] = FB_AD[26..16];
|
||||
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
|
||||
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VDB
|
||||
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
|
||||
VDL_VDB[].CLK = MAIN_CLK;
|
||||
VDL_VDB[] = FB_AD[26..16];
|
||||
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
|
||||
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VDE
|
||||
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
|
||||
VDL_VDE[].CLK = MAIN_CLK;
|
||||
VDL_VDE[] = FB_AD[26..16];
|
||||
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
|
||||
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VBB
|
||||
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
|
||||
VDL_VBB[].CLK = MAIN_CLK;
|
||||
VDL_VBB[] = FB_AD[26..16];
|
||||
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
|
||||
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VSS
|
||||
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
|
||||
VDL_VSS[].CLK = MAIN_CLK;
|
||||
VDL_VSS[] = FB_AD[26..16];
|
||||
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
|
||||
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VFT
|
||||
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
|
||||
VDL_VFT[].CLK = MAIN_CLK;
|
||||
VDL_VFT[] = FB_AD[26..16];
|
||||
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
|
||||
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VCT
|
||||
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
|
||||
VDL_VCT[].CLK = MAIN_CLK;
|
||||
VDL_VCT[] = FB_AD[24..16];
|
||||
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
|
||||
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VMD
|
||||
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
|
||||
VDL_VMD[].CLK = MAIN_CLK;
|
||||
VDL_VMD[] = FB_AD[19..16];
|
||||
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
|
||||
-- VBE
|
||||
VBE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C153"; -- $82A6/2
|
||||
VBE[].CLK = MAIN_CLK;
|
||||
VBE[] = FB_AD[26..16];
|
||||
VBE[10..8].ENA = VBE_CS & !nFB_WR & FB_B2;
|
||||
VBE[7..0].ENA = VBE_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- VDB
|
||||
VDB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C154"; -- $82A8/2
|
||||
VDB[].CLK = MAIN_CLK;
|
||||
VDB[] = FB_AD[26..16];
|
||||
VDB[10..8].ENA = VDB_CS & !nFB_WR & FB_B0;
|
||||
VDB[7..0].ENA = VDB_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- VDE
|
||||
VDE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C155"; -- $82AA/2
|
||||
VDE[].CLK = MAIN_CLK;
|
||||
VDE[] = FB_AD[26..16];
|
||||
VDE[10..8].ENA = VDE_CS & !nFB_WR & FB_B2;
|
||||
VDE[7..0].ENA = VDE_CS & !nFB_WR & FB_B3;
|
||||
-- VBB
|
||||
VBB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C152"; -- $82A4/2
|
||||
VBB[].CLK = MAIN_CLK;
|
||||
VBB[] = FB_AD[26..16];
|
||||
VBB[10..8].ENA = VBB_CS & !nFB_WR & FB_B0;
|
||||
VBB[7..0].ENA = VBB_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- VSS
|
||||
VSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C156"; -- $82AC/2
|
||||
VSS[].CLK = MAIN_CLK;
|
||||
VSS[] = FB_AD[26..16];
|
||||
VSS[10..8].ENA = VSS_CS & !nFB_WR & FB_B0;
|
||||
VSS[7..0].ENA = VSS_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- VFT
|
||||
VFT_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C151"; -- $82A2/2
|
||||
VFT[].CLK = MAIN_CLK;
|
||||
VFT[] = FB_AD[26..16];
|
||||
VFT[10..8].ENA = VFT_CS & !nFB_WR & FB_B2;
|
||||
VFT[7..0].ENA = VFT_CS & !nFB_WR & FB_B3;
|
||||
|
||||
-- VCO
|
||||
VCO_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C160"; -- $82C0 / 2 Falcon clock control register VCO
|
||||
VCO[].CLK = MAIN_CLK;
|
||||
VCO[] = FB_AD[24..16];
|
||||
VCO[8].ENA = VCO_CS & !nFB_WR & FB_B0;
|
||||
VCO[7..0].ENA = VCO_CS & !nFB_WR & FB_B1;
|
||||
|
||||
-- VCNTRL
|
||||
VCNTRL_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C161"; -- $82C2 / 2 Falcon resolution control register VCNTRL
|
||||
VCNTRL[].CLK = MAIN_CLK;
|
||||
VCNTRL[] = FB_AD[19..16];
|
||||
VCNTRL[3..0].ENA = VCNTRL_CS & !nFB_WR & FB_B3;
|
||||
|
||||
--- REGISTER OUT
|
||||
-- low word register access
|
||||
FB_AD[31..16] = lpm_bustri_WORD(
|
||||
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
|
||||
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
|
||||
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
|
||||
# VDL_LOF_CS & VDL_LOF[]
|
||||
# VDL_LWD_CS & VDL_LWD[]
|
||||
# VDL_HBE_CS & (0,VDL_HBE[])
|
||||
# VDL_HDB_CS & (0,VDL_HDB[])
|
||||
# VDL_HDE_CS & (0,VDL_HDE[])
|
||||
# VDL_HBB_CS & (0,VDL_HBB[])
|
||||
# VDL_HSS_CS & (0,VDL_HSS[])
|
||||
# VDL_HHT_CS & (0,VDL_HHT[])
|
||||
# VDL_VBE_CS & (0,VDL_VBE[])
|
||||
# VDL_VDB_CS & (0,VDL_VDB[])
|
||||
# VDL_VDE_CS & (0,VDL_VDE[])
|
||||
# VDL_VBB_CS & (0,VDL_VBB[])
|
||||
# VDL_VSS_CS & (0,VDL_VSS[])
|
||||
# VDL_VFT_CS & (0,VDL_VFT[])
|
||||
# VDL_VCT_CS & (0,VDL_VCT[])
|
||||
# VDL_VMD_CS & (0,VDL_VMD[])
|
||||
ST_SHIFT_MODE_CS & (0, ST_SHIFT_MODE[],B"00000000")
|
||||
# FALCON_SHIFT_MODE_CS & (0, FALCON_SHIFT_MODE[])
|
||||
# SYS_CTR_CS & (B"100000000", SYS_CTR[6..4], !BLITTER_RUN, SYS_CTR[2..0])
|
||||
# LOF_CS & LOF[]
|
||||
# LWD_CS & LWD[]
|
||||
# HBE_CS & (0, HBE[])
|
||||
# HDB_CS & (0, HDB[])
|
||||
# HDE_CS & (0, HDE[])
|
||||
# HBB_CS & (0, HBB[])
|
||||
# HSS_CS & (0, HSS[])
|
||||
# HHT_CS & (0, HHT[])
|
||||
# VBE_CS & (0, VBE[])
|
||||
# VDB_CS & (0, VDB[])
|
||||
# VDE_CS & (0, VDE[])
|
||||
# VBB_CS & (0, VBB[])
|
||||
# VSS_CS & (0, VSS[])
|
||||
# VFT_CS & (0, VFT[])
|
||||
# VCO_CS & (0, VCO[])
|
||||
# VCNTRL_CS & (0, VCNTRL[])
|
||||
# ACP_VCTR_CS & ACP_VCTR[31..16]
|
||||
# ATARI_HH_CS & ATARI_HH[31..16]
|
||||
# ATARI_VH_CS & ATARI_VH[31..16]
|
||||
# ATARI_HL_CS & ATARI_HL[31..16]
|
||||
# ATARI_VL_CS & ATARI_VL[31..16]
|
||||
# CCR_CS & (0,CCR[23..16])
|
||||
# CCR_CS & (0, CCR[23..16])
|
||||
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
|
||||
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
|
||||
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
|
||||
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
|
||||
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA")
|
||||
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
|
||||
# HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
|
||||
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
|
||||
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
|
||||
# VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE);
|
||||
|
||||
-- high word register access
|
||||
FB_AD[15..0] = lpm_bustri_WORD(
|
||||
ACP_VCTR_CS & ACP_VCTR[15..0]
|
||||
# ATARI_HH_CS & ATARI_HH[15..0]
|
||||
# ATARI_VH_CS & ATARI_VH[15..0]
|
||||
# ATARI_HL_CS & ATARI_HL[15..0]
|
||||
# ATARI_VL_CS & ATARI_VL[15..0]
|
||||
# CCR_CS & CCR[15..0]
|
||||
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
|
||||
# CCR_CS & CCR[15..0],
|
||||
(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
|
||||
|
||||
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
|
||||
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
|
||||
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
|
||||
# HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
|
||||
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
|
||||
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
|
||||
# VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS;
|
||||
|
||||
-- VIDEO AUSGABE SETZEN
|
||||
CLK17M.CLK = CLK33M;
|
||||
CLK17M = !CLK17M;
|
||||
|
||||
CLK13M.CLK = CLK25M;
|
||||
CLK13M = !CLK13M;
|
||||
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
|
||||
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
|
||||
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
|
||||
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
|
||||
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
|
||||
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
|
||||
|
||||
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz,
|
||||
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz,
|
||||
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, VGA monitor
|
||||
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA monitor
|
||||
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
|
||||
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
|
||||
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- HORIZONTALE SYNC L<EFBFBD>NGE in PIXEL_CLK
|
||||
-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
|
||||
----------------------------------------------------------------
|
||||
HSY_LEN[].CLK = MAIN_CLK;
|
||||
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
|
||||
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
|
||||
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
|
||||
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
|
||||
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
|
||||
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
|
||||
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
|
||||
-- HSY_LEN[].CLK = MAIN_CLK;
|
||||
HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro)
|
||||
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels
|
||||
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 640 pixels
|
||||
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 320 pixels
|
||||
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels
|
||||
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
|
||||
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
|
||||
# 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns
|
||||
|
||||
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
|
||||
# 4 & !ST_VIDEO & !VDL_VMD2
|
||||
# 16 & ST_VIDEO & VDL_VMD2
|
||||
# 32 & ST_VIDEO & !VDL_VMD2;
|
||||
MULF[] = 2 & !ST_VIDEO & VCNTRL2 -- MULTIPLIKATIONS FAKTOR
|
||||
# 4 & !ST_VIDEO & !VCNTRL2
|
||||
# 16 & ST_VIDEO & VCNTRL2
|
||||
# 32 & ST_VIDEO & !VCNTRL2;
|
||||
|
||||
|
||||
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
|
||||
# 640 & !VDL_VMD2;
|
||||
HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN
|
||||
# 640 & !VCNTRL2;
|
||||
|
||||
-- DOPPELZEILENMODUS
|
||||
DOP_ZEI.CLK = MAIN_CLK;
|
||||
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
|
||||
DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS
|
||||
|
||||
INTER_ZEI.CLK = PIXEL_CLK;
|
||||
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
DOP_FIFO_CLR.CLK = PIXEL_CLK;
|
||||
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
|
||||
INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
# DOP_ZEI & VVCNT0 == VDIS_START0 & VVCNT[] != 0 & VHCNT[] > (HDIS_END[] - 2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
|
||||
DOP_FIFO_CLR.CLK = PIXEL_CLK;
|
||||
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
|
||||
|
||||
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
|
||||
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
|
||||
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
|
||||
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
|
||||
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
|
||||
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
|
||||
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
||||
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
||||
# HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
|
||||
HDIS_START[] = HDB[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[] + 1 & !ACP_VIDEO_ON; --
|
||||
|
||||
HDIS_END[] = HDE[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[] + HDIS_LEN[] & !ACP_VIDEO_ON; --
|
||||
|
||||
RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON
|
||||
# HDIS_END[] + 1 & !ACP_VIDEO_ON; --
|
||||
|
||||
HS_START[] = HSS[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
||||
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
||||
# (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
|
||||
H_TOTAL[] = HHT[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
||||
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
||||
# (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
|
||||
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
|
||||
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
|
||||
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
|
||||
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
|
||||
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
|
||||
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
|
||||
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
-- Z<>HLER
|
||||
RAND_OBEN[] = VBE[] & ACP_VIDEO_ON
|
||||
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
|
||||
VDIS_START[] = VDB[] & ACP_VIDEO_ON
|
||||
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0, VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
|
||||
VDIS_END[] = VDE[] & ACP_VIDEO_ON
|
||||
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
|
||||
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
|
||||
# (0, VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
|
||||
RAND_UNTEN[] = VBB[] & ACP_VIDEO_ON
|
||||
# VDIS_END[] + 1 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0, VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
|
||||
VS_START[] = VSS[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
||||
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
||||
# (0, VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
|
||||
V_TOTAL[] = VFT[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
||||
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
||||
# (0, VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
-- ZÄHLER
|
||||
LAST.CLK = PIXEL_CLK;
|
||||
LAST = VHCNT[]==(H_TOTAL[]-2);
|
||||
LAST = VHCNT[] == (H_TOTAL[] - 2);
|
||||
|
||||
VHCNT[].CLK = PIXEL_CLK;
|
||||
VHCNT[] = (VHCNT[] + 1) & !LAST;
|
||||
VVCNT[].CLK = PIXEL_CLK;
|
||||
VVCNT[].ENA = LAST;
|
||||
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
|
||||
VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1);
|
||||
|
||||
-- DISPLAY ON OFF
|
||||
DPO_ZL.CLK = PIXEL_CLK;
|
||||
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
|
||||
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <EFBFBD>BERNEHMEN
|
||||
DPO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
|
||||
DPO_ON.CLK = PIXEL_CLK;
|
||||
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
|
||||
DPO_ON = VHCNT[] == RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
|
||||
|
||||
DPO_OFF.CLK = PIXEL_CLK;
|
||||
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
|
||||
DPO_OFF = VHCNT[] == (RAND_RECHTS[] - 1);
|
||||
|
||||
DISP_ON.CLK = PIXEL_CLK;
|
||||
DISP_ON = DISP_ON & !DPO_OFF
|
||||
# DPO_ON & DPO_ZL;
|
||||
|
||||
-- DATENTRANSFER ON OFF
|
||||
VDO_ON.CLK = PIXEL_CLK;
|
||||
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
|
||||
VDO_OFF.CLK = PIXEL_CLK;
|
||||
VDO_OFF = VHCNT[]==HDIS_END[];
|
||||
VDO_ZL.CLK = PIXEL_CLK;
|
||||
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
|
||||
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
|
||||
VCO_ON.CLK = PIXEL_CLK;
|
||||
VCO_ON = VHCNT[] == (HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
|
||||
|
||||
VCO_OFF.CLK = PIXEL_CLK;
|
||||
VCO_OFF = VHCNT[] == HDIS_END[];
|
||||
|
||||
VCO_ZL.CLK = PIXEL_CLK;
|
||||
VCO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
|
||||
VCO_ZL = (VVCNT[] >= (VDIS_START[] - 1)) & (VVCNT[] < VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
|
||||
|
||||
VDTRON.CLK = PIXEL_CLK;
|
||||
VDTRON = VDTRON & !VDO_OFF
|
||||
# VDO_ON & VDO_ZL;
|
||||
-- VERZ<52>GERUNG UND SYNC
|
||||
VDTRON = VDTRON & !VCO_OFF
|
||||
# VCO_ON & VCO_ZL;
|
||||
|
||||
-- VERZÖGERUNG UND SYNC
|
||||
HSYNC_START.CLK = PIXEL_CLK;
|
||||
HSYNC_START = VHCNT[]==HS_START[]-3;
|
||||
HSYNC_START = VHCNT[] == HS_START[] - 3;
|
||||
|
||||
HSYNC_I[].CLK = PIXEL_CLK;
|
||||
HSYNC_I[] = HSY_LEN[] & HSYNC_START
|
||||
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
|
||||
HSYNC_I[] = HSY_LEN[] & HSYNC_START
|
||||
# (HSYNC_I[] - 1) & !HSYNC_START & HSYNC_I[] != 0;
|
||||
|
||||
VSYNC_START.CLK = PIXEL_CLK;
|
||||
VSYNC_START.ENA = LAST;
|
||||
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
|
||||
VSYNC_START = VVCNT[] == (VS_START[] - 3); -- start am ende der Zeile vor dem vsync
|
||||
|
||||
VSYNC_I[].CLK = PIXEL_CLK;
|
||||
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
|
||||
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
|
||||
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<EFBFBD>hlen bis 0
|
||||
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[] != 0; -- runterzählen bis 0
|
||||
|
||||
VERZ[][].CLK = PIXEL_CLK;
|
||||
VERZ[][1] = VERZ[][0];
|
||||
VERZ[][2] = VERZ[][1];
|
||||
@@ -620,18 +711,23 @@ BEGIN
|
||||
VERZ[][8] = VERZ[][7];
|
||||
VERZ[][9] = VERZ[][8];
|
||||
VERZ[0][0] = DISP_ON;
|
||||
-- VERZ[1][0] = HSYNC_I[]!=0;
|
||||
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
|
||||
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<EFBFBD>GLICH WENN BEIDE
|
||||
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
|
||||
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<EFBFBD>GLICH WENN BEIDE
|
||||
-- VERZ[1][0] = HSYNC_I[] != 0;
|
||||
VERZ[1][0] = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0
|
||||
# ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
|
||||
VERZ[2][0] = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0
|
||||
# ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
|
||||
|
||||
nBLANK.CLK = PIXEL_CLK;
|
||||
nBLANK = VERZ[0][8];
|
||||
|
||||
HSYNC.CLK = PIXEL_CLK;
|
||||
HSYNC = VERZ[1][9];
|
||||
|
||||
VSYNC.CLK = PIXEL_CLK;
|
||||
VSYNC = VERZ[2][9];
|
||||
|
||||
nSYNC = GND;
|
||||
|
||||
-- RANDFARBE MACHEN ------------------------------------
|
||||
RAND[].CLK = PIXEL_CLK;
|
||||
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
|
||||
@@ -643,31 +739,37 @@ BEGIN
|
||||
RAND[6] = RAND[5];
|
||||
RAND_ON = RAND[6];
|
||||
----------------------------------------------------------
|
||||
|
||||
CLR_FIFO.CLK = PIXEL_CLK;
|
||||
CLR_FIFO.ENA = LAST;
|
||||
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<EFBFBD>SCHEN
|
||||
CLR_FIFO = VVCNT[] == V_TOTAL[] - 2; -- IN LETZTER ZEILE LÖSCHEN
|
||||
|
||||
START_ZEILE.CLK = PIXEL_CLK;
|
||||
START_ZEILE.ENA = LAST;
|
||||
START_ZEILE = VVCNT[]==0; -- ZEILE 1
|
||||
START_ZEILE = VVCNT[] == 0; -- ZEILE 1
|
||||
|
||||
SYNC_PIX.CLK = PIXEL_CLK;
|
||||
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN
|
||||
SYNC_PIX = VHCNT[] == 3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
|
||||
SYNC_PIX1.CLK = PIXEL_CLK;
|
||||
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN
|
||||
SYNC_PIX1 = VHCNT[] == 5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
|
||||
SYNC_PIX2.CLK = PIXEL_CLK;
|
||||
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN
|
||||
SYNC_PIX2 = VHCNT[] == 7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
|
||||
|
||||
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
|
||||
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
|
||||
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
|
||||
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
|
||||
|
||||
FIFO_RDE.CLK = PIXEL_CLK;
|
||||
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
|
||||
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
|
||||
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
|
||||
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
|
||||
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
|
||||
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
|
||||
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<EFBFBD>TZLICH F<EFBFBD>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
|
||||
FIFO_RDE = (SUB_PIXEL_CNT[6..0] == 1 & COLOR1
|
||||
# SUB_PIXEL_CNT[5..0] == 1 & COLOR2
|
||||
# SUB_PIXEL_CNT[4..0] == 1 & COLOR4
|
||||
# SUB_PIXEL_CNT[3..0] == 1 & COLOR8
|
||||
# SUB_PIXEL_CNT[2..0] == 1 & COLOR16
|
||||
# SUB_PIXEL_CNT[1..0] == 1 & COLOR24) & VDTRON
|
||||
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
|
||||
|
||||
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
|
||||
|
||||
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
|
||||
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
|
||||
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
|
||||
|
||||
Reference in New Issue
Block a user