added radeon_vid.c
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@@ -1,7 +1,6 @@
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#ifndef __RADEONFB_H__
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#define __RADEONFB_H__
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//#include "config.h"
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#include <bas_string.h>
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#include "pci.h"
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#include "mod_devicetable.h"
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@@ -13,16 +12,6 @@
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//#include "radeon_theatre.h"
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#include "radeon_reg.h"
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#ifndef point32_ter
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#define point32_ter void*
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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/* Buffer are aligned on 4096 byte boundaries */
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#define RADEON_BUFFER_ALIGN 0x00000fff
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@@ -488,12 +477,12 @@ extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr);
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extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val);
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extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask);
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#define INREG8(addr) *((uint8_t *)(rinfo->mmio_base+addr))
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#define INREG16(addr) swpw(*(uint16_t *)(rinfo->mmio_base+addr))
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#define INREG(addr) swpl(*(uint32_t *)(rinfo->mmio_base+addr))
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#define OUTREG8(addr,val) (*((uint8_t *)(rinfo->mmio_base+addr)) = val)
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#define OUTREG16(addr,val) (*((uint16_t *)(rinfo->mmio_base+addr)) = swpw(val))
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#define OUTREG(addr,val) (*((uint32_t *)(rinfo->mmio_base+addr)) = swpl(val))
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#define INREG8(addr) *((uint8_t *)(rinfo->mmio_base + addr))
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#define INREG16(addr) swpw(*(uint16_t *)(rinfo->mmio_base + addr))
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#define INREG(addr) swpl(*(uint32_t *)(rinfo->mmio_base + addr))
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#define OUTREG8(addr,val) (*((uint8_t *)(rinfo->mmio_base + addr)) = val)
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#define OUTREG16(addr,val) (*((uint16_t *)(rinfo->mmio_base + addr)) = swpw(val))
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#define OUTREG(addr,val) (*((uint32_t *)(rinfo->mmio_base + addr)) = swpl(val))
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extern int32_t *tab_funcs_pci;
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#define BIOS_IN8(v) (* ((uint8_t *) rinfo->bios_seg_phys + v))
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@@ -575,24 +564,22 @@ extern void RADEONVIP_reset(struct radeonfb_info *rinfo);
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/* Accel functions */
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extern void RADEONWaitForFifoFunction(struct radeonfb_info *rinfo, int32_t entries);
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extern void RADEONEngineFlush(struct radeonfb_info *rinfo);
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extern void RADEONEngineReset(struct radeonfb_info *rinfo);
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extern void RADEONEngineRestore(struct radeonfb_info *rinfo);
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extern void RADEONEngineInit(struct radeonfb_info *rinfo);
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extern void RADEONWaitForIdleMMIO(struct radeonfb_info *rinfo);
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extern void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries);
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extern void radeon_engine_flush(struct radeonfb_info *rinfo);
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extern void radeon_engine_reset(struct radeonfb_info *rinfo);
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extern void radeon_engine_restore(struct radeonfb_info *rinfo);
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extern void radeon_engine_init(struct radeonfb_info *rinfo);
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extern void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo);
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#define RADEONWaitForFifo(rinfo, entries) \
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do { \
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if(rinfo->fifo_slots < entries) \
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RADEONWaitForFifoFunction(rinfo, entries); \
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rinfo->fifo_slots -= entries; \
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} while(0)
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#define radeon_engine_idle() radeon_wait_for_idle_mmio(rinfo)
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#define radeon_engine_flush(rinfo) RADEONEngineFlush(rinfo)
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#define radeonfb_engine_reset(rinfo) RADEONEngineReset(rinfo)
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#define radeonfb_engine_init(rinfo) RADEONEngineInit(rinfo)
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#define radeon_engine_idle() RADEONWaitForIdleMMIO(rinfo)
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#define radeon_wait_for_fifo(rinfo, entries) \
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do \
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{ \
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if (rinfo->fifo_slots < entries) \
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radeon_wait_for_fifo_function(rinfo, entries); \
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rinfo->fifo_slots -= entries; \
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} while (0)
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static inline int radeonfb_sync(struct fb_info *info)
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{
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