reverted to last released to make it work again
This commit is contained in:
Markus Fröschle
File diff suppressed because it is too large
Load Diff
@@ -24,6 +24,26 @@
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* Copyright 2013 M. Froeschle
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* Copyright 2013 M. Froeschle
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*/
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*/
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#define ACR_BA(x) ((x) & 0xffff0000)
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#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
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#define ACR_E(x) (((x) & 1) << 15)
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#define ACR_S(x) (((x) & 3) << 13)
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#define ACR_S_USERMODE 0
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#define ACR_S_SUPERVISOR_MODE 1
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#define ACR_S_ALL 2
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#define ACR_AMM(x) (((x) & 1) << 10)
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#define ACR_CM(x) (((x) & 3) << 5)
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#define ACR_CM_CACHEABLE_WT 0x0
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#define ACR_CM_CACHEABLE_CB 0x1
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#define ACR_CM_CACHE_INH_PRECISE 0x2
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#define ACR_CM_CACHE_INH_IMPRECISE 0x3
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#define ACR_SP(x) (((x) & 1) << 3)
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#define ACR_W(x) (((x) & 1) << 2)
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#include <stdint.h>
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#include <stdint.h>
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#include "bas_printf.h"
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#include "bas_printf.h"
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#include "bas_types.h"
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#include "bas_types.h"
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@@ -42,12 +62,12 @@
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#error "unknown machine!"
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#error "unknown machine!"
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#endif /* MACHINE_FIREBEE */
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#endif /* MACHINE_FIREBEE */
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#define DBG_MMU
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//#define DEBUG_MMU
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#ifdef DBG_MMU
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#ifdef DEBUG_MMU
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#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg);} while(0)
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#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
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#else
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#else
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#define dbg(format, arg...) do {;} while (0)
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#define dbg(format, arg...) do {;} while (0)
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#endif /* DBG_MMU */
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#endif /* DEBUG_MMU */
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/*
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/*
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* set ASID register
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* set ASID register
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@@ -59,11 +79,11 @@ inline uint32_t set_asid(uint32_t value)
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uint32_t ret = rt_asid;
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uint32_t ret = rt_asid;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],ASID\n\t"
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"movec %[value],ASID\n\t"
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: /* no output */
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: /* no output */
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: [value] "r" (value)
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: [value] "r" (value)
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:
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:
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);
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);
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rt_asid = value;
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rt_asid = value;
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@@ -81,11 +101,11 @@ inline uint32_t set_acr0(uint32_t value)
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uint32_t ret = rt_acr0;
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uint32_t ret = rt_acr0;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],ACR0\n\t"
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"movec %[value],ACR0\n\t"
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: /* not output */
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: /* not output */
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: [value] "r" (value)
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: [value] "r" (value)
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:
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:
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);
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);
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rt_acr0 = value;
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rt_acr0 = value;
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return ret;
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return ret;
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@@ -101,11 +121,11 @@ inline uint32_t set_acr1(uint32_t value)
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uint32_t ret = rt_acr1;
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uint32_t ret = rt_acr1;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],ACR1\n\t"
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"movec %[value],ACR1\n\t"
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: /* not output */
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: /* not output */
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: [value] "r" (value)
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: [value] "r" (value)
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:
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:
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);
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);
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rt_acr1 = value;
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rt_acr1 = value;
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return ret;
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return ret;
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@@ -122,11 +142,11 @@ inline uint32_t set_acr2(uint32_t value)
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uint32_t ret = rt_acr2;
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uint32_t ret = rt_acr2;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],ACR2\n\t"
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"movec %[value],ACR2\n\t"
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: /* not output */
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: /* not output */
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: [value] "r" (value)
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: [value] "r" (value)
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:
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:
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);
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);
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rt_acr2 = value;
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rt_acr2 = value;
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return ret;
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return ret;
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@@ -142,11 +162,11 @@ inline uint32_t set_acr3(uint32_t value)
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uint32_t ret = rt_acr3;
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uint32_t ret = rt_acr3;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],ACR3\n\t"
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"movec %[value],ACR3\n\t"
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: /* not output */
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: /* not output */
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: [value] "r" (value)
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: [value] "r" (value)
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:
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:
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);
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);
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rt_acr3 = value;
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rt_acr3 = value;
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return ret;
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return ret;
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@@ -158,417 +178,276 @@ inline uint32_t set_mmubar(uint32_t value)
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uint32_t ret = rt_mmubar;
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uint32_t ret = rt_mmubar;
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__asm__ __volatile__(
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__asm__ __volatile__(
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"movec %[value],MMUBAR\n\t"
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"movec %[value],MMUBAR\n\t"
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: /* no output */
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: /* no output */
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: [value] "r" (value)
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: [value] "r" (value)
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: /* no clobber */
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: /* no clobber */
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);
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);
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rt_mmubar = value;
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rt_mmubar = value;
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NOP();
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NOP();
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return ret;
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return ret;
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}
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}
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/*
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* TODO: this would be nicer in an include file
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*/
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extern uint8_t _SYS_SRAM[];
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#define SYS_SRAM_ADDRESS ((uint32_t) &_SYS_SRAM[0])
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extern uint8_t _SYS_SRAM_SIZE[];
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extern uint8_t _FASTRAM_END[];
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extern uint32_t _TOS;
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struct mmu_mapping
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{
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uint32_t phys;
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uint32_t virt;
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uint32_t length;
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uint32_t pagesize;
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struct map_flags flags;
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};
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static struct mmu_mapping locked_map[] =
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{
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{
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/* first Megabyte of physical memory */
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0x0, /* physical address */
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0x0, /* virtual address */
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0x100000, /* 1 MByte */
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MMU_PAGE_SIZE_1M,
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{ CACHE_COPYBACK, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* Falcon video memory. Needs special care */
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0x60d00000,
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0xd00000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_USER, SCA_PAGE_ID, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* TOS in RAM */
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(uint32_t) &_TOS,
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(uint32_t) &_TOS,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_COPYBACK, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE },
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},
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{
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/* Firebee I/O area */
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0xfff00000,
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0x00f00000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_USER, 0, ACCESS_READ | ACCESS_WRITE },
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},
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{
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/* BaS in RAM */
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SDRAM_START + SDRAM_SIZE - 0x00200000,
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SDRAM_START + SDRAM_SIZE - 0x00200000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* driver memory */
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SDRAM_START + SDRAM_SIZE - 0x00100000,
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SDRAM_START + SDRAM_SIZE - 0x00100000,
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0x100000,
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MMU_PAGE_SIZE_1M,
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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};
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static int num_locked_mmu_maps = sizeof(locked_map) / sizeof(struct mmu_mapping);
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static struct mmu_mapping memory_map[] =
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{
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/* map OS system vectors supervisor-protected */
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{
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0,
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0,
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0x800,
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MMU_PAGE_SIZE_1K,
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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0x800,
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0x800,
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0x800,
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MMU_PAGE_SIZE_1K,
|
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
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},
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{
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/* when the first 4k are filled with 1k pages, we can switch to 8k pages */
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0x1000,
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0x1000,
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0xff000,
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MMU_PAGE_SIZE_8K,
|
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
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},
|
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{
|
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/* arrived at a 1Meg border, we can switch to 1Meg pages */
|
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0x100000,
|
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0x100000,
|
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0xc00000,
|
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MMU_PAGE_SIZE_1M,
|
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
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},
|
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/* Falcon video ram left out intentionally here (see above) */
|
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{
|
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/* ROM */
|
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0xe00000,
|
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0xe00000,
|
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0x100000,
|
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MMU_PAGE_SIZE_1M,
|
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE },
|
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},
|
|
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{
|
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/* FASTRAM */
|
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0x1000000,
|
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0x1000000,
|
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(uint32_t) _FASTRAM_END - 0x1000000,
|
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MMU_PAGE_SIZE_1M,
|
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{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
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},
|
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{
|
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/* MBAR */
|
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MBAR_ADDRESS,
|
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MBAR_ADDRESS,
|
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0x100000,
|
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MMU_PAGE_SIZE_1M,
|
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
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},
|
|
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{
|
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/* RAMBAR0 */
|
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RAMBAR0_ADDRESS,
|
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RAMBAR0_ADDRESS,
|
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(uint32_t) _RAMBAR0_SIZE,
|
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MMU_PAGE_SIZE_1K,
|
|
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
|
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},
|
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{
|
|
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/* RAMBAR1 */
|
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RAMBAR1_ADDRESS,
|
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RAMBAR1_ADDRESS,
|
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(uint32_t) _RAMBAR1_SIZE,
|
|
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MMU_PAGE_SIZE_1K,
|
|
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
|
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},
|
|
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{
|
|
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/* SYSTEM SRAM */
|
|
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SYS_SRAM_ADDRESS,
|
|
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SYS_SRAM_ADDRESS,
|
|
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(uint32_t) _SYS_SRAM_SIZE,
|
|
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MMU_PAGE_SIZE_8K,
|
|
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{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
|
|
||||||
},
|
|
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{
|
|
||||||
/* Firebee FPGA registers */
|
|
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(uint32_t) 0xf0000000,
|
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(uint32_t) 0xf0000000,
|
|
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(uint32_t) 0x08000000,
|
|
||||||
MMU_PAGE_SIZE_1M,
|
|
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{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
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},
|
|
||||||
{
|
|
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/* Falcon I/O registers */
|
|
||||||
(uint32_t) 0xfff00000,
|
|
||||||
(uint32_t) 0xfff00000,
|
|
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(uint32_t) 0x100000,
|
|
||||||
MMU_PAGE_SIZE_1M,
|
|
||||||
{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* the same, but different virtual address */
|
|
||||||
(uint32_t) 0x00f00000,
|
|
||||||
(uint32_t) 0xfff00000,
|
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||||||
(uint32_t) 0x100000,
|
|
||||||
MMU_PAGE_SIZE_1M,
|
|
||||||
{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* PCI memory */
|
|
||||||
(uint32_t) PCI_MEMORY_OFFSET,
|
|
||||||
(uint32_t) PCI_MEMORY_OFFSET,
|
|
||||||
(uint32_t) PCI_MEMORY_SIZE,
|
|
||||||
MMU_PAGE_SIZE_1M,
|
|
||||||
{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* PCI I/O */
|
|
||||||
(uint32_t) PCI_IO_OFFSET,
|
|
||||||
(uint32_t) PCI_IO_OFFSET,
|
|
||||||
(uint32_t) PCI_IO_SIZE,
|
|
||||||
MMU_PAGE_SIZE_1M,
|
|
||||||
{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
static int num_mmu_maps = sizeof(memory_map) / sizeof(struct mmu_mapping);
|
|
||||||
|
|
||||||
static struct mmu_mapping *lookup_mapping(uint32_t virt)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* dumb, for now
|
|
||||||
*/
|
|
||||||
|
|
||||||
for (i = 0; i < num_mmu_maps; i++)
|
|
||||||
{
|
|
||||||
if (virt >= memory_map[i].virt && virt <= memory_map[i].virt + memory_map[i].length - 1)
|
|
||||||
return &memory_map[i];
|
|
||||||
}
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
void mmu_init(void)
|
void mmu_init(void)
|
||||||
{
|
{
|
||||||
extern uint8_t _MMUBAR[];
|
extern uint8_t _MMUBAR[];
|
||||||
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
|
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
|
||||||
int i;
|
extern uint8_t _TOS[];
|
||||||
|
uint32_t TOS = (uint32_t) &_TOS[0];
|
||||||
|
|
||||||
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
|
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
|
||||||
|
|
||||||
/* set data access attributes in ACR0 and ACR1 */
|
/* set data access attributes in ACR0 and ACR1 */
|
||||||
|
set_acr0(ACR_W(0) | /* read and write accesses permitted */
|
||||||
set_acr0(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */
|
ACR_SP(0) | /* supervisor and user mode access permitted */
|
||||||
ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */
|
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
|
||||||
ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* cache inhibit, precise */
|
ACR_AMM(0) | /* control region > 16 MB */
|
||||||
ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */
|
ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */
|
||||||
ACR_S(ACR_S_ALL) | /* memory visible in user and supervisor mode */
|
ACR_E(1) | /* enable ACR */
|
||||||
ACR_E(1) | /* enable ACR */
|
|
||||||
#if defined(MACHINE_FIREBEE)
|
#if defined(MACHINE_FIREBEE)
|
||||||
ACR_ADMSK(0x3f) | /* cover 1 GB area from 0xc0000000 to 0xffffffff */
|
ACR_ADMSK(0x3f) | /* cover 1GB area from 0xc0000000 to 0xffffffff */
|
||||||
ACR_BA(0xc0000000)); /* equals area from 3 to 4 GB */
|
ACR_BA(0xc0000000)); /* (equals area from 3 to 4 GB */
|
||||||
#elif defined(MACHINE_M5484LITE)
|
#elif defined(MACHINE_M5484LITE)
|
||||||
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
|
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
|
||||||
ACR_BA(0x80000000));
|
ACR_BA(0x80000000));
|
||||||
#elif defined(MACHINE_M54455)
|
#elif defined(MACHINE_M54455)
|
||||||
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
|
ACR_ADMSK(0x7f) |
|
||||||
ACR_BA(0x80000000));
|
ACR_BA(0x80000000)); /* FIXME: not determined yet */
|
||||||
#else
|
#else
|
||||||
#error unknown machine
|
#error unknown machine!
|
||||||
#endif /* MACHINE_FIREBEE */
|
#endif /* MACHINE_FIREBEE */
|
||||||
|
|
||||||
set_acr1(ACR_WRITE_PROTECT(0) | /* read and write accesses permitted */
|
// set_acr1(0x601fc000);
|
||||||
ACR_SUPERVISOR_PROTECT(0) | /* supervisor and user mode access permitted */
|
set_acr1(ACR_W(0) |
|
||||||
|
ACR_SP(0) |
|
||||||
|
ACR_CM(0) |
|
||||||
#if defined(MACHINE_FIREBEE)
|
#if defined(MACHINE_FIREBEE)
|
||||||
ACR_CACHE_MODE(CACHE_WRITETHROUGH) | /* video RAM on the Firebee */
|
ACR_CM(ACR_CM_CACHEABLE_WT) | /* video RAM on the Firebee */
|
||||||
#elif defined(MACHINE_M5484LITE)
|
#elif defined(MACHINE_M5484LITE)
|
||||||
ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* Compact Flash on the M548xLITE */
|
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */
|
||||||
#elif defined(MACHINE_M54455)
|
#elif defined(MACHINE_M54455)
|
||||||
ACR_CACHE_MODE(CACHE_NOCACHE_PRECISE) | /* FIXME: not clear yet */
|
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* FIXME: not determined yet */
|
||||||
#else
|
#else
|
||||||
#error unknown machine
|
#error unknown machine!
|
||||||
#endif
|
#endif /* MACHINE_FIREBEE */
|
||||||
ACR_ADDRESS_MASK_MODE(0) | /* region > 16 MByte */
|
ACR_AMM(0) |
|
||||||
ACR_S(ACR_S_ALL) | /* memory visible from user and supervisor mode */
|
ACR_S(ACR_S_ALL) |
|
||||||
ACR_E(1) | /* enable ACR */
|
ACR_E(1) |
|
||||||
ACR_ADMSK(0x1f) |
|
ACR_ADMSK(0x1f) |
|
||||||
ACR_BA(0x60000000));
|
ACR_BA(0x60000000));
|
||||||
|
|
||||||
|
/* set instruction access attributes in ACR2 and ACR3 */
|
||||||
|
|
||||||
/*
|
//set_acr2(0xe007c400);
|
||||||
* set instruction access attributes in ACR2 and ACR3.
|
set_acr2(ACR_W(0) |
|
||||||
*/
|
ACR_SP(0) |
|
||||||
|
ACR_CM(0) |
|
||||||
set_acr2(ACR_WRITE_PROTECT(0) |
|
ACR_CM(ACR_CM_CACHEABLE_WT) |
|
||||||
ACR_SUPERVISOR_PROTECT(0) |
|
ACR_AMM(1) |
|
||||||
ACR_CACHE_MODE(CACHE_WRITETHROUGH) |
|
|
||||||
ACR_ADDRESS_MASK_MODE(1) |
|
|
||||||
ACR_S(ACR_S_ALL) |
|
ACR_S(ACR_S_ALL) |
|
||||||
ACR_E(1) |
|
ACR_E(1) |
|
||||||
ACR_ADMSK(0x07) |
|
ACR_ADMSK(0x7) |
|
||||||
ACR_BA(0xe0000000));
|
ACR_BA(0xe0000000));
|
||||||
|
|
||||||
set_acr3(0); /* disable ACR3 */
|
/* disable ACR3 */
|
||||||
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
|
set_acr3(0x0);
|
||||||
|
|
||||||
|
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
|
||||||
|
|
||||||
/* clear all MMU TLB entries */
|
/* clear all MMU TLB entries */
|
||||||
MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
|
||||||
|
|
||||||
/* map locked TLB entries */
|
/* create locked TLB entries */
|
||||||
for (i = 0; i < num_locked_mmu_maps; i++)
|
|
||||||
{
|
|
||||||
mmu_map_page(locked_map[i].virt, locked_map[i].phys, locked_map->pagesize, locked_map->flags);
|
|
||||||
|
|
||||||
if (locked_map[i].flags.page_id == SCA_PAGE_ID)
|
/*
|
||||||
{
|
* 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical
|
||||||
video_tlb = 0x2000;
|
*/
|
||||||
video_sbt = 0x0;
|
MCF_MMU_MMUTR = 0x0 | /* virtual address */
|
||||||
}
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
}
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
MCF_MMU_MMUDR = 0x0 | /* physical address */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x1) | /* cacheable, copyback */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
|
||||||
|
* mapped to physical address 0x60d0'0000 (FPGA video memory)
|
||||||
|
* video RAM: read write execute normal write true
|
||||||
|
*/
|
||||||
|
|
||||||
|
MCF_MMU_MMUTR = 0x00d00000 | /* virtual address */
|
||||||
|
#if defined(MACHINE_FIREBEE)
|
||||||
|
MCF_MMU_MMUTR_ID(SCA_PAGE_ID) |
|
||||||
|
#endif /* MACHINE_FIREBEE */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
#if defined(MACHINE_FIREBEE)
|
||||||
|
/* map FPGA video memory for FireBee only */
|
||||||
|
MCF_MMU_MMUDR = 0x60d00000 | /* physical address */
|
||||||
|
#elif defined(MACHINE_M5484LITE)
|
||||||
|
MCF_MMU_MMUDR = 0x00d00000 | /* physical address */
|
||||||
|
#elif defined(MACHINE_M54455)
|
||||||
|
MCF_MMU_MMUDR = 0x60d00000 | /* FIXME: not determined yet */
|
||||||
|
#else
|
||||||
|
#error unknown machine!
|
||||||
|
#endif /* MACHINE_FIREBEE */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x0) | /* cachable writethrough */
|
||||||
|
/* caveat: can't be supervisor protected since TOS puts the application stack there! */
|
||||||
|
//MCF_MMU_MMUDR_SP | /* supervisor protect */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
|
||||||
|
#if defined(MACHINE_FIREBEE)
|
||||||
|
video_tlb = 0x2000; /* set page as video page */
|
||||||
|
video_sbt = 0x0; /* clear time */
|
||||||
|
#endif /* MACHINE_FIREBEE */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Make the TOS (in SDRAM) read-only
|
||||||
|
* This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
|
||||||
|
*/
|
||||||
|
MCF_MMU_MMUTR = TOS | /* virtual address */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
MCF_MMU_MMUDR = TOS | /* physical address */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x1) | /* cachable copyback */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
//MCF_MMU_MMUDR_W | /* write access enable (FIXME: for now) */
|
||||||
|
MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
|
||||||
|
#if MACHINE_FIREBEE
|
||||||
|
/*
|
||||||
|
* Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
|
||||||
|
* area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
|
||||||
|
*/
|
||||||
|
|
||||||
|
MCF_MMU_MMUTR = 0x00f00000 | /* virtual address */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
MCF_MMU_MMUDR = 0xfff00000 | /* physical address */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x2) | /* nocache precise */
|
||||||
|
MCF_MMU_MMUDR_SP | /* supervisor protect */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
#endif /* MACHINE_FIREBEE */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
|
||||||
|
* virtual address. This is also used when BaS is in RAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) | /* virtual address */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) | /* physical address */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x0) | /* cacheable writethrough */
|
||||||
|
MCF_MMU_MMUDR_SP | /* supervisor protect */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
|
||||||
|
* virtual address. Used uncached for drivers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* virtual address */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) | /* physical address */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x2) | /* nocache precise */
|
||||||
|
MCF_MMU_MMUDR_SP | /* supervisor protect */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
//MCF_MMU_MMUDR_X | /* execute access enable */
|
||||||
|
MCF_MMU_MMUDR_LK; /* lock entry */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
void mmutr_miss(uint32_t address)
|
||||||
* handle an access error
|
|
||||||
* upper level routine called from access_exception inside exceptions.S
|
|
||||||
*/
|
|
||||||
bool access_exception(uint32_t pc, uint32_t format_status)
|
|
||||||
{
|
{
|
||||||
int fault_status;
|
dbg("MMU TLB MISS at 0x%08x\r\n", address);
|
||||||
uint32_t fault_address;
|
flush_and_invalidate_caches();
|
||||||
uint32_t mmu_status;
|
|
||||||
|
|
||||||
/*
|
switch (address)
|
||||||
* extract fault status from format_status exception stack field
|
|
||||||
*/
|
|
||||||
fault_status = format_status & 0xc030000;
|
|
||||||
mmu_status = MCF_MMU_MMUSR;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* determine if access fault was caused by a TLB miss
|
|
||||||
*/
|
|
||||||
switch (fault_status)
|
|
||||||
{
|
{
|
||||||
case 0x4010000: /* TLB miss on opword of instruction fetch */
|
case keyctl:
|
||||||
case 0x4020000: /* TLB miss on extension word of instruction fetch */
|
case keybd:
|
||||||
//fault_address = pc;
|
/* do something to emulate the IKBD access */
|
||||||
//break;
|
dbg("IKBD access\r\n");
|
||||||
case 0x8020000: /* TLB miss on data write */
|
break;
|
||||||
case 0xc020000: /* TLB miss on data read or read-modify-write */
|
|
||||||
fault_address = MCF_MMU_MMUAR;
|
case midictl:
|
||||||
/*
|
case midi:
|
||||||
* the following line must stay commented or we risk a double fault (debugging
|
/* do something to emulate MIDI access */
|
||||||
* output requiring itself a page mapping):
|
dbg("MIDI ACIA access\r\n");
|
||||||
*/
|
|
||||||
// dbg("access fault - TLB miss at %p. Fault status = 0x0%x\r\n", pc, fault_status);
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
return false;
|
/* add missed page to TLB */
|
||||||
|
MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
|
||||||
|
MCF_MMU_MMUTR_SG | /* shared global */
|
||||||
|
MCF_MMU_MMUTR_V; /* valid */
|
||||||
|
|
||||||
|
MCF_MMU_MMUDR = (address & 0xfff00000) | /* physical aligned to 1M */
|
||||||
|
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
|
||||||
|
MCF_MMU_MMUDR_CM(0x1) | /* cacheable copyback */
|
||||||
|
MCF_MMU_MMUDR_R | /* read access enable */
|
||||||
|
MCF_MMU_MMUDR_W | /* write access enable */
|
||||||
|
MCF_MMU_MMUDR_X; /* execute access enable */
|
||||||
|
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
|
|
||||||
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
||||||
|
MCF_MMU_MMUOR_ACC | /* access TLB */
|
||||||
|
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
if (mmu_status & MCF_MMU_MMUSR_HIT) /* did the last fault hit in TLB? */
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* if yes, then we already mapped that page during a previous turn and this is in fact a bus error
|
|
||||||
*/
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
struct mmu_mapping *map;
|
|
||||||
|
|
||||||
|
|
||||||
if ((map = lookup_mapping(fault_address)) != NULL)
|
|
||||||
{
|
|
||||||
uint32_t mask;
|
|
||||||
|
|
||||||
switch (map->pagesize)
|
|
||||||
{
|
|
||||||
case MMU_PAGE_SIZE_1M:
|
|
||||||
mask = ~(0x100000 - 1);
|
|
||||||
break;
|
|
||||||
case MMU_PAGE_SIZE_4K:
|
|
||||||
mask = ~(0x1000 - 1);
|
|
||||||
break;
|
|
||||||
case MMU_PAGE_SIZE_8K:
|
|
||||||
mask = ~(0x2000 - 1);
|
|
||||||
break;
|
|
||||||
case MMU_PAGE_SIZE_1K:
|
|
||||||
mask = ~(0x400 - 1);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
mmu_map_page(fault_address & mask, fault_address & mask, map->pagesize, map->flags);
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags)
|
|
||||||
{
|
|
||||||
|
|
||||||
/*
|
|
||||||
* add page to TLB
|
|
||||||
*/
|
|
||||||
MCF_MMU_MMUTR = virt | /* virtual address */
|
|
||||||
MCF_MMU_MMUTR_ID(flags.page_id) |
|
|
||||||
MCF_MMU_MMUTR_SG | /* shared global */
|
|
||||||
MCF_MMU_MMUTR_V; /* valid */
|
|
||||||
|
|
||||||
MCF_MMU_MMUDR = phys | /* physical address */
|
|
||||||
MCF_MMU_MMUDR_SZ(map_size) | /* 1 MB page size */
|
|
||||||
MCF_MMU_MMUDR_CM(flags.cache_mode) |
|
|
||||||
(flags.access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
|
|
||||||
(flags.access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
|
|
||||||
(flags.access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0); /* execute access enable */
|
|
||||||
|
|
||||||
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
|
|
||||||
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
|
||||||
|
|
||||||
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
|
|
||||||
MCF_MMU_MMUOR_ACC | /* access TLB */
|
|
||||||
MCF_MMU_MMUOR_UAA; /* update allocation address field */
|
|
||||||
dbg("mapped virt=%p to phys=%p\r\n", virt, phys);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user