enabled MCDMA for fec
This commit is contained in:
54
dma/dma.c
54
dma/dma.c
@@ -48,12 +48,53 @@ static char used_reqs[32];
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static struct dma_channel dma_channel[NCHANNELS] =
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static struct dma_channel dma_channel[NCHANNELS] =
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{
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{
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{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
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{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
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{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
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{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
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{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
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{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
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{-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL},
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{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
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};
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};
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/********************************************************************/
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/*
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* Enable all DMA interrupts
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*
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* Parameters:
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* pri Interrupt Priority
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* lvl Interrupt Level
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*/
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void dma_irq_enable(uint8_t lvl, uint8_t pri)
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{
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/* Setup the DMA ICR (#48) */
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MCF_INTC_ICR48 = 0
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| MCF_INTC_ICR_IP(pri)
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| MCF_INTC_ICR_IL(lvl);
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/* Unmask all task interrupts */
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MCF_DMA_DIMR = 0;
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/* Clear the interrupt pending register */
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MCF_DMA_DIPR = 0;
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/* Unmask the DMA interrupt in the interrupt controller */
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MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
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}
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/********************************************************************/
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/*
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* Disable all DMA interrupts
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*/
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void dma_irq_disable(void)
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{
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/* Mask all task interrupts */
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MCF_DMA_DIMR = (uint32_t) ~0;
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/* Clear any pending task interrupts */
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MCF_DMA_DIPR = (uint32_t) ~0;
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/* Mask the DMA interrupt in the interrupt controller */
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MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
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}
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int dma_set_initiator(int initiator)
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int dma_set_initiator(int initiator)
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{
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{
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switch (initiator)
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switch (initiator)
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@@ -365,6 +406,7 @@ void dma_clear_channel(int channel)
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dma_channel[channel].handler = NULL;
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dma_channel[channel].handler = NULL;
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}
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}
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}
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}
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/*
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/*
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* Return the channel being initiated by the given requestor
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* Return the channel being initiated by the given requestor
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*
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*
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@@ -379,7 +421,7 @@ int dma_get_channel(int requestor)
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{
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{
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uint32_t i;
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uint32_t i;
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for (i=0; i<NCHANNELS; ++i)
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for (i = 0; i < NCHANNELS; ++i)
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{
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{
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if (dma_channel[i].req == requestor)
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if (dma_channel[i].req == requestor)
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return i;
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return i;
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@@ -398,7 +440,7 @@ void dma_free_channel(int requestor)
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{
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{
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uint32_t i;
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uint32_t i;
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for (i=0; i<NCHANNELS; ++i)
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for (i=0; i < NCHANNELS; ++i)
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{
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{
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if (dma_channel[i].req == requestor)
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if (dma_channel[i].req == requestor)
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{
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{
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@@ -40,6 +40,9 @@ extern void dma_clear_channel(int channel);
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extern uint32_t dma_get_initiator(int requestor);
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extern uint32_t dma_get_initiator(int requestor);
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extern int dma_set_initiator(int initiator);
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extern int dma_set_initiator(int initiator);
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extern void dma_free_initiator(int initiator);
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extern void dma_free_initiator(int initiator);
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extern void dma_irq_enable(uint8_t lvl, uint8_t pri);
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extern void dma_irq_disable(void);
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extern int dma_interrupt_handler(void *arg1, void *arg2);
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#endif /* _DMA_H_ */
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#endif /* _DMA_H_ */
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18
sys/BaS.c
18
sys/BaS.c
@@ -268,6 +268,18 @@ void network_init(void)
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return;
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return;
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}
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}
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/*
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* Register the DMA interrupt handler
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*/
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handler = dma_interrupt_handler;
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vector = 112;
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if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL,NULL))
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{
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xprintf("Error: Unable to register handler\n");
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return;
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}
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nif_init(&nif1);
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nif_init(&nif1);
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nif1.mtu = ETH_MTU;
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nif1.mtu = ETH_MTU;
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nif1.send = fec0_send;
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nif1.send = fec0_send;
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@@ -282,7 +294,9 @@ void network_init(void)
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ip_init(&ip_info, myip, gateway, netmask);
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ip_init(&ip_info, myip, gateway, netmask);
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nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
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nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
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bootp_request(&nif1, 0);
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dma_irq_enable(6, 0);
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//bootp_request(&nif1, 0);
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}
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}
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void BaS(void)
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void BaS(void)
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@@ -422,7 +436,7 @@ void BaS(void)
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enable_coldfire_interrupts();
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enable_coldfire_interrupts();
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//set_ipl(0);
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//set_ipl(0);
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//network_init();
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network_init();
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xprintf("call EmuTOS\r\n");
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xprintf("call EmuTOS\r\n");
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ROM_HEADER* os_header = (ROM_HEADER*)TOS;
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ROM_HEADER* os_header = (ROM_HEADER*)TOS;
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@@ -307,6 +307,7 @@ init_vec_loop:
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move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
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move.l (sp)+,a2 // Restore registers
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move.l (sp)+,a2 // Restore registers
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rts
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rts
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@@ -205,6 +205,7 @@ bool isr_execute_handler(int vector)
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if ((isrtab[index].vector == vector) &&
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if ((isrtab[index].vector == vector) &&
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(isrtab[index].type == ISR_DBUG_ISR))
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(isrtab[index].type == ISR_DBUG_ISR))
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{
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{
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xprintf("calling BaS isr handler at %p\r\n", isrtab[index].handler);
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if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
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if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
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{
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{
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retval = true;
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retval = true;
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@@ -221,6 +222,7 @@ bool isr_execute_handler(int vector)
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if ((isrtab[index].vector == vector) &&
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if ((isrtab[index].vector == vector) &&
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(isrtab[index].type == ISR_USER_ISR))
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(isrtab[index].type == ISR_USER_ISR))
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{
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{
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xprintf("calling USR isr handler at %p\r\n", isrtab[index].handler);
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if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
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if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
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{
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{
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retval = true;
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retval = true;
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