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fixed formatting

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This commit is contained in:
Markus Fröschle
2014-08-04 20:50:39 +00:00
parent b40ddd37fc
commit 4c5b6d02e9
1 changed files with 374 additions and 374 deletions
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742
vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
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@@ -47,410 +47,410 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
entity VIDEO_CTRL is entity VIDEO_CTRL is
port( port(
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
FB_CSn : in std_logic_vector(2 downto 1); FB_CSn : in std_logic_vector(2 downto 1);
FB_WRn : in std_logic; FB_WRn : in std_logic;
FB_OEn : in std_logic; FB_OEn : in std_logic;
FB_SIZE : in std_logic_vector(1 downto 0); FB_SIZE : in std_logic_vector(1 downto 0);
FB_ADR : in std_logic_vector(31 downto 0); FB_ADR : in std_logic_vector(31 downto 0);
CLK33M : in std_logic; CLK33M : in std_logic;
CLK25M : in std_logic; CLK25M : in std_logic;
BLITTER_RUN : in std_logic; BLITTER_RUN : in std_logic;
CLK_VIDEO : in std_logic; CLK_VIDEO : in std_logic;
VR_D : in std_logic_vector(8 downto 0); VR_D : in std_logic_vector(8 downto 0);
VR_BUSY : in std_logic; VR_BUSY : in std_logic;
COLOR8 : out std_logic; COLOR8 : out std_logic;
FBEE_CLUT_RD : out std_logic; FBEE_CLUT_RD : out std_logic;
COLOR1 : out std_logic; COLOR1 : out std_logic;
FALCON_CLUT_RDH : out std_logic; FALCON_CLUT_RDH : out std_logic;
FALCON_CLUT_RDL : out std_logic; FALCON_CLUT_RDL : out std_logic;
FALCON_CLUT_WR : out std_logic_vector(3 downto 0); FALCON_CLUT_WR : out std_logic_vector(3 downto 0);
CLUT_ST_RD : out std_logic; CLUT_ST_RD : out std_logic;
CLUT_ST_WR : out std_logic_vector(1 downto 0); CLUT_ST_WR : out std_logic_vector(1 downto 0);
CLUT_MUX_ADR : out std_logic_vector(3 downto 0); CLUT_MUX_ADR : out std_logic_vector(3 downto 0);
HSYNC : out std_logic; HSYNC : out std_logic;
VSYNC : out std_logic; VSYNC : out std_logic;
BLANKn : out std_logic; BLANKn : out std_logic;
SYNCn : out std_logic; SYNCn : out std_logic;
PD_VGAn : out std_logic; PD_VGAn : out std_logic;
FIFO_RDE : out std_logic; FIFO_RDE : out std_logic;
COLOR2 : out std_logic; COLOR2 : out std_logic;
COLOR4 : out std_logic; COLOR4 : out std_logic;
CLK_PIXEL : out std_logic; CLK_PIXEL : out std_logic;
CLUT_OFF : out std_logic_vector(3 downto 0); CLUT_OFF : out std_logic_vector(3 downto 0);
BLITTER_ON : out std_logic; BLITTER_ON : out std_logic;
VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); VIDEO_RAM_CTR : out std_logic_vector(15 downto 0);
VIDEO_MOD_TA : out std_logic; VIDEO_MOD_TA : out std_logic;
CCR : out std_logic_vector(23 downto 0); CCR : out std_logic_vector(23 downto 0);
CCSEL : out std_logic_vector(2 downto 0); CCSEL : out std_logic_vector(2 downto 0);
FBEE_CLUT_WR : out std_logic_vector(3 downto 0); FBEE_CLUT_WR : out std_logic_vector(3 downto 0);
INTER_ZEI : out std_logic; INTER_ZEI : out std_logic;
DOP_FIFO_CLR : out std_logic; DOP_FIFO_CLR : out std_logic;
VIDEO_RECONFIG : out std_logic; VIDEO_RECONFIG : out std_logic;
VR_WR : out std_logic; VR_WR : out std_logic;
VR_RD : out std_logic; VR_RD : out std_logic;
FIFO_CLR : out std_logic; FIFO_CLR : out std_logic;
DATA_IN : in std_logic_vector(31 downto 0); DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0);
DATA_EN_H : out std_logic; DATA_EN_H : out std_logic;
DATA_EN_L : out std_logic DATA_EN_L : out std_logic
); );
end entity VIDEO_CTRL; end entity VIDEO_CTRL;
architecture BEHAVIOUR of VIDEO_CTRL is architecture BEHAVIOUR of VIDEO_CTRL is
signal CLK17M : std_logic; signal CLK17M : std_logic;
signal CLK13M : std_logic; signal CLK13M : std_logic;
signal FBEE_CLUT_CS : std_logic; signal FBEE_CLUT_CS : std_logic;
signal FBEE_CLUT : std_logic; signal FBEE_CLUT : std_logic;
signal VIDEO_PLL_CONFIG_CS : std_logic; signal VIDEO_PLL_CONFIG_CS : std_logic;
signal VR_WR_I : std_logic; signal VR_WR_I : std_logic;
signal VR_DOUT : std_logic_vector(8 downto 0); signal VR_DOUT : std_logic_vector(8 downto 0);
signal VR_FRQ : std_logic_vector(7 downto 0); signal VR_FRQ : std_logic_vector(7 downto 0);
signal VIDEO_PLL_RECONFIG_CS : std_logic; signal VIDEO_PLL_RECONFIG_CS : std_logic;
signal VIDEO_RECONFIG_I : std_logic; signal VIDEO_RECONFIG_I : std_logic;
signal FALCON_CLUT_CS : std_logic; signal FALCON_CLUT_CS : std_logic;
signal FALCON_CLUT : std_logic; signal FALCON_CLUT : std_logic;
signal ST_CLUT_CS : std_logic; signal ST_CLUT_CS : std_logic;
signal ST_CLUT : std_logic; signal ST_CLUT : std_logic;
signal FB_B : std_logic_vector(3 downto 0); signal FB_B : std_logic_vector(3 downto 0);
signal FB_16B : std_logic_vector(1 downto 0); signal FB_16B : std_logic_vector(1 downto 0);
signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); signal ST_SHIFT_MODE : std_logic_vector(1 downto 0);
signal ST_SHIFT_MODE_CS : std_logic; signal ST_SHIFT_MODE_CS : std_logic;
signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0);
signal FALCON_SHIFT_MODE_CS : std_logic; signal FALCON_SHIFT_MODE_CS : std_logic;
signal CLUT_MUX_AV_1 : std_logic_vector(3 downto 0); signal CLUT_MUX_AV_1 : std_logic_vector(3 downto 0);
signal CLUT_MUX_AV_0 : std_logic_vector(3 downto 0); signal CLUT_MUX_AV_0 : std_logic_vector(3 downto 0);
signal FBEE_VCTR_CS : std_logic; signal FBEE_VCTR_CS : std_logic;
signal FBEE_VCTR : std_logic_vector(31 downto 0); signal FBEE_VCTR : std_logic_vector(31 downto 0);
signal CCR_CS : std_logic; signal CCR_CS : std_logic;
signal CCR_I : std_logic_vector(23 downto 0); signal CCR_I : std_logic_vector(23 downto 0);
signal FBEE_VIDEO_ON : std_logic; signal FBEE_VIDEO_ON : std_logic;
signal SYS_CTR : std_logic_vector(6 downto 0); signal SYS_CTR : std_logic_vector(6 downto 0);
signal SYS_CTR_CS : std_logic; signal SYS_CTR_CS : std_logic;
signal VDL_LOF : std_logic_vector(15 downto 0); signal VDL_LOF : std_logic_vector(15 downto 0);
signal VDL_LOF_CS : std_logic; signal VDL_LOF_CS : std_logic;
signal VDL_LWD : std_logic_vector(15 downto 0); signal VDL_LWD : std_logic_vector(15 downto 0);
signal VDL_LWD_CS : std_logic; signal VDL_LWD_CS : std_logic;
-- Miscellaneous control registers: -- Miscellaneous control registers:
signal CLUT_TA : std_logic; -- Requires one wait state. signal CLUT_TA : std_logic; -- Requires one wait state.
signal HSYNC_I : std_logic_vector(7 downto 0); signal HSYNC_I : std_logic_vector(7 downto 0);
signal HSY_LEN : std_logic_vector(7 downto 0); -- Length of a HSYNC pulse in CLK_PIXEL cycles. signal HSY_LEN : std_logic_vector(7 downto 0); -- Length of a HSYNC pulse in CLK_PIXEL cycles.
signal HSYNC_START : std_logic; signal HSYNC_START : std_logic;
signal LAST : std_logic; -- Last pixel of a line indicator. signal LAST : std_logic; -- Last pixel of a line indicator.
signal VSYNC_START : std_logic; signal VSYNC_START : std_logic;
signal VSYNC_I : std_logic_vector(2 downto 0); signal VSYNC_I : std_logic_vector(2 downto 0);
signal BLANK_In : std_logic; signal BLANK_In : std_logic;
signal DISP_ON : std_logic; signal DISP_ON : std_logic;
signal DPO_ZL : std_logic; signal DPO_ZL : std_logic;
signal DPO_ON : std_logic; signal DPO_ON : std_logic;
signal DPO_OFF : std_logic; signal DPO_OFF : std_logic;
signal VDTRON : std_logic; signal VDTRON : std_logic;
signal VDO_ZL : std_logic; signal VDO_ZL : std_logic;
signal VDO_ON : std_logic; signal VDO_ON : std_logic;
signal VDO_OFF : std_logic; signal VDO_OFF : std_logic;
signal VHCNT : std_logic_vector(11 downto 0); signal VHCNT : std_logic_vector(11 downto 0);
signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0); signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0);
signal VVCNT : std_logic_vector(10 downto 0); signal VVCNT : std_logic_vector(10 downto 0);
signal VERZ_2 : std_logic_vector(9 downto 0); signal VERZ_2 : std_logic_vector(9 downto 0);
signal VERZ_1 : std_logic_vector(9 downto 0); signal VERZ_1 : std_logic_vector(9 downto 0);
signal VERZ_0 : std_logic_vector(9 downto 0); signal VERZ_0 : std_logic_vector(9 downto 0);
signal RAND : std_logic_vector(6 downto 0); signal RAND : std_logic_vector(6 downto 0);
signal RAND_ON : std_logic; signal RAND_ON : std_logic;
signal START_ZEILE : std_logic; signal START_ZEILE : std_logic;
signal SYNC_PIX : std_logic; signal SYNC_PIX : std_logic;
signal SYNC_PIX1 : std_logic; signal SYNC_PIX1 : std_logic;
signal SYNC_PIX2 : std_logic; signal SYNC_PIX2 : std_logic;
-- Legacy ATARI resolutions: -- Legacy ATARI resolutions:
signal ATARI_SYNC : std_logic; signal ATARI_SYNC : std_logic;
signal ATARI_HH : std_logic_vector(31 downto 0); -- Horizontal timing 640x480. signal ATARI_HH : std_logic_vector(31 downto 0); -- Horizontal timing 640x480.
signal ATARI_HH_CS : std_logic; signal ATARI_HH_CS : std_logic;
signal ATARI_VH : std_logic_vector(31 downto 0); -- Vertical timing 640x480. signal ATARI_VH : std_logic_vector(31 downto 0); -- Vertical timing 640x480.
signal ATARI_VH_CS : std_logic; signal ATARI_VH_CS : std_logic;
signal ATARI_HL : std_logic_vector(31 downto 0); -- Horizontal timing 320x240. signal ATARI_HL : std_logic_vector(31 downto 0); -- Horizontal timing 320x240.
signal ATARI_HL_CS : std_logic; signal ATARI_HL_CS : std_logic;
signal ATARI_VL : std_logic_vector(31 downto 0); -- Vertical timing 320x240. signal ATARI_VL : std_logic_vector(31 downto 0); -- Vertical timing 320x240.
signal ATARI_VL_CS : std_logic; signal ATARI_VL_CS : std_logic;
-- Horizontal stuff: -- Horizontal stuff:
signal BORDER_LEFT : std_logic_vector(11 downto 0); signal BORDER_LEFT : std_logic_vector(11 downto 0);
signal HDIS_START : std_logic_vector(11 downto 0); signal HDIS_START : std_logic_vector(11 downto 0);
signal HDIS_END : std_logic_vector(11 downto 0); signal HDIS_END : std_logic_vector(11 downto 0);
signal BORDER_RIGHT : std_logic_vector(11 downto 0); signal BORDER_RIGHT : std_logic_vector(11 downto 0);
signal HS_START : std_logic_vector(11 downto 0); signal HS_START : std_logic_vector(11 downto 0);
signal H_TOTAL : std_logic_vector(11 downto 0); signal H_TOTAL : std_logic_vector(11 downto 0);
signal HDIS_LEN : std_logic_vector(11 downto 0); signal HDIS_LEN : std_logic_vector(11 downto 0);
signal MULF : std_logic_vector(5 downto 0); signal MULF : std_logic_vector(5 downto 0);
signal VDL_HHT : std_logic_vector(11 downto 0); signal VDL_HHT : std_logic_vector(11 downto 0);
signal VDL_HHT_CS : std_logic; signal VDL_HHT_CS : std_logic;
signal VDL_HBE : std_logic_vector(11 downto 0); signal VDL_HBE : std_logic_vector(11 downto 0);
signal VDL_HBE_CS : std_logic; signal VDL_HBE_CS : std_logic;
signal VDL_HDB : std_logic_vector(11 downto 0); signal VDL_HDB : std_logic_vector(11 downto 0);
signal VDL_HDB_CS : std_logic; signal VDL_HDB_CS : std_logic;
signal VDL_HDE : std_logic_vector(11 downto 0); signal VDL_HDE : std_logic_vector(11 downto 0);
signal VDL_HDE_CS : std_logic; signal VDL_HDE_CS : std_logic;
signal VDL_HBB : std_logic_vector(11 downto 0); signal VDL_HBB : std_logic_vector(11 downto 0);
signal VDL_HBB_CS : std_logic; signal VDL_HBB_CS : std_logic;
signal VDL_HSS : std_logic_vector(11 downto 0); signal VDL_HSS : std_logic_vector(11 downto 0);
signal VDL_HSS_CS : std_logic; signal VDL_HSS_CS : std_logic;
-- Vertical stuff: -- Vertical stuff:
signal BORDER_TOP : std_logic_vector(10 downto 0); signal BORDER_TOP : std_logic_vector(10 downto 0);
signal VDIS_START : std_logic_vector(10 downto 0); signal VDIS_START : std_logic_vector(10 downto 0);
signal VDIS_END : std_logic_vector(10 downto 0); signal VDIS_END : std_logic_vector(10 downto 0);
signal BORDER_BOTTOM : std_logic_vector(10 downto 0); signal BORDER_BOTTOM : std_logic_vector(10 downto 0);
signal VS_START : std_logic_vector(10 downto 0); signal VS_START : std_logic_vector(10 downto 0);
signal V_TOTAL : std_logic_vector(10 downto 0); signal V_TOTAL : std_logic_vector(10 downto 0);
signal FALCON_VIDEO : std_logic; signal FALCON_VIDEO : std_logic;
signal ST_VIDEO : std_logic; signal ST_VIDEO : std_logic;
signal INTER_ZEI_I : std_logic; signal INTER_ZEI_I : std_logic;
signal DOP_ZEI : std_logic; signal DOP_ZEI : std_logic;
signal VDL_VBE : std_logic_vector(10 downto 0); signal VDL_VBE : std_logic_vector(10 downto 0);
signal VDL_VBE_CS : std_logic; signal VDL_VBE_CS : std_logic;
signal VDL_VDB : std_logic_vector(10 downto 0); signal VDL_VDB : std_logic_vector(10 downto 0);
signal VDL_VDB_CS : std_logic; signal VDL_VDB_CS : std_logic;
signal VDL_VDE : std_logic_vector(10 downto 0); signal VDL_VDE : std_logic_vector(10 downto 0);
signal VDL_VDE_CS : std_logic; signal VDL_VDE_CS : std_logic;
signal VDL_VBB : std_logic_vector(10 downto 0); signal VDL_VBB : std_logic_vector(10 downto 0);
signal VDL_VBB_CS : std_logic; signal VDL_VBB_CS : std_logic;
signal VDL_VSS : std_logic_vector(10 downto 0); signal VDL_VSS : std_logic_vector(10 downto 0);
signal VDL_VSS_CS : std_logic; signal VDL_VSS_CS : std_logic;
signal VDL_VFT : std_logic_vector(10 downto 0); signal VDL_VFT : std_logic_vector(10 downto 0);
signal VDL_VFT_CS : std_logic; signal VDL_VFT_CS : std_logic;
signal VDL_VCT : std_logic_vector(8 downto 0); signal VDL_VCT : std_logic_vector(8 downto 0);
signal VDL_VCT_CS : std_logic; signal VDL_VCT_CS : std_logic;
signal VDL_VMD : std_logic_vector(3 downto 0); signal VDL_VMD : std_logic_vector(3 downto 0);
signal VDL_VMD_CS : std_logic; signal VDL_VMD_CS : std_logic;
signal COLOR1_I : std_logic; signal COLOR1_I : std_logic;
signal COLOR2_I : std_logic; signal COLOR2_I : std_logic;
signal COLOR4_I : std_logic; signal COLOR4_I : std_logic;
signal COLOR8_I : std_logic; signal COLOR8_I : std_logic;
signal COLOR16_I : std_logic; signal COLOR16_I : std_logic;
signal COLOR24_I : std_logic; signal COLOR24_I : std_logic;
signal VIDEO_MOD_TA_I : std_logic; signal VIDEO_MOD_TA_I : std_logic;
signal VR_RD_I : std_logic; signal VR_RD_I : std_logic;
signal CLK_PIXEL_I : std_logic; signal CLK_PIXEL_I : std_logic;
signal MUL1 : unsigned (16 downto 0); signal MUL1 : unsigned (16 downto 0);
signal MUL2 : unsigned(16 downto 0); signal MUL2 : unsigned(16 downto 0);
signal MUL3 : unsigned(16 downto 0); signal MUL3 : unsigned(16 downto 0);
begin begin
VR_WR <= VR_WR_I; VR_WR <= VR_WR_I;
VIDEO_RECONFIG <= VIDEO_RECONFIG_I; VIDEO_RECONFIG <= VIDEO_RECONFIG_I;
CCR <= CCR_I; CCR <= CCR_I;
INTER_ZEI <= INTER_ZEI_I; INTER_ZEI <= INTER_ZEI_I;
VIDEO_MOD_TA <= VIDEO_MOD_TA_I; VIDEO_MOD_TA <= VIDEO_MOD_TA_I;
VR_RD <= VR_RD_I; VR_RD <= VR_RD_I;
CLK_PIXEL <= CLK_PIXEL_I; CLK_PIXEL <= CLK_PIXEL_I;
-- Byte selectors: -- Byte selectors:
FB_B(0) <= '1' when FB_ADR(1 downto 0) = "00" else '0'; -- Byte 0. FB_B(0) <= '1' when FB_ADR(1 downto 0) = "00" else '0'; -- Byte 0.
FB_B(1) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word. FB_B(1) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word.
'1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long. '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long.
'1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' and FB_ADR(1) = '0' else -- High word. '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' and FB_ADR(1) = '0' else -- High word.
'1' when FB_ADR(1 downto 0) = "01" else '0'; -- Byte 1. '1' when FB_ADR(1 downto 0) = "01" else '0'; -- Byte 1.
FB_B(2) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word. FB_B(2) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word.
'1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long. '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long.
'1' when FB_ADR(1 downto 0) = "10" else '0'; -- Byte 2. '1' when FB_ADR(1 downto 0) = "10" else '0'; -- Byte 2.
FB_B(3) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word. FB_B(3) <= '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else -- Long word.
'1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long. '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- Long.
'1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' and FB_ADR(1) = '1' else -- Low word. '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3. '1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3.
-- 16 std_logic selectors: -- 16 bit selectors:
FB_16B(0) <= not FB_ADR(0); FB_16B(0) <= not FB_ADR(0);
FB_16B(1) <= '1'when FB_ADR(0) = '1' else FB_16B(1) <= '1'when FB_ADR(0) = '1' else
'1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- No byte. '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else -- No byte.
'1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' else -- No byte. '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '0' else -- No byte.
'1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else '0'; -- No byte. '1' when FB_SIZE(1) = '1' and FB_SIZE(0) = '1' else '0'; -- No byte.
-- Firebee CLUT: -- Firebee CLUT:
FBEE_CLUT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 10) = "000000000000000000" else '0'; -- 0-3FF/1024 FBEE_CLUT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 10) = "000000000000000000" else '0'; -- 0-3FF/1024
FBEE_CLUT_RD <= '1' when FBEE_CLUT_CS = '1' and FB_OEn = '0' else '0'; FBEE_CLUT_RD <= '1' when FBEE_CLUT_CS = '1' and FB_OEn = '0' else '0';
FBEE_CLUT_WR <= FB_B when FBEE_CLUT_CS = '1' and FB_WRn = '0' else x"0"; FBEE_CLUT_WR <= FB_B when FBEE_CLUT_CS = '1' and FB_WRn = '0' else x"0";
P_CLUT_TA : process P_CLUT_TA : process
begin begin
wait until CLK_MAIN = '1' and CLK_MAIN' event; wait until CLK_MAIN = '1' and CLK_MAIN' event;
if VIDEO_MOD_TA_I = '0' and FBEE_CLUT_CS = '1' then if VIDEO_MOD_TA_I = '0' and FBEE_CLUT_CS = '1' then
CLUT_TA <= '1'; CLUT_TA <= '1';
elsif VIDEO_MOD_TA_I = '0' and FALCON_CLUT_CS = '1' then elsif VIDEO_MOD_TA_I = '0' and FALCON_CLUT_CS = '1' then
CLUT_TA <= '1'; CLUT_TA <= '1';
elsif VIDEO_MOD_TA_I = '0' and ST_CLUT_CS = '1' then elsif VIDEO_MOD_TA_I = '0' and ST_CLUT_CS = '1' then
CLUT_TA <= '1'; CLUT_TA <= '1';
else else
CLUT_TA <= '0'; CLUT_TA <= '0';
end if; end if;
end process P_CLUT_TA; end process P_CLUT_TA;
--Falcon CLUT: --Falcon CLUT:
FALCON_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 10) = "1111100110" else '0'; -- $F9800/$400 FALCON_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 10) = "1111100110" else '0'; -- $F9800/$400
FALCON_CLUT_RDH <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '0' else '0'; -- High word. FALCON_CLUT_RDH <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '0' else '0'; -- High word.
FALCON_CLUT_RDL <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '1' else '0'; -- Low word. FALCON_CLUT_RDL <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '1' else '0'; -- Low word.
FALCON_CLUT_WR(1 downto 0) <= FB_16B when FB_ADR(1) = '0' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00"; FALCON_CLUT_WR(1 downto 0) <= FB_16B when FB_ADR(1) = '0' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00";
FALCON_CLUT_WR(3 downto 2) <= FB_16B when FB_ADR(1) = '1' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00"; FALCON_CLUT_WR(3 downto 2) <= FB_16B when FB_ADR(1) = '1' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00";
-- ST CLUT: -- ST CLUT:
ST_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 5) = "111110000010010" else '0'; -- $F8240/$2 ST_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 5) = "111110000010010" else '0'; -- $F8240/$2
CLUT_ST_RD <= '1' when ST_CLUT_CS = '1' and FB_OEn = '0' else '0'; CLUT_ST_RD <= '1' when ST_CLUT_CS = '1' and FB_OEn = '0' else '0';
CLUT_ST_WR <= FB_16B when ST_CLUT_CS = '1' and FB_WRn = '0' else "00"; CLUT_ST_WR <= FB_16B when ST_CLUT_CS = '1' and FB_WRn = '0' else "00";
ST_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110000" else '0'; -- $F8260/$2. ST_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110000" else '0'; -- $F8260/$2.
FALCON_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110011" else '0'; -- $F8266/$2. FALCON_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110011" else '0'; -- $F8266/$2.
FBEE_VCTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000000" else '0'; -- $400/$4 FBEE_VCTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000000" else '0'; -- $400/$4
ATARI_HH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000100" else '0'; -- $410/4 ATARI_HH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000100" else '0'; -- $410/4
ATARI_VH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000101" else '0'; -- $414/4 ATARI_VH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000101" else '0'; -- $414/4
ATARI_HL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000110" else '0'; -- $418/4 ATARI_HL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000110" else '0'; -- $418/4
ATARI_VL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000111" else '0'; -- $41C/4 ATARI_VL_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000000000100000111" else '0'; -- $41C/4
P_VIDEO_CONTROL : process P_VIDEO_CONTROL : process
begin begin
wait until CLK_MAIN = '1' and CLK_MAIN' event; wait until CLK_MAIN = '1' and CLK_MAIN' event;
if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(0) = '1' then if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(0) = '1' then
ST_SHIFT_MODE <= DATA_IN(25 downto 24); ST_SHIFT_MODE <= DATA_IN(25 downto 24);
end if; end if;
if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(2) = '1' then if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(2) = '1' then
FALCON_SHIFT_MODE(10 downto 8) <= DATA_IN(26 downto 24); FALCON_SHIFT_MODE(10 downto 8) <= DATA_IN(26 downto 24);
elsif FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(3) = '1' then elsif FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(3) = '1' then
FALCON_SHIFT_MODE(7 downto 0) <= DATA_IN(23 downto 16); FALCON_SHIFT_MODE(7 downto 0) <= DATA_IN(23 downto 16);
end if; end if;
-- Firebee VIDEO CONTROL: -- Firebee VIDEO CONTROL:
-- Bit 0 = FBEE VIDEO ON, 1 = POWER ON VIDEO DAC, 2 = FBEE 24BIT, -- Bit 0 = FBEE VIDEO ON, 1 = POWER ON VIDEO DAC, 2 = FBEE 24BIT,
-- Bit 3 = FBEE 16BIT, 4 = FBEE 8BIT, 5 = FBEE 1BIT, -- Bit 3 = FBEE 16BIT, 4 = FBEE 8BIT, 5 = FBEE 1BIT,
-- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency, -- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency,
-- Bit 15 = SYNC ALLOWED, 31..16 = VIDEO_RAM_CTR, -- Bit 15 = SYNC ALLOWED, 31..16 = VIDEO_RAM_CTR,
-- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS. -- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS.
if FBEE_VCTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then if FBEE_VCTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
FBEE_VCTR(31 downto 24) <= DATA_IN(31 downto 24); FBEE_VCTR(31 downto 24) <= DATA_IN(31 downto 24);
elsif FBEE_VCTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then elsif FBEE_VCTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
FBEE_VCTR(23 downto 16) <= DATA_IN(23 downto 16); FBEE_VCTR(23 downto 16) <= DATA_IN(23 downto 16);
elsif FBEE_VCTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then elsif FBEE_VCTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
FBEE_VCTR(15 downto 8) <= DATA_IN(15 downto 8); FBEE_VCTR(15 downto 8) <= DATA_IN(15 downto 8);
elsif FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then elsif FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
FBEE_VCTR(5 downto 0) <= DATA_IN(5 downto 0); FBEE_VCTR(5 downto 0) <= DATA_IN(5 downto 0);
end if; end if;
-- ST or Falcon shift mode: assert when X..shift register: -- ST or Falcon shift mode: assert when X..shift register:
if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' then if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
end if; end if;
if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' then if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
end if; end if;
if FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' and DATA_IN(0) = '1' then if FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' and DATA_IN(0) = '1' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON; FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
end if; end if;
-- ATARI ST mode -- ATARI ST mode
-- Horizontal timing 640x480: -- Horizontal timing 640x480:
if ATARI_HH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then if ATARI_HH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
ATARI_HH(31 downto 24) <= DATA_IN(31 downto 24); ATARI_HH(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_HH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then elsif ATARI_HH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
ATARI_HH(23 downto 16) <= DATA_IN(23 downto 16); ATARI_HH(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_HH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then elsif ATARI_HH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
ATARI_HH(15 downto 8) <= DATA_IN(15 downto 8); ATARI_HH(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_HH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then elsif ATARI_HH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
ATARI_HH(7 downto 0) <= DATA_IN(7 downto 0); ATARI_HH(7 downto 0) <= DATA_IN(7 downto 0);
end if; end if;
-- Vertical timing 640x480: -- Vertical timing 640x480:
if ATARI_VH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then if ATARI_VH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
ATARI_VH(31 downto 24) <= DATA_IN(31 downto 24); ATARI_VH(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_VH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then elsif ATARI_VH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
ATARI_VH(23 downto 16) <= DATA_IN(23 downto 16); ATARI_VH(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_VH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then elsif ATARI_VH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
ATARI_VH(15 downto 8) <= DATA_IN(15 downto 8); ATARI_VH(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_VH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then elsif ATARI_VH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
ATARI_VH(7 downto 0) <= DATA_IN(7 downto 0); ATARI_VH(7 downto 0) <= DATA_IN(7 downto 0);
end if; end if;
-- Horizontal timing 320x240: -- Horizontal timing 320x240:
if ATARI_HL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then if ATARI_HL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
ATARI_HL(31 downto 24) <= DATA_IN(31 downto 24); ATARI_HL(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_HL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then elsif ATARI_HL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
ATARI_HL(23 downto 16) <= DATA_IN(23 downto 16); ATARI_HL(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_HL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then elsif ATARI_HL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
ATARI_HL(15 downto 8) <= DATA_IN(15 downto 8); ATARI_HL(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_HL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then elsif ATARI_HL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
ATARI_HL(7 downto 0) <= DATA_IN(7 downto 0); ATARI_HL(7 downto 0) <= DATA_IN(7 downto 0);
end if; end if;
-- Vertical timing 320x240: -- Vertical timing 320x240:
if ATARI_VL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then if ATARI_VL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
ATARI_VL(31 downto 24) <= DATA_IN(31 downto 24); ATARI_VL(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_VL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then elsif ATARI_VL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
ATARI_VL(23 downto 16) <= DATA_IN(23 downto 16); ATARI_VL(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_VL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then elsif ATARI_VL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
ATARI_VL(15 downto 8) <= DATA_IN(15 downto 8); ATARI_VL(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_VL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then elsif ATARI_VL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
ATARI_VL(7 downto 0) <= DATA_IN(7 downto 0); ATARI_VL(7 downto 0) <= DATA_IN(7 downto 0);
end if; end if;
end process P_VIDEO_CONTROL; end process P_VIDEO_CONTROL;
CLUT_OFF <= FALCON_SHIFT_MODE(3 downto 0) when COLOR4_I = '1' else x"0"; CLUT_OFF <= FALCON_SHIFT_MODE(3 downto 0) when COLOR4_I = '1' else x"0";
PD_VGAn <= FBEE_VCTR(1); PD_VGAn <= FBEE_VCTR(1);
FBEE_VIDEO_ON <= FBEE_VCTR(0); FBEE_VIDEO_ON <= FBEE_VCTR(0);
ATARI_SYNC <= FBEE_VCTR(26); -- If 1 -> automatic resolution. ATARI_SYNC <= FBEE_VCTR(26); -- If 1 -> automatic resolution.
COLOR1_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "10" and COLOR8_I = '0' else -- ST mono. COLOR1_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "10" and COLOR8_I = '0' else -- ST mono.
'1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(10) = '1' and COLOR16_I = '0' and COLOR8_I = '0' else -- Falcon mono. '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(10) = '1' and COLOR16_I = '0' and COLOR8_I = '0' else -- Falcon mono.
'1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(5 downto 2) = "1000" else '0'; -- Firebee mode. '1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(5 downto 2) = "1000" else '0'; -- Firebee mode.
COLOR2_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "01" and COLOR8_I = '0' else '0'; -- ST 4 colours. COLOR2_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "01" and COLOR8_I = '0' else '0'; -- ST 4 colours.
COLOR4_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "00" and COLOR8_I = '0' else -- ST 16 colours. COLOR4_I <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and ST_SHIFT_MODE = "00" and COLOR8_I = '0' else -- ST 16 colours.
'1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' and COLOR8_I = '0' and COLOR1_I = '0' else '0'; -- Falcon mode. '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and COLOR16_I = '0' and COLOR8_I = '0' and COLOR1_I = '0' else '0'; -- Falcon mode.
COLOR8_I <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(4) = '1' and COLOR16_I = '0' else -- Falcon mode. COLOR8_I <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(4) = '1' and COLOR16_I = '0' else -- Falcon mode.
'1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(4 downto 2) = "100" else '0'; -- Firebee mode. '1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(4 downto 2) = "100" else '0'; -- Firebee mode.
COLOR16_I <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(8) = '1' else -- Falcon mode. COLOR16_I <= '1' when FALCON_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_SHIFT_MODE(8) = '1' else -- Falcon mode.
'1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(3 downto 2) = "10" else '0'; -- Firebee mode. '1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(3 downto 2) = "10" else '0'; -- Firebee mode.
COLOR24_I <= '1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(2) = '1' else '0'; -- Firebee mode. COLOR24_I <= '1' when FBEE_VIDEO_ON = '1' and FBEE_VCTR(2) = '1' else '0'; -- Firebee mode.
COLOR1 <= COLOR1_I; COLOR1 <= COLOR1_I;
COLOR2 <= COLOR2_I; COLOR2 <= COLOR2_I;
COLOR4 <= COLOR4_I; COLOR4 <= COLOR4_I;
COLOR8 <= COLOR8_I; COLOR8 <= COLOR8_I;
-- VIDEO PLL config and reconfig: -- VIDEO PLL config and reconfig:
VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only. VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only.
VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800. VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800.
VR_RD_I <= '1' when VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' else '0'; VR_RD_I <= '1' when VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' else '0';
P_VIDEO_CONFIG: process P_VIDEO_CONFIG: process
variable LOCK : boolean; variable LOCK : boolean;
begin begin
wait until CLK_MAIN = '1' and CLK_MAIN' event; wait until CLK_MAIN = '1' and CLK_MAIN' event;
if VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and VR_WR_I = '0' then if VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and VR_WR_I = '0' then
VR_WR_I <= '1'; -- This is a strobe. VR_WR_I <= '1'; -- This is a strobe.
else else
VR_WR_I <= '0'; VR_WR_I <= '0';
end if; end if;
if VR_BUSY = '1' then if VR_BUSY = '1' then
VR_DOUT <= VR_D; VR_DOUT <= VR_D;
end if; end if;
if VR_WR_I = '1' and FB_ADR(8 downto 0) = "000000100" then if VR_WR_I = '1' and FB_ADR(8 downto 0) = "000000100" then
VR_FRQ <= DATA_IN(23 downto 16); VR_FRQ <= DATA_IN(23 downto 16);
end if; end if;
if VIDEO_PLL_RECONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and LOCK = false then if VIDEO_PLL_RECONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and LOCK = false then
VIDEO_RECONFIG_I <= '1'; -- This is a strobe. VIDEO_RECONFIG_I <= '1'; -- This is a strobe.
LOCK := true; LOCK := true;
elsif VIDEO_PLL_RECONFIG_CS = '0' or FB_WRn = '1' or VR_BUSY = '1' then elsif VIDEO_PLL_RECONFIG_CS = '0' or FB_WRn = '1' or VR_BUSY = '1' then
VIDEO_RECONFIG_I <= '0'; VIDEO_RECONFIG_I <= '0';
LOCK := false; LOCK := false;
else else
VIDEO_RECONFIG_I <= '0'; VIDEO_RECONFIG_I <= '0';
end if; end if;
end process P_VIDEO_CONFIG; end process P_VIDEO_CONFIG;
VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16); VIDEO_RAM_CTR <= FBEE_VCTR(31 downto 16);
@@ -727,7 +727,7 @@ begin
P_DOUBLE_LINE_2 : process P_DOUBLE_LINE_2 : process
begin begin
wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I'event;
if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then if DOP_ZEI = '1' and VVCNT(0) /= VDIS_START(0) and VVCNT /= "00000000000" and VHCNT < std_logic_vector(unsigned(HDIS_END) - 1) then
INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC. INTER_ZEI_I <= '1'; -- Switch insertion line to "double". Line zero due to SYNC.
elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then elsif DOP_ZEI = '1' and VVCNT(0) = VDIS_START(0) and VVCNT /= "00000000000" and VHCNT > std_logic_vector(unsigned(HDIS_END) - 10) then