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removed all dependencies to obsolete ieee.std_logic_arith and ieee.std_logic_unsigned in favour of ieee.numeric_std. There are a few things that still need to be fixed because of that, however.

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This commit is contained in:
Markus Fröschle
2014-08-04 17:23:47 +00:00
parent d96e0b82bc
commit 4c2be14e28
42 changed files with 2695 additions and 2662 deletions
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46
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_gpio.vhd
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@@ -56,42 +56,42 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_GPIO is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Timer controls:
AER_4 : out bit;
AER_3 : out bit;
AER_4 : out std_logic;
AER_3 : out std_logic;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_OUT_EN : buffer bit_vector(7 downto 0);
GP_INT : out bit_vector(7 downto 0)
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_OUT_EN : buffer std_logic_vector(7 downto 0);
GP_INT : out std_logic_vector(7 downto 0)
);
end entity WF68901IP_GPIO;
architecture BEHAVIOR of WF68901IP_GPIO is
signal GPDR : bit_vector(7 downto 0);
signal DDR : bit_vector(7 downto 0);
signal AER : bit_vector(7 downto 0);
signal GPDR_I : bit_vector(7 downto 0);
signal GPDR : std_logic_vector(7 downto 0);
signal DDR : std_logic_vector(7 downto 0);
signal AER : std_logic_vector(7 downto 0);
signal GPDR_I : std_logic_vector(7 downto 0);
begin
-- These two bits control the timers A and B pulse width operation and the
-- These two std_logics control the timers A and B pulse width operation and the
-- timers A and B event count operation.
AER_4 <= AER(4);
AER_3 <= AER(3);
@@ -120,7 +120,7 @@ begin
end if;
end process GPIO_REGISTERS;
GPIP_OUT <= GPDR; -- Port outputs.
GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP.
GPIP_OUT_EN <= DDR; -- The DDR is capable to control std_logicwise the GPIP.
DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0';
DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else
AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else
@@ -128,7 +128,7 @@ begin
P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR)
-- Read back control: Read the port pins, if the data direction is configured as input.
-- Read the respective GPDR register bit, if the data direction is configured as output.
-- Read the respective GPDR register std_logic, if the data direction is configured as output.
begin
for i in 7 downto 0 loop
if GPIP_OUT_EN(i) = '1' then -- Port is configured output.

104
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_interrupts.vhd
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@@ -58,48 +58,48 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_INTERRUPTS is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Interrupt sources:
GP_INT : in bit_vector(7 downto 0);
GP_INT : in std_logic_vector(7 downto 0);
AER_4 : in bit;
AER_3 : in bit;
TAI : in bit;
TBI : in bit;
TA_PWM : in bit;
TB_PWM : in bit;
TIMER_A_INT : in bit;
TIMER_B_INT : in bit;
TIMER_C_INT : in bit;
TIMER_D_INT : in bit;
AER_4 : in std_logic;
AER_3 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TA_PWM : in std_logic;
TB_PWM : in std_logic;
TIMER_A_INT : in std_logic;
TIMER_B_INT : in std_logic;
TIMER_C_INT : in std_logic;
TIMER_D_INT : in std_logic;
RCV_ERR : in bit;
TRM_ERR : in bit;
RCV_BUF_F : in bit;
TRM_BUF_E : in bit
RCV_ERR : in std_logic;
TRM_ERR : in std_logic;
RCV_BUF_F : in std_logic;
TRM_BUF_E : in std_logic
);
end entity WF68901IP_INTERRUPTS;
@@ -108,27 +108,27 @@ architecture BEHAVIOR of WF68901IP_INTERRUPTS is
type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
signal INT_STATE : INT_STATES;
-- The registers:
signal IERA : bit_vector(7 downto 0);
signal IERB : bit_vector(7 downto 0);
signal IPRA : bit_vector(7 downto 0);
signal IPRB : bit_vector(7 downto 0);
signal ISRA : bit_vector(7 downto 0);
signal ISRB : bit_vector(7 downto 0);
signal IMRA : bit_vector(7 downto 0);
signal IMRB : bit_vector(7 downto 0);
signal VR : bit_vector(7 downto 3);
signal IERA : std_logic_vector(7 downto 0);
signal IERB : std_logic_vector(7 downto 0);
signal IPRA : std_logic_vector(7 downto 0);
signal IPRB : std_logic_vector(7 downto 0);
signal ISRA : std_logic_vector(7 downto 0);
signal ISRB : std_logic_vector(7 downto 0);
signal IMRA : std_logic_vector(7 downto 0);
signal IMRB : std_logic_vector(7 downto 0);
signal VR : std_logic_vector(7 downto 3);
-- Interconnect:
signal VECT_NUMBER : bit_vector(7 downto 0);
signal INT_SRC : bit_vector(15 downto 0);
signal INT_SRC_EDGE : bit_vector(15 downto 0);
signal INT_ENA : bit_vector(15 downto 0);
signal INT_MASK : bit_vector(15 downto 0);
signal INT_PENDING : bit_vector(15 downto 0);
signal INT_SERVICE : bit_vector(15 downto 0);
signal INT_PASS : bit_vector(15 downto 0);
signal INT_OUT : bit_vector(15 downto 0);
signal GP_INT_4 : bit;
signal GP_INT_3 : bit;
signal VECT_NUMBER : std_logic_vector(7 downto 0);
signal INT_SRC : std_logic_vector(15 downto 0);
signal INT_SRC_EDGE : std_logic_vector(15 downto 0);
signal INT_ENA : std_logic_vector(15 downto 0);
signal INT_MASK : std_logic_vector(15 downto 0);
signal INT_PENDING : std_logic_vector(15 downto 0);
signal INT_SERVICE : std_logic_vector(15 downto 0);
signal INT_PASS : std_logic_vector(15 downto 0);
signal INT_OUT : std_logic_vector(15 downto 0);
signal GP_INT_4 : std_logic;
signal GP_INT_3 : std_logic;
begin
-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
@@ -162,7 +162,7 @@ begin
EDGE_ENA: process(RESETn, CLK)
-- These are the 16 edge detectors of the 16 interrupt input sources. This
-- process also provides the disabling or enabling via the IERA and IERB registers.
variable LOCK : bit_vector(15 downto 0);
variable LOCK : std_logic_vector(15 downto 0);
begin
if RESETn = '0' then
INT_SRC_EDGE <= x"0000";
@@ -234,7 +234,7 @@ begin
end if;
-- Pending register:
-- set and clear bit logic.
-- set and clear std_logic logic.
for i in 15 downto 8 loop
if INT_SRC_EDGE(i) = '1' then
IPRA(i-8) <= '1';
@@ -255,7 +255,7 @@ begin
end loop;
-- In-Service register:
-- Set bit logic, VR(3) is the service register enable.
-- Set std_logic logic, VR(3) is the service register enable.
for i in 15 downto 8 loop
if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
ISRA(i-8) <= '1';

334
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_pkg.vhd
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@@ -60,203 +60,203 @@ use ieee.std_logic_1164.all;
package WF68901IP_PKG is
component WF68901IP_USART_TOP
port ( CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RX_ERR_INT : out bit;
RX_BUFF_INT : out bit;
TX_ERR_INT : out bit;
TX_BUFF_INT : out bit;
RRn : out bit;
TRn : out bit
port ( CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
RX_ERR_INT : out std_logic;
RX_BUFF_INT : out std_logic;
TX_ERR_INT : out std_logic;
TX_BUFF_INT : out std_logic;
RRn : out std_logic;
TRn : out std_logic
);
end component;
component WF68901IP_USART_CTRL
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RX_SAMPLE : in bit;
RX_DATA : in bit_vector(7 downto 0);
TX_DATA : out bit_vector(7 downto 0);
SCR_OUT : out bit_vector(7 downto 0);
BF : in bit;
BE : in bit;
FE : in bit;
OE : in bit;
UE : in bit;
PE : in bit;
M_CIP : in bit;
FS_B : in bit;
TX_END : in bit;
CL : out bit_vector(1 downto 0);
ST : out bit_vector(1 downto 0);
FS_CLR : out bit;
RSR_READ : out bit;
TSR_READ : out bit;
UDR_READ : out bit;
UDR_WRITE : out bit;
LOOPBACK : out bit;
SDOUT_EN : out bit;
SD_LEVEL : out bit;
CLK_MODE : out bit;
RE : out bit;
TE : out bit;
P_ENA : out bit;
P_EOn : out bit;
SS : out bit;
BR : out bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
RX_SAMPLE : in std_logic;
RX_DATA : in std_logic_vector(7 downto 0);
TX_DATA : out std_logic_vector(7 downto 0);
SCR_OUT : out std_logic_vector(7 downto 0);
BF : in std_logic;
BE : in std_logic;
FE : in std_logic;
OE : in std_logic;
UE : in std_logic;
PE : in std_logic;
M_CIP : in std_logic;
FS_B : in std_logic;
TX_END : in std_logic;
CL : out std_logic_vector(1 downto 0);
ST : out std_logic_vector(1 downto 0);
FS_CLR : out std_logic;
RSR_READ : out std_logic;
TSR_READ : out std_logic;
UDR_READ : out std_logic;
UDR_WRITE : out std_logic;
LOOPBACK : out std_logic;
SDOUT_EN : out std_logic;
SD_LEVEL : out std_logic;
CLK_MODE : out std_logic;
RE : out std_logic;
TE : out std_logic;
P_ENA : out std_logic;
P_EOn : out std_logic;
SS : out std_logic;
BR : out std_logic
);
end component;
component WF68901IP_USART_TX
port (
CLK : in bit;
RESETn : in bit;
SCR : in bit_vector(7 downto 0);
TX_DATA : in bit_vector(7 downto 0);
SDATA_OUT : out bit;
TXCLK : in bit;
CL : in bit_vector(1 downto 0);
ST : in bit_vector(1 downto 0);
TE : in bit;
BR : in bit;
P_ENA : in bit;
P_EOn : in bit;
UDR_WRITE : in bit;
TSR_READ : in bit;
CLK_MODE : in bit;
TX_END : out bit;
UE : out bit;
BE : out bit
CLK : in std_logic;
RESETn : in std_logic;
SCR : in std_logic_vector(7 downto 0);
TX_DATA : in std_logic_vector(7 downto 0);
SDATA_OUT : out std_logic;
TXCLK : in std_logic;
CL : in std_logic_vector(1 downto 0);
ST : in std_logic_vector(1 downto 0);
TE : in std_logic;
BR : in std_logic;
P_ENA : in std_logic;
P_EOn : in std_logic;
UDR_WRITE : in std_logic;
TSR_READ : in std_logic;
CLK_MODE : in std_logic;
TX_END : out std_logic;
UE : out std_logic;
BE : out std_logic
);
end component;
component WF68901IP_USART_RX
port (
CLK : in bit;
RESETn : in bit;
SCR : in bit_vector(7 downto 0);
RX_SAMPLE : out bit;
RX_DATA : out bit_vector(7 downto 0);
RXCLK : in bit;
SDATA_IN : in bit;
CL : in bit_vector(1 downto 0);
ST : in bit_vector(1 downto 0);
P_ENA : in bit;
P_EOn : in bit;
CLK_MODE : in bit;
RE : in bit;
FS_CLR : in bit;
SS : in bit;
RSR_READ : in bit;
UDR_READ : in bit;
M_CIP : out bit;
FS_B : out bit;
BF : out bit;
OE : out bit;
PE : out bit;
FE : out bit
CLK : in std_logic;
RESETn : in std_logic;
SCR : in std_logic_vector(7 downto 0);
RX_SAMPLE : out std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RXCLK : in std_logic;
SDATA_IN : in std_logic;
CL : in std_logic_vector(1 downto 0);
ST : in std_logic_vector(1 downto 0);
P_ENA : in std_logic;
P_EOn : in std_logic;
CLK_MODE : in std_logic;
RE : in std_logic;
FS_CLR : in std_logic;
SS : in std_logic;
RSR_READ : in std_logic;
UDR_READ : in std_logic;
M_CIP : out std_logic;
FS_B : out std_logic;
BF : out std_logic;
OE : out std_logic;
PE : out std_logic;
FE : out std_logic
);
end component;
component WF68901IP_INTERRUPTS
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
GP_INT : in bit_vector(7 downto 0);
AER_4 : in bit;
AER_3 : in bit;
TAI : in bit;
TBI : in bit;
TA_PWM : in bit;
TB_PWM : in bit;
TIMER_A_INT : in bit;
TIMER_B_INT : in bit;
TIMER_C_INT : in bit;
TIMER_D_INT : in bit;
RCV_ERR : in bit;
TRM_ERR : in bit;
RCV_BUF_F : in bit;
TRM_BUF_E : in bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
GP_INT : in std_logic_vector(7 downto 0);
AER_4 : in std_logic;
AER_3 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TA_PWM : in std_logic;
TB_PWM : in std_logic;
TIMER_A_INT : in std_logic;
TIMER_B_INT : in std_logic;
TIMER_C_INT : in std_logic;
TIMER_D_INT : in std_logic;
RCV_ERR : in std_logic;
TRM_ERR : in std_logic;
RCV_BUF_F : in std_logic;
TRM_BUF_E : in std_logic
);
end component;
component WF68901IP_GPIO
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
AER_4 : out bit;
AER_3 : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_OUT_EN : out bit_vector(7 downto 0);
GP_INT : out bit_vector(7 downto 0)
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
AER_4 : out std_logic;
AER_3 : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_OUT_EN : out std_logic_vector(7 downto 0);
GP_INT : out std_logic_vector(7 downto 0)
);
end component;
component WF68901IP_TIMERS
port (
CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
XTAL1 : in bit;
TAI : in bit;
TBI : in bit;
AER_4 : in bit;
AER_3 : in bit;
TA_PWM : out bit;
TB_PWM : out bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
TIMER_A_INT : out bit;
TIMER_B_INT : out bit;
TIMER_C_INT : out bit;
TIMER_D_INT : out bit
CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
XTAL1 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
AER_4 : in std_logic;
AER_3 : in std_logic;
TA_PWM : out std_logic;
TB_PWM : out std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
TIMER_A_INT : out std_logic;
TIMER_B_INT : out std_logic;
TIMER_C_INT : out std_logic;
TIMER_D_INT : out std_logic
);
end component;

238
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd
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@@ -65,71 +65,71 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TIMERS is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
AER_4 : in bit;
AER_3 : in bit;
TA_PWM : out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
TB_PWM : out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
TAO : buffer bit;
TBO : buffer bit;
TCO : buffer bit;
TDO : buffer bit;
TIMER_A_INT : out bit;
TIMER_B_INT : out bit;
TIMER_C_INT : out bit;
TIMER_D_INT : out bit
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
AER_4 : in std_logic;
AER_3 : in std_logic;
TA_PWM : out std_logic; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
TB_PWM : out std_logic; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
TAO : buffer std_logic;
TBO : buffer std_logic;
TCO : buffer std_logic;
TDO : buffer std_logic;
TIMER_A_INT : out std_logic;
TIMER_B_INT : out std_logic;
TIMER_C_INT : out std_logic;
TIMER_D_INT : out std_logic
);
end entity WF68901IP_TIMERS;
architecture BEHAVIOR of WF68901IP_TIMERS is
signal XTAL1_S : bit;
signal XTAL_STRB : bit;
signal TACR : bit_vector(4 downto 0); -- Timer A control register.
signal TBCR : bit_vector(4 downto 0); -- Timer B control register.
signal TCDCR : bit_vector(5 downto 0); -- Timer C and D control register.
signal TADR : bit_vector(7 downto 0); -- Timer A data register.
signal TBDR : bit_vector(7 downto 0); -- Timer B data register.
signal TCDR : bit_vector(7 downto 0); -- Timer C data register.
signal TDDR : bit_vector(7 downto 0); -- Timer D data register.
signal TIMER_A : std_logic_vector(7 downto 0); -- Timer A count register.
signal TIMER_B : std_logic_vector(7 downto 0); -- Timer B count register.
signal TIMER_C : std_logic_vector(7 downto 0); -- Timer C count register.
signal TIMER_D : std_logic_vector(7 downto 0); -- Timer D count register.
signal TIMER_R_A : bit_vector(7 downto 0); -- Timer A readback register.
signal TIMER_R_B : bit_vector(7 downto 0); -- Timer B readback register.
signal TIMER_R_C : bit_vector(7 downto 0); -- Timer C readback register.
signal TIMER_R_D : bit_vector(7 downto 0); -- Timer D readback register.
signal A_CNTSTRB : bit;
signal B_CNTSTRB : bit;
signal C_CNTSTRB : bit;
signal D_CNTSTRB : bit;
signal TAI_I : bit;
signal TBI_I : bit;
signal TAI_STRB : bit; -- Strobe for the event counter mode.
signal TBI_STRB : bit; -- Strobe for the event counter mode.
signal TAO_I : bit; -- Timer A output signal.
signal TBO_I : bit; -- Timer A output signal.
signal XTAL1_S : std_logic;
signal XTAL_STRB : std_logic;
signal TACR : std_logic_vector(4 downto 0); -- Timer A control register.
signal TBCR : std_logic_vector(4 downto 0); -- Timer B control register.
signal TCDCR : std_logic_vector(5 downto 0); -- Timer C and D control register.
signal TADR : std_logic_vector(7 downto 0); -- Timer A data register.
signal TBDR : std_logic_vector(7 downto 0); -- Timer B data register.
signal TCDR : std_logic_vector(7 downto 0); -- Timer C data register.
signal TDDR : std_logic_vector(7 downto 0); -- Timer D data register.
signal TIMER_A : unsigned (7 downto 0); -- Timer A count register.
signal TIMER_B : unsigned (7 downto 0); -- Timer B count register.
signal TIMER_C : unsigned (7 downto 0); -- Timer C count register.
signal TIMER_D : unsigned (7 downto 0); -- Timer D count register.
signal TIMER_R_A : std_logic_vector (7 downto 0); -- Timer A readback register.
signal TIMER_R_B : std_logic_vector (7 downto 0); -- Timer B readback register.
signal TIMER_R_C : std_logic_vector (7 downto 0); -- Timer C readback register.
signal TIMER_R_D : std_logic_vector (7 downto 0); -- Timer D readback register.
signal A_CNTSTRB : std_logic;
signal B_CNTSTRB : std_logic;
signal C_CNTSTRB : std_logic;
signal D_CNTSTRB : std_logic;
signal TAI_I : std_logic;
signal TBI_I : std_logic;
signal TAI_STRB : std_logic; -- Strobe for the event counter mode.
signal TBI_STRB : std_logic; -- Strobe for the event counter mode.
signal TAO_I : std_logic; -- Timer A output signal.
signal TBO_I : std_logic; -- Timer A output signal.
begin
SYNC: process
-- This process provides a 'clean' XTAL1.
@@ -183,45 +183,45 @@ begin
end if;
end process TIMER_REGISTERS;
TIMER_READBACK : process(RESETn, CLK)
-- This process provides the readback information for the
-- timers A to D. The information read is the information
-- last clocked into the timer read register when the DSn
-- pin had last gone high prior to the current read cycle.
variable READ_A : boolean;
variable READ_B : boolean;
variable READ_C : boolean;
variable READ_D : boolean;
begin
if RESETn = '0' then
TIMER_R_A <= x"00";
TIMER_R_B <= x"00";
TIMER_R_C <= x"00";
TIMER_R_D <= x"00";
elsif CLK = '1' and CLK' event then
if DSn = '0' and RWn = '1' and RS = "01111" then
READ_A := true;
elsif DSn = '0' and RWn = '1' and RS = "10000" then
READ_B := true;
elsif DSn = '0' and RWn = '1' and RS = "10001" then
READ_C := true;
elsif DSn = '0' and RWn = '1' and RS = "10010" then
READ_D := true;
elsif DSn = '1' and READ_A = true then
TIMER_R_A <= To_BitVector(TIMER_A);
READ_A := false;
elsif DSn = '1' and READ_B = true then
TIMER_R_B <= To_BitVector(TIMER_B);
READ_B := false;
elsif DSn = '1' and READ_C = true then
TIMER_R_C <= To_BitVector(TIMER_C);
READ_C := false;
elsif DSn = '1' and READ_D = true then
TIMER_R_D <= To_BitVector(TIMER_D);
READ_D := false;
end if;
end if;
end process TIMER_READBACK;
TIMER_READBACK : process(RESETn, CLK)
-- This process provides the readback information for the
-- timers A to D. The information read is the information
-- last clocked into the timer read register when the DSn
-- pin had last gone high prior to the current read cycle.
variable READ_A : boolean;
variable READ_B : boolean;
variable READ_C : boolean;
variable READ_D : boolean;
begin
if RESETn = '0' then
TIMER_R_A <= x"00";
TIMER_R_B <= x"00";
TIMER_R_C <= x"00";
TIMER_R_D <= x"00";
elsif CLK = '1' and CLK' event then
if DSn = '0' and RWn = '1' and RS = "01111" then
READ_A := true;
elsif DSn = '0' and RWn = '1' and RS = "10000" then
READ_B := true;
elsif DSn = '0' and RWn = '1' and RS = "10001" then
READ_C := true;
elsif DSn = '0' and RWn = '1' and RS = "10010" then
READ_D := true;
elsif DSn = '1' and READ_A = true then
TIMER_R_A <= std_logic_vector(TIMER_A);
READ_A := false;
elsif DSn = '1' and READ_B = true then
TIMER_R_B <= std_logic_vector(TIMER_B);
READ_B := false;
elsif DSn = '1' and READ_C = true then
TIMER_R_C <= std_logic_vector(TIMER_C);
READ_C := false;
elsif DSn = '1' and READ_D = true then
TIMER_R_D <= std_logic_vector(TIMER_D);
READ_D := false;
end if;
end if;
end process TIMER_READBACK;
DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "01011" and RS <= "10010" else '0';
DATA_OUT <= "000" & TACR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01100" else
@@ -290,12 +290,12 @@ begin
PRESCALE_A: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
A_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TACR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -313,12 +313,12 @@ begin
PRESCALE_B: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
B_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TBCR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -336,12 +336,12 @@ begin
PRESCALE_C: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
C_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TCDCR(5 downto 3) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -359,12 +359,12 @@ begin
PRESCALE_D: process
-- The prescalers work even if the RESETn is asserted.
variable PRESCALE : std_logic_vector(7 downto 0);
variable PRESCALE : unsigned (7 downto 0);
begin
wait until CLK = '1' and CLK' event;
D_CNTSTRB <= '0';
if PRESCALE > x"00" and XTAL_STRB = '1' then
PRESCALE := PRESCALE - '1';
PRESCALE := PRESCALE - 1;
elsif XTAL_STRB = '1' then
case TCDCR(2 downto 0) is
when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
@@ -391,32 +391,32 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_A <= To_StdLogicVector(DATA_IN);
TIMER_A <= unsigned(DATA_IN);
else
case TACR(3 downto 0) is
when x"0" => -- Timer is off.
TAO_I <= '0';
when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= TIMER_A - 1;
elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
when x"8" => -- Event count operation.
if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= unsigned(TIMER_A) - 1;
elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
TIMER_A <= TIMER_A - '1';
TIMER_A <= unsigned(TIMER_A) - 1;
elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
TIMER_A <= To_StdLogicVector(TADR);
TIMER_A <= unsigned(TADR);
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
@@ -436,32 +436,32 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_B <= To_StdLogicVector(DATA_IN);
TIMER_B <= unsigned(DATA_IN);
else
case TBCR(3 downto 0) is
when x"0" => -- Timer is off.
TBO_I <= '0';
when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
when x"8" => -- Event count operation.
if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
TIMER_B <= TIMER_B - '1';
TIMER_B <= TIMER_B - 1;
elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
TIMER_B <= To_StdLogicVector(TBDR);
TIMER_B <= unsigned(TBDR);
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
@@ -481,16 +481,16 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_C <= To_StdLogicVector(DATA_IN);
TIMER_C <= unsigned(DATA_IN);
else
case TCDCR(5 downto 3) is
when "000" => -- Timer is off.
TCO <= '0';
when others => -- Delay counter mode.
if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count.
TIMER_C <= TIMER_C - '1';
TIMER_C <= TIMER_C - 1;
elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload.
TIMER_C <= To_StdLogicVector(TCDR);
TIMER_C <= unsigned(TCDR);
TCO <= not TCO; -- Toggle the timer C output pin.
TIMER_C_INT <= '1';
end if;
@@ -510,16 +510,16 @@ begin
--
if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then
-- The timer is reloaded simultaneously to it's timer data register, if it is off.
TIMER_D <= To_StdLogicVector(DATA_IN);
TIMER_D <= unsigned(DATA_IN);
else
case TCDCR(2 downto 0) is
when "000" => -- Timer is off.
TDO <= '0';
when others => -- Delay counter mode.
if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count.
TIMER_D <= TIMER_D - '1';
TIMER_D <= TIMER_D - 1;
elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload.
TIMER_D <= To_StdLogicVector(TDDR);
TIMER_D <= unsigned(TDDR);
TDO <= not TDO; -- Toggle the timer D output pin.
TIMER_D_INT <= '1';
end if;

120
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top.vhd
View File

@@ -62,103 +62,103 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TOP is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
RS : in std_logic_vector(5 downto 1);
DATA : inout std_logic_vector(7 downto 0);
GPIP : inout std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in bit;
TC : in bit;
SI : in bit;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_TOP;
architecture STRUCTURE of WF68901IP_TOP is
component WF68901IP_TOP_SOC
port(CLK : in bit;
RESETn : in bit;
DSn : in bit;
CSn : in bit;
RWn : in bit;
DTACKn : out bit;
RS : in bit_vector(5 downto 1);
port(CLK : in std_logic;
RESETn : in std_logic;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_EN : out bit_vector(7 downto 0);
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
XTAL1 : in bit;
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RRn : out bit;
TRn : out bit
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
XTAL1 : in std_logic;
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
RRn : out std_logic;
TRn : out std_logic
);
end component;
--
signal DTACK_In : bit;
signal IRQ_In : bit;
signal DTACK_In : std_logic;
signal IRQ_In : std_logic;
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : bit;
signal GPIP_IN : bit_vector(7 downto 0);
signal GPIP_OUT : bit_vector(7 downto 0);
signal GPIP_EN : bit_vector(7 downto 0);
signal SO_I : bit;
signal SO_EN : bit;
signal DATA_EN : std_logic;
signal GPIP_IN : std_logic_vector(7 downto 0);
signal GPIP_OUT : std_logic_vector(7 downto 0);
signal GPIP_EN : std_logic_vector(7 downto 0);
signal SO_I : std_logic;
signal SO_EN : std_logic;
begin
DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
GPIP_IN <= To_BitVector(GPIP);
GPIP_IN <= GPIP;
P_GPIP_OUT: process(GPIP_OUT, GPIP_EN)
begin

130
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_top_soc.vhd
View File

@@ -67,88 +67,88 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_TOP_SOC is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DTACKn : out bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
GPIP_IN : in bit_vector(7 downto 0);
GPIP_OUT : out bit_vector(7 downto 0);
GPIP_EN : out bit_vector(7 downto 0);
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in bit; -- Use an oszillator instead of a quartz.
TAI : in bit;
TBI : in bit;
TAO : out bit;
TBO : out bit;
TCO : out bit;
TDO : out bit;
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in bit;
TC : in bit;
SI : in bit;
SO : out bit;
SO_EN : out bit;
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_TOP_SOC;
architecture STRUCTURE of WF68901IP_TOP_SOC is
signal DATA_IN_I : bit_vector(7 downto 0);
signal DTACK_In : bit;
signal DATA_IN_I : std_logic_vector(7 downto 0);
signal DTACK_In : std_logic;
signal DTACK_LOCK : boolean;
signal DTACK_OUTn : bit;
signal RX_ERR_INT_I : bit;
signal TX_ERR_INT_I : bit;
signal RX_BUFF_INT_I : bit;
signal TX_BUFF_INT_I : bit;
signal DATA_OUT_USART_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_USART_I : bit;
signal DATA_OUT_INT_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_INT_I : bit;
signal DATA_OUT_GPIO_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_GPIO_I : bit;
signal DATA_OUT_TIMERS_I : bit_vector(7 downto 0);
signal DATA_OUT_EN_TIMERS_I : bit;
signal SO_I : bit;
signal SO_EN_I : bit;
signal GPIP_IN_I : bit_vector(7 downto 0);
signal GPIP_OUT_I : bit_vector(7 downto 0);
signal GPIP_EN_I : bit_vector(7 downto 0);
signal GP_INT_I : bit_vector(7 downto 0);
signal TIMER_A_INT_I : bit;
signal TIMER_B_INT_I : bit;
signal TIMER_C_INT_I : bit;
signal TIMER_D_INT_I : bit;
signal IRQ_In : bit;
signal AER_4_I : bit;
signal AER_3_I : bit;
signal TA_PWM_I : bit;
signal TB_PWM_I : bit;
signal DTACK_OUTn : std_logic;
signal RX_ERR_INT_I : std_logic;
signal TX_ERR_INT_I : std_logic;
signal RX_BUFF_INT_I : std_logic;
signal TX_BUFF_INT_I : std_logic;
signal DATA_OUT_USART_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_USART_I : std_logic;
signal DATA_OUT_INT_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_INT_I : std_logic;
signal DATA_OUT_GPIO_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_GPIO_I : std_logic;
signal DATA_OUT_TIMERS_I : std_logic_vector(7 downto 0);
signal DATA_OUT_EN_TIMERS_I : std_logic;
signal SO_I : std_logic;
signal SO_EN_I : std_logic;
signal GPIP_IN_I : std_logic_vector(7 downto 0);
signal GPIP_OUT_I : std_logic_vector(7 downto 0);
signal GPIP_EN_I : std_logic_vector(7 downto 0);
signal GP_INT_I : std_logic_vector(7 downto 0);
signal TIMER_A_INT_I : std_logic;
signal TIMER_B_INT_I : std_logic;
signal TIMER_C_INT_I : std_logic;
signal TIMER_D_INT_I : std_logic;
signal IRQ_In : std_logic;
signal AER_4_I : std_logic;
signal AER_3_I : std_logic;
signal TA_PWM_I : std_logic;
signal TB_PWM_I : std_logic;
begin
-- Interrupt request (open drain):
IRQn <= IRQ_In;
@@ -162,13 +162,13 @@ begin
GPIP_OUT <= GPIP_OUT_I;
GPIP_EN <= GPIP_EN_I;
DATA_IN_I <= To_BitVector(DATA_IN);
DATA_IN_I <= DATA_IN;
DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I;
-- Output data multiplexer:
DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else
To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else
To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else
To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
DATA_OUT <= DATA_OUT_USART_I when DATA_OUT_EN_USART_I = '1' else
DATA_OUT_INT_I when DATA_OUT_EN_INT_I = '1' else
DATA_OUT_GPIO_I when DATA_OUT_EN_GPIO_I = '1' else
DATA_OUT_TIMERS_I when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
-- Data acknowledge handshake is provided by the following statement and the consecutive two
-- processes. For more information refer to the M68000 family reference manual.

90
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
View File

@@ -56,67 +56,67 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_CTRL is
port (
-- System Control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- USART data register
RX_SAMPLE : in bit;
RX_DATA : in bit_vector(7 downto 0);
TX_DATA : out bit_vector(7 downto 0);
SCR_OUT : out bit_vector(7 downto 0);
RX_SAMPLE : in std_logic;
RX_DATA : in std_logic_vector(7 downto 0);
TX_DATA : out std_logic_vector(7 downto 0);
SCR_OUT : out std_logic_vector(7 downto 0);
-- USART control inputs:
BF : in bit;
BE : in bit;
FE : in bit;
OE : in bit;
UE : in bit;
PE : in bit;
M_CIP : in bit;
FS_B : in bit;
TX_END : in bit;
BF : in std_logic;
BE : in std_logic;
FE : in std_logic;
OE : in std_logic;
UE : in std_logic;
PE : in std_logic;
M_CIP : in std_logic;
FS_B : in std_logic;
TX_END : in std_logic;
-- USART control outputs:
CL : out bit_vector(1 downto 0);
ST : out bit_vector(1 downto 0);
FS_CLR : out bit;
UDR_WRITE : out bit;
UDR_READ : out bit;
RSR_READ : out bit;
TSR_READ : out bit;
LOOPBACK : out bit;
SDOUT_EN : out bit;
SD_LEVEL : out bit;
CLK_MODE : out bit;
RE : out bit;
TE : out bit;
P_ENA : out bit;
P_EOn : out bit;
SS : out bit;
BR : out bit
CL : out std_logic_vector(1 downto 0);
ST : out std_logic_vector(1 downto 0);
FS_CLR : out std_logic;
UDR_WRITE : out std_logic;
UDR_READ : out std_logic;
RSR_READ : out std_logic;
TSR_READ : out std_logic;
LOOPBACK : out std_logic;
SDOUT_EN : out std_logic;
SD_LEVEL : out std_logic;
CLK_MODE : out std_logic;
RE : out std_logic;
TE : out std_logic;
P_ENA : out std_logic;
P_EOn : out std_logic;
SS : out std_logic;
BR : out std_logic
);
end entity WF68901IP_USART_CTRL;
architecture BEHAVIOR of WF68901IP_USART_CTRL is
signal SCR : bit_vector(7 downto 0); -- Synchronous data register.
signal UCR : bit_vector(7 downto 1); -- USART control register.
signal RSR : bit_vector(7 downto 0); -- Receiver status register.
signal TSR : bit_vector(7 downto 0); -- Transmitter status register.
signal UDR : bit_vector(7 downto 0); -- USART data register.
signal SCR : std_logic_vector(7 downto 0); -- Synchronous data register.
signal UCR : std_logic_vector(7 downto 1); -- USART control register.
signal RSR : std_logic_vector(7 downto 0); -- Receiver status register.
signal TSR : std_logic_vector(7 downto 0); -- Transmitter status register.
signal UDR : std_logic_vector(7 downto 0); -- USART data register.
begin
USART_REGISTERS: process(RESETn, CLK)
begin

156
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
View File

@@ -58,52 +58,52 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_RX is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
SCR : in bit_vector(7 downto 0); -- Synchronous character.
RX_SAMPLE : buffer bit; -- Flag indicating valid shift register data.
RX_DATA : out bit_vector(7 downto 0); -- Received data.
SCR : in std_logic_vector(7 downto 0); -- Synchronous character.
RX_SAMPLE : buffer std_logic; -- Flag indicating valid shift register data.
RX_DATA : out std_logic_vector(7 downto 0); -- Received data.
RXCLK : in bit; -- Receiver clock.
SDATA_IN : in bit; -- Serial data input.
RXCLK : in std_logic; -- Receiver clock.
SDATA_IN : in std_logic; -- Serial data input.
CL : in bit_vector(1 downto 0); -- Character length.
ST : in bit_vector(1 downto 0); -- Start and stop bit configuration.
P_ENA : in bit; -- Parity enable.
P_EOn : in bit; -- Even or odd parity.
CLK_MODE : in bit; -- Clock mode configuration bit.
RE : in bit; -- Receiver enable.
FS_CLR : in bit; -- Clear the Found/Search flag for resynchronisation purpose.
SS : in bit; -- Synchronous strip enable.
UDR_READ : in bit; -- Flag indicating reading the data register.
RSR_READ : in bit; -- Flag indicating reading the receiver status register.
CL : in std_logic_vector(1 downto 0); -- Character length.
ST : in std_logic_vector(1 downto 0); -- Start and stop std_logic configuration.
P_ENA : in std_logic; -- Parity enable.
P_EOn : in std_logic; -- Even or odd parity.
CLK_MODE : in std_logic; -- Clock mode configuration std_logic.
RE : in std_logic; -- Receiver enable.
FS_CLR : in std_logic; -- Clear the Found/Search flag for resynchronisation purpose.
SS : in std_logic; -- Synchronous strip enable.
UDR_READ : in std_logic; -- Flag indicating reading the data register.
RSR_READ : in std_logic; -- Flag indicating reading the receiver status register.
M_CIP : out bit; -- Match/Character in progress.
FS_B : buffer bit; -- Find/Search or Break detect flag.
BF : out bit; -- Buffer full.
OE : out bit; -- Overrun error.
PE : out bit; -- Parity error.
FE : out bit -- Framing error.
M_CIP : out std_logic; -- Match/Character in progress.
FS_B : buffer std_logic; -- Find/Search or Break detect flag.
BF : out std_logic; -- Buffer full.
OE : out std_logic; -- Overrun error.
PE : out std_logic; -- Parity error.
FE : out std_logic -- Framing error.
);
end entity WF68901IP_USART_RX;
architecture BEHAVIOR of WF68901IP_USART_RX is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal SDATA_DIV16 : bit;
signal SDATA_IN_I : bit;
signal SDATA_EDGE : bit;
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal CLK_2_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
signal SDATA_DIV16 : std_logic;
signal SDATA_IN_I : std_logic;
signal SDATA_EDGE : std_logic;
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal CLK_STRB : std_logic;
signal CLK_2_STRB : std_logic;
signal BITCNT : unsigned (2 downto 0);
signal BREAK : boolean;
signal RDRF : bit;
signal RDRF : std_logic;
signal STARTBIT : boolean;
begin
BF <= RDRF; -- Buffer full = Receiver Data Register Full.
@@ -113,21 +113,21 @@ begin
'1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0';
-- Data multiplexer for the received data:
RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits.
"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits.
'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits.
SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits.
RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 datastd_logics.
"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 datastd_logics.
'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 datastd_logics.
SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 datastd_logics.
P_SAMPLE: process
-- This process provides the 'valid transition logic' of the originally MC68901. For further
-- details see the 'M68000 FAMILY REFERENCE MANUAL'.
variable LOW_FLT : std_logic_vector(1 downto 0);
variable HI_FLT : std_logic_vector(1 downto 0);
variable LOW_FLT : unsigned (1 downto 0);
variable HI_FLT : unsigned (1 downto 0);
variable CLK_LOCK : boolean;
variable EDGE_LOCK : boolean;
variable TIMER : std_logic_vector(2 downto 0);
variable TIMER : unsigned (2 downto 0);
variable TIMER_LOCK : boolean;
variable NEW_SDATA : bit;
variable NEW_SDATA : std_logic;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' or RE = '0' then
@@ -141,18 +141,18 @@ begin
NEW_SDATA := '1';
-- Positive or negative edge detector for the incoming data.
-- Any transition must be valid for at least three receiver clock
-- cycles. The TIMER locking inhibits detecting four receiver
-- cycles. The TIMER locking inhistd_logics detecting four receiver
-- clock cycles after a valid transition.
elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then
CLK_LOCK := true;
EDGE_LOCK := false;
HI_FLT := "00";
LOW_FLT := LOW_FLT - '1';
LOW_FLT := LOW_FLT - 1;
elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then
CLK_LOCK := true;
EDGE_LOCK := false;
LOW_FLT := "11";
HI_FLT := HI_FLT + '1';
HI_FLT := HI_FLT + 1;
elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then
EDGE_LOCK := true;
SDATA_EDGE <= '1'; -- Falling edge detected.
@@ -183,26 +183,26 @@ begin
elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then
TIMER_LOCK := true;
SDATA_DIV16 <= NEW_SDATA; -- Scan the new data.
TIMER := TIMER + '1'; -- Timing is active.
TIMER := TIMER + 1; -- Timing is active.
elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then
TIMER_LOCK := true;
TIMER := TIMER + '1'; -- Timing is active.
TIMER := TIMER + 1; -- Timing is active.
elsif RXCLK = '0' then
TIMER_LOCK := false;
end if;
end process P_SAMPLE;
P_START_BIT: process(CLK)
-- This is the valid start bit logic of the original MC68901 multi function
-- This is the valid start std_logic logic of the original MC68901 multi function
-- port's USART receiver.
variable TMP : std_logic_vector(2 downto 0);
variable TMP : unsigned (2 downto 0);
variable LOCK : boolean;
begin
if CLK = '1' and CLK' event then
if RESETn = '0' then
TMP := "000";
LOCK := true;
elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled.
elsif RE = '0' or RCV_STATE /= IDLE then -- Start std_logic logic disabled.
TMP := "000";
LOCK := true;
elsif SDATA_EDGE = '1' then
@@ -210,7 +210,7 @@ begin
LOCK := false; -- Start counting.
elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then
LOCK := true;
TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid.
TMP := TMP + 1; -- Count 8 low std_logics to declare start condition valid.
elsif RXCLK = '0' then
LOCK := false;
end if;
@@ -228,7 +228,7 @@ begin
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(4 downto 0);
variable CLK_DIVCNT : unsigned (4 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CLK_MODE = '0' then -- Divider off.
@@ -241,7 +241,7 @@ begin
else
CLK_STRB <= '0';
end if;
CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
CLK_2_STRB <= '0'; -- No 1 1/2 stop std_logics in no div by 16 mode.
elsif SDATA_EDGE = '1' then
CLK_DIVCNT := "01100"; -- Div by 16 mode.
CLK_STRB <= '0'; -- Default.
@@ -250,11 +250,11 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
CLK_STRB <= '0'; -- Default.
CLK_2_STRB <= '0'; -- Default.
if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_LOCK := true;
if CLK_DIVCNT = "01000" then
-- This strobe is asserted at half of the clock cycle.
-- It is used for the stop bit timing.
-- It is used for the stop std_logic timing.
CLK_2_STRB <= '1';
end if;
elsif CLK_DIVCNT = "00000" then
@@ -309,7 +309,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process P_M_CIP;
BREAK_DETECT: process(RESETn, CLK)
-- A break condition occurs, if there is no STOP1 bit and the
-- A break condition occurs, if there is no STOP1 std_logic and the
-- shift register contains zero data.
begin
if RESETn = '0' then
@@ -319,7 +319,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
BREAK <= false;
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then
BREAK <= true; -- Break detected (empty shift register and no stop bit).
BREAK <= true; -- Break detected (empty shift register and no stop std_logic).
elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then
BREAK <= false; -- UPDATE.
elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
@@ -332,7 +332,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
P_FS_B: process(RESETn, CLK)
-- In the synchronous mode, this process provides the flag detecting the synchronous
-- character. In the asynchronous mode, the flag indicates a break condition.
variable FS_B_I : bit;
variable FS_B_I : std_logic;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
@@ -378,9 +378,9 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode.
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode.
BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1').
BITCNT <= BITCNT + 1; -- Count, if matched data found (FS_B = '1').
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
@@ -403,7 +403,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process BUFFER_FULL;
OVERRUN: process(RESETn, CLK)
variable OE_I : bit;
variable OE_I : std_logic;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
@@ -438,8 +438,8 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable P_ERR : bit;
variable PAR_TMP : std_logic;
variable P_ERR : std_logic;
begin
if RESETn = '0' then
PE <= '0';
@@ -472,8 +472,8 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
FRAME_ERR: process(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
-- during stop std_logic 1 and stop std_logic 2.
variable FE_I: std_logic;
begin
if RESETn = '0' then
FE_I := '0';
@@ -518,15 +518,15 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
if ST = "00" then
RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode.
elsif SDATA_IN_I = '0' and CLK_MODE = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
RCV_NEXT_STATE <= SAMPLE; -- Startstd_logic detected in div by 1 mode.
elsif STARTBIT = true and CLK_MODE = '1' then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
RCV_NEXT_STATE <= WAIT_START; -- Startstd_logic detected in div by 16 mode.
else
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
RCV_NEXT_STATE <= IDLE; -- No startstd_logic; sleep well :-)
end if;
when WAIT_START =>
-- This state delays the sample process by one CLK_STRB pulse
-- to eliminate the start bit.
-- to eliminate the start std_logic.
if CLK_STRB = '1' then
RCV_NEXT_STATE <= SAMPLE;
else
@@ -535,14 +535,14 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
when SAMPLE =>
if CLK_STRB = '1' then
if CL = "11" and BITCNT < "100" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data std_logics.
elsif CL = "10" and BITCNT < "101" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data std_logics.
elsif CL = "01" and BITCNT < "110" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data std_logics.
elsif CL = "00" and BITCNT < "111" then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits).
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data std_logics.
elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop std_logics).
RCV_NEXT_STATE <= IDLE; -- No parity check enabled.
elsif P_ENA = '0' then
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
@@ -554,7 +554,7 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end if;
when PARITY =>
if CLK_STRB = '1' then
if ST = "00" then -- Synchronous mode (no stop bits).
if ST = "00" then -- Synchronous mode (no stop std_logics).
RCV_NEXT_STATE <= IDLE;
else
RCV_NEXT_STATE <= STOP1;
@@ -564,21 +564,21 @@ CLK_DIVCNT := "01100"; -- Div by 16 mode.
end if;
when STOP1 =>
if CLK_STRB = '1' then
if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data.
if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop std_logic after non zero data.
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif ST = "11" or ST = "10" then
RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected.
RCV_NEXT_STATE <= STOP2; -- More than one stop std_logics selected.
else
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
RCV_NEXT_STATE <= SYNC; -- One stop std_logic selected.
end if;
else
RCV_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_2_STRB = '1' and ST = "10" then
RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected.
RCV_NEXT_STATE <= SYNC; -- One and a half stop std_logics selected.
elsif CLK_STRB = '1' then
RCV_NEXT_STATE <= SYNC; -- Two stop bits selected.
RCV_NEXT_STATE <= SYNC; -- Two stop std_logics selected.
else
RCV_NEXT_STATE <= STOP2;
end if;

106
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_top.vhd
View File

@@ -58,76 +58,76 @@ use work.wf68901ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_TOP is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_OUT_EN : out std_logic;
-- Serial I/O control:
RC : in bit; -- Receiver clock.
TC : in bit; -- Transmitter clock.
SI : in bit; -- Serial input.
SO : out bit; -- Serial output.
SO_EN : out bit; -- Serial output enable.
RC : in std_logic; -- Receiver clock.
TC : in std_logic; -- Transmitter clock.
SI : in std_logic; -- Serial input.
SO : out std_logic; -- Serial output.
SO_EN : out std_logic; -- Serial output enable.
-- Interrupt channels:
RX_ERR_INT : out bit; -- Receiver errors.
RX_BUFF_INT : out bit; -- Receiver buffer full.
TX_ERR_INT : out bit; -- Transmitter errors.
TX_BUFF_INT : out bit; -- Transmitter buffer empty.
RX_ERR_INT : out std_logic; -- Receiver errors.
RX_BUFF_INT : out std_logic; -- Receiver buffer full.
TX_ERR_INT : out std_logic; -- Transmitter errors.
TX_BUFF_INT : out std_logic; -- Transmitter buffer empty.
-- DMA control:
RRn : out bit;
TRn : out bit
RRn : out std_logic;
TRn : out std_logic
);
end entity WF68901IP_USART_TOP;
architecture STRUCTURE of WF68901IP_USART_TOP is
signal BF_I : bit;
signal BE_I : bit;
signal FE_I : bit;
signal OE_I : bit;
signal UE_I : bit;
signal PE_I : bit;
signal LOOPBACK_I : bit;
signal SD_LEVEL_I : bit;
signal SDATA_IN_I : bit;
signal SDATA_OUT_I : bit;
signal RXCLK_I : bit;
signal CLK_MODE_I : bit;
signal SCR_I : bit_vector(7 downto 0);
signal RX_SAMPLE_I : bit;
signal RX_DATA_I : bit_vector(7 downto 0);
signal TX_DATA_I : bit_vector(7 downto 0);
signal CL_I : bit_vector(1 downto 0);
signal ST_I : bit_vector(1 downto 0);
signal P_ENA_I : bit;
signal P_EOn_I : bit;
signal RE_I : bit;
signal TE_I : bit;
signal FS_CLR_I : bit;
signal SS_I : bit;
signal M_CIP_I : bit;
signal FS_B_I : bit;
signal BR_I : bit;
signal UDR_READ_I : bit;
signal UDR_WRITE_I : bit;
signal RSR_READ_I : bit;
signal TSR_READ_I : bit;
signal TX_END_I : bit;
signal BF_I : std_logic;
signal BE_I : std_logic;
signal FE_I : std_logic;
signal OE_I : std_logic;
signal UE_I : std_logic;
signal PE_I : std_logic;
signal LOOPBACK_I : std_logic;
signal SD_LEVEL_I : std_logic;
signal SDATA_IN_I : std_logic;
signal SDATA_OUT_I : std_logic;
signal RXCLK_I : std_logic;
signal CLK_MODE_I : std_logic;
signal SCR_I : std_logic_vector(7 downto 0);
signal RX_SAMPLE_I : std_logic;
signal RX_DATA_I : std_logic_vector(7 downto 0);
signal TX_DATA_I : std_logic_vector(7 downto 0);
signal CL_I : std_logic_vector(1 downto 0);
signal ST_I : std_logic_vector(1 downto 0);
signal P_ENA_I : std_logic;
signal P_EOn_I : std_logic;
signal RE_I : std_logic;
signal TE_I : std_logic;
signal FS_CLR_I : std_logic;
signal SS_I : std_logic;
signal M_CIP_I : std_logic;
signal FS_B_I : std_logic;
signal BR_I : std_logic;
signal UDR_READ_I : std_logic;
signal UDR_WRITE_I : std_logic;
signal RSR_READ_I : std_logic;
signal TSR_READ_I : std_logic;
signal TX_END_I : std_logic;
begin
SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I;
-- Loopback mode:

98
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
View File

@@ -57,45 +57,45 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF68901IP_USART_TX is
port (
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
SCR : in bit_vector(7 downto 0); -- Synchronous character.
TX_DATA : in bit_vector(7 downto 0); -- Normal data.
SCR : in std_logic_vector(7 downto 0); -- Synchronous character.
TX_DATA : in std_logic_vector(7 downto 0); -- Normal data.
SDATA_OUT : out bit; -- Serial data output.
TXCLK : in bit; -- Transmitter clock.
SDATA_OUT : out std_logic; -- Serial data output.
TXCLK : in std_logic; -- Transmitter clock.
CL : in bit_vector(1 downto 0); -- Character length.
ST : in bit_vector(1 downto 0); -- Start and stop bit configuration.
TE : in bit; -- Transmitter enable.
BR : in bit; -- BREAK character send enable (all '0' without stop bit).
P_ENA : in bit; -- Parity enable.
P_EOn : in bit; -- Even or odd parity.
UDR_WRITE : in bit; -- Flag indicating writing the data register.
TSR_READ : in bit; -- Flag indicating reading the transmitter status register.
CLK_MODE : in bit; -- Transmitter clock mode.
CL : in std_logic_vector(1 downto 0); -- Character length.
ST : in std_logic_vector(1 downto 0); -- Start and stop std_logic configuration.
TE : in std_logic; -- Transmitter enable.
BR : in std_logic; -- BREAK character send enable (all '0' without stop std_logic).
P_ENA : in std_logic; -- Parity enable.
P_EOn : in std_logic; -- Even or odd parity.
UDR_WRITE : in std_logic; -- Flag indicating writing the data register.
TSR_READ : in std_logic; -- Flag indicating reading the transmitter status register.
CLK_MODE : in std_logic; -- Transmitter clock mode.
TX_END : out bit; -- End of transmission flag.
UE : out bit; -- Underrun Flag.
BE : out bit -- Buffer empty flag.
TX_END : out std_logic; -- End of transmission flag.
UE : out std_logic; -- Underrun Flag.
BE : out std_logic -- Buffer empty flag.
);
end entity WF68901IP_USART_TX;
architecture BEHAVIOR of WF68901IP_USART_TX is
type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
signal TR_STATE, TR_NEXT_STATE : TR_STATES;
signal CLK_STRB : bit;
signal CLK_2_STRB : bit;
signal SHIFT_REG : bit_vector(7 downto 0);
signal BITCNT : std_logic_vector(2 downto 0);
signal PARITY_I : bit;
signal TDRE : bit;
signal BREAK : bit;
signal CLK_STRB : std_logic;
signal CLK_2_STRB : std_logic;
signal SHIFT_REG : std_logic_vector(7 downto 0);
signal BITCNT : unsigned (2 downto 0);
signal PARITY_I : std_logic;
signal TDRE : std_logic;
signal BREAK : std_logic;
begin
BE <= TDRE; -- Buffer empty flag.
@@ -140,7 +140,7 @@ begin
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(4 downto 0);
variable CLK_DIVCNT : unsigned (4 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CLK_MODE = '0' then -- Divider off.
@@ -153,7 +153,7 @@ begin
else
CLK_STRB <= '0';
end if;
CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
CLK_2_STRB <= '0'; -- No 1 1/2 stop std_logics in no div by 16 mode.
elsif TR_STATE = IDLE then
CLK_DIVCNT := "10000"; -- Div by 16 mode.
CLK_STRB <= '0';
@@ -162,11 +162,11 @@ begin
CLK_2_STRB <= '0'; -- Default.
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_DIVCNT := CLK_DIVCNT - 1;
CLK_LOCK := true;
if CLK_DIVCNT = "01000" then
-- This strobe is asserted at half of the clock cycle.
-- It is used for the stop bit timing.
-- It is used for the stop std_logic timing.
CLK_2_STRB <= '1';
end if;
elsif CLK_DIVCNT = "00000" then
@@ -197,10 +197,10 @@ begin
elsif TR_STATE = LOAD_SHFT then
-- Load 'normal' data if there is no break condition:
case CL is
when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits.
when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits.
when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits.
when "00" => SHIFT_REG <= TX_DATA; -- 8 databits.
when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 datastd_logics.
when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 datastd_logics.
when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 datastd_logics.
when "00" => SHIFT_REG <= TX_DATA; -- 8 datastd_logics.
end case;
elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
@@ -209,11 +209,11 @@ begin
end process SHIFTREG;
P_BITCNT: process
-- Counter for the data bits transmitted.
-- Counter for the data std_logics transmitted.
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
BITCNT <= BITCNT + 1;
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
@@ -274,7 +274,7 @@ begin
end process P_TX_END;
PARITY_GEN: process
variable PAR_TMP : bit;
variable PAR_TMP : std_logic;
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = START then -- Calculate the parity during the start phase.
@@ -325,7 +325,7 @@ begin
end if;
when LOAD_SHFT =>
TR_NEXT_STATE <= START;
when START => -- Send the start bit.
when START => -- Send the start std_logic.
if CLK_STRB = '1' then
TR_NEXT_STATE <= SHIFTOUT;
else
@@ -334,15 +334,15 @@ begin
when SHIFTOUT =>
if CLK_STRB = '1' then
if BITCNT < "100" and CL = "11" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data std_logics.
elsif BITCNT < "101" and CL = "10" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data std_logics.
elsif BITCNT < "110" and CL = "01" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data std_logics.
elsif BITCNT < "111" and CL = "00" then
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data std_logics.
elsif P_ENA = '0' and BREAK = '1' then
TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits.
TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop std_logics.
elsif P_ENA = '0' and ST = "00" then
TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled.
elsif P_ENA = '0' then
@@ -355,9 +355,9 @@ begin
end if;
when PARITY =>
if CLK_STRB = '1' then
if ST = "00" then -- Synchronous mode (no stop bits).
if ST = "00" then -- Synchronous mode (no stop std_logics).
TR_NEXT_STATE <= IDLE;
elsif BREAK = '1' then -- No stop bits during break condition.
elsif BREAK = '1' then -- No stop std_logics during break condition.
TR_NEXT_STATE <= IDLE;
else
TR_NEXT_STATE <= STOP1;
@@ -367,17 +367,17 @@ begin
end if;
when STOP1 =>
if CLK_STRB = '1' and (ST = "11" or ST = "10") then
TR_NEXT_STATE <= STOP2; -- More than one stop bits selected.
TR_NEXT_STATE <= STOP2; -- More than one stop std_logics selected.
elsif CLK_STRB = '1' then
TR_NEXT_STATE <= IDLE; -- One stop bits selected.
TR_NEXT_STATE <= IDLE; -- One stop std_logics selected.
else
TR_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_2_STRB = '1' and ST = "10" then
TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected.
TR_NEXT_STATE <= IDLE; -- One and a half stop std_logics selected.
elsif CLK_STRB = '1' then
TR_NEXT_STATE <= IDLE; -- Two stop bits detected.
TR_NEXT_STATE <= IDLE; -- Two stop std_logics detected.
else
TR_NEXT_STATE <= STOP2;
end if;