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removed all dependencies to obsolete ieee.std_logic_arith and ieee.std_logic_unsigned in favour of ieee.numeric_std. There are a few things that still need to be fixed because of that, however.

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This commit is contained in:
Markus Fröschle
2014-08-04 17:23:47 +00:00
parent d96e0b82bc
commit 4c2be14e28
42 changed files with 2695 additions and 2662 deletions
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48
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_am_detector.vhd
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@@ -22,9 +22,9 @@
---- 2. every second pulse is a data. ----
---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ----
---- 4. a logic 0 is represented by one clock pulse and no data pulse. ----
---- 5. Hence there are a maximum of two pulses per data bit. ----
---- 6. one clock and one data pulse come together in one bit cell. ----
---- 7. the duration of a bit cell in FM is 4 microseconds. ----
---- 5. Hence there are a maximum of two pulses per data std_logic. ----
---- 6. one clock and one data pulse come together in one std_logic cell. ----
---- 7. the duration of a std_logic cell in FM is 4 microseconds. ----
---- 8. an ID address mark is represented as data FE with clock C7. ----
---- 9. a DATA address mark is represented as data FB with clock C7. ----
---- Examples: ----
@@ -52,11 +52,11 @@
---- 4. a logic 0 is represented by a clock pulse and no data pulse if ----
---- following a 0. ----
---- 5. a logic 0 is represented by no pulse if following a 1. ----
---- 6. Hence there are a maximum of one pulse per data bit. ----
---- 7. one clock and one data pulse form together one bit cell. ----
---- 8. the duration of a bit cell in MFM is 2 microseconds. ----
---- 6. Hence there are a maximum of one pulse per data std_logic. ----
---- 7. one clock and one data pulse form together one std_logic cell. ----
---- 8. the duration of a std_logic cell in MFM is 2 microseconds. ----
---- 9. an address mark sync is represented as data A1 with missing clock ----
---- pulse between bit 4 and 5. ----
---- pulse between std_logic 4 and 5. ----
---- Examples: ----
---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows: ----
---- 0101010101010100 this is the ID address mark. ----
@@ -66,11 +66,11 @@
---- 0101010101001010 this is the deleted DATA address mark. ----
---- the A1 data 1 0 1 0 0 0 0 1 is represented as follows: ----
---- 0100010010101001 ----
---- with the missing clock pulse between bits 4 and 5 there results: ----
---- with the missing clock pulse between std_logics 4 and 5 there results: ----
---- results: 0100010010001001 this is the address mark sync. ----
---- ----
---- Both MFM and FM are during read and write shifted with most significant ----
---- bit (MSB) first. During the FM address marks are written without a ----
---- std_logic (MSB) first. During the FM address marks are written without a ----
---- SYNC pulse the MFM coded data requires a synchronisation (A1 with ----
---- missing clock pulse because at the beginning of the data stream it is ----
---- not defined wether a clock pulse or a data pulse appears first. In FM ----
@@ -122,34 +122,34 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_AM_DETECTOR is
port(
-- System control
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Controls:
DDEn : in bit;
DDEn : in std_logic;
-- Serial data and clock:
DATA : in bit;
DATA_STRB : in bit;
DATA : in std_logic;
DATA_STRB : in std_logic;
-- Address mark detector:
ID_AM : out bit; -- ID address mark strobe.
DATA_AM : out bit; -- Data address mark strobe.
DDATA_AM : out bit -- Deleted data address mark strobe.
ID_AM : out std_logic; -- ID address mark strobe.
DATA_AM : out std_logic; -- Data address mark strobe.
DDATA_AM : out std_logic -- Deleted data address mark strobe.
);
end WF1772IP_AM_DETECTOR;
architecture BEHAVIOR of WF1772IP_AM_DETECTOR is
signal SHIFT : bit_vector(15 downto 0);
signal SHIFT : std_logic_vector(15 downto 0);
signal SYNC : boolean;
signal ID_AM_I : bit;
signal DATA_AM_I : bit;
signal DDATA_AM_I : bit;
signal ID_AM_I : std_logic;
signal DATA_AM_I : std_logic;
signal DDATA_AM_I : std_logic;
begin
SHIFTREG: process(RESETn, CLK)
begin
@@ -176,7 +176,7 @@ begin
-- SYNC goes low again. This mechanism is used to detect the correct address
-- marks in the MFM data stream during the type III read track command.
-- This is an improvement over the original WD1772 chip.
variable TMP : std_logic_vector(4 downto 0);
variable TMP : unsigned (4 downto 0);
begin
if RESETn = '0' then
TMP := "00000";
@@ -184,7 +184,7 @@ begin
if SHIFT = "0100010010001001" and DDEn = '0' then
TMP := "10001"; -- Load sync time counter.
elsif DATA_STRB = '1' and TMP > "00000" then
TMP := TMP - '1';
TMP := TMP - 1;
end if;
end if;
case TMP is

162
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd
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@@ -71,85 +71,85 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_CONTROL is
port(
-- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Chip control signals:
A1, A0 : in bit;
RWn : in bit;
CSn : in bit;
DDEn : in bit;
A1, A0 : in std_logic;
RWn : in std_logic;
CSn : in std_logic;
DDEn : in std_logic;
-- Registers:
DR : in bit_vector(7 downto 0); -- Data register.
DR : in std_logic_vector(7 downto 0); -- Data register.
CMD : in std_logic_vector(7 downto 0); -- Command register.
DSR : in std_logic_vector(7 downto 0); -- Shift register.
TR : in std_logic_vector(7 downto 0); -- Track register.
SR : in std_logic_vector(7 downto 0); -- Sector register.
-- Status flags:
MO : buffer bit; -- Motor on status flag.
WR_PR : out bit; -- Write protect status flag.
SPINUP_RECTYPE : out bit; -- Spin up / record type status flag.
SEEK_RNF : out bit; -- Seek error / record not found status flag.
CRC_ERRFLAG : out bit; -- CRC status flag.
LOST_DATA_TR00 : out bit; -- Status flag indicates lost data or track 00 position.
DRQ : out bit; -- Data request.
DRQ_IPn : out bit; -- Data request status flag.
BUSY : buffer bit; -- BUSY status flag.
MO : buffer std_logic; -- Motor on status flag.
WR_PR : out std_logic; -- Write protect status flag.
SPINUP_RECTYPE : out std_logic; -- Spin up / record type status flag.
SEEK_RNF : out std_logic; -- Seek error / record not found status flag.
CRC_ERRFLAG : out std_logic; -- CRC status flag.
LOST_DATA_TR00 : out std_logic; -- Status flag indicates lost data or track 00 position.
DRQ : out std_logic; -- Data request.
DRQ_IPn : out std_logic; -- Data request status flag.
BUSY : buffer std_logic; -- BUSY status flag.
-- Address mark detector controls:
AM_2_DISK : out bit; -- Enables / disables the address mark detector.
ID_AM : in bit; -- Address mark of the ID field
DATA_AM : in bit; -- Address mark of the data field
DDATA_AM : in bit; -- Address mark of a deleted data field
AM_2_DISK : out std_logic; -- Enables / disables the address mark detector.
ID_AM : in std_logic; -- Address mark of the ID field
DATA_AM : in std_logic; -- Address mark of the data field
DDATA_AM : in std_logic; -- Address mark of a deleted data field
-- CRC unit controls:
CRC_ERR : in bit; -- CRC decoder's error.
CRC_PRES : out bit; -- Preset CRC during write operations.
CRC_ERR : in std_logic; -- CRC decoder's error.
CRC_PRES : out std_logic; -- Preset CRC during write operations.
-- Track register controls:
TR_PRES : out bit; -- Set x"FF".
TR_CLR : out bit; -- Clear.
TR_INC : out bit; -- Increment.
TR_DEC : out bit; -- Decrement.
TR_PRES : out std_logic; -- Set x"FF".
TR_CLR : out std_logic; -- Clear.
TR_INC : out std_logic; -- Increment.
TR_DEC : out std_logic; -- Decrement.
-- Sector register control:
SR_LOAD : out bit; -- Load.
SR_INC : out bit; -- Increment.
SR_LOAD : out std_logic; -- Load.
SR_INC : out std_logic; -- Increment.
-- The TRACK_NR is required during the type III command
-- 'Read Address'. TRACK_NR is the content of the TRACKMEM.
TRACK_NR : out std_logic_vector(7 downto 0);
-- DATA register control:
DR_CLR : out bit; -- Clear.
DR_LOAD : out bit; -- LOAD.
DR_CLR : out std_logic; -- Clear.
DR_LOAD : out std_logic; -- LOAD.
-- Shift register control:
SHFT_LOAD_ND : out bit; -- Load normal data.
SHFT_LOAD_SD : out bit; -- Load special data.
SHFT_LOAD_ND : out std_logic; -- Load normal data.
SHFT_LOAD_SD : out std_logic; -- Load special data.
-- Transceiver controls:
CRC_2_DISK : out bit; -- Cause the Transceiver to write out CRC data.
DSR_2_DISK : out bit; -- Cause the Transceiver to write normal data.
FF_2_DISK : out bit; -- Cause the Transceiver to write x"FF" bytes.
PRECOMP_EN : out bit; -- Enables the write precompensation.
CRC_2_DISK : out std_logic; -- Cause the Transceiver to write out CRC data.
DSR_2_DISK : out std_logic; -- Cause the Transceiver to write normal data.
FF_2_DISK : out std_logic; -- Cause the Transceiver to write x"FF" bytes.
PRECOMP_EN : out std_logic; -- Enables the write precompensation.
-- Miscellaneous Controls:
DATA_STRB : in bit; -- Data strobe (read and write operation)
WPRTn : in bit; -- Write protect flag
IPn : in bit; -- Index pulse flag
TRACK00n : in bit; -- Track zero flag
DISK_RWn : out bit; -- This signal reflects the data direction.
DIRC : out bit; -- Step direction control.
STEP : out bit; -- Step pulse.
WG : out bit; -- Write gate control.
INTRQ : out bit -- Interrupt request flag.
DATA_STRB : in std_logic; -- Data strobe (read and write operation)
WPRTn : in std_logic; -- Write protect flag
IPn : in std_logic; -- Index pulse flag
TRACK00n : in std_logic; -- Track zero flag
DISK_RWn : out std_logic; -- This signal reflects the data direction.
DIRC : out std_logic; -- Step direction control.
STEP : out std_logic; -- Step pulse.
WG : out std_logic; -- Write gate control.
INTRQ : out std_logic -- Interrupt request flag.
);
end WF1772IP_CONTROL;
@@ -176,17 +176,17 @@ architecture BEHAVIOR of WF1772IP_CONTROL is
signal CMD_WR : boolean;
signal STAT_RD : boolean;
signal DELAY : boolean;
signal DRQ_I : bit;
signal DRQ_I : std_logic;
signal INDEX_CNT : boolean;
signal DIR : bit;
signal INDEX_MARK : bit;
signal DIR : std_logic;
signal INDEX_MARK : std_logic;
signal STEP_TRAP : boolean;
signal TYPE_IV_BREAK : boolean;
signal BYTE_RDY : boolean;
signal SECT_LEN : std_logic_vector(10 downto 0);
signal SECT_LEN : unsigned (10 downto 0);
signal TRACKMEM : std_logic_vector(7 downto 0);
signal T3_TRADR : boolean;
signal T3_DATATYPE : bit_vector(7 downto 0);
signal T3_DATATYPE : std_logic_vector(7 downto 0);
begin
-- The Forced interrupt stops any command at the end of an internal micro instruction.
-- Forced interrupt waits until ALU operations in progress are complete (CRC calculations,
@@ -720,7 +720,7 @@ begin
-- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows:
-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.
-- In T1_VERIFY_DELAY there is a delay of 30ms.
variable DELCNT : std_logic_vector(19 downto 0);
variable DELCNT : unsigned (19 downto 0);
begin
if RESETn = '0' then
DELCNT := (others => '0');
@@ -734,21 +734,21 @@ begin
case CMD_STATE is
-- Time delays work on CLK edges.
when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY =>
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
-- Bit count delays work on data strobes.
-- Read from disk operation:
when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT |
T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM | T2_FIRSTBYTE |
T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC =>
if DATA_STRB = '1' then
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
end if;
-- Write to disk operation:
when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN |
T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST |
T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST =>
if DATA_STRB = '1' then
DELCNT := DELCNT + '1';
DELCNT := DELCNT + 1;
end if;
when others =>
DELCNT := (others => '0'); -- Clear the delay counter if not used.
@@ -786,7 +786,7 @@ begin
when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE |
T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR =>
case DELCNT is
when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times.
when x"00008" => DELAY <= true; -- The delay in this case is 8 std_logic times.
when others => DELAY <= false;
end case;
when T1_SCAN_CRC =>
@@ -795,9 +795,9 @@ begin
when others => DELAY <= false;
end case;
when T2_WR_AM =>
if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode).
if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark std_logics (FM mode).
DELAY <= true;
elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode).
elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark std_logics (MFM mode).
DELAY <= true;
else
DELAY <= false;
@@ -811,9 +811,9 @@ begin
DELAY <= false;
end if;
when T2_WR_LEADIN =>
if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode.
if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero std_logics in FM mode.
DELAY <= true;
elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode.
elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero std_logics in MFM mode.
DELAY <= true;
else
DELAY <= false;
@@ -853,16 +853,16 @@ begin
when others => DELAY <= false;
end case;
when T3_WR_DATA =>
if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits.
if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC std_logics.
DELAY <= true;
elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits.
elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data std_logics.
DELAY <= true;
else
DELAY <= false;
end if;
when T3_SHIFT =>
case DELCNT is
when x"00001" => DELAY <= true; -- Scan just one data bit.
when x"00001" => DELAY <= true; -- Scan just one data std_logic.
when others => DELAY <= false;
end case;
when others =>
@@ -876,8 +876,8 @@ begin
-- It is achieved by counting the index pulses of the disk. This encounters problems,
-- if the disk is not inserted. For this reason there is additionally to the index counter
-- a timeout which is active if there are no index pulses.
variable CNT : std_logic_vector(3 downto 0);
variable TIMEOUT : std_logic_vector(27 downto 0);
variable CNT : unsigned (3 downto 0);
variable TIMEOUT : unsigned (27 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
@@ -890,14 +890,14 @@ begin
when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC |
T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM =>
if IPn = '0' and LOCK = false then -- Count the index pulses.
CNT := CNT + '1';
CNT := CNT + 1;
LOCK := true;
elsif IPn = '1' then
LOCK := false;
end if;
--
if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s.
TIMEOUT := TIMEOUT + '1';
TIMEOUT := TIMEOUT + 1;
end if;
when others =>
CNT := x"0";
@@ -959,7 +959,7 @@ begin
-- This process counts the bytes read in the type III read address
-- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2,
-- T3_SET_DRQ_2 and T3_CHECK_RD.
variable CNT : std_logic_vector(2 downto 0);
variable CNT : unsigned (2 downto 0);
begin
if RESETn = '0' then
CNT := "000";
@@ -968,7 +968,7 @@ begin
when T3_VERIFY_AM =>
CNT := "000"; -- Clear the counter right befor the count operation.
when T3_SET_DRQ_2 =>
CNT := CNT + '1'; -- Increment after each read cycle.
CNT := CNT + 1; -- Increment after each read cycle.
when others =>
null;
end case;
@@ -981,17 +981,17 @@ begin
BYTEASMBLY: process(RESETn, CLK)
-- This process controls the condition in the CMD_STATE T3_CHECK_DR.
-- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted.
-- Therefore the std_logics shifted into the DSR in command state T3_SHIFT are counted.
-- The count condition is entering the command state T3_CHECK_INDEX_3. The clear
-- condition is either the command state IDLE or the command state T3_CHECK_DR.
variable CNT : std_logic_vector(3 downto 0);
variable CNT : unsigned (3 downto 0);
begin
if RESETn = '0' then
CNT := x"0";
elsif CLK = '1' and CLK' event then
case CMD_STATE is
when IDLE => CNT := x"0";
when T3_CHECK_INDEX_3 => CNT := CNT + '1';
when T3_CHECK_INDEX_3 => CNT := CNT + 1;
when T3_CHECK_DR => CNT := (others => '0');
when others => null;
end case;
@@ -1037,7 +1037,7 @@ begin
when others =>
null;
end case;
-- The data request bit is also cleared by reading or writing the
-- The data request std_logic is also cleared by reading or writing the
-- data register (direct memory access operation).
if (DATA_RD = true or DATA_WR = true) then
DRQ_I <= '0';
@@ -1144,7 +1144,7 @@ begin
end process P_INTRQ;
P_LOST_DATA_TR00: process(RESETn, CLK)
-- Logic for the status bit number 2:
-- Logic for the status std_logic number 2:
-- The TRACK00 flag is used to detect wether a floppy disk drive
-- is connected or not.
begin
@@ -1174,7 +1174,7 @@ begin
end process P_LOST_DATA_TR00;
MOTORSWITCH: process(RESETn, CLK)
variable INDEXCNT : std_logic_vector(3 downto 0);
variable INDEXCNT : unsigned (3 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
@@ -1186,7 +1186,7 @@ begin
INDEXCNT := x"9"; -- Initialise the index counter.
LOCK := false;
elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then
INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state.
INDEXCNT := INDEXCNT - 1; -- Count the index pulses in the IDLE state.
LOCK := true;
elsif IPn = '1' then
LOCK := false;
@@ -1255,7 +1255,7 @@ begin
-- If after 255 stepping pulses no TRACK00n was not detected, the
-- RESTORE command is terminated and the interrupt request and the
-- seek error are set.
variable STEP_CNT : std_logic_vector(7 downto 0);
variable STEP_CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
STEP_CNT := (others => '0');
@@ -1265,7 +1265,7 @@ begin
elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command.
STEP_CNT := x"00";
elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then
STEP_CNT := STEP_CNT + '1';
STEP_CNT := STEP_CNT + 1;
end if;
end if;
--
@@ -1278,7 +1278,7 @@ begin
STEPPULSE: process(RESETn, CLK)
-- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us.
-- in FM mode This process is responsible to provide the correct pulse lengths.
variable CNT : std_logic_vector(7 downto 0);
variable CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
CNT := (others => '0');
@@ -1289,7 +1289,7 @@ begin
when '0' => CNT := x"40"; --Start counter for MFM step pulse.
end case;
elsif CNT > x"00" then
CNT := CNT -1; -- Count 63 or 127 CLK cycles ...
CNT := CNT - 1; -- Count 63 or 127 CLK cycles ...
end if;
case CNT is
when x"00" => STEP <= '0';
@@ -1339,7 +1339,7 @@ begin
when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -.
end case;
when T2_LOAD_DATA | T2_LOAD_SHFT =>
SECT_LEN <= SECT_LEN - '1';
SECT_LEN <= SECT_LEN - 1;
when others =>
null;
end case;

28
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
View File

@@ -84,33 +84,33 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_CRC_LOGIC is
port(
-- System control
CLK : in bit;
RESETn : in bit;
DISK_RWn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
DISK_RWn : in std_logic;
-- Preset controls:
DDEn : in bit;
ID_AM : in bit;
DDEn : in std_logic;
ID_AM : in std_logic;
DATA_AM : in Bit;
DDATA_AM : in Bit;
-- CRC unit:
SD : in bit; -- Serial data input.
CRC_STRB : in bit; -- Data strobe.
CRC_2_DISK : in bit; -- Forces the unit to flush the CRC remainder.
CRC_PRES : in bit; -- Presets the CRC unit during write to disk.
CRC_SDOUT : out bit; -- Serial data output.
CRC_ERR : out bit -- Indicates CRC error.
SD : in std_logic; -- Serial data input.
CRC_STRB : in std_logic; -- Data strobe.
CRC_2_DISK : in std_logic; -- Forces the unit to flush the CRC remainder.
CRC_PRES : in std_logic; -- Presets the CRC unit during write to disk.
CRC_SDOUT : out std_logic; -- Serial data output.
CRC_ERR : out std_logic -- Indicates CRC error.
);
end WF1772IP_CRC_LOGIC;
architecture BEHAVIOR of WF1772IP_CRC_LOGIC is
signal CRC_SHIFT : bit_vector(15 downto 0);
signal CRC_SHIFT : std_logic_vector(15 downto 0);
begin
P_CRC: process
-- The shift register is initialised with appropriate values in HD or DD mode.
@@ -148,7 +148,7 @@ begin
-- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC
-- verification. In this operating condition the ID or the data field is compared
-- against the CRC checksum. if there are no errors, the shift register's value is
-- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the
-- x"0000" after the last std_logic of the checksum is shifted in. In write to disk mode the
-- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the
-- ID or data field.
CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) &

80
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
View File

@@ -80,7 +80,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_DIGITAL_PLL is
generic(
@@ -94,37 +94,37 @@ entity WF1772IP_DIGITAL_PLL is
-- may not drop below zero.
TOP : integer range 0 to 255 := 152; -- +18.0%
BOTTOM : integer range 0 to 255 := 104; -- -18.0%
PHASE_CORR : integer range 0 to 128 := 75
PHASE_CORR : unsigned (7 downto 0) := to_unsigned(75, 8)
);
port(
-- System control
CLK : in bit; -- 16MHz clock.
RESETn : in bit;
CLK : in std_logic; -- 16MHz clock.
RESETn : in std_logic;
-- Controls
DDEn : in bit; -- Double density enable.
HDTYPE : in bit; -- This control is '1' when HD disks are inserted.
DISK_RWn : in bit; -- Read write control.
DDEn : in std_logic; -- Double density enable.
HDTYPE : in std_logic; -- This control is '1' when HD disks are inserted.
DISK_RWn : in std_logic; -- Read write control.
-- Data and clock lines
RDn : in bit; -- Read signal from the disk.
PLL_D : out bit; -- Synchronous read signal.
PLL_DSTRB : out bit -- Read strobe.
RDn : in std_logic; -- Read signal from the disk.
PLL_D : out std_logic; -- Synchronous read signal.
PLL_DSTRB : out std_logic -- Read strobe.
);
end WF1772IP_DIGITAL_PLL;
architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is
signal RD_In : bit;
signal UP, DOWN : bit;
signal PHASE_DECREASE : bit;
signal PHASE_INCREASE : bit;
signal HI_STOP, LOW_STOP : bit;
signal PER_CNT : std_logic_vector(7 downto 0);
signal ADDER_IN : std_logic_vector(7 downto 0);
signal ADDER_MSBs : bit_vector(2 downto 0);
signal RD_PULSE : bit;
signal ROLL_OVER : bit;
signal HISTORY_REG : bit_vector(1 downto 0);
signal RD_In : std_logic;
signal UP, DOWN : std_logic;
signal PHASE_DECREASE : std_logic;
signal PHASE_INCREASE : std_logic;
signal HI_STOP, LOW_STOP : std_logic;
signal PER_CNT : unsigned (7 downto 0);
signal ADDER_IN : unsigned (7 downto 0);
signal ADDER_MSBs : std_logic_vector(2 downto 0);
signal RD_PULSE : std_logic;
signal ROLL_OVER : std_logic;
signal HISTORY_REG : std_logic_vector(1 downto 0);
signal ERROR_HISTORY : integer range 0 to 2;
begin
INPORT: process
@@ -172,9 +172,9 @@ begin
PER_CNT <= "10000000"; -- Initial value is 128.
elsif CLK = '1' and CLK' event then
if UP = '1' then
PER_CNT <= PER_CNT + '1';
PER_CNT <= PER_CNT + 1;
elsif DOWN = '1' then
PER_CNT <= PER_CNT - '1';
PER_CNT <= PER_CNT - 1;
end if;
end if;
end process PERIOD_CNT;
@@ -186,9 +186,9 @@ begin
-- of the PLL in read from disk mode. It should be a good solution concer-
-- ning alternative read write cycles.
"10000000" when DISK_RWn = '0' else -- Nominal value for write to disk.
PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags.
PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds.
PER_CNT; -- No phase correction;
(PER_CNT + PHASE_CORR) when PHASE_INCREASE = '1' else -- Phase lags.
(PER_CNT - PHASE_CORR) when PHASE_DECREASE = '1' else -- Phase leeds.
(PER_CNT); -- No phase correction;
ADDER: process(RESETn, CLK, DDEn, HDTYPE)
-- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock.
@@ -200,7 +200,8 @@ begin
-- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0.
-- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1.
-- The given times are the half of a data period time in MFM or FM.
variable ADDER_DATA : std_logic_vector(12 downto 0);
variable ADDER_DATA : unsigned (12 downto 0);
variable cat : std_logic_vector(1 downto 0) := "00";
begin
if RESETn = '0' then
ADDER_DATA := (others => '0');
@@ -208,15 +209,16 @@ begin
ADDER_DATA := ADDER_DATA + ADDER_IN;
end if;
--
case DDEn & HDTYPE is
cat := DDEn & HDTYPE;
case cat is
when "01" => -- MFM mode using HD disks, results in 1us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(10 downto 8));
when "00" => -- MFM mode using DD disks, results in 2us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
when "11" => -- FM mode using HD disks, results in 2us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
when "10" => -- FM mode using DD disks, results in 4us inspection period:
ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10));
ADDER_MSBs <= std_logic_vector(ADDER_DATA(12 downto 10));
end case;
end process ADDER;
@@ -285,7 +287,7 @@ begin
FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP)
-- The frequency decoder controls the period of the data inspection window respective to the
-- ERROR_HISTORY for the 11 bit adder is as follows:
-- ERROR_HISTORY for the 11 std_logic adder is as follows:
-- ERROR_HISTORY = 0:
-- -> no correction necessary <-
-- ERROR_HISTORY = 1:
@@ -294,9 +296,9 @@ begin
-- ERROR_HISTORY = 2:
-- MSBs input: 7 6 5 4 3 2 1 0
-- Correction output: -4 -3 -2 -1 +1 +2 +3 +4
-- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation
-- The most significant std_logic of the FREQ_AMOUNT controls incrementation or decrementation
-- of the adder (0 is up).
variable FREQ_AMOUNT: std_logic_vector(3 downto 0);
variable FREQ_AMOUNT: unsigned (3 downto 0);
begin
if RESETn = '0' then
FREQ_AMOUNT := "0000";
@@ -329,7 +331,7 @@ begin
FREQ_AMOUNT := "0000";
end case;
elsif FREQ_AMOUNT(2 downto 0) > "000" then
FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register.
FREQ_AMOUNT := FREQ_AMOUNT - 1; -- Modify the frequency amount register.
end if;
end if;
--
@@ -348,13 +350,13 @@ begin
end process FREQUENCY_DECODER;
PHASE_DECODER: process(RESETn, CLK)
-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit
-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant std_logic
-- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a
-- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of
-- phase lag, the next rollover should come later (indicated by a '1' of the most significant std_logic of
-- PHASE_AMOUNT).
-- This implementation gives the freedom to adjust the phase amount individually for every mode
-- depending on DDEn and HDTYPE.
variable PHASE_AMOUNT: std_logic_vector(5 downto 0);
variable PHASE_AMOUNT: unsigned (5 downto 0);
begin
if RESETn = '0' then
PHASE_AMOUNT := "000000";

250
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_pkg.vhd
View File

@@ -64,169 +64,169 @@ package WF1772IP_PKG is
-- component declarations:
component WF1772IP_AM_DETECTOR
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
DATA : in bit;
DATA_STRB : in bit;
ID_AM : out bit;
DATA_AM : out bit;
DDATA_AM : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
DATA : in std_logic;
DATA_STRB : in std_logic;
ID_AM : out std_logic;
DATA_AM : out std_logic;
DDATA_AM : out std_logic
);
end component;
component WF1772IP_CONTROL
port(
CLK : in bit;
RESETn : in bit;
A1, A0 : in bit;
RWn : in bit;
CSn : in bit;
DDEn : in bit;
DR : in bit_vector(7 downto 0);
CLK : in std_logic;
RESETn : in std_logic;
A1, A0 : in std_logic;
RWn : in std_logic;
CSn : in std_logic;
DDEn : in std_logic;
DR : in std_logic_vector(7 downto 0);
CMD : in std_logic_vector(7 downto 0);
DSR : in std_logic_vector(7 downto 0);
TR : in std_logic_vector(7 downto 0);
SR : in std_logic_vector(7 downto 0);
MO : out bit;
WR_PR : out bit;
SPINUP_RECTYPE : out bit;
SEEK_RNF : out bit;
CRC_ERRFLAG : out bit;
LOST_DATA_TR00 : out bit;
DRQ : out bit;
DRQ_IPn : out bit;
BUSY : out bit;
AM_2_DISK : out bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
CRC_ERR : in bit;
CRC_PRES : out bit;
TR_PRES : out bit;
TR_CLR : out bit;
TR_INC : out bit;
TR_DEC : out bit;
SR_LOAD : out bit;
SR_INC : out bit;
MO : out std_logic;
WR_PR : out std_logic;
SPINUP_RECTYPE : out std_logic;
SEEK_RNF : out std_logic;
CRC_ERRFLAG : out std_logic;
LOST_DATA_TR00 : out std_logic;
DRQ : out std_logic;
DRQ_IPn : out std_logic;
BUSY : out std_logic;
AM_2_DISK : out std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
CRC_ERR : in std_logic;
CRC_PRES : out std_logic;
TR_PRES : out std_logic;
TR_CLR : out std_logic;
TR_INC : out std_logic;
TR_DEC : out std_logic;
SR_LOAD : out std_logic;
SR_INC : out std_logic;
TRACK_NR : out std_logic_vector(7 downto 0);
DR_CLR : out bit;
DR_LOAD : out bit;
SHFT_LOAD_SD : out bit;
SHFT_LOAD_ND : out bit;
CRC_2_DISK : out bit;
DSR_2_DISK : out bit;
FF_2_DISK : out bit;
PRECOMP_EN : out bit;
DATA_STRB : in bit;
DISK_RWn : out bit;
WPRTn : in bit;
TRACK00n : in bit;
IPn : in bit;
DIRC : out bit;
STEP : out bit;
WG : out bit;
INTRQ : out bit
DR_CLR : out std_logic;
DR_LOAD : out std_logic;
SHFT_LOAD_SD : out std_logic;
SHFT_LOAD_ND : out std_logic;
CRC_2_DISK : out std_logic;
DSR_2_DISK : out std_logic;
FF_2_DISK : out std_logic;
PRECOMP_EN : out std_logic;
DATA_STRB : in std_logic;
DISK_RWn : out std_logic;
WPRTn : in std_logic;
TRACK00n : in std_logic;
IPn : in std_logic;
DIRC : out std_logic;
STEP : out std_logic;
WG : out std_logic;
INTRQ : out std_logic
);
end component;
component WF1772IP_CRC_LOGIC
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
DISK_RWn : in bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
SD : in bit;
CRC_STRB : in bit;
CRC_2_DISK : in bit;
CRC_PRES : in bit;
CRC_SDOUT : out bit;
CRC_ERR : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
DISK_RWn : in std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
SD : in std_logic;
CRC_STRB : in std_logic;
CRC_2_DISK : in std_logic;
CRC_PRES : in std_logic;
CRC_SDOUT : out std_logic;
CRC_ERR : out std_logic
);
end component;
component WF1772IP_DIGITAL_PLL
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
HDTYPE : in bit;
DISK_RWn : in bit;
RDn : in bit;
PLL_D : out bit;
PLL_DSTRB : out bit
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
DISK_RWn : in std_logic;
RDn : in std_logic;
PLL_D : out std_logic;
PLL_DSTRB : out std_logic
);
end component;
component WF1772IP_REGISTERS
port(
CLK : in bit;
RESETn : in bit;
CSn : in bit;
ADR : in bit_vector(1 downto 0);
RWn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CSn : in std_logic;
ADR : in std_logic_vector(1 downto 0);
RWn : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
CMD : out std_logic_vector(7 downto 0);
SR : out std_logic_vector(7 downto 0);
TR : out std_logic_vector(7 downto 0);
DSR : out std_logic_vector(7 downto 0);
DR : out bit_vector(7 downto 0);
SD_R : in bit;
DATA_STRB : in bit;
DR_CLR : in bit;
DR_LOAD : in bit;
TR_PRES : in bit;
TR_CLR : in bit;
TR_INC : in bit;
TR_DEC : in bit;
DR : out std_logic_vector(7 downto 0);
SD_R : in std_logic;
DATA_STRB : in std_logic;
DR_CLR : in std_logic;
DR_LOAD : in std_logic;
TR_PRES : in std_logic;
TR_CLR : in std_logic;
TR_INC : in std_logic;
TR_DEC : in std_logic;
TRACK_NR : in std_logic_vector(7 downto 0);
SR_LOAD : in bit;
SR_INC : in bit;
SHFT_LOAD_SD : in bit;
SHFT_LOAD_ND : in bit;
MOTOR_ON : in bit;
WRITE_PROTECT : in bit;
SPINUP_RECTYPE : in bit;
SEEK_RNF : in bit;
CRC_ERRFLAG : in bit;
LOST_DATA_TR00 : in bit;
DRQ : in bit;
DRQ_IPn : in bit;
BUSY : in bit;
DDEn : in bit
SR_LOAD : in std_logic;
SR_INC : in std_logic;
SHFT_LOAD_SD : in std_logic;
SHFT_LOAD_ND : in std_logic;
MOTOR_ON : in std_logic;
WRITE_PROTECT : in std_logic;
SPINUP_RECTYPE : in std_logic;
SEEK_RNF : in std_logic;
CRC_ERRFLAG : in std_logic;
LOST_DATA_TR00 : in std_logic;
DRQ : in std_logic;
DRQ_IPn : in std_logic;
BUSY : in std_logic;
DDEn : in std_logic
);
end component;
component WF1772IP_TRANSCEIVER
port(
CLK : in bit;
RESETn : in bit;
DDEn : in bit;
HDTYPE : in bit;
ID_AM : in bit;
DATA_AM : in bit;
DDATA_AM : in bit;
SHFT_LOAD_SD : in bit;
DR : in bit_vector(7 downto 0);
PRECOMP_EN : in bit;
AM_TYPE : in bit;
AM_2_DISK : in bit;
CRC_2_DISK : in bit;
DSR_2_DISK : in bit;
FF_2_DISK : in bit;
CLK : in std_logic;
RESETn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
ID_AM : in std_logic;
DATA_AM : in std_logic;
DDATA_AM : in std_logic;
SHFT_LOAD_SD : in std_logic;
DR : in std_logic_vector(7 downto 0);
PRECOMP_EN : in std_logic;
AM_TYPE : in std_logic;
AM_2_DISK : in std_logic;
CRC_2_DISK : in std_logic;
DSR_2_DISK : in std_logic;
FF_2_DISK : in std_logic;
SR_SDOUT : in std_logic;
CRC_SDOUT : in bit;
WRn : out bit;
PLL_DSTRB : in bit;
PLL_D : in bit;
WDATA : out bit;
DATA_STRB : out bit;
SD_R : out bit
CRC_SDOUT : in std_logic;
WRn : out std_logic;
PLL_DSTRB : in std_logic;
PLL_D : in std_logic;
WDATA : out std_logic;
DATA_STRB : out std_logic;
SD_R : out std_logic
);
end component;
end WF1772IP_PKG;

76
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_registers.vhd
View File

@@ -59,65 +59,65 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_REGISTERS is
port(
-- System control:
CLK : in bit;
RESETn : in bit;
CLK : in std_logic;
RESETn : in std_logic;
-- Bus interface:
CSn : in bit;
ADR : in bit_vector(1 downto 0);
RWn : in bit;
CSn : in std_logic;
ADR : in std_logic_vector(1 downto 0);
RWn : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0);
DATA_EN : out bit;
DATA_EN : out std_logic;
-- FDC data:
CMD : out std_logic_vector(7 downto 0); -- Command register.
SR : out std_logic_vector(7 downto 0); -- Sector register.
TR : out std_logic_vector(7 downto 0); -- Track register.
DSR : out std_logic_vector(7 downto 0); -- Data shift register.
DR : out bit_vector(7 downto 0); -- Data register.
DR : out std_logic_vector(7 downto 0); -- Data register.
-- Serial data and clock strobes (in and out):
DATA_STRB : in bit; -- Strobe for the incoming data.
SD_R : in bit; -- Serial data input.
DATA_STRB : in std_logic; -- Strobe for the incoming data.
SD_R : in std_logic; -- Serial data input.
-- DATA register control:
DR_CLR : in bit; -- Clear.
DR_LOAD : in bit; -- LOAD.
DR_CLR : in std_logic; -- Clear.
DR_LOAD : in std_logic; -- LOAD.
-- Track register controls:
TR_PRES : in bit; -- Set x"FF".
TR_CLR : in bit; -- Clear.
TR_INC : in bit; -- Increment.
TR_DEC : in bit; -- Decrement.
TR_PRES : in std_logic; -- Set x"FF".
TR_CLR : in std_logic; -- Clear.
TR_INC : in std_logic; -- Increment.
TR_DEC : in std_logic; -- Decrement.
-- Sector register control:
TRACK_NR : in std_logic_vector(7 downto 0);
SR_LOAD : in bit; -- Load.
SR_INC : in bit; -- Increment.
SR_LOAD : in std_logic; -- Load.
SR_INC : in std_logic; -- Increment.
-- Shift register control:
SHFT_LOAD_SD : in bit;
SHFT_LOAD_ND : in bit;
SHFT_LOAD_SD : in std_logic;
SHFT_LOAD_ND : in std_logic;
-- Status register stuff
MOTOR_ON : in bit;
WRITE_PROTECT : in bit;
SPINUP_RECTYPE : in bit; -- Disk is on speed / data mark status.
SEEK_RNF : in bit; -- Seek error / record not found status flag.
CRC_ERRFLAG : in bit; -- CRC status flag.
LOST_DATA_TR00 : in bit;
DRQ : in bit;
DRQ_IPn : in bit;
BUSY : in bit;
MOTOR_ON : in std_logic;
WRITE_PROTECT : in std_logic;
SPINUP_RECTYPE : in std_logic; -- Disk is on speed / data mark status.
SEEK_RNF : in std_logic; -- Seek error / record not found status flag.
CRC_ERRFLAG : in std_logic; -- CRC status flag.
LOST_DATA_TR00 : in std_logic;
DRQ : in std_logic;
DRQ_IPn : in std_logic;
BUSY : in std_logic;
-- Others:
DDEn : in bit
DDEn : in std_logic
);
end WF1772IP_REGISTERS;
@@ -131,7 +131,7 @@ signal DATA_REG : std_logic_vector(7 downto 0);
signal COMMAND_REG : std_logic_vector(7 downto 0);
signal SECTOR_REG : std_logic_vector(7 downto 0);
signal TRACK_REG : std_logic_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal STATUS_REG : std_logic_vector(7 downto 0);
signal SD_R_I : std_logic;
begin
-- Type conversion To_Std_Logic:
@@ -176,7 +176,7 @@ begin
end if;
end process DATAREG;
-- Data register buffered for further data processing.
DR <= To_BitVector(DATA_REG);
DR <= (DATA_REG);
SECTORREG: process(RESETn, CLK)
begin
@@ -190,7 +190,7 @@ begin
-- 'Read Address'.
SECTOR_REG <= TRACK_NR;
elsif SR_INC = '1' then
SECTOR_REG <= SECTOR_REG + '1';
SECTOR_REG <= std_logic_vector(unsigned(SECTOR_REG) + 1);
end if;
end if;
end process SECTORREG;
@@ -208,9 +208,9 @@ begin
elsif TR_CLR = '1' then
TRACK_REG <= (others => '0'); -- Reset the track register.
elsif TR_INC = '1' then
TRACK_REG <= TRACK_REG + '1'; -- Increment register contents.
TRACK_REG <= std_logic_vector(unsigned(TRACK_REG) + 1); -- Increment register contents.
elsif TR_DEC = '1' then
TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents.
TRACK_REG <= std_logic_vector(unsigned(TRACK_REG) - 1); -- Decrement register contents.
end if;
end if;
end process TRACKREG;
@@ -253,12 +253,12 @@ begin
-- The register data after writing to the track register is valid at least
-- after 32us in FM mode and after 16us in MFM mode.
-- Read from status register. This register is read only:
-- Be aware, that the status register data bits 7 to 1 after writing
-- Be aware, that the status register data std_logics 7 to 1 after writing
-- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and
-- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
-- the std_logic 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else
SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else
DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else
To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0';
end architecture BEHAVIOR;

78
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top.vhd
View File

@@ -69,60 +69,60 @@ use work.WF1772IP_PKG.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TOP is
port (
CLK : in bit; -- 16MHz clock!
MRn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic; -- 16MHz clock!
MRn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA : inout std_logic_vector(7 downto 0);
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks.
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end entity WF1772IP_TOP;
architecture STRUCTURE of WF1772IP_TOP is
component WF1772IP_TOP_SOC
port (
CLK : in bit;
RESETn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic;
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit;
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic;
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end component;
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_EN : bit;
signal DATA_EN : std_logic;
begin
DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');

124
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd
View File

@@ -73,82 +73,82 @@ use work.WF1772IP_PKG.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TOP_SOC is
port (
CLK : in bit; -- 16MHz clock!
RESETn : in bit;
CSn : in bit;
RWn : in bit;
A1, A0 : in bit;
CLK : in std_logic; -- 16MHz clock!
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out bit;
RDn : in bit;
TR00n : in bit;
IPn : in bit;
WPRTn : in bit;
DDEn : in bit;
HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks.
MO : out bit;
WG : out bit;
WD : out bit;
STEP : out bit;
DIRC : out bit;
DRQ : out bit;
INTRQ : out bit
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end entity WF1772IP_TOP_SOC;
architecture STRUCTURE of WF1772IP_TOP_SOC is
signal DATA_OUT_REG : std_logic_vector(7 downto 0);
signal DATA_EN_REG : bit;
signal DATA_EN_REG : std_logic;
signal CMD_I : std_logic_vector(7 downto 0);
signal DR_I : bit_vector(7 downto 0);
signal DR_I : std_logic_vector(7 downto 0);
signal DSR_I : std_logic_vector(7 downto 0);
signal TR_I : std_logic_vector(7 downto 0);
signal SR_I : std_logic_vector(7 downto 0);
signal ID_AM_I : bit;
signal DATA_AM_I : bit;
signal DDATA_AM_I : bit;
signal AM_TYPE_I : bit;
signal AM_2_DISK_I : bit;
signal DATA_STRB_I : bit;
signal BUSY_I : bit;
signal DRQ_I : bit;
signal DRQ_IPn_I : bit;
signal LD_TR00_I : bit;
signal SP_RT_I : bit;
signal SEEK_RNF_I : bit;
signal WR_PR_I : bit;
signal MO_I : bit;
signal PLL_DSTRB_I : bit;
signal PLL_D_I : bit;
signal CRC_SD_I : bit;
signal CRC_ERR_I : bit;
signal CRC_PRES_I : bit;
signal CRC_ERRFLAG_I : bit;
signal SD_R_I : bit;
signal CRC_SDOUT_I : bit;
signal SHFT_LOAD_SD_I : bit;
signal SHFT_LOAD_ND_I : bit;
signal WR_In : bit;
signal TR_PRES_I : bit;
signal TR_CLR_I : bit;
signal TR_INC_I : bit;
signal TR_DEC_I : bit;
signal SR_LOAD_I : bit;
signal SR_INC_I : bit;
signal DR_CLR_I : bit;
signal DR_LOAD_I : bit;
signal ID_AM_I : std_logic;
signal DATA_AM_I : std_logic;
signal DDATA_AM_I : std_logic;
signal AM_TYPE_I : std_logic;
signal AM_2_DISK_I : std_logic;
signal DATA_STRB_I : std_logic;
signal BUSY_I : std_logic;
signal DRQ_I : std_logic;
signal DRQ_IPn_I : std_logic;
signal LD_TR00_I : std_logic;
signal SP_RT_I : std_logic;
signal SEEK_RNF_I : std_logic;
signal WR_PR_I : std_logic;
signal MO_I : std_logic;
signal PLL_DSTRB_I : std_logic;
signal PLL_D_I : std_logic;
signal CRC_SD_I : std_logic;
signal CRC_ERR_I : std_logic;
signal CRC_PRES_I : std_logic;
signal CRC_ERRFLAG_I : std_logic;
signal SD_R_I : std_logic;
signal CRC_SDOUT_I : std_logic;
signal SHFT_LOAD_SD_I : std_logic;
signal SHFT_LOAD_ND_I : std_logic;
signal WR_In : std_logic;
signal TR_PRES_I : std_logic;
signal TR_CLR_I : std_logic;
signal TR_INC_I : std_logic;
signal TR_DEC_I : std_logic;
signal SR_LOAD_I : std_logic;
signal SR_INC_I : std_logic;
signal DR_CLR_I : std_logic;
signal DR_LOAD_I : std_logic;
signal TRACK_NR_I : std_logic_vector(7 downto 0);
signal CRC_2_DISK_I : bit;
signal DSR_2_DISK_I : bit;
signal FF_2_DISK_I : bit;
signal PRECOMP_EN_I : bit;
signal DISK_RWn_I : bit;
signal WDATA_I : bit;
signal CRC_2_DISK_I : std_logic;
signal DSR_2_DISK_I : std_logic;
signal FF_2_DISK_I : std_logic;
signal PRECOMP_EN_I : std_logic;
signal DISK_RWn_I : std_logic;
signal WDATA_I : std_logic;
begin
-- Three state data bus:
DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0');
@@ -160,7 +160,7 @@ begin
DRQ <= DRQ_I;
-- Write deleted data address mark in MFM mode in 'Write Sector' command in
-- case of asserted command bit 0.
-- case of asserted command std_logic 0.
AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1';
-- The CRC unit is used during read from disk and write to disk.

108
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd
View File

@@ -65,69 +65,69 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity WF1772IP_TRANSCEIVER is
port(
-- System control
CLK : in bit; -- must be 16MHz
RESETn : in bit;
CLK : in std_logic; -- must be 16MHz
RESETn : in std_logic;
-- Data and Control:
HDTYPE : in bit; -- Floppy type HD or DD.
DDEn : in bit; -- Double density select (FM or MFM).
ID_AM : in bit; -- ID addressmark strobe.
HDTYPE : in std_logic; -- Floppy type HD or DD.
DDEn : in std_logic; -- Double density select (FM or MFM).
ID_AM : in std_logic; -- ID addressmark strobe.
DATA_AM : in Bit; -- Data addressmark strobe.
DDATA_AM : in Bit; -- Deleted data addressmark strobe.
SHFT_LOAD_SD : in bit; -- Indication for shift register load time.
DR : in bit_vector(7 downto 0); -- Content of the data register.
SHFT_LOAD_SD : in std_logic; -- Indication for shift register load time.
DR : in std_logic_vector(7 downto 0); -- Content of the data register.
-- Data strobes:
PLL_DSTRB : in bit; -- Clock strobe for RD serial data input.
DATA_STRB : buffer bit;
PLL_DSTRB : in std_logic; -- Clock strobe for RD serial data input.
DATA_STRB : buffer std_logic;
-- Data strobe and data for the CRC during write operation:
WDATA : buffer bit;
WDATA : buffer std_logic;
-- Encoder (logic to disk):
PRECOMP_EN : in bit; -- control signal for MFM write precompensation.
AM_TYPE : in bit; -- Write deleted address mark in MFM mode when 0.
AM_2_DISK : in bit;
DSR_2_DISK : in bit;
FF_2_DISK : in bit;
CRC_2_DISK : in bit;
PRECOMP_EN : in std_logic; -- control signal for MFM write precompensation.
AM_TYPE : in std_logic; -- Write deleted address mark in MFM mode when 0.
AM_2_DISK : in std_logic;
DSR_2_DISK : in std_logic;
FF_2_DISK : in std_logic;
CRC_2_DISK : in std_logic;
SR_SDOUT : in std_logic; -- encoder's data input from the shift register (serial).
CRC_SDOUT : in bit; -- encoder's data input from the CRC unit (serial).
WRn : out bit; -- write output for the MFM drive containing clock and data.
CRC_SDOUT : in std_logic; -- encoder's data input from the CRC unit (serial).
WRn : out std_logic; -- write output for the MFM drive containing clock and data.
-- Decoder (disk to logic):
PLL_D : in bit; -- Serial data input.
SD_R : out bit -- Serial (decoded) data output.
PLL_D : in std_logic; -- Serial data input.
SD_R : out std_logic -- Serial (decoded) data output.
);
end WF1772IP_TRANSCEIVER;
architecture BEHAVIOR of WF1772IP_TRANSCEIVER is
type MFM_STATES is (A_00, B_01, C_10);
type PRECOMP_VALUES is (EARLY, NOMINAL, LATE);
type DEC_STATES is (CLK_PHASE, DATA_PHASE);
type MFM_STATES is (A_00, B_01, C_10);
type PRECOMP_VALUES is (EARLY, NOMINAL, LATE);
type DEC_STATES is (CLK_PHASE, DATA_PHASE);
signal MFM_STATE : MFM_STATES;
signal NEXT_MFM_STATE : MFM_STATES;
signal PRECOMP : PRECOMP_VALUES;
signal DEC_STATE : DEC_STATES;
signal NEXT_DEC_STATE : DEC_STATES;
signal MFM_STATE : MFM_STATES;
signal NEXT_MFM_STATE : MFM_STATES;
signal PRECOMP : PRECOMP_VALUES;
signal DEC_STATE : DEC_STATES;
signal NEXT_DEC_STATE : DEC_STATES;
signal FM_In : bit;
signal FM_In : std_logic;
signal CLKMASK : bit; -- Control for suppression of FM clock transitions.
signal CLKMASK : std_logic; -- Control for suppression of FM clock transitions.
signal MFM_10_STRB : bit;
signal MFM_01_STRB : bit;
signal MFM_10_STRB : std_logic;
signal MFM_01_STRB : std_logic;
signal WR_CNT : std_logic_vector(3 downto 0);
signal MFM_In : bit;
signal WR_CNT : std_logic_vector(3 downto 0);
signal MFM_In : std_logic;
signal AM_SHFT : bit_vector(31 downto 0);
signal AM_SHFT : std_logic_vector(31 downto 0);
begin
-- ####################### encoder stuff ###########################
@@ -157,7 +157,7 @@ begin
-- Input multiplexer:
WDATA <= AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data.
To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data.
'1' when FF_2_DISK = '1' else '0'; -- Write zeros is default.
@@ -168,10 +168,10 @@ begin
CLK_MASK: process(CLK)
-- This part of software controls the suppression of the clock pulses
-- during transmission of several FM special characters. During writing
-- 'normal' data to the disk, only 8 mask bits of the shift register are
-- used. During writing MFM sync and address mark bits, the register is
-- used with 32 mask bits.
variable MASK_SHFT : bit_vector(23 downto 0);
-- 'normal' data to the disk, only 8 mask std_logics of the shift register are
-- used. During writing MFM sync and address mark std_logics, the register is
-- used with 32 mask std_logics.
variable MASK_SHFT : std_logic_vector(23 downto 0);
variable LOCK : boolean;
begin
if CLK = '1' and CLK' event then
@@ -189,8 +189,8 @@ begin
end case;
elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode.
case DR is
when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5.
when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4.
when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between std_logics 4 and 5.
when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between std_logics 3 and 4.
when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
end case;
elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode.
@@ -212,14 +212,14 @@ begin
FM_ENCODER: process (RESETn, DATA_STRB, CLK)
-- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles
-- per FM bit.
-- per FM std_logic.
-- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles
-- per FM bit.
-- per FM std_logic.
-- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies.
-- This process provides the FM encoded signal. The first pulse is in any case the clock
-- pulse and the second pulse is due to data. The FM encoding is very simple and therefore
-- self explaining.
variable CNT : std_logic_vector(7 downto 0);
variable CNT : unsigned (7 downto 0);
begin
if RESETn = '0' then
FM_In <= '1';
@@ -230,7 +230,7 @@ begin
if DATA_STRB = '1' then
CNT := x"00";
else
CNT := CNT + '1';
CNT := CNT + 1;
end if;
-- The flux reversal pulses are centered between the DATA_STRB pulses.
-- In detail: the clock pulse appears in the middle of the first half
@@ -318,7 +318,7 @@ begin
-- WRITEPATTERN(2) is the previous WDATA.
-- WRITEPATTERN(1) is the current WDATA to be sent.
-- WRITEPATTERN(0) is the next WDATA to be sent.
variable WRITEPATTERN : bit_vector(3 downto 0);
variable WRITEPATTERN : std_logic_vector(3 downto 0);
begin
if RESETn = '0' then
PRECOMP <= NOMINAL;
@@ -343,14 +343,14 @@ begin
MFM_STROBES: process (RESETn, DATA_STRB, CLK)
-- For the MFM frequency is 250 kBps for DD type floppies, there are 64
-- 16 MHz clock cycles per MFM bit and for HD type floppies, which have
-- 500 kBps there are 32 16MHz clock pulses for one MFM bit.
-- 16 MHz clock cycles per MFM std_logic and for HD type floppies, which have
-- 500 kBps there are 32 16MHz clock pulses for one MFM std_logic.
-- The MFM state machine (Moore) switches on the DATA_STRB.
-- During one cycle there are the two further strobes MFM_10_STRB and
-- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT.
-- The strobes are centered in the middle of the first half and in the
-- middle of the second half of the DATA_STRB cycle.
variable CNT : std_logic_vector(5 downto 0);
variable CNT : unsigned (5 downto 0);
begin
if RESETn = '0' then
CNT := "000000";
@@ -358,7 +358,7 @@ begin
if DATA_STRB = '1' then
CNT := (others => '0');
else
CNT := CNT + '1';
CNT := CNT + 1;
end if;
if HDTYPE = '1' then
case CNT is
@@ -397,7 +397,7 @@ begin
-- WD177x floppy disc controller.
MFM_WR_TIMING: process(RESETn, CLK)
variable CLKMASK_MFM : bit;
variable CLKMASK_MFM : std_logic;
begin
if RESETn = '0' then
WR_CNT <= x"F";
@@ -413,7 +413,7 @@ begin
elsif MFM_STATE = B_01 and MFM_01_STRB = '1' then
WR_CNT <= x"0";
elsif WR_CNT < x"F" then
WR_CNT <= WR_CNT + '1';
WR_CNT <= std_logic_vector(unsigned(WR_CNT) + 1);
end if;
end if;
end process MFM_WR_TIMING;