disabled FPGA early until its initialized freshly.

BaS_gcc/mcf5474.bdm

@@ -1,9 +1,10 @@
-#!/usr/local/bin/bdmctrl
+#!/usr/local/bin/bdmctrl -v10
 #
 # firebee board initialization for bdmctrl 
 #
 open $1
 reset
+sleep 10000
 
 wait
 
@@ -28,21 +29,21 @@ write 0xFF000500 0xE0000000 4
 write 0xFF000508 0x00001180 4
 write 0xFF000504 0x007F0001 4
 # Init CS1 (Atari I/O address range)
-#write 0xFF00050C 0xFFF00000 4
-#write 0xFF000514 0x00002180 4
-#write 0xFF000510 0x000F0001 4
+write 0xFF00050C 0xFFF00000 4
+write 0xFF000514 0x00002180 4
+write 0xFF000510 0x000F0001 4
 # Init CS2 (FireBee 32 bit I/O address range)
-#write 0xFF000518 0xF0000000 4
-#write 0xFF000520 0x00002100 4
-#write 0xFF00051C 0x07FF0001 4
+write 0xFF000518 0xF0000000 4
+write 0xFF000520 0x00002100 4
+write 0xFF00051C 0x07FF0001 4
 # Init CS3 (FireBee 16 bit I/O address range)
-#write 0xFF000524 0xF8000000 4
-#write 0xFF00052C 0x00000180 4
-#write 0xFF000528 0x03FF0001 4
+write 0xFF000524 0xF8000000 4
+write 0xFF00052C 0x00000180 4
+write 0xFF000528 0x03FF0001 4
 # Init CS4 (FireBee video address range)
-#write 0xFF000530 0x40000000 4
-#write 0xFF000538 0x00000018 4
-#write 0xFF000534 0x003F0001 4
+write 0xFF000530 0x40000000 4
+write 0xFF000538 0x00000018 4
+write 0xFF000534 0x003F0001 4
 
 
 # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
@@ -69,6 +70,7 @@ write 0xFF000240 0x80000000 4	# disable watchdog arbiter
 flash 0xE0000000 flash29
 # do not flash yet. First check if board can be initialized correctly
 
+# load -v bas.elf
 load -v ram.elf
 wait
 sleep 1000

BaS_gcc/sources/init_fpga.c

@@ -85,6 +85,8 @@ void init_fpga(void)
 		}
 	} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END));
 
+	xprintf("finished copying. Clocking\r\n");
+
 	if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)
 	{
 		for (i = 0; i < 4000; i++)

BaS_gcc/sources/startcf.S

@@ -40,7 +40,7 @@ _rom_entry:
 		move.l	d0,MCF_MMU_MMUCR
 
 		/* Initialize RAMBARs: locate SRAM and validate it */
-		move.l	#__RAMBAR0 + 0x7,%d0 	/* supervisor only */
+		move.l	#__RAMBAR0 + 0x7,d0 	/* supervisor only */
 		movec	d0,RAMBAR0
 		move.l	#__RAMBAR1 + 0x1,d0
 		movec	d0,RAMBAR1

BaS_gcc/sources/sysinit.c

@@ -174,6 +174,16 @@ void init_gpio(void)
 
 	// ALLE DIR NORMAL INPUT = 0
 	MCF_GPIO_PDDR_FEC1L = 0b00011110;	/* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */
+
+#define FPGA_STATUS		(1 << 0)
+#define FPGA_CLOCK		(1 << 1)
+#define FPGA_CONFIG		(1 << 2)
+#define FPGA_DATA0		(1 << 3)
+#define FPGA_CONF_DONE	(1 << 5)
+
+	/* pull FPGA config to low as early as possible */
+	MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;		/* FPGA clock => low */
+	MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG;	/* FPGA config => low */
 }
 
 /*