change PCI area cache mode to CACHE_NOCACHE_PRECISE
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@@ -595,8 +595,8 @@ void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_i
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#else
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#else
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BEGIN_ACCEL(4);
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BEGIN_ACCEL(4);
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#endif
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#endif
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OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
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OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x + skipleft) & 0xffff));
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OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
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OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x + w) & 0xffff));
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OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
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OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
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/* Have to pad the width here and use clipping engine */
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/* Have to pad the width here and use clipping engine */
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OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
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OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
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@@ -297,7 +297,7 @@ int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
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struct mmu_page_descriptor_ram pci_descriptor =
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struct mmu_page_descriptor_ram pci_descriptor =
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{
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{
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.cache_mode = CACHE_COPYBACK,
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.cache_mode = CACHE_NOCACHE_PRECISE,
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.supervisor_protect = 0,
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.supervisor_protect = 0,
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.read = 1,
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.read = 1,
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.write = 1,
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.write = 1,
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@@ -327,7 +327,9 @@ int mmu_map_data_page(uint32_t virt, uint8_t asid)
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{
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{
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phys = virt;
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phys = virt;
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page = &pci_descriptor;
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page = &pci_descriptor;
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};
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}
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else
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return 0;
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