tried, but did not find the cause of access error during alignment of the TD buffers...

BaS_gcc/Makefile

@@ -33,8 +33,6 @@ INCLUDE=-Iinclude
 CFLAGS=-mcpu=5474\
 	   -Wall\
 		-g \
-	   -Winline\
-	   -O \
 	   -fomit-frame-pointer\
 	   -ffreestanding\
 	   -fleading-underscore\

BaS_gcc/bas.lk.in

@@ -68,17 +68,17 @@ SECTIONS
 		__BAS_DATA_START = .;
 		*(.data)
 		__BAS_DATA_END = .;
+		__BAS_BSS_START = .;
 		*(.bss)	
+		__BAS_BSS_END = .;
 #endif /* TARGET_ADDRESS */
-#if (TARGET_ADDRESS < 0x1FFFFFFF && TARGET_ADDRESS > 0)
-		. = ALIGN(16);
-		_usb_buffer = .;
-		. = . + USB_BUFFER_SIZE;
-#endif
-
 #if (FORMAT == elf32-m68k)
 		*(.rodata)
 		*(.rodata.*)
+#endif
+#if (TARGET_ADDRESS < 0x1FFFFFFF && TARGET_ADDRESS > 0)
+		. = ALIGN(16);
+		_usb_buffer = .;
 #endif
 	} > bas_rom
 
@@ -96,7 +96,9 @@ SECTIONS
 			__BAS_DATA_START = .;
 			*(.data)
 			__BAS_DATA_END = .;
+			__BAS_BSS_START = .;
 			*(.bss)	
+			__BAS_BSS_END = .;
 
 			/* The BaS copy routine assumes that tha BaS size
 		 	 * is a multiple of the following value.

BaS_gcc/bas_m5484.bdm

@@ -22,8 +22,8 @@ write-ctrl 0x0C04 0xFF100007
 # Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
 write-ctrl 0x0C05 0xFF101001
 
-# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
-write 0xFF000500 0xE0080000 4
+write 0xFF000500 0xE0000000 4
 write 0xFF000508 0x00041180 4
 write 0xFF000504 0x003F0001 4
 wait
@@ -49,9 +49,4 @@ write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
 sleep 100
 
 load -v m5484lite/ram.elf
-write-ctrl 0x80e	0x2700
-write-ctrl 0x2	0xa50c8120
-dump-register SR
-dump-register CACR
-dump-register MBAR
 execute

BaS_gcc/include/m5484l.h

@@ -29,7 +29,7 @@
 
 #define SYSCLK			100000
 
-#define BOOTFLASH_BASE_ADDRESS	0xE0000000
+#define BOOTFLASH_BASE_ADDRESS	0xFF800000
 #define BOOTFLASH_SIZE				0x400000				/* LITEKIT has 4MB flash */
 #define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)
 

BaS_gcc/include/ohci.h

@@ -447,7 +447,7 @@ static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pip
 #define NUM_TD 64
 
 /* pointers to aligned storage */
-td_t *ptd;
+extern td_t *ptd;
 
 /* TDs ... */
 static inline struct td *td_alloc(struct usb_device *usb_dev)

BaS_gcc/sources/BaS.c

@@ -230,12 +230,14 @@ void BaS(void)
 	nvram_init();
 #endif /* MACHINE_FIREBEE */
 
+#ifdef MACHINE_FIREBEE 
 	xprintf("copy EmuTOS: ");
 
 	/* copy EMUTOS */
 	src = (uint8_t *) EMUTOS;
 	memcpy(dst, src, EMUTOS_SIZE);
 	xprintf("finished\r\n");
+#endif /* MACHINE_FIREBEE */
 
 	xprintf("initialize MMU: ");
 	mmu_init();

BaS_gcc/sources/ohci-hcd.c

@@ -1403,6 +1403,7 @@ static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pipe
 	urb->transfer_buffer = buffer;
 	urb->transfer_buffer_length = transfer_len;
 	urb->interval = interval;
+
 	/* device pulled? Shortcut the action. */
 	if (ohci->devgone == dev)
 	{
@@ -1895,6 +1896,7 @@ static void hc_free_buffers(ohci_t *ohci)
 
 /*-------------------------------------------------------------------------*/
 
+td_t *ptd;
 /*
  * low level initalisation routine, called from usb.c
  */
@@ -1936,6 +1938,7 @@ int ohci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 	ohci->ohci_dev = (struct ohci_device *) (((uint32_t) ohci->ohci_dev_unaligned + 7) & ~7);
 	memset(ohci->ohci_dev, 0, sizeof(struct ohci_device));
 	info("aligned EDs %p", ohci->ohci_dev);
+
 	ohci->td_unaligned = (td_t *) usb_malloc(sizeof(td_t) * (NUM_TD + 1));
 	if (ohci->td_unaligned == NULL)
 	{
@@ -1943,10 +1946,13 @@ int ohci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 		hc_free_buffers(ohci);
 		return(-1);
 	}
+	
 	ptd = (td_t *) (((uint32_t) ohci->td_unaligned + 7) & ~7);
+
 	xprintf("memset from %p to %p\r\n", ptd, ptd + sizeof(td_t) * NUM_TD);
 	memset(ptd, 0, sizeof(td_t) * NUM_TD);
 	info("aligned TDs %p", ptd);
+
 	ohci->disabled = 1;
 	ohci->sleeping = 0;
 	ohci->irq = -1;

BaS_gcc/sources/sysinit.c

@@ -352,10 +352,10 @@ void init_fbcs()
 			MCF_FBCS_CSCR_WS(6)|						/* 6 Waitstates */
 			MCF_FBCS_CSCR_AA;							/* */
 	MCF_FBCS0_CSMR = BOOTFLASH_BAM |
-			MCF_FBCS_CSMR_V;				/* 8 MByte on */
+			MCF_FBCS_CSMR_V;							/* enable */
 
 
-#ifdef MACHINE_FIREBEE /* FBC setup for FireBee */
+#if MACHINE_FIREBEE /* FBC setup for FireBee */
 	MCF_FBCS1_CSAR = 0xFFF00000;			/* ATARI I/O ADRESS */
 	MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16	/* 16BIT PORT */
 	    | MCF_FBCS_CSCR_WS(8)				/* DEFAULT 8WS */
@@ -381,6 +381,12 @@ void init_fbcs()
 	    | MCF_FBCS_CSCR_BSTW;				// BURST WRITE ENABLE
 	MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G	// 4000'0000-7FFF'FFFF
 			  | MCF_FBCS_CSMR_V;
+#elif MACHINE_M5484LITE
+	/* disable other FBCS for now */
+	MCF_FBCS1_CSMR = 0;
+	MCF_FBCS2_CSMR = 0;
+	MCF_FBCS3_CSMR = 0;
+	MCF_FBCS4_CSMR = 0;
 #endif /* MACHINE_FIREBEE */
 
 
@@ -837,7 +843,7 @@ extern uint8_t _BAS_RESIDENT_TEXT[];
 extern uint8_t _BAS_RESIDENT_TEXT_SIZE[];
 #define BAS_RESIDENT_TEXT_SIZE ((uint32_t) _BAS_RESIDENT_TEXT_SIZE)
 
-void clear_datasegment(void)
+void clear_data_segment(void)
 {
 	extern uint8_t _BAS_DATA_START[];
 	uint8_t *BAS_DATA_START = &_BAS_DATA_START[0];
@@ -847,6 +853,16 @@ void clear_datasegment(void)
 	bzero(BAS_DATA_START, BAS_DATA_END - BAS_DATA_START);
 }
 
+void clear_bss_segment(void)
+{
+	extern uint8_t _BAS_BSS_START[];
+	uint8_t * BAS_BSS_START = &_BAS_BSS_START[0];
+	extern uint8_t _BAS_BSS_END[];
+	uint8_t *BAS_BSS_END = &_BAS_BSS_END[0];
+
+	bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_END);
+}
+
 void initialize_hardware(void)
 {
 	/* Test for FireTOS switch: DIP switch #5 up */
@@ -881,8 +897,9 @@ void initialize_hardware(void)
 
 	if (BAS_LMA != BAS_IN_RAM)
 	{
-		clear_datasegment();
+		clear_data_segment();
 	}
+	clear_bss_segment();
 
 	init_gpio();
 	init_serial();