PCI memory access working
This commit is contained in:
Markus Fröschle
117
include/pci.h
117
include/pci.h
@@ -27,22 +27,27 @@
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#define PCI_MEMORY_OFFSET 0x80000000
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#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
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#define PCI_IO_OFFSET 0xD0000000
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#define PCI_IO_SIZE 0x10000000 /* 128 MByte PCI I/O window */
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#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
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#define PCI_LANESWAP_B(x) (x ^ 3)
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#define PCI_LANESWAP_W(x) (x ^ 2)
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#define PCI_LANESWAP_L(x) (x) /* for completeness only */
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/*
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* Note: the byte offsets are in little endian format, so you can't use them
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* on byteswapped (Motorola format) values!
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* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
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* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
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* and for pci_xxx_config_word() into PCI_LANESWAP_W()
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*/
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#define PCIIDR 0x00 /* PCI Configuration ID Register */
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#define PCICSR 0x04 /* PCI Command/Status Register */
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#define PCICR 0x04 /* PCI Command Register */
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#define PCISR 0x06 /* PCI Status Register */
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#define PCIREV 0x08 /* PCI Revision ID Register */
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#define PCICCR 0x0B /* PCI Class Code Register */
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#define PCICLSR 0x0C /* PCI Cache Line Size Register */
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#define PCILTR 0x0D /* PCI Latency Timer Register */
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#define PCIHTR 0x0E /* PCI Header Type Register */
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#define PCIBISTR 0x0F /* PCI Build-In Self Test Register */
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#define PCICR 0x06 /* PCI Command Register */
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#define PCISR 0x04 /* PCI Status Register */
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#define PCIREV 0x0B /* PCI Revision ID Register */
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#define PCICCR 0x08 /* PCI Class Code Register */
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#define PCICLSR 0x0F /* PCI Cache Line Size Register */
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#define PCILTR 0x0E /* PCI Latency Timer Register */
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#define PCIHTR 0x0D /* PCI Header Type Register */
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#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
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#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
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Accesses to Local, Runtime, and DMA */
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#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
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@@ -55,13 +60,13 @@
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#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
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#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
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#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
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#define PCISID 0x2E /* PCI Subsystem ID */
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#define PCISID 0x2D /* PCI Subsystem ID */
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#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
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#define CAP_PTR 0x34 /* New Capability Pointer */
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#define PCIILR 0x3C /* PCI Interrupt Line Register */
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#define PCIIPR 0x3D /* PCI Interrupt Pin Register */
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#define PCIMGR 0x3E /* PCI Min_Gnt Register */
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#define PCIMLR 0x3F /* PCI Max_Lat Register */
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#define PCIILR 0x3F /* PCI Interrupt Line Register */
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#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
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#define PCIMGR 0x3D /* PCI Min_Gnt Register */
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#define PCIMLR 0x3C /* PCI Max_Lat Register */
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#define PMCAPID 0x40 /* Power Management Capability ID */
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#define PMNEXT 0x41 /* Power Management Next Capability
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Pointer */
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@@ -81,41 +86,41 @@
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/*
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* bit definitions for PCICSR lower half (Command Register)
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*/
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#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */
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#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
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#define PCICSR_MASTER (1 << 2) /* if set: device is master */
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#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
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#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
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#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
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#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */
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#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */
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#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */
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#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
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#define PCICSR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
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#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
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#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
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#define PCICR_MASTER (1 << 2) /* if set: device is master */
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#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
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#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
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#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
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#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
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#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
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#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
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#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
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#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
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/*
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* bit definitions for PCICSR upper half (Status Register)
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*/
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#define PCICSR_INTERRUPT (1 << 3) /* device requested interrupt */
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#define PCICSR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
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#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */
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#define PCICSR_UDF (1 << 6) /* UDF supported */
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#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
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#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */
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#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
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#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
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#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
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#define PCISR_UDF (1 << 6) /* UDF supported */
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#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
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#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
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#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */
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#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */
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#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */
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#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */
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#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */
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#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
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#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
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#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
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#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
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#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
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/* Header type 1 (PCI-to-PCI bridges) */
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#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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#define PCI_SUBORDINATE_BUS 0x1A /* Highest bus number behind the bridge */
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#define PCI_SEC_LATENCY_TIMER 0x1B /* Latency timer for secondary interface */
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#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
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#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
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#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
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#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
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#define PCI_IO_LIMIT 0x1D
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#define PCI_SEC_STATUS 0x1E /* Secondary status register, only bit 14 used */
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#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
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#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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@@ -186,28 +191,28 @@ typedef struct /* structure of address conversion */
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/* PCI configuration space macros */
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/* register 0x00 macros */
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#define PCI_VENDOR_ID(i) swpw((uint16_t)(((i) & 0xffff0000) >> 16))
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#define PCI_DEVICE_ID(i) swpw((uint16_t) ((i) & 0xffff))
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#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
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#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
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/* register 0x04 macros */
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#define PCI_STATUS(i) ((i) & 0xffff)
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#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
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/* register 0x08 macros */
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#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24)
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#define PCI_SUBCLASS(i) ((swpl((i)) & 0x00ff0000) >> 16)
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#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8)
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#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff))
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#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24)
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#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16)
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#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8)
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#define PCI_REVISION_ID(i) (((i) & 0x000000ff))
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/* register 0x0c macros */
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#define PCI_BIST(i) ((swpl((i)) & 0xff000000) >> 24)
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#define PCI_HEADER_TYPE(i) ((swpl((i)) & 0x00ff0000) >> 16)
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#define PCI_LAT_TIMER(i) ((swpl((i)) & 0x0000ff00) >> 8)
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#define PCI_CACHELINE_SIZE(i) ((swpl((i)) & 0x000000ff))
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#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
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#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
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#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
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#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
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/* register 0x2c macros */
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#define PCI_SUBSYS_ID(i) (((i) & 0xffff0000) >> 16)
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#define PCI_SUBSYS_VID(i) (((i) & 0xffff))
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#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
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#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
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/* register 0x34 macros */
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#define PCI_CAPABILITIES(i) ((i) & 0xff)
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@@ -350,4 +355,6 @@ extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
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#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
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#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
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extern void pci_dump_registers(int32_t handle);
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#endif /* _PCI_H_ */
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