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modified to incorporate printf routine

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This commit is contained in:
Markus Fröschle
2012-10-25 16:38:45 +00:00
parent 467cad91af
commit 410323d676
7 changed files with 32 additions and 103 deletions
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2
BaS_GNU/BaS_GNU/.gdbinit
View File

@@ -3,6 +3,6 @@ define tr
target remote | m68k-atari-mint-gdbserver pipe /dev/bdmcf3
end
tr
source 5474.gdb
source mcf5474.gdb

76
BaS_GNU/BaS_GNU/5474.gdb
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@@ -1,76 +0,0 @@
#
# GDB Init script for the Coldfire 5474 processor (Firebee board).
#
# The main purpose of this script is to configure the
# DRAM controller so code can be loaded.
#
#
define addresses
set $vbr = 0x00000000
set $mbar = 0xFF000000
set $rambar0 = 0xFF100000
set $rambar1 = 0xFF101000
end
#
# Setup the DRAM controller.
#
define setup-dram
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
# flash address
set *((long *) 0xFF000500) = 0xE0000000
# 16 bit 4ws aa
set *((long *) 0xFF000508) = 0x00041180
# 8MB on
set *((long *) 0xFF000504) = 0x007F0001
# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
# SDRAMDS configuration
set *((long *) 0xFF000004) = 0x000002AA
# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
set *((long *) 0xFF000020) = 0x0000001A
# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
set *((long *) 0xFF000024) = 0x0800001A
# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
set *((long *) 0xFF000028) = 0x1000001A
# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
set *((long *) 0xFF00002C) = 0x1800001A
# SDCFG1
set *((long *) 0xFF000108) = 0x73622830
# SDCFG2
set *((long *) 0xFF00010C) = 0x46770000
# SDCR + IPALL
set *((long *) 0xFF000104) = 0xE10D0002
# SDMR (write to LEMR)
set *((long *) 0xFF000100) = 0x40010000
# SDMR (write to LMR)
set *((long *) 0xFF000100) = 0x048D0000
# SDCR + IPALL
set *((long *) 0xFF000104) = 0xE10D0002
# SDCR + IREF (first refresh)
set *((long *) 0xFF000104) = 0xE10D0004
# SDCR + IREF (first refresh)
set *((long *) 0xFF000104) = 0xE10D0004
# SDMR (write to LMR)
set *((long *) 0xFF000100) = 0x008D0000
# SDCR (lock SDMR and enable refresh)
set *((long *) 0xFF000104) = 0x710D0F00
end
#
# Wake up the board
#
define initBoard
addresses
setup-dram
end
initBoard

2
BaS_GNU/BaS_GNU/Makefile
View File

@@ -68,7 +68,7 @@ OBJS=$(COBJS) $(AOBJS)
$(MAPFILE) $(LDCFILE) depend
$(FLASH_EXEC): TARGET_ADDRESS=0xe0000000
$(RAM_EXEC): TARGET_ADDRESS=0x01000000
$(RAM_EXEC): TARGET_ADDRESS=0x10000000
$(FLASH_EXEC) $(RAM_EXEC): $(STRT_OBJ) $(OBJS)
$(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) $(LDCSRC) -o $(LDCFILE)

3
BaS_GNU/BaS_GNU/bas.lk.in
View File

@@ -76,6 +76,8 @@ SECTIONS {
objs/BaS.o(.text)
/* put other routines into the same segment (RAM) as BaS.o */
objs/sd_card_asm.o(.text)
_printf_before_copy = . - (ADDR(.bas) - LOADADDR(.bas));
_printf_after_copy = ABSOLUTE(.);
objs/printf.o(.text)
objs/printf_helper.o(.text)
objs/sd_card.o(.text)
@@ -86,6 +88,7 @@ SECTIONS {
objs/illegal_instruction.o(.text)
*(.data)
*(.bss)
_bas_end = ABSOLUTE(.);
} > ram

17
BaS_GNU/BaS_GNU/mcf5474.bdm
View File

@@ -6,7 +6,7 @@ open $1
reset
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
flash 0xE0000000 flash29
#flash 0xE0000000 flash29
# do not flash yet. First check if board can be initialized correctly
# set VBR
@@ -15,11 +15,15 @@ write-ctrl 0x0801 0x00000000
# Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000
# Turn on MMUBAR at 0xFF04_0000
#write-ctrl 0x0008 0xFF000001
#write 0xFF000008 0x00000000 4
# Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100035
write-ctrl 0x0C04 0xFF100007
# Turn on RAMBAR1 at address FF10_1000
write-ctrl 0x0C05 0xFF101035
write-ctrl 0x0C05 0xFF101001
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4
@@ -44,8 +48,5 @@ write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
# load -v ram.s19 # unfortunately, this seems to work only with elf files
load -v bas.s19.elf # TODO: bdmctrl tries to flash but doesn't succed. Don't know why yet
#load -v ram.s19.elf
sleep 60000
execute 0x1000000
load -v ram.s19.elf
execute 0x10000000

14
BaS_GNU/BaS_GNU/sources/BaS.c
View File

@@ -38,16 +38,14 @@ void BaS(void)
uint8_t *src;
uint8_t *dst = tos_base;
uint32_t *adr;
#ifdef _NOT_USED_
/*
az_sectors = sd_card_init();
if (az_sectors > 0)
{
sd_card_idle();
}
#endif /* _NOT_USED_ */
*/
/* Initialize the NVRAM */
MCF_PSC3_PSCTB_8BIT = 'ACPF';
wait_10ms();
@@ -71,7 +69,7 @@ void BaS(void)
{
* (uint8_t *) 0xffff8963 = (uint8_t) MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */
}
uart_out_word(' OK!');
uart_out_word(' OK.');
}
@@ -87,15 +85,15 @@ void BaS(void)
uart_out_word('MMU ');
mmu_init();
uart_out_word(' OK!');
uart_out_word(' OK.');
uart_out_word('EXC ');
vec_init();
uart_out_word(' OK!');
uart_out_word(' OK.');
uart_out_word('ILLG');
illegal_table_make();
uart_out_word(' OK!');
uart_out_word(' OK.');
/* interrupts */

21
BaS_GNU/BaS_GNU/sources/sysinit.c
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@@ -76,7 +76,7 @@ void init_slt(void)
MCF_SLT0_SCR = 0x05000000;
uart_out_word('SLT ');
uart_out_word('OK! ');
uart_out_word('OK. ');
uart_out_word(0x0a0d);
}
@@ -153,7 +153,7 @@ void init_serial(void)
uart_out_word('SERI');
uart_out_word('AL O');
uart_out_word('K! ');
uart_out_word('K. ');
uart_out_word(0x0a0d);
}
@@ -196,7 +196,7 @@ void init_ddram(void)
MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh)
}
uart_out_word('M OK');
uart_out_word('! ');
uart_out_word('. ');
uart_out_word(0x0a0d);
}
@@ -238,7 +238,7 @@ void init_fbcs()
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
uart_out_word(' OK!');
uart_out_word(' OK.');
uart_out_word(0x0a0d);
}
@@ -296,7 +296,7 @@ void init_pll(void)
* (volatile uint8_t *) 0xf0000800 = 0; /* set */
uart_out_word('SET!');
uart_out_word('SET.');
uart_out_word(0x0a0d);
}
@@ -377,7 +377,7 @@ void init_PCI(void) {
/* reset PCI devices */
MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
uart_out_word('OK! ');
uart_out_word('OK. ');
uart_out_word(0x0d0a);
}
@@ -412,7 +412,7 @@ void test_upd720101(void)
MCF_PCI_PCICAR_FUNCNUM(0) +
MCF_PCI_PCICAR_DWORD(57);
}
uart_out_word('OK! ');
uart_out_word('OK. ');
uart_out_word(0x0d0a);
}
@@ -564,7 +564,7 @@ loop_i2c:
next:
uart_out_word('NOT ');
dvi_ok:
uart_out_word('OK! ');
uart_out_word('OK. ');
uart_out_word(0x0a0d);
MCF_I2C_I2CR = 0x0; // i2c off
@@ -665,7 +665,7 @@ livo:
}
MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
uart_out_word(' OK!');
uart_out_word(' OK.');
uart_out_word(0x0a0d);
}
@@ -714,6 +714,9 @@ void initialize_hardware(void) {
init_gpio();
init_serial();
uart_out_word(0x0d0a);
uart_out_word('----');
init_slt();
init_fbcs();
init_ddram();