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started testbench bus transaction implementation

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This commit is contained in:
Markus Fröschle
2014-06-13 06:26:42 +00:00
parent 05a13bdf16
commit 40e6a71e47
2 changed files with 642 additions and 637 deletions
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11
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -17,9 +17,9 @@ architecture beh of ddr_ctlr_tb is
signal DDR_SYNC_66M : std_logic; signal DDR_SYNC_66M : std_logic;
signal FB_CS1n : std_logic; signal FB_CS1n : std_logic;
signal FB_OEn : std_logic; signal FB_OEn : std_logic;
signal FB_SIZE0 : std_logic; signal FB_SIZE0 : std_logic := '1';
signal FB_SIZE1 : std_logic; signal FB_SIZE1 : std_logic := '1'; -- long word access
signal FB_ALE : std_logic; signal FB_ALE : std_logic := 'Z'; -- defined reset state
signal FB_WRn : std_logic; signal FB_WRn : std_logic;
signal FIFO_CLR : std_logic; signal FIFO_CLR : std_logic;
signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0); signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0);
@@ -52,6 +52,9 @@ architecture beh of ddr_ctlr_tb is
signal DATA_EN_H : std_logic; signal DATA_EN_H : std_logic;
signal DATA_EN_L : std_logic; signal DATA_EN_L : std_logic;
signal bus_state_type is (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual
signal bus_state : bus_state_type;
component DDR_CTRL_V1 component DDR_CTRL_V1
port( port(
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
@@ -160,6 +163,8 @@ begin
stimulate : process stimulate : process
begin begin
wait for rising_edge(clock) and clock = '1';
-- begin Coldfire bus transaction
FB_ADR <= "00000000000000000000000000000001"; FB_ADR <= "00000000000000000000000000000001";
wait for 20 ns; wait for 20 ns;
FB_ADR <= "10000000000000000000000000000000"; FB_ADR <= "10000000000000000000000000000000";