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added interface structure to make the MCD DMA available to MiNT (DMAC cookie). MinT's FEC driver works somewhat, but not reliable yet.

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This commit is contained in:
Markus Fröschle
2014-01-01 21:28:17 +00:00
parent 8424a836a1
commit 40c89dd900
15 changed files with 589 additions and 625 deletions
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34
BaS_gcc/dma/dma.c
View File

@@ -35,6 +35,13 @@
#include "m5484l.h"
#endif /* MACHINE_FIREBEE */
#define DBG_DMA
#ifdef DBG_DMA
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_DMA */
extern char _SYS_SRAM[];
#define SYS_SRAM &_SYS_SRAM[0]
@@ -68,6 +75,7 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
MCF_INTC_ICR48 = 0
| MCF_INTC_ICR_IP(pri)
| MCF_INTC_ICR_IL(lvl);
dbg("%s:DMA irq assigned level %d, priority %d\r\n", __FUNCTION__, lvl, pri);
/* Unmask all task interrupts */
MCF_DMA_DIMR = 0;
@@ -77,6 +85,9 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
/* Unmask the DMA interrupt in the interrupt controller */
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
dbg("%s: DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n",
__FUNCTION__);
}
/********************************************************************/
@@ -93,6 +104,8 @@ void dma_irq_disable(void)
/* Mask the DMA interrupt in the interrupt controller */
MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
dbg("%s: DMA interrupts masked and disabled\r\n", __FUNCTION__);
}
int dma_set_initiator(int initiator)
@@ -365,6 +378,7 @@ void dma_free_initiator(int requestor)
break;
}
}
dbg("%s: DMA requestor %d freed\r\n", __FUNCTION__, requestor);
}
/*
@@ -381,18 +395,21 @@ int dma_set_channel(int requestor, void (*handler)(void))
int i;
/* Check to see if this requestor is already assigned to a channel */
dbg("%s: check if requestor %d is already assigned to a channel\r\n", __FUNCTION__, requestor);
if ((i = dma_get_channel(requestor)) != -1)
return i;
for (i=0; i<NCHANNELS; ++i)
for (i = 0; i < NCHANNELS; ++i)
{
if (dma_channel[i].req == -1)
{
dma_channel[i].req = requestor;
dma_channel[i].handler = handler;
dbg("%s: assigned channel %d to requestor %d\r\n", __FUNCTION__, i, requestor);
return i;
}
}
dbg("%s: no free DMA channel found for requestor %d\r\n", __FUNCTION__, requestor);
/* All channels taken */
return -1;
@@ -426,6 +443,7 @@ int dma_get_channel(int requestor)
if (dma_channel[i].req == requestor)
return i;
}
dbg("%s: no channel occupied by requestor %d\r\n", __FUNCTION__, requestor);
return -1;
}
@@ -462,7 +480,7 @@ int dma_interrupt_handler(void *arg1, void *arg2)
(void)arg1;
(void)arg2;
ipl = set_ipl(0x2700);
ipl = set_ipl(7);
/*
* Determine which interrupt(s) triggered by AND'ing the
@@ -477,7 +495,7 @@ int dma_interrupt_handler(void *arg1, void *arg2)
/* Clear the interrupt in the pending register */
MCF_DMA_DIPR = interrupts;
for (i = 0; i < 16; ++i, interrupts>>=1)
for (i = 0; i < 16; ++i, interrupts >>= 1)
{
if (interrupts & 0x1)
{
@@ -488,6 +506,7 @@ int dma_interrupt_handler(void *arg1, void *arg2)
}
set_ipl(ipl);
return 1;
}
/********************************************************************/
@@ -503,7 +522,7 @@ void *dma_memcpy(void *dst, void *src, size_t n)
ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
if (ret == MCD_OK)
{
xprintf("DMA on channel 1 successfully started\r\n");
dbg("%s: DMA on channel 1 successfully started\r\n", __FUNCTION__);
}
do
@@ -545,7 +564,7 @@ void *dma_memcpy(void *dst, void *src, size_t n)
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
xprintf("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
dbg("%s: took %d ms (%f Mbytes/second)\r\n", __FUNCTION__, time, n / (float) time / 1000.0);
return dst;
}
@@ -554,18 +573,17 @@ int dma_init(void)
{
int res;
xprintf("MCD DMA API initialization: ");
dbg("%s: MCD DMA API initialization: ", __FUNCTION__);
res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
if (res != MCD_OK)
{
xprintf("DMA API initialization failed (0x%x)\r\n", res);
dbg("%s: DMA API initialization failed (0x%x)\r\n", __FUNCTION__, res);
return 0;
}
// test
dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000); /* copy one megabyte of flash to RAM */
xprintf("DMA finished\r\n");
return 0;
}

142
BaS_gcc/include/fec.h
View File

@@ -28,7 +28,8 @@
/*
* FEC Event Log
*/
typedef struct {
typedef struct
{
int total; /* total count of errors */
int hberr; /* heartbeat error */
int babr; /* babbling receiver */
@@ -56,109 +57,40 @@ typedef struct {
} FEC_EVENT_LOG;
int
fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t );
int
fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *);
void
fec_mii_init(uint8_t, uint32_t);
void
fec_mib_init(uint8_t);
void
fec_mib_dump(uint8_t);
void
fec_log_init(uint8_t);
void
fec_log_dump(uint8_t);
void
fec_debug_dump(uint8_t);
void
fec_duplex (uint8_t, uint8_t);
uint8_t
fec_hash_address(const uint8_t *);
void
fec_set_address (uint8_t ch, const uint8_t *);
void
fec_reset (uint8_t);
void
fec_init (uint8_t, uint8_t, const uint8_t *);
void
fec_rx_start(uint8_t, int8_t *);
void
fec_rx_restart(uint8_t);
void
fec_rx_stop (uint8_t);
void
fec_rx_frame(uint8_t, NIF *);
void
fec0_rx_frame(void);
void
fec1_rx_frame(void);
void
fec_tx_start(uint8_t, int8_t *);
void
fec_tx_restart(uint8_t);
void
fec_tx_stop (uint8_t);
void
fec0_tx_frame(void);
void
fec1_tx_frame(void);
int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
int
fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
int
fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
void
fec_irq_enable(uint8_t, uint8_t, uint8_t);
void
fec_irq_disable(uint8_t);
void
fec_interrupt_handler(uint8_t);
int
fec0_interrupt_handler(void *, void *);
int
fec1_interrupt_handler(void *, void *);
void
fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
void
fec_eth_reset(uint8_t);
void
fec_eth_stop(uint8_t);
/********************************************************************/
extern int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t );
extern int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *);
extern void fec_mii_init(uint8_t, uint32_t);
extern void fec_mib_init(uint8_t);
extern void fec_mib_dump(uint8_t);
extern void fec_log_init(uint8_t);
extern void fec_log_dump(uint8_t);
extern void fec_debug_dump(uint8_t);
extern void fec_duplex (uint8_t, uint8_t);
extern uint8_t fec_hash_address(const uint8_t *);
extern void fec_set_address (uint8_t ch, const uint8_t *);
extern void fec_reset (uint8_t);
extern void fec_init (uint8_t, uint8_t, const uint8_t *);
extern void fec_rx_start(uint8_t, int8_t *);
extern void fec_rx_restart(uint8_t);
extern void fec_rx_stop (uint8_t);
extern void fec_rx_frame(uint8_t, NIF *);
extern void fec0_rx_frame(void);
extern void fec1_rx_frame(void);
extern void fec_tx_start(uint8_t, int8_t *);
extern void fec_tx_restart(uint8_t);
extern void fec_tx_stop (uint8_t);
extern void fec0_tx_frame(void);
extern void fec1_tx_frame(void);
extern int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
extern int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
extern void fec_irq_disable(uint8_t);
extern void fec_interrupt_handler(uint8_t);
extern int fec0_interrupt_handler(void *, void *);
extern int fec1_interrupt_handler(void *, void *);
extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
extern void fec_eth_reset(uint8_t);
extern void fec_eth_stop(uint8_t);
#endif /* _FEC_H_ */

6
BaS_gcc/include/fecbd.h
View File

@@ -8,6 +8,8 @@
#ifndef _FECBD_H_
#define _FECBD_H_
#include "bas_types.h"
/********************************************************************/
#define Rx 1
@@ -27,10 +29,10 @@
* Number of Rx and Tx Buffers and Buffer Descriptors
*/
#ifndef NRXBD
#define NRXBD 10
#define NRXBD 20
#endif
#ifndef NTXBD
#define NTXBD 4
#define NTXBD 20
#endif
/*

6
BaS_gcc/include/interrupts.h
View File

@@ -78,14 +78,12 @@
#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
#define DMA_INTC_LVL 6 /* interrupt level for DMA interrupt */
#define DMA_INTC_PRI 0 /* interrupt priority for DMA interrupt */
#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */
#define FEC0_INTC_PRI 0 /* interrupt priority for FEC0 */
#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */
#define FEC1_INTC_PRI 1 /* interrupt priority for FEC1 */
#define FEC1_INTC_PRI 7 /* interrupt priority for FEC1 */
#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)

2
BaS_gcc/include/nbuf.h
View File

@@ -8,6 +8,8 @@
#ifndef _NBUF_H_
#define _NBUF_H_
#include "bas_types.h"
/********************************************************************/
/*
* Include the Queue structure definitions

135
BaS_gcc/net/fec.c
View File

@@ -27,6 +27,13 @@
#error Unknown machine!
#endif
#define DBG_FEC
#ifdef DBG_FEC
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_FEC */
FEC_EVENT_LOG fec_log[2];
@@ -86,6 +93,7 @@ int fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII)
break;
}
if(timeout == FEC_MII_TIMEOUT)
return 1;
@@ -226,32 +234,33 @@ void fec_log_init(uint8_t ch)
*/
void fec_log_dump(uint8_t ch)
{
xprintf("\n FEC%d Log\n---------------\n",ch);
xprintf("Total: %4d\n", fec_log[ch].total);
xprintf("hberr: %4d\n", fec_log[ch].hberr);
xprintf("babr: %4d\n", fec_log[ch].babr);
xprintf("babt: %4d\n", fec_log[ch].babt);
xprintf("gra: %4d\n", fec_log[ch].gra);
xprintf("txf: %4d\n", fec_log[ch].txf);
xprintf("mii: %4d\n", fec_log[ch].mii);
xprintf("lc: %4d\n", fec_log[ch].lc);
xprintf("rl: %4d\n", fec_log[ch].rl);
xprintf("xfun: %4d\n", fec_log[ch].xfun);
xprintf("xferr: %4d\n", fec_log[ch].xferr);
xprintf("rferr: %4d\n", fec_log[ch].rferr);
xprintf("dtxf: %4d\n", fec_log[ch].dtxf);
xprintf("drxf: %4d\n", fec_log[ch].drxf);
xprintf("\nRFSW:\n");
xprintf("inv: %4d\n", fec_log[ch].rfsw_inv);
xprintf("m: %4d\n", fec_log[ch].rfsw_m);
xprintf("bc: %4d\n", fec_log[ch].rfsw_bc);
xprintf("mc: %4d\n", fec_log[ch].rfsw_mc);
xprintf("lg: %4d\n", fec_log[ch].rfsw_lg);
xprintf("no: %4d\n", fec_log[ch].rfsw_no);
xprintf("cr: %4d\n", fec_log[ch].rfsw_cr);
xprintf("ov: %4d\n", fec_log[ch].rfsw_ov);
xprintf("tr: %4d\n", fec_log[ch].rfsw_tr);
xprintf("---------------\n\n");
dbg("%s: \r\n FEC%d Log\r\n", __FUNCTION__, ch);
dbg("%s: ---------------\r\n", __FUNCTION__);
dbg("%s: Total: %4d\r\n", __FUNCTION__, fec_log[ch].total);
dbg("%s: hberr: %4d\r\n", __FUNCTION__, fec_log[ch].hberr);
dbg("%s: babr: %4d\r\n", __FUNCTION__, fec_log[ch].babr);
dbg("%s: babt: %4d\r\n", __FUNCTION__, fec_log[ch].babt);
dbg("%s: gra: %4d\r\n", __FUNCTION__, fec_log[ch].gra);
dbg("%s: txf: %4d\r\n", __FUNCTION__, fec_log[ch].txf);
dbg("%s: mii: %4d\r\n", __FUNCTION__, fec_log[ch].mii);
dbg("%s: lc: %4d\r\n", __FUNCTION__, fec_log[ch].lc);
dbg("%s: rl: %4d\r\n", __FUNCTION__, fec_log[ch].rl);
dbg("%s: xfun: %4d\r\n", __FUNCTION__, fec_log[ch].xfun);
dbg("%s: xferr: %4d\r\n", __FUNCTION__, fec_log[ch].xferr);
dbg("%s: rferr: %4d\r\n", __FUNCTION__, fec_log[ch].rferr);
dbg("%s: dtxf: %4d\r\n", __FUNCTION__, fec_log[ch].dtxf);
dbg("%s: drxf: %4d\r\n", __FUNCTION__, fec_log[ch].drxf);
dbg("%s: \r\nRFSW:\r\n", __FUNCTION__);
dbg("%s: inv: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_inv);
dbg("%s: m: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_m);
dbg("%s: bc: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_bc);
dbg("%s: mc: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_mc);
dbg("%s: lg: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_lg);
dbg("%s: no: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_no);
dbg("%s: cr: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_cr);
dbg("%s: ov: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_ov);
dbg("%s: tr: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_tr);
dbg("%s: ---------------\r\n\r\n", __FUNCTION__);
}
/********************************************************************/
@@ -263,30 +272,30 @@ void fec_log_dump(uint8_t ch)
*/
void fec_debug_dump(uint8_t ch)
{
xprintf("\n------------- FEC%d -------------\n",ch);
xprintf("EIR %08x \n", MCF_FEC_EIR(ch));
xprintf("EIMR %08x \n", MCF_FEC_EIMR(ch));
xprintf("ECR %08x \n", MCF_FEC_ECR(ch));
xprintf("RCR %08x \n", MCF_FEC_RCR(ch));
xprintf("R_HASH %08x \n", MCF_FEC_RHR_HASH(ch));
xprintf("TCR %08x \n", MCF_FEC_TCR(ch));
xprintf("FECTFWR %08x \n", MCF_FEC_FECTFWR(ch));
xprintf("FECRFSR %08x \n", MCF_FEC_FECRFSR(ch));
xprintf("FECRFCR %08x \n", MCF_FEC_FECRFCR(ch));
xprintf("FECRLRFP %08x \n", MCF_FEC_FECRLRFP(ch));
xprintf("FECRLWFP %08x \n", MCF_FEC_FECRLWFP(ch));
xprintf("FECRFAR %08x \n", MCF_FEC_FECRFAR(ch));
xprintf("FECRFRP %08x \n", MCF_FEC_FECRFRP(ch));
xprintf("FECRFWP %08x \n", MCF_FEC_FECRFWP(ch));
xprintf("FECTFSR %08x \n", MCF_FEC_FECTFSR(ch));
xprintf("FECTFCR %08x \n", MCF_FEC_FECTFCR(ch));
xprintf("FECTLRFP %08x \n", MCF_FEC_FECTLRFP(ch));
xprintf("FECTLWFP %08x \n", MCF_FEC_FECTLWFP(ch));
xprintf("FECTFAR %08x \n", MCF_FEC_FECTFAR(ch));
xprintf("FECTFRP %08x \n", MCF_FEC_FECTFRP(ch));
xprintf("FECTFWP %08x \n", MCF_FEC_FECTFWP(ch));
xprintf("FRST %08x \n", MCF_FEC_FECFRST(ch));
xprintf("--------------------------------\n\n");
dbg("\n------------- FEC%d -------------\n",ch);
dbg("EIR %08x \n", MCF_FEC_EIR(ch));
dbg("EIMR %08x \n", MCF_FEC_EIMR(ch));
dbg("ECR %08x \n", MCF_FEC_ECR(ch));
dbg("RCR %08x \n", MCF_FEC_RCR(ch));
dbg("R_HASH %08x \n", MCF_FEC_RHR_HASH(ch));
dbg("TCR %08x \n", MCF_FEC_TCR(ch));
dbg("FECTFWR %08x \n", MCF_FEC_FECTFWR(ch));
dbg("FECRFSR %08x \n", MCF_FEC_FECRFSR(ch));
dbg("FECRFCR %08x \n", MCF_FEC_FECRFCR(ch));
dbg("FECRLRFP %08x \n", MCF_FEC_FECRLRFP(ch));
dbg("FECRLWFP %08x \n", MCF_FEC_FECRLWFP(ch));
dbg("FECRFAR %08x \n", MCF_FEC_FECRFAR(ch));
dbg("FECRFRP %08x \n", MCF_FEC_FECRFRP(ch));
dbg("FECRFWP %08x \n", MCF_FEC_FECRFWP(ch));
dbg("FECTFSR %08x \n", MCF_FEC_FECTFSR(ch));
dbg("FECTFCR %08x \n", MCF_FEC_FECTFCR(ch));
dbg("FECTLRFP %08x \n", MCF_FEC_FECTLRFP(ch));
dbg("FECTLWFP %08x \n", MCF_FEC_FECTLWFP(ch));
dbg("FECTFAR %08x \n", MCF_FEC_FECTFAR(ch));
dbg("FECTFRP %08x \n", MCF_FEC_FECTFRP(ch));
dbg("FECTFWP %08x \n", MCF_FEC_FECTFWP(ch));
dbg("FRST %08x \n", MCF_FEC_FECFRST(ch));
dbg("--------------------------------\n\n");
}
/********************************************************************/
@@ -722,7 +731,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
if (new_nbuf == NULL)
{
#ifdef DEBUG_PRINT
xprintf("nbuf_alloc() failed\n");
dbg("nbuf_alloc() failed\n");
#endif
/*
@@ -1031,7 +1040,11 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
/* Check the length */
if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU)
{
dbg("%s: nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
__FUNCTION__, nbuf->length, ETH_HDR_LEN, ETH_MTU);
return 0;
}
/*
* Copy the destination address, source address, and Ethernet
@@ -1162,7 +1175,7 @@ static void fec_irq_handler(uint8_t ch)
#ifdef DEBUG
if (event != eir)
xprintf("Pending but not enabled: 0x%08X\n", (event ^ eir));
dbg("Pending but not enabled: 0x%08X\n", (event ^ eir));
#endif
/*
@@ -1175,8 +1188,8 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].rferr++;
#ifdef DEBUG
xprintf("RFERR\n");
xprintf("FECRFSR%d = 0x%08x\n", ch, MCF_FEC_FECRFSR(ch));
dbg("RFERR\n");
dbg("FECRFSR%d = 0x%08x\n", ch, MCF_FEC_FECRFSR(ch));
fec_eth_stop(ch);
#endif
}
@@ -1185,7 +1198,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].xferr++;
#ifdef DEBUG
xprintf("XFERR\n");
dbg("XFERR\n");
#endif
}
if (event & MCF_FEC_EIR_XFUN)
@@ -1193,7 +1206,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].xfun++;
#ifdef DEBUG
xprintf("XFUN\n");
dbg("XFUN\n");
fec_eth_stop(ch);
#endif
}
@@ -1202,7 +1215,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].rl++;
#ifdef DEBUG
xprintf("RL\n");
dbg("RL\n");
#endif
}
if (event & MCF_FEC_EIR_LC)
@@ -1210,7 +1223,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].lc++;
#ifdef DEBUG
xprintf("LC\n");
dbg("LC\n");
#endif
}
if (event & MCF_FEC_EIR_MII)
@@ -1230,7 +1243,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].babt++;
#ifdef DEBUG
xprintf("BABT\n");
dbg("BABT\n");
#endif
}
if (event & MCF_FEC_EIR_BABR)
@@ -1238,7 +1251,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].babr++;
#ifdef DEBUG
xprintf("BABR\n");
dbg("BABR\n");
#endif
}
if (event & MCF_FEC_EIR_HBERR)
@@ -1246,7 +1259,7 @@ static void fec_irq_handler(uint8_t ch)
fec_log[ch].total++;
fec_log[ch].hberr++;
#ifdef DEBUG
xprintf("HBERR\n");
dbg("HBERR\n");
#endif
}
}

9
BaS_gcc/net/fecbd.c
View File

@@ -11,6 +11,13 @@
#include "bas_printf.h"
#include <stddef.h>
#define DBG_FECBD
#ifdef DBG_FECBD
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_FECBD */
/*
* This implements a simple static buffer descriptor
* ring for each channel and each direction
@@ -73,7 +80,7 @@ void fecbd_init(uint8_t ch)
nbuf = nbuf_alloc();
if (nbuf == NULL)
{
xprintf("%s: could not allocate network buffer\r\n", __FUNCTION__);
dbg("%s: could not allocate network buffer\r\n", __FUNCTION__);
return;
}

6
BaS_gcc/net/ip.c
View File

@@ -13,7 +13,7 @@
#define IP_DEBUG
#if defined(IP_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
@@ -168,7 +168,7 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
route = ip_resolve_route(nif, dest);
if (route == NULL)
{
dbg("Unable to locate %d.%d.%d.%d\n",
dbg("%s: Unable to locate %d.%d.%d.%d\r\n", __FUNCTION__,
dest[0], dest[1], dest[2], dest[3]);
return 0;
}
@@ -178,7 +178,7 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
route = bc;
dbg("%s: route = broadcast\r\n", __FUNCTION__);
dbg("%s: nif = %p\r\n", __FUNCTION__, nif);
dbg("%s: nif->send = %p\n\t", __FUNCTION__, nif->send);
dbg("%s: nif->send = %p\r\n", __FUNCTION__, nif->send);
}
return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);

26
BaS_gcc/net/nbuf.c
View File

@@ -10,6 +10,14 @@
#include "exceptions.h"
#include "bas_types.h"
#include "bas_printf.h"
#define DBG_NBUF
#if defined(DBG_NBUF)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_NBUF */
/*
* Queues used for network buffer storage
*/
@@ -40,9 +48,7 @@ int nbuf_init(void)
queue_init(&nbuf_queue[i]);
}
#ifdef DEBUG_PRINT
printf("Creating %d net buffers of %d bytes\r\n",NBUF_MAX,NBUF_SZ);
#endif
dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);
for (i = 0; i < NBUF_MAX; ++i)
{
@@ -70,7 +76,7 @@ int nbuf_init(void)
queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
}
xprintf("NBUF allocation complete\r\n");
dbg("NBUF allocation complete\r\n");
return 0;
}
@@ -184,7 +190,7 @@ void nbuf_reset(void)
*/
void nbuf_debug_dump(void)
{
#ifdef DEBUG
#ifdef DBG_NBUF
NBUF *nbuf;
int i, j, level;
@@ -192,14 +198,14 @@ void nbuf_debug_dump(void)
for (i = 0; i < NBUF_MAXQ; ++i)
{
printf("\n\nQueue #%d\n\n",i);
printf("\tBuffer Location\tOffset\tLength\n");
printf("--------------------------------------\n");
dbg("\n\nQueue #%d\n\n", i);
dbg("\tBuffer Location\tOffset\tLength\n");
dbg("--------------------------------------\n");
j = 0;
nbuf = (NBUF *)queue_peek(&nbuf_queue[i]);
while (nbuf != NULL)
{
printf("%d\t 0x%08x\t0x%04x\t0x%04x\n",j++,nbuf->data,
dbg("%d\t 0x%08x\t0x%04x\t0x%04x\n",j++,nbuf->data,
nbuf->offset,
nbuf->length);
nbuf = (NBUF *)nbuf->node.next;
@@ -207,5 +213,5 @@ void nbuf_debug_dump(void)
}
set_ipl(level);
#endif
#endif DBG_NBUF
}

10
BaS_gcc/pci/pci.c
View File

@@ -40,11 +40,11 @@
#define dbg(format, arg...) do { ; } while (0)
#endif /* DEBUG_PCI */
#if MACHINE_FIREBEE
#define pci_config_wait() wait(40000); /* FireBee USB not properly detected otherwise !?? */
#elif MACHINE_M5484LITE
//#if MACHINE_FIREBEE
//#define pci_config_wait() wait(40000); /* FireBee USB not properly detected otherwise !?? */
//#elif MACHINE_M5484LITE
#define pci_config_wait() do { __asm__ __volatile("tpf" ::: "memory"); } while (0)
#endif
//#endif
/*
* PCI device class descriptions displayed during PCI bus scan
@@ -924,6 +924,7 @@ void init_pci(void)
init_xlbus_arbiter();
MCF_PCI_PCIGSCR = 1; /* reset PCI */
wait(400000); /* give devices a chance to come up */
/*
* setup the PCI arbiter
@@ -1001,6 +1002,7 @@ void init_pci(void)
MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
do {;} while (MCF_PCI_PCIGSCR & MCF_PCI_PCIGSCR_PR); /* wait until reset finished */
xprintf("finished\r\n");
wait(400000); /* give devices a chance to come up */
/* initialize/clear resource descriptor table */
memset(&resource_descriptors, 0, NUM_CARDS * NUM_RESOURCES * sizeof(struct pci_rd));

15
BaS_gcc/sys/BaS.c
View File

@@ -262,9 +262,10 @@ void network_init(void)
handler = fec0_interrupt_handler;
vector = 103;
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL, (void *) &nif1))
{
dbg("%s: unable to register handler\r\n", __FUNCTION__);
dbg("%s: unable to register handler for vector %d\r\n", __FUNCTION__, vector);
return;
}
@@ -276,15 +277,16 @@ void network_init(void)
if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL,NULL))
{
xprintf("Error: Unable to register handler\n");
dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
return;
}
#ifdef _NOT_USED_
nif_init(&nif1);
nif1.mtu = ETH_MTU;
nif1.send = fec0_send;
fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
// fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
memcpy(nif1.hwa, mac, 6);
memcpy(nif1.broadcast, bc, 6);
@@ -293,10 +295,11 @@ void network_init(void)
ip_init(&ip_info, myip, gateway, netmask);
nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
#endif
dma_irq_enable(6, 6);
//set_ipl(0);
dma_irq_enable(6, 0);
//bootp_request(&nif1, 0);
// bootp_request(&nif1, 0);
}
void BaS(void)

11
BaS_gcc/sys/driver_mem.c
View File

@@ -24,14 +24,7 @@
#include "m5484l.h"
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#undef DRIVER_MEM_DEBUG
//#undef DRIVER_MEM_DEBUG
#ifdef DRIVER_MEM_DEBUG
#define dbg(fmt, args...) xprintf(fmt, ##args)
@@ -114,7 +107,7 @@ static MD *ffit(long amount, MPB *mp)
}
maxval = 0;
maxflg = ((amount == -1) ? TRUE : FALSE) ;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{

5
BaS_gcc/sys/exceptions.S
View File

@@ -306,7 +306,7 @@ init_vec_loop:
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
//move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
move.l (sp)+,a2 // Restore registers
@@ -994,7 +994,8 @@ _lowlevel_isr_handler:
jsr _isr_execute_handler
lea 4(sp),sp
cmp.l #1,d0
beq handled
//beq handled // this is probably not a too bright idea for hw interrupts not known to TOS
bra handled
nothandled:
movem.l (sp),d0-d1/a0-a1
unlk a6

37
BaS_gcc/sys/interrupts.c
View File

@@ -36,7 +36,7 @@ extern void (*rt_vbr[])(void);
#define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
@@ -57,7 +57,7 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
if (source < 1 || source > 63)
{
xprintf("%s: interrupt source %d not defined\r\n", __FUNCTION__, source);
dbg("%s: interrupt source %d not defined\r\n", __FUNCTION__, source);
return -1;
}
@@ -68,7 +68,7 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
{
if (ICR[i] == lp)
{
xprintf("%s: level %d and priority %d already used for interrupt source %d!\r\n", __FUNCTION__,
dbg("%s: level %d and priority %d already used for interrupt source %d!\r\n", __FUNCTION__,
level, priority, i);
return -1;
}
@@ -158,10 +158,12 @@ int isr_register_handler(int type, int vector,
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
return true;
}
}
dbg("%s: no available slots\n\t", __FUNCTION__);
dbg("%s: no available slots to register handler for vector %d\n\r", __FUNCTION__, vector);
return false; /* no available slots */
}
@@ -183,8 +185,11 @@ void isr_remove_handler(int type, int (*handler)(void *, void *))
isrtab[index].handler = 0;
isrtab[index].hdev = 0;
isrtab[index].harg = 0;
return;
}
}
dbg("%s: no such handler registered (type=%d, handler=%p\r\n", __FUNCTION__, type, handler);
}
@@ -205,32 +210,14 @@ bool isr_execute_handler(int vector)
if ((isrtab[index].vector == vector) &&
(isrtab[index].type == ISR_DBUG_ISR))
{
xprintf("calling BaS isr handler at %p\r\n", isrtab[index].handler);
retval = true;
if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
{
retval = true;
break;
return retval;
}
}
}
/*
* Try to locate a user-registered Interrupt Service Routine handler.
*/
for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
{
if ((isrtab[index].vector == vector) &&
(isrtab[index].type == ISR_USER_ISR))
{
xprintf("calling USR isr handler at %p\r\n", isrtab[index].handler);
if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
{
retval = true;
break;
}
}
}
dbg("%s: no BaS isr handler for vector %d found\r\n", __FUNCTION__, vector);
return retval;
}

2
BaS_gcc/sys/mmu.c
View File

@@ -62,7 +62,7 @@
#define DEBUG_MMU
#ifdef DEBUG_MMU
#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
#else
#define dbg_mmu(format, arg...) do {;} while (0)
#endif /* DEBUG_MMU */