USB controller detected on FireBee - needs a long wait time for config access there...
This commit is contained in:
@@ -1,7 +1,7 @@
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#set disassemble-next-line on
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#set disassemble-next-line on
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define tr
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define tr
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# target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
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# target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
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target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
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target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
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monitor bdm-reset
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monitor bdm-reset
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end
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end
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define tbtr
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define tbtr
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@@ -52,4 +52,4 @@ load -v m5484lite/ram.elf
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execute
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execute
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# wait is _needed_ here if using the P&E BDM interface. Otherwise
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# wait is _needed_ here if using the P&E BDM interface. Otherwise
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# the Coldfire resets after some time!
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# the Coldfire resets after some time!
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#wait
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wait
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@@ -270,7 +270,7 @@ static int ehci_reset(void)
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uint32_t *reg_ptr;
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uint32_t *reg_ptr;
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int ret = 0;
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int ret = 0;
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if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC)
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if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC)
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&& (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2))
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&& (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2))
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{
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{
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debug("ehci_reset set 48MHz clock\r\n");
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debug("ehci_reset set 48MHz clock\r\n");
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pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
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pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
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@@ -203,9 +203,10 @@ _mmu_init:
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move.l d1,MCF_MMU_MMUDR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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#elif MACHINE_M5484LITE
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#endif
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//
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//
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// Instead, we lock PCI address space. Uncached, precise. For now, only for the M5484LITE
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// We lock PCI address space. Uncached, precise.
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//
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//
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move.l #0x80000000|std_mmutr,d0
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move.l #0x80000000|std_mmutr,d0
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move.l #0x80000000|nocache_precise_mmudr|MCF_MMU_MMUDR_LK,d1
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move.l #0x80000000|nocache_precise_mmudr|MCF_MMU_MMUDR_LK,d1
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@@ -213,7 +214,6 @@ _mmu_init:
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move.l d1,MCF_MMU_MMUDR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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#endif /* MACHINE_FIREBEE */
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// maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address
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// maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0
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@@ -32,6 +32,8 @@
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#include "util.h"
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#include "util.h"
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#include "wait.h"
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#include "wait.h"
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#define pci_config_wait() wait(10000); /* FireBee USB not properly detected otherwise */
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/*
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/*
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* PCI device class descriptions displayed during PCI bus scan
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* PCI device class descriptions displayed during PCI bus scan
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*/
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*/
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@@ -122,12 +124,16 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
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MCF_PCI_PCICAR_DEVNUM(device) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_DEVNUM(device) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset / 4);
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MCF_PCI_PCICAR_DWORD(offset / 4);
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pci_config_wait();
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value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
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value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
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/* finish PCI configuration access special cycle (allow regular PCI accesses) */
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/* finish PCI configuration access special cycle (allow regular PCI accesses) */
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MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
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MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
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pci_config_wait();
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return value;
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return value;
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}
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}
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@@ -165,10 +171,15 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_FUNCNUM(function) | /* function number */
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MCF_PCI_PCICAR_DWORD(offset / 4);
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MCF_PCI_PCICAR_DWORD(offset / 4);
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pci_config_wait();
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* (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */
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* (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */
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pci_config_wait();
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/* finish configuration space access cycle */
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/* finish configuration space access cycle */
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MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
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MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
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pci_config_wait();
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return PCI_SUCCESSFUL;
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return PCI_SUCCESSFUL;
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}
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}
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@@ -202,9 +213,9 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
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uint16_t n = 0;
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uint16_t n = 0;
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int32_t handle;
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int32_t handle;
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for (bus = 0; bus < 255; bus++)
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for (bus = 0; bus < 2; bus++)
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{
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{
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for (device = 10; device < 32; device++)
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for (device = 10; device < 31; device++)
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{
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{
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uint32_t value;
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uint32_t value;
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uint8_t htr;
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uint8_t htr;
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@@ -402,20 +413,21 @@ void pci_scan(void)
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int16_t index = 0;
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int16_t index = 0;
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xprintf("\r\nPCI bus scan...\r\n\r\n");
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xprintf("\r\nPCI bus scan...\r\n\r\n");
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xprintf(" Bus| Dev|Func|Vndr|D-ID|\r\n");
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xprintf(" Bus| Dev|Func|Vndr|D-ID|Hndl|\r\n");
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xprintf("----+----+----+----+----|\r\n");
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xprintf("----+----+----+----+----+----+\r\n");
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handle = pci_find_device(0x0, 0xFFFF, index);
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handle = pci_find_device(0x0, 0xFFFF, index);
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while (handle != PCI_DEVICE_NOT_FOUND)
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while (handle > 0)
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{
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{
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uint32_t value;
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uint32_t value;
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value = swpl(pci_read_config_longword(handle, PCIIDR));
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value = pci_read_config_longword(handle, PCIIDR);
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xprintf(" %02x | %02x | %02x |%04x|%04x| %s (0x%02x)\r\n",
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xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x)\r\n",
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PCI_BUS_FROM_HANDLE(handle),
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PCI_BUS_FROM_HANDLE(handle),
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PCI_DEVICE_FROM_HANDLE(handle),
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PCI_DEVICE_FROM_HANDLE(handle),
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PCI_FUNCTION_FROM_HANDLE(handle),
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PCI_FUNCTION_FROM_HANDLE(handle),
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PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
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PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
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handle,
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device_class(pci_read_config_byte(handle, PCICCR)),
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device_class(pci_read_config_byte(handle, PCICCR)),
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pci_read_config_byte(handle, PCICCR));
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pci_read_config_byte(handle, PCICCR));
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@@ -477,6 +489,9 @@ void init_pci(void)
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xprintf("initializing PCI bridge:");
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xprintf("initializing PCI bridge:");
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init_eport();
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init_xlbus_arbiter();
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI
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+ MCF_PCIARB_PACR_EXTMPRI(0x1F)
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+ MCF_PCIARB_PACR_EXTMPRI(0x1F)
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+ MCF_PCIARB_PACR_INTMINTEN
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+ MCF_PCIARB_PACR_INTMINTEN
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@@ -537,7 +552,7 @@ void init_pci(void)
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/* initialize handles array */
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/* initialize handles array */
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memset(handles, 0, NUM_CARDS * sizeof(uint16_t));
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memset(handles, 0, NUM_CARDS * sizeof(uint16_t));
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#if MACHINE_FIREBEE
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#if _NOT_USED_
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/*
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/*
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* experimental: leave "old" USB initialization in place for the FireBee USB controller
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* experimental: leave "old" USB initialization in place for the FireBee USB controller
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* which seems to be found on second access only with the new PCI scan routines
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* which seems to be found on second access only with the new PCI scan routines
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@@ -568,7 +583,7 @@ void init_pci(void)
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MCF_PCI_PCICAR_FUNCNUM(0) +
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MCF_PCI_PCICAR_FUNCNUM(0) +
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MCF_PCI_PCICAR_DWORD(57);
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MCF_PCI_PCICAR_DWORD(57);
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}
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}
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#endif /* MACHINE_FIREBEE */
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#endif /* _NOT_USED_ */
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/*
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/*
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* do normal initialization
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* do normal initialization
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@@ -517,7 +517,7 @@ void init_usb(void)
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do
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do
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{
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{
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handle = pci_find_device(0x0000, 0xffffL, index++);
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handle = pci_find_device(0x0000, 0xffff, index++);
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if (handle > 0)
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if (handle > 0)
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{
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{
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uint32_t id = 0;
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uint32_t id = 0;
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@@ -553,7 +553,7 @@ void init_usb(void)
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board = ohci_usb_pci_table;
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board = ohci_usb_pci_table;
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while (board->vendor)
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while (board->vendor)
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{
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{
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if ((board->vendor == (id & 0xffff)) && board->device == PCI_DEVICE_ID(id))
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if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
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{
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{
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if (usb_init(handle, board) >= 0)
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if (usb_init(handle, board) >= 0)
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usb_found++;
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usb_found++;
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@@ -1030,8 +1030,6 @@ void initialize_hardware(void)
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dvi_on();
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dvi_on();
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#endif /* MACHINE_FIREBEE */
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#endif /* MACHINE_FIREBEE */
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init_pci();
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init_pci();
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init_eport();
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init_xlbus_arbiter();
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/* moved the following line (temporarily) to BaS (after MMU init) to be able to catch adressing errors on USB init */
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/* moved the following line (temporarily) to BaS (after MMU init) to be able to catch adressing errors on USB init */
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//init_usb();
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//init_usb();
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#if MACHINE_FIREBEE
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#if MACHINE_FIREBEE
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@@ -160,11 +160,11 @@ int usb_init(int32_t handle, const struct pci_device_id *ent)
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xprintf("sorry, no uhci driver available\r\n");
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xprintf("sorry, no uhci driver available\r\n");
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break;
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break;
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case PCI_CLASS_SERIAL_USB_OHCI:
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case PCI_CLASS_SERIAL_USB_OHCI:
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xprintf("initialize ohci interface, ");
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xprintf("initialize ohci interface\r\n");
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res = ohci_usb_lowlevel_init(handle, ent, &priv);
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res = ohci_usb_lowlevel_init(handle, ent, &priv);
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break;
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break;
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case PCI_CLASS_SERIAL_USB_EHCI:
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case PCI_CLASS_SERIAL_USB_EHCI:
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xprintf("initialize ehci interface, ");
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xprintf("initialize ehci interface\r\n");
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res = ehci_usb_lowlevel_init(handle, ent, &priv);
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res = ehci_usb_lowlevel_init(handle, ent, &priv);
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break;
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break;
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default: res = -1; break;
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default: res = -1; break;
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