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finally fixed multiple drivers problem

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This commit is contained in:
Markus Fröschle
2016-07-28 11:48:10 +00:00
parent 69d3f17a8b
commit 3cddba74a6
9 changed files with 760 additions and 907 deletions
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100
Video/BLITTER/BLITTER.vhd
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@@ -1,73 +1,47 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blitter is
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
port
(
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic;
FB_ALE : IN std_logic;
nFB_WR : IN std_logic;
nFB_OE : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0);
BLITTER_ON : IN std_logic;
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
DDRCLK0 : IN std_logic;
BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0);
BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0);
SR_BLITTER_DACK : IN std_logic;
BLITTER_RUN : OUT std_logic;
BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0);
BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0);
BLITTER_SIG : OUT std_logic;
BLITTER_WR : OUT std_logic;
blitter_ta : OUT std_logic;
fb_ad_in : in std_logic_vector(31 DOWNTO 0);
nRSTO : in std_logic;
MAIN_CLK : in std_logic;
FB_ALE : in std_logic;
nFB_WR : in std_logic;
nFB_OE : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
BLITTER_ON : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
nFB_CS1 : in std_logic;
nFB_CS2 : in std_logic;
nFB_CS3 : in std_logic;
DDRCLK0 : in std_logic;
BLITTER_DIN : in std_logic_vector(127 downto 0);
BLITTER_DACK : in std_logic_vector(4 downto 0);
SR_BLITTER_DACK : in std_logic;
blitter_run : out std_logic;
blitter_dout : out std_logic_vector(127 downto 0);
blitter_adr : out std_logic_vector(31 downto 0);
blitter_sig : out std_logic;
blitter_wr : out std_logic;
blitter_ta : out std_logic;
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
end BLITTER;
ARCHITECTURE rtl OF blitter IS
architecture rtl of blitter is
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
begin
blitter_run <= '0';
blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
blitter_adr <= x"76543210";
blitter_sig <= '0';
blitter_wr <= '0';
blitter_ta <= '0';
END rtl;
fb_ad_out <= (others => 'Z');
end rtl;